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-rw-r--r--libcpu/mips/loongson_1c/cache.c194
-rw-r--r--libcpu/mips/loongson_1c/cache.h48
-rw-r--r--libcpu/mips/loongson_1c/cpuport.c144
-rw-r--r--libcpu/mips/loongson_1c/exception.c42
-rw-r--r--libcpu/mips/loongson_1c/mipscfg.c60
5 files changed, 244 insertions, 244 deletions
diff --git a/libcpu/mips/loongson_1c/cache.c b/libcpu/mips/loongson_1c/cache.c
index bf97db9b4e..c755c0e4e8 100644
--- a/libcpu/mips/loongson_1c/cache.c
+++ b/libcpu/mips/loongson_1c/cache.c
@@ -13,12 +13,12 @@
* 2011-08-08 lgnq modified for LS1B
* 2015-07-08 chinesebear modified for loongson 1c
*/
-
+
#include <rtthread.h>
#include "../common/mipsregs.h"
-#define K0BASE 0x80000000
-#define PRID_LS1C 0x4220
+#define K0BASE 0x80000000
+#define PRID_LS1C 0x4220
extern void Clear_TagLo (void);
extern void Invalidate_Icache_Ls1c(unsigned int);
@@ -27,21 +27,21 @@ extern void Invalidate_Dcache_Fill_Ls1c(unsigned int);
extern void Writeback_Invalidate_Dcache(unsigned int);
extern void enable_cpu_cache(void);
-typedef struct cacheinfo_t
+typedef struct cacheinfo_t
{
- unsigned int icache_size;
- unsigned int dcache_size;
- unsigned int icacheline_size;
- unsigned int dcacheline_size;
+ unsigned int icache_size;
+ unsigned int dcache_size;
+ unsigned int icacheline_size;
+ unsigned int dcacheline_size;
} cacheinfo_t ;
-typedef struct cacheop_t
+typedef struct cacheop_t
{
- void (*Clear_TagLo) (void);
- void (*Invalidate_Icache) (unsigned int);
- void (*Invalidate_Dcache_Fill) (unsigned int);
- void (*Invalidate_Dcache_ClearTag) (unsigned int);
- void (*Init_Cache)(void);
+ void (*Clear_TagLo) (void);
+ void (*Invalidate_Icache) (unsigned int);
+ void (*Invalidate_Dcache_Fill) (unsigned int);
+ void (*Invalidate_Dcache_ClearTag) (unsigned int);
+ void (*Init_Cache)(void);
} cacheop_t ;
static cacheop_t cacheop, *pcacheop;
@@ -54,24 +54,24 @@ int identify_cpu(void)
pcacheop = &cacheop;
pcacheinfo = &cacheinfo;
- rt_kprintf("CPU configure: 0x%08x\n", read_c0_config());
+ rt_kprintf("CPU configure: 0x%08x\n", read_c0_config());
cpu_id = read_c0_prid();
switch (cpu_id)
- {
- case PRID_LS1C:
- rt_kprintf("CPU:Loongson 1C\n");
- pcacheop->Clear_TagLo = Clear_TagLo;
- pcacheop->Invalidate_Icache = Invalidate_Icache_Ls1c;
- pcacheop->Invalidate_Dcache_Fill = Invalidate_Dcache_Fill_Ls1c;
- pcacheop->Invalidate_Dcache_ClearTag = Invalidate_Dcache_ClearTag_Ls1c;
- break;
- default:
- rt_kprintf("Unknown CPU type, system halted!\n");
- while (1)
- {
- ;
- }
- break;
+ {
+ case PRID_LS1C:
+ rt_kprintf("CPU:Loongson 1C\n");
+ pcacheop->Clear_TagLo = Clear_TagLo;
+ pcacheop->Invalidate_Icache = Invalidate_Icache_Ls1c;
+ pcacheop->Invalidate_Dcache_Fill = Invalidate_Dcache_Fill_Ls1c;
+ pcacheop->Invalidate_Dcache_ClearTag = Invalidate_Dcache_ClearTag_Ls1c;
+ break;
+ default:
+ rt_kprintf("Unknown CPU type, system halted!\n");
+ while (1)
+ {
+ ;
+ }
+ break;
}
return 0;
@@ -90,7 +90,7 @@ void probe_cache(void)
icache_sets = 64 << ((config1 >> 22) & 7);
icache_ways = 1 + ((config1 >> 16) & 7);
icache_size = icache_sets * icache_ways * icache_line_size;
-
+
if ((dcache_line_size = ((config1 >> 10) & 7)))
dcache_line_size = 2 << dcache_line_size;
else
@@ -98,7 +98,7 @@ void probe_cache(void)
dcache_sets = 64 << ((config1 >> 13) & 7);
dcache_ways = 1 + ((config1 >> 7) & 7);
dcache_size = dcache_sets * dcache_ways * dcache_line_size;
-
+
rt_kprintf("DCache %2dkb, linesize %d bytes.\n", dcache_size >> 10, dcache_line_size);
rt_kprintf("ICache %2dkb, linesize %d bytes.\n", icache_size >> 10, icache_line_size);
@@ -112,122 +112,122 @@ void probe_cache(void)
void invalidate_writeback_dcache_all(void)
{
- unsigned int start = K0BASE;
- unsigned int end = (start + pcacheinfo->dcache_size);
+ unsigned int start = K0BASE;
+ unsigned int end = (start + pcacheinfo->dcache_size);
- while (start < end)
- {
- Writeback_Invalidate_Dcache(start); //hit writeback invalidate
- start += pcacheinfo->dcacheline_size;
- }
+ while (start < end)
+ {
+ Writeback_Invalidate_Dcache(start); //hit writeback invalidate
+ start += pcacheinfo->dcacheline_size;
+ }
}
void invalidate_writeback_dcache(unsigned long addr, int size)
{
- unsigned long start, end;
-
- start = (addr +pcacheinfo->dcacheline_size -1) & (- pcacheinfo->dcacheline_size);
- end = (end + size + pcacheinfo->dcacheline_size -1) & ( -pcacheinfo->dcacheline_size);
-
- while (start <end)
- {
- Writeback_Invalidate_Dcache(start);
- start += pcacheinfo->dcacheline_size;
- }
+ unsigned long start, end;
+
+ start = (addr +pcacheinfo->dcacheline_size -1) & (- pcacheinfo->dcacheline_size);
+ end = (end + size + pcacheinfo->dcacheline_size -1) & ( -pcacheinfo->dcacheline_size);
+
+ while (start <end)
+ {
+ Writeback_Invalidate_Dcache(start);
+ start += pcacheinfo->dcacheline_size;
+ }
}
void invalidate_icache_all(void)
{
- unsigned int start = K0BASE;
- unsigned int end = (start + pcacheinfo->icache_size);
+ unsigned int start = K0BASE;
+ unsigned int end = (start + pcacheinfo->icache_size);
- while (start < end)
- {
- pcacheop->Invalidate_Icache(start);
- start += pcacheinfo->icacheline_size;
- }
+ while (start < end)
+ {
+ pcacheop->Invalidate_Icache(start);
+ start += pcacheinfo->icacheline_size;
+ }
}
void invalidate_dcache_all(void)
-{
- unsigned int start = K0BASE;
- unsigned int end = (start + pcacheinfo->dcache_size);
- while (start <end)
- {
- Invalidate_Dcache_Fill_Ls1c(start);
- start += pcacheinfo->icacheline_size;
- }
+{
+ unsigned int start = K0BASE;
+ unsigned int end = (start + pcacheinfo->dcache_size);
+ while (start <end)
+ {
+ Invalidate_Dcache_Fill_Ls1c(start);
+ start += pcacheinfo->icacheline_size;
+ }
}
//with cache disabled
void init_dcache(void)
{
- unsigned int start = K0BASE;
- unsigned int end = (start + pcacheinfo->dcache_size);
+ unsigned int start = K0BASE;
+ unsigned int end = (start + pcacheinfo->dcache_size);
- while (start < end)
- {
- pcacheop->Invalidate_Dcache_ClearTag(start);
- start += pcacheinfo->dcacheline_size;
- }
+ while (start < end)
+ {
+ pcacheop->Invalidate_Dcache_ClearTag(start);
+ start += pcacheinfo->dcacheline_size;
+ }
}
void rt_hw_cache_init(void)
{
unsigned int start, end;
-
- /* 1. identify cpu and probe cache */
- identify_cpu();
- probe_cache();
- start = K0BASE;
- end = (start + pcacheinfo->icache_size);
+ /* 1. identify cpu and probe cache */
+ identify_cpu();
+ probe_cache();
+
+ start = K0BASE;
+ end = (start + pcacheinfo->icache_size);
/*
- * 2. clear CP0 taglo/taghi register;
+ * 2. clear CP0 taglo/taghi register;
*/
pcacheop->Clear_TagLo();
- /*
- * 3. invalidate instruction cache;
+ /*
+ * 3. invalidate instruction cache;
*/
- while (start < end)
+ while (start < end)
{
- pcacheop->Invalidate_Icache(start); //index invalidate icache
- start += pcacheinfo->icacheline_size;
+ pcacheop->Invalidate_Icache(start); //index invalidate icache
+ start += pcacheinfo->icacheline_size;
}
/*
- * 4. invalidate data cache;
+ * 4. invalidate data cache;
*/
start = K0BASE;
end = (start + pcacheinfo->dcache_size);
- while(start < end)
+ while(start < end)
{
- pcacheop->Invalidate_Dcache_ClearTag(start);
- start += pcacheinfo->dcacheline_size;
+ pcacheop->Invalidate_Dcache_ClearTag(start);
+ start += pcacheinfo->dcacheline_size;
}
start = K0BASE;
- while(start < end)
+ while(start < end)
{
- pcacheop->Invalidate_Dcache_Fill(start); //index invalidate dcache
- start += pcacheinfo->dcacheline_size;
+ pcacheop->Invalidate_Dcache_Fill(start); //index invalidate dcache
+ start += pcacheinfo->dcacheline_size;
}
start = K0BASE;
- while(start < end)
+ while(start < end)
{
- pcacheop->Invalidate_Dcache_ClearTag(start);
- start += pcacheinfo->dcacheline_size;
+ pcacheop->Invalidate_Dcache_ClearTag(start);
+ start += pcacheinfo->dcacheline_size;
}
- /* enable cache */
- enable_cpu_cache();
- rt_kprintf("enable cpu cache done\n");
+ /* enable cache */
+ enable_cpu_cache();
+ rt_kprintf("enable cpu cache done\n");
- return ;
+ return ;
}
diff --git a/libcpu/mips/loongson_1c/cache.h b/libcpu/mips/loongson_1c/cache.h
index b5c2d4501e..8ca015ef4f 100644
--- a/libcpu/mips/loongson_1c/cache.h
+++ b/libcpu/mips/loongson_1c/cache.h
@@ -12,8 +12,8 @@
* 2010-07-09 Bernard first version
* 2011-08-08 lgnq modified for LS1B
*/
-#ifndef __CACHE_H__
-#define __CACHE_H__
+#ifndef __CACHE_H__
+#define __CACHE_H__
/*
* Cache Operations
@@ -22,31 +22,31 @@
#define Index_Writeback_Inv_D 0x01
#define Index_Invalidate_SI 0x02
#define Index_Writeback_Inv_SD 0x03
-#define Index_Load_Tag_I 0x04
-#define Index_Load_Tag_D 0x05
-#define Index_Load_Tag_SI 0x06
-#define Index_Load_Tag_SD 0x07
-#define Index_Store_Tag_I 0x08
-#define Index_Store_Tag_D 0x09
-#define Index_Store_Tag_SI 0x0A
-#define Index_Store_Tag_SD 0x0B
-#define Create_Dirty_Excl_D 0x0d
-#define Create_Dirty_Excl_SD 0x0f
-#define Hit_Invalidate_I 0x10
-#define Hit_Invalidate_D 0x11
-#define Hit_Invalidate_SI 0x12
-#define Hit_Invalidate_SD 0x13
-#define Fill 0x14
-#define Hit_Writeback_Inv_D 0x15
+#define Index_Load_Tag_I 0x04
+#define Index_Load_Tag_D 0x05
+#define Index_Load_Tag_SI 0x06
+#define Index_Load_Tag_SD 0x07
+#define Index_Store_Tag_I 0x08
+#define Index_Store_Tag_D 0x09
+#define Index_Store_Tag_SI 0x0A
+#define Index_Store_Tag_SD 0x0B
+#define Create_Dirty_Excl_D 0x0d
+#define Create_Dirty_Excl_SD 0x0f
+#define Hit_Invalidate_I 0x10
+#define Hit_Invalidate_D 0x11
+#define Hit_Invalidate_SI 0x12
+#define Hit_Invalidate_SD 0x13
+#define Fill 0x14
+#define Hit_Writeback_Inv_D 0x15
/* 0x16 is unused */
-#define Hit_Writeback_Inv_SD 0x17
-#define Hit_Writeback_I 0x18
-#define Hit_Writeback_D 0x19
+#define Hit_Writeback_Inv_SD 0x17
+#define Hit_Writeback_I 0x18
+#define Hit_Writeback_D 0x19
/* 0x1a is unused */
-#define Hit_Writeback_SD 0x1b
+#define Hit_Writeback_SD 0x1b
/* 0x1c is unused */
/* 0x1e is unused */
-#define Hit_Set_Virtual_SI 0x1e
-#define Hit_Set_Virtual_SD 0x1f
+#define Hit_Set_Virtual_SI 0x1e
+#define Hit_Set_Virtual_SD 0x1f
#endif
diff --git a/libcpu/mips/loongson_1c/cpuport.c b/libcpu/mips/loongson_1c/cpuport.c
index 03fdc2a514..147f4882bf 100644
--- a/libcpu/mips/loongson_1c/cpuport.c
+++ b/libcpu/mips/loongson_1c/cpuport.c
@@ -31,13 +31,13 @@ register rt_uint32_t $GP __asm__ ("$28");
*/
void rt_hw_cpu_reset(void)
{
- /* open the watch-dog */
- WDT_EN = 0x01; /* watch dog enable */
- WDT_TIMER = 0x01; /* watch dog will be timeout after 1 tick */
- WDT_SET = 0x01; /* watch dog start */
+ /* open the watch-dog */
+ WDT_EN = 0x01; /* watch dog enable */
+ WDT_TIMER = 0x01; /* watch dog will be timeout after 1 tick */
+ WDT_SET = 0x01; /* watch dog start */
- rt_kprintf("reboot system...\n");
- while (1);
+ rt_kprintf("reboot system...\n");
+ while (1);
}
/**
@@ -46,9 +46,9 @@ void rt_hw_cpu_reset(void)
*/
void rt_hw_cpu_shutdown(void)
{
- rt_kprintf("shutdown...\n");
+ rt_kprintf("shutdown...\n");
- while (1);
+ while (1);
}
extern rt_uint32_t cp0_get_cause(void);
@@ -68,73 +68,73 @@ extern rt_uint32_t cp0_get_lo(void);
*/
rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, rt_uint8_t *stack_addr, void *texit)
{
- rt_uint32_t *stk;
+ rt_uint32_t *stk;
static rt_uint32_t g_sr = 0;
- static rt_uint32_t g_gp = 0;
+ static rt_uint32_t g_gp = 0;
if (g_sr == 0)
{
- g_sr = cp0_get_status();
- g_sr &= 0xfffffffe;
- g_sr |= 0x8401;
+ g_sr = cp0_get_status();
+ g_sr &= 0xfffffffe;
+ g_sr |= 0x8401;
- g_gp = $GP;
+ g_gp = $GP;
}
/** Start at stack top */
stk = (rt_uint32_t *)stack_addr;
- *(stk) = (rt_uint32_t) tentry; /* pc: Entry Point */
- *(--stk) = (rt_uint32_t) 0xeeee; /* c0_cause */
- *(--stk) = (rt_uint32_t) 0xffff; /* c0_badvaddr */
- *(--stk) = (rt_uint32_t) cp0_get_lo(); /* lo */
- *(--stk) = (rt_uint32_t) cp0_get_hi(); /* hi */
- *(--stk) = (rt_uint32_t) g_sr; /* C0_SR: HW2 = En, IE = En */
- *(--stk) = (rt_uint32_t) texit; /* ra */
- *(--stk) = (rt_uint32_t) 0x0000001e; /* s8 */
- *(--stk) = (rt_uint32_t) stack_addr; /* sp */
- *(--stk) = (rt_uint32_t) g_gp; /* gp */
- *(--stk) = (rt_uint32_t) 0x0000001b; /* k1 */
- *(--stk) = (rt_uint32_t) 0x0000001a; /* k0 */
- *(--stk) = (rt_uint32_t) 0x00000019; /* t9 */
- *(--stk) = (rt_uint32_t) 0x00000018; /* t8 */
- *(--stk) = (rt_uint32_t) 0x00000017; /* s7 */
- *(--stk) = (rt_uint32_t) 0x00000016; /* s6 */
- *(--stk) = (rt_uint32_t) 0x00000015; /* s5 */
- *(--stk) = (rt_uint32_t) 0x00000014; /* s4 */
- *(--stk) = (rt_uint32_t) 0x00000013; /* s3 */
- *(--stk) = (rt_uint32_t) 0x00000012; /* s2 */
- *(--stk) = (rt_uint32_t) 0x00000011; /* s1 */
- *(--stk) = (rt_uint32_t) 0x00000010; /* s0 */
- *(--stk) = (rt_uint32_t) 0x0000000f; /* t7 */
- *(--stk) = (rt_uint32_t) 0x0000000e; /* t6 */
- *(--stk) = (rt_uint32_t) 0x0000000d; /* t5 */
- *(--stk) = (rt_uint32_t) 0x0000000c; /* t4 */
- *(--stk) = (rt_uint32_t) 0x0000000b; /* t3 */
- *(--stk) = (rt_uint32_t) 0x0000000a; /* t2 */
- *(--stk) = (rt_uint32_t) 0x00000009; /* t1 */
- *(--stk) = (rt_uint32_t) 0x00000008; /* t0 */
- *(--stk) = (rt_uint32_t) 0x00000007; /* a3 */
- *(--stk) = (rt_uint32_t) 0x00000006; /* a2 */
- *(--stk) = (rt_uint32_t) 0x00000005; /* a1 */
- *(--stk) = (rt_uint32_t) parameter; /* a0 */
- *(--stk) = (rt_uint32_t) 0x00000003; /* v1 */
- *(--stk) = (rt_uint32_t) 0x00000002; /* v0 */
- *(--stk) = (rt_uint32_t) 0x00000001; /* at */
- *(--stk) = (rt_uint32_t) 0x00000000; /* zero */
+ *(stk) = (rt_uint32_t) tentry; /* pc: Entry Point */
+ *(--stk) = (rt_uint32_t) 0xeeee; /* c0_cause */
+ *(--stk) = (rt_uint32_t) 0xffff; /* c0_badvaddr */
+ *(--stk) = (rt_uint32_t) cp0_get_lo(); /* lo */
+ *(--stk) = (rt_uint32_t) cp0_get_hi(); /* hi */
+ *(--stk) = (rt_uint32_t) g_sr; /* C0_SR: HW2 = En, IE = En */
+ *(--stk) = (rt_uint32_t) texit; /* ra */
+ *(--stk) = (rt_uint32_t) 0x0000001e; /* s8 */
+ *(--stk) = (rt_uint32_t) stack_addr; /* sp */
+ *(--stk) = (rt_uint32_t) g_gp; /* gp */
+ *(--stk) = (rt_uint32_t) 0x0000001b; /* k1 */
+ *(--stk) = (rt_uint32_t) 0x0000001a; /* k0 */
+ *(--stk) = (rt_uint32_t) 0x00000019; /* t9 */
+ *(--stk) = (rt_uint32_t) 0x00000018; /* t8 */
+ *(--stk) = (rt_uint32_t) 0x00000017; /* s7 */
+ *(--stk) = (rt_uint32_t) 0x00000016; /* s6 */
+ *(--stk) = (rt_uint32_t) 0x00000015; /* s5 */
+ *(--stk) = (rt_uint32_t) 0x00000014; /* s4 */
+ *(--stk) = (rt_uint32_t) 0x00000013; /* s3 */
+ *(--stk) = (rt_uint32_t) 0x00000012; /* s2 */
+ *(--stk) = (rt_uint32_t) 0x00000011; /* s1 */
+ *(--stk) = (rt_uint32_t) 0x00000010; /* s0 */
+ *(--stk) = (rt_uint32_t) 0x0000000f; /* t7 */
+ *(--stk) = (rt_uint32_t) 0x0000000e; /* t6 */
+ *(--stk) = (rt_uint32_t) 0x0000000d; /* t5 */
+ *(--stk) = (rt_uint32_t) 0x0000000c; /* t4 */
+ *(--stk) = (rt_uint32_t) 0x0000000b; /* t3 */
+ *(--stk) = (rt_uint32_t) 0x0000000a; /* t2 */
+ *(--stk) = (rt_uint32_t) 0x00000009; /* t1 */
+ *(--stk) = (rt_uint32_t) 0x00000008; /* t0 */
+ *(--stk) = (rt_uint32_t) 0x00000007; /* a3 */
+ *(--stk) = (rt_uint32_t) 0x00000006; /* a2 */
+ *(--stk) = (rt_uint32_t) 0x00000005; /* a1 */
+ *(--stk) = (rt_uint32_t) parameter; /* a0 */
+ *(--stk) = (rt_uint32_t) 0x00000003; /* v1 */
+ *(--stk) = (rt_uint32_t) 0x00000002; /* v0 */
+ *(--stk) = (rt_uint32_t) 0x00000001; /* at */
+ *(--stk) = (rt_uint32_t) 0x00000000; /* zero */
- /* return task's current stack address */
- return (rt_uint8_t *)stk;
+ /* return task's current stack address */
+ return (rt_uint8_t *)stk;
}
#define cache_op(op,addr) \
- __asm__ __volatile__( \
- " .set push \n" \
- " .set noreorder \n" \
- " .set mips3\n\t \n" \
- " cache %0, %1 \n" \
- " .set pop \n" \
- : \
- : "i" (op), "R" (*(unsigned char *)(addr)))
+ __asm__ __volatile__( \
+ " .set push \n" \
+ " .set noreorder \n" \
+ " .set mips3\n\t \n" \
+ " cache %0, %1 \n" \
+ " .set pop \n" \
+ : \
+ : "i" (op), "R" (*(unsigned char *)(addr)))
#if defined(CONFIG_CPU_LOONGSON2)
#define Hit_Invalidate_I 0x00
@@ -148,17 +148,17 @@ rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, rt_uint8_t *stack_ad
void flush_cache(unsigned long start_addr, unsigned long size)
{
- unsigned long lsize = CONFIG_SYS_CACHELINE_SIZE;
- unsigned long addr = start_addr & ~(lsize - 1);
- unsigned long aend = (start_addr + size - 1) & ~(lsize - 1);
+ unsigned long lsize = CONFIG_SYS_CACHELINE_SIZE;
+ unsigned long addr = start_addr & ~(lsize - 1);
+ unsigned long aend = (start_addr + size - 1) & ~(lsize - 1);
- while (1) {
- cache_op(Hit_Writeback_Inv_D, addr);
- cache_op(Hit_Invalidate_I, addr);
- if (addr == aend)
- break;
- addr += lsize;
- }
+ while (1) {
+ cache_op(Hit_Writeback_Inv_D, addr);
+ cache_op(Hit_Invalidate_I, addr);
+ if (addr == aend)
+ break;
+ addr += lsize;
+ }
}
diff --git a/libcpu/mips/loongson_1c/exception.c b/libcpu/mips/loongson_1c/exception.c
index 4a3745cbc5..dbcec42ab6 100644
--- a/libcpu/mips/loongson_1c/exception.c
+++ b/libcpu/mips/loongson_1c/exception.c
@@ -25,7 +25,7 @@
/**
* exception handle table
*/
-#define RT_EXCEPTION_MAX 8
+#define RT_EXCEPTION_MAX 8
exception_func_t sys_exception_handlers[RT_EXCEPTION_MAX];
/**
@@ -47,45 +47,45 @@ exception_func_t rt_set_except_vector(int n, exception_func_t func)
void tlb_refill_handler(void)
{
- rt_kprintf("tlb-miss happens, epc: 0x%08x\n", read_c0_epc());
- rt_hw_cpu_shutdown();
+ rt_kprintf("tlb-miss happens, epc: 0x%08x\n", read_c0_epc());
+ rt_hw_cpu_shutdown();
}
void cache_error_handler(void)
{
- rt_kprintf("cache exception happens, epc: 0x%08x\n", read_c0_epc());
- rt_hw_cpu_shutdown();
+ rt_kprintf("cache exception happens, epc: 0x%08x\n", read_c0_epc());
+ rt_hw_cpu_shutdown();
}
static void unhandled_exception_handle(pt_regs_t *regs)
{
- rt_kprintf("exception happens, epc: 0x%08x, cause: 0x%08x\n", regs->cp0_epc, read_c0_cause());
+ rt_kprintf("exception happens, epc: 0x%08x, cause: 0x%08x\n", regs->cp0_epc, read_c0_cause());
}
void install_default_execpt_handle(void)
{
- rt_int32_t i;
+ rt_int32_t i;
- for (i=0; i<RT_EXCEPTION_MAX; i++)
- sys_exception_handlers[i] = (exception_func_t)unhandled_exception_handle;
+ for (i=0; i<RT_EXCEPTION_MAX; i++)
+ sys_exception_handlers[i] = (exception_func_t)unhandled_exception_handle;
}
void exception_handler(pt_regs_t *regs)
{
- rt_uint32_t cause;
- rt_uint32_t index;
+ rt_uint32_t cause;
+ rt_uint32_t index;
- cause = (read_c0_cause() & read_c0_config());
- cause = (cause & 0xfc00) >> 8;
+ cause = (read_c0_cause() & read_c0_config());
+ cause = (cause & 0xfc00) >> 8;
- for (index = RT_EXCEPTION_MAX; index > 0; index --)
- {
- if (cause & (1 << index))
- {
- sys_exception_handlers[index](regs);
- cause &= ~(1 << index);
- }
- }
+ for (index = RT_EXCEPTION_MAX; index > 0; index --)
+ {
+ if (cause & (1 << index))
+ {
+ sys_exception_handlers[index](regs);
+ cause &= ~(1 << index);
+ }
+ }
}
/*@}*/
diff --git a/libcpu/mips/loongson_1c/mipscfg.c b/libcpu/mips/loongson_1c/mipscfg.c
index 10dd3fee9e..73e9efd965 100644
--- a/libcpu/mips/loongson_1c/mipscfg.c
+++ b/libcpu/mips/loongson_1c/mipscfg.c
@@ -17,18 +17,18 @@
mips32_core_cfg_t g_mips_core =
{
- 16, /* icache_line_size */
- 256, /* icache_lines_per_way */
- 4, /* icache_ways */
- 16, /* dcache_line_size */
- 256, /* dcache_lines_per_way */
- 4, /* dcache_ways */
- 16, /* max_tlb_entries */
+ 16, /* icache_line_size */
+ 256, /* icache_lines_per_way */
+ 4, /* icache_ways */
+ 16, /* dcache_line_size */
+ 256, /* dcache_lines_per_way */
+ 4, /* dcache_ways */
+ 16, /* max_tlb_entries */
};
static rt_uint16_t m_pow(rt_uint16_t b, rt_uint16_t n)
{
- rt_uint16_t rets = 1;
+ rt_uint16_t rets = 1;
while (n--)
rets *= b;
@@ -38,7 +38,7 @@ static rt_uint16_t m_pow(rt_uint16_t b, rt_uint16_t n)
static rt_uint16_t m_log2(rt_uint16_t b)
{
- rt_uint16_t rets = 0;
+ rt_uint16_t rets = 0;
while (b != 1)
{
@@ -54,29 +54,29 @@ static rt_uint16_t m_log2(rt_uint16_t b)
*/
void mips32_cfg_init(void)
{
- rt_uint16_t val;
- rt_uint32_t cp0_config1;
+ rt_uint16_t val;
+ rt_uint32_t cp0_config1;
- cp0_config1 = read_c0_config();
- if (cp0_config1 & 0x80000000)
- {
- cp0_config1 = read_c0_config1();
+ cp0_config1 = read_c0_config();
+ if (cp0_config1 & 0x80000000)
+ {
+ cp0_config1 = read_c0_config1();
- val = (cp0_config1 & (7<<22))>>22;
- g_mips_core.icache_lines_per_way = 64 * m_pow(2, val);
- val = (cp0_config1 & (7<<19))>>19;
- g_mips_core.icache_line_size = 2 * m_pow(2, val);
- val = (cp0_config1 & (7<<16))>>16;
- g_mips_core.icache_ways = val + 1;
+ val = (cp0_config1 & (7<<22))>>22;
+ g_mips_core.icache_lines_per_way = 64 * m_pow(2, val);
+ val = (cp0_config1 & (7<<19))>>19;
+ g_mips_core.icache_line_size = 2 * m_pow(2, val);
+ val = (cp0_config1 & (7<<16))>>16;
+ g_mips_core.icache_ways = val + 1;
- val = (cp0_config1 & (7<<13))>>13;
- g_mips_core.dcache_lines_per_way = 64 * m_pow(2, val);
- val = (cp0_config1 & (7<<10))>>10;
- g_mips_core.dcache_line_size = 2 * m_pow(2, val);
- val = (cp0_config1 & (7<<7))>>7;
- g_mips_core.dcache_ways = val + 1;
+ val = (cp0_config1 & (7<<13))>>13;
+ g_mips_core.dcache_lines_per_way = 64 * m_pow(2, val);
+ val = (cp0_config1 & (7<<10))>>10;
+ g_mips_core.dcache_line_size = 2 * m_pow(2, val);
+ val = (cp0_config1 & (7<<7))>>7;
+ g_mips_core.dcache_ways = val + 1;
- val = (cp0_config1 & (0x3F<<25))>>25;
- g_mips_core.max_tlb_entries = val + 1;
- }
+ val = (cp0_config1 & (0x3F<<25))>>25;
+ g_mips_core.max_tlb_entries = val + 1;
+ }
}
generated by cgit v1.3.1 (git 2.54.0) at 2026-10-24 05:44:05 +0000