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Increase RT_CPUS_NR from 4 to 8 in the K1 default configuration
and regenerate rtconfig.h.
Add the SpacemiT K1 entry and peripheral support matrix to the
BSP overview.
Verified eight-core boot and root filesystem mounting with the
RISC-V ticket spinlock fix.
Signed-off-by: GuEe-GUI <[email protected]>
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Sync the HPMicro BSPs with hpm_sdk v1.13.0 and add the HPM5100EVK
(HPM5151) board.
- add the hpm5100evk BSP (board/startup/applications/Kconfig/docs) and
register it in .github/ALL_BSP_COMPILE.json, bsp/README.md and the
HPMicro READMEs
- re-sync the 11 existing boards (board/startup/debug scripts/linker
scripts/applications) with hpm_sdk v1.13.0, keeping the RT-Thread
specific parts: clock_time based drv_timer, CXX wired into the scons
environment, SConscript outputs under build/, named Kconfig choices,
rt_hw_us_delay in board_delay_*, board local codec files
- sync the shared driver layer with hpm_sdk v1.13.0 (GPTMRv2/PTMR,
PUART, soft I2C/SPI and the remaining peripheral driver updates)
- select the hpm_sdk v1.13.0 online package (PKG_USING_HPM_SDK_V113)
- use -Og instead of -O0 for the debug builds and print floats with the
RT-Thread klibc implementation instead of newlib nano
- initialize the RT-Thread heap before the SDK console init: the SDK
console_init() calls setvbuf(), which allocates through the C library
malloc() and tripped RT_ASSERT() in rt_smem_alloc() on the boards
built with RT_USING_DEBUG
- keep only ram_rtt.ld/flash_rtt.ld per board, align the DLM origin to
4KB on hpm5300evk/hpm5301evklite (the unaligned origin made the
linker emit a file backed PT_LOAD for the RAM area, which broke
"program rtthread.elf"), and anchor the generated .bin at the flash
base address 0x80000000
- sync the hpm6750evk openocd debug scripts with the new style used by
the other boards (hpm_common.cfg/hpm_reset.cfg with arp_halt)
- keep the upstream synced board/startup/libraries trees of bsp/hpmicro out of the
changed-file cppcheck run (same policy as bsp/hpmicro/.clang-format-ignore): the
check runs without the hpm_sdk include paths, so it reports ATTR_PLACE_AT and the
linker script symbol arithmetic in c_startup() as errors
- give the hpmicro boards in the changed-file scons trigger list the RV32 toolchain
they need (RISC-V-GCC-RV32) and add the matching installation step to that
workflow: the entries used sourcery-arm, which only provides the ARM toolchain,
so those legs could not find riscv32-unknown-elf-gcc
- keep hpm5100evk's ram_rtt.ld identical to the hpm_sdk v1.13.0
reference: the .fast_ram sections belong in DLM there (the DLM has
enough headroom), and that also makes its RAM and flash layouts agree
- skip the dependency pre-check when cleaning (scons -c): it runs from
DoBuilding() unconditionally, so a clean request with packages/ not
fetched yet was aborted with exit code 1 instead of cleaning
- make the manual scons trigger workflow runnable: it aborted while still
downloading actions because actions/upload-artifact@v3 is deprecated,
and scons was not on PATH because ~/.env/env.sh was never sourced.
Install tools/requirements.txt and source the Env PATH script in the
build step, and use @main action versions, as bsp_buildings.yml does
- start the LED demo thread only when rt_thread_create() succeeded
Tested:
- 12 boards x {ram_debug, ram_release, flash_debug, flash_release}:
48/48 clean builds
- flash boot + msh on hpm5100evk, hpm5300evk, hpm5e00evk, hpm6200evk,
hpm6300evk, hpm6750evk, hpm6750evk2, hpm6750evkmini, hpm6800evk,
hpm6e00evk, hpm6p00evk (list device/timer, ps, free, reset, rt_kprintf
float formatting)
- re-ran .github/workflows/manual_trigger_scons_except_STM32_all.yml with
the matrix reduced to the three hpmicro rows: all three legs build and
scons --dist succeeds with no local workarounds
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with ci-attach
The N32H47x_48x and N32H49x series share drv_tim.c with N32H7xx, but only the
H7xx branch was ever implemented, so clock timer, LPTIM, PWM and pulse encoder
built to nothing on n32h487zgl7-evb and n32h497zgl7-evb. This adds those
branches and gives all three boards a ci-attach entry set that actually
compiles what the drivers claim to support.
Drivers
- drv_tim.c gains the H47x_48x/H49x clock-source and clock-enable branches,
the ATIM/GTIM/BTIM instance tables and n32_tim_clock_freq_get(), which
reads the real PCLK/HCLK/SYSCLK back from RCC rather than assuming one.
ATIMCLKSEL is inverted between the two families and is handled as such.
- drv_lptim.c derives its tick from the real LSI value instead of a
hard-coded one, unlocks the backup domain before touching RCC, latches
the prescaler, and returns -RT_EINVAL rather than clamping a bad rate.
- drv_pwm.c and drv_pulse_encoder.c are extended to the H47x_48x/H49x
instances; the H7xx encoder's update event is cleared through
TIM_EnableUpdateEvt() because that family has no TIM_ConfigUpdateEvt().
- config/{h47x_48x,h49x}/{tim,pwm,pulse_encoder,lptim}_config.h are new and
enumerate the instances each series has, for the existing drivers to read.
Kconfig
Each board defines the timer menus in its own board/Kconfig, so that a
board's peripheral options live with the board and the shared driver
Kconfig stays series-neutral; libraries/N32_Drivers/drivers/Kconfig is
byte-identical to upstream/master. All three copies enforce the mutual
exclusion drv_pulse_encoder.c documents (a timer instance enabled for both
clock timer and pulse encoder collides at link time on the shared ISR
symbol); N32H7xx's menus had none at all and are brought in line.
ci-attach
51 entries across the three boards (17/16/18). h487 carries three NAND
entries - peripheral.nand, peripheral.nand_16b and peripheral.nand_large -
and h497 and h760 carry one each. peripheral.nand_large exists because
drv_nand.c picks the row-address cycle count from pages_per_block *
block_count: 2 cycles up to 65536 pages, 3 up to 16777216, else 4. Every
other NAND entry takes the Kconfig default 64 * 1024 = 65536, which lands
exactly on the first boundary, so the >= 3 and >= 4 arms were compiled by
nothing at all - it takes a geometry past the 24-bit row width to reach the
top rung. The entry pins that geometry to arm them; it is not a claim about
the part on the board.
Fixes carried in the same series
- drv_nand.c emitted its third row-address byte under `== 3`, so a 4-cycle
part would set the count to 4 and then match no emitter, dropping the
high row-address bytes outright. The three guards are now >= 3 with the
>= 4 byte added. row_addr is uint32_t at all three sites.
- timer_ctrl() wrote the prescaler straight to a 16-bit PSC field.
TIM_ConfigPrescaler() neither masks nor validates, so any freq below
timer_clock/65537 was truncated and the timer ran at an unrelated rate
while timer->freq still recorded the requested one. That window is
reachable: both boards clock timers at 240 MHz, so the honest floor is
~3662 Hz while tim_config.h sets minfreq = 3000 and only [minfreq,
maxfreq] is checked - 3000 Hz lands in PSC as 14463, about 16.6 kHz.
Division by zero and any prescaler above 0xFFFF now return -RT_EINVAL.
The H7xx branch had the identical truncation, so the same two guards
are applied there too.
- n32_tim_enable_clock() closed each new branch with RT_ASSERT(RT_TRUE).
With RT_DEBUGING_ASSERT on, RT_ASSERT() expands to `if (!(EX))
rt_assert_handler(...)`, so that guard could never fire: a timer
matching none of the branch's instances enabled no clock at all and
the caller went on to touch an unclocked peripheral's registers. All
three branches are now RT_FALSE. The H7xx guard cannot fire today -
every instance its config header can hand out is already in that
branch's ladder - so fixing it arms the guard against a future
instance added to the table but not the ladder, rather than changing
any existing configuration.
- h497's sdram entry asked for BSP_SDRAM_SIZE=32 while sdram_port.h
documents the part as 8 MB and board/Kconfig declares `range 8 256` with
`default 8`; the 32 came from h760, whose own default happens to be 32.
- drv_hard_i2c.c had no init path at all for H47x_48x/H49x, leaving those
series with an unconfigured controller; the SCL rate now travels in the
config struct instead of being assumed.
- drv_qspi.c and drv_spi.c indexed buffers longer than 65535 bytes with
16-bit counters, which wraps at exactly 65536.
- n32eth_cfg.h is added because the H7xx and H49x SDKs' eth.h include it
but no package in the tree ships it. It probes for the series headers
because the SDK includes it before rtconfig.h can define SOC_SERIES_*,
with a part-macro fallback for ARM Compiler 5, which has no
__has_include() and is what every Keil project in this BSP uses.
- n32h487zgl7-evb now builds with its real 8 MHz crystal; left at the
header's 16 MHz default, RCC_GetClocksFreqValue() reports every clock at
twice its value and the timer prescalers come out twice too large.
- n32h760zil7-stb's timer menus had no mutual exclusion at all, so a timer
instance could be enabled as both a clock timer and a pulse encoder; 24
ISR symbols are defined by both drivers under those two guards, so only
the linker would have caught it. Its 14 PWM menus and its 14 encoder
entries now carry the same guard as the two new boards', using the
PWMn == PULSE_ENCODERN == instance n mapping that config/h7xx's
pulse_encoder_config.h establishes. On the PWM side that guard is a
resource guard, not a link one: drv_pwm.c defines no ISRs.
- the same board's LPTIM menu selected RT_USING_LPTIMER, which is not
declared anywhere in the tree. A select of an undeclared symbol is an
implicit symbol and raises no diagnostic, so the line had never done
anything; it is dropped, as the two new menus already do. Three stm32
boards still carry it and are left alone.
The H49x LPTIM EXTI lines needed the user manual rather than the SDK to
settle, and the manual sides with the driver: N32H49x maps EXTI line 21 to
the LPTIM1 wakeup event and line 22 to LPTIM2, which is what
n32_lptim_get_exti_line() returns. The headers disagree only because
n32h49x_exti.h's EXTI_LINE16..24 block is a verbatim copy of
n32h47x_48x_exti.h's - that one carries on past line 24 and names 25/26 as
the LPTIM events with 21/22 as COMP1/COMP4 - while the H49x series has no
comparator in its SDK at all, so its copy of that text is stale. The
driver states the reasoning in a comment rather than the bare value.
The H49x timer clock-source bits needed the user manual rather than the SDK
to settle. For GTIM8/9/10 (RCC_CFG2 bit 27) h49x names the cleared case
RCC_GTIM_CLKSRC_SYSCLKDIV where h47x_48x names it RCC_GTIM_CLKSRC_PCLK, and
the manual sides with the driver's arithmetic: bit 27 selects SYSCLK, or
SYSCLK/(APB2 prescaler / 2) when that prescaler is engaged - the same rule
the driver writes from the HCLK side as PCLK2 doubled whenever PCLK2 is
below HCLK. Both boards hold AHBPRES at RCC_SYSCLK_DIV1, so HCLK and SYSCLK
are the same 240 MHz and either spelling gives the same number. The driver
tests the raw bit and not either family's constant, so the naming difference
never reaches the code. The same chapter confirms bit 28's inversion, which
the ATIM branches already follow.
Verified: all three boards build from scratch under --strict (gcc -Werror)
with zero diagnostics; all 51 ci-attach entries build clean; the three
series were rebuilt after the assert fix, each through the --attach path
that compiles its branch (devices.timer on all three boards - h760's
default leaves BSP_USING_CLOCK_TIMER off, so drv_tim.c is not compiled by
it at all), rebuilt again after the Kconfig guards, whose
effect was checked by loading the tree with kconfiglib and confirming that
clock-timer ATIM1 with pulse encoder1 goes from satisfiable to unsatisfiable
while a non-colliding pair is left alone); the NAND row-address arms were
confirmed compiled by injecting #error markers and rebuilding through the
real --attach path; each board's committed .config and rtconfig.h reproduce
byte-for-byte from a fresh defconfig; and the CI clang-format gate reports
0 files / 0 lines.
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* [bsp][esp32-c6] add ESP32-C6-DevKitC-1 support
Add bsp/ESP/ESP32_C6. Default image is GPIO, UART0 and ADC. The C6 IDF sources are not in RT-Thread-packages/esp-idf yet.
* [bsp][esp32-c6] fix CI format, C6 package and CH32V203 D6 build
clang-format the files the format check rejected. Fetch the C6 scons
branch when the downloaded ESP-IDF package has no C6 target. Patch the
CH32V20x SDK under libraries so a D6 build no longer calls Exit().
* [bsp][esp32-c6] fetch mbedtls and stop pkgs from pulling the C6 branch
* [bsp][esp32-c6] rebuild CI against the package branch tip
* [bsp][esp32-c6] rebuild CI against the strict-mode package tip
* [bsp][esp32-c6] fix the reviewed ADC, math and package pin bugs
Keep the IDF tree on the reviewed commit, and stop the ADC and critical-section paths from reporting success when they did not.
* [bsp][esp32-c6] reserve stuck interrupt lines and lock ADC
CPU lines 3 and 4 never latch an enable, so copying the handler left the non-IRAM mask on the old line. Reserve those lines and let the allocator write the mask and the route together. The C6 oneshot registers are shared, so one mutex covers enable and convert.
* [bsp][esp32-c6] list the peripherals this board actually runs
GPIO, UART0 and ADC1 have been read on the DevKitC-1. Radios and the untested buses stay marked unsupported.
* [bsp][esp32-c6] keep SPI unsupported after the loopback mismatch
GPIO7 shorted to GPIO2 returned 0xA5000000 for a sent 0xA5, so the table does not mark SPI supported.
---------
Co-authored-by: seteiro <[email protected]>
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- libraries/N32_Drivers: add ADC/DAC/I2C/SPI config headers for the
h47x_48x, h49x and h7xx series, and extend the shared drivers
(adc, dac, eth, gpio, hard_i2c, nand, qspi, sdram, spi, usart, wdt).
- n32h487zgl7-evb / n32h497zgl7-evb: add board ports (femc_timing,
phy_reset, usb_config) and update Kconfig, SConscript, rtconfig and
the IAR/Keil project files.
- n32h760zil7-stb: update Kconfig and rtconfig.
- CI: register the three n32hxxx boards.
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* [bsp][stm32] Add stm32n657-st-nucleo BSP
* style: format STM32 HAL drivers and STM32N657 BSP with clang-format
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Add support for audio, display, Ethernet, PCIe, PHY, SDIO, UFS,
hardware crypto and multimedia accelerators. Update the RK3300 and
RK3500 configurations and validation applications accordingly.
Signed-off-by: GuEe-GUI <[email protected]>
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- reorganize common Raspberry Pi drivers under the device framework
- add the Raspberry Pi 5 BSP, configuration and documentation
- add BCM2712 and DesignWare AXI DMA controller support
- distinguish BCM2712 DMA32 and DMA40 channels by channel mask
- restore DesignWare AXI DMA enable bits after controller reset
- support a shared AXI maximum burst length across DMA channels
Signed-off-by: GuEe-GUI <[email protected]>
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n32h497zgl7-evb和n32h487zgl7-evb bsp (#11627)
1、修改n32\n32gxx_lxx\n32g4frml-stb中的GCC启动文件bl entry
2、修复完善n32h760zil7-stb bsp，支持GCC环境、支持更多外设
3、添加n32h487zgl7-evb初版BSP
4、添加n32h497zgl7-evb初版BSP
5、删除n32g452xx这个bsp
---------
Co-authored-by: OnlyoutzZ <OnlyoutzZ+github[bot]@noreply.github.com>
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Add initial BSP support for the DM-MC02 board based on STM32H723VGT6.
Supported peripherals (Stage 1):
- GPIO (RT_USING_PIN)
- UART1 as FinSH console
Note: Onboard WS2812 LED and other peripherals are planned for Stage 2.
Also update bsp/README.md BSP support summary table.
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Link: https://github.com/RT-Thread/rt-thread/pull/11232
Signed-off-by: GuEe-GUI <[email protected]>
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* feat(bsp/gd32): 增加GDF405RG芯片BSP
* chore(bsp/gd32): 取消git对RTE目录的跟踪，并更新README中的BSP条目
* style(bsp/gd32): 修改格式
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修改clang_format-ignore文件,根据反馈修改n32h7xxx/libraries/N32_Drivers/nano/*下的文件格式，修改n32h7xxx/n32/n32hxxx/n32h760zil7-stb/applications/main.c文件，区别处理Nano下头文件包含
将N32 BSP的.clang-format-ignore文件放入libraries同级目录
忽略库文件格式检查
fix(cherryusb): fix dwc2 host size check
Signed-off-by: sakumisu <[email protected]>
[components][clock_time] Refactor time subsystem around clock_time (#11111)
* [components][clock_time] Refactor time subsystem around clock_time
Introduce the clock_time core with clock source/event separation, high-resolution scheduling, and boot-time helpers, plus clock_timer adapters for timer peripherals.
Remove legacy ktime/cputime/hwtimer implementations and migrate arch and BSP time paths to the new subsystem while keeping POSIX time integration functional.
Update drivers, Kconfig/SConscript wiring, documentation, and tests; add clock_time overview docs and align naming to clock_boottime/clock_hrtimer/clock_timer.
* [components][clock_time] Use BSP-provided clock timer frequency on riscv64
* [risc-v] Use runtime clock timer frequency for tick and delays
* [bsp] Add clock timer frequency hooks for riscv64 boards
* [bsp] Update Renesas RA driver doc clock_timer link
* [bsp] Sync zynqmp-r5-axu4ev rtconfig after config refresh
* [bsp][rk3500] Update rk3500 clock configuration
* [bsp][hpmicro] Add rt_hw_us_delay hook and update board delays
* [bsp][stm32l496-st-nucleo] enable clock_time for hwtimer sample in ci
* [bsp][hpmicro] Fix rtconfig include scope for hpm6750evk
Move rtconfig.h include outside the ENET_MULTIPLE_PORT guard for hpm6750evk and hpm6750evk2 so configuration macros are available regardless of ENET settings.
* [bsp][raspi3] select clock time for systimer
* [bsp][hpm5300evk] Trim trailing blank line
* [bsp][hpm5301evklite] Trim trailing blank line
* [bsp][hpm5e00evk] Trim trailing blank line
* [bsp][hpm6200evk] Trim trailing blank line
* [bsp][hpm6300evk] Trim trailing blank line
* [bsp][hpm6750evk] Trim trailing blank line
* [bsp][hpm6750evk2] Trim trailing blank line
* [bsp][hpm6750evkmini] Trim trailing blank line
* [bsp][hpm6800evk] Trim trailing blank line
* [bsp][hpm6e00evk] Trim trailing blank line
* [bsp][nxp] switch lpc178x to gcc and remove mcx timer source
* [bsp][stm32] fix the CONFIG_RT_USING_CLOCK_TIME issue.
* [docs][clock_time] add clock time documentation
* [docs][clock_time] Update clock time subsystem documentation
- Update device driver index to use correct page reference
- Clarify upper layer responsibilities in architecture overview
- Update README to describe POSIX/libc, Soft RTC, and device driver usage
- Refine architecture diagram with improved layout and color scheme
- Remove obsolete clock_timer.md file
* [kernel][utest] Trim trailing space
* [clock_time] Fix hrtimer wrap handling
* [clock_time] fix the static rt_inline issue
* [clock_time] fix the rt_clock_hrtimer_control result issue
解决N32 BSP project.ewp和project.uvprojx冲突
更新RTT最新同步
sdio: fix missing card status polling after CMD6 in eMMC DDR mode switch
fix[dfs_v1]: prevent vnode ref underflow and double release on close/fd release
feat[STM32][CAN]: drain RX FIFO frames in ISR with a bounded limit to reduce overruns
- Add CAN_ISR_DRAIN_LIMIT (default 3) to cap ISR work
- Drain multiple frames per RX0/RX1 interrupt to reduce FIFO FULL/OVERRUN
docs(can): improve dev_can.h docs for batched RX example
fix[STM32][RTC]: Compute tv_usec from SecondFraction/SubSeconds and skip during shift pending
Use the generic SecondFraction/SubSeconds formula when SSR/PRER are available.
If SHPF is present and a shift is pending, keep tv_usec at 0.
Platforms without SSR/PRER (e.g. F1) default to 0.
[bsp][gd32]:add gd32vw533xx pwm support
Update Nsing's BSP architecture and add N32H7xx series BSPs. (#11159)
* 更新国民技术BSP架构，添加N32H7xx系列BSP
* 修改clang_format-ignore文件,根据反馈修改n32h7xxx/libraries/N32_Drivers/nano/*下的文件格式，修改n32h7xxx/n32/n32hxxx/n32h760zil7-stb/applications/main.c文件，区别处理Nano下头文件包含
* 将N32 BSP的.clang-format-ignore文件放入libraries同级目录
* 忽略库文件格式检查
* 解决N32 BSP project.ewp和project.uvprojx冲突
* 更新RTT最新同步
rename i2c mutex
Co-authored-by: BernardXiong <[email protected]>
Squashed commit of the following:
commit cadd095cd34bb2eaab5e39466f56674a9fe3f19b
Merge: 5ad4edcf39 68da106253
Author: Onlyou_tzZ <[email protected]>
Date: Wed Feb 4 22:50:54 2026 +0800
Merge branch 'RT-Thread:master' into master
commit 68da10625347cfe34fad8b73a78feffbe311d561
Author: CYFS <[email protected]>
Date: Wed Feb 4 16:45:30 2026 +0800
[components][drivers]:fix wlan err
commit 5ad4edcf39330f01f698d95c322c3d0f8aae2feb
Author: Onlyou_tzZ <[email protected]>
Date: Wed Feb 4 20:22:40 2026 +0800
更新BSP下README.md中N32相关的描述
更新BSP下README.md中N32相关的描述
[components][drivers]:fix wlan err
[components][lwip]: fix ping timeout handling and support LWIP_SO_SNDRCVTIMEO_NONSTANDARD
[gd32][uart] Add GD32VW553 series UART driver support (#11147)
* feat(gd32): add GD32VW55x series USART driver support
- Add support for GD32VW55x series UART/USART peripherals
- Implement proper GPIO alternate function configuration for GD32VW55x
- Add conditional compilation for different GD32 series (GD32VF103V vs GD32VW55x)
- Remove unused UART3/UART4 configurations from Kconfig
* Update drv_usart.c
* Update drv_usart.h follow AI Review.
* Update bsp/gd32/risc-v/libraries/gd32_drivers/drv_usart.c
Co-authored-by: Copilot <[email protected]>
* feat: optimize gd32 uart driver error messages
---------
Co-authored-by: Copilot <[email protected]>
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RK3588/RK3576/RK356x/RK3308
Signed-off-by: GuEe-GUI <[email protected]>
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新增 ft32f407xe-starter 板级支持
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revise the README.md
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Requirement: The BSP for the k230 platform in the RT-Thread repository does not yet have a gnne driver.
Solution: Provide gnne driver for the k230 platform in the RT-Thread repository.
- Implements mutex lock mechanism for AI2D and GNNE modules.
- Adds HARDLOCK_AI2D support in hardlock driver for mutual exclusion.
- Implements poll operation for device status monitoring.
- Updates documentation in bsp/README.md.
Signed-off-by: ChuanN-sudo <[email protected]>
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Requirement: The BSP for the k230 platform in the RT-Thread repository does not yet have an spi driver.
Solution: Provide spi driver for the k230 platform in the RT-Thread repository.
- Supports SPI0(OSPI) controller with 1/2/4/8 data lines.
- Supports SPI1(QSPI0) and SPI2(QSPI1) controllers with 1/2/4 data lines.
- Implements DMA-based transfers for OSPI, QSPI, and DSPI modes.
- Falls back to standard IRQ-driven transfers for legacy SPI mode (single line).
- Updates documentation in bsp/README.md
Signed-off-by: ChuanN-sudo <[email protected]>
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* List of RT-Thread BSP Support Additions.
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* Add riscv_32e support
* add bl808 lp core
* update README.md
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