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with ci-attach
The N32H47x_48x and N32H49x series share drv_tim.c with N32H7xx, but only the
H7xx branch was ever implemented, so clock timer, LPTIM, PWM and pulse encoder
built to nothing on n32h487zgl7-evb and n32h497zgl7-evb. This adds those
branches and gives all three boards a ci-attach entry set that actually
compiles what the drivers claim to support.
Drivers
- drv_tim.c gains the H47x_48x/H49x clock-source and clock-enable branches,
the ATIM/GTIM/BTIM instance tables and n32_tim_clock_freq_get(), which
reads the real PCLK/HCLK/SYSCLK back from RCC rather than assuming one.
ATIMCLKSEL is inverted between the two families and is handled as such.
- drv_lptim.c derives its tick from the real LSI value instead of a
hard-coded one, unlocks the backup domain before touching RCC, latches
the prescaler, and returns -RT_EINVAL rather than clamping a bad rate.
- drv_pwm.c and drv_pulse_encoder.c are extended to the H47x_48x/H49x
instances; the H7xx encoder's update event is cleared through
TIM_EnableUpdateEvt() because that family has no TIM_ConfigUpdateEvt().
- config/{h47x_48x,h49x}/{tim,pwm,pulse_encoder,lptim}_config.h are new and
enumerate the instances each series has, for the existing drivers to read.
Kconfig
Each board defines the timer menus in its own board/Kconfig, so that a
board's peripheral options live with the board and the shared driver
Kconfig stays series-neutral; libraries/N32_Drivers/drivers/Kconfig is
byte-identical to upstream/master. All three copies enforce the mutual
exclusion drv_pulse_encoder.c documents (a timer instance enabled for both
clock timer and pulse encoder collides at link time on the shared ISR
symbol); N32H7xx's menus had none at all and are brought in line.
ci-attach
51 entries across the three boards (17/16/18). h487 carries three NAND
entries - peripheral.nand, peripheral.nand_16b and peripheral.nand_large -
and h497 and h760 carry one each. peripheral.nand_large exists because
drv_nand.c picks the row-address cycle count from pages_per_block *
block_count: 2 cycles up to 65536 pages, 3 up to 16777216, else 4. Every
other NAND entry takes the Kconfig default 64 * 1024 = 65536, which lands
exactly on the first boundary, so the >= 3 and >= 4 arms were compiled by
nothing at all - it takes a geometry past the 24-bit row width to reach the
top rung. The entry pins that geometry to arm them; it is not a claim about
the part on the board.
Fixes carried in the same series
- drv_nand.c emitted its third row-address byte under `== 3`, so a 4-cycle
part would set the count to 4 and then match no emitter, dropping the
high row-address bytes outright. The three guards are now >= 3 with the
>= 4 byte added. row_addr is uint32_t at all three sites.
- timer_ctrl() wrote the prescaler straight to a 16-bit PSC field.
TIM_ConfigPrescaler() neither masks nor validates, so any freq below
timer_clock/65537 was truncated and the timer ran at an unrelated rate
while timer->freq still recorded the requested one. That window is
reachable: both boards clock timers at 240 MHz, so the honest floor is
~3662 Hz while tim_config.h sets minfreq = 3000 and only [minfreq,
maxfreq] is checked - 3000 Hz lands in PSC as 14463, about 16.6 kHz.
Division by zero and any prescaler above 0xFFFF now return -RT_EINVAL.
The H7xx branch had the identical truncation, so the same two guards
are applied there too.
- n32_tim_enable_clock() closed each new branch with RT_ASSERT(RT_TRUE).
With RT_DEBUGING_ASSERT on, RT_ASSERT() expands to `if (!(EX))
rt_assert_handler(...)`, so that guard could never fire: a timer
matching none of the branch's instances enabled no clock at all and
the caller went on to touch an unclocked peripheral's registers. All
three branches are now RT_FALSE. The H7xx guard cannot fire today -
every instance its config header can hand out is already in that
branch's ladder - so fixing it arms the guard against a future
instance added to the table but not the ladder, rather than changing
any existing configuration.
- h497's sdram entry asked for BSP_SDRAM_SIZE=32 while sdram_port.h
documents the part as 8 MB and board/Kconfig declares `range 8 256` with
`default 8`; the 32 came from h760, whose own default happens to be 32.
- drv_hard_i2c.c had no init path at all for H47x_48x/H49x, leaving those
series with an unconfigured controller; the SCL rate now travels in the
config struct instead of being assumed.
- drv_qspi.c and drv_spi.c indexed buffers longer than 65535 bytes with
16-bit counters, which wraps at exactly 65536.
- n32eth_cfg.h is added because the H7xx and H49x SDKs' eth.h include it
but no package in the tree ships it. It probes for the series headers
because the SDK includes it before rtconfig.h can define SOC_SERIES_*,
with a part-macro fallback for ARM Compiler 5, which has no
__has_include() and is what every Keil project in this BSP uses.
- n32h487zgl7-evb now builds with its real 8 MHz crystal; left at the
header's 16 MHz default, RCC_GetClocksFreqValue() reports every clock at
twice its value and the timer prescalers come out twice too large.
- n32h760zil7-stb's timer menus had no mutual exclusion at all, so a timer
instance could be enabled as both a clock timer and a pulse encoder; 24
ISR symbols are defined by both drivers under those two guards, so only
the linker would have caught it. Its 14 PWM menus and its 14 encoder
entries now carry the same guard as the two new boards', using the
PWMn == PULSE_ENCODERN == instance n mapping that config/h7xx's
pulse_encoder_config.h establishes. On the PWM side that guard is a
resource guard, not a link one: drv_pwm.c defines no ISRs.
- the same board's LPTIM menu selected RT_USING_LPTIMER, which is not
declared anywhere in the tree. A select of an undeclared symbol is an
implicit symbol and raises no diagnostic, so the line had never done
anything; it is dropped, as the two new menus already do. Three stm32
boards still carry it and are left alone.
The H49x LPTIM EXTI lines needed the user manual rather than the SDK to
settle, and the manual sides with the driver: N32H49x maps EXTI line 21 to
the LPTIM1 wakeup event and line 22 to LPTIM2, which is what
n32_lptim_get_exti_line() returns. The headers disagree only because
n32h49x_exti.h's EXTI_LINE16..24 block is a verbatim copy of
n32h47x_48x_exti.h's - that one carries on past line 24 and names 25/26 as
the LPTIM events with 21/22 as COMP1/COMP4 - while the H49x series has no
comparator in its SDK at all, so its copy of that text is stale. The
driver states the reasoning in a comment rather than the bare value.
The H49x timer clock-source bits needed the user manual rather than the SDK
to settle. For GTIM8/9/10 (RCC_CFG2 bit 27) h49x names the cleared case
RCC_GTIM_CLKSRC_SYSCLKDIV where h47x_48x names it RCC_GTIM_CLKSRC_PCLK, and
the manual sides with the driver's arithmetic: bit 27 selects SYSCLK, or
SYSCLK/(APB2 prescaler / 2) when that prescaler is engaged - the same rule
the driver writes from the HCLK side as PCLK2 doubled whenever PCLK2 is
below HCLK. Both boards hold AHBPRES at RCC_SYSCLK_DIV1, so HCLK and SYSCLK
are the same 240 MHz and either spelling gives the same number. The driver
tests the raw bit and not either family's constant, so the naming difference
never reaches the code. The same chapter confirms bit 28's inversion, which
the ATIM branches already follow.
Verified: all three boards build from scratch under --strict (gcc -Werror)
with zero diagnostics; all 51 ci-attach entries build clean; the three
series were rebuilt after the assert fix, each through the --attach path
that compiles its branch (devices.timer on all three boards - h760's
default leaves BSP_USING_CLOCK_TIMER off, so drv_tim.c is not compiled by
it at all), rebuilt again after the Kconfig guards, whose
effect was checked by loading the tree with kconfiglib and confirming that
clock-timer ATIM1 with pulse encoder1 goes from satisfiable to unsatisfiable
while a non-colliding pair is left alone); the NAND row-address arms were
confirmed compiled by injecting #error markers and rebuilding through the
real --attach path; each board's committed .config and rtconfig.h reproduce
byte-for-byte from a fresh defconfig; and the CI clang-format gate reports
0 files / 0 lines.
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The N32H7xx branch of drv_hard_i2c.c had never been compiled. The file takes
its peripheral declarations from board.h, and only n32h497zgl7-evb includes
n32h49x_i2c.h, so on H7xx every I2C symbol was undefined and the option could
not build at all. Include the peripheral header from the driver itself, the way
drv_sdram.c already does.
I2C_ABORT_ON_TIMEOUT also degraded to a bare `state = I2C_READY` on H7xx, at the
four rt_completion_wait() timeouts in n32_i2c_master_xfer(). The H49x
implementation is written against the older IP - I2C_ClrIntPendingBit,
I2C_STS2_BUSY, I2C_CTRL1_STOPGEN - none of which exist in the H7xx SDK, so give
H7xx its own teardown. It disables the interrupt and DMA request sources,
disables the DMA channel that would otherwise stay armed against the caller's
buffer, releases the bus and clears the status residue.
Only flags with a matching INTCLR bit may be passed to I2C_ClrFlag(), which is a
plain "INTCLR |= flag" write; TFC (0x40) and BUSY (0x8000) have none.
I2C_Configuration() was called from n32_i2c_init() but defined nowhere in the
tree. It is a board hook for pin mux, which is not the driver's job - the H49x
path configures no pins either - so drop the call.
Verified by building n32h760zil7-stb with BSP_USING_HARD_I2C1 and its TX/RX DMA
enabled, which now compiles and links with no warnings, and n32h497zgl7-evb with
I2C1/I2C2 DMA enabled, whose image size is unchanged. Neither board routes I2C
pins yet, so this is build-verified only, not hardware-verified.
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drv_sdram.c includes <sdram_port.h> unconditionally under BSP_USING_SDRAM,
and n32h497zgl7-evb had no such header, so the option could not build at
all. Add one for the M12L64164A fitted on this board: 4 banks x 1M x 16
bits = 8 MB, 12 row address bits, 8 column address bits, SDRAM1 mapped at
0x98000000. The timing values are the ones validated on this board in
hardware.
Three of the Kconfig defaults described a different part:
BSP_SDRAM_DATA_WIDTH_SEL default 32 -> 16
BSP_SDRAM_COLUMN_BITS_SEL default 9 -> 8
BSP_SDRAM_SIZE default 32 -> 8
BANK1, ROW_BIT_12 and CAS_LATENCY_3 already matched and are unchanged.
Verified by building n32h497zgl7-evb with BSP_PERIPH_PIN_CFG_READY and
BSP_USING_SDRAM enabled: drv_sdram.c and the SDK's n32h49x_sdram.c compile
and link with no warnings.
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- qspi: both XSPI variants poll the status flags with no bound, so an
unresponsive bus hangs the caller and silently defeats the timeout it
passed in. Route every wait through the timeout-carrying helpers,
return -RT_ETIMEOUT and disable the controller on failure, and replace
the "poll then send" loops with one bounded wait per element.
- hard_i2c: the interrupt receive path programs the BYTENUM window once
and never reloads it, so a longer message was truncated and still
reported as success; refuse it with -RT_EINVAL (enable RX DMA for
longer reads) instead of capping XferSize. Stop capping the transmit
byte count at the window size as well: BYTENUM counts received bytes
only, and the cap stopped feeding DAT after byte 255 while TXDATE
stayed asserted. Reject RT_I2C_NO_START/RT_I2C_NO_STOP on the series
without frame chaining, where they would silently become a fresh START
and a STOP, and tear the DMA channel down when the address phase times
out instead of leaving it armed against a buffer about to unwind.
- spi: the H7xx LLI chain advanced the memory side by SPI_DMA_BLOCK_MAX
bytes although BlkTfrSize counts elements, so a 16-bit transfer walked
half a word early per node; advance by elements and scale both the
chunk offset and the staging buffer by the data width. Propagate the
DMA arm failure that was ignored.
- nand: an odd data length has no halfword-only encoding on the 16-bit
bus and padding would program a byte the caller never asked for, so
refuse it before the command phase; issue the empty-page dummy store
as a halfword there too, where 8-bit AHB writes are unsupported.
- Kconfig: gate the Ethernet/SDRAM/LCD/QSPI/NAND options behind
BSP_PERIPH_PIN_CFG_READY on all three boards. The peripheral clock and
IO are not configured for these boards yet, so selecting one of them
builds a driver whose pins stay in the reset function.
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- libraries/N32_Drivers: add ADC/DAC/I2C/SPI config headers for the
h47x_48x, h49x and h7xx series, and extend the shared drivers
(adc, dac, eth, gpio, hard_i2c, nand, qspi, sdram, spi, usart, wdt).
- n32h487zgl7-evb / n32h497zgl7-evb: add board ports (femc_timing,
phy_reset, usb_config) and update Kconfig, SConscript, rtconfig and
the IAR/Keil project files.
- n32h760zil7-stb: update Kconfig and rtconfig.
- CI: register the three n32hxxx boards.
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n32h497zgl7-evb和n32h487zgl7-evb bsp (#11627)
1、修改n32\n32gxx_lxx\n32g4frml-stb中的GCC启动文件bl entry
2、修复完善n32h760zil7-stb bsp，支持GCC环境、支持更多外设
3、添加n32h487zgl7-evb初版BSP
4、添加n32h497zgl7-evb初版BSP
5、删除n32g452xx这个bsp
---------
Co-authored-by: OnlyoutzZ <OnlyoutzZ+github[bot]@noreply.github.com>
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* 更新国民技术BSP架构，添加N32H7xx系列BSP
* 修改clang_format-ignore文件,根据反馈修改n32h7xxx/libraries/N32_Drivers/nano/*下的文件格式，修改n32h7xxx/n32/n32hxxx/n32h760zil7-stb/applications/main.c文件，区别处理Nano下头文件包含
* 将N32 BSP的.clang-format-ignore文件放入libraries同级目录
* 忽略库文件格式检查
* 解决N32 BSP project.ewp和project.uvprojx冲突
* 更新RTT最新同步
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* [components][clock_time] Refactor time subsystem around clock_time
Introduce the clock_time core with clock source/event separation, high-resolution scheduling, and boot-time helpers, plus clock_timer adapters for timer peripherals.
Remove legacy ktime/cputime/hwtimer implementations and migrate arch and BSP time paths to the new subsystem while keeping POSIX time integration functional.
Update drivers, Kconfig/SConscript wiring, documentation, and tests; add clock_time overview docs and align naming to clock_boottime/clock_hrtimer/clock_timer.
* [components][clock_time] Use BSP-provided clock timer frequency on riscv64
* [risc-v] Use runtime clock timer frequency for tick and delays
* [bsp] Add clock timer frequency hooks for riscv64 boards
* [bsp] Update Renesas RA driver doc clock_timer link
* [bsp] Sync zynqmp-r5-axu4ev rtconfig after config refresh
* [bsp][rk3500] Update rk3500 clock configuration
* [bsp][hpmicro] Add rt_hw_us_delay hook and update board delays
* [bsp][stm32l496-st-nucleo] enable clock_time for hwtimer sample in ci
* [bsp][hpmicro] Fix rtconfig include scope for hpm6750evk
Move rtconfig.h include outside the ENET_MULTIPLE_PORT guard for hpm6750evk and hpm6750evk2 so configuration macros are available regardless of ENET settings.
* [bsp][raspi3] select clock time for systimer
* [bsp][hpm5300evk] Trim trailing blank line
* [bsp][hpm5301evklite] Trim trailing blank line
* [bsp][hpm5e00evk] Trim trailing blank line
* [bsp][hpm6200evk] Trim trailing blank line
* [bsp][hpm6300evk] Trim trailing blank line
* [bsp][hpm6750evk] Trim trailing blank line
* [bsp][hpm6750evk2] Trim trailing blank line
* [bsp][hpm6750evkmini] Trim trailing blank line
* [bsp][hpm6800evk] Trim trailing blank line
* [bsp][hpm6e00evk] Trim trailing blank line
* [bsp][nxp] switch lpc178x to gcc and remove mcx timer source
* [bsp][stm32] fix the CONFIG_RT_USING_CLOCK_TIME issue.
* [docs][clock_time] add clock time documentation
* [docs][clock_time] Update clock time subsystem documentation
- Update device driver index to use correct page reference
- Clarify upper layer responsibilities in architecture overview
- Update README to describe POSIX/libc, Soft RTC, and device driver usage
- Refine architecture diagram with improved layout and color scheme
- Remove obsolete clock_timer.md file
* [kernel][utest] Trim trailing space
* [clock_time] Fix hrtimer wrap handling
* [clock_time] fix the static rt_inline issue
* [clock_time] fix the rt_clock_hrtimer_control result issue
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加超时时间、flush、获取缓冲区数据长度命令、数据溢出逻辑修复、稳定性细节优化、添加更多serial_v2测试用例
[components][serial_v2] 优化txflush逻辑、对tx的activated做中断保护
[components][at] at_client适配新版serial_v2
[components][at] at_server适配新版serial_v2
[components][serial_v2] 测试用例增加循环调用，format测试用例
[components][serial_v2] poll模式判断逻辑错误
[components][serial_v2] 测试用例去掉一些非必要延时
[components][serial_v2] 测试例程使用menuconfig进行配置，更新readme
[components][at_client] at_client_getchar返回值错误、at_client解析线程优先级错误设置
[components][at] 错误码应该返回负值
[components][serial_v2] TCFLSH和FIONREAD完善、control函数增加错误返回值
[components][serial_v2] RT_SERIAL_CTRL_GET_RX_DATA_LEN更改为RT_SERIAL_CTRL_GET_UNREAD_BYTES_COUNT
[utest][serial_v2] TC_UART_SEND_TIMES替换为RT_SERIAL_TC_SEND_ITERATIONS
[components][serial_v2] FIONREAD参数应该是无符号类型
[utest][serial_v2] 完善测试用例
[components][serial_v2] 避免使用三目运算符
[components][serial_v2] 使用clang-format格式化代码
[components][serial_v2] 添加get超时时间命令
[components][serial_v2] 完善posix接口
[components][serial_v2] 阻塞接口添加阻塞时间为0时的处理逻辑、优化RX阻塞接收逻辑
[components][serial_v2] 设置超时时间命令的参数改为指针形式
[components][serial_v2] nbuf发送添加超时时间为0时的逻辑
[components][serial_v2] 完善添加测试用例
[utest][serial_v2] 修复依赖关系
[components][serial_v2] 非阻塞模式下tx_flush错误修复
[components][serial_v2] activated使用原子API
[components][serial_v2] 优化DMA逻辑、没使能DMA时屏蔽DMA逻辑节约资源
[components][serial_v2] 提供写满时丢弃新数据和覆盖旧数据策略，写满丢弃策略效率更高
[components][serial_v2] 部分平台适配写满时两种策略功能
[components][serial_v2] DMA模式暂不支持丢弃新数据策略
[utest][serial_v2] 优化测试代码
[components][serial_v2] DMA模式下使用乒乓缓冲、DMA模式支持丢弃新数据策略
[utest][serial_v2] 适配DMA乒乓缓冲
[bsp][serial_v2] 部分bsp适配DMA下乒乓缓冲
[components][serial_v2] 使用spinlock替换中断，对部分结构体变量使用原子操作
[utest][serial_v2] 更新测试用例
[components][at] 适配new serialv2不再判断RTT版本号
[components][at] 删除多余的中文注释
[utest][serial_v2] 添加交叉echo示例，qemu环境下专用
[bsp][qemu] 适配串口v2并开启fifo
[components][at] 修复合并导致的错误
[bsp][n32] 适配serial_v2，没有经过测试
[components][serial_v2] 格式化代码
[utest][serial_v2] 删除无意义的打印
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sync update
some optimize
[bsp][driver] Updates the naming convention of the i2c configuration item
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* sync and update
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* [errno code]fix that use RT_ENOSYS without -
* Update bsp/airm2m/air32f103/libraries/rt_drivers/drv_hwtimer.c
---------
Co-authored-by: Man, Jianting (Meco) <[email protected]>
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rt_ssize_t can give negative error code, which follows the unix style correctly
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新增n32g4frml-stb bsp，在n32g4frml-stb 开发板上测试通过。
Add n32g4frml-stb bsp. passed the test on the n32g4frml-stb board.
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* 修改ry命令，已便于自定义保存路径
* modified: components/utilities/ymodem/ry_sy.c
* 修复从被动错误恢复后发送返回异常
* 修复在自动重传模式下,ACK异常阻塞线程
- 删除TX中断函数else分支。仅当RQCP位 置一才进入该中断
- 添加SCE中断函数中关于ACK_ERR的else判断。自动重传模式下会进入该判断,打断自动重传释放完成量。
* 增加对于CAN1与CAN2的SCE中断和TX中断的公共处理函数
* formatting格式化代码
* update struct can_filter_item and rt_can_msg
1. 对过滤器号和索引号结构体定义中同一名称hdr进行重命名hdr_bank和hdr_index,
以便准确区分.采用宏定义兼容以前变量名.
2. 添加接收标识rxfifo,已指明是哪个RXFIFO.
* 更正42M下的波特率
* 修复接收获取索引号错误
* 添加接收标识
* 更新注释
* 取消CANFD限制
* update struct can_filter_item and rt_can_msg
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�设置工作模式时已设置,后面出现重复设置。
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add bsp n32g43xcl-stb,n32g45xcl-stb,n32g45xml-stb,n32g45xrl-stb,n32g457qel-stb,n32l40xcl-stb,n32l43xml-stb,n32l43xrl-stb,n32l436_evb,n32wb45xl-evb
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* [bsp][sconscript] 整理统一sconscript格式
* update
* update
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