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Newer GCC emits C++ global constructors into .init_array, which many
linker scripts keep outside [__ctors_start__, __ctors_end__), so they
never ran. Walk __init_array_start/__init_array_end (weak) as well,
skipping entries already covered by the ctors range.
Add RT_USING_CPP_CRT_INIT for ports whose startup runtime already runs
.init_array, default on for the simulator. With it set, only the
.init_array walk is skipped; the ctors range is still walked.
Renesas RA/RA_WIRELESS/RZ families select it when C++ is enabled: FSP
SystemInit() already walks .init_array, so boards whose linker script
only provides __init_array_* would run constructors twice. Boards that
fold .init_array into the ctors range (ra6m3-hmi-board, ra8d1, rz)
still run them once via RT-Thread.
Also source env.sh and restore RTT_EXEC_PATH in ToolsCI project generate
and dist steps so scons is on PATH (exit 127) and the ARM toolchain path
is not overwritten by env.sh.
Fixes #11778
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修复 SCI SPI 分频参数和运行时配置生命周期，保持位宽单位一致，应用模式及片选配置，并在收发超时或错误后停止传输、清理状态。
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erase and write operation occurs.
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Add M85 device-tree GPIO and external-interrupt controllers, IRQ20 FSP integration, built-in DTB support, and BSP usage documentation.
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同步 Renesas BSP 的 MDK5 工程生成方式，移除对 RASC gpdsc/build hook 的依赖，并更新由 scons 生成的 Keil 工程。
已保留存在实际 via 文件的 BSP 配置，仅移除缺失 via 文件的引用。
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The Renesas LCD helper treats LCD_WIDTH and LCD_HEIGHT as pixel counts. The framebuffer clear loop and lcd_draw_pixel() accepted those count values as valid indexes, which can write one pixel past the framebuffer.
Use strict bounds for the 0-based framebuffer indexes and adjust the 180-degree rotation mapping to target the last valid row and column.
Generated-by: OpenAI Codex
Signed-off-by: Old-Ding <[email protected]>
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Validate the second and third digits of RA PXXX pin names against their own characters. The previous checks used name[1] for those upper bounds, so non-digit suffixes could pass validation.
Generated-by: OpenAI Codex
Signed-off-by: Old-Ding <[email protected]>
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* [utest][pin] add pin loopback utest
* [utest][pin] add BSP CI coverage
* [utest][pin] fix BSP CI config
* [utest][pin] fix ra8p1 utest link section
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* [components][clock_time] Refactor time subsystem around clock_time
Introduce the clock_time core with clock source/event separation, high-resolution scheduling, and boot-time helpers, plus clock_timer adapters for timer peripherals.
Remove legacy ktime/cputime/hwtimer implementations and migrate arch and BSP time paths to the new subsystem while keeping POSIX time integration functional.
Update drivers, Kconfig/SConscript wiring, documentation, and tests; add clock_time overview docs and align naming to clock_boottime/clock_hrtimer/clock_timer.
* [components][clock_time] Use BSP-provided clock timer frequency on riscv64
* [risc-v] Use runtime clock timer frequency for tick and delays
* [bsp] Add clock timer frequency hooks for riscv64 boards
* [bsp] Update Renesas RA driver doc clock_timer link
* [bsp] Sync zynqmp-r5-axu4ev rtconfig after config refresh
* [bsp][rk3500] Update rk3500 clock configuration
* [bsp][hpmicro] Add rt_hw_us_delay hook and update board delays
* [bsp][stm32l496-st-nucleo] enable clock_time for hwtimer sample in ci
* [bsp][hpmicro] Fix rtconfig include scope for hpm6750evk
Move rtconfig.h include outside the ENET_MULTIPLE_PORT guard for hpm6750evk and hpm6750evk2 so configuration macros are available regardless of ENET settings.
* [bsp][raspi3] select clock time for systimer
* [bsp][hpm5300evk] Trim trailing blank line
* [bsp][hpm5301evklite] Trim trailing blank line
* [bsp][hpm5e00evk] Trim trailing blank line
* [bsp][hpm6200evk] Trim trailing blank line
* [bsp][hpm6300evk] Trim trailing blank line
* [bsp][hpm6750evk] Trim trailing blank line
* [bsp][hpm6750evk2] Trim trailing blank line
* [bsp][hpm6750evkmini] Trim trailing blank line
* [bsp][hpm6800evk] Trim trailing blank line
* [bsp][hpm6e00evk] Trim trailing blank line
* [bsp][nxp] switch lpc178x to gcc and remove mcx timer source
* [bsp][stm32] fix the CONFIG_RT_USING_CLOCK_TIME issue.
* [docs][clock_time] add clock time documentation
* [docs][clock_time] Update clock time subsystem documentation
- Update device driver index to use correct page reference
- Clarify upper layer responsibilities in architecture overview
- Update README to describe POSIX/libc, Soft RTC, and device driver usage
- Refine architecture diagram with improved layout and color scheme
- Remove obsolete clock_timer.md file
* [kernel][utest] Trim trailing space
* [clock_time] Fix hrtimer wrap handling
* [clock_time] fix the static rt_inline issue
* [clock_time] fix the rt_clock_hrtimer_control result issue
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义 (#10859)
* [BSP][renesas][rsoc][fix]:移除HAL_Drivers/config/ra2a1,add pwm configuration items
* 在pwm_config里新增对BSP_USING_PWM10到BSP_USING_PWM12的定义
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* [bsp][renesas][ra4m1-ek] add a new bsp for ra4m1-ek board
* [bsp][renesas][ra4m1-ek] fix can driver compile problem
* [bsp][renesas][ra4m1-ek] bsp code format
* [bsp][renesas][ra4m1-ek] reset file status to original generated by RASC
* [bsp][renesas][ra4m1-ek] support RT-Thread Nano
* [bsp][renesas][ra4m1-ek] make it mini support for GPIO && USART
* [bsp][renesas][ra4m1-ek] make it compilable under the GCC compiler
* [bsp][renesas][ra4m1-ek] remove component RT_USING_CPLUSPLUS
* [bsp][renesas][ra4m1-ek] reduce bsp peripheral device driver
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* [bsp/renesas] add bsp ra4e2-ek
* bsp: Renesas ra4e2-ek bsp support the nano
* fix bsp and SOC_SERIES_R7FA4E2
* remove file R7FA4E2B9.svd
工程未使用此文件，
此文件在renesas bsp中已有一份,此文件可以删除
bsp\renesas\ra4e2-eco\script\R7FA4E2B9.svd
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add AD\DA and Flash device
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* [bsp][renesas]add EK-RA2E2 sci_uart support
* [bsp][renesas] add EK-RA2E2 (i2c/spi/adc/pwm/flash/gpio interrupt) support
* [bsp][renesas] comment drv_flash.c and format drv_i2c.c
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* add EK-RA2E2 support
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statically created.
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* bsp: all Renesas bsp support the nano one-click switch.
* fix pr conflicts.
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