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- Enable SPI6 on-chip driver with TX/RX selectable DMA/BDMA modes
(BDMA options come from the shared HAL_Drivers Kconfig)
- Reserve the WS2812 BDMA buffer section (.ws2812_bdma) in SRAM4
across GCC/IAR/MDK5 linker scripts for a standalone package
- Sync CubeMX configuration and regenerate MDK5 project
- Update README with SPI6/BDMA support status
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IlinkIcfFile in 5 BSP template.ewp files pointed to absolute paths on other developers' machines, which scons --target=iar copies into the generated project.ewp and breaks builds elsewhere.
Affected: asm9260t, mm32f3270-100ask-pitaya, stm32f103-100ask-mini, stm32f103-100ask-pro and imxrt1180-nxp-evk/cm7 (3 configurations).
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Add the missing UART4 RX DMA definitions for STM32H7.
UART4 RX DMA uses DMA1 Stream0 with the UART4 RX DMA request.
The configuration is enabled when BSP_UART4_RX_USING_DMA is selected.
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将函数声明从static改为extern，解决跨文件调用时的链接错误，
确保DMA、BDMA和GPDMA类型的日志标签能够正确生成。
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* [bsp][stm32] Add stm32n657-st-nucleo BSP
* style: format STM32 HAL drivers and STM32N657 BSP with clang-format
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- Unify DMA/BDMA/GPDMA descriptors in drv_dma (common fields + per-type union)
- Support BDMA in SPI driver with h7 dma/spi config header updates
- Add SPI6 TX/RX BDMA Kconfig options for H7
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Enable RT_USING_HW_STACK_GUARD on Cortex-M4, which was previously only
available on Cortex-M7 and Cortex-M33.
Core porting (libcpu/arm/cortex-m4/):
- Add mpu.c/mpu.h/mputype.h aligned with the Cortex-M7 MPU layer. The only
difference is the default memory type attribute: Cortex-M4 has no L1 cache,
so the cacheability bits are reduced to three cases.
- Add rt_hw_stack_guard_init() to cpuport.c.
- Add missing #include <rtconfig.h> to context_gcc.S and invoke
rt_hw_mpu_table_switch() in the PendSV context switch path.
- Update SConscript to exclude mpu.c when memory protection is disabled.
BSP reference (bsp/stm32/stm32f407-fk407m2-zgt6/):
- board.h: include rtthread.h and define NUM_STATIC_REGIONS.
- board.c: define static_regions[] marking the Flash region read-only,
guarded by RT_USING_MEM_PROTECTION so it is not enabled by default.
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Improve the Rust build integration across core, applications, components, and module examples. Fix build failure propagation, target and feature handling, linker flags, example configuration semantics, and add STM32 CI attach coverage.
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Add device-tree GPIO/EXTI controllers, built-in DTB support for GCC and ArmClang, and BSP integration for STM32F407 RT-Spark and STM32H750 ART-Pi. Document how BSP users enable the DM drivers.
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* [bsp][drives]fix(spi_config):修复H7的SPI6配置缺失问题
* style: format code with clang-format [skip ci]
* [bsp][stm32]refactor:(spi_config):去除尚不支持的DMA相关配置
* [bsp][stm32]refactor(spi_config):格式化SPI_CONFIG.H
---------
Co-authored-by: moment-NEW <moment-NEW+github[bot]@noreply.github.com>
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* feat[ADC V2]: add ADC V2 driver support
add ADC V2 core APIs, session state management, and sequence read support
add STM32 ADC V2 HAL backend with internal-channel and VREF handling
add per-series STM32 ADC V2 default configuration headers
wire ADC V2 Kconfig and SConscript integration for components and STM32 BSP drivers
keep ADC V2 mutually exclusive with the legacy ADC driver path
* feat[ADC V2]: add ADC V2 MSH special channel read support
add generic ADC V2 MSH commands for probing, configuring, raw reads, voltage reads, and sequence reads
add STM32 ADC V2 backend special commands for VREFINT, temperature sensor, and VBAT reads
add STM32 helper APIs for special logical channels, sampling time, resolution, and temperature calculation
wire ADC V2 MSH sources through Kconfig and SConscript
* feat[ADC V2]: add ADC V2 stream DMA support
add ADC V2 stream APIs with latest-frame and FIFO buffering policies
wire STM32 ADC V2 to circular DMA stream mode with per-instance Kconfig options
extend STM32 ADC config headers and DMA helpers for stream DMA configuration
add FinSH stream commands for start, read, cancel, and stop operations
handle Cortex-M7 cache-safe DMA buffers for STM32 stream sampling
* feat[ADC V2]: add timer trigger support for ADC V2 streams
add ADC V2 trigger configuration, validation, and lifecycle coordination
add timer update trigger support through clock timer TRGO controls
map STM32 ADC V2 timer update triggers to HAL external trigger selector fields
add Kconfig, SConscript, and MSH entries for ADC trigger setup and inspection
* feat[ADCV2]: add timer and comparator trigger selectors
add ADC V2 timer compare and analog comparator trigger configuration support
extend clock timer trigger config with compare event and channel fields
wire STM32 ADC external trigger selector mappings for TIM update, TIM compare, and COMP output
add FinSH trigger_set commands and Kconfig switches for timer and comparator trigger backends
* fix[ADC V2]: resolve ADC V1 compatibility Kconfig loop
* ci[ADC V2][stm32]: add ADC v2 peripheral config for stm32f407-rt-spark BSP
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add serial v2 RX DMA event mode configuration for DMA-enabled builds
support STM32 UART RX DMA half/full transfer interrupt policy selection
validate RX DMA event mode before applying serial configuration
restore serial configuration when backend configure fails
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Add initial BSP support for the DM-MC02 board based on STM32H723VGT6.
Supported peripherals (Stage 1):
- GPIO (RT_USING_PIN)
- UART1 as FinSH console
Note: Onboard WS2812 LED and other peripherals are planned for Stage 2.
Also update bsp/README.md BSP support summary table.
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* [utest][pin] add pin loopback utest
* [utest][pin] add BSP CI coverage
* [utest][pin] fix BSP CI config
* [utest][pin] fix ra8p1 utest link section
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1.Remove unnecessary comments
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centralize hard I2C per-message route state for DMA, interrupt, and polling paths
make multi-message and no-stop transfers use sequential HAL APIs only
snapshot scheduler and interrupt context once for stable async transfer decisions
reuse the transaction timeout for async wait logging and abort recovery
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snapshot scheduler and interrupt state once per SPI message
reuse the message-level async route decision for all split chunks
disable DMA and interrupt paths consistently when async transfer is unavailable
avoid mixed async and polling policies within one logical SPI transfer
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preload the actual HAL receive buffer with 0xFF for receive-only transfers
rename spi_dma_flag to spi_xfer_flags to match DMA and interrupt flags
clarify SPI async completion and transfer-mode comments
add Doxygen comments for STM32 SPI runtime structures and handlers
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introduce interrupt transfer route selection and SPI IRQ visibility macros
unify DMA and INT completion handling with timeout-triggered abort recovery
keep short transfers on polling and use DMA or INT only when eligible
refine STM32 SPI init and IRQ registration paths for mixed transfer backends
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refine the stm32 hard spi dma configuration hierarchy with shared feature macros
align dma flag usage with rt-device dma flags and gate dma-only fields and paths
make the dma transfer threshold configurable through BSP_SPI_DMA_TRANS_MIN_LEN
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enable I2C error irq when async transfer paths are used fall back to polling when scheduler or interrupt context cannot wait for completion complete the wait path on HAL error callback and abort the transfer on async timeout or error allow INT and DMA mode flags to coexist and keep recovery behavior aligned across STM32 I2C IPs
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- migrate STM32 HAL driver DMA config macros to shared descriptor init helpers
- add overridable DMA priority and NVIC priority fields for board-level configs
- align SPI, UART, I2C, SDIO, and QSPI DMA descriptors across visible STM32 series configs
- simplify per-series DMA config definitions and reduce duplicated field assignments
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- add drv_dma common helpers and stm32_dma_config descriptors for STM32 series
- refactor i2c, spi, usart, qspi, and sdio DMA setup and deinit paths to reuse the common layer
- unify DMA IRQ enable, rollback handling, and const board-level DMA configuration usage
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calculation
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add a control command to register a per-device uart error callback
invoke the callback from the HAL uart error hook and clear it before close
return -RT_ENOSYS when dma mode is requested without dma support
propagate the set-int fallback result in optmode setup to keep control return values explicit
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