| Age | Commit message (Collapse) | Author |
|---|
|
|
|
|
|
- Add chip macro for driver
- Modify 'IDLE_THREAD_STACK_SIZE' to 512
- Modify 'HWTIMER' to 'CLOCK_TIMER'
- Use 'clang-format' format driver and BSP code
- Fix SPI clock division configuration
|
|
|
|
|
|
|
|
* [bsp][imxrt1180-nxp-evk]add TIMER support
* [bsp][imxrt1180-nxp-evk]update TIMER support
* [bsp][imxrt1180-nxp-evk] move fsl_gpt.c inclusion to SDK package SConscript
* [bsp][imxrt1180-nxp-evk] restore main.c to original Hello_World version
* [bsp][imxrt1180-nxp-evk] remove libraries/drivers/drv_timer.h
* [bsp][imxrt1180-nxp-evk]update TIMER support
|
|
|
|
|
|
|
|
同步 Renesas BSP 的 MDK5 工程生成方式，移除对 RASC gpdsc/build hook 的依赖，并更新由 scons 生成的 Keil 工程。
已保留存在实际 via 文件的 BSP 配置，仅移除缺失 via 文件的引用。
|
|
rt_hw_eth_init() clears ENET descriptor tables using element size times count, but the RX/TX data buffers used sizeof(size), which only covers the width of the size field.
Use the configured buffer count and size so the whole RX/TX buffer areas are initialized before handing them to the ENET descriptor configuration.
Make the Cppcheck intent explicit for the HPM placement macros and the LPI_CSR register read so the touched file passes static analysis.
Signed-off-by: Old-Ding <[email protected]>
|
|
RT_CAN_CMD_SET_BITTIMING receives an array of struct rt_can_bit_timing entries. The Rockchip CAN-FD driver used sizeof(&timing->items[n]) when copying those entries, so only pointer-sized bytes were copied into the device configuration.
Use the element size so both arbitration and data phase timing structures are copied completely.
Generated-by: OpenAI Codex
Signed-off-by: Old-Ding <[email protected]>
|
|
Reset the whole FQSpi_CmdPack object before reusing it in the QSPI debug commands. Using sizeof(&cmd_pack) only clears the pointer-sized prefix and can leave stale fields in the command pack.
Generated-by: OpenAI Codex
Signed-off-by: Old-Ding <[email protected]>
|
|
Check the buffer limits before reading ptr[i] in bufferred_fgets(). Also guard CR/LF skipping against the available input bytes so reading a full buffer does not inspect one byte past the source.
Generated-by: OpenAI Codex
Signed-off-by: Old-Ding <[email protected]>
|
|
The Renesas LCD helper treats LCD_WIDTH and LCD_HEIGHT as pixel counts. The framebuffer clear loop and lcd_draw_pixel() accepted those count values as valid indexes, which can write one pixel past the framebuffer.
Use strict bounds for the 0-based framebuffer indexes and adjust the 180-degree rotation mapping to target the last valid row and column.
Generated-by: OpenAI Codex
Signed-off-by: Old-Ding <[email protected]>
|
|
* feat[ADC V2]: add ADC V2 driver support
add ADC V2 core APIs, session state management, and sequence read support
add STM32 ADC V2 HAL backend with internal-channel and VREF handling
add per-series STM32 ADC V2 default configuration headers
wire ADC V2 Kconfig and SConscript integration for components and STM32 BSP drivers
keep ADC V2 mutually exclusive with the legacy ADC driver path
* feat[ADC V2]: add ADC V2 MSH special channel read support
add generic ADC V2 MSH commands for probing, configuring, raw reads, voltage reads, and sequence reads
add STM32 ADC V2 backend special commands for VREFINT, temperature sensor, and VBAT reads
add STM32 helper APIs for special logical channels, sampling time, resolution, and temperature calculation
wire ADC V2 MSH sources through Kconfig and SConscript
* feat[ADC V2]: add ADC V2 stream DMA support
add ADC V2 stream APIs with latest-frame and FIFO buffering policies
wire STM32 ADC V2 to circular DMA stream mode with per-instance Kconfig options
extend STM32 ADC config headers and DMA helpers for stream DMA configuration
add FinSH stream commands for start, read, cancel, and stop operations
handle Cortex-M7 cache-safe DMA buffers for STM32 stream sampling
* feat[ADC V2]: add timer trigger support for ADC V2 streams
add ADC V2 trigger configuration, validation, and lifecycle coordination
add timer update trigger support through clock timer TRGO controls
map STM32 ADC V2 timer update triggers to HAL external trigger selector fields
add Kconfig, SConscript, and MSH entries for ADC trigger setup and inspection
* feat[ADCV2]: add timer and comparator trigger selectors
add ADC V2 timer compare and analog comparator trigger configuration support
extend clock timer trigger config with compare event and channel fields
wire STM32 ADC external trigger selector mappings for TIM update, TIM compare, and COMP output
add FinSH trigger_set commands and Kconfig switches for timer and comparator trigger backends
* fix[ADC V2]: resolve ADC V1 compatibility Kconfig loop
* ci[ADC V2][stm32]: add ADC v2 peripheral config for stm32f407-rt-spark BSP
|
|
Validate the second and third digits of RA PXXX pin names against their own characters. The previous checks used name[1] for those upper bounds, so non-digit suffixes could pass validation.
Generated-by: OpenAI Codex
Signed-off-by: Old-Ding <[email protected]>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
add serial v2 RX DMA event mode configuration for DMA-enabled builds
support STM32 UART RX DMA half/full transfer interrupt policy selection
validate RX DMA event mode before applying serial configuration
restore serial configuration when backend configure fails
|
|
|
|
|
|
|
|
The I2C will timeout in fan53555, fixed it.
Signed-off-by: GuEe-GUI <[email protected]>
|
|
|
|
Add initial BSP support for the DM-MC02 board based on STM32H723VGT6.
Supported peripherals (Stage 1):
- GPIO (RT_USING_PIN)
- UART1 as FinSH console
Note: Onboard WS2812 LED and other peripherals are planned for Stage 2.
Also update bsp/README.md BSP support summary table.
|
|
* [utest][pin] add pin loopback utest
* [utest][pin] add BSP CI coverage
* [utest][pin] fix BSP CI config
* [utest][pin] fix ra8p1 utest link section
|
|
|
|
1.Remove unnecessary comments
|
|
|
|
Link: https://github.com/RT-Thread/rt-thread/pull/11232
Signed-off-by: GuEe-GUI <[email protected]>
|
|
centralize hard I2C per-message route state for DMA, interrupt, and polling paths
make multi-message and no-stop transfers use sequential HAL APIs only
snapshot scheduler and interrupt context once for stable async transfer decisions
reuse the transaction timeout for async wait logging and abort recovery
|
|
snapshot scheduler and interrupt state once per SPI message
reuse the message-level async route decision for all split chunks
disable DMA and interrupt paths consistently when async transfer is unavailable
avoid mixed async and polling policies within one logical SPI transfer
|
|
Signed-off-by: GuEe-GUI <[email protected]>
|
|
Signed-off-by: GuEe-GUI <[email protected]>
|
|
1. version for v1.2
2. support packed queue
1. support MMIO/PCI over bus
2. new virtio queue api with dma/cpu sync
3. update for virtio device drivers:
- net
- block
- console
- input
- gpu
4. new virtio device drivers:
- 9p
- crypto
- rng
- scmi
- scsi
Signed-off-by: GuEe-GUI <[email protected]>
|
|
|
|
|
|
|
|
|
|
|
