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* [libcpu][risc-v] Refactor the RISC-V architecture port
Introduce an opt-in unified RISC-V common layer for RV32 and RV64 while keeping existing BSPs on the legacy implementation during migration.
- use ARCH_RISCV and ARCH_CPU_64BIT for architecture and XLEN selection
- unify context, trap, MMU, cache, timer, SBI, SMP and ISA handling
- add PLIC, CLIC, ACLINT, APLIC and IMSIC support
- map physical hart IDs to contiguous logical CPU IDs
- add T-Head vendor overrides while preserving legacy ports
- migrate qemu-virt64-riscv with RV32 and RV64 support
- update clock_time, MM, LWP, OFW, PCI and Rust integration
Existing BSPs continue using legacy_common or common64 unless they select RT_USING_RISCV_NEW_COMMON.
Signed-off-by: GuEe-GUI <[email protected]>
* [libcpu][risc-v] skip disabled CPU nodes in early FDT walk
Rbb666 noted that rt_hw_fdt_install_early() walked every /cpus child
without checking status, so disabled cores still joined hart registration
and MMU capability probing. Skip nodes that are not okay/ok via
rt_fdt_device_is_available() before reading reg or mmu-type.
Signed-off-by: seteiro <[email protected]>
* [libcpu][risc-v] Fix per-CPU page table mapping
- reuse existing non-leaf page table entries when mapping per-CPU areas
- reject leaf entry conflicts instead of overwriting mappings
Signed-off-by: GuEe-GUI <[email protected]>
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Signed-off-by: GuEe-GUI <[email protected]>
Signed-off-by: seteiro <[email protected]>
Co-authored-by: seteiro <[email protected]>
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* [DM/OFW][PCI] Fix address translation and PCI resource enumeration
Rework OFW address translation to walk nested bus ranges in the correct
direction and cache "ranges" and "dma-ranges" independently. Handle PCI
three-cell addresses without treating the PCI flags cell as part of the
address, and fix CPU-to-DMA and DMA-to-CPU translation across nested
buses.
Fix PCI BAR sizing and assignment by disabling address decoding during
probing, preserving BAR attribute bits, and programming 64-bit BARs
correctly. Add device enable and disable helpers so resources and bus
mastering are enabled before driver probe.
Program bridge memory and prefetch windows while scanning downstream
buses, correctly link child buses into the PCI bus hierarchy, and avoid
unnecessary PCIe link retraining when the link is already active.
Allow host bridges without a device-tree pci-domain property by
allocating unique domains dynamically, while preserving explicit domain
assignments.
Fix MSI and MSI-X IRQ setup, rollback, vector addressing, and affinity
selection.
Add the Raspberry Pi PCI vendor ID for RP1 and other downstream devices.
Signed-off-by: GuEe-GUI <[email protected]>
* style: format code with clang-format
* style: format complete changed files with clang-format
* drivers: pci: address OFW review feedback
* style: format PCI and OFW changes for current master
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Signed-off-by: GuEe-GUI <[email protected]>
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[OFW] io ranges use ptr array to storage without ofw data
ofw data is private data for every ofw node that
the drivers of ofw node will use item.
replace the ranges supported to a ptr array.
the ptr array size is config by `RT_USING_OFW_BUS_RANGES_NUMBER`
Signed-off-by: GuEe-GUI <[email protected]>
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We support OFW API to replace fdt old API, and add
IRQ, IO, Platform-Bus, CPUs ... OFW node contorl.
To support work with Device Tree or ACPI in drivers
that use IRQ, we make a programmable interrupt
controller driver's model.
Signed-off-by: GuEe-GUI <[email protected]>
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