| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2026-09-10 | [libcpu] Fix RZ/N2L interrupt dispatch | CYFS | |
| 2026-09-01 | fix[arm][cortex-m4]: clarify MPU permission expressions | wdfk-prog | |
| 2026-08-26 | [arm][cortex-m4] Add hardware stack guard support | hanzhijian | |
| Enable RT_USING_HW_STACK_GUARD on Cortex-M4, which was previously only available on Cortex-M7 and Cortex-M33. Core porting (libcpu/arm/cortex-m4/): - Add mpu.c/mpu.h/mputype.h aligned with the Cortex-M7 MPU layer. The only difference is the default memory type attribute: Cortex-M4 has no L1 cache, so the cacheability bits are reduced to three cases. - Add rt_hw_stack_guard_init() to cpuport.c. - Add missing #include <rtconfig.h> to context_gcc.S and invoke rt_hw_mpu_table_switch() in the PendSV context switch path. - Update SConscript to exclude mpu.c when memory protection is disabled. BSP reference (bsp/stm32/stm32f407-fk407m2-zgt6/): - board.h: include rtthread.h and define NUM_STATIC_REGIONS. - board.c: define static_regions[] marking the Flash region read-only, guarded by RT_USING_MEM_PROTECTION so it is not enabled by default. | |||
| 2026-08-12 | refactor(pic): dispatch NVIC IRQs through traps | Rbb666 | |
| 2026-08-12 | fix(dm): route Cortex-M resets through power core | Rbb666 | |
| 2026-08-12 | feat(dm): support OFW on Cortex-M targets | Rbb666 | |
| Add the ARM NVIC PIC driver, no-MMU I/O mapping, built-in FDT support, and Cortex-M CPU hooks required by the native RT-Thread device model. | |||
| 2026-06-02 | fix IAR build error | 蒙蒙plus | |
| 2026-05-19 | [libcpu][arm][cortex-m33] allows rewrite to interrupt enable/disable api to ↵ | Evlers | |
| support independent interrupts management | |||
| 2026-04-08 | feat(core): Add Cortex-M4 interrupt context helpers | wdfk-prog | |
| 2026-04-07 | fix(libcpu): correct arm mpu region validation precedence | AFWEF_147 | |
| 2026-04-07 | fix(libcpu): validate arm irq vectors before masking | AFWEF_147 | |
| 2026-04-03 | [docs][libcpu][arm][cortex-a] correct TLBIALL comments in start_gcc.S | laidene | |
| 2026-03-16 | feat(core): Add 8-bit and 16-bit atomic operation support | wdfk-prog | |
| 2026-03-15 | [libcpu][cortex-m7]Canonical alignment | wdfk-prog | |
| 2026-02-13 | chore: fix typo in components and libcpu | theqengineer | |
| 2026-01-10 | [libcpu][arm][cortex-a] Fixup mmu setup early | laidene | |
| Correct the starting virtual address of _reset alignment to 16MB | |||
| 2026-01-09 | Update libcpu/arm/cortex-a/gic.c | laidene | |
| 2026-01-09 | [docs][libcpu][arm][cortex-a] add comment for gic.c | laidene | |
| 2026-01-04 | [docs][libcpu][arm][cortex-a] add comment for mmu.h (#11104) | caicunjun | |
| * [docs][libcpu][arm][cortex-a] add comment for mmu.h * [docs][libcpu][arm][cortex-a] beautify comment for mmu.h * [docs][libcpu][arm][cortex-a] delete extra space at the end of lines | |||
| 2025-12-26 | [docs][libcpu][arm][cortex-a] update comment for start_gcc.S #11089 | caicunjun | |
| 2025-11-16 | Reorganize Group names in build system for clarity and IDE integration #10923 | Copilot | |
| 2025-11-12 | [libcpu][cortex-a] Refactor FPU stack initialization for maintainability ↵ | Copilot | |
| (#10919) * Initial plan * [libcpu][cortex-a] Improve FPU stack initialization implementation Co-authored-by: BernardXiong <[email protected]> * [libcpu][cortex-a] Replace FPU init loop with rt_memset Co-authored-by: BernardXiong <[email protected]> --------- Co-authored-by: copilot-swe-agent[bot] <[email protected]> Co-authored-by: BernardXiong <[email protected]> | |||
| 2025-11-07 | [Components] Remove vbus component and realview-a8-vmm libcpu (#10863) | Copilot | |
| * Initial plan * Remove vbus component and related code Co-authored-by: BernardXiong <[email protected]> --------- Co-authored-by: copilot-swe-agent[bot] <[email protected]> Co-authored-by: BernardXiong <[email protected]> | |||
| 2025-11-02 | [libcpu/arm/cortex-m33]: Fix incorrect CPU architecture in GCC context switch | Yucai Liu | |
| The context_gcc.S file was incorrectly marked as cortex-m4 in both the doxygen comment and .cpu directive, while the IAR and KEIL versions correctly specify cortex-m33. This file uses ARMv8-M specific features (PSPLIM register, TrustZone support) that are not available in Cortex-M4. Changes: - Update doxygen group from cortex-m4 to cortex-m33 - Change .cpu directive from cortex-m4 to cortex-m33 | |||
| 2025-10-11 | bsp/w60x: fixes cppcheck: (#10781) | Yonggang Luo | |
| [cpp_check.py 80 INFO] bsp/w60x/drivers/drv_rtc.c:58:11: error: Syntax Error: AST broken, binary operator '&=' doesn't have two operands. [internalAstError] [cpp_check.py 80 INFO] libcpu/arm/s3c24x0/rtc.c:34:12: error: Expression 'RTCCON|=RTCCON|=0x01' depends on order of evaluation of side effects [unknownEvaluationOrder] | |||
| 2025-10-10 | Remove rarely used rt_time_t | Yonggang Luo | |
| next_delay should be rt_tick_t Use time_t for RT_DEVICE_CTRL_RTC_GET_TIME | |||
| 2025-09-28 | fix:Fixed compilation error for libcpu/cortex-m4. (#10756) | R b b666 | |
| 2025-08-20 | [libcpu][cortex-m33]Added HardFault_Handler to save floating point registers | Rbb666 | |
| 2025-08-19 | [libcpu][cortex-m4]Added HardFault_Handler to save floating point registers. | Rbb666 | |
| 2025-08-19 | [libcpu ][cm3]The parameter passed to the unified rt_exception_hook is ↵ | R b b666 | |
| exception_stack. (#10619) | |||
| 2025-06-24 | libcpu/bsp: fix the M33 assembly syntax errors and fix the compilation error ↵ | kurisaw | |
| of bsp | |||
| 2025-04-11 | libcpu: cleanup undefined rt_hw_mmu_kernel_map_init (#10177) | Chen Wang | |
| * libcpu: cleanup undefined rt_hw_mmu_kernel_map_init rt_hw_mmu_kernel_map_init() is declared in header files but no definition found, cleanup the code. Signed-off-by: Chen Wang <[email protected]> * bsp: allwinner: d1: remove calling of rt_hw_mmu_kernel_map_init rt_hw_mmu_kernel_map_init is an undefined function, calling it is meaningless. Signed-off-by: Chen Wang <[email protected]> --------- Signed-off-by: Chen Wang <[email protected]> | |||
| 2025-03-18 | [bsp][stm32][artpi]:fix artpi nano (#10122) | CYFS | |
| 2025-03-17 | [fix]Fix cm33 compilation problem when block is turned on | Rbb666 | |
| 2025-01-08 | fix: add \n for addr2line hint | Meco Man | |
| 2024-12-04 | rzn2l-rsk support studio | kurisaw | |
| 2024-12-04 | [libcpu][drivers] cortex-r52 abnormal takeover and software rtc naming change | kurisaw | |
| 2024-11-20 | [DM/FIXUP] add cortex-m23's cpuport.h | GuEe-GUI | |
| Signed-off-by: GuEe-GUI <[email protected]> | |||
| 2024-11-06 | [libcpu][component] fixed the r52 kernel gcc context switch assembly | kurisaw | |
| 2024-10-23 | [kernel] Specification interrupt nested level variable declaration type (#9568) | Yuqiang Wang | |
| 2024-08-29 | add readme files | Evlers | |
| 2024-08-29 | [libcpu][arm][cortex-m4] allows rewrite to interrupt enable/disable api to ↵ | Evlers | |
| support independent interrupts management | |||
| 2024-07-11 | Correct ".cpu cortex-m4" to ".cpu cortex-m7" | childerxxx | |
| 2024-05-26 | [libcpu] discard rt_current_thread (#8976) | Shell | |
| * [libcpu] rv64: discard rt_current_thread * arm: using rt_thread_self to fetch current TCB | |||
| 2024-04-18 | [cpu_cache] fix function replaced by macro | wirano | |
| 2024-04-18 | [libcpu] remove .asm files in cortex-r52 | Meco Man | |
| 2024-04-18 | Delete unnecessary configurations in cortex-r52 | Rbb666 | |
| 2024-04-10 | [bsp][renesas]Add cortex-r52 rzt2m adaptation | Rbb666 | |
| 2024-03-29 | [bsp][art-pi-smart] 关闭内存对齐检查来避免数据访问异常 | liYangYang | |
| 2024-03-28 | sync smart & dfs (#8672) | Shell | |
| Signed-off-by: xqyjlj <[email protected]> Signed-off-by: Shell <[email protected]> Co-authored-by: xqyjlj <[email protected]> | |||
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index : rt-thread.git | |
| Unnamed repository; edit this file 'description' to name the repository. |
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