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Eight-core boot on SpacemiT K1 could stall with one CPU in the
unlock LR/SC loop, two CPUs allocating tickets, and the remaining
CPUs waiting for the scheduler lock.
Replace LR/SC ticket allocation with amoadd.w.aqrl and release the
lock with a halfword owner update. Order critical-section accesses
after acquiring ownership and before releasing it.
Verified eight-core boot on K1 with temporary diagnostics and
reservation-clearing changes removed.
Signed-off-by: GuEe-GUI <[email protected]>
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* [libcpu][risc-v] Refactor the RISC-V architecture port
Introduce an opt-in unified RISC-V common layer for RV32 and RV64 while keeping existing BSPs on the legacy implementation during migration.
- use ARCH_RISCV and ARCH_CPU_64BIT for architecture and XLEN selection
- unify context, trap, MMU, cache, timer, SBI, SMP and ISA handling
- add PLIC, CLIC, ACLINT, APLIC and IMSIC support
- map physical hart IDs to contiguous logical CPU IDs
- add T-Head vendor overrides while preserving legacy ports
- migrate qemu-virt64-riscv with RV32 and RV64 support
- update clock_time, MM, LWP, OFW, PCI and Rust integration
Existing BSPs continue using legacy_common or common64 unless they select RT_USING_RISCV_NEW_COMMON.
Signed-off-by: GuEe-GUI <[email protected]>
* [libcpu][risc-v] skip disabled CPU nodes in early FDT walk
Rbb666 noted that rt_hw_fdt_install_early() walked every /cpus child
without checking status, so disabled cores still joined hart registration
and MMU capability probing. Skip nodes that are not okay/ok via
rt_fdt_device_is_available() before reading reg or mmu-type.
Signed-off-by: seteiro <[email protected]>
* [libcpu][risc-v] Fix per-CPU page table mapping
- reuse existing non-leaf page table entries when mapping per-CPU areas
- reject leaf entry conflicts instead of overwriting mappings
Signed-off-by: GuEe-GUI <[email protected]>
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Signed-off-by: GuEe-GUI <[email protected]>
Signed-off-by: seteiro <[email protected]>
Co-authored-by: seteiro <[email protected]>
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Enable RT_USING_HW_STACK_GUARD on Cortex-M4, which was previously only
available on Cortex-M7 and Cortex-M33.
Core porting (libcpu/arm/cortex-m4/):
- Add mpu.c/mpu.h/mputype.h aligned with the Cortex-M7 MPU layer. The only
difference is the default memory type attribute: Cortex-M4 has no L1 cache,
so the cacheability bits are reduced to three cases.
- Add rt_hw_stack_guard_init() to cpuport.c.
- Add missing #include <rtconfig.h> to context_gcc.S and invoke
rt_hw_mpu_table_switch() in the PendSV context switch path.
- Update SConscript to exclude mpu.c when memory protection is disabled.
BSP reference (bsp/stm32/stm32f407-fk407m2-zgt6/):
- board.h: include rtthread.h and define NUM_STATIC_REGIONS.
- board.c: define static_regions[] marking the Flash region read-only,
guarded by RT_USING_MEM_PROTECTION so it is not enabled by default.
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- reorganize common Raspberry Pi drivers under the device framework
- add the Raspberry Pi 5 BSP, configuration and documentation
- add BCM2712 and DesignWare AXI DMA controller support
- distinguish BCM2712 DMA32 and DMA40 channels by channel mask
- restore DesignWare AXI DMA enable bits after controller reset
- support a shared AXI maximum burst length across DMA channels
Signed-off-by: GuEe-GUI <[email protected]>
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* [dm][dma] update DMA interface
Extend DMA mapping to honor OFW dma-ranges even
when no reserved memory pool is present,
and add PCI host-bridge DMA-region translation for PCI devices.
Prefer 32-bit-addressable allocations for translated devices,
improve pool allocation fallbacks and synchronization,
and establish a linear mapping for installed DMA pools when possible.
Signed-off-by: GuEe-GUI <[email protected]>
* [dm][dma] fixup PL330 work flow
Fix PL330 channel allocation so device-tree cells
select peripheral request lines rather than execution channels.
Generate proper peripheral DMA microcode using DMAWFP, DMALDP, DMASTP, and DMAFLUSHP,
encode burst lengths correctly,
honor transfer direction and non-secure attributes,
and allocate microcode from DMA-coherent memory.
Signed-off-by: GuEe-GUI <[email protected]>
* style: format code with clang-format
* style: format complete changed files with clang-format
* drivers: dma: fix diagnostic format types
* style: format DMA changes for current master
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Signed-off-by: GuEe-GUI <[email protected]>
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Add the ARM NVIC PIC driver, no-MMU I/O mapping, built-in FDT support, and Cortex-M CPU hooks required by the native RT-Thread device model.
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aspace with non-global PTE.
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Signed-off-by: GuEe-GUI <[email protected]>
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This is a builtin fdt example BSP
Signed-off-by: GuEe-GUI <[email protected]>
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support independent interrupts management
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- Implement _noncache() and _cache() function features;
- Correct rt_hw_mmu_setup function for NORMAL_NOCACHE_MEM type property configuration;
- Update C908/C906 PTE macro definition configuration;
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* [components][clock_time] Refactor time subsystem around clock_time
Introduce the clock_time core with clock source/event separation, high-resolution scheduling, and boot-time helpers, plus clock_timer adapters for timer peripherals.
Remove legacy ktime/cputime/hwtimer implementations and migrate arch and BSP time paths to the new subsystem while keeping POSIX time integration functional.
Update drivers, Kconfig/SConscript wiring, documentation, and tests; add clock_time overview docs and align naming to clock_boottime/clock_hrtimer/clock_timer.
* [components][clock_time] Use BSP-provided clock timer frequency on riscv64
* [risc-v] Use runtime clock timer frequency for tick and delays
* [bsp] Add clock timer frequency hooks for riscv64 boards
* [bsp] Update Renesas RA driver doc clock_timer link
* [bsp] Sync zynqmp-r5-axu4ev rtconfig after config refresh
* [bsp][rk3500] Update rk3500 clock configuration
* [bsp][hpmicro] Add rt_hw_us_delay hook and update board delays
* [bsp][stm32l496-st-nucleo] enable clock_time for hwtimer sample in ci
* [bsp][hpmicro] Fix rtconfig include scope for hpm6750evk
Move rtconfig.h include outside the ENET_MULTIPLE_PORT guard for hpm6750evk and hpm6750evk2 so configuration macros are available regardless of ENET settings.
* [bsp][raspi3] select clock time for systimer
* [bsp][hpm5300evk] Trim trailing blank line
* [bsp][hpm5301evklite] Trim trailing blank line
* [bsp][hpm5e00evk] Trim trailing blank line
* [bsp][hpm6200evk] Trim trailing blank line
* [bsp][hpm6300evk] Trim trailing blank line
* [bsp][hpm6750evk] Trim trailing blank line
* [bsp][hpm6750evk2] Trim trailing blank line
* [bsp][hpm6750evkmini] Trim trailing blank line
* [bsp][hpm6800evk] Trim trailing blank line
* [bsp][hpm6e00evk] Trim trailing blank line
* [bsp][nxp] switch lpc178x to gcc and remove mcx timer source
* [bsp][stm32] fix the CONFIG_RT_USING_CLOCK_TIME issue.
* [docs][clock_time] add clock time documentation
* [docs][clock_time] Update clock time subsystem documentation
- Update device driver index to use correct page reference
- Clarify upper layer responsibilities in architecture overview
- Update README to describe POSIX/libc, Soft RTC, and device driver usage
- Refine architecture diagram with improved layout and color scheme
- Remove obsolete clock_timer.md file
* [kernel][utest] Trim trailing space
* [clock_time] Fix hrtimer wrap handling
* [clock_time] fix the static rt_inline issue
* [clock_time] fix the rt_clock_hrtimer_control result issue
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definition with RT_USING_DM (#11100)
* Initial plan
* [risc-v][common64] Make rt_hw_cpu_shutdown weak to fix multiple definition error
Co-authored-by: BernardXiong <[email protected]>
---------
Co-authored-by: copilot-swe-agent[bot] <[email protected]>
Co-authored-by: BernardXiong <[email protected]>
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Correct the starting virtual address of _reset alignment to 16MB
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* [docs][libcpu][arm][cortex-a] add comment for mmu.h
* [docs][libcpu][arm][cortex-a] beautify comment for mmu.h
* [docs][libcpu][arm][cortex-a] delete extra space at the end of lines
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1. PSCI port to system power.
2. Support builtin fdt.
3. Update system aspace size.
4. Support DMA memory probe.
5. Fixup not backtrace in Serror for device bus fault.
Signed-off-by: GuEe-GUI <[email protected]>
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- allow overriding the isr numbers via RT_HW_ISR_NUM macro
Signed-off-by: Fan YANG <[email protected]>
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1.Add the necessary function declarations for SMP enablement and implement the corresponding
functionalities, including rt_hw_secondary_cpu_up, secondary_cpu_entry, rt_hw_local_irq_disable,
rt_hw_local_irq_enable, rt_hw_secondary_cpu_idle_exec, rt_hw_spin_lock_init, rt_hw_spin_lock,
rt_hw_spin_unlock, rt_hw_ipi_send, rt_hw_interrupt_set_priority, rt_hw_interrupt_get_priority,
rt_hw_ipi_init, rt_hw_ipi_handler_install, and rt_hw_ipi_handler.
2.In the two functions (rt_hw_context_switch_to and rt_hw_context_switch) in context_gcc.S,
add a call to rt_cpus_lock_status_restore to update the scheduler information.
3.If the MMU is enabled, use the .percpu section and record different hartids by configuring
special page tables; if the MMU is not enabled, record them directly in the satp register.
Additionally, add dynamic startup based on core configuration.The .percpu section is only used
when both ARCH_MM_MMU and RT_USING_SMP are enabled. However, there is a certain amount of space
waste since no macro guard is added for it in the link script currently.
4.The physical memory of QEMU started in CI is 128MB, so RT_HW_PAGE_END is modified from the
original +256MB to +128MB. Modify the SConscript file under the common64 directory to include
common/atomic_riscv.c in the compilation process.
Signed-off-by: Mengchen Teng <[email protected]>
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(#10919)
* Initial plan
* [libcpu][cortex-a] Improve FPU stack initialization implementation
Co-authored-by: BernardXiong <[email protected]>
* [libcpu][cortex-a] Replace FPU init loop with rt_memset
Co-authored-by: BernardXiong <[email protected]>
---------
Co-authored-by: copilot-swe-agent[bot] <[email protected]>
Co-authored-by: BernardXiong <[email protected]>
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* Initial plan
* Remove vbus component and related code
Co-authored-by: BernardXiong <[email protected]>
---------
Co-authored-by: copilot-swe-agent[bot] <[email protected]>
Co-authored-by: BernardXiong <[email protected]>
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The context_gcc.S file was incorrectly marked as cortex-m4 in both the
doxygen comment and .cpu directive, while the IAR and KEIL versions
correctly specify cortex-m33. This file uses ARMv8-M specific features
(PSPLIM register, TrustZone support) that are not available in Cortex-M4.
Changes:
- Update doxygen group from cortex-m4 to cortex-m33
- Change .cpu directive from cortex-m4 to cortex-m33
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Signed-off-by: Yonggang Luo <[email protected]>
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