1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
|
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2020-05-12 hqfang first version
*/
#include "drv_timer.h"
#ifdef BSP_USING_CLOCK_TIMER
#if !defined(BSP_USING_CLOCK_TIMER0) && !defined(BSP_USING_CLOCK_TIMER1) && !defined(BSP_USING_CLOCK_TIMER2) \
&& !defined(BSP_USING_CLOCK_TIMER3) && !defined(BSP_USING_CLOCK_TIMER4)
#error "Please define at least one BSP_USING_CLOCK_TIMERx"
/* this driver can be disabled at menuconfig -> Hardware Drivers Config -> On-chip Peripheral Drivers -> Enable CLOCK_TIMER */
#endif
static struct gd32_clock_timer_config clock_timer_config[] =
{
#ifdef BSP_USING_CLOCK_TIMER0
{
"timer0",
TIMER0,
TIMER0_UP_IRQn,
},
#endif
#ifdef BSP_USING_CLOCK_TIMER1
{
"timer1",
TIMER1,
TIMER1_IRQn,
},
#endif
#ifdef BSP_USING_CLOCK_TIMER2
{
"timer2",
TIMER2,
TIMER2_IRQn,
},
#endif
#ifdef BSP_USING_CLOCK_TIMER3
{
"timer3",
TIMER3,
TIMER3_IRQn,
},
#endif
#ifdef BSP_USING_CLOCK_TIMER4
{
"timer4",
TIMER4,
TIMER4_IRQn,
},
#endif
#ifdef BSP_USING_CLOCK_TIMER5
{
"timer5",
TIMER5,
TIMER5_IRQn,
},
#endif
#ifdef BSP_USING_CLOCK_TIMER6
{
"timer6",
TIMER6,
TIMER6_IRQn,
},
#endif
};
static struct gd32_clock_timer clock_timer_obj[sizeof(clock_timer_config) / sizeof(clock_timer_config[0])] = {0};
static rt_err_t gd32_clock_timer_control(rt_clock_timer_t *timer, rt_uint32_t cmd, void *args)
{
rt_err_t err = RT_EOK;
struct gd32_clock_timer_config *config;
RT_ASSERT(timer != RT_NULL);
config = (struct gd32_clock_timer_config *)timer->parent.user_data;
switch (cmd)
{
case CLOCK_TIMER_CTRL_FREQ_SET:
{
uint32_t clk;
uint8_t clkpre;
uint32_t pre;
if (config->timer_periph != TIMER0)
{
clk = rcu_clock_freq_get(CK_APB1);
clkpre = GET_BITS(RCU_CFG0, 8, 10);
}
else
{
clk = rcu_clock_freq_get(CK_APB2);
clkpre = GET_BITS(RCU_CFG0, 11, 13);
}
if (clkpre >= 4)
{
clk = clk * 2;
}
pre = (clk / * ((uint32_t *)args)) - 1;
TIMER_PSC(config->timer_periph) = (uint32_t)pre;
}
break;
case CLOCK_TIMER_CTRL_STOP:
timer_disable(config->timer_periph);
break;
default:
err = -RT_ENOSYS;
break;
}
return err;
}
static rt_uint32_t gd32_clock_timer_count_get(rt_clock_timer_t *timer)
{
rt_uint32_t CurrentTimer_Count;
struct gd32_clock_timer_config *config;
RT_ASSERT(timer != RT_NULL);
config = (struct gd32_clock_timer_config *)timer->parent.user_data;
CurrentTimer_Count = timer_counter_read(config->timer_periph);
return CurrentTimer_Count;
}
static void gd32_clock_timer_init(rt_clock_timer_t *timer, rt_uint32_t state)
{
struct gd32_clock_timer_config *config;
timer_parameter_struct initpara;
RT_ASSERT(timer != RT_NULL);
config = (struct gd32_clock_timer_config *)timer->parent.user_data;
if (state == 1)
{
timer_deinit(config->timer_periph);
timer_struct_para_init(&initpara);
timer_init(config->timer_periph, &initpara);
}
else
{
timer_disable(config->timer_periph);
timer_interrupt_enable(config->timer_periph, TIMER_INT_FLAG_UP);
ECLIC_DisableIRQ(config->irqn);
}
}
static rt_err_t gd32_clock_timer_start(rt_clock_timer_t *timer, rt_uint32_t cnt, rt_clock_timer_mode_t mode)
{
struct gd32_clock_timer_config *config;
RT_ASSERT(timer != RT_NULL);
config = (struct gd32_clock_timer_config *)timer->parent.user_data;
if (mode == CLOCK_TIMER_MODE_ONESHOT)
{
timer_single_pulse_mode_config(config->timer_periph, TIMER_SP_MODE_SINGLE);
}
else
{
timer_single_pulse_mode_config(config->timer_periph, TIMER_SP_MODE_REPETITIVE);
}
timer_counter_value_config(config->timer_periph, 0);
timer_autoreload_value_config(config->timer_periph, cnt);
timer_interrupt_enable(config->timer_periph, TIMER_INT_FLAG_UP);
timer_enable(config->timer_periph);
ECLIC_EnableIRQ(config->irqn);
return RT_EOK;
}
static void gd32_clock_timer_stop(rt_clock_timer_t *timer)
{
struct gd32_clock_timer_config *config;
RT_ASSERT(timer != RT_NULL);
config = (struct gd32_clock_timer_config *)timer->parent.user_data;
timer_disable(config->timer_periph);
ECLIC_DisableIRQ(config->irqn);
}
static const struct rt_clock_timer_ops gd32_clock_timer_ops =
{
.init = gd32_clock_timer_init,
.start = gd32_clock_timer_start,
.stop = gd32_clock_timer_stop,
.count_get = gd32_clock_timer_count_get,
.control = gd32_clock_timer_control,
};
static const struct rt_clock_timer_info gd32_clock_timer_info =
{
54000000, /* the maximum count frequency can be set */
1000, /* the minimum count frequency can be set */
0xFFFF,
CLOCK_TIMER_CNTMODE_UP,
};
#ifdef BSP_USING_CLOCK_TIMER0
void TIMER0_UP_IRQHandler(void)
{
timer_interrupt_flag_clear(clock_timer_obj[0].config->timer_periph, TIMER_INT_FLAG_UP);
rt_clock_timer_isr(&clock_timer_obj[0].time_device);
}
#endif
#ifdef BSP_USING_CLOCK_TIMER1
void TIMER1_IRQHandler(void)
{
timer_interrupt_flag_clear(clock_timer_obj[1].config->timer_periph, TIMER_INT_FLAG_UP);
rt_clock_timer_isr(&clock_timer_obj[1].time_device);
}
#endif
#ifdef BSP_USING_CLOCK_TIMER2
void TIMER2_IRQHandler(void)
{
timer_interrupt_flag_clear(clock_timer_obj[2].config->timer_periph, TIMER_INT_FLAG_UP);
rt_clock_timer_isr(&clock_timer_obj[2].time_device);
}
#endif
#ifdef BSP_USING_CLOCK_TIMER3
void TIMER3_IRQHandler(void)
{
timer_interrupt_flag_clear(clock_timer_obj[3].config->timer_periph, TIMER_INT_FLAG_UP);
rt_clock_timer_isr(&clock_timer_obj[3].time_device);
}
#endif
#ifdef BSP_USING_CLOCK_TIMER4
void TIMER4_IRQHandler(void)
{
timer_interrupt_flag_clear(clock_timer_obj[4].config->timer_periph, TIMER_INT_FLAG_UP);
rt_clock_timer_isr(&clock_timer_obj[4].time_device);
}
#endif
#ifdef BSP_USING_CLOCK_TIMER5
void TIMER5_IRQHandler(void)
{
timer_interrupt_flag_clear(clock_timer_obj[5].config->timer_periph, TIMER_INT_FLAG_UP);
rt_clock_timer_isr(&clock_timer_obj[5].time_device);
}
#endif
#ifdef BSP_USING_CLOCK_TIMER6
void TIMER6_IRQHandler(void)
{
timer_interrupt_flag_clear(clock_timer_obj[6].config->timer_periph, TIMER_INT_FLAG_UP);
rt_clock_timer_isr(&clock_timer_obj[6].time_device);
}
#endif
static int rt_clock_timer_init(void)
{
int i = 0;
int result = RT_EOK;
#ifdef BSP_USING_CLOCK_TIMER0
rcu_periph_clock_enable(RCU_TIMER0);
#endif
#ifdef BSP_USING_CLOCK_TIMER1
rcu_periph_clock_enable(RCU_TIMER1);
#endif
#ifdef BSP_USING_CLOCK_TIMER2
rcu_periph_clock_enable(RCU_TIMER2);
#endif
#ifdef BSP_USING_CLOCK_TIMER3
rcu_periph_clock_enable(RCU_TIMER3);
#endif
#ifdef BSP_USING_CLOCK_TIMER4
rcu_periph_clock_enable(RCU_TIMER4);
#endif
#ifdef BSP_USING_CLOCK_TIMER5
rcu_periph_clock_enable(RCU_TIMER5);
#endif
#ifdef BSP_USING_CLOCK_TIMER6
rcu_periph_clock_enable(RCU_TIMER6);
#endif
for (i = 0; i < sizeof(clock_timer_obj) / sizeof(clock_timer_obj[0]); i++)
{
clock_timer_obj[i].time_device.info = &gd32_clock_timer_info;
clock_timer_obj[i].time_device.ops = &gd32_clock_timer_ops;
clock_timer_obj[i].config = &clock_timer_config[i];
rt_clock_timer_register(&clock_timer_obj[i].time_device, \
clock_timer_obj[i].config->name, clock_timer_obj[i].config);
}
return result;
}
INIT_DEVICE_EXPORT(rt_clock_timer_init);
#endif /* RT_USING_CLOCK_TIME */
|
