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authorFrédéric Desbiens <[email protected]>2026-10-02 10:42:44 -0400
committerGitHub <[email protected]>2026-10-02 10:42:44 -0400
commit93387b0a60382a29579bbad5045c68328e3751df (patch)
tree42be790d602cb76f55090e5a7c418df7ea2b3428 /ports/risc-v32/gnu/src/tx_thread_context_save.S
parent44d7c95c582d415c4ad84527180b29c93c3bf664 (diff)
parent28281cd5647d4671236ca08d19bd18ed15b2265a (diff)
Merge pull request #783 from eclipse-threadx/devv6.5.2.202603_rel
Merged changes ahead of the v6.5.2.202603 release
Diffstat (limited to 'ports/risc-v32/gnu/src/tx_thread_context_save.S')
-rw-r--r--ports/risc-v32/gnu/src/tx_thread_context_save.S168
1 files changed, 66 insertions, 102 deletions
diff --git a/ports/risc-v32/gnu/src/tx_thread_context_save.S b/ports/risc-v32/gnu/src/tx_thread_context_save.S
index 0a0c0c15..e93d5870 100644
--- a/ports/risc-v32/gnu/src/tx_thread_context_save.S
+++ b/ports/risc-v32/gnu/src/tx_thread_context_save.S
@@ -1,5 +1,6 @@
/***************************************************************************
* Copyright (c) 2025 10xEngineers
+ * Copyright (c) 2026 Eclipse ThreadX contributors
*
* This program and the accompanying materials are made available under the
* terms of the MIT License which is available at
@@ -8,6 +9,7 @@
* SPDX-License-Identifier: MIT
**************************************************************************/
+// Portions of this file were generated with AI assistance.
/**************************************************************************/
/**************************************************************************/
@@ -20,6 +22,10 @@
/**************************************************************************/
.section .text
+
+#include "tx_port.h"
+ .equ TX_TRAP_FRAME_SIZE, TX_RISCV_TRAP_FRAME_SIZE
+
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
@@ -61,7 +67,7 @@ _tx_thread_context_save:
/* Upon entry to this routine, RA/x1 has been saved on the stack
and the stack has been already allocated for the entire context:
- addi sp, sp, -32*4 (or -65*4)
+ addi sp, sp, -TX_TRAP_FRAME_SIZE (400 with FP, 128 without)
sw ra, 28*4(sp)
*/
@@ -100,59 +106,34 @@ _tx_thread_context_save:
/* Save mstatus and skip FP state if FS is Off. */
csrr t0, mstatus
sw t0, 29*4(sp)
-#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double)
+#if defined(__riscv_float_abi_double)
srli t1, t0, 13
andi t1, t1, 0x3
beqz t1, _tx_thread_skip_fpu_save
-#endif
- /* Save floating point registers. */
-#if defined(__riscv_float_abi_single)
- fsw f0, 31*4(sp) // Store ft0
- fsw f1, 32*4(sp) // Store ft1
- fsw f2, 33*4(sp) // Store ft2
- fsw f3, 34*4(sp) // Store ft3
- fsw f4, 35*4(sp) // Store ft4
- fsw f5, 36*4(sp) // Store ft5
- fsw f6, 37*4(sp) // Store ft6
- fsw f7, 38*4(sp) // Store ft7
- fsw f10, 41*4(sp) // Store fa0
- fsw f11, 42*4(sp) // Store fa1
- fsw f12, 43*4(sp) // Store fa2
- fsw f13, 44*4(sp) // Store fa3
- fsw f14, 45*4(sp) // Store fa4
- fsw f15, 46*4(sp) // Store fa5
- fsw f16, 47*4(sp) // Store fa6
- fsw f17, 48*4(sp) // Store fa7
- fsw f28, 59*4(sp) // Store ft8
- fsw f29, 60*4(sp) // Store ft9
- fsw f30, 61*4(sp) // Store ft10
- fsw f31, 62*4(sp) // Store ft11
- csrr t0, fcsr
- sw t0, 63*4(sp) // Store fcsr
-#elif defined(__riscv_float_abi_double)
- fsd f0, 31*4(sp) // Store ft0
- fsd f1, 32*4(sp) // Store ft1
- fsd f2, 33*4(sp) // Store ft2
- fsd f3, 34*4(sp) // Store ft3
- fsd f4, 35*4(sp) // Store ft4
- fsd f5, 36*4(sp) // Store ft5
- fsd f6, 37*4(sp) // Store ft6
- fsd f7, 38*4(sp) // Store ft7
- fsd f10, 41*4(sp) // Store fa0
- fsd f11, 42*4(sp) // Store fa1
- fsd f12, 43*4(sp) // Store fa2
- fsd f13, 44*4(sp) // Store fa3
- fsd f14, 45*4(sp) // Store fa4
- fsd f15, 46*4(sp) // Store fa5
- fsd f16, 47*4(sp) // Store fa6
- fsd f17, 48*4(sp) // Store fa7
- fsd f28, 59*4(sp) // Store ft8
- fsd f29, 60*4(sp) // Store ft9
- fsd f30, 61*4(sp) // Store ft10
- fsd f31, 62*4(sp) // Store ft11
+ /* Save floating point registers (doubles at 128 + i*8). */
+ fsd f0, 16*8(sp) // Store ft0
+ fsd f1, 17*8(sp) // Store ft1
+ fsd f2, 18*8(sp) // Store ft2
+ fsd f3, 19*8(sp) // Store ft3
+ fsd f4, 20*8(sp) // Store ft4
+ fsd f5, 21*8(sp) // Store ft5
+ fsd f6, 22*8(sp) // Store ft6
+ fsd f7, 23*8(sp) // Store ft7
+ fsd f10, 26*8(sp) // Store fa0
+ fsd f11, 27*8(sp) // Store fa1
+ fsd f12, 28*8(sp) // Store fa2
+ fsd f13, 29*8(sp) // Store fa3
+ fsd f14, 30*8(sp) // Store fa4
+ fsd f15, 31*8(sp) // Store fa5
+ fsd f16, 32*8(sp) // Store fa6
+ fsd f17, 33*8(sp) // Store fa7
+ fsd f28, 44*8(sp) // Store ft8
+ fsd f29, 45*8(sp) // Store ft9
+ fsd f30, 46*8(sp) // Store ft10
+ fsd f31, 47*8(sp) // Store ft11
csrr t0, fcsr
- sw t0, 63*4(sp) // Store fcsr
+ sw t0, 96*4(sp) // Store fcsr
#endif
_tx_thread_skip_fpu_save:
@@ -173,7 +154,11 @@ _tx_thread_skip_fpu_save:
/* Call the ISR execution exit function if enabled. */
#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
+ addi sp, sp, -16 // Reserve space to save the return address
+ sw ra, 0(sp) // Save the return address
call _tx_execution_isr_enter // Call the ISR execution enter function
+ lw ra, 0(sp) // Recover the return address
+ addi sp, sp, 16 // Recover the reserved stack space
#endif
ret // Return to ISR
@@ -200,59 +185,34 @@ _tx_thread_nested_save:
/* Save mstatus and skip FP state if FS is Off. */
csrr t0, mstatus
sw t0, 29*4(sp)
-#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double)
+#if defined(__riscv_float_abi_double)
srli t1, t0, 13
andi t1, t1, 0x3
beqz t1, _tx_thread_skip_nested_fpu_save
-#endif
- /* Save floating point registers. */
-#if defined(__riscv_float_abi_single)
- fsw f0, 31*4(sp) // Store ft0
- fsw f1, 32*4(sp) // Store ft1
- fsw f2, 33*4(sp) // Store ft2
- fsw f3, 34*4(sp) // Store ft3
- fsw f4, 35*4(sp) // Store ft4
- fsw f5, 36*4(sp) // Store ft5
- fsw f6, 37*4(sp) // Store ft6
- fsw f7, 38*4(sp) // Store ft7
- fsw f10, 41*4(sp) // Store fa0
- fsw f11, 42*4(sp) // Store fa1
- fsw f12, 43*4(sp) // Store fa2
- fsw f13, 44*4(sp) // Store fa3
- fsw f14, 45*4(sp) // Store fa4
- fsw f15, 46*4(sp) // Store fa5
- fsw f16, 47*4(sp) // Store fa6
- fsw f17, 48*4(sp) // Store fa7
- fsw f28, 59*4(sp) // Store ft8
- fsw f29, 60*4(sp) // Store ft9
- fsw f30, 61*4(sp) // Store ft10
- fsw f31, 62*4(sp) // Store ft11
- csrr t0, fcsr
- sw t0, 63*4(sp) // Store fcsr
-#elif defined(__riscv_float_abi_double)
- fsd f0, 31*4(sp) // Store ft0
- fsd f1, 32*4(sp) // Store ft1
- fsd f2, 33*4(sp) // Store ft2
- fsd f3, 34*4(sp) // Store ft3
- fsd f4, 35*4(sp) // Store ft4
- fsd f5, 36*4(sp) // Store ft5
- fsd f6, 37*4(sp) // Store ft6
- fsd f7, 38*4(sp) // Store ft7
- fsd f10, 41*4(sp) // Store fa0
- fsd f11, 42*4(sp) // Store fa1
- fsd f12, 43*4(sp) // Store fa2
- fsd f13, 44*4(sp) // Store fa3
- fsd f14, 45*4(sp) // Store fa4
- fsd f15, 46*4(sp) // Store fa5
- fsd f16, 47*4(sp) // Store fa6
- fsd f17, 48*4(sp) // Store fa7
- fsd f28, 59*4(sp) // Store ft8
- fsd f29, 60*4(sp) // Store ft9
- fsd f30, 61*4(sp) // Store ft10
- fsd f31, 62*4(sp) // Store ft11
+ /* Save floating point registers (doubles at 128 + i*8). */
+ fsd f0, 16*8(sp) // Store ft0
+ fsd f1, 17*8(sp) // Store ft1
+ fsd f2, 18*8(sp) // Store ft2
+ fsd f3, 19*8(sp) // Store ft3
+ fsd f4, 20*8(sp) // Store ft4
+ fsd f5, 21*8(sp) // Store ft5
+ fsd f6, 22*8(sp) // Store ft6
+ fsd f7, 23*8(sp) // Store ft7
+ fsd f10, 26*8(sp) // Store fa0
+ fsd f11, 27*8(sp) // Store fa1
+ fsd f12, 28*8(sp) // Store fa2
+ fsd f13, 29*8(sp) // Store fa3
+ fsd f14, 30*8(sp) // Store fa4
+ fsd f15, 31*8(sp) // Store fa5
+ fsd f16, 32*8(sp) // Store fa6
+ fsd f17, 33*8(sp) // Store fa7
+ fsd f28, 44*8(sp) // Store ft8
+ fsd f29, 45*8(sp) // Store ft9
+ fsd f30, 46*8(sp) // Store ft10
+ fsd f31, 47*8(sp) // Store ft11
csrr t0, fcsr
- sw t0, 63*4(sp) // Store fcsr
+ sw t0, 96*4(sp) // Store fcsr
#endif
_tx_thread_skip_nested_fpu_save:
@@ -261,7 +221,11 @@ _tx_thread_skip_nested_fpu_save:
/* Call the ISR execution exit function if enabled. */
#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
+ addi sp, sp, -16 // Reserve space to save the return address
+ sw ra, 0(sp) // Save the return address
call _tx_execution_isr_enter // Call the ISR execution enter function
+ lw ra, 0(sp) // Recover the return address
+ addi sp, sp, 16 // Recover the reserved stack space
#endif
ret // Return to ISR
@@ -270,16 +234,16 @@ _tx_thread_idle_system_save:
#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
+ addi sp, sp, -16 // Reserve space to save the return address
+ sw ra, 0(sp) // Save the return address
call _tx_execution_isr_enter // Call the ISR execution enter function
+ lw ra, 0(sp) // Recover the return address
+ addi sp, sp, 16 // Recover the reserved stack space
#endif
/* Interrupt occurred in the scheduling loop. */
/* }
} */
-#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double)
- addi sp, sp, 65*4 // Recover stack frame - with floating point enabled
-#else
- addi sp, sp, 32*4 // Recover the reserved stack space
-#endif
+ addi sp, sp, TX_TRAP_FRAME_SIZE // Recover the reserved stack space
ret // Return to calling ISR
generated by cgit v1.3.1 (git 2.54.0) at 2026-10-23 23:34:55 +0000