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authorXiuwen Cai <[email protected]>2023-12-28 13:17:58 +0800
committerGitHub <[email protected]>2023-12-28 13:17:58 +0800
commit39f3c86c61ec478720bac9fca8f17ccedb8f052b (patch)
tree9e8260b4b5fc1bb056675510fb765c2e063fd33e /ports
parent9f3e35d3dcacfac3eed6df8fb8cc6ed9a5a680d5 (diff)
Add error handling in lock initialization in the Xtensa port (#340)v6.4.0_rel
* Add error handling in lock initialization. * Update release data and version.
Diffstat (limited to 'ports')
-rw-r--r--ports/xtensa/xcc/src/tx_clib_lock.c6
1 files changed, 6 insertions, 0 deletions
diff --git a/ports/xtensa/xcc/src/tx_clib_lock.c b/ports/xtensa/xcc/src/tx_clib_lock.c
index 072cbd52..b95bf12b 100644
--- a/ports/xtensa/xcc/src/tx_clib_lock.c
+++ b/ports/xtensa/xcc/src/tx_clib_lock.c
@@ -35,6 +35,10 @@
/* DATE NAME DESCRIPTION */
/* */
/* 12-31-2020 Cadence Design Systems Initial Version 6.1.3 */
+/* 12-31-2023 Xiuwen Cai Modified comment(s), and */
+/* added error handling in */
+/* lock initialization, */
+/* resulting in version 6.4.0 */
/* */
/**************************************************************************/
@@ -155,6 +159,8 @@ _Mtxinit (_Rmtx * mtx)
if (lcnt >= XT_NUM_CLIB_LOCKS) {
/* Fatal error */
+ *mtx = NULL;
+ return;
}
lock = &(xclib_locks[lcnt]);