diff options
| author | Tiejun Zhou <[email protected]> | 2023-03-08 08:26:22 +0000 |
|---|---|---|
| committer | Tiejun Zhou <[email protected]> | 2023-03-08 08:26:22 +0000 |
| commit | 2aa19f3de0b6cf09bb9dca78c8a53fe337b8f0f7 (patch) | |
| tree | 8ec91a64e0831e3100a6ad9a5dec41d9fd7fc74f /ports_module/cortex_a7/iar | |
| parent | 745395d6a2f931c85c4428425db21eb7d03b4324 (diff) | |
Release 6.2.1 on 08 Mar 2023. Expand to see details.v6.2.1_rel
cee19603d Include tx_user.h conditionally.
e40e08007 Update owners
d69641273 Update release date and version
394aee52f Add tx_user.h to GNU port assembly files
5cca2ddd0 RISC-V 64 bit port for Microchip
e0f2c373c Link Winmm.lib that required by the high-resolution timer.
6af472a68 Update Win32 port with high resolution timer.
aea7b556a Add DMB ISH barrier inst in ARMv8-A SMP scheduler
19091a262 Add .section .preamble to m3 m4 m7 module ports
ced60e1b7 Add missing parenthesis in ports assembly file
309dc77ca Modules Cortex-A7 IAR new port
c752a4063 Modules Cortex-A7 GNU new port
dc224b90f Fix race condition in tx_thread_wait_abort and update regression test
6e261f5b7 create threadx cmsis-pack
Diffstat (limited to 'ports_module/cortex_a7/iar')
48 files changed, 35434 insertions, 0 deletions
diff --git a/ports_module/cortex_a7/iar/example_build/azure_rtos.eww b/ports_module/cortex_a7/iar/example_build/azure_rtos.eww new file mode 100644 index 00000000..a8dd1c9e --- /dev/null +++ b/ports_module/cortex_a7/iar/example_build/azure_rtos.eww @@ -0,0 +1,19 @@ +<?xml version="1.0" encoding="UTF-8"?> +<workspace> + <project> + <path>$WS_DIR$\sample_threadx.ewp</path> + </project> + <project> + <path>$WS_DIR$\sample_threadx_module.ewp</path> + </project> + <project> + <path>$WS_DIR$\sample_threadx_module_manager.ewp</path> + </project> + <project> + <path>$WS_DIR$\tx.ewp</path> + </project> + <project> + <path>$WS_DIR$\txm.ewp</path> + </project> + <batchBuild /> +</workspace> diff --git a/ports_module/cortex_a7/iar/example_build/cstartup.s b/ports_module/cortex_a7/iar/example_build/cstartup.s new file mode 100644 index 00000000..329decce --- /dev/null +++ b/ports_module/cortex_a7/iar/example_build/cstartup.s @@ -0,0 +1,156 @@ + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Part one of the system initialization code, +;; contains low-level +;; initialization. +;; +;; Copyright 2007 IAR Systems. All rights reserved. +;; +;; $Revision: 14520 $ +;; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION IRQ_STACK:DATA:NOROOT(3) + SECTION FIQ_STACK:DATA:NOROOT(3) + SECTION CSTACK:DATA:NOROOT(3) + +; +; The module in this file are included in the libraries, and may be +; replaced by any user-defined modules that define the PUBLIC symbol +; __iar_program_start or a user defined start symbol. +; +; To override the cstartup defined in the library, simply add your +; modified version to the workbench project. + + SECTION .intvec:CODE:NOROOT(2) + + PUBLIC __vector + PUBLIC __vector_0x14 + PUBLIC __iar_program_start + EXTERN __tx_undefined + EXTERN SWI_Handler + EXTERN __tx_prefetch_handler + EXTERN __tx_abort_handler + EXTERN __tx_irq_handler + EXTERN __tx_fiq_handler + + ARM +__vector: + ; All default exception handlers (except reset) are + ; defined as weak symbol definitions. + ; If a handler is defined by the application it will take precedence. + LDR PC,Reset_Addr ; Reset + LDR PC,Undefined_Addr ; Undefined instructions + LDR PC,SWI_Addr ; Software interrupt (SWI/SVC) + LDR PC,Prefetch_Addr ; Prefetch abort + LDR PC,Abort_Addr ; Data abort +__vector_0x14: + DCD 0 ; RESERVED + LDR PC,IRQ_Addr ; IRQ + LDR PC,FIQ_Addr ; FIQ + +Reset_Addr: DCD __iar_program_start +Undefined_Addr: DCD __tx_undefined +SWI_Addr: DCD SWI_Handler +Prefetch_Addr: DCD __tx_prefetch_handler +Abort_Addr: DCD __tx_abort_handler +IRQ_Addr: DCD __tx_irq_handler +FIQ_Addr: DCD __tx_fiq_handler + +; -------------------------------------------------- +; ?cstartup -- low-level system initialization code. +; +; After a reser execution starts here, the mode is ARM, supervisor +; with interrupts disabled. +; + + + + SECTION .text:CODE:NOROOT(2) + +; PUBLIC ?cstartup + EXTERN ?main + REQUIRE __vector + + ARM + +__iar_program_start: +?cstartup: + +; +; Add initialization needed before setup of stackpointers here. +; + +; +; Initialize the stack pointers. +; The pattern below can be used for any of the exception stacks: +; FIQ, IRQ, SVC, ABT, UND, SYS. +; The USR mode uses the same stack as SYS. +; The stack segments must be defined in the linker command file, +; and be declared above. +; + + +; -------------------- +; Mode, correspords to bits 0-5 in CPSR + +MODE_MSK DEFINE 0x1F ; Bit mask for mode bits in CPSR + +USR_MODE DEFINE 0x10 ; User mode +FIQ_MODE DEFINE 0x11 ; Fast Interrupt Request mode +IRQ_MODE DEFINE 0x12 ; Interrupt Request mode +SVC_MODE DEFINE 0x13 ; Supervisor mode +ABT_MODE DEFINE 0x17 ; Abort mode +UND_MODE DEFINE 0x1B ; Undefined Instruction mode +SYS_MODE DEFINE 0x1F ; System mode + + + MRS r0, cpsr ; Original PSR value + + ;; Set up the interrupt stack pointer. + + BIC r0, r0, #MODE_MSK ; Clear the mode bits + ORR r0, r0, #IRQ_MODE ; Set IRQ mode bits + MSR cpsr_c, r0 ; Change the mode + LDR sp, =SFE(IRQ_STACK) ; End of IRQ_STACK + + ;; Set up the fast interrupt stack pointer. + + BIC r0, r0, #MODE_MSK ; Clear the mode bits + ORR r0, r0, #FIQ_MODE ; Set FIR mode bits + MSR cpsr_c, r0 ; Change the mode + LDR sp, =SFE(FIQ_STACK) ; End of FIQ_STACK + + ;; Set up the normal stack pointer. + + BIC r0 ,r0, #MODE_MSK ; Clear the mode bits + ORR r0 ,r0, #SYS_MODE ; Set System mode bits + MSR cpsr_c, r0 ; Change the mode + LDR sp, =SFE(CSTACK) ; End of CSTACK + +#ifdef __ARMVFP__ + MRC p15, 0, r1, c1, c0, 2 ; r1 = Access Control Register + ORR r1, r1, #(0xf << 20) ; Enable full access for p10,11 + MCR p15, 0, r1, c1, c0, 2 ; Access Control Register = r1 + MOV r1, #0 + MCR p15, 0, r1, c7, c5, 4 ; Flush prefetch buffer because of FMXR below and + ; CP 10 & 11 were only just enabled + MOV r0, #0x40000000 ; Enable VFP itself + FMXR FPEXC, r0 ; FPEXC = r0 +#endif + +; +; Add more initialization here +; + +; Continue to ?main for C-level initialization. + + B ?main + + END + + + diff --git a/ports_module/cortex_a7/iar/example_build/sample_threadx.c b/ports_module/cortex_a7/iar/example_build/sample_threadx.c new file mode 100644 index 00000000..983109cc --- /dev/null +++ b/ports_module/cortex_a7/iar/example_build/sample_threadx.c @@ -0,0 +1,376 @@ +/* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight + threads of different priorities, using a message queue, semaphore, mutex, event flags group, + byte pool, and block pool. */ + +#include "tx_api.h" + +#define DEMO_STACK_SIZE 1024 +#define DEMO_BYTE_POOL_SIZE 9120 +#define DEMO_BLOCK_POOL_SIZE 100 +#define DEMO_QUEUE_SIZE 100 + + +/* Define the ThreadX object control blocks... */ + +TX_THREAD thread_0; +TX_THREAD thread_1; +TX_THREAD thread_2; +TX_THREAD thread_3; +TX_THREAD thread_4; +TX_THREAD thread_5; +TX_THREAD thread_6; +TX_THREAD thread_7; +TX_QUEUE queue_0; +TX_SEMAPHORE semaphore_0; +TX_MUTEX mutex_0; +TX_EVENT_FLAGS_GROUP event_flags_0; +TX_BYTE_POOL byte_pool_0; +TX_BLOCK_POOL block_pool_0; + + + +/* Define byte pool memory. */ + +UCHAR byte_pool_memory[DEMO_BYTE_POOL_SIZE]; + + + +/* Define the counters used in the demo application... */ + +ULONG thread_0_counter; +ULONG thread_1_counter; +ULONG thread_1_messages_sent; +ULONG thread_2_counter; +ULONG thread_2_messages_received; +ULONG thread_3_counter; +ULONG thread_4_counter; +ULONG thread_5_counter; +ULONG thread_6_counter; +ULONG thread_7_counter; + + +/* Define thread prototypes. */ + +void thread_0_entry(ULONG thread_input); +void thread_1_entry(ULONG thread_input); +void thread_2_entry(ULONG thread_input); +void thread_3_and_4_entry(ULONG thread_input); +void thread_5_entry(ULONG thread_input); +void thread_6_and_7_entry(ULONG thread_input); + + +/* Define main entry point. */ + +int main() +{ + + /* Enter the ThreadX kernel. */ + tx_kernel_enter(); +} + + +/* Define what the initial system looks like. */ + +void tx_application_define(void *first_unused_memory) +{ + +CHAR *pointer = TX_NULL; + + + /* Create a byte memory pool from which to allocate the thread stacks. */ + tx_byte_pool_create(&byte_pool_0, "byte pool 0", byte_pool_memory, DEMO_BYTE_POOL_SIZE); + + /* Put system definition stuff in here, e.g. thread creates and other assorted + create information. */ + + /* Allocate the stack for thread 0. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create the main thread. */ + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, + 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); + + + /* Allocate the stack for thread 1. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 1 and 2. These threads pass information through a ThreadX + message queue. It is also interesting to note that these threads have a time + slice. */ + tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 2. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 3. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + An interesting thing here is that both threads share the same instruction area. */ + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 4. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 5. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create thread 5. This thread simply pends on an event flag which will be set + by thread_0. */ + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, + 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 6. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 7. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the message queue. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_QUEUE_SIZE*sizeof(ULONG), TX_NO_WAIT); + + /* Create the message queue shared by threads 1 and 2. */ + tx_queue_create(&queue_0, "queue 0", TX_1_ULONG, pointer, DEMO_QUEUE_SIZE*sizeof(ULONG)); + + /* Create the semaphore used by threads 3 and 4. */ + tx_semaphore_create(&semaphore_0, "semaphore 0", 1); + + /* Create the event flags group used by threads 1 and 5. */ + tx_event_flags_create(&event_flags_0, "event flags 0"); + + /* Create the mutex used by thread 6 and 7 without priority inheritance. */ + tx_mutex_create(&mutex_0, "mutex 0", TX_NO_INHERIT); + + /* Allocate the memory for a small block pool. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_BLOCK_POOL_SIZE, TX_NO_WAIT); + + /* Create a block memory pool to allocate a message buffer from. */ + tx_block_pool_create(&block_pool_0, "block pool 0", sizeof(ULONG), pointer, DEMO_BLOCK_POOL_SIZE); + + /* Allocate a block and release the block memory. */ + tx_block_allocate(&block_pool_0, (VOID **) &pointer, TX_NO_WAIT); + + /* Release the block back to the pool. */ + tx_block_release(pointer); +} + + + +/* Define the test threads. */ + +void thread_0_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sits in while-forever-sleep loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_0_counter++; + + /* Sleep for 10 ticks. */ + tx_thread_sleep(10); + + /* Set event flag 0 to wakeup thread 5. */ + status = tx_event_flags_set(&event_flags_0, 0x1, TX_OR); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_1_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sends messages to a queue shared by thread 2. */ + while(1) + { + + /* Increment the thread counter. */ + thread_1_counter++; + + /* Send message to queue 0. */ + status = tx_queue_send(&queue_0, &thread_1_messages_sent, TX_WAIT_FOREVER); + + /* Check completion status. */ + if (status != TX_SUCCESS) + break; + + /* Increment the message sent. */ + thread_1_messages_sent++; + } +} + + +void thread_2_entry(ULONG thread_input) +{ + +ULONG received_message; +UINT status; + + /* This thread retrieves messages placed on the queue by thread 1. */ + while(1) + { + + /* Increment the thread counter. */ + thread_2_counter++; + + /* Retrieve a message from the queue. */ + status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); + + /* Check completion status and make sure the message is what we + expected. */ + if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) + break; + + /* Otherwise, all is okay. Increment the received message count. */ + thread_2_messages_received++; + } +} + + +void thread_3_and_4_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 3 and thread 4. As the loop + below shows, these function compete for ownership of semaphore_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 3) + thread_3_counter++; + else + thread_4_counter++; + + /* Get the semaphore with suspension. */ + status = tx_semaphore_get(&semaphore_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the semaphore. */ + tx_thread_sleep(2); + + /* Release the semaphore. */ + status = tx_semaphore_put(&semaphore_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_5_entry(ULONG thread_input) +{ + +UINT status; +ULONG actual_flags; + + + /* This thread simply waits for an event in a forever loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_5_counter++; + + /* Wait for event flag 0. */ + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + &actual_flags, TX_WAIT_FOREVER); + + /* Check status. */ + if ((status != TX_SUCCESS) || (actual_flags != 0x1)) + break; + } +} + + +void thread_6_and_7_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 6 and thread 7. As the loop + below shows, these function compete for ownership of mutex_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 6) + thread_6_counter++; + else + thread_7_counter++; + + /* Get the mutex with suspension. */ + status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Get the mutex again with suspension. This shows + that an owning thread may retrieve the mutex it + owns multiple times. */ + status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the mutex. */ + tx_thread_sleep(2); + + /* Release the mutex. */ + status = tx_mutex_put(&mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Release the mutex again. This will actually + release ownership since it was obtained twice. */ + status = tx_mutex_put(&mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} diff --git a/ports_module/cortex_a7/iar/example_build/sample_threadx.ewd b/ports_module/cortex_a7/iar/example_build/sample_threadx.ewd new file mode 100644 index 00000000..579e4443 --- /dev/null +++ b/ports_module/cortex_a7/iar/example_build/sample_threadx.ewd @@ -0,0 +1,3088 @@ +<?xml version="1.0" encoding="UTF-8"?> +<project> + <fileVersion>3</fileVersion> + <configuration> + <name>Debug</name> + <toolchain> + <name>ARM</name> + </toolchain> + <debug>1</debug> + <settings> + <name>C-SPY</name> + <archiveVersion>2</archiveVersion> + <data> + <version>32</version> + <wantNonLocal>1</wantNonLocal> + <debug>1</debug> + <option> + <name>CInput</name> + <state>1</state> + </option> + <option> + <name>CEndian</name> + <state>1</state> + </option> + <option> + <name>CProcessor</name> + <state>1</state> + </option> + <option> + <name>OCVariant</name> + <state>0</state> + </option> + <option> + <name>MacOverride</name> + <state>0</state> + </option> + <option> + <name>MacFile</name> + <state></state> + </option> + <option> + <name>MemOverride</name> + <state>0</state> + </option> + <option> + <name>MemFile</name> + <state>$TOOLKIT_DIR$\CONFIG\debugger\TexasInstruments\RM48L530PGE.ddf</state> + </option> + <option> + <name>RunToEnable</name> + <state>0</state> + </option> + <option> + <name>RunToName</name> + <state>main</state> + </option> + <option> + <name>CExtraOptionsCheck</name> + <state>0</state> + </option> + <option> + <name>CExtraOptions</name> + <state></state> + </option> + <option> + <name>CFpuProcessor</name> + <state>1</state> + </option> + <option> + <name>OCDDFArgumentProducer</name> + <state></state> + </option> + <option> + <name>OCDownloadSuppressDownload</name> + <state>0</state> + </option> + <option> + <name>OCDownloadVerifyAll</name> + <state>1</state> + </option> + <option> + <name>OCProductVersion</name> + <state>4.11A</state> + </option> + <option> + <name>OCDynDriverList</name> + <state>ARMSIM_ID</state> + </option> + <option> + <name>OCLastSavedByProductVersion</name> + <state>9.20.4.46976</state> + </option> + <option> + <name>UseFlashLoader</name> + <state>1</state> + </option> + <option> + <name>CLowLevel</name> + <state>1</state> + </option> + <option> + <name>OCBE8Slave</name> + <state>1</state> + </option> + <option> + <name>MacFile2</name> + <state></state> + </option> + <option> + <name>CDevice</name> + <state>1</state> + </option> + <option> + <name>FlashLoadersV3</name> + <state>$TOOLKIT_DIR$\config\flashloader\TexasInstruments\FlashRM48L550.board</state> + </option> + <option> + <name>OCImagesSuppressCheck1</name> + <state>0</state> + </option> + <option> + <name>OCImagesPath1</name> + <state></state> + </option> + <option> + <name>OCImagesSuppressCheck2</name> + <state>0</state> + </option> + <option> + <name>OCImagesPath2</name> + <state></state> + </option> + <option> + <name>OCImagesSuppressCheck3</name> + <state>0</state> + </option> + <option> + <name>OCImagesPath3</name> + <state></state> + </option> + <option> + <name>OverrideDefFlashBoard</name> + <state>0</state> + </option> + <option> + <name>OCImagesOffset1</name> + <state></state> + </option> + <option> + <name>OCImagesOffset2</name> + <state></state> + </option> + <option> + <name>OCImagesOffset3</name> + <state></state> + </option> + <option> + <name>OCImagesUse1</name> + <state>0</state> + </option> + <option> + <name>OCImagesUse2</name> + <state>0</state> + </option> + <option> + <name>OCImagesUse3</name> + <state>0</state> + </option> + <option> + <name>OCDeviceConfigMacroFile</name> + <state>1</state> + </option> + <option> + <name>OCDebuggerExtraOption</name> + <state>1</state> + </option> + <option> + <name>OCAllMTBOptions</name> + <state>1</state> + </option> + <option> + <name>OCMulticoreNrOfCores</name> + <state>1</state> + </option> + <option> + <name>OCMulticoreWorkspace</name> + <state></state> + </option> + <option> + <name>OCMulticoreSlaveProject</name> + <state></state> + </option> + <option> + <name>OCMulticoreSlaveConfiguration</name> + <state></state> + </option> + <option> + <name>OCDownloadExtraImage</name> + <state>1</state> + </option> + <option> + <name>OCAttachSlave</name> + <state>0</state> + </option> + <option> + <name>MassEraseBeforeFlashing</name> + <state>0</state> + </option> + <option> + <name>OCMulticoreNrOfCoresSlave</name> + <state>1</state> + </option> + <option> + <name>OCMulticoreAMPConfigType</name> + <state>0</state> + </option> + <option> + <name>OCMulticoreSessionFile</name> + <state></state> + </option> + <option> + <name>OCTpiuBaseOption</name> + <state>1</state> + </option> + </data> + </settings> + <settings> + <name>ARMSIM_ID</name> + <archiveVersion>2</archiveVersion> + <data> + <version>1</version> + <wantNonLocal>1</wantNonLocal> + <debug>1</debug> + <option> + <name>OCSimDriverInfo</name> + <state>1</state> + </option> + <option> + <name>OCSimEnablePSP</name> + <state>0</state> + </option> + <option> + <name>OCSimPspOverrideConfig</name> + <state>0</state> + </option> + <option> + <name>OCSimPspConfigFile</name> + <state></state> + </option> + </data> + </settings> + <settings> + <name>CADI_ID</name> + <archiveVersion>2</archiveVersion> + <data> + <version>0</version> + <wantNonLocal>1</wantNonLocal> + <debug>1</debug> + <option> + <name>CCadiMemory</name> + <state>1</state> + </option> + <option> + <name>Fast Model</name> + <state></state> + </option> + <option> + <name>CCADILogFileCheck</name> + <state>0</state> + </option> + <option> + <name>CCADILogFileEditB</name> + <state>$PROJ_DIR$\cspycomm.log</state> + </option> + <option> + <name>OCDriverInfo</name> + <state>1</state> + </option> + </data> + </settings> + <settings> + <name>CMSISDAP_ID</name> + <archiveVersion>2</archiveVersion> + <data> + <version>4</version> + <wantNonLocal>1</wantNonLocal> + <debug>1</debug> + <option> + <name>OCDriverInfo</name> + <state>1</state> + </option> + <option> + <name>OCIarProbeScriptFile</name> + <state>1</state> + </option> + <option> + <name>CMSISDAPResetList</name> + <version>1</version> + <state>10</state> + </option> + <option> + <name>CMSISDAPHWResetDuration</name> + <state>300</state> + </option> + <option> + <name>CMSISDAPHWResetDelay</name> + <state>200</state> + </option> + <option> + <name>CMSISDAPDoLogfile</name> + <state>0</state> + </option> + <option> + <name>CMSISDAPLogFile</name> + <state>$PROJ_DIR$\cspycomm.log</state> + </option> + <option> + <name>CMSISDAPInterfaceRadio</name> + <state>0</state> + </option> + <option> + <name>CMSISDAPInterfaceCmdLine</name> + <state>0</state> + </option> + <option> + <name>CMSISDAPMultiTargetEnable</name> + <state>0</state> + </option> + <option> + <name>CMSISDAPMultiTarget</name> + <state>0</state> + </option> + <option> + <name>CMSISDAPJtagSpeedList</name> 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<name>CCIjetUsbSerialNo</name> + <state></state> + </option> + <option> + <name>CCIjetUsbSerialNoSelect</name> + <state>0</state> + </option> + <option> + <name>CatchV8ARReset</name> + <state>0</state> + </option> + <option> + <name>CatchV8AREREL1NS</name> + <state>0</state> + </option> + <option> + <name>CatchV8AREREL1S</name> + <state>0</state> + </option> + <option> + <name>CatchV8AREREL2NS</name> + <state>0</state> + </option> + <option> + <name>CatchV8AREREL3S</name> + <state>0</state> + </option> + <option> + <name>CatchV8AREEL1NS</name> + <state>0</state> + </option> + <option> + <name>CatchV8ARREL1NS</name> + <state>0</state> + </option> + <option> + <name>CatchV8AREEL1S</name> + <state>0</state> + </option> + <option> + <name>CatchV8ARREL1S</name> + <state>0</state> + </option> + <option> + <name>CatchV8AREEL2NS</name> + <state>0</state> + </option> + <option> + <name>CatchV8ARREL2NS</name> + <state>0</state> + </option> + <option> + <name>CatchV8AREEL3S</name> + <state>0</state> + </option> + <option> + <name>CatchV8ARREL3S</name> + <state>0</state> + </option> + </data> + </settings> + <settings> + <name>JLINK_ID</name> + <archiveVersion>2</archiveVersion> + <data> + <version>16</version> + <wantNonLocal>1</wantNonLocal> + <debug>0</debug> + <option> + <name>CCCatchSFERR</name> + <state>0</state> + </option> + <option> + <name>JLinkSpeed</name> + <state></state> + </option> + <option> + <name>CCJLinkDoLogfile</name> + <state>0</state> + </option> + <option> + <name>CCJLinkLogFile</name> + <state>$TOOLKIT_DIR$\cspycomm.log</state> + </option> + <option> + <name>CCJLinkHWResetDelay</name> + <state></state> + </option> + <option> + <name>OCDriverInfo</name> + <state>1</state> + </option> + <option> + <name>JLinkInitialSpeed</name> + <state>32</state> + </option> + <option> + <name>CCDoJlinkMultiTarget</name> + <state>0</state> + </option> + <option> + <name>CCScanChainNonARMDevices</name> + <state>0</state> + </option> + <option> + <name>CCJLinkMultiTarget</name> + <state>0</state> + </option> + <option> + <name>CCJLinkIRLength</name> + <state>0</state> + </option> + <option> + <name>CCJLinkCommRadio</name> + <state>0</state> + </option> + <option> + <name>CCJLinkTCPIP</name> + <state>aaa.bbb.ccc.ddd</state> + </option> + <option> + <name>CCJLinkSpeedRadioV2</name> + <state>0</state> + </option> + <option> + <name>CCUSBDevice</name> + <version>1</version> + <state>1</state> + </option> + <option> + <name>CCRDICatchReset</name> + <state>0</state> + </option> + <option> + <name>CCRDICatchUndef</name> + <state>0</state> + </option> + <option> + <name>CCRDICatchSWI</name> + <state>0</state> + </option> + <option> + <name>CCRDICatchData</name> + <state>0</state> + </option> + <option> + <name>CCRDICatchPrefetch</name> + <state>0</state> + </option> + <option> + <name>CCRDICatchIRQ</name> + <state>0</state> + </option> + <option> + <name>CCRDICatchFIQ</name> + <state>0</state> + </option> + <option> + <name>CCJLinkBreakpointRadio</name> + <state>0</state> + </option> + <option> + <name>CCJLinkDoUpdateBreakpoints</name> + <state>0</state> + </option> + <option> + <name>CCJLinkUpdateBreakpoints</name> + <state>main</state> + </option> + <option> + <name>CCJLinkInterfaceRadio</name> + <state>0</state> + </option> + <option> + <name>CCJLinkResetList</name> + <version>6</version> + <state>5</state> + </option> + <option> + <name>CCJLinkInterfaceCmdLine</name> + <state>0</state> + </option> + <option> + <name>CCCatchCORERESET</name> + <state>0</state> + </option> + <option> + <name>CCCatchMMERR</name> + <state>0</state> + </option> + <option> + <name>CCCatchNOCPERR</name> + <state>0</state> + </option> + <option> + <name>CCCatchCHRERR</name> + <state>0</state> + </option> + <option> + <name>CCCatchSTATERR</name> + <state>0</state> + </option> + <option> + <name>CCCatchBUSERR</name> + <state>0</state> + </option> + <option> + <name>CCCatchINTERR</name> + <state>0</state> + </option> + <option> + <name>CCCatchHARDERR</name> + <state>0</state> + </option> + <option> + <name>CCCatchDummy</name> + <state>0</state> + </option> + <option> + <name>OCJLinkScriptFile</name> + <state>1</state> + </option> + <option> + <name>CCJLinkUsbSerialNo</name> + <state></state> + </option> + <option> + <name>CCTcpIpAlt</name> + <version>0</version> + <state>0</state> + </option> + <option> + <name>CCJLinkTcpIpSerialNo</name> + <state></state> + </option> + <option> + <name>CCCpuClockEdit</name> + <state>72.0</state> + </option> + <option> + <name>CCSwoClockAuto</name> + <state>0</state> + </option> + <option> + <name>CCSwoClockEdit</name> + <state>2000</state> + </option> + <option> + <name>OCJLinkTraceSource</name> + <state>0</state> + </option> + <option> + <name>OCJLinkTraceSourceDummy</name> + <state>0</state> + </option> + <option> + <name>OCJLinkDeviceName</name> + <state>1</state> + </option> + </data> + </settings> + <settings> + <name>LMIFTDI_ID</name> + <archiveVersion>2</archiveVersion> + <data> + <version>3</version> + <wantNonLocal>1</wantNonLocal> + <debug>0</debug> + <option> + <name>OCDriverInfo</name> + <state>1</state> + </option> + <option> + <name>LmiftdiSpeed</name> + <state>500</state> + </option> + <option> + <name>CCLmiftdiDoLogfile</name> + <state>0</state> + </option> + <option> + <name>CCLmiftdiLogFile</name> + <state>$TOOLKIT_DIR$\cspycomm.log</state> + </option> + <option> + <name>CCLmiFtdiInterfaceRadio</name> + <state>0</state> + </option> + <option> + <name>CCLmiFtdiInterfaceCmdLine</name> + <state>0</state> + </option> + <option> + <name>CCLmiftdiUsbSerialNo</name> + <state></state> + </option> + <option> + <name>CCLmiftdiUsbSerialNoSelect</name> + <state>0</state> + </option> + <option> + <name>CCLmiftdiResetList</name> + <version>0</version> + <state>0</state> + </option> + </data> + </settings> + <settings> + <name>NULINK_ID</name> + <archiveVersion>2</archiveVersion> + <data> + <version>0</version> + <wantNonLocal>1</wantNonLocal> + <debug>0</debug> + <option> + <name>OCDriverInfo</name> + <state>1</state> + </option> + <option> + <name>DoLogfile</name> + <state>0</state> + </option> + <option> + <name>LogFile</name> + <state>$PROJ_DIR$\cspycomm.log</state> + </option> + </data> + </settings> + <settings> + <name>PEMICRO_ID</name> + <archiveVersion>2</archiveVersion> + <data> + <version>3</version> + <wantNonLocal>1</wantNonLocal> + <debug>0</debug> + <option> + <name>OCDriverInfo</name> + <state>1</state> + </option> + <option> + <name>CCJPEMicroShowSettings</name> + <state>0</state> + </option> + <option> + <name>DoLogfile</name> + <state>0</state> + </option> + <option> + <name>LogFile</name> + <state>$PROJ_DIR$\cspycomm.log</state> + </option> + </data> + </settings> + <settings> + <name>STLINK_ID</name> + <archiveVersion>2</archiveVersion> + <data> + <version>7</version> + <wantNonLocal>1</wantNonLocal> + <debug>0</debug> + <option> + <name>OCDriverInfo</name> + <state>1</state> + </option> + <option> + <name>CCSTLinkInterfaceRadio</name> + <state>0</state> + </option> + <option> + <name>CCSTLinkInterfaceCmdLine</name> + <state>0</state> + </option> + <option> + <name>CCSTLinkResetList</name> + <version>3</version> + <state>0</state> + </option> + <option> + <name>CCCpuClockEdit</name> + <state>72.0</state> + </option> + <option> + <name>CCSwoClockAuto</name> + <state>0</state> + </option> + <option> + <name>CCSwoClockEdit</name> + <state>2000</state> + </option> + <option> + <name>DoLogfile</name> + <state>0</state> + </option> + <option> + <name>LogFile</name> + <state>$PROJ_DIR$\cspycomm.log</state> + </option> + <option> + <name>CCSTLinkDoUpdateBreakpoints</name> + <state>0</state> + </option> + <option> + <name>CCSTLinkUpdateBreakpoints</name> + <state>_call_main</state> + </option> + <option> + <name>CCSTLinkCatchCORERESET</name> + <state>0</state> + </option> + <option> + <name>CCSTLinkCatchMMERR</name> + <state>0</state> + </option> + <option> + <name>CCSTLinkCatchNOCPERR</name> + <state>0</state> + </option> + <option> + <name>CCSTLinkCatchCHRERR</name> + <state>0</state> + </option> + <option> + <name>CCSTLinkCatchSTATERR</name> + <state>0</state> + </option> + <option> + <name>CCSTLinkCatchBUSERR</name> + <state>0</state> + </option> + <option> + <name>CCSTLinkCatchINTERR</name> + <state>0</state> + </option> + <option> + <name>CCSTLinkCatchSFERR</name> + <state>0</state> + </option> + <option> + <name>CCSTLinkCatchHARDERR</name> + <state>0</state> + </option> + <option> + <name>CCSTLinkCatchDummy</name> + <state>0</state> + </option> + <option> + <name>CCSTLinkUsbSerialNo</name> + <state></state> + </option> + <option> + <name>CCSTLinkUsbSerialNoSelect</name> + <state>0</state> + </option> + <option> + <name>CCSTLinkJtagSpeedList</name> + <version>2</version> + <state>0</state> + </option> + <option> + <name>CCSTLinkDAPNumber</name> + <state></state> + </option> + <option> + <name>CCSTLinkDebugAccessPortRadio</name> + <state>0</state> + </option> + <option> + <name>CCSTLinkUseServerSelect</name> + <state>0</state> + </option> + <option> + <name>CCSTLinkProbeList</name> + <version>1</version> + <state>0</state> + </option> + </data> + </settings> + <settings> + <name>THIRDPARTY_ID</name> + <archiveVersion>2</archiveVersion> + <data> + <version>0</version> + <wantNonLocal>1</wantNonLocal> + <debug>0</debug> + <option> + <name>CThirdPartyDriverDll</name> + <state>Browse to your third-party driver</state> + </option> + <option> + <name>CThirdPartyLogFileCheck</name> + <state>0</state> + </option> + <option> + <name>CThirdPartyLogFileEditB</name> + <state>$TOOLKIT_DIR$\cspycomm.log</state> + </option> + <option> + <name>OCDriverInfo</name> + <state>1</state> + </option> + </data> + </settings> + <settings> + <name>TIFET_ID</name> + <archiveVersion>2</archiveVersion> + <data> + <version>1</version> + <wantNonLocal>1</wantNonLocal> + <debug>0</debug> + <option> + <name>OCDriverInfo</name> + <state>1</state> + </option> + <option> + <name>CCMSPFetResetList</name> + <version>0</version> + <state>0</state> + </option> + <option> + <name>CCMSPFetInterfaceRadio</name> + <state>0</state> + </option> + <option> + <name>CCMSPFetInterfaceCmdLine</name> + <state>0</state> + </option> + <option> + <name>CCMSPFetTargetVccTypeDefault</name> + <state>0</state> + </option> + <option> + <name>CCMSPFetTargetVoltage</name> + <state>###Uninitialized###</state> + </option> + <option> + <name>CCMSPFetVCCDefault</name> + <state>1</state> + </option> + <option> + <name>CCMSPFetTargetSettlingtime</name> + <state>0</state> + </option> + <option> + <name>CCMSPFetRadioJtagSpeedType</name> + <state>1</state> + </option> + <option> + <name>CCMSPFetConnection</name> + <version>0</version> + <state>0</state> + </option> + <option> + <name>CCMSPFetUsbComPort</name> + <state>Automatic</state> + </option> + <option> + <name>CCMSPFetAllowAccessToBSL</name> + <state>0</state> + </option> + <option> + <name>CCMSPFetDoLogfile</name> + <state>0</state> + </option> + <option> + <name>CCMSPFetLogFile</name> + <state>$PROJ_DIR$\cspycomm.log</state> + </option> + <option> + <name>CCMSPFetRadioEraseFlash</name> + <state>1</state> + </option> + </data> + </settings> + <settings> + <name>XDS100_ID</name> + <archiveVersion>2</archiveVersion> + <data> + <version>9</version> + <wantNonLocal>1</wantNonLocal> + <debug>0</debug> + <option> + <name>OCDriverInfo</name> + <state>1</state> + </option> + <option> + <name>TIPackageOverride</name> + <state>0</state> + </option> + <option> + <name>TIPackage</name> + <state></state> + </option> + <option> + <name>BoardFile</name> + <state></state> + </option> + <option> + <name>DoLogfile</name> + <state>0</state> + </option> + <option> + <name>LogFile</name> + <state>$PROJ_DIR$\cspycomm.log</state> + </option> + <option> + <name>CCXds100BreakpointRadio</name> + <state>0</state> + </option> + <option> + <name>CCXds100DoUpdateBreakpoints</name> + <state>0</state> + </option> + <option> + <name>CCXds100UpdateBreakpoints</name> + <state>_call_main</state> + </option> + <option> + <name>CCXds100CatchReset</name> + <state>0</state> + </option> + <option> + <name>CCXds100CatchUndef</name> + <state>0</state> + </option> + <option> + <name>CCXds100CatchSWI</name> + <state>0</state> + </option> + <option> + <name>CCXds100CatchData</name> + <state>0</state> + </option> + <option> + <name>CCXds100CatchPrefetch</name> + <state>0</state> + </option> + <option> + <name>CCXds100CatchIRQ</name> + <state>0</state> + </option> + <option> + <name>CCXds100CatchFIQ</name> + <state>0</state> + </option> + <option> + <name>CCXds100CatchCORERESET</name> + <state>0</state> + </option> + <option> + <name>CCXds100CatchMMERR</name> + <state>0</state> + </option> + <option> + <name>CCXds100CatchNOCPERR</name> + <state>0</state> + </option> + <option> + <name>CCXds100CatchCHRERR</name> + <state>0</state> + </option> + <option> + <name>CCXds100CatchSTATERR</name> + <state>0</state> + </option> + <option> + <name>CCXds100CatchBUSERR</name> + <state>0</state> + </option> + <option> + <name>CCXds100CatchINTERR</name> + <state>0</state> + </option> + <option> + <name>CCXds100CatchSFERR</name> + <state>0</state> + </option> + <option> + <name>CCXds100CatchHARDERR</name> + <state>0</state> + </option> + <option> + <name>CCXds100CatchDummy</name> + <state>0</state> + </option> + <option> + <name>CCXds100CpuClockEdit</name> + <state></state> + </option> + <option> + <name>CCXds100SwoClockAuto</name> + <state>0</state> + </option> + <option> + <name>CCXds100SwoClockEdit</name> + <state>1000</state> + </option> + <option> + <name>CCXds100HWResetDelay</name> + <state>0</state> + </option> + <option> + <name>CCXds100ResetList</name> + <version>1</version> + <state>0</state> + </option> + <option> + <name>CCXds100UsbSerialNo</name> + <state></state> + </option> + <option> + <name>CCXds100UsbSerialNoSelect</name> + <state>0</state> + </option> + <option> + <name>CCXds100JtagSpeedList</name> + <version>0</version> + <state>0</state> + </option> + <option> + <name>CCXds100InterfaceRadio</name> + <state>2</state> + </option> + <option> + <name>CCXds100InterfaceCmdLine</name> + <state>0</state> + </option> + <option> + <name>CCXds100ProbeList</name> + <version>0</version> + <state>2</state> + </option> + <option> + <name>CCXds100SWOPortRadio</name> + <state>0</state> + </option> + <option> + <name>CCXds100SWOPort</name> + <state>1</state> + </option> + <option> + <name>CCXDSTargetVccEnable</name> + <state>0</state> + </option> + <option> + <name>CCXDSTargetVoltage</name> + <state>###Uninitialized###</state> + </option> + <option> + <name>OCXDSDigitalStatesConfigFile</name> + <state>1</state> + </option> + <option> + <name>OCSelectedCoreName</name> + <state>1</state> + </option> + </data> + </settings> + <debuggerPlugins> + <plugin> + <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$TOOLKIT_DIR$\plugins\rtos\FreeRtos\FreeRtosArmPlugin.ENU.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin2.ENU.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm9.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm9BE.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + </debuggerPlugins> + </configuration> +</project> diff --git a/ports_module/cortex_a7/iar/example_build/sample_threadx.ewp b/ports_module/cortex_a7/iar/example_build/sample_threadx.ewp new file mode 100644 index 00000000..a1924c1f --- /dev/null +++ b/ports_module/cortex_a7/iar/example_build/sample_threadx.ewp @@ -0,0 +1,2135 @@ +<?xml version="1.0" encoding="UTF-8"?> +<project> + <fileVersion>3</fileVersion> + <configuration> + <name>Debug</name> + <toolchain> + <name>ARM</name> + </toolchain> + <debug>1</debug> + <settings> + <name>General</name> + <archiveVersion>3</archiveVersion> + <data> + <version>34</version> + <wantNonLocal>1</wantNonLocal> + <debug>1</debug> + <option> + <name>BrowseInfoPath</name> + <state>Debug\BrowseInfo</state> + </option> + <option> + <name>ExePath</name> + <state>Debug\Exe</state> + </option> + <option> + <name>ObjPath</name> + <state>Debug\Obj</state> + </option> + <option> + <name>ListPath</name> + <state>Debug\List</state> + </option> + <option> + <name>GEndianMode</name> + <state>0</state> + </option> + <option> + <name>Input description</name> + <state>Full formatting, without multibyte support.</state> + </option> + <option> + <name>Output description</name> + <state>Full formatting, without multibyte support.</state> + </option> + <option> + <name>GOutputBinary</name> + <state>0</state> + </option> + <option> + <name>OGCoreOrChip</name> + <state>0</state> + </option> + <option> + <name>GRuntimeLibSelect</name> + <version>0</version> + <state>1</state> + </option> + <option> + <name>GRuntimeLibSelectSlave</name> + <version>0</version> + <state>1</state> + </option> + <option> + <name>RTDescription</name> + <state>Use the normal configuration of the C/C++ runtime library. No locale interface, C locale, no file descriptor support, no multibytes in printf and scanf, and no hex floats in strtod.</state> + </option> + <option> + <name>OGProductVersion</name> + <state>4.11A</state> + </option> + <option> + <name>OGLastSavedByProductVersion</name> + <state>9.20.4.46976</state> + </option> + <option> + <name>OGChipSelectEditMenu</name> + <state>RM48L530PGE TexasInstruments RM48L530PGE</state> + </option> + <option> + <name>GenLowLevelInterface</name> + <state>1</state> + </option> + <option> + <name>GEndianModeBE</name> + <state>0</state> + </option> + <option> + <name>OGBufferedTerminalOutput</name> + <state>0</state> + </option> + <option> + <name>GenStdoutInterface</name> + <state>0</state> + </option> + <option> + <name>RTConfigPath2</name> + <state>$TOOLKIT_DIR$\inc\c\DLib_Config_Normal.h</state> + </option> + <option> + <name>GBECoreSlave</name> + <version>31</version> + <state>42</state> + </option> + <option> + <name>OGUseCmsis</name> + <state>0</state> + </option> + <option> + <name>OGUseCmsisDspLib</name> + <state>0</state> + </option> + <option> + <name>GRuntimeLibThreads</name> + <state>0</state> + </option> + <option> + <name>CoreVariant</name> + <version>31</version> + <state>52</state> + </option> + <option> + <name>GFPUDeviceSlave</name> + <state>RM48L530PGE TexasInstruments RM48L530PGE</state> + </option> + <option> + <name>FPU2</name> + <version>0</version> + <state>3</state> + </option> + <option> + <name>NrRegs</name> + <version>0</version> + <state>1</state> + </option> + <option> + <name>NEON</name> + <state>0</state> + </option> + <option> + <name>GFPUCoreSlave2</name> + <version>31</version> + <state>42</state> + </option> + <option> + <name>OGCMSISPackSelectDevice</name> + </option> + <option> + <name>OgLibHeap</name> + <state>0</state> + </option> + <option> + <name>OGLibAdditionalLocale</name> + <state>0</state> + </option> + <option> + <name>OGPrintfVariant</name> + <version>0</version> + <state>1</state> + </option> + <option> + <name>OGPrintfMultibyteSupport</name> + <state>0</state> + </option> + <option> + <name>OGScanfVariant</name> + <version>0</version> + <state>1</state> + </option> + <option> + <name>OGScanfMultibyteSupport</name> + <state>0</state> + </option> + <option> + <name>GenLocaleTags</name> + <state></state> + </option> + <option> + <name>GenLocaleDisplayOnly</name> + <state></state> + </option> + <option> + <name>DSPExtension</name> + <state>0</state> + </option> + <option> + <name>TrustZone</name> + <state>0</state> + </option> + <option> + <name>TrustZoneModes</name> + <version>0</version> + <state>0</state> + </option> + <option> + <name>OGAarch64Abi</name> + <state>0</state> + </option> + <option> + <name>OG_32_64Device</name> + <state>0</state> + </option> + <option> + <name>BuildFilesPath</name> + <state>Debug</state> + </option> + </data> + </settings> + <settings> + <name>ICCARM</name> + <archiveVersion>2</archiveVersion> + <data> + <version>37</version> + <wantNonLocal>1</wantNonLocal> + <debug>1</debug> + <option> + <name>CCOptimizationNoSizeConstraints</name> + <state>0</state> + </option> + <option> + <name>IFpuProcessor</name> + <state>1</state> + </option> + <option> + <name>OutputFile</name> + <state>$FILE_BNAME$.o</state> + </option> + <option> + <name>CCDefines</name> + <state></state> + </option> + <option> + <name>CCPreprocFile</name> + <state>0</state> + </option> + <option> + <name>CCPreprocComments</name> + <state>0</state> + </option> + <option> + <name>CCPreprocLine</name> + <state>0</state> + </option> + <option> + <name>CCListCFile</name> + <state>0</state> + </option> + <option> + <name>CCListCMnemonics</name> + <state>1</state> + </option> + <option> + <name>CCListCMessages</name> + <state>1</state> + </option> + <option> + <name>CCListAssFile</name> + <state>0</state> + </option> + <option> + <name>CCListAssSource</name> + <state>0</state> + </option> + <option> + <name>CCEnableRemarks</name> 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<name>CCRequirePrototypes</name> + <state>0</state> + </option> + <option> + <name>CCDiagWarnAreErr</name> + <state>0</state> + </option> + <option> + <name>CCCompilerRuntimeInfo</name> + <state>1</state> + </option> + <option> + <name>CCLibConfigHeader</name> + <state>1</state> + </option> + <option> + <name>PreInclude</name> + <state></state> + </option> + <option> + <name>CCIncludePath2</name> + <state>$PROJ_DIR$\..\inc</state> + <state>$PROJ_DIR$\..\..\..\..\common\inc</state> + </option> + <option> + <name>CCStdIncCheck</name> + <state>0</state> + </option> + <option> + <name>CCCodeSection</name> + <state>.text</state> + </option> + <option> + <name>IProcessorMode2</name> + <state>0</state> + </option> + <option> + <name>CCOptLevel</name> + <state>1</state> + </option> + <option> + <name>CCOptStrategy</name> + <version>0</version> + <state>0</state> + </option> + <option> + <name>CCOptLevelSlave</name> + <state>1</state> + </option> + <option> + <name>CCPosIndRopi</name> + <state>0</state> + </option> + <option> + <name>CCPosIndRwpi</name> + <state>0</state> + </option> + <option> + <name>CCPosIndNoDynInit</name> + <state>0</state> + </option> + <option> + <name>IccLang</name> + <state>0</state> + </option> + <option> + <name>IccCDialect</name> + <state>1</state> + </option> + <option> + <name>IccAllowVLA</name> + <state>0</state> + </option> + <option> + <name>IccStaticDestr</name> + <state>1</state> + </option> + <option> + <name>IccCppInlineSemantics</name> + <state>1</state> + </option> + <option> + <name>IccCmsis</name> + <state>1</state> + </option> + <option> + <name>IccFloatSemantics</name> + <state>0</state> + </option> + <option> + <name>CCNoLiteralPool</name> + <state>0</state> + </option> + <option> + <name>CCOptStrategySlave</name> + <version>0</version> + <state>0</state> + </option> + <option> + <name>CCGuardCalls</name> + <state>1</state> + </option> + <option> + <name>CCEncSource</name> + <state>0</state> + </option> + <option> + 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</settings> + <settings> + <name>CUSTOM</name> + <archiveVersion>3</archiveVersion> + <data> + <extensions></extensions> + <cmdline></cmdline> + <hasPrio>0</hasPrio> + <buildSequence>inputOutputBased</buildSequence> + </data> + </settings> + <settings> + <name>BUILDACTION</name> + <archiveVersion>1</archiveVersion> + <data> + <prebuild></prebuild> + <postbuild></postbuild> + </data> + </settings> + <settings> + <name>ILINK</name> + <archiveVersion>0</archiveVersion> + <data> + <version>26</version> + <wantNonLocal>1</wantNonLocal> + <debug>1</debug> + <option> + <name>IlinkLibIOConfig</name> + <state>1</state> + </option> + <option> + <name>IlinkInputFileSlave</name> + <state>0</state> + </option> + <option> + <name>IlinkOutputFile</name> + <state>sample_threadx.out</state> + </option> + <option> + <name>IlinkDebugInfoEnable</name> + <state>1</state> + </option> + <option> + <name>IlinkKeepSymbols</name> + <state></state> + </option> + <option> + <name>IlinkRawBinaryFile</name> + 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<state>0</state> + </option> + <option> + <name>IlinkLogInlining</name> + <state>0</state> + </option> + <option> + <name>IlinkLogMerging</name> + <state>0</state> + </option> + <option> + <name>IlinkDemangle</name> + <state>0</state> + </option> + <option> + <name>IlinkWrapperFileEnable</name> + <state>0</state> + </option> + <option> + <name>IlinkWrapperFile</name> + <state></state> + </option> + </data> + </settings> + <settings> + <name>IARCHIVE</name> + <archiveVersion>0</archiveVersion> + <data> + <version>0</version> + <wantNonLocal>1</wantNonLocal> + <debug>1</debug> + <option> + <name>IarchiveInputs</name> + <state></state> + </option> + <option> + <name>IarchiveOverride</name> + <state>0</state> + </option> + <option> + <name>IarchiveOutput</name> + <state>###Unitialized###</state> + </option> + </data> + </settings> + <settings> + <name>Coder</name> + <archiveVersion>0</archiveVersion> + <data /> + </settings> + </configuration> + <configuration> + <name>Release</name> + <toolchain> + <name>ARM</name> + </toolchain> + <debug>0</debug> + <settings> + <name>General</name> + <archiveVersion>3</archiveVersion> + <data> + <version>34</version> + <wantNonLocal>1</wantNonLocal> + <debug>0</debug> + <option> + <name>BrowseInfoPath</name> + <state>Release\BrowseInfo</state> + </option> + <option> + <name>ExePath</name> + <state>Release\Exe</state> + </option> + <option> + <name>ObjPath</name> + <state>Release\Obj</state> + </option> + <option> + <name>ListPath</name> + <state>Release\List</state> + </option> + <option> + <name>GEndianMode</name> + <state>0</state> + </option> + <option> + <name>Input description</name> + <state></state> + </option> + <option> + <name>Output description</name> + <state></state> + </option> + <option> + <name>GOutputBinary</name> + <state>0</state> + </option> + <option> + <name>OGCoreOrChip</name> + <state>0</state> + </option> + <option> + <name>GRuntimeLibSelect</name> + <version>0</version> + <state>1</state> + </option> + <option> + <name>GRuntimeLibSelectSlave</name> + <version>0</version> + <state>1</state> + </option> + <option> + <name>RTDescription</name> + <state></state> + </option> + <option> + <name>OGProductVersion</name> + <state>4.11A</state> + </option> + <option> + <name>OGLastSavedByProductVersion</name> + <state>8.10.1.12859</state> + </option> + <option> + <name>OGChipSelectEditMenu</name> + <state>LPC2106 Philips LPC2106</state> + </option> + <option> + <name>GenLowLevelInterface</name> + <state>0</state> + </option> + <option> + <name>GEndianModeBE</name> + <state>0</state> + </option> + <option> + <name>OGBufferedTerminalOutput</name> + <state>0</state> + </option> + <option> + <name>GenStdoutInterface</name> + <state>0</state> + </option> + <option> + <name>RTConfigPath2</name> + <state></state> + </option> + <option> + <name>GBECoreSlave</name> + <version>31</version> + <state>0</state> + </option> + <option> + <name>OGUseCmsis</name> + <state>0</state> + </option> + <option> + <name>OGUseCmsisDspLib</name> + <state>0</state> + </option> + <option> + <name>GRuntimeLibThreads</name> + <state>0</state> + </option> + <option> + <name>CoreVariant</name> + <version>31</version> + <state>0</state> + </option> + <option> + <name>GFPUDeviceSlave</name> + <state>LPC2106 Philips LPC2106</state> + </option> + <option> + <name>FPU2</name> + <version>0</version> + <state>0</state> + </option> + <option> + <name>NrRegs</name> + <version>0</version> + <state>0</state> + </option> + <option> + <name>NEON</name> + <state>0</state> + </option> + <option> + <name>GFPUCoreSlave2</name> + <version>31</version> + <state>0</state> + </option> + <option> + <name>OGCMSISPackSelectDevice</name> + </option> + <option> + <name>OgLibHeap</name> + <state>0</state> + </option> + <option> + <name>OGLibAdditionalLocale</name> + <state>0</state> + </option> + <option> + <name>OGPrintfVariant</name> + <version>0</version> + <state>1</state> + </option> + <option> + <name>OGPrintfMultibyteSupport</name> + <state>0</state> + </option> + <option> + <name>OGScanfVariant</name> + <version>0</version> + <state>1</state> + </option> + <option> + <name>OGScanfMultibyteSupport</name> + <state>0</state> + </option> + <option> + <name>GenLocaleTags</name> + <state></state> + </option> + <option> + <name>GenLocaleDisplayOnly</name> + <state></state> + </option> + <option> + <name>DSPExtension</name> + <state>0</state> + </option> + <option> + <name>TrustZone</name> + <state>0</state> + </option> + <option> + <name>TrustZoneModes</name> + <version>0</version> + <state>0</state> + </option> + <option> + <name>OGAarch64Abi</name> + <state>0</state> + </option> + <option> + <name>OG_32_64Device</name> + <state>0</state> + </option> + <option> + <name>BuildFilesPath</name> + <state>Release</state> + </option> + </data> + </settings> + <settings> + <name>ICCARM</name> + <archiveVersion>2</archiveVersion> + <data> + <version>37</version> + <wantNonLocal>1</wantNonLocal> + <debug>0</debug> + <option> + <name>CCOptimizationNoSizeConstraints</name> + <state>0</state> + </option> + <option> + <name>IFpuProcessor</name> + <state>1</state> + </option> + <option> + <name>OutputFile</name> + <state></state> + </option> + <option> + <name>CCDefines</name> + <state></state> + </option> + <option> + <name>CCPreprocFile</name> + <state>0</state> + </option> + <option> + <name>CCPreprocComments</name> + <state>0</state> + </option> + <option> + <name>CCPreprocLine</name> + <state>0</state> + </option> + <option> + <name>CCListCFile</name> + <state>0</state> + </option> + <option> + <name>CCListCMnemonics</name> + <state>0</state> + </option> + <option> + <name>CCListCMessages</name> + <state>0</state> + </option> + <option> + <name>CCListAssFile</name> + <state>0</state> + </option> + <option> + <name>CCListAssSource</name> + <state>0</state> + </option> + <option> + <name>CCEnableRemarks</name> + <state>0</state> + </option> + <option> + <name>CCDiagSuppress</name> + <state></state> + </option> + <option> + <name>CCDiagRemark</name> + <state></state> + </option> + <option> + <name>CCDiagWarning</name> + <state></state> + </option> + <option> + <name>CCDiagError</name> + <state></state> + </option> + <option> + <name>CCObjPrefix</name> + <state>1</state> + </option> + <option> + <name>CCAllowList</name> + <version>1</version> + <state>11111100</state> + </option> + <option> + <name>CCDebugInfo</name> + <state>0</state> + </option> + <option> + <name>IEndianMode</name> + <state>1</state> + </option> + <option> + <name>IProcessor</name> + <state>1</state> + </option> + <option> + <name>IExtraOptionsCheck</name> + <state>0</state> + </option> + <option> + <name>IExtraOptions</name> + <state></state> + </option> + <option> + <name>CCLangConformance</name> + <state>0</state> + </option> + <option> + <name>CCSignedPlainChar</name> + <state>1</state> + </option> + <option> + <name>CCRequirePrototypes</name> + <state>0</state> + </option> + <option> + <name>CCDiagWarnAreErr</name> + <state>0</state> + </option> + <option> + <name>CCCompilerRuntimeInfo</name> + <state>1</state> + </option> + <option> + <name>CCLibConfigHeader</name> + <state>1</state> + </option> + <option> + <name>PreInclude</name> + <state></state> + </option> + <option> + <name>CCIncludePath2</name> + <state></state> + </option> + <option> + <name>CCStdIncCheck</name> + <state>0</state> + </option> + <option> + <name>CCCodeSection</name> + <state>.text</state> + </option> + <option> + <name>IProcessorMode2</name> + <state>1</state> + </option> + <option> + <name>CCOptLevel</name> + <state>3</state> + </option> + <option> + <name>CCOptStrategy</name> + <version>0</version> + <state>1</state> + </option> + <option> + <name>CCOptLevelSlave</name> + <state>3</state> + </option> + <option> + <name>CCPosIndRopi</name> + <state>0</state> + </option> + <option> + <name>CCPosIndRwpi</name> + <state>0</state> + </option> + <option> + <name>CCPosIndNoDynInit</name> + <state>0</state> + </option> + <option> + <name>IccLang</name> + <state>0</state> + </option> + <option> + <name>IccCDialect</name> + <state>1</state> + </option> + <option> + <name>IccAllowVLA</name> + <state>0</state> + </option> + <option> + <name>IccStaticDestr</name> + <state>1</state> + </option> + <option> + <name>IccCppInlineSemantics</name> + <state>1</state> + </option> + <option> + <name>IccCmsis</name> + <state>1</state> + </option> + <option> + <name>IccFloatSemantics</name> + <state>0</state> + </option> + <option> + <name>CCNoLiteralPool</name> + <state>0</state> + </option> + <option> + <name>CCOptStrategySlave</name> + <version>0</version> + <state>1</state> + </option> + <option> + <name>CCGuardCalls</name> + <state>1</state> + </option> + <option> + <name>CCEncSource</name> + <state>0</state> + </option> + <option> + <name>CCEncOutput</name> + <state>0</state> + </option> + <option> + <name>CCEncOutputBom</name> + <state>1</state> + </option> + <option> + <name>CCEncInput</name> + <state>0</state> + </option> + <option> + <name>IccExceptions2</name> + <state>0</state> + </option> + <option> + <name>IccRTTI2</name> + <state>0</state> + </option> + <option> + <name>OICompilerExtraOption</name> + <state>1</state> + </option> + <option> + <name>CCStackProtection</name> + <state>0</state> + </option> + </data> + </settings> + <settings> + <name>AARM</name> + <archiveVersion>2</archiveVersion> + <data> + <version>11</version> + <wantNonLocal>1</wantNonLocal> + <debug>0</debug> + <option> + <name>AOutputFile</name> + <state></state> + </option> + <option> + <name>AObjPrefix</name> + <state>1</state> + </option> + <option> + <name>AEndian</name> + <state>1</state> + </option> + <option> + <name>ACaseSensitivity</name> + <state>1</state> + </option> + <option> + <name>MacroChars</name> + <version>0</version> + <state>0</state> + </option> + <option> + <name>AWarnEnable</name> + <state>0</state> + </option> + <option> + <name>AWarnWhat</name> + <state>0</state> + </option> + <option> + <name>AWarnOne</name> + <state></state> + </option> + <option> + <name>AWarnRange1</name> + <state></state> + </option> + <option> + <name>AWarnRange2</name> + <state></state> + </option> + <option> + <name>ADebug</name> + <state>0</state> + </option> + <option> + <name>AltRegisterNames</name> + <state>0</state> + </option> + <option> + <name>ADefines</name> + <state></state> + </option> + <option> + <name>AList</name> + <state>0</state> + </option> + <option> + <name>AListHeader</name> + <state>1</state> + </option> + <option> + <name>AListing</name> + <state>1</state> + </option> + <option> + <name>Includes</name> + <state>0</state> + </option> + <option> + <name>MacDefs</name> + <state>0</state> + </option> + <option> + <name>MacExps</name> + <state>1</state> + </option> + <option> + <name>MacExec</name> + <state>0</state> + </option> + <option> + <name>OnlyAssed</name> + <state>0</state> + </option> + <option> + <name>MultiLine</name> + <state>0</state> + </option> + <option> + <name>PageLengthCheck</name> + <state>0</state> + </option> + <option> + <name>PageLength</name> + <state>80</state> + </option> + <option> + <name>TabSpacing</name> + <state>8</state> + </option> + <option> + <name>AXRef</name> + <state>0</state> + </option> + <option> + <name>AXRefDefines</name> + <state>0</state> + </option> + <option> + <name>AXRefInternal</name> + <state>0</state> + </option> + <option> + <name>AXRefDual</name> + <state>0</state> + </option> + <option> + <name>AProcessor</name> + <state>1</state> + </option> + <option> + <name>AFpuProcessor</name> + <state>1</state> + </option> + <option> + <name>ALimitErrorsCheck</name> + <state>0</state> + </option> + <option> + <name>ALimitErrorsEdit</name> + <state>100</state> + </option> + <option> + <name>AIgnoreStdInclude</name> + <state>0</state> + </option> + <option> + <name>AUserIncludes</name> + <state></state> + </option> + <option> + <name>AExtraOptionsCheckV2</name> + <state>0</state> + </option> + <option> + <name>AExtraOptionsV2</name> + <state></state> + </option> + <option> + <name>AsmNoLiteralPool</name> + <state>0</state> + </option> + <option> + <name>PreInclude</name> + <state></state> + </option> + </data> + </settings> + <settings> + <name>OBJCOPY</name> + <archiveVersion>0</archiveVersion> + <data> + <version>1</version> + <wantNonLocal>1</wantNonLocal> + <debug>0</debug> + <option> + <name>OOCOutputFormat</name> + <version>3</version> + <state>0</state> + </option> + <option> + <name>OCOutputOverride</name> + <state>0</state> + </option> + <option> + <name>OOCOutputFile</name> + <state></state> + </option> + <option> + <name>OOCCommandLineProducer</name> + <state>1</state> + </option> + <option> + <name>OOCObjCopyEnable</name> + <state>0</state> + </option> + </data> + </settings> + <settings> + <name>CUSTOM</name> + <archiveVersion>3</archiveVersion> + <data> + <extensions></extensions> + <cmdline></cmdline> + <hasPrio>0</hasPrio> + <buildSequence>inputOutputBased</buildSequence> + </data> + </settings> + <settings> + <name>BUILDACTION</name> + <archiveVersion>1</archiveVersion> + <data> + <prebuild></prebuild> + <postbuild></postbuild> + </data> + </settings> + <settings> + <name>ILINK</name> + <archiveVersion>0</archiveVersion> + <data> + <version>26</version> + <wantNonLocal>1</wantNonLocal> + <debug>0</debug> + <option> + <name>IlinkLibIOConfig</name> + <state>1</state> + </option> + <option> + <name>IlinkInputFileSlave</name> + <state>0</state> + </option> + <option> + <name>IlinkOutputFile</name> + <state>###Unitialized###</state> + </option> + <option> + <name>IlinkDebugInfoEnable</name> + <state>1</state> + </option> + <option> + <name>IlinkKeepSymbols</name> + <state></state> + </option> + <option> + <name>IlinkRawBinaryFile</name> + <state></state> + </option> + <option> + <name>IlinkRawBinarySymbol</name> + <state></state> + </option> + <option> + <name>IlinkRawBinarySegment</name> + <state></state> + </option> + <option> + <name>IlinkRawBinaryAlign</name> + <state></state> + </option> + <option> + <name>IlinkDefines</name> + <state></state> + </option> + <option> + <name>IlinkConfigDefines</name> + <state></state> + </option> + <option> + <name>IlinkMapFile</name> + <state>0</state> + </option> + <option> + <name>IlinkLogFile</name> + <state>0</state> + </option> + <option> + <name>IlinkLogInitialization</name> + <state>0</state> + </option> + <option> + <name>IlinkLogModule</name> + <state>0</state> + </option> + <option> + <name>IlinkLogSection</name> + <state>0</state> + </option> + <option> + <name>IlinkLogVeneer</name> + <state>0</state> + </option> + <option> + <name>IlinkIcfOverride</name> + <state>0</state> + </option> + <option> + <name>IlinkIcfFile</name> + <state>lnk0t.icf</state> + </option> + <option> + <name>IlinkIcfFileSlave</name> + <state></state> + </option> + <option> + <name>IlinkEnableRemarks</name> + <state>0</state> + </option> + <option> + <name>IlinkSuppressDiags</name> + <state></state> + </option> + <option> + <name>IlinkTreatAsRem</name> + <state></state> + </option> + <option> + <name>IlinkTreatAsWarn</name> + <state></state> + </option> + <option> + <name>IlinkTreatAsErr</name> + <state></state> + </option> + <option> + <name>IlinkWarningsAreErrors</name> + <state>0</state> + </option> + <option> + <name>IlinkUseExtraOptions</name> + <state>0</state> + </option> + <option> + <name>IlinkExtraOptions</name> + <state></state> + </option> + <option> + <name>IlinkLowLevelInterfaceSlave</name> + <state>1</state> + </option> + <option> + <name>IlinkAutoLibEnable</name> + <state>1</state> + </option> + <option> + <name>IlinkAdditionalLibs</name> + <state></state> + </option> + <option> + <name>IlinkOverrideProgramEntryLabel</name> + <state>0</state> + </option> + <option> + <name>IlinkProgramEntryLabelSelect</name> + <state>0</state> + </option> + <option> + <name>IlinkProgramEntryLabel</name> + <state></state> + </option> + <option> + <name>DoFill</name> + <state>0</state> + </option> + <option> + <name>FillerByte</name> + <state>0xFF</state> + </option> + <option> + <name>FillerStart</name> + <state>0x0</state> + </option> + <option> + <name>FillerEnd</name> + <state>0x0</state> + </option> + <option> + <name>CrcSize</name> + <version>0</version> + <state>1</state> + </option> + <option> + <name>CrcAlign</name> + <state>1</state> + </option> + <option> + <name>CrcPoly</name> + <state>0x11021</state> + </option> + <option> + <name>CrcCompl</name> + <version>0</version> + <state>0</state> + </option> + <option> + <name>CrcBitOrder</name> + <version>0</version> + <state>0</state> + </option> + <option> + <name>CrcInitialValue</name> + <state>0x0</state> + </option> + <option> + <name>DoCrc</name> + <state>0</state> + </option> + <option> + <name>IlinkBE8Slave</name> + <state>1</state> + </option> + <option> + <name>IlinkBufferedTerminalOutput</name> + <state>1</state> + </option> + <option> + <name>IlinkStdoutInterfaceSlave</name> + <state>1</state> + </option> + <option> + <name>CrcFullSize</name> + <state>0</state> + </option> + <option> + <name>IlinkIElfToolPostProcess</name> + <state>0</state> + </option> + <option> + <name>IlinkLogAutoLibSelect</name> + <state>0</state> + </option> + <option> + <name>IlinkLogRedirSymbols</name> + <state>0</state> + </option> + <option> + <name>IlinkLogUnusedFragments</name> + <state>0</state> + </option> + <option> + <name>IlinkCrcReverseByteOrder</name> + <state>0</state> + </option> + <option> + <name>IlinkCrcUseAsInput</name> + <state>1</state> + </option> + <option> + <name>IlinkOptInline</name> + <state>1</state> + </option> + <option> + <name>IlinkOptExceptionsAllow</name> + <state>1</state> + </option> + <option> + <name>IlinkOptExceptionsForce</name> + <state>0</state> + </option> + <option> + <name>IlinkCmsis</name> + <state>1</state> + </option> + <option> + <name>IlinkOptMergeDuplSections</name> + <state>0</state> + </option> + <option> + <name>IlinkOptUseVfe</name> + <state>1</state> + </option> + <option> + <name>IlinkOptForceVfe</name> + <state>0</state> + </option> + <option> + <name>IlinkStackAnalysisEnable</name> + <state>0</state> + </option> + <option> + <name>IlinkStackControlFile</name> + <state></state> + </option> + <option> + <name>IlinkStackCallGraphFile</name> + <state></state> + </option> + <option> + <name>CrcAlgorithm</name> + <version>1</version> + <state>1</state> + </option> + <option> + <name>CrcUnitSize</name> + <version>0</version> + <state>0</state> + </option> + <option> + <name>IlinkThreadsSlave</name> + <state>1</state> + </option> + <option> + <name>IlinkLogCallGraph</name> + <state>0</state> + </option> + <option> + <name>IlinkIcfFile_AltDefault</name> + <state></state> + </option> + <option> + <name>IlinkEncInput</name> + <state>0</state> + </option> + <option> + <name>IlinkEncOutput</name> + <state>0</state> + </option> + <option> + <name>IlinkEncOutputBom</name> + <state>1</state> + </option> + <option> + <name>IlinkHeapSelect</name> + <state>1</state> + </option> + <option> + <name>IlinkLocaleSelect</name> + <state>1</state> + </option> + <option> + <name>IlinkTrustzoneImportLibraryOut</name> + <state>###Unitialized###</state> + </option> + <option> + <name>OILinkExtraOption</name> + <state>1</state> + </option> + <option> + <name>IlinkRawBinaryFile2</name> + <state></state> + </option> + <option> + <name>IlinkRawBinarySymbol2</name> + <state></state> + </option> + <option> + <name>IlinkRawBinarySegment2</name> + <state></state> + </option> + <option> + <name>IlinkRawBinaryAlign2</name> + <state></state> + </option> + <option> + <name>IlinkLogCrtRoutineSelection</name> + <state>0</state> + </option> + <option> + <name>IlinkLogFragmentInfo</name> + <state>0</state> + </option> + <option> + <name>IlinkLogInlining</name> + <state>0</state> + </option> + <option> + <name>IlinkLogMerging</name> + <state>0</state> + </option> + <option> + <name>IlinkDemangle</name> + <state>0</state> + </option> + <option> + <name>IlinkWrapperFileEnable</name> + <state>0</state> + </option> + <option> + <name>IlinkWrapperFile</name> + <state></state> + </option> + </data> + </settings> + <settings> + <name>IARCHIVE</name> + <archiveVersion>0</archiveVersion> + <data> + <version>0</version> + <wantNonLocal>1</wantNonLocal> + <debug>0</debug> + <option> + <name>IarchiveInputs</name> + <state></state> + </option> + <option> + <name>IarchiveOverride</name> + <state>0</state> + </option> + <option> + <name>IarchiveOutput</name> + <state>###Unitialized###</state> + </option> + </data> + </settings> + <settings> + <name>Coder</name> + <archiveVersion>0</archiveVersion> + <data /> + </settings> + </configuration> + <file> + <name>$PROJ_DIR$\cstartup.s</name> + </file> + <file> + <name>$PROJ_DIR$\sample_threadx.c</name> + </file> + <file> + <name>$PROJ_DIR$\Debug\Exe\tx.a</name> + </file> + <file> + <name>$PROJ_DIR$\tx_initialize_low_level.s</name> + </file> +</project> diff --git a/ports_module/cortex_a7/iar/example_build/sample_threadx.icf b/ports_module/cortex_a7/iar/example_build/sample_threadx.icf new file mode 100644 index 00000000..13723763 --- /dev/null +++ b/ports_module/cortex_a7/iar/example_build/sample_threadx.icf @@ -0,0 +1,49 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x00000040; +define symbol __ICFEDIT_region_ROM_end__ = 0x0013FFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x08000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x0802FFFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x200; +define symbol __ICFEDIT_size_svcstack__ = 0x100; +define symbol __ICFEDIT_size_irqstack__ = 0x100; +define symbol __ICFEDIT_size_fiqstack__ = 0x100; +define symbol __ICFEDIT_size_undstack__ = 0x100; +define symbol __ICFEDIT_size_abtstack__ = 0x100; +define symbol __ICFEDIT_size_heap__ = 0x200; +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; + +define symbol __region_DRAM_start__ = 0x80000000; +define symbol __region_DRAM_end__ = 0x807FFFFF; +define region DRAM_region = mem:[from __region_DRAM_start__ to __region_DRAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block SVC_STACK with alignment = 8, size = __ICFEDIT_size_svcstack__ { }; +define block IRQ_STACK with alignment = 8, size = __ICFEDIT_size_irqstack__ { }; +define block FIQ_STACK with alignment = 8, size = __ICFEDIT_size_fiqstack__ { }; +define block UND_STACK with alignment = 8, size = __ICFEDIT_size_undstack__ { }; +define block ABT_STACK with alignment = 8, size = __ICFEDIT_size_abtstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +initialize by copy with packing = none { section __DLIB_PERTHREAD }; // Required in a multi-threaded application +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block SVC_STACK, block IRQ_STACK, block FIQ_STACK, + block UND_STACK, block ABT_STACK, block HEAP}; +place in DRAM_region { section DRAM }; + +place in RAM_region { last section FREE_MEM};
\ No newline at end of file diff --git a/ports_module/cortex_a7/iar/example_build/sample_threadx_module.c b/ports_module/cortex_a7/iar/example_build/sample_threadx_module.c new file mode 100644 index 00000000..d81c0c6d --- /dev/null +++ b/ports_module/cortex_a7/iar/example_build/sample_threadx_module.c @@ -0,0 +1,428 @@ +/* This is a small demo of the high-performance ThreadX kernel running as a module. It includes + examples of eight threads of different priorities, using a message queue, semaphore, mutex, + event flags group, byte pool, and block pool. */ + +/* Specify that this is a module! */ + +#define TXM_MODULE + + +/* Include the ThreadX module definitions. */ + +#include "txm_module.h" + + +/* Define constants. */ + +#define DEMO_STACK_SIZE 1024 +#define DEMO_BYTE_POOL_SIZE 9120 +#define DEMO_BLOCK_POOL_SIZE 100 +#define DEMO_QUEUE_SIZE 100 + + +/* Define the pool space in the bss section of the module. ULONG is used to + get the word alignment. */ + +ULONG demo_module_pool_space[DEMO_BYTE_POOL_SIZE / 4]; + + +/* Define the ThreadX object control blocks... */ + +TX_THREAD *thread_0; +TX_THREAD *thread_1; +TX_THREAD *thread_2; +TX_THREAD *thread_3; +TX_THREAD *thread_4; +TX_THREAD *thread_5; +TX_THREAD *thread_6; +TX_THREAD *thread_7; +TX_QUEUE *queue_0; +TX_SEMAPHORE *semaphore_0; +TX_MUTEX *mutex_0; +TX_EVENT_FLAGS_GROUP *event_flags_0; +TX_BYTE_POOL *byte_pool_0; +TX_BLOCK_POOL *block_pool_0; + + +/* Define the counters used in the demo application... */ + +ULONG thread_0_counter; +ULONG thread_1_counter; +ULONG thread_1_messages_sent; +ULONG thread_2_counter; +ULONG thread_2_messages_received; +ULONG thread_3_counter; +ULONG thread_4_counter; +ULONG thread_5_counter; +ULONG thread_6_counter; +ULONG thread_7_counter; +ULONG semaphore_0_puts; +ULONG event_0_sets; +ULONG queue_0_sends; + +/* Define thread prototypes. */ + +void thread_0_entry(ULONG thread_input); +void thread_1_entry(ULONG thread_input); +void thread_2_entry(ULONG thread_input); +void thread_3_and_4_entry(ULONG thread_input); +void thread_5_entry(ULONG thread_input); +void thread_6_and_7_entry(ULONG thread_input); + +void semaphore_0_notify(TX_SEMAPHORE *semaphore_ptr) +{ + + if (semaphore_ptr == semaphore_0) + semaphore_0_puts++; +} + + +void event_0_notify(TX_EVENT_FLAGS_GROUP *event_flag_group_ptr) +{ + + if (event_flag_group_ptr == event_flags_0) + event_0_sets++; +} + + +void queue_0_notify(TX_QUEUE *queue_ptr) +{ + + if (queue_ptr == queue_0) + queue_0_sends++; +} + + +/* Define the module start function. */ + +void demo_module_start(ULONG id) +{ + +CHAR *pointer; + + /* Allocate all the objects. In MMU mode, modules cannot allocate control blocks within + their own memory area so they cannot corrupt the resident portion of ThreadX by overwriting + the control block(s). */ + txm_module_object_allocate((void *) &thread_0, sizeof(TX_THREAD)); + txm_module_object_allocate((void *) &thread_1, sizeof(TX_THREAD)); + txm_module_object_allocate((void *) &thread_2, sizeof(TX_THREAD)); + txm_module_object_allocate((void *) &thread_3, sizeof(TX_THREAD)); + txm_module_object_allocate((void *) &thread_4, sizeof(TX_THREAD)); + txm_module_object_allocate((void *) &thread_5, sizeof(TX_THREAD)); + txm_module_object_allocate((void *) &thread_6, sizeof(TX_THREAD)); + txm_module_object_allocate((void *) &thread_7, sizeof(TX_THREAD)); + txm_module_object_allocate((void *) &queue_0, sizeof(TX_QUEUE)); + txm_module_object_allocate((void *) &semaphore_0, sizeof(TX_SEMAPHORE)); + txm_module_object_allocate((void *) &mutex_0, sizeof(TX_MUTEX)); + txm_module_object_allocate((void *) &event_flags_0, sizeof(TX_EVENT_FLAGS_GROUP)); + txm_module_object_allocate((void *) &byte_pool_0, sizeof(TX_BYTE_POOL)); + txm_module_object_allocate((void *) &block_pool_0, sizeof(TX_BLOCK_POOL)); + + /* Create a byte memory pool from which to allocate the thread stacks. */ + tx_byte_pool_create(byte_pool_0, "module byte pool 0", demo_module_pool_space, DEMO_BYTE_POOL_SIZE); + + /* Put system definition stuff in here, e.g. thread creates and other assorted + create information. */ + + /* Allocate the stack for thread 0. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create the main thread. */ + tx_thread_create(thread_0, "module thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, + 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); + + + /* Allocate the stack for thread 1. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 1 and 2. These threads pass information through a ThreadX + message queue. It is also interesting to note that these threads have a time + slice. */ + tx_thread_create(thread_1, "module thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 2. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(thread_2, "module thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 3. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + An interesting thing here is that both threads share the same instruction area. */ + tx_thread_create(thread_3, "module thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 4. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(thread_4, "module thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 5. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create thread 5. This thread simply pends on an event flag which will be set + by thread_0. */ + tx_thread_create(thread_5, "module thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, + 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 6. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ + tx_thread_create(thread_6, "module thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 7. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(thread_7, "module thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the message queue. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_QUEUE_SIZE*sizeof(ULONG), TX_NO_WAIT); + + /* Create the message queue shared by threads 1 and 2. */ + tx_queue_create(queue_0, "module queue 0", TX_1_ULONG, pointer, DEMO_QUEUE_SIZE*sizeof(ULONG)); + + tx_queue_send_notify(queue_0, queue_0_notify); + + /* Create the semaphore used by threads 3 and 4. */ + tx_semaphore_create(semaphore_0, "module semaphore 0", 1); + + tx_semaphore_put_notify(semaphore_0, semaphore_0_notify); + + /* Create the event flags group used by threads 1 and 5. */ + tx_event_flags_create(event_flags_0, "module event flags 0"); + + tx_event_flags_set_notify(event_flags_0, event_0_notify); + + /* Create the mutex used by thread 6 and 7 without priority inheritance. */ + tx_mutex_create(mutex_0, "module mutex 0", TX_NO_INHERIT); + + /* Allocate the memory for a small block pool. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_BLOCK_POOL_SIZE, TX_NO_WAIT); + + /* Create a block memory pool to allocate a message buffer from. */ + tx_block_pool_create(block_pool_0, "module block pool 0", sizeof(ULONG), pointer, DEMO_BLOCK_POOL_SIZE); + + /* Allocate a block and release the block memory. */ + tx_block_allocate(block_pool_0, (VOID **) &pointer, TX_NO_WAIT); + + /* Release the block back to the pool. */ + tx_block_release(pointer); +} + + +/* Define the test threads. */ + +void thread_0_entry(ULONG thread_input) +{ + +UINT status; + + /* Test external/shared memory. */ + *(ULONG *) 0x90000000 = 0xdeadbeef; + *(ULONG *) 0x90000FFC = 0xfeed0add; + *(ULONG *) 0x90001000 = 0xfedcba01; + + /* This thread simply sits in while-forever-sleep loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_0_counter++; + + /* Sleep for 10 ticks. */ + tx_thread_sleep(10); + + /* Set event flag 0 to wakeup thread 5. */ + status = tx_event_flags_set(event_flags_0, 0x1, TX_OR); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_1_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sends messages to a queue shared by thread 2. */ + while(1) + { + + /* Increment the thread counter. */ + thread_1_counter++; + + /* Send message to queue 0. */ + status = tx_queue_send(queue_0, &thread_1_messages_sent, TX_WAIT_FOREVER); + + /* Check completion status. */ + if (status != TX_SUCCESS) + break; + + /* Increment the message sent. */ + thread_1_messages_sent++; + } +} + + +void thread_2_entry(ULONG thread_input) +{ + +ULONG received_message; +UINT status; + + /* This thread retrieves messages placed on the queue by thread 1. */ + while(1) + { + + /* Increment the thread counter. */ + thread_2_counter++; + + /* Retrieve a message from the queue. */ + status = tx_queue_receive(queue_0, &received_message, TX_WAIT_FOREVER); + + /* Check completion status and make sure the message is what we + expected. */ + if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) + break; + + /* Otherwise, all is okay. Increment the received message count. */ + thread_2_messages_received++; + } +} + + +void thread_3_and_4_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 3 and thread 4. As the loop + below shows, these function compete for ownership of semaphore_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 3) + thread_3_counter++; + else + thread_4_counter++; + + /* Get the semaphore with suspension. */ + status = tx_semaphore_get(semaphore_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the semaphore. */ + tx_thread_sleep(2); + + /* Release the semaphore. */ + status = tx_semaphore_put(semaphore_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_5_entry(ULONG thread_input) +{ + +UINT status; +ULONG actual_flags; + + + /* This thread simply waits for an event in a forever loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_5_counter++; + + /* Wait for event flag 0. */ + status = tx_event_flags_get(event_flags_0, 0x1, TX_OR_CLEAR, + &actual_flags, TX_WAIT_FOREVER); + + /* Check status. */ + if ((status != TX_SUCCESS) || (actual_flags != 0x1)) + break; + } +} + + +void thread_6_and_7_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 6 and thread 7. As the loop + below shows, these function compete for ownership of mutex_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 6) + thread_6_counter++; + else + thread_7_counter++; + + /* Get the mutex with suspension. */ + status = tx_mutex_get(mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Get the mutex again with suspension. This shows + that an owning thread may retrieve the mutex it + owns multiple times. */ + status = tx_mutex_get(mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the mutex. */ + tx_thread_sleep(2); + + /* Release the mutex. */ + status = tx_mutex_put(mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Release the mutex again. This will actually + release ownership since it was obtained twice. */ + status = tx_mutex_put(mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + diff --git a/ports_module/cortex_a7/iar/example_build/sample_threadx_module.ewd b/ports_module/cortex_a7/iar/example_build/sample_threadx_module.ewd new file mode 100644 index 00000000..e785027c --- /dev/null +++ b/ports_module/cortex_a7/iar/example_build/sample_threadx_module.ewd @@ -0,0 +1,3088 @@ +<?xml version="1.0" encoding="UTF-8"?> +<project> + <fileVersion>3</fileVersion> + <configuration> + <name>Debug</name> + <toolchain> + <name>ARM</name> + </toolchain> + <debug>1</debug> + <settings> + <name>C-SPY</name> + <archiveVersion>2</archiveVersion> + <data> + <version>32</version> + <wantNonLocal>1</wantNonLocal> + <debug>1</debug> + <option> + <name>CInput</name> + <state>1</state> + </option> + <option> + <name>CEndian</name> + <state>1</state> + </option> + <option> + <name>CProcessor</name> + <state>1</state> + </option> + <option> + <name>OCVariant</name> + <state>0</state> + </option> + <option> + <name>MacOverride</name> + <state>0</state> + </option> + <option> + <name>MacFile</name> + <state></state> + </option> + <option> + <name>MemOverride</name> + <state>0</state> + </option> + <option> + <name>MemFile</name> + <state></state> + </option> + <option> + <name>RunToEnable</name> + <state>1</state> + </option> + <option> + <name>RunToName</name> + <state>main</state> + </option> + <option> + <name>CExtraOptionsCheck</name> + <state>0</state> + </option> + <option> + <name>CExtraOptions</name> + <state></state> + </option> + <option> + <name>CFpuProcessor</name> + <state>1</state> + </option> + <option> + <name>OCDDFArgumentProducer</name> + <state></state> + </option> + <option> + <name>OCDownloadSuppressDownload</name> + <state>0</state> + </option> + <option> + <name>OCDownloadVerifyAll</name> + <state>0</state> + </option> + <option> + <name>OCProductVersion</name> + <state>8.40.2.22864</state> + </option> + <option> + <name>OCDynDriverList</name> + <state>ARMSIM_ID</state> + </option> + <option> + <name>OCLastSavedByProductVersion</name> + <state>8.50.4.26131</state> + </option> + <option> + <name>UseFlashLoader</name> + <state>1</state> + </option> + <option> + <name>CLowLevel</name> + <state>1</state> + </option> + <option> + <name>OCBE8Slave</name> + <state>1</state> + </option> + <option> + <name>MacFile2</name> + <state></state> + </option> + <option> + <name>CDevice</name> + <state>1</state> + </option> + <option> + <name>FlashLoadersV3</name> + <state>$TOOLKIT_DIR$\config\flashloader\</state> + </option> + <option> + <name>OCImagesSuppressCheck1</name> + <state>0</state> + </option> + <option> + <name>OCImagesPath1</name> + <state></state> + </option> + <option> + <name>OCImagesSuppressCheck2</name> + <state>0</state> + </option> + <option> + <name>OCImagesPath2</name> + <state></state> + </option> + <option> + <name>OCImagesSuppressCheck3</name> + <state>0</state> + </option> + <option> + <name>OCImagesPath3</name> + <state></state> + </option> + <option> + <name>OverrideDefFlashBoard</name> + <state>0</state> + </option> + <option> + <name>OCImagesOffset1</name> + <state></state> + </option> + <option> + <name>OCImagesOffset2</name> + <state></state> + </option> + <option> + <name>OCImagesOffset3</name> + <state></state> + </option> + <option> + <name>OCImagesUse1</name> + <state>0</state> + </option> + <option> + <name>OCImagesUse2</name> + <state>0</state> + </option> + <option> + <name>OCImagesUse3</name> + <state>0</state> + </option> + <option> + <name>OCDeviceConfigMacroFile</name> + <state>1</state> + </option> + <option> + <name>OCDebuggerExtraOption</name> + <state>1</state> + </option> + <option> + <name>OCAllMTBOptions</name> + <state>1</state> + </option> + <option> + <name>OCMulticoreNrOfCores</name> + <state>1</state> + </option> + <option> + <name>OCMulticoreWorkspace</name> + <state></state> + </option> + <option> + <name>OCMulticoreSlaveProject</name> + <state></state> + </option> + <option> + <name>OCMulticoreSlaveConfiguration</name> + <state></state> + </option> + <option> + <name>OCDownloadExtraImage</name> + <state>1</state> + </option> + <option> + <name>OCAttachSlave</name> + <state>0</state> + </option> + <option> + <name>MassEraseBeforeFlashing</name> + <state>0</state> + </option> + <option> + <name>OCMulticoreNrOfCoresSlave</name> + <state>1</state> + </option> + <option> + <name>OCMulticoreAMPConfigType</name> + <state>0</state> + </option> + <option> + <name>OCMulticoreSessionFile</name> + <state></state> + </option> + <option> + <name>OCTpiuBaseOption</name> + <state>1</state> + </option> + </data> + </settings> + <settings> + <name>ARMSIM_ID</name> + <archiveVersion>2</archiveVersion> + <data> + <version>1</version> + <wantNonLocal>1</wantNonLocal> + <debug>1</debug> + <option> + <name>OCSimDriverInfo</name> + <state>1</state> + </option> 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</option> + <option> + <name>CatchV8ARReset</name> + <state>0</state> + </option> + <option> + <name>CatchV8AREREL1NS</name> + <state>0</state> + </option> + <option> + <name>CatchV8AREREL1S</name> + <state>0</state> + </option> + <option> + <name>CatchV8AREREL2NS</name> + <state>0</state> + </option> + <option> + <name>CatchV8AREREL3S</name> + <state>0</state> + </option> + <option> + <name>CatchV8AREEL1NS</name> + <state>0</state> + </option> + <option> + <name>CatchV8ARREL1NS</name> + <state>0</state> + </option> + <option> + <name>CatchV8AREEL1S</name> + <state>0</state> + </option> + <option> + <name>CatchV8ARREL1S</name> + <state>0</state> + </option> + <option> + <name>CatchV8AREEL2NS</name> + <state>0</state> + </option> + <option> + <name>CatchV8ARREL2NS</name> + <state>0</state> + </option> + <option> + <name>CatchV8AREEL3S</name> + <state>0</state> + </option> + <option> + <name>CatchV8ARREL3S</name> + <state>0</state> + </option> + </data> + </settings> + <settings> + <name>JLINK_ID</name> + <archiveVersion>2</archiveVersion> + <data> + <version>16</version> + <wantNonLocal>1</wantNonLocal> + <debug>0</debug> + <option> + <name>JLinkSpeed</name> + <state>1000</state> + </option> + <option> + <name>CCJLinkDoLogfile</name> + <state>0</state> + </option> + <option> + <name>CCJLinkLogFile</name> + <state>$PROJ_DIR$\cspycomm.log</state> + </option> + <option> + <name>CCJLinkHWResetDelay</name> + <state>0</state> + </option> + <option> + <name>OCDriverInfo</name> + <state>1</state> + </option> + <option> + <name>JLinkInitialSpeed</name> + <state>1000</state> + </option> + <option> + <name>CCDoJlinkMultiTarget</name> + <state>0</state> + </option> + <option> + <name>CCScanChainNonARMDevices</name> + <state>0</state> + </option> + <option> + <name>CCJLinkMultiTarget</name> + <state>0</state> + </option> + <option> + <name>CCJLinkIRLength</name> + <state>0</state> + </option> + <option> + <name>CCJLinkCommRadio</name> + <state>0</state> + </option> + <option> + <name>CCJLinkTCPIP</name> + <state>aaa.bbb.ccc.ddd</state> + </option> + <option> + <name>CCJLinkSpeedRadioV2</name> + <state>0</state> + </option> + <option> + <name>CCUSBDevice</name> + <version>1</version> + <state>1</state> + </option> + <option> + <name>CCRDICatchReset</name> + <state>0</state> + </option> + <option> + <name>CCRDICatchUndef</name> + <state>0</state> + </option> + <option> + <name>CCRDICatchSWI</name> + <state>0</state> + </option> + <option> + <name>CCRDICatchData</name> + <state>0</state> + </option> + <option> + <name>CCRDICatchPrefetch</name> + <state>0</state> + </option> + <option> + <name>CCRDICatchIRQ</name> + <state>0</state> + </option> + <option> + <name>CCRDICatchFIQ</name> + <state>0</state> + </option> + <option> + <name>CCJLinkBreakpointRadio</name> + <state>0</state> + </option> + <option> + <name>CCJLinkDoUpdateBreakpoints</name> + <state>0</state> + </option> + <option> + <name>CCJLinkUpdateBreakpoints</name> + <state>_call_main</state> + </option> + <option> + <name>CCJLinkInterfaceRadio</name> + <state>0</state> + </option> + <option> + <name>CCJLinkResetList</name> + <version>6</version> + <state>5</state> + </option> + <option> + <name>CCJLinkInterfaceCmdLine</name> + <state>0</state> + </option> + <option> + <name>CCCatchCORERESET</name> + <state>0</state> + </option> + <option> + <name>CCCatchMMERR</name> + <state>0</state> + </option> + <option> + <name>CCCatchNOCPERR</name> + <state>0</state> + </option> + <option> + <name>CCCatchCHRERR</name> + <state>0</state> + </option> + <option> + <name>CCCatchSTATERR</name> + <state>0</state> + </option> + <option> + <name>CCCatchBUSERR</name> + <state>0</state> + </option> + <option> + <name>CCCatchINTERR</name> + <state>0</state> + </option> + <option> + <name>CCCatchSFERR</name> + <state>0</state> + </option> + <option> + <name>CCCatchHARDERR</name> + <state>0</state> + </option> + <option> + <name>CCCatchDummy</name> + <state>0</state> + </option> + <option> + <name>OCJLinkScriptFile</name> + <state>1</state> + </option> + <option> + <name>CCJLinkUsbSerialNo</name> + <state></state> + </option> + <option> + <name>CCTcpIpAlt</name> + <version>0</version> + <state>0</state> + </option> + <option> + <name>CCJLinkTcpIpSerialNo</name> + <state></state> + </option> + <option> + <name>CCCpuClockEdit</name> + <state></state> + </option> + <option> + <name>CCSwoClockAuto</name> + <state>0</state> + </option> + <option> + <name>CCSwoClockEdit</name> + <state>2000</state> + </option> + <option> + <name>OCJLinkTraceSource</name> + <state>0</state> + </option> + <option> + <name>OCJLinkTraceSourceDummy</name> + <state>0</state> + </option> + <option> + <name>OCJLinkDeviceName</name> + <state>1</state> + </option> + </data> + </settings> + <settings> + <name>LMIFTDI_ID</name> + <archiveVersion>2</archiveVersion> + <data> + <version>3</version> + <wantNonLocal>1</wantNonLocal> + <debug>0</debug> + <option> + <name>OCDriverInfo</name> + <state>1</state> + </option> + <option> + <name>LmiftdiSpeed</name> + <state>500</state> + </option> + <option> + <name>CCLmiftdiDoLogfile</name> + <state>0</state> + </option> + <option> + <name>CCLmiftdiLogFile</name> + <state>$PROJ_DIR$\cspycomm.log</state> + </option> + <option> + <name>CCLmiFtdiInterfaceRadio</name> + <state>0</state> + </option> + <option> + <name>CCLmiFtdiInterfaceCmdLine</name> + <state>0</state> + </option> + <option> + <name>CCLmiftdiUsbSerialNo</name> + <state></state> + </option> + <option> + <name>CCLmiftdiUsbSerialNoSelect</name> + <state>0</state> + </option> + <option> + <name>CCLmiftdiResetList</name> + <version>0</version> + <state>0</state> + </option> + </data> + </settings> + <settings> + <name>NULINK_ID</name> + <archiveVersion>2</archiveVersion> + <data> + <version>0</version> + <wantNonLocal>1</wantNonLocal> + <debug>0</debug> + <option> + <name>OCDriverInfo</name> + <state>1</state> + </option> + <option> + <name>DoLogfile</name> + <state>0</state> + </option> + <option> + <name>LogFile</name> + <state>$PROJ_DIR$\cspycomm.log</state> + </option> + </data> + </settings> + <settings> + <name>PEMICRO_ID</name> + <archiveVersion>2</archiveVersion> + <data> + <version>3</version> + <wantNonLocal>1</wantNonLocal> + <debug>0</debug> + <option> + <name>OCDriverInfo</name> + <state>1</state> + </option> + <option> + <name>CCJPEMicroShowSettings</name> + <state>0</state> + </option> + <option> + <name>DoLogfile</name> + <state>0</state> + </option> + <option> + <name>LogFile</name> + <state>$PROJ_DIR$\cspycomm.log</state> + </option> + </data> + </settings> + <settings> + <name>STLINK_ID</name> + <archiveVersion>2</archiveVersion> + <data> + <version>7</version> + <wantNonLocal>1</wantNonLocal> + <debug>0</debug> + <option> + <name>OCDriverInfo</name> + <state>1</state> + </option> + <option> + <name>CCSTLinkInterfaceRadio</name> + <state>0</state> + </option> + <option> + <name>CCSTLinkInterfaceCmdLine</name> + <state>0</state> + </option> + <option> + <name>CCSTLinkResetList</name> + <version>3</version> + <state>0</state> + </option> + <option> + <name>CCCpuClockEdit</name> + <state></state> + </option> + <option> + <name>CCSwoClockAuto</name> + <state>1</state> + </option> + <option> + <name>CCSwoClockEdit</name> + <state>2000</state> + </option> + <option> + <name>DoLogfile</name> + <state>0</state> + </option> + <option> + <name>LogFile</name> + <state>$PROJ_DIR$\cspycomm.log</state> + </option> + <option> + <name>CCSTLinkDoUpdateBreakpoints</name> + <state>0</state> + </option> + <option> + <name>CCSTLinkUpdateBreakpoints</name> + <state>_call_main</state> + </option> + <option> + <name>CCSTLinkCatchCORERESET</name> + <state>0</state> + </option> + <option> + <name>CCSTLinkCatchMMERR</name> + <state>0</state> + </option> + <option> + <name>CCSTLinkCatchNOCPERR</name> + <state>0</state> + </option> + <option> + <name>CCSTLinkCatchCHRERR</name> + <state>0</state> + </option> + <option> + <name>CCSTLinkCatchSTATERR</name> + <state>0</state> + </option> + <option> + <name>CCSTLinkCatchBUSERR</name> + <state>0</state> + </option> + <option> + <name>CCSTLinkCatchINTERR</name> + <state>0</state> + </option> + <option> + <name>CCSTLinkCatchSFERR</name> + <state>0</state> + </option> + <option> + <name>CCSTLinkCatchHARDERR</name> + <state>0</state> + </option> + <option> + <name>CCSTLinkCatchDummy</name> + <state>0</state> + </option> + <option> + <name>CCSTLinkUsbSerialNo</name> + <state></state> + </option> + <option> + <name>CCSTLinkUsbSerialNoSelect</name> + <state>0</state> + </option> + <option> + <name>CCSTLinkJtagSpeedList</name> + <version>2</version> + <state>0</state> + </option> + <option> + <name>CCSTLinkDAPNumber</name> + <state></state> + </option> + <option> + <name>CCSTLinkDebugAccessPortRadio</name> + <state>0</state> + </option> + <option> + <name>CCSTLinkUseServerSelect</name> + <state>0</state> + </option> + <option> + <name>CCSTLinkProbeList</name> + <version>1</version> + <state>0</state> + </option> + </data> + </settings> + <settings> + <name>THIRDPARTY_ID</name> + <archiveVersion>2</archiveVersion> + <data> + <version>0</version> + <wantNonLocal>1</wantNonLocal> + <debug>0</debug> + <option> + <name>CThirdPartyDriverDll</name> + <state>###Uninitialized###</state> + </option> + <option> + <name>CThirdPartyLogFileCheck</name> + <state>0</state> + </option> + <option> + <name>CThirdPartyLogFileEditB</name> + <state>$PROJ_DIR$\cspycomm.log</state> + </option> + <option> + <name>OCDriverInfo</name> + <state>1</state> + </option> + </data> + </settings> + <settings> + <name>TIFET_ID</name> + <archiveVersion>2</archiveVersion> + <data> + <version>1</version> + <wantNonLocal>1</wantNonLocal> + <debug>0</debug> + <option> + <name>OCDriverInfo</name> + <state>1</state> + </option> + <option> + <name>CCMSPFetResetList</name> + <version>0</version> + <state>0</state> + </option> + <option> + <name>CCMSPFetInterfaceRadio</name> + <state>0</state> + </option> + <option> + <name>CCMSPFetInterfaceCmdLine</name> + <state>0</state> + </option> + <option> + <name>CCMSPFetTargetVccTypeDefault</name> + <state>0</state> + </option> + <option> + <name>CCMSPFetTargetVoltage</name> + <state>###Uninitialized###</state> + </option> + <option> + <name>CCMSPFetVCCDefault</name> + <state>1</state> + </option> + <option> + <name>CCMSPFetTargetSettlingtime</name> + <state>0</state> + </option> + <option> + <name>CCMSPFetRadioJtagSpeedType</name> + <state>1</state> + </option> + <option> + <name>CCMSPFetConnection</name> + <version>0</version> + <state>0</state> + </option> + <option> + <name>CCMSPFetUsbComPort</name> + <state>Automatic</state> + </option> + <option> + <name>CCMSPFetAllowAccessToBSL</name> + <state>0</state> + </option> + <option> + <name>CCMSPFetDoLogfile</name> + <state>0</state> + </option> + <option> + <name>CCMSPFetLogFile</name> + <state>$PROJ_DIR$\cspycomm.log</state> + </option> + <option> + <name>CCMSPFetRadioEraseFlash</name> + <state>1</state> + </option> + </data> + </settings> + <settings> + <name>XDS100_ID</name> + <archiveVersion>2</archiveVersion> + <data> + <version>9</version> + <wantNonLocal>1</wantNonLocal> + <debug>0</debug> + <option> + <name>OCDriverInfo</name> + <state>1</state> + </option> + <option> + <name>TIPackageOverride</name> + <state>0</state> + </option> + <option> + <name>TIPackage</name> + <state></state> + </option> + <option> + <name>BoardFile</name> + <state></state> + </option> + <option> + <name>DoLogfile</name> + <state>0</state> + </option> + <option> + <name>LogFile</name> + <state>$PROJ_DIR$\cspycomm.log</state> + </option> + <option> + <name>CCXds100BreakpointRadio</name> + <state>0</state> + </option> + <option> + <name>CCXds100DoUpdateBreakpoints</name> + <state>0</state> + </option> + <option> + <name>CCXds100UpdateBreakpoints</name> + <state>_call_main</state> + </option> + <option> + <name>CCXds100CatchReset</name> + <state>0</state> + </option> + <option> + <name>CCXds100CatchUndef</name> + <state>0</state> + </option> + <option> + <name>CCXds100CatchSWI</name> + <state>0</state> + </option> + <option> + <name>CCXds100CatchData</name> + <state>0</state> + </option> + <option> + <name>CCXds100CatchPrefetch</name> + <state>0</state> + </option> + <option> + <name>CCXds100CatchIRQ</name> + <state>0</state> + </option> + <option> + <name>CCXds100CatchFIQ</name> + <state>0</state> + </option> + <option> + <name>CCXds100CatchCORERESET</name> + <state>0</state> + </option> + <option> + <name>CCXds100CatchMMERR</name> + <state>0</state> + </option> + <option> + <name>CCXds100CatchNOCPERR</name> + <state>0</state> + </option> + <option> + <name>CCXds100CatchCHRERR</name> + <state>0</state> + </option> + <option> + <name>CCXds100CatchSTATERR</name> + <state>0</state> + </option> + <option> + <name>CCXds100CatchBUSERR</name> + <state>0</state> + </option> + <option> + <name>CCXds100CatchINTERR</name> + <state>0</state> + </option> + <option> + <name>CCXds100CatchSFERR</name> + <state>0</state> + </option> + <option> + <name>CCXds100CatchHARDERR</name> + <state>0</state> + </option> + <option> + <name>CCXds100CatchDummy</name> + <state>0</state> + </option> + <option> + <name>CCXds100CpuClockEdit</name> + <state></state> + </option> + <option> + <name>CCXds100SwoClockAuto</name> + <state>0</state> + </option> + <option> + <name>CCXds100SwoClockEdit</name> + <state>1000</state> + </option> + <option> + <name>CCXds100HWResetDelay</name> + <state>0</state> + </option> + <option> + <name>CCXds100ResetList</name> + <version>1</version> + <state>0</state> + </option> + <option> + <name>CCXds100UsbSerialNo</name> + <state></state> + </option> + <option> + <name>CCXds100UsbSerialNoSelect</name> + <state>0</state> + </option> + <option> + <name>CCXds100JtagSpeedList</name> + <version>0</version> + <state>0</state> + </option> + <option> + <name>CCXds100InterfaceRadio</name> + <state>2</state> + </option> + <option> + <name>CCXds100InterfaceCmdLine</name> + <state>0</state> + </option> + <option> + <name>CCXds100ProbeList</name> + <version>0</version> + <state>3</state> + </option> + <option> + <name>CCXds100SWOPortRadio</name> + <state>0</state> + </option> + <option> + <name>CCXds100SWOPort</name> + <state>1</state> + </option> + <option> + <name>CCXDSTargetVccEnable</name> + <state>0</state> + </option> + <option> + <name>CCXDSTargetVoltage</name> + <state>###Uninitialized###</state> + </option> + <option> + <name>OCXDSDigitalStatesConfigFile</name> + <state>1</state> + </option> + <option> + <name>OCSelectedCoreName</name> + <state>1</state> + </option> + </data> + </settings> + <debuggerPlugins> + <plugin> + <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$TOOLKIT_DIR$\plugins\rtos\FreeRtos\FreeRtosArmPlugin.ENU.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin2.ENU.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm9.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm9BE.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + </debuggerPlugins> + </configuration> +</project> diff --git a/ports_module/cortex_a7/iar/example_build/sample_threadx_module.ewp b/ports_module/cortex_a7/iar/example_build/sample_threadx_module.ewp new file mode 100644 index 00000000..6141e05c --- /dev/null +++ b/ports_module/cortex_a7/iar/example_build/sample_threadx_module.ewp @@ -0,0 +1,2133 @@ +<?xml version="1.0" encoding="UTF-8"?> +<project> + <fileVersion>3</fileVersion> + <configuration> + <name>Debug</name> + <toolchain> + <name>ARM</name> + </toolchain> + <debug>1</debug> + <settings> + <name>General</name> + <archiveVersion>3</archiveVersion> + <data> + <version>34</version> + <wantNonLocal>1</wantNonLocal> + <debug>1</debug> + <option> + <name>BrowseInfoPath</name> + <state>Debug\BrowseInfo</state> + </option> + <option> + <name>ExePath</name> + <state>Debug\Exe</state> + </option> + <option> + <name>ObjPath</name> + <state>Debug\Obj</state> + </option> + <option> + <name>ListPath</name> + <state>Debug\List</state> + </option> + <option> + <name>GEndianMode</name> + <state>0</state> + </option> + <option> + <name>Input description</name> + <state>Full formatting, without multibyte support.</state> + </option> + <option> + <name>Output description</name> + <state>Full formatting, without multibyte support.</state> + </option> + <option> + <name>GOutputBinary</name> + <state>0</state> + </option> + <option> + <name>OGCoreOrChip</name> + <state>0</state> + </option> + <option> + <name>GRuntimeLibSelect</name> + <version>0</version> + <state>1</state> + </option> + <option> + <name>GRuntimeLibSelectSlave</name> + <version>0</version> + <state>1</state> + </option> + <option> + <name>RTDescription</name> + <state>Use the normal configuration of the C/C++ runtime library. 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<option> + <name>IlinkLogCrtRoutineSelection</name> + <state>0</state> + </option> + <option> + <name>IlinkLogFragmentInfo</name> + <state>0</state> + </option> + <option> + <name>IlinkLogInlining</name> + <state>0</state> + </option> + <option> + <name>IlinkLogMerging</name> + <state>0</state> + </option> + <option> + <name>IlinkDemangle</name> + <state>0</state> + </option> + <option> + <name>IlinkWrapperFileEnable</name> + <state>0</state> + </option> + <option> + <name>IlinkWrapperFile</name> + <state></state> + </option> + </data> + </settings> + <settings> + <name>IARCHIVE</name> + <archiveVersion>0</archiveVersion> + <data> + <version>0</version> + <wantNonLocal>1</wantNonLocal> + <debug>1</debug> + <option> + <name>IarchiveInputs</name> + <state></state> + </option> + <option> + <name>IarchiveOverride</name> + <state>0</state> + </option> + <option> + <name>IarchiveOutput</name> + <state>###Unitialized###</state> + </option> + </data> + </settings> + <settings> + <name>Coder</name> + <archiveVersion>0</archiveVersion> + <data /> + </settings> + </configuration> + <configuration> + <name>Release</name> + <toolchain> + <name>ARM</name> + </toolchain> + <debug>0</debug> + <settings> + <name>General</name> + <archiveVersion>3</archiveVersion> + <data> + <version>34</version> + <wantNonLocal>1</wantNonLocal> + <debug>0</debug> + <option> + <name>BrowseInfoPath</name> + <state>Release\BrowseInfo</state> + </option> + <option> + <name>ExePath</name> + <state>Release\Exe</state> + </option> + <option> + <name>ObjPath</name> + <state>Release\Obj</state> + </option> + <option> + <name>ListPath</name> + <state>Release\List</state> + </option> + <option> + <name>GEndianMode</name> + <state>0</state> + </option> + <option> + <name>Input description</name> + <state></state> + </option> + <option> + <name>Output description</name> + <state></state> + </option> + <option> + <name>GOutputBinary</name> + <state>0</state> + </option> + <option> + <name>OGCoreOrChip</name> + <state>0</state> + </option> + <option> + <name>GRuntimeLibSelect</name> + <version>0</version> + <state>1</state> + </option> + <option> + <name>GRuntimeLibSelectSlave</name> + <version>0</version> + <state>1</state> + </option> + <option> + <name>RTDescription</name> + <state></state> + </option> + <option> + <name>OGProductVersion</name> + <state>6.10.1.52170</state> + </option> + <option> + <name>OGLastSavedByProductVersion</name> + <state>7.70.1.11471</state> + </option> + <option> + <name>OGChipSelectEditMenu</name> + <state>Default None</state> + </option> + <option> + <name>GenLowLevelInterface</name> + <state>0</state> + </option> + <option> + <name>GEndianModeBE</name> + <state>0</state> + </option> + <option> + <name>OGBufferedTerminalOutput</name> + <state>0</state> + </option> + <option> + <name>GenStdoutInterface</name> + <state>0</state> + </option> + <option> + <name>RTConfigPath2</name> + <state></state> + </option> + <option> + <name>GBECoreSlave</name> + <version>31</version> + <state>0</state> + </option> + <option> + <name>OGUseCmsis</name> + <state>0</state> + </option> + <option> + <name>OGUseCmsisDspLib</name> + <state>0</state> + </option> + <option> + <name>GRuntimeLibThreads</name> + <state>0</state> + </option> + <option> + <name>CoreVariant</name> + <version>31</version> + <state>0</state> + </option> + <option> + <name>GFPUDeviceSlave</name> + <state>Default None</state> + </option> + <option> + <name>FPU2</name> + <version>0</version> + <state>0</state> + </option> + <option> + <name>NrRegs</name> + <version>0</version> + <state>0</state> + </option> + <option> + <name>NEON</name> + <state>0</state> + </option> + <option> + <name>GFPUCoreSlave2</name> + <version>31</version> + <state>0</state> + </option> + <option> + <name>OGCMSISPackSelectDevice</name> + </option> + <option> + <name>OgLibHeap</name> + <state>0</state> + </option> + <option> + <name>OGLibAdditionalLocale</name> + <state>0</state> + </option> + <option> + <name>OGPrintfVariant</name> + <version>0</version> + <state>1</state> + </option> + <option> + <name>OGPrintfMultibyteSupport</name> + <state>0</state> + </option> + <option> + <name>OGScanfVariant</name> + <version>0</version> + <state>1</state> + </option> + <option> + <name>OGScanfMultibyteSupport</name> + <state>0</state> + </option> + <option> + <name>GenLocaleTags</name> + <state></state> + </option> + <option> + <name>GenLocaleDisplayOnly</name> + <state></state> + </option> + <option> + <name>DSPExtension</name> + <state>0</state> + </option> + <option> + <name>TrustZone</name> + <state>0</state> + </option> + <option> + <name>TrustZoneModes</name> + <version>0</version> + <state>0</state> + </option> + <option> + <name>OGAarch64Abi</name> + <state>0</state> + </option> + <option> + <name>OG_32_64Device</name> + <state>0</state> + </option> + <option> + <name>BuildFilesPath</name> + <state>Release</state> + </option> + </data> + </settings> + <settings> + <name>ICCARM</name> + <archiveVersion>2</archiveVersion> + <data> + <version>37</version> + <wantNonLocal>1</wantNonLocal> + <debug>0</debug> + <option> + <name>CCOptimizationNoSizeConstraints</name> + <state>0</state> + </option> + <option> + <name>CCDefines</name> + <state>NDEBUG</state> + </option> + <option> + <name>CCPreprocFile</name> + <state>0</state> + </option> + <option> + <name>CCPreprocComments</name> + <state>0</state> + </option> + <option> + <name>CCPreprocLine</name> + <state>0</state> + </option> + <option> + <name>CCListCFile</name> + <state>0</state> + </option> + <option> + <name>CCListCMnemonics</name> + <state>0</state> + </option> + <option> + <name>CCListCMessages</name> + <state>0</state> + </option> + <option> + <name>CCListAssFile</name> + <state>0</state> + </option> + <option> + <name>CCListAssSource</name> + <state>0</state> + </option> + <option> + <name>CCEnableRemarks</name> + <state>0</state> + </option> + <option> + <name>CCDiagSuppress</name> + <state></state> + </option> + <option> + <name>CCDiagRemark</name> + <state></state> + </option> + <option> + <name>CCDiagWarning</name> + <state></state> + </option> + <option> + <name>CCDiagError</name> + <state></state> + </option> + <option> + <name>CCObjPrefix</name> + <state>1</state> + </option> + <option> + <name>CCAllowList</name> + <version>1</version> + <state>11111110</state> + </option> + <option> + <name>CCDebugInfo</name> + <state>0</state> + </option> + <option> + <name>IEndianMode</name> + <state>1</state> + </option> + <option> + <name>IProcessor</name> + <state>1</state> + </option> + <option> + <name>IExtraOptionsCheck</name> + <state>0</state> + </option> + <option> + <name>IExtraOptions</name> + <state></state> + </option> + <option> + <name>CCLangConformance</name> + <state>0</state> + </option> + <option> + <name>CCSignedPlainChar</name> + <state>1</state> + </option> + <option> + <name>CCRequirePrototypes</name> + <state>0</state> + </option> + <option> + <name>CCDiagWarnAreErr</name> + <state>0</state> + </option> + <option> + <name>CCCompilerRuntimeInfo</name> + <state>0</state> + </option> + <option> + <name>IFpuProcessor</name> + <state>1</state> + </option> + <option> + <name>OutputFile</name> + <state></state> + </option> + <option> + <name>CCLibConfigHeader</name> + <state>1</state> + </option> + <option> + <name>PreInclude</name> + <state></state> + </option> + <option> + <name>CCIncludePath2</name> + <state></state> + </option> + <option> + <name>CCStdIncCheck</name> + <state>0</state> + </option> + <option> + <name>CCCodeSection</name> + <state>.text</state> + </option> + <option> + <name>IProcessorMode2</name> + <state>1</state> + </option> + <option> + <name>CCOptLevel</name> + <state>3</state> + </option> + <option> + <name>CCOptStrategy</name> + <version>0</version> + <state>0</state> + </option> + <option> + <name>CCOptLevelSlave</name> + <state>1</state> + </option> + <option> + <name>CCPosIndRopi</name> + <state>0</state> + </option> + <option> + <name>CCPosIndRwpi</name> + <state>0</state> + </option> + <option> + <name>CCPosIndNoDynInit</name> + <state>0</state> + </option> + <option> + <name>IccLang</name> + <state>0</state> + </option> + <option> + <name>IccCDialect</name> + <state>1</state> + </option> + <option> + <name>IccAllowVLA</name> + <state>0</state> + </option> + <option> + <name>IccStaticDestr</name> + <state>1</state> + </option> + <option> + <name>IccCppInlineSemantics</name> + <state>0</state> + </option> + <option> + <name>IccCmsis</name> + <state>1</state> + </option> + <option> + <name>IccFloatSemantics</name> + <state>0</state> + </option> + <option> + <name>CCNoLiteralPool</name> + <state>0</state> + </option> + <option> + <name>CCOptStrategySlave</name> + <version>0</version> + <state>0</state> + </option> + <option> + <name>CCGuardCalls</name> + <state>1</state> + </option> + <option> + <name>CCEncSource</name> + <state>0</state> + </option> + <option> + <name>CCEncOutput</name> + <state>0</state> + </option> + <option> + <name>CCEncOutputBom</name> + <state>1</state> + </option> + <option> + <name>CCEncInput</name> + <state>0</state> + </option> + <option> + <name>IccExceptions2</name> + <state>0</state> + </option> + <option> + <name>IccRTTI2</name> + <state>0</state> + </option> + <option> + <name>OICompilerExtraOption</name> + <state>1</state> + </option> + <option> + <name>CCStackProtection</name> + <state>0</state> + </option> + </data> + </settings> + <settings> + <name>AARM</name> + <archiveVersion>2</archiveVersion> + <data> + <version>11</version> + <wantNonLocal>1</wantNonLocal> + <debug>0</debug> + <option> + <name>AObjPrefix</name> + <state>1</state> + </option> + <option> + <name>AEndian</name> + <state>1</state> + </option> + <option> + <name>ACaseSensitivity</name> + <state>1</state> + </option> + <option> + <name>MacroChars</name> + <version>0</version> + <state>0</state> + </option> + <option> + <name>AWarnEnable</name> + <state>0</state> + </option> + <option> + <name>AWarnWhat</name> + <state>0</state> + </option> + <option> + <name>AWarnOne</name> + <state></state> + </option> + <option> + <name>AWarnRange1</name> + <state></state> + </option> + <option> + <name>AWarnRange2</name> + <state></state> + </option> + <option> + <name>ADebug</name> + <state>0</state> + </option> + <option> + <name>AltRegisterNames</name> + <state>0</state> + </option> + <option> + <name>ADefines</name> + <state></state> + </option> + <option> + <name>AList</name> + <state>0</state> + </option> + <option> + <name>AListHeader</name> + <state>1</state> + </option> + <option> + <name>AListing</name> + <state>1</state> + </option> + <option> + <name>Includes</name> + <state>0</state> + </option> + <option> + <name>MacDefs</name> + <state>0</state> + </option> + <option> + <name>MacExps</name> + <state>1</state> + </option> + <option> + <name>MacExec</name> + <state>0</state> + </option> + <option> + <name>OnlyAssed</name> + <state>0</state> + </option> + <option> + <name>MultiLine</name> + <state>0</state> + </option> + <option> + <name>PageLengthCheck</name> + <state>0</state> + </option> + <option> + <name>PageLength</name> + <state>80</state> + </option> + <option> + <name>TabSpacing</name> + <state>8</state> + </option> + <option> + <name>AXRef</name> + <state>0</state> + </option> + <option> + <name>AXRefDefines</name> + <state>0</state> + </option> + <option> + <name>AXRefInternal</name> + <state>0</state> + </option> + <option> + <name>AXRefDual</name> + <state>0</state> + </option> + <option> + <name>AProcessor</name> + <state>1</state> + </option> + <option> + <name>AFpuProcessor</name> + <state>1</state> + </option> + <option> + <name>AOutputFile</name> + <state></state> + </option> + <option> + <name>ALimitErrorsCheck</name> + <state>0</state> + </option> + <option> + <name>ALimitErrorsEdit</name> + <state>100</state> + </option> + <option> + <name>AIgnoreStdInclude</name> + <state>0</state> + </option> + <option> + <name>AUserIncludes</name> + <state></state> + </option> + <option> + <name>AExtraOptionsCheckV2</name> + <state>0</state> + </option> + <option> + <name>AExtraOptionsV2</name> + <state></state> + </option> + <option> + <name>AsmNoLiteralPool</name> + <state>0</state> + </option> + <option> + <name>PreInclude</name> + <state></state> + </option> + </data> + </settings> + <settings> + <name>OBJCOPY</name> + <archiveVersion>0</archiveVersion> + <data> + <version>1</version> + <wantNonLocal>1</wantNonLocal> + <debug>0</debug> + <option> + <name>OOCOutputFormat</name> + <version>3</version> + <state>0</state> + </option> + <option> + <name>OCOutputOverride</name> + <state>0</state> + </option> + <option> + <name>OOCOutputFile</name> + <state></state> + </option> + <option> + <name>OOCCommandLineProducer</name> + <state>1</state> + </option> + <option> + <name>OOCObjCopyEnable</name> + <state>0</state> + </option> + </data> + </settings> + <settings> + <name>CUSTOM</name> + <archiveVersion>3</archiveVersion> + <data> + <extensions></extensions> + <cmdline></cmdline> + <hasPrio>0</hasPrio> + <buildSequence>inputOutputBased</buildSequence> + </data> + </settings> + <settings> + <name>BUILDACTION</name> + <archiveVersion>1</archiveVersion> + <data> + <prebuild></prebuild> + <postbuild></postbuild> + </data> + </settings> + <settings> + <name>ILINK</name> + <archiveVersion>0</archiveVersion> + <data> + <version>26</version> + <wantNonLocal>1</wantNonLocal> + <debug>0</debug> + <option> + <name>IlinkLibIOConfig</name> + <state>1</state> + </option> + <option> + <name>IlinkInputFileSlave</name> + <state>0</state> + </option> + <option> + <name>IlinkOutputFile</name> + <state>###Unitialized###</state> + </option> + <option> + <name>IlinkDebugInfoEnable</name> + <state>1</state> + </option> + <option> + <name>IlinkKeepSymbols</name> + <state></state> + </option> + <option> + <name>IlinkRawBinaryFile</name> + <state></state> + </option> + <option> + <name>IlinkRawBinarySymbol</name> + <state></state> + </option> + <option> + <name>IlinkRawBinarySegment</name> + <state></state> + </option> + <option> + <name>IlinkRawBinaryAlign</name> + <state></state> + </option> + <option> + <name>IlinkDefines</name> + <state></state> + </option> + <option> + <name>IlinkConfigDefines</name> + <state></state> + </option> + <option> + <name>IlinkMapFile</name> + <state>0</state> + </option> + <option> + <name>IlinkLogFile</name> + <state>0</state> + </option> + <option> + <name>IlinkLogInitialization</name> + <state>0</state> + </option> + <option> + <name>IlinkLogModule</name> + <state>0</state> + </option> + <option> + <name>IlinkLogSection</name> + <state>0</state> + </option> + <option> + <name>IlinkLogVeneer</name> + <state>0</state> + </option> + <option> + <name>IlinkIcfOverride</name> + <state>0</state> + </option> + <option> + <name>IlinkIcfFile</name> + <state>lnk0t.icf</state> + </option> + <option> + <name>IlinkIcfFileSlave</name> + <state></state> + </option> + <option> + <name>IlinkEnableRemarks</name> + <state>0</state> + </option> + <option> + <name>IlinkSuppressDiags</name> + <state></state> + </option> + <option> + <name>IlinkTreatAsRem</name> + <state></state> + </option> + <option> + <name>IlinkTreatAsWarn</name> + <state></state> + </option> + <option> + <name>IlinkTreatAsErr</name> + <state></state> + </option> + <option> + <name>IlinkWarningsAreErrors</name> + <state>0</state> + </option> + <option> + <name>IlinkUseExtraOptions</name> + <state>0</state> + </option> + <option> + <name>IlinkExtraOptions</name> + <state></state> + </option> + <option> + <name>IlinkLowLevelInterfaceSlave</name> + <state>1</state> + </option> + <option> + <name>IlinkAutoLibEnable</name> + <state>1</state> + </option> + <option> + <name>IlinkAdditionalLibs</name> + <state></state> + </option> + <option> + <name>IlinkOverrideProgramEntryLabel</name> + <state>0</state> + </option> + <option> + <name>IlinkProgramEntryLabelSelect</name> + <state>0</state> + </option> + <option> + <name>IlinkProgramEntryLabel</name> + <state></state> + </option> + <option> + <name>DoFill</name> + <state>0</state> + </option> + <option> + <name>FillerByte</name> + <state>0xFF</state> + </option> + <option> + <name>FillerStart</name> + <state>0x0</state> + </option> + <option> + <name>FillerEnd</name> + <state>0x0</state> + </option> + <option> + <name>CrcSize</name> + <version>0</version> + <state>1</state> + </option> + <option> + <name>CrcAlign</name> + <state>1</state> + </option> + <option> + <name>CrcPoly</name> + <state>0x11021</state> + </option> + <option> + <name>CrcCompl</name> + <version>0</version> + <state>0</state> + </option> + <option> + <name>CrcBitOrder</name> + <version>0</version> + <state>0</state> + </option> + <option> + <name>CrcInitialValue</name> + <state>0x0</state> + </option> + <option> + <name>DoCrc</name> + <state>0</state> + </option> + <option> + <name>IlinkBE8Slave</name> + <state>1</state> + </option> + <option> + <name>IlinkBufferedTerminalOutput</name> + <state>1</state> + </option> + <option> + <name>IlinkStdoutInterfaceSlave</name> + <state>1</state> + </option> + <option> + <name>CrcFullSize</name> + <state>0</state> + </option> + <option> + <name>IlinkIElfToolPostProcess</name> + <state>0</state> + </option> + <option> + <name>IlinkLogAutoLibSelect</name> + <state>0</state> + </option> + <option> + <name>IlinkLogRedirSymbols</name> + <state>0</state> + </option> + <option> + <name>IlinkLogUnusedFragments</name> + <state>0</state> + </option> + <option> + <name>IlinkCrcReverseByteOrder</name> + <state>0</state> + </option> + <option> + <name>IlinkCrcUseAsInput</name> + <state>1</state> + </option> + <option> + <name>IlinkOptInline</name> + <state>1</state> + </option> + <option> + <name>IlinkOptExceptionsAllow</name> + <state>1</state> + </option> + <option> + <name>IlinkOptExceptionsForce</name> + <state>0</state> + </option> + <option> + <name>IlinkCmsis</name> + <state>1</state> + </option> + <option> + <name>IlinkOptMergeDuplSections</name> + <state>0</state> + </option> + <option> + <name>IlinkOptUseVfe</name> + <state>1</state> + </option> + <option> + <name>IlinkOptForceVfe</name> + <state>0</state> + </option> + <option> + <name>IlinkStackAnalysisEnable</name> + <state>0</state> + </option> + <option> + <name>IlinkStackControlFile</name> + <state></state> + </option> + <option> + <name>IlinkStackCallGraphFile</name> + <state></state> + </option> + <option> + <name>CrcAlgorithm</name> + <version>1</version> + <state>1</state> + </option> + <option> + <name>CrcUnitSize</name> + <version>0</version> + <state>0</state> + </option> + <option> + <name>IlinkThreadsSlave</name> + <state>1</state> + </option> + <option> + <name>IlinkLogCallGraph</name> + <state>0</state> + </option> + <option> + <name>IlinkIcfFile_AltDefault</name> + <state></state> + </option> + <option> + <name>IlinkEncInput</name> + <state>0</state> + </option> + <option> + <name>IlinkEncOutput</name> + <state>0</state> + </option> + <option> + <name>IlinkEncOutputBom</name> + <state>1</state> + </option> + <option> + <name>IlinkHeapSelect</name> + <state>1</state> + </option> + <option> + <name>IlinkLocaleSelect</name> + <state>1</state> + </option> + <option> + <name>IlinkTrustzoneImportLibraryOut</name> + <state>###Unitialized###</state> + </option> + <option> + <name>OILinkExtraOption</name> + <state>1</state> + </option> + <option> + <name>IlinkRawBinaryFile2</name> + <state></state> + </option> + <option> + <name>IlinkRawBinarySymbol2</name> + <state></state> + </option> + <option> + <name>IlinkRawBinarySegment2</name> + <state></state> + </option> + <option> + <name>IlinkRawBinaryAlign2</name> + <state></state> + </option> + <option> + <name>IlinkLogCrtRoutineSelection</name> + <state>0</state> + </option> + <option> + <name>IlinkLogFragmentInfo</name> + <state>0</state> + </option> + <option> + <name>IlinkLogInlining</name> + <state>0</state> + </option> + <option> + <name>IlinkLogMerging</name> + <state>0</state> + </option> + <option> + <name>IlinkDemangle</name> + <state>0</state> + </option> + <option> + <name>IlinkWrapperFileEnable</name> + <state>0</state> + </option> + <option> + <name>IlinkWrapperFile</name> + <state></state> + </option> + </data> + </settings> + <settings> + <name>IARCHIVE</name> + <archiveVersion>0</archiveVersion> + <data> + <version>0</version> + <wantNonLocal>1</wantNonLocal> + <debug>0</debug> + <option> + <name>IarchiveInputs</name> + <state></state> + </option> + <option> + <name>IarchiveOverride</name> + <state>0</state> + </option> + <option> + <name>IarchiveOutput</name> + <state>###Unitialized###</state> + </option> + </data> + </settings> + <settings> + <name>Coder</name> + <archiveVersion>0</archiveVersion> + <data /> + </settings> + </configuration> + <file> + <name>$PROJ_DIR$\sample_threadx_module.c</name> + </file> + <file> + <name>$PROJ_DIR$\Debug\Exe\txm.a</name> + </file> + <file> + <name>$PROJ_DIR$\txm_module_preamble.s</name> + </file> +</project> diff --git a/ports_module/cortex_a7/iar/example_build/sample_threadx_module.icf b/ports_module/cortex_a7/iar/example_build/sample_threadx_module.icf new file mode 100644 index 00000000..bed79adf --- /dev/null +++ b/ports_module/cortex_a7/iar/example_build/sample_threadx_module.icf @@ -0,0 +1,44 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */ +/*-Specials-*/ +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x00100000; +define symbol __ICFEDIT_region_ROM_end__ = 0x0013FFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x08000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x0800FFFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0; +define symbol __ICFEDIT_size_svcstack__ = 0; +define symbol __ICFEDIT_size_irqstack__ = 0; +define symbol __ICFEDIT_size_fiqstack__ = 0; +define symbol __ICFEDIT_size_undstack__ = 0; +define symbol __ICFEDIT_size_abtstack__ = 0; +define symbol __ICFEDIT_size_heap__ = 0x100; +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; + +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +define movable block ROPI with alignment = 4, fixed order +{ + ro object txm_module_preamble.o, + ro, + ro data +}; + +define movable block RWPI with alignment = 8, fixed order, static base +{ + rw, + block HEAP +}; + +place in ROM_region { block ROPI }; +place in RAM_region { block RWPI }; + diff --git a/ports_module/cortex_a7/iar/example_build/sample_threadx_module_manager.c b/ports_module/cortex_a7/iar/example_build/sample_threadx_module_manager.c new file mode 100644 index 00000000..9aa08e2f --- /dev/null +++ b/ports_module/cortex_a7/iar/example_build/sample_threadx_module_manager.c @@ -0,0 +1,133 @@ +/* Small demonstration of the ThreadX module manager. This demonstration assumes the program + manager is loaded at 0 and that RAM addresses 0x200000 through 0x400000 are available for + use. */ + +#include "tx_api.h" +#include "txm_module.h" + + +#define DEMO_STACK_SIZE 1024 + + +/* Define the ThreadX object control blocks... */ + +TX_THREAD module_manager; + +/* Define thread prototypes. */ + +void module_manager_entry(ULONG thread_input); + +/* Define the module object pool area. */ +UCHAR object_memory[16384]; + +UCHAR manager_thread_stack[DEMO_STACK_SIZE]; + +/* Define the module data pool area. */ +#define MODULE_DATA_SIZE 65536/2 +unsigned char module_data_area[MODULE_DATA_SIZE]; + +/* Define a module instance. */ +TXM_MODULE_INSTANCE my_module1; +TXM_MODULE_INSTANCE my_module2; + +/* Module code is in an array created by module_to_c_array utility. */ +//extern unsigned char module_code[]; + +/* Define the count of memory faults. */ +ULONG memory_faults; + +/* Define fault handler. */ +VOID module_fault_handler(TX_THREAD *thread, TXM_MODULE_INSTANCE *module) +{ + /* Just increment the fault counter. */ + memory_faults++; +} + +/* Define main entry point. */ + +int main() +{ + + /* Enter the ThreadX kernel. */ + tx_kernel_enter(); +} + + +/* Define what the initial system looks like. */ + +void tx_application_define(void *first_unused_memory) +{ + + /* Create the module manager thread. */ + tx_thread_create(&module_manager, "Module Manager Thread", module_manager_entry, 0, + manager_thread_stack, DEMO_STACK_SIZE, + 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); +} + + +/* Define the test threads. */ + +void module_manager_entry(ULONG thread_input) +{ + + /* Initialize the module manager. */ + txm_module_manager_initialize((VOID *) module_data_area, MODULE_DATA_SIZE); + + /* Create a pool for module objects. */ + txm_module_manager_object_pool_create(object_memory, sizeof(object_memory)); + + /* Register a fault handler. */ + txm_module_manager_memory_fault_notify(module_fault_handler); + + /* Initialize MMU. */ + txm_module_manager_mm_initialize(); + + /* Load the module that is already there, in this example it is placed there by the multiple image download. */ + txm_module_manager_in_place_load(&my_module1, "my module1", (VOID *) 0x00100000); + + /* Load a second instance of the module. */ + //txm_module_manager_in_place_load(&my_module2, "my module2", (VOID *) module_code); + + /* Enable shared memory regions for one module. */ + //txm_module_manager_external_memory_enable(&my_module2, (void*)0x90000000, 0x010000, 0x3F); + + /* Start the modules. */ + txm_module_manager_start(&my_module1); + //txm_module_manager_start(&my_module2); + + /* Sleep for a while and let the modules run.... */ + tx_thread_sleep(50); + + /* Thread 0 in module1 should be terminated due to violating the MMU. */ + + /* Stop the modules. */ + txm_module_manager_stop(&my_module1); + txm_module_manager_stop(&my_module2); + + /* Unload the modules. */ + txm_module_manager_unload(&my_module1); + txm_module_manager_unload(&my_module2); + + /* Reload the modules. */ + txm_module_manager_in_place_load(&my_module2, "my module2", (VOID *) 0x00100000); + txm_module_manager_in_place_load(&my_module1, "my module1", (VOID *) 0x00100000); + + /* Give both modules shared memory. */ + txm_module_manager_external_memory_enable(&my_module2, (void*)0x90000000, 0x010000, 0x3F); + txm_module_manager_external_memory_enable(&my_module1, (void*)0x90000000, 0x010000, 0x3F); + + /* Start the module again. */ + txm_module_manager_start(&my_module2); + txm_module_manager_start(&my_module1); + + /* Now just spin... */ + while(1) + { + tx_thread_sleep(100); + /* Thread 0 and 5 in module1 should not exist because they violate the maximum priority. */ + } +} + + + + diff --git a/ports_module/cortex_a7/iar/example_build/sample_threadx_module_manager.ewd b/ports_module/cortex_a7/iar/example_build/sample_threadx_module_manager.ewd new file mode 100644 index 00000000..bffc6509 --- /dev/null +++ b/ports_module/cortex_a7/iar/example_build/sample_threadx_module_manager.ewd @@ -0,0 +1,3088 @@ +<?xml version="1.0" encoding="UTF-8"?> +<project> + <fileVersion>3</fileVersion> + <configuration> + <name>Debug</name> + <toolchain> + <name>ARM</name> + </toolchain> + <debug>1</debug> + <settings> + <name>C-SPY</name> + <archiveVersion>2</archiveVersion> + <data> + <version>32</version> + <wantNonLocal>1</wantNonLocal> + <debug>1</debug> + <option> + <name>CInput</name> + <state>1</state> + </option> + <option> + <name>CEndian</name> + <state>1</state> + </option> + <option> + <name>CProcessor</name> + <state>1</state> + </option> + <option> + <name>OCVariant</name> + <state>0</state> + </option> + <option> + <name>MacOverride</name> + <state>0</state> + </option> + <option> + <name>MacFile</name> + <state>B:\Program Files (x86)\IAR Systems\Embedded Workbench 8.0\arm\config\flashloader\TexasInstruments\FlashTMS570LS3x.mac</state> + </option> + <option> + <name>MemOverride</name> + <state>0</state> + </option> + <option> + <name>MemFile</name> + <state>$TOOLKIT_DIR$\CONFIG\debugger\TexasInstruments\RM48L952ZWT.ddf</state> + </option> + <option> + <name>RunToEnable</name> + <state>0</state> + </option> + <option> + <name>RunToName</name> + <state>main</state> + </option> + <option> + <name>CExtraOptionsCheck</name> + <state>0</state> + </option> + <option> + <name>CExtraOptions</name> + <state></state> + </option> + <option> + <name>CFpuProcessor</name> + <state>1</state> + </option> + <option> + <name>OCDDFArgumentProducer</name> + <state></state> + </option> + <option> + <name>OCDownloadSuppressDownload</name> + <state>0</state> + </option> + <option> + <name>OCDownloadVerifyAll</name> + <state>1</state> + </option> + <option> + <name>OCProductVersion</name> + <state>8.10.1.12859</state> + </option> + <option> + <name>OCDynDriverList</name> + <state>ARMSIM_ID</state> + </option> + <option> + <name>OCLastSavedByProductVersion</name> + <state>8.50.4.26131</state> + </option> + <option> + <name>UseFlashLoader</name> + <state>1</state> + </option> + <option> + <name>CLowLevel</name> + <state>1</state> + </option> + <option> + <name>OCBE8Slave</name> + <state>1</state> + </option> + <option> + <name>MacFile2</name> + <state></state> + </option> + <option> + <name>CDevice</name> + <state>1</state> + </option> + <option> + <name>FlashLoadersV3</name> + <state>$TOOLKIT_DIR$\config\flashloader\TexasInstruments\FlashRM48L950.board</state> + </option> + <option> + <name>OCImagesSuppressCheck1</name> + <state>0</state> + </option> + <option> + <name>OCImagesPath1</name> + <state>$PROJ_DIR$\Debug\Exe\sample_threadx_module.out</state> + </option> + <option> + <name>OCImagesSuppressCheck2</name> + <state>0</state> + </option> + <option> + <name>OCImagesPath2</name> + <state></state> + </option> + <option> + <name>OCImagesSuppressCheck3</name> + <state>0</state> + </option> + <option> + <name>OCImagesPath3</name> + <state></state> + </option> + <option> + <name>OverrideDefFlashBoard</name> + <state>0</state> + </option> + <option> + <name>OCImagesOffset1</name> + <state>0</state> + </option> + <option> + <name>OCImagesOffset2</name> + <state></state> + </option> + <option> + <name>OCImagesOffset3</name> + <state></state> + </option> + <option> + <name>OCImagesUse1</name> + <state>1</state> + </option> + <option> + <name>OCImagesUse2</name> + <state>0</state> + </option> + <option> + <name>OCImagesUse3</name> + <state>0</state> + </option> + <option> + <name>OCDeviceConfigMacroFile</name> + <state>1</state> + </option> + <option> + <name>OCDebuggerExtraOption</name> + <state>1</state> + </option> + <option> + <name>OCAllMTBOptions</name> + <state>1</state> + </option> + <option> + <name>OCMulticoreNrOfCores</name> + <state>1</state> + </option> + <option> + <name>OCMulticoreWorkspace</name> + <state></state> + </option> + <option> + <name>OCMulticoreSlaveProject</name> + <state></state> + </option> + <option> + <name>OCMulticoreSlaveConfiguration</name> + <state></state> + </option> + <option> + <name>OCDownloadExtraImage</name> + <state>1</state> + </option> + <option> + <name>OCAttachSlave</name> + <state>0</state> + </option> + <option> + <name>MassEraseBeforeFlashing</name> + <state>0</state> + </option> + <option> + <name>OCMulticoreNrOfCoresSlave</name> + <state>1</state> + </option> + <option> + <name>OCMulticoreAMPConfigType</name> + <state>0</state> + </option> + <option> + <name>OCMulticoreSessionFile</name> + <state></state> + </option> + <option> + <name>OCTpiuBaseOption</name> + <state>1</state> + </option> + </data> + </settings> + <settings> + <name>ARMSIM_ID</name> + <archiveVersion>2</archiveVersion> + <data> + <version>1</version> + <wantNonLocal>1</wantNonLocal> + <debug>1</debug> + <option> + <name>OCSimDriverInfo</name> + <state>1</state> + </option> + <option> + <name>OCSimEnablePSP</name> + <state>0</state> + </option> + <option> + <name>OCSimPspOverrideConfig</name> + <state>0</state> + </option> + <option> + <name>OCSimPspConfigFile</name> + <state></state> + </option> + </data> + </settings> + <settings> + <name>CADI_ID</name> + <archiveVersion>2</archiveVersion> + <data> + <version>0</version> + <wantNonLocal>1</wantNonLocal> + <debug>1</debug> + <option> + <name>CCadiMemory</name> + <state>1</state> + </option> + <option> + <name>Fast Model</name> + <state></state> + </option> + <option> + <name>CCADILogFileCheck</name> + <state>0</state> + </option> + <option> + <name>CCADILogFileEditB</name> + <state>$PROJ_DIR$\cspycomm.log</state> + </option> + <option> + <name>OCDriverInfo</name> + <state>1</state> + </option> + </data> + </settings> + <settings> + <name>CMSISDAP_ID</name> + <archiveVersion>2</archiveVersion> + <data> + <version>4</version> + <wantNonLocal>1</wantNonLocal> + <debug>1</debug> + <option> + <name>OCDriverInfo</name> + <state>1</state> + </option> + <option> + <name>OCIarProbeScriptFile</name> + <state>1</state> + </option> + <option> + <name>CMSISDAPResetList</name> + <version>1</version> + <state>10</state> + </option> + <option> + <name>CMSISDAPHWResetDuration</name> + <state>300</state> + </option> + <option> + <name>CMSISDAPHWResetDelay</name> + <state>200</state> + </option> + <option> + <name>CMSISDAPDoLogfile</name> + <state>0</state> + </option> + <option> + <name>CMSISDAPLogFile</name> + <state>$PROJ_DIR$\cspycomm.log</state> + </option> + <option> + <name>CMSISDAPInterfaceRadio</name> + <state>0</state> + </option> + <option> + <name>CMSISDAPInterfaceCmdLine</name> + <state>0</state> + </option> + <option> + <name>CMSISDAPMultiTargetEnable</name> + <state>0</state> + </option> + <option> + <name>CMSISDAPMultiTarget</name> + <state>0</state> + </option> + <option> + <name>CMSISDAPJtagSpeedList</name> + <version>0</version> + <state>0</state> + </option> + <option> + <name>CMSISDAPBreakpointRadio</name> + <state>0</state> + </option> + <option> + <name>CMSISDAPRestoreBreakpointsCheck</name> + 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<state></state> + </option> + <option> + <name>CCCMSISDAPUsbSerialNoSelect</name> + <state>0</state> + </option> + </data> + </settings> + <settings> + <name>GDBSERVER_ID</name> + <archiveVersion>2</archiveVersion> + <data> + <version>0</version> + <wantNonLocal>1</wantNonLocal> + <debug>1</debug> + <option> + <name>OCDriverInfo</name> + <state>1</state> + </option> + <option> + <name>TCPIP</name> + <state>aaa.bbb.ccc.ddd</state> + </option> + <option> + <name>DoLogfile</name> + <state>0</state> + </option> + <option> + <name>LogFile</name> + <state>$PROJ_DIR$\cspycomm.log</state> + </option> + <option> + <name>CCJTagBreakpointRadio</name> + <state>0</state> + </option> + <option> + <name>CCJTagDoUpdateBreakpoints</name> + <state>0</state> + </option> + <option> + <name>CCJTagUpdateBreakpoints</name> + <state>_call_main</state> + </option> + </data> + </settings> + <settings> + <name>IJET_ID</name> + <archiveVersion>2</archiveVersion> + <data> + <version>9</version> + <wantNonLocal>1</wantNonLocal> + <debug>1</debug> + <option> + <name>OCDriverInfo</name> + <state>1</state> + </option> + <option> + <name>OCIarProbeScriptFile</name> + <state>1</state> + </option> + <option> + <name>IjetResetList</name> + <version>1</version> + <state>10</state> + </option> + <option> + <name>IjetHWResetDuration</name> + <state>300</state> + </option> + <option> + <name>IjetHWResetDelay</name> + <state>200</state> + </option> + <option> + <name>IjetPowerFromProbe</name> + <state>1</state> + </option> + <option> + <name>IjetPowerRadio</name> + <state>0</state> + </option> + <option> + <name>IjetDoLogfile</name> + <state>0</state> + </option> + <option> + <name>IjetLogFile</name> + <state>$PROJ_DIR$\cspycomm.log</state> + </option> + <option> + <name>IjetInterfaceRadio</name> + <state>0</state> + </option> + <option> + <name>IjetInterfaceCmdLine</name> + <state>0</state> + </option> + <option> + <name>IjetMultiTargetEnable</name> + <state>0</state> + </option> + <option> + <name>IjetMultiTarget</name> + <state>0</state> + </option> + <option> + <name>IjetScanChainNonARMDevices</name> + <state>0</state> + </option> + <option> + <name>IjetIRLength</name> + <state>0</state> + </option> + <option> + <name>IjetJtagSpeedList</name> + <version>0</version> + <state>0</state> + </option> + <option> + <name>IjetProtocolRadio</name> + <state>0</state> + </option> + <option> + <name>IjetSwoPin</name> + <state>0</state> + </option> + <option> + <name>IjetCpuClockEdit</name> + <state></state> + </option> + <option> + <name>IjetSwoPrescalerList</name> + <version>1</version> + <state>0</state> + </option> + <option> + <name>IjetBreakpointRadio</name> + <state>0</state> + </option> + <option> + <name>IjetRestoreBreakpointsCheck</name> + <state>0</state> + </option> + <option> + <name>IjetUpdateBreakpointsEdit</name> + <state>_call_main</state> + </option> + <option> + <name>RDICatchReset</name> + <state>0</state> + </option> + <option> + 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<state>0</state> + </option> + <option> + <name>CCSTLinkCatchBUSERR</name> + <state>0</state> + </option> + <option> + <name>CCSTLinkCatchINTERR</name> + <state>0</state> + </option> + <option> + <name>CCSTLinkCatchSFERR</name> + <state>0</state> + </option> + <option> + <name>CCSTLinkCatchHARDERR</name> + <state>0</state> + </option> + <option> + <name>CCSTLinkCatchDummy</name> + <state>0</state> + </option> + <option> + <name>CCSTLinkUsbSerialNo</name> + <state></state> + </option> + <option> + <name>CCSTLinkUsbSerialNoSelect</name> + <state>0</state> + </option> + <option> + <name>CCSTLinkJtagSpeedList</name> + <version>2</version> + <state>0</state> + </option> + <option> + <name>CCSTLinkDAPNumber</name> + <state></state> + </option> + <option> + <name>CCSTLinkDebugAccessPortRadio</name> + <state>0</state> + </option> + <option> + <name>CCSTLinkUseServerSelect</name> + <state>0</state> + </option> + <option> + <name>CCSTLinkProbeList</name> + <version>1</version> + <state>0</state> + </option> + </data> + </settings> + <settings> + <name>THIRDPARTY_ID</name> + <archiveVersion>2</archiveVersion> + <data> + <version>0</version> + <wantNonLocal>1</wantNonLocal> + <debug>0</debug> + <option> + <name>CThirdPartyDriverDll</name> + <state>###Uninitialized###</state> + </option> + <option> + <name>CThirdPartyLogFileCheck</name> + <state>0</state> + </option> + <option> + <name>CThirdPartyLogFileEditB</name> + <state>$PROJ_DIR$\cspycomm.log</state> + </option> + <option> + <name>OCDriverInfo</name> + <state>1</state> + </option> + </data> + </settings> + <settings> + <name>TIFET_ID</name> + <archiveVersion>2</archiveVersion> + <data> + <version>1</version> + <wantNonLocal>1</wantNonLocal> + <debug>0</debug> + <option> + <name>OCDriverInfo</name> + <state>1</state> + </option> + <option> + <name>CCMSPFetResetList</name> + <version>0</version> + <state>0</state> + </option> + <option> + <name>CCMSPFetInterfaceRadio</name> + <state>0</state> + </option> + <option> + <name>CCMSPFetInterfaceCmdLine</name> + <state>0</state> + </option> + <option> + <name>CCMSPFetTargetVccTypeDefault</name> + <state>0</state> + </option> + <option> + <name>CCMSPFetTargetVoltage</name> + <state>###Uninitialized###</state> + </option> + <option> + <name>CCMSPFetVCCDefault</name> + <state>1</state> + </option> + <option> + <name>CCMSPFetTargetSettlingtime</name> + <state>0</state> + </option> + <option> + <name>CCMSPFetRadioJtagSpeedType</name> + <state>1</state> + </option> + <option> + <name>CCMSPFetConnection</name> + <version>0</version> + <state>0</state> + </option> + <option> + <name>CCMSPFetUsbComPort</name> + <state>Automatic</state> + </option> + <option> + <name>CCMSPFetAllowAccessToBSL</name> + <state>0</state> + </option> + <option> + <name>CCMSPFetDoLogfile</name> + <state>0</state> + </option> + <option> + <name>CCMSPFetLogFile</name> + <state>$PROJ_DIR$\cspycomm.log</state> + </option> + <option> + <name>CCMSPFetRadioEraseFlash</name> + <state>1</state> + </option> + </data> + </settings> + <settings> + <name>XDS100_ID</name> + <archiveVersion>2</archiveVersion> + <data> + <version>9</version> + <wantNonLocal>1</wantNonLocal> + <debug>0</debug> + <option> + <name>OCDriverInfo</name> + <state>1</state> + </option> + <option> + <name>TIPackageOverride</name> + <state>0</state> + </option> + <option> + <name>TIPackage</name> + <state></state> + </option> + <option> + <name>BoardFile</name> + <state></state> + </option> + <option> + <name>DoLogfile</name> + <state>0</state> + </option> + <option> + <name>LogFile</name> + <state>$PROJ_DIR$\cspycomm.log</state> + </option> + <option> + <name>CCXds100BreakpointRadio</name> + <state>0</state> + </option> + <option> + <name>CCXds100DoUpdateBreakpoints</name> + <state>0</state> + </option> + <option> + <name>CCXds100UpdateBreakpoints</name> + <state>_call_main</state> + </option> + <option> + <name>CCXds100CatchReset</name> + <state>0</state> + </option> + <option> + <name>CCXds100CatchUndef</name> + <state>0</state> + </option> + <option> + <name>CCXds100CatchSWI</name> + <state>0</state> + </option> + <option> + <name>CCXds100CatchData</name> + <state>0</state> + </option> + <option> + <name>CCXds100CatchPrefetch</name> + <state>0</state> + </option> + <option> + <name>CCXds100CatchIRQ</name> + <state>0</state> + </option> + <option> + <name>CCXds100CatchFIQ</name> + <state>0</state> + </option> + <option> + <name>CCXds100CatchCORERESET</name> + <state>0</state> + </option> + <option> + <name>CCXds100CatchMMERR</name> + <state>0</state> + </option> + <option> + <name>CCXds100CatchNOCPERR</name> + <state>0</state> + </option> + <option> + <name>CCXds100CatchCHRERR</name> + <state>0</state> + </option> + <option> + <name>CCXds100CatchSTATERR</name> + <state>0</state> + </option> + <option> + <name>CCXds100CatchBUSERR</name> + <state>0</state> + </option> + <option> + <name>CCXds100CatchINTERR</name> + <state>0</state> + </option> + <option> + <name>CCXds100CatchSFERR</name> + <state>0</state> + </option> + <option> + <name>CCXds100CatchHARDERR</name> + <state>0</state> + </option> + <option> + <name>CCXds100CatchDummy</name> + <state>0</state> + </option> + <option> + <name>CCXds100CpuClockEdit</name> + <state></state> + </option> + <option> + <name>CCXds100SwoClockAuto</name> + <state>0</state> + </option> + <option> + <name>CCXds100SwoClockEdit</name> + <state>1000</state> + </option> + <option> + <name>CCXds100HWResetDelay</name> + <state>0</state> + </option> + <option> + <name>CCXds100ResetList</name> + <version>1</version> + <state>0</state> + </option> + <option> + <name>CCXds100UsbSerialNo</name> + <state></state> + </option> + <option> + <name>CCXds100UsbSerialNoSelect</name> + <state>0</state> + </option> + <option> + <name>CCXds100JtagSpeedList</name> + <version>0</version> + <state>0</state> + </option> + <option> + <name>CCXds100InterfaceRadio</name> + <state>2</state> + </option> + <option> + <name>CCXds100InterfaceCmdLine</name> + <state>0</state> + </option> + <option> + <name>CCXds100ProbeList</name> + <version>0</version> + <state>2</state> + </option> + <option> + <name>CCXds100SWOPortRadio</name> + <state>0</state> + </option> + <option> + <name>CCXds100SWOPort</name> + <state>1</state> + </option> + <option> + <name>CCXDSTargetVccEnable</name> + <state>0</state> + </option> + <option> + <name>CCXDSTargetVoltage</name> + <state>###Uninitialized###</state> + </option> + <option> + <name>OCXDSDigitalStatesConfigFile</name> + <state>1</state> + </option> + <option> + <name>OCSelectedCoreName</name> + <state>1</state> + </option> + </data> + </settings> + <debuggerPlugins> + <plugin> + <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$TOOLKIT_DIR$\plugins\rtos\FreeRtos\FreeRtosArmPlugin.ENU.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin2.ENU.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm9.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm9BE.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + </debuggerPlugins> + </configuration> +</project> diff --git a/ports_module/cortex_a7/iar/example_build/sample_threadx_module_manager.ewp b/ports_module/cortex_a7/iar/example_build/sample_threadx_module_manager.ewp new file mode 100644 index 00000000..3d7db51f --- /dev/null +++ b/ports_module/cortex_a7/iar/example_build/sample_threadx_module_manager.ewp @@ -0,0 +1,2138 @@ +<?xml version="1.0" encoding="UTF-8"?> +<project> + <fileVersion>3</fileVersion> + <configuration> + <name>Debug</name> + <toolchain> + <name>ARM</name> + </toolchain> + <debug>1</debug> + <settings> + <name>General</name> + <archiveVersion>3</archiveVersion> + <data> + <version>34</version> + <wantNonLocal>1</wantNonLocal> + <debug>1</debug> + <option> + <name>BrowseInfoPath</name> + <state>Debug\BrowseInfo</state> + </option> + <option> + <name>ExePath</name> + <state>Debug\Exe</state> + </option> + <option> + <name>ObjPath</name> + <state>Debug\Obj</state> + </option> + <option> + <name>ListPath</name> + <state>Debug\List</state> + </option> + <option> + <name>GEndianMode</name> + <state>0</state> + </option> + <option> + <name>Input description</name> + <state>Full formatting, without multibyte support.</state> + </option> + <option> + <name>Output description</name> + <state>Full formatting, without multibyte support.</state> + </option> + <option> + <name>GOutputBinary</name> + <state>0</state> + </option> + <option> + <name>OGCoreOrChip</name> + <state>0</state> + </option> + <option> + <name>GRuntimeLibSelect</name> + <version>0</version> + <state>1</state> + </option> + <option> + <name>GRuntimeLibSelectSlave</name> + <version>0</version> + <state>1</state> + </option> + <option> + <name>RTDescription</name> + <state>Use the normal configuration of the C/C++ runtime library. No locale interface, C locale, no file descriptor support, no multibytes in printf and scanf, and no hex floats in strtod.</state> + </option> + <option> + <name>OGProductVersion</name> + <state>6.10.1.52170</state> + </option> + <option> + <name>OGLastSavedByProductVersion</name> + <state>9.20.4.46976</state> + </option> + <option> + <name>OGChipSelectEditMenu</name> + <state>RM48L952ZWT TexasInstruments RM48L952ZWT</state> + </option> + <option> + <name>GenLowLevelInterface</name> + <state>1</state> + </option> + <option> + <name>GEndianModeBE</name> + <state>0</state> + </option> + <option> + <name>OGBufferedTerminalOutput</name> + <state>0</state> + </option> + <option> + <name>GenStdoutInterface</name> + <state>0</state> + </option> + <option> + <name>RTConfigPath2</name> + <state>$TOOLKIT_DIR$\inc\c\DLib_Config_Normal.h</state> + </option> + <option> + <name>GBECoreSlave</name> + <version>31</version> + <state>42</state> + </option> + <option> + <name>OGUseCmsis</name> + <state>0</state> + </option> + <option> + <name>OGUseCmsisDspLib</name> + <state>0</state> + </option> + <option> + <name>GRuntimeLibThreads</name> + <state>0</state> + </option> + <option> + <name>CoreVariant</name> + <version>31</version> + <state>52</state> + </option> + <option> + <name>GFPUDeviceSlave</name> + <state>RM48L952ZWT TexasInstruments RM48L952ZWT</state> + </option> + <option> + <name>FPU2</name> + <version>0</version> + <state>5</state> + </option> + <option> + <name>NrRegs</name> + <version>0</version> + <state>2</state> + </option> + <option> + <name>NEON</name> + <state>1</state> + </option> + <option> + <name>GFPUCoreSlave2</name> + <version>31</version> + <state>52</state> + </option> + <option> + <name>OGCMSISPackSelectDevice</name> + </option> + <option> + <name>OgLibHeap</name> + <state>0</state> + </option> + <option> + <name>OGLibAdditionalLocale</name> + <state>0</state> + </option> + <option> + <name>OGPrintfVariant</name> + <version>0</version> + <state>1</state> + </option> + <option> + <name>OGPrintfMultibyteSupport</name> + <state>0</state> + </option> + <option> + <name>OGScanfVariant</name> + <version>0</version> + <state>1</state> + </option> + <option> + <name>OGScanfMultibyteSupport</name> + <state>0</state> + </option> + <option> + <name>GenLocaleTags</name> + <state></state> + </option> + <option> + <name>GenLocaleDisplayOnly</name> + <state></state> + </option> + <option> + <name>DSPExtension</name> + <state>0</state> + </option> + <option> + <name>TrustZone</name> + <state>0</state> + </option> + <option> + <name>TrustZoneModes</name> + <version>0</version> + <state>0</state> + </option> + <option> + <name>OGAarch64Abi</name> + <state>0</state> + </option> + <option> + <name>OG_32_64Device</name> + <state>0</state> + </option> + <option> + <name>BuildFilesPath</name> + <state>Debug</state> + </option> + </data> + </settings> + <settings> + <name>ICCARM</name> + <archiveVersion>2</archiveVersion> + <data> + <version>37</version> + <wantNonLocal>1</wantNonLocal> + <debug>1</debug> + <option> + <name>CCOptimizationNoSizeConstraints</name> + <state>0</state> + </option> + <option> + <name>CCDefines</name> + <state></state> + </option> + <option> + <name>CCPreprocFile</name> + <state>0</state> + </option> + <option> + <name>CCPreprocComments</name> + <state>0</state> + </option> + <option> + <name>CCPreprocLine</name> + <state>0</state> + </option> + <option> + <name>CCListCFile</name> + <state>0</state> + </option> + <option> + <name>CCListCMnemonics</name> + <state>0</state> + </option> + <option> + <name>CCListCMessages</name> + <state>0</state> + </option> + <option> + <name>CCListAssFile</name> + <state>1</state> + </option> + <option> + <name>CCListAssSource</name> + <state>0</state> + </option> + <option> + <name>CCEnableRemarks</name> + <state>0</state> + </option> + <option> + <name>CCDiagSuppress</name> + <state></state> + </option> + <option> + <name>CCDiagRemark</name> + <state></state> + </option> + <option> + <name>CCDiagWarning</name> + <state></state> + </option> + <option> + <name>CCDiagError</name> + <state></state> + </option> + <option> + <name>CCObjPrefix</name> + <state>1</state> + </option> + <option> + <name>CCAllowList</name> + <version>1</version> + <state>11111110</state> + </option> + <option> + <name>CCDebugInfo</name> + <state>1</state> + </option> + <option> + <name>IEndianMode</name> + <state>1</state> + </option> + <option> + <name>IProcessor</name> + <state>1</state> + </option> + <option> + <name>IExtraOptionsCheck</name> + <state>0</state> + </option> + <option> + <name>IExtraOptions</name> + <state></state> + </option> + <option> + <name>CCLangConformance</name> + <state>0</state> + </option> + <option> + <name>CCSignedPlainChar</name> + <state>1</state> + </option> + <option> + <name>CCRequirePrototypes</name> + <state>0</state> + </option> + <option> + <name>CCDiagWarnAreErr</name> + <state>0</state> + </option> + <option> + <name>CCCompilerRuntimeInfo</name> + <state>0</state> + </option> + <option> + <name>IFpuProcessor</name> + <state>1</state> + </option> + <option> + <name>OutputFile</name> + <state>$FILE_BNAME$.o</state> + </option> + <option> + <name>CCLibConfigHeader</name> + <state>1</state> + </option> + <option> + <name>PreInclude</name> + <state></state> + </option> + <option> + <name>CCIncludePath2</name> + <state>$PROJ_DIR$\..\inc</state> + <state>$PROJ_DIR$\..\..\..\..\common\inc</state> + <state>$PROJ_DIR$\..\..\..\..\common_modules\inc</state> + </option> + <option> + <name>CCStdIncCheck</name> + <state>0</state> + </option> + <option> + <name>CCCodeSection</name> + <state>.text</state> + </option> + <option> + <name>IProcessorMode2</name> + <state>1</state> + </option> + <option> + <name>CCOptLevel</name> + <state>3</state> + </option> + <option> + <name>CCOptStrategy</name> + <version>0</version> + <state>1</state> + </option> + <option> + <name>CCOptLevelSlave</name> + <state>3</state> + </option> + <option> + <name>CCPosIndRopi</name> + <state>0</state> + </option> + <option> + <name>CCPosIndRwpi</name> + <state>0</state> + </option> + <option> + <name>CCPosIndNoDynInit</name> + <state>0</state> + </option> + <option> + <name>IccLang</name> + <state>0</state> + </option> + <option> + <name>IccCDialect</name> + <state>1</state> + </option> + <option> + <name>IccAllowVLA</name> + <state>0</state> + </option> + <option> + <name>IccStaticDestr</name> + <state>1</state> + </option> + <option> + <name>IccCppInlineSemantics</name> + <state>0</state> + </option> + <option> + <name>IccCmsis</name> + <state>1</state> + </option> + <option> + <name>IccFloatSemantics</name> + <state>0</state> + </option> + <option> + <name>CCNoLiteralPool</name> + <state>0</state> + </option> + <option> + <name>CCOptStrategySlave</name> + <version>0</version> + <state>1</state> + </option> + <option> + <name>CCGuardCalls</name> + <state>1</state> + </option> + <option> + <name>CCEncSource</name> + <state>0</state> + </option> + <option> + <name>CCEncOutput</name> + <state>0</state> + </option> + <option> + <name>CCEncOutputBom</name> + <state>1</state> + </option> + <option> + <name>CCEncInput</name> + <state>0</state> + </option> + <option> + <name>IccExceptions2</name> + <state>0</state> + </option> + <option> + <name>IccRTTI2</name> + <state>0</state> + </option> + <option> + <name>OICompilerExtraOption</name> + <state>1</state> + </option> + <option> + <name>CCStackProtection</name> + <state>0</state> + </option> + </data> + </settings> + <settings> + <name>AARM</name> + <archiveVersion>2</archiveVersion> + <data> + <version>11</version> + <wantNonLocal>1</wantNonLocal> + <debug>1</debug> + <option> + <name>AObjPrefix</name> + <state>1</state> + </option> + <option> + <name>AEndian</name> + <state>1</state> + </option> + <option> + <name>ACaseSensitivity</name> + <state>1</state> + </option> + <option> + <name>MacroChars</name> + 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<name>MacExec</name> + <state>0</state> + </option> + <option> + <name>OnlyAssed</name> + <state>0</state> + </option> + <option> + <name>MultiLine</name> + <state>0</state> + </option> + <option> + <name>PageLengthCheck</name> + <state>0</state> + </option> + <option> + <name>PageLength</name> + <state>80</state> + </option> + <option> + <name>TabSpacing</name> + <state>8</state> + </option> + <option> + <name>AXRef</name> + <state>0</state> + </option> + <option> + <name>AXRefDefines</name> + <state>0</state> + </option> + <option> + <name>AXRefInternal</name> + <state>0</state> + </option> + <option> + <name>AXRefDual</name> + <state>0</state> + </option> + <option> + <name>AProcessor</name> + <state>1</state> + </option> + <option> + <name>AFpuProcessor</name> + <state>1</state> + </option> + <option> + <name>AOutputFile</name> + <state>$FILE_BNAME$.o</state> + </option> + <option> + <name>ALimitErrorsCheck</name> + <state>0</state> + </option> + <option> + <name>ALimitErrorsEdit</name> + <state>100</state> + </option> + <option> + <name>AIgnoreStdInclude</name> + <state>0</state> + </option> + <option> + <name>AUserIncludes</name> + <state></state> + </option> + <option> + <name>AExtraOptionsCheckV2</name> + <state>0</state> + </option> + <option> + <name>AExtraOptionsV2</name> + <state></state> + </option> + <option> + <name>AsmNoLiteralPool</name> + <state>0</state> + </option> + <option> + <name>PreInclude</name> + <state></state> + </option> + </data> + </settings> + <settings> + <name>OBJCOPY</name> + <archiveVersion>0</archiveVersion> + <data> + <version>1</version> + <wantNonLocal>1</wantNonLocal> + <debug>1</debug> + <option> + <name>OOCOutputFormat</name> + <version>3</version> + <state>0</state> + </option> + <option> + <name>OCOutputOverride</name> + <state>0</state> + </option> + <option> + <name>OOCOutputFile</name> + <state>sample_threadx_module_manager.srec</state> + </option> + <option> + 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+ <option> + <name>CrcBitOrder</name> + <version>0</version> + <state>0</state> + </option> + <option> + <name>CrcInitialValue</name> + <state>0x0</state> + </option> + <option> + <name>DoCrc</name> + <state>0</state> + </option> + <option> + <name>IlinkBE8Slave</name> + <state>1</state> + </option> + <option> + <name>IlinkBufferedTerminalOutput</name> + <state>1</state> + </option> + <option> + <name>IlinkStdoutInterfaceSlave</name> + <state>1</state> + </option> + <option> + <name>CrcFullSize</name> + <state>0</state> + </option> + <option> + <name>IlinkIElfToolPostProcess</name> + <state>0</state> + </option> + <option> + <name>IlinkLogAutoLibSelect</name> + <state>0</state> + </option> + <option> + <name>IlinkLogRedirSymbols</name> + <state>0</state> + </option> + <option> + <name>IlinkLogUnusedFragments</name> + <state>0</state> + </option> + <option> + <name>IlinkCrcReverseByteOrder</name> + <state>0</state> + </option> + <option> + <name>IlinkCrcUseAsInput</name> + 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<name>IarchiveOutput</name> + <state>###Unitialized###</state> + </option> + </data> + </settings> + <settings> + <name>Coder</name> + <archiveVersion>0</archiveVersion> + <data /> + </settings> + </configuration> + <configuration> + <name>Release</name> + <toolchain> + <name>ARM</name> + </toolchain> + <debug>0</debug> + <settings> + <name>General</name> + <archiveVersion>3</archiveVersion> + <data> + <version>34</version> + <wantNonLocal>1</wantNonLocal> + <debug>0</debug> + <option> + <name>BrowseInfoPath</name> + <state>Release\BrowseInfo</state> + </option> + <option> + <name>ExePath</name> + <state>Release\Exe</state> + </option> + <option> + <name>ObjPath</name> + <state>Release\Obj</state> + </option> + <option> + <name>ListPath</name> + <state>Release\List</state> + </option> + <option> + <name>GEndianMode</name> + <state>0</state> + </option> + <option> + <name>Input description</name> + <state>Full formatting, without multibyte support.</state> + </option> + <option> + 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+ </option> + <option> + <name>CCPosIndRopi</name> + <state>0</state> + </option> + <option> + <name>CCPosIndRwpi</name> + <state>0</state> + </option> + <option> + <name>CCPosIndNoDynInit</name> + <state>0</state> + </option> + <option> + <name>IccLang</name> + <state>0</state> + </option> + <option> + <name>IccCDialect</name> + <state>1</state> + </option> + <option> + <name>IccAllowVLA</name> + <state>0</state> + </option> + <option> + <name>IccStaticDestr</name> + <state>1</state> + </option> + <option> + <name>IccCppInlineSemantics</name> + <state>0</state> + </option> + <option> + <name>IccCmsis</name> + <state>1</state> + </option> + <option> + <name>IccFloatSemantics</name> + <state>0</state> + </option> + <option> + <name>CCNoLiteralPool</name> + <state>0</state> + </option> + <option> + <name>CCOptStrategySlave</name> + <version>0</version> + <state>0</state> + </option> + <option> + <name>CCGuardCalls</name> + <state>1</state> + </option> + <option> + <name>CCEncSource</name> + <state>0</state> + </option> + <option> + <name>CCEncOutput</name> + <state>0</state> + </option> + <option> + <name>CCEncOutputBom</name> + <state>1</state> + </option> + <option> + <name>CCEncInput</name> + <state>0</state> + </option> + <option> + <name>IccExceptions2</name> + <state>0</state> + </option> + <option> + <name>IccRTTI2</name> + <state>0</state> + </option> + <option> + <name>OICompilerExtraOption</name> + <state>1</state> + </option> + <option> + <name>CCStackProtection</name> + <state>0</state> + </option> + </data> + </settings> + <settings> + <name>AARM</name> + <archiveVersion>2</archiveVersion> + <data> + <version>11</version> + <wantNonLocal>1</wantNonLocal> + <debug>0</debug> + <option> + <name>AObjPrefix</name> + <state>1</state> + </option> + <option> + <name>AEndian</name> + <state>1</state> + </option> + <option> + <name>ACaseSensitivity</name> + <state>1</state> + </option> + <option> + <name>MacroChars</name> + <version>0</version> + <state>0</state> + </option> + <option> + <name>AWarnEnable</name> + <state>0</state> + </option> + <option> + <name>AWarnWhat</name> + <state>0</state> + </option> + <option> + <name>AWarnOne</name> + <state></state> + </option> + <option> + <name>AWarnRange1</name> + <state></state> + </option> + <option> + <name>AWarnRange2</name> + <state></state> + </option> + <option> + <name>ADebug</name> + <state>0</state> + </option> + <option> + <name>AltRegisterNames</name> + <state>0</state> + </option> + <option> + <name>ADefines</name> + <state></state> + </option> + <option> + <name>AList</name> + <state>0</state> + </option> + <option> + <name>AListHeader</name> + <state>1</state> + </option> + <option> + <name>AListing</name> + <state>1</state> + </option> + <option> + <name>Includes</name> + <state>0</state> + </option> + <option> + <name>MacDefs</name> + <state>0</state> + </option> + <option> + <name>MacExps</name> + <state>1</state> + </option> + <option> + <name>MacExec</name> + <state>0</state> + </option> + <option> + <name>OnlyAssed</name> + <state>0</state> + </option> + <option> + <name>MultiLine</name> + <state>0</state> + </option> + <option> + <name>PageLengthCheck</name> + <state>0</state> + </option> + <option> + <name>PageLength</name> + <state>80</state> + </option> + <option> + <name>TabSpacing</name> + <state>8</state> + </option> + <option> + <name>AXRef</name> + <state>0</state> + </option> + <option> + <name>AXRefDefines</name> + <state>0</state> + </option> + <option> + <name>AXRefInternal</name> + <state>0</state> + </option> + <option> + <name>AXRefDual</name> + <state>0</state> + </option> + <option> + <name>AProcessor</name> + <state>1</state> + </option> + <option> + <name>AFpuProcessor</name> + <state>1</state> + </option> + <option> + <name>AOutputFile</name> + <state>$FILE_BNAME$.o</state> + </option> + <option> + <name>ALimitErrorsCheck</name> + <state>0</state> + </option> + <option> + <name>ALimitErrorsEdit</name> + <state>100</state> + </option> + <option> + <name>AIgnoreStdInclude</name> + <state>0</state> + </option> + <option> + <name>AUserIncludes</name> + <state></state> + </option> + <option> + <name>AExtraOptionsCheckV2</name> + <state>0</state> + </option> + <option> + <name>AExtraOptionsV2</name> + <state></state> + </option> + <option> + <name>AsmNoLiteralPool</name> + <state>0</state> + </option> + <option> + <name>PreInclude</name> + <state></state> + </option> + </data> + </settings> + <settings> + <name>OBJCOPY</name> + <archiveVersion>0</archiveVersion> + <data> + <version>1</version> + <wantNonLocal>1</wantNonLocal> + <debug>0</debug> + <option> + <name>OOCOutputFormat</name> + <version>3</version> + <state>0</state> + </option> + <option> + <name>OCOutputOverride</name> + <state>0</state> + </option> + <option> + <name>OOCOutputFile</name> + <state></state> + </option> + <option> + <name>OOCCommandLineProducer</name> + <state>1</state> + </option> + <option> + <name>OOCObjCopyEnable</name> + <state>0</state> + </option> + </data> + </settings> + <settings> + <name>CUSTOM</name> + <archiveVersion>3</archiveVersion> + <data> + <extensions></extensions> + <cmdline></cmdline> + <hasPrio>0</hasPrio> + <buildSequence>inputOutputBased</buildSequence> + </data> + </settings> + <settings> + <name>BUILDACTION</name> + <archiveVersion>1</archiveVersion> + <data> + <prebuild></prebuild> + <postbuild></postbuild> + </data> + </settings> + <settings> + <name>ILINK</name> + <archiveVersion>0</archiveVersion> + <data> + <version>26</version> + <wantNonLocal>1</wantNonLocal> + <debug>0</debug> + <option> + <name>IlinkLibIOConfig</name> + <state>1</state> + </option> + <option> + <name>IlinkInputFileSlave</name> + <state>0</state> + </option> + <option> + <name>IlinkOutputFile</name> + <state>sample_threadx_module_manager.out</state> + </option> + <option> + <name>IlinkDebugInfoEnable</name> + <state>1</state> + </option> + <option> + <name>IlinkKeepSymbols</name> + <state></state> + </option> + <option> + <name>IlinkRawBinaryFile</name> + <state></state> + </option> + <option> + <name>IlinkRawBinarySymbol</name> + <state></state> + </option> + <option> + <name>IlinkRawBinarySegment</name> + <state></state> + </option> + <option> + <name>IlinkRawBinaryAlign</name> + <state></state> + </option> + <option> + <name>IlinkDefines</name> + <state></state> + </option> + <option> + <name>IlinkConfigDefines</name> + <state></state> + </option> + <option> + <name>IlinkMapFile</name> + <state>0</state> + </option> + <option> + <name>IlinkLogFile</name> + <state>0</state> + </option> + <option> + <name>IlinkLogInitialization</name> + <state>0</state> + </option> + <option> + <name>IlinkLogModule</name> + <state>0</state> + </option> + <option> + <name>IlinkLogSection</name> + <state>0</state> + </option> + <option> + <name>IlinkLogVeneer</name> + <state>0</state> + </option> + <option> + <name>IlinkIcfOverride</name> + <state>1</state> + </option> + <option> + <name>IlinkIcfFile</name> + <state>C:\Users\cindydeng\AzureRTOS\threadx\modules\cortex-a-port\threadx\ports_module\cortex_a7\iar\example_build\sample_threadx_module_manager.icf</state> + </option> + <option> + <name>IlinkIcfFileSlave</name> + <state></state> + </option> + <option> + <name>IlinkEnableRemarks</name> + <state>0</state> + </option> + <option> + <name>IlinkSuppressDiags</name> + <state></state> + </option> + <option> + <name>IlinkTreatAsRem</name> + <state></state> + </option> + <option> + <name>IlinkTreatAsWarn</name> + <state></state> + </option> + <option> + <name>IlinkTreatAsErr</name> + <state></state> + </option> + <option> + <name>IlinkWarningsAreErrors</name> + <state>0</state> + </option> + <option> + <name>IlinkUseExtraOptions</name> + <state>0</state> + </option> + <option> + <name>IlinkExtraOptions</name> + <state></state> + </option> + <option> + <name>IlinkLowLevelInterfaceSlave</name> + <state>1</state> + </option> + <option> + <name>IlinkAutoLibEnable</name> + <state>1</state> + </option> + <option> + <name>IlinkAdditionalLibs</name> + <state></state> + </option> + <option> + <name>IlinkOverrideProgramEntryLabel</name> + <state>0</state> + </option> + <option> + <name>IlinkProgramEntryLabelSelect</name> + <state>0</state> + </option> + <option> + <name>IlinkProgramEntryLabel</name> + <state>__iar_program_start</state> + </option> + <option> + <name>DoFill</name> + <state>0</state> + </option> + <option> + <name>FillerByte</name> + <state>0xFF</state> + </option> + <option> + <name>FillerStart</name> + <state>0x0</state> + </option> + <option> + <name>FillerEnd</name> + <state>0x0</state> + </option> + <option> + <name>CrcSize</name> + <version>0</version> + <state>1</state> + </option> + <option> + <name>CrcAlign</name> + <state>1</state> + </option> + <option> + <name>CrcPoly</name> + <state>0x11021</state> + </option> + <option> + <name>CrcCompl</name> + <version>0</version> + <state>0</state> + </option> + <option> + <name>CrcBitOrder</name> + <version>0</version> + <state>0</state> + </option> + <option> + <name>CrcInitialValue</name> + <state>0x0</state> + </option> + <option> + <name>DoCrc</name> + <state>0</state> + </option> + <option> + <name>IlinkBE8Slave</name> + <state>1</state> + </option> + <option> + <name>IlinkBufferedTerminalOutput</name> + <state>1</state> + </option> + <option> + <name>IlinkStdoutInterfaceSlave</name> + <state>1</state> + </option> + <option> + <name>CrcFullSize</name> + <state>0</state> + </option> + <option> + <name>IlinkIElfToolPostProcess</name> + <state>0</state> + </option> + <option> + <name>IlinkLogAutoLibSelect</name> + <state>0</state> + </option> + <option> + <name>IlinkLogRedirSymbols</name> + <state>0</state> + </option> + <option> + <name>IlinkLogUnusedFragments</name> + <state>0</state> + </option> + <option> + <name>IlinkCrcReverseByteOrder</name> + <state>0</state> + </option> + <option> + <name>IlinkCrcUseAsInput</name> + <state>1</state> + </option> + <option> + <name>IlinkOptInline</name> + <state>1</state> + </option> + <option> + <name>IlinkOptExceptionsAllow</name> + <state>1</state> + </option> + <option> + <name>IlinkOptExceptionsForce</name> + <state>0</state> + </option> + <option> + <name>IlinkCmsis</name> + <state>1</state> + </option> + <option> + <name>IlinkOptMergeDuplSections</name> + <state>0</state> + </option> + <option> + <name>IlinkOptUseVfe</name> + <state>1</state> + </option> + <option> + <name>IlinkOptForceVfe</name> + <state>0</state> + </option> + <option> + <name>IlinkStackAnalysisEnable</name> + <state>0</state> + </option> + <option> + <name>IlinkStackControlFile</name> + <state></state> + </option> + <option> + <name>IlinkStackCallGraphFile</name> + <state></state> + </option> + <option> + <name>CrcAlgorithm</name> + <version>1</version> + <state>1</state> + </option> + <option> + <name>CrcUnitSize</name> + <version>0</version> + <state>0</state> + </option> + <option> + <name>IlinkThreadsSlave</name> + <state>1</state> + </option> + <option> + <name>IlinkLogCallGraph</name> + <state>0</state> + </option> + <option> + <name>IlinkIcfFile_AltDefault</name> + <state></state> + </option> + <option> + <name>IlinkEncInput</name> + <state>0</state> + </option> + <option> + <name>IlinkEncOutput</name> + <state>0</state> + </option> + <option> + <name>IlinkEncOutputBom</name> + <state>1</state> + </option> + <option> + <name>IlinkHeapSelect</name> + <state>1</state> + </option> + <option> + <name>IlinkLocaleSelect</name> + <state>1</state> + </option> + <option> + <name>IlinkTrustzoneImportLibraryOut</name> + <state>sample_threadx_module_manager_import_lib.o</state> + </option> + <option> + <name>OILinkExtraOption</name> + <state>1</state> + </option> + <option> + <name>IlinkRawBinaryFile2</name> + <state></state> + </option> + <option> + <name>IlinkRawBinarySymbol2</name> + <state></state> + </option> + <option> + <name>IlinkRawBinarySegment2</name> + <state></state> + </option> + <option> + <name>IlinkRawBinaryAlign2</name> + <state></state> + </option> + <option> + <name>IlinkLogCrtRoutineSelection</name> + <state>0</state> + </option> + <option> + <name>IlinkLogFragmentInfo</name> + <state>0</state> + </option> + <option> + <name>IlinkLogInlining</name> + <state>0</state> + </option> + <option> + <name>IlinkLogMerging</name> + <state>0</state> + </option> + <option> + <name>IlinkDemangle</name> + <state>0</state> + </option> + <option> + <name>IlinkWrapperFileEnable</name> + <state>0</state> + </option> + <option> + <name>IlinkWrapperFile</name> + <state></state> + </option> + </data> + </settings> + <settings> + <name>IARCHIVE</name> + <archiveVersion>0</archiveVersion> + <data> + <version>0</version> + <wantNonLocal>1</wantNonLocal> + <debug>0</debug> + <option> + <name>IarchiveInputs</name> + <state></state> + </option> + <option> + <name>IarchiveOverride</name> + <state>0</state> + </option> + <option> + <name>IarchiveOutput</name> + <state>###Unitialized###</state> + </option> + </data> + </settings> + <settings> + <name>Coder</name> + <archiveVersion>0</archiveVersion> + <data /> + </settings> + </configuration> + <file> + <name>$PROJ_DIR$\cstartup.s</name> + </file> + <file> + <name>$PROJ_DIR$\sample_threadx_module_manager.c</name> + </file> + <file> + <name>$PROJ_DIR$\Debug\Exe\tx.a</name> + </file> + <file> + <name>$PROJ_DIR$\tx_initialize_low_level.s</name> + </file> +</project> diff --git a/ports_module/cortex_a7/iar/example_build/sample_threadx_module_manager.icf b/ports_module/cortex_a7/iar/example_build/sample_threadx_module_manager.icf new file mode 100644 index 00000000..f076b002 --- /dev/null +++ b/ports_module/cortex_a7/iar/example_build/sample_threadx_module_manager.icf @@ -0,0 +1,51 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x00000040; +define symbol __ICFEDIT_region_ROM_end__ = 0x000FFFFF; //Module in 0x00100000-0x0013FFFF +define symbol __ICFEDIT_region_RAM_start__ = 0x08000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x081FFFFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x200; +define symbol __ICFEDIT_size_svcstack__ = 0x100; +define symbol __ICFEDIT_size_irqstack__ = 0x100; +define symbol __ICFEDIT_size_fiqstack__ = 0x100; +define symbol __ICFEDIT_size_undstack__ = 0x100; +define symbol __ICFEDIT_size_abtstack__ = 0x100; +define symbol __ICFEDIT_size_heap__ = 0x200; +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; + +define symbol __region_DRAM_start__ = 0x80000000; +define symbol __region_DRAM_end__ = 0x807FFFFF; +define region DRAM_region = mem:[from __region_DRAM_start__ to __region_DRAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block SVC_STACK with alignment = 8, size = __ICFEDIT_size_svcstack__ { }; +define block IRQ_STACK with alignment = 8, size = __ICFEDIT_size_irqstack__ { }; +define block FIQ_STACK with alignment = 8, size = __ICFEDIT_size_fiqstack__ { }; +define block UND_STACK with alignment = 8, size = __ICFEDIT_size_undstack__ { }; +define block ABT_STACK with alignment = 8, size = __ICFEDIT_size_abtstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; +define block PAGE_ALIGN with alignment = 4096 { section page_align }; + +initialize by copy { readwrite }; +initialize by copy with packing = none { section __DLIB_PERTHREAD }; // Required in a multi-threaded application +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly, + block PAGE_ALIGN }; +place in RAM_region { readwrite, + block CSTACK, block SVC_STACK, block IRQ_STACK, block FIQ_STACK, + block UND_STACK, block ABT_STACK, block HEAP}; +place in DRAM_region { section DRAM }; + +place in RAM_region { last section FREE_MEM};
\ No newline at end of file diff --git a/ports_module/cortex_a7/iar/example_build/tx.ewd b/ports_module/cortex_a7/iar/example_build/tx.ewd new file mode 100644 index 00000000..42ecf5fe --- /dev/null +++ b/ports_module/cortex_a7/iar/example_build/tx.ewd @@ -0,0 +1,3088 @@ +<?xml version="1.0" encoding="UTF-8"?> +<project> + <fileVersion>3</fileVersion> + <configuration> + <name>Debug</name> + <toolchain> + <name>ARM</name> + </toolchain> + <debug>1</debug> + <settings> + <name>C-SPY</name> + <archiveVersion>2</archiveVersion> + <data> + <version>32</version> + <wantNonLocal>1</wantNonLocal> + <debug>1</debug> + <option> + <name>CInput</name> + <state>1</state> + </option> + <option> + <name>CEndian</name> + <state>1</state> + </option> + <option> + <name>CProcessor</name> + <state>1</state> + </option> + <option> + <name>OCVariant</name> + <state>0</state> + </option> + <option> + <name>MacOverride</name> + <state>0</state> + </option> + <option> + <name>MacFile</name> + <state></state> + </option> + <option> + <name>MemOverride</name> + <state>0</state> + </option> + <option> + <name>MemFile</name> + <state></state> + </option> + <option> + <name>RunToEnable</name> + <state>1</state> + </option> + <option> + <name>RunToName</name> + <state>main</state> + </option> + <option> + <name>CExtraOptionsCheck</name> + <state>0</state> + </option> + <option> + <name>CExtraOptions</name> + <state></state> + </option> + <option> + <name>CFpuProcessor</name> + <state>1</state> + </option> + <option> + <name>OCDDFArgumentProducer</name> + <state></state> + </option> + <option> + <name>OCDownloadSuppressDownload</name> + <state>0</state> + </option> + <option> + <name>OCDownloadVerifyAll</name> + <state>0</state> + </option> + <option> + <name>OCProductVersion</name> + <state>9.20.4.46976</state> + </option> + <option> + <name>OCDynDriverList</name> + <state>ARMSIM_ID</state> + </option> + <option> + <name>OCLastSavedByProductVersion</name> + <state></state> + </option> + <option> + <name>UseFlashLoader</name> + <state>1</state> + </option> + <option> + <name>CLowLevel</name> + <state>1</state> + </option> + <option> + <name>OCBE8Slave</name> + <state>1</state> + </option> + <option> + <name>MacFile2</name> + <state></state> + </option> + <option> + <name>CDevice</name> + <state>1</state> + </option> + <option> + <name>FlashLoadersV3</name> + <state></state> + </option> + <option> + <name>OCImagesSuppressCheck1</name> + <state>0</state> + </option> + <option> + <name>OCImagesPath1</name> + <state></state> + </option> + <option> + <name>OCImagesSuppressCheck2</name> + <state>0</state> + </option> + <option> + <name>OCImagesPath2</name> + <state></state> + </option> + <option> + <name>OCImagesSuppressCheck3</name> + <state>0</state> + </option> + <option> + <name>OCImagesPath3</name> + <state></state> + </option> + <option> + <name>OverrideDefFlashBoard</name> + <state>0</state> + </option> + <option> + <name>OCImagesOffset1</name> + <state></state> + </option> + <option> + <name>OCImagesOffset2</name> + <state></state> + </option> + <option> + <name>OCImagesOffset3</name> + <state></state> + </option> + <option> + <name>OCImagesUse1</name> + <state>0</state> + </option> + <option> + <name>OCImagesUse2</name> + <state>0</state> + </option> + <option> + <name>OCImagesUse3</name> + <state>0</state> + </option> + <option> + <name>OCDeviceConfigMacroFile</name> + <state>1</state> + </option> + <option> + <name>OCDebuggerExtraOption</name> + <state>1</state> + </option> + <option> + <name>OCAllMTBOptions</name> + <state>1</state> + </option> + <option> + <name>OCMulticoreNrOfCores</name> + <state></state> + </option> + <option> + <name>OCMulticoreWorkspace</name> + <state></state> + </option> + <option> + <name>OCMulticoreSlaveProject</name> + <state></state> + </option> + <option> + <name>OCMulticoreSlaveConfiguration</name> + <state></state> + </option> + <option> + <name>OCDownloadExtraImage</name> + <state>1</state> + </option> + <option> + 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+ <archiveVersion>2</archiveVersion> + <data> + <version>0</version> + <wantNonLocal>1</wantNonLocal> + <debug>1</debug> + <option> + <name>CCadiMemory</name> + <state>1</state> + </option> + <option> + <name>Fast Model</name> + <state></state> + </option> + <option> + <name>CCADILogFileCheck</name> + <state>0</state> + </option> + <option> + <name>CCADILogFileEditB</name> + <state>$PROJ_DIR$\cspycomm.log</state> + </option> + <option> + <name>OCDriverInfo</name> + <state>1</state> + </option> + </data> + </settings> + <settings> + <name>CMSISDAP_ID</name> + <archiveVersion>2</archiveVersion> + <data> + <version>4</version> + <wantNonLocal>1</wantNonLocal> + <debug>1</debug> + <option> + <name>OCDriverInfo</name> + <state>1</state> + </option> + <option> + <name>OCIarProbeScriptFile</name> + <state>1</state> + </option> + <option> + <name>CMSISDAPResetList</name> + <version>1</version> + <state>10</state> + </option> + <option> + <name>CMSISDAPHWResetDuration</name> + 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<name>IjetMultiCPUNumber</name> + <state>0</state> + </option> + <option> + <name>IjetSelectedCPUBehaviour</name> + <state>0</state> + </option> + <option> + <name>ICpuName</name> + <state></state> + </option> + <option> + <name>OCJetEmuParams</name> + <state>1</state> + </option> + <option> + <name>IjetPreferETB</name> + <state>1</state> + </option> + <option> + <name>IjetTraceSettingsList</name> + <version>0</version> + <state>0</state> + </option> + <option> + <name>IjetTraceSizeList</name> + <version>0</version> + <state>4</state> + </option> + <option> + <name>FlashBoardPathSlave</name> + <state>0</state> + </option> + <option> + <name>CCIjetUsbSerialNo</name> + <state></state> + </option> + <option> + <name>CCIjetUsbSerialNoSelect</name> + <state>0</state> + </option> + <option> + <name>CatchV8ARReset</name> + <state>0</state> + </option> + <option> + <name>CatchV8AREREL1NS</name> + <state>0</state> + </option> + <option> + <name>CatchV8AREREL1S</name> + <state>0</state> + </option> + <option> + <name>CatchV8AREREL2NS</name> + <state>0</state> + </option> + <option> + <name>CatchV8AREREL3S</name> + <state>0</state> + </option> + <option> + <name>CatchV8AREEL1NS</name> + <state>0</state> + </option> + <option> + <name>CatchV8ARREL1NS</name> + <state>0</state> + </option> + <option> + <name>CatchV8AREEL1S</name> + <state>0</state> + </option> + <option> + <name>CatchV8ARREL1S</name> + <state>0</state> + </option> + <option> + <name>CatchV8AREEL2NS</name> + <state>0</state> + </option> + <option> + <name>CatchV8ARREL2NS</name> + <state>0</state> + </option> + <option> + <name>CatchV8AREEL3S</name> + <state>0</state> + </option> + <option> + <name>CatchV8ARREL3S</name> + <state>0</state> + </option> + </data> + </settings> + <settings> + <name>JLINK_ID</name> + <archiveVersion>2</archiveVersion> + <data> + <version>16</version> + <wantNonLocal>1</wantNonLocal> + <debug>0</debug> + <option> + <name>JLinkSpeed</name> + <state>1000</state> + </option> + <option> + <name>CCJLinkDoLogfile</name> + <state>0</state> + </option> + <option> + <name>CCJLinkLogFile</name> + <state>$PROJ_DIR$\cspycomm.log</state> + </option> + <option> + <name>CCJLinkHWResetDelay</name> + <state>0</state> + </option> + <option> + <name>OCDriverInfo</name> + <state>1</state> + </option> + <option> + <name>JLinkInitialSpeed</name> + <state>1000</state> + </option> + <option> + <name>CCDoJlinkMultiTarget</name> + <state>0</state> + </option> + <option> + <name>CCScanChainNonARMDevices</name> + <state>0</state> + </option> + <option> + <name>CCJLinkMultiTarget</name> + <state>0</state> + </option> + <option> + <name>CCJLinkIRLength</name> + <state>0</state> + </option> + <option> + <name>CCJLinkCommRadio</name> + <state>0</state> + </option> + <option> + <name>CCJLinkTCPIP</name> + <state>aaa.bbb.ccc.ddd</state> + </option> + <option> + <name>CCJLinkSpeedRadioV2</name> + <state>0</state> + </option> + <option> + <name>CCUSBDevice</name> + <version>1</version> + <state>1</state> + </option> + <option> + <name>CCRDICatchReset</name> + <state>0</state> + </option> + <option> + <name>CCRDICatchUndef</name> + <state>0</state> + </option> + <option> + <name>CCRDICatchSWI</name> + <state>0</state> + </option> + <option> + <name>CCRDICatchData</name> + <state>0</state> + </option> + <option> + <name>CCRDICatchPrefetch</name> + <state>0</state> + </option> + <option> + <name>CCRDICatchIRQ</name> + <state>0</state> + </option> + <option> + <name>CCRDICatchFIQ</name> + <state>0</state> + </option> + <option> + <name>CCJLinkBreakpointRadio</name> + <state>0</state> + </option> + <option> + <name>CCJLinkDoUpdateBreakpoints</name> + <state>0</state> + </option> + <option> + <name>CCJLinkUpdateBreakpoints</name> + <state>_call_main</state> + </option> + <option> + <name>CCJLinkInterfaceRadio</name> + <state>1</state> + </option> + <option> + <name>CCJLinkResetList</name> + <version>6</version> + <state>5</state> + </option> + <option> + <name>CCJLinkInterfaceCmdLine</name> + <state>0</state> + </option> + <option> + <name>CCCatchCORERESET</name> + <state>0</state> + </option> + <option> + <name>CCCatchMMERR</name> + <state>0</state> + </option> + <option> + <name>CCCatchNOCPERR</name> + <state>0</state> + </option> + <option> + <name>CCCatchCHRERR</name> + <state>0</state> + </option> + <option> + <name>CCCatchSTATERR</name> + <state>0</state> + </option> + <option> + <name>CCCatchBUSERR</name> + <state>0</state> + </option> + <option> + <name>CCCatchINTERR</name> + <state>0</state> + </option> + <option> + <name>CCCatchSFERR</name> + <state>0</state> + </option> + <option> + <name>CCCatchHARDERR</name> + <state>0</state> + </option> + <option> + <name>CCCatchDummy</name> + <state>0</state> + </option> + <option> + <name>OCJLinkScriptFile</name> + <state>1</state> + </option> + <option> + <name>CCJLinkUsbSerialNo</name> + <state></state> + </option> + <option> + <name>CCTcpIpAlt</name> + <version>0</version> + <state>0</state> + </option> + <option> + <name>CCJLinkTcpIpSerialNo</name> + <state></state> + </option> + <option> + <name>CCCpuClockEdit</name> + <state></state> + </option> + <option> + <name>CCSwoClockAuto</name> + <state>0</state> + </option> + <option> + <name>CCSwoClockEdit</name> + <state>2000</state> + </option> + <option> + <name>OCJLinkTraceSource</name> + <state>0</state> + </option> + <option> + <name>OCJLinkTraceSourceDummy</name> + <state>0</state> + </option> + <option> + <name>OCJLinkDeviceName</name> + <state>1</state> + </option> + </data> + </settings> + <settings> + <name>LMIFTDI_ID</name> + <archiveVersion>2</archiveVersion> + <data> + <version>3</version> + <wantNonLocal>1</wantNonLocal> + <debug>0</debug> + <option> + <name>OCDriverInfo</name> + <state>1</state> + </option> + <option> + <name>LmiftdiSpeed</name> + <state>500</state> + </option> + <option> + <name>CCLmiftdiDoLogfile</name> + <state>0</state> + </option> + <option> + <name>CCLmiftdiLogFile</name> + <state>$PROJ_DIR$\cspycomm.log</state> + </option> + <option> + <name>CCLmiFtdiInterfaceRadio</name> + <state>1</state> + </option> + <option> + <name>CCLmiFtdiInterfaceCmdLine</name> + <state>0</state> + </option> + <option> + <name>CCLmiftdiUsbSerialNo</name> + <state></state> + </option> + <option> + <name>CCLmiftdiUsbSerialNoSelect</name> + <state>0</state> + </option> + <option> + <name>CCLmiftdiResetList</name> + <version>0</version> + <state>0</state> + </option> + </data> + </settings> + <settings> + <name>NULINK_ID</name> + <archiveVersion>2</archiveVersion> + <data> + <version>0</version> + <wantNonLocal>1</wantNonLocal> + <debug>0</debug> + <option> + <name>OCDriverInfo</name> + <state>1</state> + </option> + <option> + <name>DoLogfile</name> + <state>0</state> + </option> + <option> + <name>LogFile</name> + <state>$PROJ_DIR$\cspycomm.log</state> + </option> + </data> + </settings> + <settings> + <name>PEMICRO_ID</name> + <archiveVersion>2</archiveVersion> + <data> + <version>3</version> + <wantNonLocal>1</wantNonLocal> + <debug>0</debug> + <option> + <name>OCDriverInfo</name> + <state>1</state> + </option> + <option> + <name>CCJPEMicroShowSettings</name> + <state>0</state> + </option> + <option> + <name>DoLogfile</name> + <state>0</state> + </option> + <option> + <name>LogFile</name> + <state>$PROJ_DIR$\cspycomm.log</state> + </option> + </data> + </settings> + <settings> + <name>STLINK_ID</name> + <archiveVersion>2</archiveVersion> + <data> + <version>7</version> + <wantNonLocal>1</wantNonLocal> + <debug>0</debug> + <option> + <name>OCDriverInfo</name> + <state>1</state> + </option> + <option> + <name>CCSTLinkInterfaceRadio</name> + <state>1</state> + </option> + <option> + <name>CCSTLinkInterfaceCmdLine</name> + <state>0</state> + </option> + <option> + <name>CCSTLinkResetList</name> + <version>3</version> + <state>0</state> + </option> + <option> + <name>CCCpuClockEdit</name> + <state></state> + </option> + <option> + <name>CCSwoClockAuto</name> + <state>1</state> + </option> + <option> + <name>CCSwoClockEdit</name> + <state>2000</state> + </option> + <option> + <name>DoLogfile</name> + <state>0</state> + </option> + <option> + <name>LogFile</name> + <state>$PROJ_DIR$\cspycomm.log</state> + </option> + <option> + <name>CCSTLinkDoUpdateBreakpoints</name> + <state>0</state> + </option> + <option> + <name>CCSTLinkUpdateBreakpoints</name> + <state>_call_main</state> + </option> + <option> + <name>CCSTLinkCatchCORERESET</name> + <state>0</state> + </option> + <option> + <name>CCSTLinkCatchMMERR</name> + <state>0</state> + </option> + <option> + <name>CCSTLinkCatchNOCPERR</name> + <state>0</state> + </option> + <option> + <name>CCSTLinkCatchCHRERR</name> + <state>0</state> + </option> + <option> + <name>CCSTLinkCatchSTATERR</name> + <state>0</state> + </option> + <option> + <name>CCSTLinkCatchBUSERR</name> + <state>0</state> + </option> + <option> + <name>CCSTLinkCatchINTERR</name> + <state>0</state> + </option> + <option> + <name>CCSTLinkCatchSFERR</name> + <state>0</state> + </option> + <option> + <name>CCSTLinkCatchHARDERR</name> + <state>0</state> + </option> + <option> + <name>CCSTLinkCatchDummy</name> + <state>0</state> + </option> + <option> + <name>CCSTLinkUsbSerialNo</name> + <state></state> + </option> + <option> + <name>CCSTLinkUsbSerialNoSelect</name> + <state>0</state> + </option> + <option> + <name>CCSTLinkJtagSpeedList</name> + <version>2</version> + <state>0</state> + </option> + <option> + <name>CCSTLinkDAPNumber</name> + <state></state> + </option> + <option> + <name>CCSTLinkDebugAccessPortRadio</name> + <state>0</state> + </option> + <option> + <name>CCSTLinkUseServerSelect</name> + <state>0</state> + </option> + <option> + <name>CCSTLinkProbeList</name> + <version>1</version> + <state>0</state> + </option> + </data> + </settings> + <settings> + <name>THIRDPARTY_ID</name> + <archiveVersion>2</archiveVersion> + <data> + <version>0</version> + <wantNonLocal>1</wantNonLocal> + <debug>0</debug> + <option> + <name>CThirdPartyDriverDll</name> + <state>###Uninitialized###</state> + </option> + <option> + <name>CThirdPartyLogFileCheck</name> + <state>0</state> + </option> + <option> + <name>CThirdPartyLogFileEditB</name> + <state>$PROJ_DIR$\cspycomm.log</state> + </option> + <option> + <name>OCDriverInfo</name> + <state>1</state> + </option> + </data> + </settings> + <settings> + <name>TIFET_ID</name> + <archiveVersion>2</archiveVersion> + <data> + <version>1</version> + <wantNonLocal>1</wantNonLocal> + <debug>0</debug> + <option> + <name>OCDriverInfo</name> + <state>1</state> + </option> + <option> + <name>CCMSPFetResetList</name> + <version>0</version> + <state>0</state> + </option> + <option> + <name>CCMSPFetInterfaceRadio</name> + <state>0</state> + </option> + <option> + <name>CCMSPFetInterfaceCmdLine</name> + <state>0</state> + </option> + <option> + <name>CCMSPFetTargetVccTypeDefault</name> + <state>0</state> + </option> + <option> + <name>CCMSPFetTargetVoltage</name> + <state>###Uninitialized###</state> + </option> + <option> + <name>CCMSPFetVCCDefault</name> + <state>1</state> + </option> + <option> + <name>CCMSPFetTargetSettlingtime</name> + <state>0</state> + </option> + <option> + <name>CCMSPFetRadioJtagSpeedType</name> + <state>1</state> + </option> + <option> + <name>CCMSPFetConnection</name> + <version>0</version> + <state>0</state> + </option> + <option> + <name>CCMSPFetUsbComPort</name> + <state>Automatic</state> + </option> + <option> + <name>CCMSPFetAllowAccessToBSL</name> + <state>0</state> + </option> + <option> + <name>CCMSPFetDoLogfile</name> + <state>0</state> + </option> + <option> + <name>CCMSPFetLogFile</name> + <state>$PROJ_DIR$\cspycomm.log</state> + </option> + <option> + <name>CCMSPFetRadioEraseFlash</name> + <state>1</state> + </option> + </data> + </settings> + <settings> + <name>XDS100_ID</name> + <archiveVersion>2</archiveVersion> + <data> + <version>9</version> + <wantNonLocal>1</wantNonLocal> + <debug>0</debug> + <option> + <name>OCDriverInfo</name> + <state>1</state> + </option> + <option> + <name>TIPackageOverride</name> + <state>0</state> + </option> + <option> + <name>TIPackage</name> + <state></state> + </option> + <option> + <name>BoardFile</name> + <state></state> + </option> + <option> + <name>DoLogfile</name> + <state>0</state> + </option> + <option> + <name>LogFile</name> + <state>$PROJ_DIR$\cspycomm.log</state> + </option> + <option> + <name>CCXds100BreakpointRadio</name> + <state>0</state> + </option> + <option> + <name>CCXds100DoUpdateBreakpoints</name> + <state>0</state> + </option> + <option> + <name>CCXds100UpdateBreakpoints</name> + <state>_call_main</state> + </option> + <option> + <name>CCXds100CatchReset</name> + <state>0</state> + </option> + <option> + <name>CCXds100CatchUndef</name> + <state>0</state> + </option> + <option> + <name>CCXds100CatchSWI</name> + <state>0</state> + </option> + <option> + <name>CCXds100CatchData</name> + <state>0</state> + </option> + <option> + <name>CCXds100CatchPrefetch</name> + <state>0</state> + </option> + <option> + <name>CCXds100CatchIRQ</name> + <state>0</state> + </option> + <option> + <name>CCXds100CatchFIQ</name> + <state>0</state> + </option> + <option> + <name>CCXds100CatchCORERESET</name> + <state>0</state> + </option> + <option> + <name>CCXds100CatchMMERR</name> + <state>0</state> + </option> + <option> + <name>CCXds100CatchNOCPERR</name> + <state>0</state> + </option> + <option> + <name>CCXds100CatchCHRERR</name> + <state>0</state> + </option> + <option> + <name>CCXds100CatchSTATERR</name> + <state>0</state> + </option> + <option> + <name>CCXds100CatchBUSERR</name> + <state>0</state> + </option> + <option> + <name>CCXds100CatchINTERR</name> + <state>0</state> + </option> + <option> + <name>CCXds100CatchSFERR</name> + <state>0</state> + </option> + <option> + <name>CCXds100CatchHARDERR</name> + <state>0</state> + </option> + <option> + <name>CCXds100CatchDummy</name> + <state>0</state> + </option> + <option> + <name>CCXds100CpuClockEdit</name> + <state></state> + </option> + <option> + <name>CCXds100SwoClockAuto</name> + <state>0</state> + </option> + <option> + <name>CCXds100SwoClockEdit</name> + <state>1000</state> + </option> + <option> + <name>CCXds100HWResetDelay</name> + <state>0</state> + </option> + <option> + <name>CCXds100ResetList</name> + <version>1</version> + <state>0</state> + </option> + <option> + <name>CCXds100UsbSerialNo</name> + <state></state> + </option> + <option> + <name>CCXds100UsbSerialNoSelect</name> + <state>0</state> + </option> + <option> + <name>CCXds100JtagSpeedList</name> + <version>0</version> + <state>0</state> + </option> + <option> + <name>CCXds100InterfaceRadio</name> + <state>2</state> + </option> + <option> + <name>CCXds100InterfaceCmdLine</name> + <state>0</state> + </option> + <option> + <name>CCXds100ProbeList</name> + <version>0</version> + <state>3</state> + </option> + <option> + <name>CCXds100SWOPortRadio</name> + <state>0</state> + </option> + <option> + <name>CCXds100SWOPort</name> + <state>1</state> + </option> + <option> + <name>CCXDSTargetVccEnable</name> + <state>0</state> + </option> + <option> + <name>CCXDSTargetVoltage</name> + <state>###Uninitialized###</state> + </option> + <option> + <name>OCXDSDigitalStatesConfigFile</name> + <state>1</state> + </option> + <option> + <name>OCSelectedCoreName</name> + <state>1</state> + </option> + </data> + </settings> + <debuggerPlugins> + <plugin> + <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$TOOLKIT_DIR$\plugins\rtos\FreeRtos\FreeRtosArmPlugin.ENU.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin2.ENU.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm9.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm9BE.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + </debuggerPlugins> + </configuration> +</project> diff --git a/ports_module/cortex_a7/iar/example_build/tx.ewp b/ports_module/cortex_a7/iar/example_build/tx.ewp new file mode 100644 index 00000000..a8855ffd --- /dev/null +++ b/ports_module/cortex_a7/iar/example_build/tx.ewp @@ -0,0 +1,2893 @@ +<?xml version="1.0" encoding="UTF-8"?> +<project> + <fileVersion>3</fileVersion> + <configuration> + <name>Debug</name> + <toolchain> + <name>ARM</name> + </toolchain> + <debug>1</debug> + <settings> + <name>General</name> + <archiveVersion>3</archiveVersion> + <data> + <version>34</version> + <wantNonLocal>1</wantNonLocal> + <debug>1</debug> + <option> + <name>BrowseInfoPath</name> + <state>Debug\BrowseInfo</state> + </option> + <option> + <name>ExePath</name> + <state>Debug\Exe</state> + </option> + <option> + <name>ObjPath</name> + <state>Debug\Obj</state> + </option> + <option> + <name>ListPath</name> + <state>Debug\List</state> + </option> + <option> + <name>GEndianMode</name> + <state>0</state> + </option> + <option> + <name>Input description</name> + <state>Full formatting, without multibyte support.</state> + </option> + <option> + <name>Output description</name> + <state>Full formatting, without multibyte support.</state> + </option> + <option> + <name>GOutputBinary</name> + <state>1</state> + </option> + <option> + <name>OGCoreOrChip</name> + <state>0</state> + </option> + <option> + <name>GRuntimeLibSelect</name> + <version>0</version> + <state>1</state> + </option> + <option> + <name>GRuntimeLibSelectSlave</name> + <version>0</version> + <state>1</state> + </option> + <option> + <name>RTDescription</name> + <state>To be used with the normal configuration of the C/C++ runtime library. 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</file> + <file> + <name>$PROJ_DIR$\..\..\..\..\common_modules\module_manager\src\txm_module_manager_application_request.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\common_modules\module_manager\src\txm_module_manager_callback_request.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\common_modules\module_manager\src\txm_module_manager_event_flags_notify_trampoline.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\module_manager\src\txm_module_manager_external_memory_enable.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\common_modules\module_manager\src\txm_module_manager_file_load.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\common_modules\module_manager\src\txm_module_manager_in_place_load.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\common_modules\module_manager\src\txm_module_manager_initialize.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\common_modules\module_manager\src\txm_module_manager_internal_load.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\common_modules\module_manager\src\txm_module_manager_kernel_dispatch.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\common_modules\module_manager\src\txm_module_manager_maximum_module_priority_set.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\module_manager\src\txm_module_manager_memory_fault_handler.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\module_manager\src\txm_module_manager_memory_fault_notify.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\common_modules\module_manager\src\txm_module_manager_memory_load.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\module_manager\src\txm_module_manager_mm_initialize.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\module_manager\src\txm_module_manager_mm_register_setup.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\common_modules\module_manager\src\txm_module_manager_object_allocate.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\common_modules\module_manager\src\txm_module_manager_object_deallocate.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\common_modules\module_manager\src\txm_module_manager_object_pointer_get.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\common_modules\module_manager\src\txm_module_manager_object_pointer_get_extended.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\common_modules\module_manager\src\txm_module_manager_object_pool_create.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\common_modules\module_manager\src\txm_module_manager_properties_get.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\common_modules\module_manager\src\txm_module_manager_queue_notify_trampoline.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\common_modules\module_manager\src\txm_module_manager_semaphore_notify_trampoline.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\common_modules\module_manager\src\txm_module_manager_start.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\common_modules\module_manager\src\txm_module_manager_stop.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\common_modules\module_manager\src\txm_module_manager_thread_create.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\common_modules\module_manager\src\txm_module_manager_thread_notify_trampoline.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\common_modules\module_manager\src\txm_module_manager_thread_reset.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\module_manager\src\txm_module_manager_thread_stack_build.s</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\common_modules\module_manager\src\txm_module_manager_timer_notify_trampoline.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\common_modules\module_manager\src\txm_module_manager_unload.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\module_manager\src\txm_module_manager_user_mode_entry.s</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\common_modules\module_manager\src\txm_module_manager_util.c</name> + </file> + </group> +</project> diff --git a/ports_module/cortex_a7/iar/example_build/tx_initialize_low_level.s b/ports_module/cortex_a7/iar/example_build/tx_initialize_low_level.s new file mode 100644 index 00000000..f592c1ed --- /dev/null +++ b/ports_module/cortex_a7/iar/example_build/tx_initialize_low_level.s @@ -0,0 +1,456 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Initialize */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_initialize.h" +;#include "tx_thread.h" +;#include "tx_timer.h" +; +; +SVC_MODE DEFINE 0xD3 ; Disable irq,fiq SVC mode +IRQ_MODE DEFINE 0xD2 ; Disable irq,fiq IRQ mode +FIQ_MODE DEFINE 0xD1 ; Disable irq,fiq FIQ mode +SYS_MODE DEFINE 0x1F ; Disable irq,fiq SYS mode +; +; + + EXTERN _tx_thread_system_stack_ptr + EXTERN _tx_initialize_unused_memory + EXTERN _tx_thread_context_save +; EXTERN _tx_thread_vectored_context_save + EXTERN _tx_thread_context_restore +#ifdef TX_ENABLE_FIQ_SUPPORT + EXTERN _tx_thread_fiq_context_save + EXTERN _tx_thread_fiq_context_restore +#endif +#ifdef TX_ENABLE_IRQ_NESTING + EXTERN _tx_thread_irq_nesting_start + EXTERN _tx_thread_irq_nesting_end +#endif +#ifdef TX_ENABLE_FIQ_NESTING + EXTERN _tx_thread_fiq_nesting_start + EXTERN _tx_thread_fiq_nesting_end +#endif + EXTERN _tx_timer_interrupt + EXTERN ?cstartup + EXTERN _tx_build_options + EXTERN _tx_version_id +; +; +; +;/* Define the FREE_MEM segment that will specify where free memory is +; defined. This must also be located in at the end of other RAM segments +; in the linker control file. The value of this segment is what is passed +; to tx_application_define. */ +; + RSEG FREE_MEM:DATA + PUBLIC __tx_free_memory_start +__tx_free_memory_start + DS32 4 +; +; +; +; +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_initialize_low_level Cortex-A7/IAR */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is responsible for any low-level processor */ +;/* initialization, including setting up interrupt vectors, setting */ +;/* up a periodic timer interrupt source, saving the system stack */ +;/* pointer for use in ISR processing later, and finding the first */ +;/* available RAM memory address for tx_application_define. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_initialize_kernel_enter ThreadX entry function */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_initialize_low_level(VOID) +;{ + RSEG .text:CODE:NOROOT(2) + CODE32 + PUBLIC _tx_initialize_low_level +_tx_initialize_low_level +; +; /****** NOTE ****** The IAR 4.11a and above releases call main in SYS mode. */ +; +; /* Remember the stack pointer, link register, and switch to SVC mode. */ +; + MOV r0, sp ; Remember the SP + MOV r1, lr ; Remember the LR + MOV r3, #SVC_MODE ; Build SVC mode CPSR + MSR CPSR_cxsf, r3 ; Switch to SVC mode + MOV sp, r0 ; Inherit the stack pointer setup by cstartup + MOV lr, r1 ; Inherit the link register +; +; /* Pickup the start of free memory. */ +; + LDR r0, =__tx_free_memory_start ; Get end of non-initialized RAM area +; +; /* Save the system stack pointer. */ +; _tx_thread_system_stack_ptr = (VOID_PTR) (sp); +; +; /* Save the first available memory address. */ +; _tx_initialize_unused_memory = (VOID_PTR) FREE_MEM; +; + LDR r2, =_tx_initialize_unused_memory ; Pickup unused memory ptr address + STR r0, [r2, #0] ; Save first free memory address +; +; /* Setup Timer for periodic interrupts. */ +; +; /* Done, return to caller. */ +; +#ifdef TX_THUMB + BX lr ; Return to caller +#else + MOV pc, lr ; Return to caller +#endif +;} +; +;/* Define shells for each of the interrupt vectors. */ +; + RSEG .text:CODE:NOROOT(2) + PUBLIC __tx_undefined +__tx_undefined + B __tx_undefined ; Undefined handler +; + RSEG .text:CODE:NOROOT(2) + PUBLIC __tx_swi_interrupt +__tx_swi_interrupt + B __tx_swi_interrupt ; Software interrupt handler +; + RSEG .text:CODE:NOROOT(2) + PUBLIC __tx_reserved_handler +__tx_reserved_handler + B __tx_reserved_handler ; Reserved exception handler +; + RSEG .text:CODE:NOROOT(2) + PUBLIC __tx_irq_handler + RSEG .text:CODE:NOROOT(2) + PUBLIC __tx_irq_processing_return +__tx_irq_handler +; +; /* Jump to context save to save system context. */ + B _tx_thread_context_save +__tx_irq_processing_return +; +; /* At this point execution is still in the IRQ mode. The CPSR, point of +; interrupt, and all C scratch registers are available for use. In +; addition, IRQ interrupts may be re-enabled - with certain restrictions - +; if nested IRQ interrupts are desired. Interrupts may be re-enabled over +; small code sequences where lr is saved before enabling interrupts and +; restored after interrupts are again disabled. */ +; +; /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start +; from IRQ mode with interrupts disabled. This routine switches to the +; system mode and returns with IRQ interrupts enabled. +; +; NOTE: It is very important to ensure all IRQ interrupts are cleared +; prior to enabling nested IRQ interrupts. */ +#ifdef TX_ENABLE_IRQ_NESTING + BL _tx_thread_irq_nesting_start +#endif +; +; /* For debug purpose, execute the timer interrupt processing here. In +; a real system, some kind of status indication would have to be checked +; before the timer interrupt handler could be called. */ +; + BL _tx_timer_interrupt ; Timer interrupt handler +; +; /* Application IRQ handlers can be called here! */ +; +; /* If interrupt nesting was started earlier, the end of interrupt nesting +; service must be called before returning to _tx_thread_context_restore. +; This routine returns in processing in IRQ mode with interrupts disabled. */ +#ifdef TX_ENABLE_IRQ_NESTING + BL _tx_thread_irq_nesting_end +#endif +; +; /* Jump to context restore to restore system context. */ + B _tx_thread_context_restore +; +; +; /* This is an example of a vectored IRQ handler. */ +; +; RSEG .text:CODE:NOROOT(2) +; PUBLIC __tx_example_vectored_irq_handler +;__tx_example_vectored_irq_handler +; +; /* Jump to context save to save system context. */ +; STMDB sp!, {r0-r3} ; Save some scratch registers +; MRS r0, SPSR ; Pickup saved SPSR +; SUB lr, lr, #4 ; Adjust point of interrupt +; STMDB sp!, {r0, r10, r12, lr} ; Store other registers +; BL _tx_thread_vectored_context_save +; +; /* At this point execution is still in the IRQ mode. The CPSR, point of +; interrupt, and all C scratch registers are available for use. In +; addition, IRQ interrupts may be re-enabled - with certain restrictions - +; if nested IRQ interrupts are desired. Interrupts may be re-enabled over +; small code sequences where lr is saved before enabling interrupts and +; restored after interrupts are again disabled. */ +; +; /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start +; from IRQ mode with interrupts disabled. This routine switches to the +; system mode and returns with IRQ interrupts enabled. +; +; NOTE: It is very important to ensure all IRQ interrupts are cleared +; prior to enabling nested IRQ interrupts. */ +;#ifdef TX_ENABLE_IRQ_NESTING +; BL _tx_thread_irq_nesting_start +;#endif +; +; /* Application IRQ handler is called here! */ +; +; /* If interrupt nesting was started earlier, the end of interrupt nesting +; service must be called before returning to _tx_thread_context_restore. +; This routine returns in processing in IRQ mode with interrupts disabled. */ +;#ifdef TX_ENABLE_IRQ_NESTING +; BL _tx_thread_irq_nesting_end +;#endif +; +; /* Jump to context restore to restore system context. */ +; B _tx_thread_context_restore +; +; +#ifdef TX_ENABLE_FIQ_SUPPORT + RSEG .text:CODE:NOROOT(2) + PUBLIC __tx_fiq_handler + RSEG .text:CODE:NOROOT(2) + PUBLIC __tx_fiq_processing_return +__tx_fiq_handler +; +; /* Jump to fiq context save to save system context. */ + B _tx_thread_fiq_context_save +__tx_fiq_processing_return +; +; /* At this point execution is still in the FIQ mode. The CPSR, point of +; interrupt, and all C scratch registers are available for use. */ +; +; /* Interrupt nesting is allowed after calling _tx_thread_fiq_nesting_start +; from FIQ mode with interrupts disabled. This routine switches to the +; system mode and returns with FIQ interrupts enabled. +; +; NOTE: It is very important to ensure all FIQ interrupts are cleared +; prior to enabling nested FIQ interrupts. */ +#ifdef TX_ENABLE_FIQ_NESTING + BL _tx_thread_fiq_nesting_start +#endif +; +; /* Application FIQ handlers can be called here! */ +; +; /* If interrupt nesting was started earlier, the end of interrupt nesting +; service must be called before returning to _tx_thread_fiq_context_restore. */ +#ifdef TX_ENABLE_FIQ_NESTING + BL _tx_thread_fiq_nesting_end +#endif +; +; /* Jump to fiq context restore to restore system context. */ + B _tx_thread_fiq_context_restore +; +; +#else + RSEG .text:CODE:NOROOT(2) + PUBLIC __tx_fiq_handler +__tx_fiq_handler + B __tx_fiq_handler ; FIQ interrupt handler +#endif + + +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* __tx_prefetch_handler & __tx_abort_handler Cortex-A7/MMU/IAR */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* Scott Larson, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function handles MMU exceptions and fills the */ +;/* _txm_module_manager_memory_fault_info struct. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _txm_module_manager_memory_fault_handler */ +;/* _tx_execution_thread_exit */ +;/* _tx_thread_schedule */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* MMU exceptions */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 Scott Larson Initial Version 6.1 */ +;/* */ +;/**************************************************************************/ + +; ******************************************************************* +; MMU Exception Handling +; ******************************************************************* +THUMB_MASK DEFINE 0x20 ; Thumb bit (5) of CPSR/SPSR +ABT_MODE DEFINE 0x17 ; ABORT mode + + EXTERN _tx_thread_system_state + EXTERN _txm_module_manager_memory_fault_info + EXTERN _tx_thread_current_ptr + EXTERN _txm_module_manager_memory_fault_handler + EXTERN _tx_execution_thread_exit + EXTERN _tx_thread_schedule + RSEG .text:CODE:NOROOT(2) + ARM + PUBLIC __tx_prefetch_handler + PUBLIC __tx_abort_handler +__tx_prefetch_handler +__tx_abort_handler + STMDB sp!, {r0-r3} ; Save some working registers + LDR r3, =_tx_thread_system_state ; Pickup address of system state var + LDR r2, [r3, #0] ; Pickup system state + ADD r2, r2, #1 ; Increment the interrupt counter + STR r2, [r3, #0] ; Store it back in the variable + SUB lr, lr, #4 ; Adjust point of exception +; +; /* Now pickup and store all the fault related information. */ +; + ; Pickup the memory fault info struct + LDR r3, =_txm_module_manager_memory_fault_info + LDR r0, =_tx_thread_current_ptr ; Build current thread pointer address + LDR r1, [r0] ; Pickup the current thread pointer + STR r1, [r3, #0] ; Save current thread pointer + STR lr, [r3, #4] ; Save point of fault + MRC p15, 0, r0, c6, c0, 0 ; Read DFAR + STR r0, [r3, #8] ; Save DFAR + MRC p15, 0, r0, c5, c0, 0 ; Read DFSR + STR r0, [r3, #12] ; Save DFSR + MRC p15, 0, r0, c6, c0, 2 ; Read IFAR + STR r0, [r3, #16] ; Save IFAR + MRC p15, 0, r0, c5, c0, 1 ; Read IFSR + STR r0, [r3, #20] ; Save IFSR + + ; Save registers r0-r12 + POP {r0-r2} + STR r0, [r3, #28] ; Save r0 + STR r1, [r3, #32] ; Save r1 + STR r2, [r3, #36] ; Save r2 + POP {r0} + STR r0, [r3, #40] ; Save r3 + STR r4, [r3, #44] ; Save r4 + STR r5, [r3, #48] ; Save r5 + STR r6, [r3, #52] ; Save r6 + STR r7, [r3, #56] ; Save r7 + STR r8, [r3, #60] ; Save r8 + STR r9, [r3, #64] ; Save r9 + STR r10,[r3, #68] ; Save r10 + STR r11,[r3, #72] ; Save r11 + STR r12,[r3, #76] ; Save r12 + + CPS #SYS_MODE ; Enter SYS mode + MOV r0, lr ; Pickup lr + MOV r1, sp ; Pickup sp + CPS #ABT_MODE ; Back to ABT mode + STR r0, [r3, #80] ; Save lr + STR r1, [r3, #24] ; Save sp + MRS r0, SPSR ; Pickup SPSR + STR r0, [r3, #84] ; Save SPSR + ORR r0, r0, #SYS_MODE ; Return into SYS mode + BIC r0, r0, #THUMB_MASK ; Clear THUMB mode + MSR SPSR_c, r0 ; Save SPSR + + ; Call memory manager fault handler + BL _txm_module_manager_memory_fault_handler + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the thread exit function to indicate the thread is no longer executing. */ +; + BL _tx_execution_thread_exit ; Call the thread exit function +#endif + + LDR r0, =_tx_thread_system_state ; Pickup address of system state + LDR r1, [r0] ; Pickup system state + SUB r1, r1, #1 ; Decrement + STR r1, [r0] ; Store new system state + + MOV r1, #0 ; Build NULL value + LDR r0, =_tx_thread_current_ptr ; Pickup address of current thread pointer + STR r1, [r0] ; Clear current thread pointer + + ; Return from exception + LDR lr, =_tx_thread_schedule ; Load scheduler address + MOVS pc, lr ; Return to scheduler +; ******************************************************************* +; End of MMU exception handling. +; ******************************************************************* + + +BUILD_OPTIONS + DC32 _tx_build_options ; Reference to ensure it comes in +VERSION_ID + DC32 _tx_version_id ; Reference to ensure it comes in + + END diff --git a/ports_module/cortex_a7/iar/example_build/txm.ewd b/ports_module/cortex_a7/iar/example_build/txm.ewd new file mode 100644 index 00000000..42ecf5fe --- /dev/null +++ b/ports_module/cortex_a7/iar/example_build/txm.ewd @@ -0,0 +1,3088 @@ +<?xml version="1.0" encoding="UTF-8"?> +<project> + <fileVersion>3</fileVersion> + <configuration> + <name>Debug</name> + <toolchain> + <name>ARM</name> + </toolchain> + <debug>1</debug> + <settings> + <name>C-SPY</name> + <archiveVersion>2</archiveVersion> + <data> + <version>32</version> + <wantNonLocal>1</wantNonLocal> + <debug>1</debug> + <option> + <name>CInput</name> + <state>1</state> + </option> + <option> + <name>CEndian</name> + <state>1</state> + </option> + <option> + <name>CProcessor</name> + <state>1</state> + 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<name>CCXds100CatchSFERR</name> + <state>0</state> + </option> + <option> + <name>CCXds100CatchHARDERR</name> + <state>0</state> + </option> + <option> + <name>CCXds100CatchDummy</name> + <state>0</state> + </option> + <option> + <name>CCXds100CpuClockEdit</name> + <state></state> + </option> + <option> + <name>CCXds100SwoClockAuto</name> + <state>0</state> + </option> + <option> + <name>CCXds100SwoClockEdit</name> + <state>1000</state> + </option> + <option> + <name>CCXds100HWResetDelay</name> + <state>0</state> + </option> + <option> + <name>CCXds100ResetList</name> + <version>1</version> + <state>0</state> + </option> + <option> + <name>CCXds100UsbSerialNo</name> + <state></state> + </option> + <option> + <name>CCXds100UsbSerialNoSelect</name> + <state>0</state> + </option> + <option> + <name>CCXds100JtagSpeedList</name> + <version>0</version> + <state>0</state> + </option> + <option> + <name>CCXds100InterfaceRadio</name> + <state>2</state> + </option> + <option> + <name>CCXds100InterfaceCmdLine</name> + <state>0</state> + </option> + <option> + <name>CCXds100ProbeList</name> + <version>0</version> + <state>3</state> + </option> + <option> + <name>CCXds100SWOPortRadio</name> + <state>0</state> + </option> + <option> + <name>CCXds100SWOPort</name> + <state>1</state> + </option> + <option> + <name>CCXDSTargetVccEnable</name> + <state>0</state> + </option> + <option> + <name>CCXDSTargetVoltage</name> + <state>###Uninitialized###</state> + </option> + <option> + <name>OCXDSDigitalStatesConfigFile</name> + <state>1</state> + </option> + <option> + <name>OCSelectedCoreName</name> + <state>1</state> + </option> + </data> + </settings> + <debuggerPlugins> + <plugin> + <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$TOOLKIT_DIR$\plugins\rtos\FreeRtos\FreeRtosArmPlugin.ENU.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin2.ENU.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm9.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm9BE.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + </debuggerPlugins> + </configuration> +</project> diff --git a/ports_module/cortex_a7/iar/example_build/txm.ewp b/ports_module/cortex_a7/iar/example_build/txm.ewp new file mode 100644 index 00000000..5eef0927 --- /dev/null +++ b/ports_module/cortex_a7/iar/example_build/txm.ewp @@ -0,0 +1,2475 @@ +<?xml version="1.0" encoding="UTF-8"?> +<project> + <fileVersion>3</fileVersion> + <configuration> + <name>Debug</name> + <toolchain> + <name>ARM</name> + </toolchain> + <debug>1</debug> + <settings> + <name>General</name> + <archiveVersion>3</archiveVersion> + <data> + <version>34</version> + <wantNonLocal>1</wantNonLocal> + <debug>1</debug> + <option> + <name>BrowseInfoPath</name> + <state>Debug\BrowseInfo</state> + </option> + <option> + <name>ExePath</name> + <state>Debug\Exe</state> + </option> + <option> + <name>ObjPath</name> + <state>Debug\Obj</state> + </option> + <option> + <name>ListPath</name> + <state>Debug\List</state> + </option> + <option> + <name>GEndianMode</name> + <state>0</state> + </option> + <option> + <name>Input description</name> + <state>Full formatting, without multibyte support.</state> + </option> + <option> + <name>Output description</name> + <state>Full formatting, without multibyte support.</state> + </option> + <option> + <name>GOutputBinary</name> + <state>1</state> + </option> + <option> + <name>OGCoreOrChip</name> + <state>0</state> + </option> + <option> + <name>GRuntimeLibSelect</name> + <version>0</version> + <state>1</state> + </option> + <option> + <name>GRuntimeLibSelectSlave</name> + <version>0</version> + <state>1</state> + </option> + <option> + <name>RTDescription</name> + <state>To be used with the normal configuration of the C/C++ runtime library. No locale interface, C locale, no file descriptor support, no multibytes in printf and scanf, and no hex floats in strtod.</state> + </option> + <option> + <name>OGProductVersion</name> + <state>6.10.1.52170</state> + </option> + <option> + <name>OGLastSavedByProductVersion</name> + <state>9.20.4.46976</state> + </option> + <option> + <name>OGChipSelectEditMenu</name> + <state>Default None</state> + </option> + <option> + <name>GenLowLevelInterface</name> + <state>1</state> + </option> + <option> + <name>GEndianModeBE</name> + <state>0</state> + </option> + <option> + <name>OGBufferedTerminalOutput</name> + <state>0</state> + </option> + <option> + <name>GenStdoutInterface</name> + <state>0</state> + </option> + <option> + <name>RTConfigPath2</name> + <state>$TOOLKIT_DIR$\inc\c\DLib_Config_Normal.h</state> + </option> + <option> + <name>GBECoreSlave</name> + <version>31</version> + <state>42</state> + </option> + <option> + <name>OGUseCmsis</name> + <state>0</state> + </option> + <option> + <name>OGUseCmsisDspLib</name> + <state>0</state> + </option> + <option> + <name>GRuntimeLibThreads</name> + <state>0</state> + </option> + <option> + <name>CoreVariant</name> + <version>31</version> + <state>52</state> + </option> + <option> + <name>GFPUDeviceSlave</name> + <state>Default None</state> + </option> + <option> + <name>FPU2</name> + <version>0</version> + <state>3</state> + </option> + <option> + <name>NrRegs</name> + <version>0</version> + <state>1</state> + </option> + <option> + <name>NEON</name> + <state>0</state> + </option> + <option> + <name>GFPUCoreSlave2</name> + <version>31</version> + <state>42</state> + </option> + <option> + <name>OGCMSISPackSelectDevice</name> + </option> + <option> + <name>OgLibHeap</name> + <state>0</state> + </option> + <option> + <name>OGLibAdditionalLocale</name> + <state>0</state> + </option> + <option> + <name>OGPrintfVariant</name> + <version>0</version> + <state>1</state> + </option> + <option> + <name>OGPrintfMultibyteSupport</name> + <state>0</state> + </option> + <option> + <name>OGScanfVariant</name> + <version>0</version> + <state>1</state> + </option> + <option> + <name>OGScanfMultibyteSupport</name> + <state>0</state> + </option> + <option> + <name>GenLocaleTags</name> + <state></state> + </option> + <option> + <name>GenLocaleDisplayOnly</name> + <state></state> + </option> + <option> + <name>DSPExtension</name> + <state>0</state> + </option> + <option> + <name>TrustZone</name> + <state>0</state> + </option> + <option> + <name>TrustZoneModes</name> + <version>0</version> + <state>0</state> + </option> + <option> + <name>OGAarch64Abi</name> + <state>0</state> + </option> + <option> + <name>OG_32_64Device</name> + <state>0</state> + </option> + <option> + <name>BuildFilesPath</name> + <state>Debug</state> + </option> + </data> + </settings> + <settings> + <name>ICCARM</name> + <archiveVersion>2</archiveVersion> + <data> + <version>37</version> + <wantNonLocal>1</wantNonLocal> + <debug>1</debug> + <option> + <name>CCOptimizationNoSizeConstraints</name> + <state>0</state> + </option> + <option> + <name>CCDefines</name> + <state></state> + </option> + <option> + <name>CCPreprocFile</name> + <state>0</state> + </option> + <option> + <name>CCPreprocComments</name> + <state>0</state> + </option> + <option> + <name>CCPreprocLine</name> + <state>0</state> + </option> + <option> + <name>CCListCFile</name> + <state>1</state> + </option> + <option> + <name>CCListCMnemonics</name> + <state>1</state> + </option> + <option> + <name>CCListCMessages</name> + <state>0</state> + </option> + <option> + <name>CCListAssFile</name> + <state>1</state> + </option> + <option> + <name>CCListAssSource</name> + <state>1</state> + </option> + <option> + <name>CCEnableRemarks</name> + <state>0</state> + </option> + <option> + <name>CCDiagSuppress</name> + <state></state> + </option> + <option> + <name>CCDiagRemark</name> + <state></state> + </option> + <option> + <name>CCDiagWarning</name> + <state></state> + </option> + <option> + <name>CCDiagError</name> + <state></state> + </option> + <option> + <name>CCObjPrefix</name> + <state>1</state> + </option> + <option> + <name>CCAllowList</name> + <version>1</version> + <state>00000000</state> + </option> + <option> + <name>CCDebugInfo</name> + <state>1</state> + </option> + <option> + <name>IEndianMode</name> + <state>1</state> + </option> + <option> + <name>IProcessor</name> + <state>1</state> + </option> + <option> + <name>IExtraOptionsCheck</name> + <state>0</state> + </option> + <option> + <name>IExtraOptions</name> + <state></state> + </option> + <option> + <name>CCLangConformance</name> + <state>0</state> + </option> + <option> + <name>CCSignedPlainChar</name> + <state>1</state> + </option> + <option> + <name>CCRequirePrototypes</name> + <state>0</state> + </option> + <option> + <name>CCDiagWarnAreErr</name> + <state>0</state> + </option> + <option> + <name>CCCompilerRuntimeInfo</name> + <state>0</state> + </option> + <option> + <name>IFpuProcessor</name> + <state>1</state> + </option> + <option> + <name>OutputFile</name> + <state>$FILE_BNAME$.o</state> + </option> + <option> + <name>CCLibConfigHeader</name> + <state>1</state> + </option> + <option> + <name>PreInclude</name> + <state></state> + </option> + <option> + <name>CCIncludePath2</name> + <state>$PROJ_DIR$\..\inc</state> + <state>$PROJ_DIR$\..\..\..\..\common\inc</state> + <state>$PROJ_DIR$\..\..\..\..\common_modules\inc</state> + </option> + <option> + <name>CCStdIncCheck</name> + <state>0</state> + </option> + <option> + <name>CCCodeSection</name> + <state>.text</state> + </option> + <option> + <name>IProcessorMode2</name> + <state>1</state> + </option> + <option> + <name>CCOptLevel</name> + <state>1</state> + </option> + <option> + <name>CCOptStrategy</name> + <version>0</version> + <state>1</state> + </option> + <option> + <name>CCOptLevelSlave</name> + <state>1</state> + </option> + <option> + <name>CCPosIndRopi</name> + <state>1</state> + </option> + <option> + <name>CCPosIndRwpi</name> + <state>1</state> + </option> + <option> + <name>CCPosIndNoDynInit</name> + <state>0</state> + </option> + <option> + <name>IccLang</name> + <state>0</state> + </option> + <option> + <name>IccCDialect</name> + <state>1</state> + </option> + <option> + <name>IccAllowVLA</name> + <state>0</state> + </option> + <option> + <name>IccStaticDestr</name> + <state>1</state> + </option> + <option> + <name>IccCppInlineSemantics</name> + <state>0</state> + </option> + <option> + <name>IccCmsis</name> + <state>1</state> + </option> + <option> + <name>IccFloatSemantics</name> + <state>0</state> + </option> + <option> + <name>CCNoLiteralPool</name> + <state>0</state> + </option> + <option> + <name>CCOptStrategySlave</name> + <version>0</version> + <state>1</state> + </option> + <option> + <name>CCGuardCalls</name> + <state>1</state> + </option> + <option> + <name>CCEncSource</name> + <state>0</state> + </option> + <option> + <name>CCEncOutput</name> + <state>0</state> + </option> + <option> + <name>CCEncOutputBom</name> + <state>1</state> + </option> + <option> + <name>CCEncInput</name> + <state>0</state> + </option> + <option> + <name>IccExceptions2</name> + <state>0</state> + </option> + <option> + <name>IccRTTI2</name> + <state>0</state> + </option> + <option> + <name>OICompilerExtraOption</name> + <state>1</state> + </option> + <option> + <name>CCStackProtection</name> + <state>0</state> + </option> + </data> + </settings> + <settings> + <name>AARM</name> + <archiveVersion>2</archiveVersion> + <data> + <version>11</version> + <wantNonLocal>1</wantNonLocal> + <debug>1</debug> + <option> + <name>AObjPrefix</name> + <state>1</state> + </option> + <option> + <name>AEndian</name> + <state>1</state> + </option> + <option> + <name>ACaseSensitivity</name> + <state>1</state> + </option> + <option> + <name>MacroChars</name> + <version>0</version> + <state>0</state> + </option> + <option> + <name>AWarnEnable</name> + <state>0</state> + </option> + <option> + <name>AWarnWhat</name> + <state>0</state> + </option> + <option> + <name>AWarnOne</name> + <state></state> + </option> + <option> + <name>AWarnRange1</name> + <state></state> + </option> + <option> + <name>AWarnRange2</name> + <state></state> + </option> + <option> + <name>ADebug</name> + <state>1</state> + </option> + <option> + <name>AltRegisterNames</name> + <state>0</state> + </option> + <option> + <name>ADefines</name> + <state></state> + </option> + <option> + <name>AList</name> + <state>0</state> + </option> + <option> + <name>AListHeader</name> + <state>1</state> + </option> + <option> + <name>AListing</name> + <state>1</state> + </option> + <option> + <name>Includes</name> + <state>0</state> + </option> + <option> + <name>MacDefs</name> + <state>0</state> + </option> + <option> + <name>MacExps</name> + <state>1</state> + </option> + <option> + <name>MacExec</name> + <state>0</state> + </option> + <option> + <name>OnlyAssed</name> + <state>0</state> + </option> + <option> + <name>MultiLine</name> + <state>0</state> + </option> + <option> + <name>PageLengthCheck</name> + <state>0</state> + </option> + <option> + <name>PageLength</name> + <state>80</state> + </option> + <option> + <name>TabSpacing</name> + <state>8</state> + </option> + <option> + <name>AXRef</name> + <state>0</state> + </option> + <option> + <name>AXRefDefines</name> + <state>0</state> + </option> + <option> + <name>AXRefInternal</name> + <state>0</state> + </option> + <option> + <name>AXRefDual</name> + <state>0</state> + </option> + <option> + <name>AProcessor</name> + <state>1</state> + </option> + <option> + <name>AFpuProcessor</name> + <state>1</state> + </option> + <option> + <name>AOutputFile</name> + <state>$FILE_BNAME$.o</state> + </option> + <option> + <name>ALimitErrorsCheck</name> + <state>0</state> + </option> + <option> + <name>ALimitErrorsEdit</name> + <state>100</state> + </option> + <option> + <name>AIgnoreStdInclude</name> + <state>0</state> + </option> + <option> + <name>AUserIncludes</name> + <state></state> + </option> + <option> + <name>AExtraOptionsCheckV2</name> + <state>0</state> + </option> + <option> + <name>AExtraOptionsV2</name> + <state></state> + </option> + <option> + <name>AsmNoLiteralPool</name> + <state>0</state> + </option> + <option> + <name>PreInclude</name> + <state></state> + </option> + </data> + </settings> + <settings> + <name>OBJCOPY</name> + <archiveVersion>0</archiveVersion> + <data> + <version>1</version> + <wantNonLocal>1</wantNonLocal> + <debug>1</debug> + <option> + <name>OOCOutputFormat</name> + <version>3</version> + <state>0</state> + </option> + <option> + <name>OCOutputOverride</name> + <state>0</state> + </option> + <option> + <name>OOCOutputFile</name> + <state></state> + </option> + <option> + <name>OOCCommandLineProducer</name> + <state>1</state> + </option> + <option> + <name>OOCObjCopyEnable</name> + <state>0</state> + </option> + </data> + </settings> + <settings> + <name>CUSTOM</name> + <archiveVersion>3</archiveVersion> + <data> + <extensions></extensions> + <cmdline></cmdline> + <hasPrio>0</hasPrio> + <buildSequence>inputOutputBased</buildSequence> + </data> + </settings> + <settings> + <name>BUILDACTION</name> + <archiveVersion>1</archiveVersion> + <data> + <prebuild></prebuild> + <postbuild></postbuild> + </data> + </settings> + <settings> + <name>ILINK</name> + <archiveVersion>0</archiveVersion> + <data> + <version>26</version> + <wantNonLocal>1</wantNonLocal> + <debug>1</debug> + <option> + <name>IlinkLibIOConfig</name> + <state>1</state> + </option> + <option> + <name>IlinkInputFileSlave</name> + <state>0</state> + </option> + <option> + <name>IlinkOutputFile</name> + <state>txm.out</state> + </option> + <option> + <name>IlinkDebugInfoEnable</name> + <state>1</state> + </option> + <option> + <name>IlinkKeepSymbols</name> + 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+ <name>IlinkIcfFile</name> + <state>lnk0t.icf</state> + </option> + <option> + <name>IlinkIcfFileSlave</name> + <state></state> + </option> + <option> + <name>IlinkEnableRemarks</name> + <state>0</state> + </option> + <option> + <name>IlinkSuppressDiags</name> + <state></state> + </option> + <option> + <name>IlinkTreatAsRem</name> + <state></state> + </option> + <option> + <name>IlinkTreatAsWarn</name> + <state></state> + </option> + <option> + <name>IlinkTreatAsErr</name> + <state></state> + </option> + <option> + <name>IlinkWarningsAreErrors</name> + <state>0</state> + </option> + <option> + <name>IlinkUseExtraOptions</name> + <state>0</state> + </option> + <option> + <name>IlinkExtraOptions</name> + <state></state> + </option> + <option> + <name>IlinkLowLevelInterfaceSlave</name> + <state>1</state> + </option> + <option> + <name>IlinkAutoLibEnable</name> + <state>1</state> + </option> + <option> + <name>IlinkAdditionalLibs</name> + <state></state> + </option> + <option> + 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+ <option> + <name>IlinkOptExceptionsForce</name> + <state>0</state> + </option> + <option> + <name>IlinkCmsis</name> + <state>1</state> + </option> + <option> + <name>IlinkOptMergeDuplSections</name> + <state>0</state> + </option> + <option> + <name>IlinkOptUseVfe</name> + <state>1</state> + </option> + <option> + <name>IlinkOptForceVfe</name> + <state>0</state> + </option> + <option> + <name>IlinkStackAnalysisEnable</name> + <state>0</state> + </option> + <option> + <name>IlinkStackControlFile</name> + <state></state> + </option> + <option> + <name>IlinkStackCallGraphFile</name> + <state></state> + </option> + <option> + <name>CrcAlgorithm</name> + <version>1</version> + <state>1</state> + </option> + <option> + <name>CrcUnitSize</name> + <version>0</version> + <state>0</state> + </option> + <option> + <name>IlinkThreadsSlave</name> + <state>1</state> + </option> + <option> + <name>IlinkLogCallGraph</name> + <state>0</state> + </option> + <option> + <name>IlinkIcfFile_AltDefault</name> + <state></state> + </option> + <option> + <name>IlinkEncInput</name> + <state>0</state> + </option> + <option> + <name>IlinkEncOutput</name> + <state>0</state> + </option> + <option> + <name>IlinkEncOutputBom</name> + <state>1</state> + </option> + <option> + <name>IlinkHeapSelect</name> + <state>1</state> + </option> + <option> + <name>IlinkLocaleSelect</name> + <state>1</state> + </option> + <option> + <name>IlinkTrustzoneImportLibraryOut</name> + <state>###Unitialized###</state> + </option> + <option> + <name>OILinkExtraOption</name> + <state>1</state> + </option> + <option> + <name>IlinkRawBinaryFile2</name> + <state></state> + </option> + <option> + <name>IlinkRawBinarySymbol2</name> + <state></state> + </option> + <option> + <name>IlinkRawBinarySegment2</name> + <state></state> + </option> + <option> + <name>IlinkRawBinaryAlign2</name> + <state></state> + </option> + <option> + <name>IlinkLogCrtRoutineSelection</name> + <state>0</state> + </option> + <option> + <name>IlinkLogFragmentInfo</name> + <state>0</state> + </option> + <option> + <name>IlinkLogInlining</name> + <state>0</state> + </option> + <option> + <name>IlinkLogMerging</name> + <state>0</state> + </option> + <option> + <name>IlinkDemangle</name> + <state>0</state> + </option> + <option> + <name>IlinkWrapperFileEnable</name> + <state>0</state> + </option> + <option> + <name>IlinkWrapperFile</name> + <state></state> + </option> + </data> + </settings> + <settings> + <name>IARCHIVE</name> + <archiveVersion>0</archiveVersion> + <data> + <version>0</version> + <wantNonLocal>1</wantNonLocal> + <debug>0</debug> + <option> + <name>IarchiveInputs</name> + <state></state> + </option> + <option> + <name>IarchiveOverride</name> + <state>0</state> + </option> + <option> + <name>IarchiveOutput</name> + <state>###Unitialized###</state> + </option> + </data> + </settings> + <settings> + <name>Coder</name> + <archiveVersion>0</archiveVersion> + <data /> + </settings> + </configuration> + <group> + <name>inc</name> + <file> + <name>$PROJ_DIR$\..\..\..\..\common\inc\tx_api.h</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\common\inc\tx_block_pool.h</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\common\inc\tx_byte_pool.h</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\common\inc\tx_event_flags.h</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\common\inc\tx_initialize.h</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\common\inc\tx_mutex.h</name> + </file> + <file> + <name>$PROJ_DIR$\..\inc\tx_port.h</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\common\inc\tx_queue.h</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\common\inc\tx_semaphore.h</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\common\inc\tx_thread.h</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\common\inc\tx_timer.h</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\common\inc\tx_trace.h</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\common\inc\tx_user_sample.h</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\common_modules\inc\txm_module.h</name> + </file> + <file> + <name>$PROJ_DIR$\..\inc\txm_module_port.h</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\common_modules\inc\txm_module_user.h</name> + </file> + </group> + <group> + <name>src</name> + <file> + <name>$PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_block_allocate.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_block_pool_create.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_block_pool_delete.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_block_pool_info_get.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_block_pool_performance_info_get.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_block_pool_performance_system_info_get.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_block_pool_prioritize.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_block_release.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_byte_allocate.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_byte_pool_create.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_byte_pool_delete.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_byte_pool_info_get.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_byte_pool_performance_info_get.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_byte_pool_performance_system_info_get.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_byte_pool_prioritize.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_byte_release.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_event_flags_create.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_event_flags_delete.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_event_flags_get.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_event_flags_info_get.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_event_flags_performance_info_get.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_event_flags_performance_system_info_get.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_event_flags_set.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_event_flags_set_notify.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_module_application_request.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_module_callback_request_thread_entry.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_module_object_allocate.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_module_object_deallocate.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_module_object_pointer_get.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_module_object_pointer_get_extended.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\module_lib\src\txm_module_thread_shell_entry.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_module_thread_system_suspend.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_mutex_create.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_mutex_delete.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_mutex_get.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_mutex_info_get.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_mutex_performance_info_get.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_mutex_performance_system_info_get.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_mutex_prioritize.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_mutex_put.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_queue_create.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_queue_delete.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_queue_flush.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_queue_front_send.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_queue_info_get.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_queue_performance_info_get.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_queue_performance_system_info_get.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_queue_prioritize.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_queue_receive.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_queue_send.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_queue_send_notify.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_semaphore_ceiling_put.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_semaphore_create.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_semaphore_delete.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_semaphore_get.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_semaphore_info_get.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_semaphore_performance_info_get.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_semaphore_performance_system_info_get.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_semaphore_prioritize.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_semaphore_put.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_semaphore_put_notify.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_thread_create.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_thread_delete.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_thread_entry_exit_notify.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_thread_identify.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_thread_info_get.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_thread_interrupt_control.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_thread_performance_info_get.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_thread_performance_system_info_get.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_thread_preemption_change.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_thread_priority_change.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_thread_relinquish.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_thread_reset.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_thread_resume.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_thread_sleep.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_thread_stack_error_notify.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_thread_suspend.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_thread_terminate.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_thread_time_slice_change.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_thread_wait_abort.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_time_get.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_time_set.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_timer_activate.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_timer_change.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_timer_create.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_timer_deactivate.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_timer_delete.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_timer_info_get.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_timer_performance_info_get.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_timer_performance_system_info_get.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_trace_buffer_full_notify.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_trace_disable.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_trace_enable.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_trace_event_filter.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_trace_event_unfilter.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_trace_interrupt_control.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_trace_isr_enter_insert.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_trace_isr_exit_insert.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_trace_user_event_insert.c</name> + </file> + </group> +</project> diff --git a/ports_module/cortex_a7/iar/example_build/txm_module_preamble.s b/ports_module/cortex_a7/iar/example_build/txm_module_preamble.s new file mode 100644 index 00000000..31ccca5b --- /dev/null +++ b/ports_module/cortex_a7/iar/example_build/txm_module_preamble.s @@ -0,0 +1,67 @@ + SECTION .text:CODE + + AAPCS INTERWORK, ROPI, RWPI_COMPATIBLE, VFP_COMPATIBLE + PRESERVE8 + + /* Define public symbols. */ + + PUBLIC __txm_module_preamble + + + /* Define application-specific start/stop entry points for the module. */ + + EXTERN demo_module_start + + + /* Define common external refrences. */ + + EXTERN _txm_module_thread_shell_entry + EXTERN _txm_module_callback_request_thread_entry + EXTERN ROPI$$Length + EXTERN RWPI$$Length + + DATA +__txm_module_preamble: + DC32 0x4D4F4455 ; Module ID + DC32 0x6 ; Module Major Version + DC32 0x1 ; Module Minor Version + DC32 32 ; Module Preamble Size in 32-bit words + DC32 0x12345678 ; Module ID (application defined) + DC32 0x00000001 ; Module Properties where: + ; Bits 31-24: Compiler ID + ; 0 -> IAR + ; 1 -> RVDS + ; 2 -> GNU + ; Bits 23-1: Reserved + ; Bit 0: 0 -> Privileged mode execution (no MPU protection) + ; 1 -> User mode execution (MPU protection) + DC32 _txm_module_thread_shell_entry - . - 0 ; Module Shell Entry Point + DC32 demo_module_start - . - 0 ; Module Start Thread Entry Point + DC32 0 ; Module Stop Thread Entry Point + DC32 1 ; Module Start/Stop Thread Priority + DC32 1022 ; Module Start/Stop Thread Stack Size + DC32 _txm_module_callback_request_thread_entry - . - 0 ; Module Callback Thread Entry + DC32 1 ; Module Callback Thread Priority + DC32 1022 ; Module Callback Thread Stack Size + DC32 ROPI$$Length ; Module Code Size + DC32 RWPI$$Length ; Module Data Size + DC32 0 ; Reserved 0 + DC32 0 ; Reserved 1 + DC32 0 ; Reserved 2 + DC32 0 ; Reserved 3 + DC32 0 ; Reserved 4 + DC32 0 ; Reserved 5 + DC32 0 ; Reserved 6 + DC32 0 ; Reserved 7 + DC32 0 ; Reserved 8 + DC32 0 ; Reserved 9 + DC32 0 ; Reserved 10 + DC32 0 ; Reserved 11 + DC32 0 ; Reserved 12 + DC32 0 ; Reserved 13 + DC32 0 ; Reserved 14 + DC32 0 ; Reserved 15 + + END + + diff --git a/ports_module/cortex_a7/iar/inc/tx_port.h b/ports_module/cortex_a7/iar/inc/tx_port.h new file mode 100644 index 00000000..3780666b --- /dev/null +++ b/ports_module/cortex_a7/iar/inc/tx_port.h @@ -0,0 +1,424 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Port Specific */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* PORT SPECIFIC C INFORMATION RELEASE */ +/* */ +/* tx_port.h Cortex-A7/IAR */ +/* 6.1.6 */ +/* */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file contains data type definitions that make the ThreadX */ +/* real-time kernel function identically on a variety of different */ +/* processor architectures. For example, the size or number of bits */ +/* in an "int" data type vary between microprocessor architectures and */ +/* even C compilers for the same microprocessor. ThreadX does not */ +/* directly use native C data types. Instead, ThreadX creates its */ +/* own special types that can be mapped to actual data types by this */ +/* file to guarantee consistency in the interface and functionality. */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ +/* macro definition, */ +/* resulting in version 6.1.6 */ +/* */ +/**************************************************************************/ + +#ifndef TX_PORT_H +#define TX_PORT_H + + +/* Determine if the optional ThreadX user define file should be used. */ + +#ifdef TX_INCLUDE_USER_DEFINE_FILE + + +/* Yes, include the user defines in tx_user.h. The defines in this file may + alternately be defined on the command line. */ + +#include "tx_user.h" +#endif + + +/* Define compiler library include files. */ + +#include <stdlib.h> +#include <string.h> +#include <intrinsics.h> +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT +#include <yvals.h> +#endif + + +/* Define ThreadX basic types for this port. */ + +#define VOID void +typedef char CHAR; +typedef unsigned char UCHAR; +typedef int INT; +typedef unsigned int UINT; +typedef long LONG; +typedef unsigned long ULONG; +typedef short SHORT; +typedef unsigned short USHORT; + + +/* Define the priority levels for ThreadX. Legal values range + from 32 to 1024 and MUST be evenly divisible by 32. */ + +#ifndef TX_MAX_PRIORITIES +#define TX_MAX_PRIORITIES 32 +#endif + + +/* Define the minimum stack for a ThreadX thread on this processor. If the size supplied during + thread creation is less than this value, the thread create call will return an error. */ + +#ifndef TX_MINIMUM_STACK +#define TX_MINIMUM_STACK 200 /* Minimum stack size for this port */ +#endif + + +/* Define the system timer thread's default stack size and priority. These are only applicable + if TX_TIMER_PROCESS_IN_ISR is not defined. */ + +#ifndef TX_TIMER_THREAD_STACK_SIZE +#define TX_TIMER_THREAD_STACK_SIZE 1024 /* Default timer thread stack size */ +#endif + +#ifndef TX_TIMER_THREAD_PRIORITY +#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ +#endif + + +/* Define various constants for the ThreadX ARM port. */ + +#ifdef TX_ENABLE_FIQ_SUPPORT +#define TX_INT_DISABLE 0xC0 /* Disable IRQ & FIQ interrupts */ +#else +#define TX_INT_DISABLE 0x80 /* Disable IRQ interrupts */ +#endif +#define TX_INT_ENABLE 0x00 /* Enable IRQ interrupts */ + + +/* Define the clock source for trace event entry time stamp. The following two item are port specific. + For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock + source constants would be: + +#define TX_TRACE_TIME_SOURCE *((ULONG *) 0x0a800024) +#define TX_TRACE_TIME_MASK 0x0000FFFFUL + +*/ + +#ifndef TX_MISRA_ENABLE +#ifndef TX_TRACE_TIME_SOURCE +#define TX_TRACE_TIME_SOURCE ++_tx_trace_simulated_time +#endif +#else +ULONG _tx_misra_time_stamp_get(VOID); +#define TX_TRACE_TIME_SOURCE _tx_misra_time_stamp_get() +#endif + +#ifndef TX_TRACE_TIME_MASK +#define TX_TRACE_TIME_MASK 0xFFFFFFFFUL +#endif + + +/* Define the port specific options for the _tx_build_options variable. This variable indicates + how the ThreadX library was built. */ + +#ifdef TX_ENABLE_FIQ_SUPPORT +#define TX_FIQ_ENABLED 1 +#else +#define TX_FIQ_ENABLED 0 +#endif + +#ifdef TX_ENABLE_IRQ_NESTING +#define TX_IRQ_NESTING_ENABLED 2 +#else +#define TX_IRQ_NESTING_ENABLED 0 +#endif + +#ifdef TX_ENABLE_FIQ_NESTING +#define TX_FIQ_NESTING_ENABLED 4 +#else +#define TX_FIQ_NESTING_ENABLED 0 +#endif + +#define TX_PORT_SPECIFIC_BUILD_OPTIONS TX_FIQ_ENABLED | TX_IRQ_NESTING_ENABLED | TX_FIQ_NESTING_ENABLED + + +/* Define the in-line initialization constant so that modules with in-line + initialization capabilities can prevent their initialization from being + a function call. */ + +#ifdef TX_MISRA_ENABLE +#define TX_DISABLE_INLINE +#else +#define TX_INLINE_INITIALIZATION +#endif + +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is + disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack + checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING + define is negated, thereby forcing the stack fill which is necessary for the stack checking + logic. */ + +#ifndef TX_MISRA_ENABLE +#ifdef TX_ENABLE_STACK_CHECKING +#undef TX_DISABLE_STACK_FILLING +#endif +#endif + + +/* Define the TX_THREAD control block extensions for this port. The main reason + for the multiple macros is so that backward compatibility can be maintained with + existing ThreadX kernel awareness modules. */ + +#define TX_THREAD_EXTENSION_0 +#define TX_THREAD_EXTENSION_1 +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT +#define TX_THREAD_EXTENSION_2 ULONG tx_thread_vfp_enable; \ + VOID *tx_thread_module_instance_ptr; \ + VOID *tx_thread_module_entry_info_ptr; \ + ULONG tx_thread_module_current_user_mode; \ + ULONG tx_thread_module_user_mode; \ + VOID *tx_thread_module_kernel_stack_start; \ + VOID *tx_thread_module_kernel_stack_end; \ + ULONG tx_thread_module_kernel_stack_size; \ + VOID *tx_thread_module_stack_ptr; \ + VOID *tx_thread_module_stack_start; \ + VOID *tx_thread_module_stack_end; \ + ULONG tx_thread_module_stack_size; \ + VOID *tx_thread_module_reserved; \ + VOID *tx_thread_iar_tls_pointer; +#else +#define TX_THREAD_EXTENSION_2 ULONG tx_thread_vfp_enable; \ + VOID *tx_thread_module_instance_ptr; \ + VOID *tx_thread_module_entry_info_ptr; \ + ULONG tx_thread_module_current_user_mode; \ + ULONG tx_thread_module_user_mode; \ + VOID *tx_thread_module_kernel_stack_start; \ + VOID *tx_thread_module_kernel_stack_end; \ + ULONG tx_thread_module_kernel_stack_size; \ + VOID *tx_thread_module_stack_ptr; \ + VOID *tx_thread_module_stack_start; \ + VOID *tx_thread_module_stack_end; \ + ULONG tx_thread_module_stack_size; \ + VOID *tx_thread_module_reserved; +#endif +#define TX_THREAD_EXTENSION_3 + + +/* Define the port extensions of the remaining ThreadX objects. */ + +#define TX_BLOCK_POOL_EXTENSION +#define TX_BYTE_POOL_EXTENSION +#define TX_EVENT_FLAGS_GROUP_EXTENSION VOID *tx_event_flags_group_module_instance; \ + VOID (*tx_event_flags_group_set_module_notify)(struct TX_EVENT_FLAGS_GROUP_STRUCT *group_ptr); +#define TX_MUTEX_EXTENSION +#define TX_QUEUE_EXTENSION VOID *tx_queue_module_instance; \ + VOID (*tx_queue_send_module_notify)(struct TX_QUEUE_STRUCT *queue_ptr); + +#define TX_SEMAPHORE_EXTENSION VOID *tx_semaphore_module_instance; \ + VOID (*tx_semaphore_put_module_notify)(struct TX_SEMAPHORE_STRUCT *semaphore_ptr); + +#define TX_TIMER_EXTENSION VOID *tx_timer_module_instance; \ + VOID (*tx_timer_module_expiration_function)(ULONG id); + + +/* Define the user extension field of the thread control block. Nothing + additional is needed for this port so it is defined as white space. */ + +#ifndef TX_THREAD_USER_EXTENSION +#define TX_THREAD_USER_EXTENSION +#endif + + +/* Define the macros for processing extensions in tx_thread_create, tx_thread_delete, + tx_thread_shell_entry, and tx_thread_terminate. */ + + +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT +#if (__VER__ < 8000000) +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) __iar_dlib_perthread_deallocate(thread_ptr -> tx_thread_iar_tls_pointer); \ + thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; +#define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION __iar_dlib_perthread_access(0); +#else +void *_tx_iar_create_per_thread_tls_area(void); +void _tx_iar_destroy_per_thread_tls_area(void *tls_ptr); +void __iar_Initlocks(void); + +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = _tx_iar_create_per_thread_tls_area(); +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) do {_tx_iar_destroy_per_thread_tls_area(thread_ptr -> tx_thread_iar_tls_pointer); \ + thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; } while(0); +#define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION do {__iar_Initlocks();} while(0); +#endif +#else +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#endif +#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) +#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) + + +/* Define the ThreadX object creation extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_CREATE_EXTENSION(group_ptr) +#define TX_MUTEX_CREATE_EXTENSION(mutex_ptr) +#define TX_QUEUE_CREATE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_CREATE_EXTENSION(semaphore_ptr) +#define TX_TIMER_CREATE_EXTENSION(timer_ptr) + + +/* Define the ThreadX object deletion extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_DELETE_EXTENSION(group_ptr) +#define TX_MUTEX_DELETE_EXTENSION(mutex_ptr) +#define TX_QUEUE_DELETE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_DELETE_EXTENSION(semaphore_ptr) +#define TX_TIMER_DELETE_EXTENSION(timer_ptr) + + +/* Determine if the ARM architecture has the CLZ instruction. This is available on + architectures v5 and above. If available, redefine the macro for calculating the + lowest bit set. */ + +#ifndef TX_DISABLE_INLINE + +#if __CORE__ > __ARM4TM__ + +#if __CPU_MODE__ == 2 + +#define TX_LOWEST_SET_BIT_CALCULATE(m, b) m = m & ((ULONG) (-((LONG) m))); \ + b = (UINT) __CLZ(m); \ + b = 31 - b; +#endif +#endif +#endif + + +/* Define ThreadX interrupt lockout and restore macros for protection on + access of critical kernel information. The restore interrupt macro must + restore the interrupt posture of the running thread prior to the value + present prior to the disable macro. In most cases, the save area macro + is used to define a local function save area for the disable and restore + macros. */ + + +/* First, check and see what mode the file is being compiled in. The IAR compiler + defines __CPU_MODE__ to 1, if the Thumb mode is present, and 2 if ARM 32-bit mode + is present. If ARM 32-bit mode is present, the fast CPSR manipulation macros + are available. Otherwise, if Thumb mode is present, we must use function calls. */ + +#ifdef TX_DISABLE_INLINE + +UINT _tx_thread_interrupt_disable(void); +void _tx_thread_interrupt_restore(UINT old_posture); + + +#define TX_INTERRUPT_SAVE_AREA UINT interrupt_save; + +#define TX_DISABLE interrupt_save = _tx_thread_interrupt_disable(); +#define TX_RESTORE _tx_thread_interrupt_restore(interrupt_save); + +#else +#if __CPU_MODE__ == 2 + +#if (__VER__ < 8002000) +__intrinsic unsigned long __get_CPSR(); +__intrinsic void __set_CPSR( unsigned long ); +#endif + + +#if (__VER__ < 8002000) +#define TX_INTERRUPT_SAVE_AREA ULONG interrupt_save; +#else +#define TX_INTERRUPT_SAVE_AREA UINT interrupt_save; +#endif + +#define TX_DISABLE interrupt_save = __get_CPSR(); \ + __set_CPSR(interrupt_save | TX_INT_DISABLE); +#define TX_RESTORE __set_CPSR(interrupt_save); + + +#else + +UINT _tx_thread_interrupt_disable(void); +void _tx_thread_interrupt_restore(UINT old_posture); + + +#define TX_INTERRUPT_SAVE_AREA UINT interrupt_save; + +#define TX_DISABLE interrupt_save = _tx_thread_interrupt_disable(); +#define TX_RESTORE _tx_thread_interrupt_restore(interrupt_save); +#endif +#endif + +/* Define VFP extension for the Cortex-A7. Each is assumed to be called in the context of the executing + thread. */ + +void tx_thread_vfp_enable(void); +void tx_thread_vfp_disable(void); + + +/* Define the interrupt lockout macros for each ThreadX object. */ + +#define TX_BLOCK_POOL_DISABLE TX_DISABLE +#define TX_BYTE_POOL_DISABLE TX_DISABLE +#define TX_EVENT_FLAGS_GROUP_DISABLE TX_DISABLE +#define TX_MUTEX_DISABLE TX_DISABLE +#define TX_QUEUE_DISABLE TX_DISABLE +#define TX_SEMAPHORE_DISABLE TX_DISABLE + + +/* Define the version ID of ThreadX. This may be utilized by the application. */ + +#ifdef TX_THREAD_INIT +CHAR _tx_version_id[] = + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-A7/IAR Version 6.2.1 *"; +#else +#ifdef TX_MISRA_ENABLE +extern CHAR _tx_version_id[100]; +#else +extern CHAR _tx_version_id[]; +#endif +#endif + +#endif + diff --git a/ports_module/cortex_a7/iar/inc/txm_module_port.h b/ports_module/cortex_a7/iar/inc/txm_module_port.h new file mode 100644 index 00000000..1b31c6f7 --- /dev/null +++ b/ports_module/cortex_a7/iar/inc/txm_module_port.h @@ -0,0 +1,424 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Interface (API) */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* APPLICATION INTERFACE DEFINITION RELEASE */ +/* */ +/* txm_module_port.h Cortex-A7/MMU/IAR */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file defines the basic module constants, interface structures, */ +/* and function prototypes. */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ + +#ifndef TXM_MODULE_PORT_H +#define TXM_MODULE_PORT_H + +/* Determine if the optional Modules user define file should be used. */ + +#ifdef TXM_MODULE_INCLUDE_USER_DEFINE_FILE + + +/* Yes, include the user defines in txm_module_user.h. The defines in this file may + alternately be defined on the command line. */ + +#include "txm_module_user.h" +#endif + +/* It is assumed that the base ThreadX tx_port.h file has been modified to add the + following extensions to the ThreadX thread control block (this code should replace + the corresponding macro define in tx_port.h): + +#define TX_THREAD_EXTENSION_2 ULONG tx_thread_vfp_enable; \ + VOID *tx_thread_module_instance_ptr; \ + VOID *tx_thread_module_entry_info_ptr; \ + ULONG tx_thread_module_current_user_mode; \ + ULONG tx_thread_module_user_mode; \ + VOID *tx_thread_module_kernel_stack_start; \ + VOID *tx_thread_module_kernel_stack_end; \ + ULONG tx_thread_module_kernel_stack_size; \ + VOID *tx_thread_module_stack_ptr; \ + VOID *tx_thread_module_stack_start; \ + VOID *tx_thread_module_stack_end; \ + ULONG tx_thread_module_stack_size; \ + VOID *tx_thread_module_reserved; + + +The following extensions must also be defined in tx_port.h: + +#define TX_EVENT_FLAGS_GROUP_EXTENSION VOID *tx_event_flags_group_module_instance; \ + VOID (*tx_event_flags_group_set_module_notify)(struct TX_EVENT_FLAGS_GROUP_STRUCT *group_ptr); + +#define TX_QUEUE_EXTENSION VOID *tx_queue_module_instance; \ + VOID (*tx_queue_send_module_notify)(struct TX_QUEUE_STRUCT *queue_ptr); + +#define TX_SEMAPHORE_EXTENSION VOID *tx_semaphore_module_instance; \ + VOID (*tx_semaphore_put_module_notify)(struct TX_SEMAPHORE_STRUCT *semaphore_ptr); + +#define TX_TIMER_EXTENSION VOID *tx_timer_module_instance; \ + VOID (*tx_timer_module_expiration_function)(ULONG id); +*/ + +/* Define the kernel stack size for a module thread. */ +#ifndef TXM_MODULE_KERNEL_STACK_SIZE +#define TXM_MODULE_KERNEL_STACK_SIZE 512 +#endif + +/* Defined, this option enables the MMU hardware and requires memory protected + module objects to be allocated from the module manager object pool. + If this is undefined, module objects can be created in the module's data area + or in the module manager object pool. If this is not defined (MMU hardware + is disabled), a module requiring memory protection will not run (the load + functions will return a TXM_MODULE_INVALID_PROPERTIES error). + Default setting for this value is defined. */ +#define TXM_MODULE_MEMORY_PROTECTION_ENABLED + +/* Define constants specific to the tools the module can be built with for this particular modules port. */ + +#define TXM_MODULE_IAR_COMPILER 0x00000000 +#define TXM_MODULE_RVDS_COMPILER 0x01000000 +#define TXM_MODULE_GNU_COMPILER 0x02000000 +#define TXM_MODULE_COMPILER_MASK 0xFF000000 +#define TXM_MODULE_OPTIONS_MASK 0x000000FF + + +/* Define the properties for this particular module port. */ +#ifdef TXM_MODULE_MEMORY_PROTECTION_ENABLED +#define TXM_MODULE_MEMORY_PROTECTION 0x00000001 +#else +#define TXM_MODULE_MEMORY_PROTECTION 0x00000000 +#endif + +#define TXM_MODULE_USER_MODE 0x00000001 + +/* Define the supported options for this module. */ + +#define TXM_MODULE_MANAGER_SUPPORTED_OPTIONS (TXM_MODULE_MEMORY_PROTECTION) +#define TXM_MODULE_MANAGER_REQUIRED_OPTIONS 0 + + +/* Define offset adjustments according to the compiler used to build the module. */ + +#define TXM_MODULE_IAR_SHELL_ADJUST 24 +#define TXM_MODULE_IAR_START_ADJUST 28 +#define TXM_MODULE_IAR_STOP_ADJUST 32 +#define TXM_MODULE_IAR_CALLBACK_ADJUST 44 + +#define TXM_MODULE_RVDS_SHELL_ADJUST 0 +#define TXM_MODULE_RVDS_START_ADJUST 0 +#define TXM_MODULE_RVDS_STOP_ADJUST 0 +#define TXM_MODULE_RVDS_CALLBACK_ADJUST 0 + +#define TXM_MODULE_GNU_SHELL_ADJUST 24 +#define TXM_MODULE_GNU_START_ADJUST 28 +#define TXM_MODULE_GNU_STOP_ADJUST 32 +#define TXM_MODULE_GNU_CALLBACK_ADJUST 44 + + +/* Define other module port-specific constants. */ + +/* Define INLINE_DECLARE to whitespace for ARM compiler. */ +#define INLINE_DECLARE + +#define TXM_MAXIMUM_MODULES 16 +#define TXM_MODULE_LEVEL1_PAGE_TABLE_SIZE 32 +#define TXM_ASID_TABLE_LENGTH 256 + +#define TXM_MODULE_CODE_PAGE_TABLE_START_OFFSET (TXM_MAXIMUM_MODULES * 0) +#define TXM_MODULE_CODE_PAGE_TABLE_END_OFFSET (TXM_MAXIMUM_MODULES * 1) +#define TXM_MODULE_DATA_PAGE_TABLE_START_OFFSET (TXM_MAXIMUM_MODULES * 2) +#define TXM_MODULE_DATA_PAGE_TABLE_END_OFFSET (TXM_MAXIMUM_MODULES * 3) + +#define TXM_MASTER_PAGE_TABLE_INDEX 0 + +/* 1 entry per 1MB, so this covers 4G address space */ +#define TXM_MASTER_PAGE_TABLE_ENTRIES 4096 + +/* Smallest MMU page size is 4kB. */ +#define TXM_MODULE_MEMORY_ALIGNMENT 4096 +#define TXM_MMU_LEVEL1_PAGE_SHIFT 20 +#define TXM_MMU_LEVEL2_PAGE_SHIFT 12 +#define TXM_LEVEL_2_PAGE_TABLE_ENTRIES 256 + +/* Level 1 section base address mask. */ +#define TXM_MMU_LEVEL1_MASK 0xFFF00000 + +/* Level 2 section base address mask. */ +#define TXM_MMU_LEVEL2_MASK 0xFFFFF000 + +/* Non-global, outer & inner write-back, write-allocate, user read, no write. */ +#define TXM_MMU_LEVEL1_CODE_ATTRIBUTES 0x000219EE +/* Non-global, outer & inner write-back, write-allocate, user read, write, no-execute. */ +#define TXM_MMU_LEVEL1_DATA_ATTRIBUTES 0x00021DFE + +/* Level 1 "level 2 descriptor base address" mask. */ +#define TXM_MMU_LEVEL1_SECOND_MASK 0xFFFFFC00 + +/* Level 1 "level 2 descriptor" attributes. */ +#define TXM_MMU_LEVEL1_SECOND_ATTRIBUTES 0x0000001E1 + +/* Kernel level 2 attributes: global, outer & inner write-back, write-allocate, user read/write */ +#define TXM_MMU_KERNEL_LEVEL2_CODE_ATTRIBUTES 0x0000006E +#define TXM_MMU_KERNEL_LEVEL2_DATA_ATTRIBUTES 0x0000005E + +/* Module level 2 attributes: non-global, outer & inner write-back, write-allocate, user read, no write. */ +#define TXM_MMU_LEVEL2_CODE_ATTRIBUTES 0x0000086E +#define TXM_MMU_LEVEL2_DATA_ATTRIBUTES 0x0000087F + + +/* Settings the user can use to set up shared memory attributes. */ +#define TXM_MMU_ATTRIBUTE_XN 0x00000001 +#define TXM_MMU_ATTRIBUTE_B 0x00000002 +#define TXM_MMU_ATTRIBUTE_C 0x00000004 +#define TXM_MMU_ATTRIBUTE_AP 0x00000018 +#define TXM_MMU_ATTRIBUTE_TEX 0x000000E0 + +/* Masks for each attribute. */ +#define TXM_MMU_ATTRIBUTE_XN_MASK 0x00000001 +#define TXM_MMU_ATTRIBUTE_B_MASK 0x00000001 +#define TXM_MMU_ATTRIBUTE_C_MASK 0x00000001 +#define TXM_MMU_ATTRIBUTE_AP_MASK 0x00000003 +#define TXM_MMU_ATTRIBUTE_TEX_MASK 0x00000007 + +/* Shift amounts for bitfields above to correct register locations. */ +#define TXM_MMU_LEVEL1_USER_ATTRIBUTE_XN_SHIFT 4 +#define TXM_MMU_LEVEL1_USER_ATTRIBUTE_B_SHIFT 1 +#define TXM_MMU_LEVEL1_USER_ATTRIBUTE_C_SHIFT 1 +#define TXM_MMU_LEVEL1_USER_ATTRIBUTE_AP_SHIFT 7 +#define TXM_MMU_LEVEL1_USER_ATTRIBUTE_TEX_SHIFT 7 +#define TXM_MMU_LEVEL1_USER_ATTRIBUTE_BASE 0x000201E2 + +#define TXM_MMU_LEVEL2_USER_ATTRIBUTE_XN_SHIFT 0 +#define TXM_MMU_LEVEL2_USER_ATTRIBUTE_B_SHIFT 1 +#define TXM_MMU_LEVEL2_USER_ATTRIBUTE_C_SHIFT 1 +#define TXM_MMU_LEVEL2_USER_ATTRIBUTE_AP_SHIFT 1 +#define TXM_MMU_LEVEL2_USER_ATTRIBUTE_TEX_SHIFT 1 +#define TXM_MMU_LEVEL2_USER_ATTRIBUTE_BASE 0x00000802 + +/* Shift amounts from bit 0 position. */ +#define TXM_MMU_LEVEL1_ATTRIBUTE_XN_SHIFT 4 +#define TXM_MMU_LEVEL1_ATTRIBUTE_B_SHIFT 2 +#define TXM_MMU_LEVEL1_ATTRIBUTE_C_SHIFT 3 +#define TXM_MMU_LEVEL1_ATTRIBUTE_AP_SHIFT 10 +#define TXM_MMU_LEVEL1_ATTRIBUTE_TEX_SHIFT 12 + +#define TXM_MMU_LEVEL2_ATTRIBUTE_XN_SHIFT 0 +#define TXM_MMU_LEVEL2_ATTRIBUTE_B_SHIFT 2 +#define TXM_MMU_LEVEL2_ATTRIBUTE_C_SHIFT 3 +#define TXM_MMU_LEVEL2_ATTRIBUTE_AP_SHIFT 4 +#define TXM_MMU_LEVEL2_ATTRIBUTE_TEX_SHIFT 6 + +/* Masks for L1 page attributes. */ +#define TXM_MMU_LEVEL1_ATTRIBUTE_XN_MASK (TXM_MMU_ATTRIBUTE_XN_MASK << TXM_MMU_LEVEL1_ATTRIBUTE_XN_SHIFT) +#define TXM_MMU_LEVEL1_ATTRIBUTE_B_MASK (TXM_MMU_ATTRIBUTE_B_MASK << TXM_MMU_LEVEL1_ATTRIBUTE_B_SHIFT) +#define TXM_MMU_LEVEL1_ATTRIBUTE_C_MASK (TXM_MMU_ATTRIBUTE_C_MASK << TXM_MMU_LEVEL1_ATTRIBUTE_C_SHIFT) +#define TXM_MMU_LEVEL1_ATTRIBUTE_AP_MASK (TXM_MMU_ATTRIBUTE_AP_MASK << TXM_MMU_LEVEL1_ATTRIBUTE_AP_SHIFT) +#define TXM_MMU_LEVEL1_ATTRIBUTE_TEX_MASK (TXM_MMU_ATTRIBUTE_TEX_MASK << TXM_MMU_LEVEL1_ATTRIBUTE_TEX_SHIFT) + +/* Masks for L2 page attributes. */ +#define TXM_MMU_LEVEL2_ATTRIBUTE_XN_MASK (TXM_MMU_ATTRIBUTE_XN_MASK << TXM_MMU_LEVEL2_ATTRIBUTE_XN_SHIFT) +#define TXM_MMU_LEVEL2_ATTRIBUTE_B_MASK (TXM_MMU_ATTRIBUTE_B_MASK << TXM_MMU_LEVEL2_ATTRIBUTE_B_SHIFT) +#define TXM_MMU_LEVEL2_ATTRIBUTE_C_MASK (TXM_MMU_ATTRIBUTE_C_MASK << TXM_MMU_LEVEL2_ATTRIBUTE_C_SHIFT) +#define TXM_MMU_LEVEL2_ATTRIBUTE_AP_MASK (TXM_MMU_ATTRIBUTE_AP_MASK << TXM_MMU_LEVEL2_ATTRIBUTE_AP_SHIFT) +#define TXM_MMU_LEVEL2_ATTRIBUTE_TEX_MASK (TXM_MMU_ATTRIBUTE_TEX_MASK << TXM_MMU_LEVEL2_ATTRIBUTE_TEX_SHIFT) + +#define TXM_ADDRESS_TRANSLATION_FAULT_BIT 1 + +#define TXM_ASID_RESERVED 0xFFFFFFFF + +#define TXM_MODULE_ASID_ERROR 0xF6 +#define TXM_MODULE_EXTERNAL_MEMORY_ENABLE_ERROR 0xF7 + +/* Number of L2 pages each module can have. */ +#define TXM_MODULE_LEVEL2_EXTERNAL_PAGES 16 +/* Size, in pages, of the L2 page pool. */ +#define TXM_LEVEL2_EXTERNAL_POOL_PAGES (TXM_MODULE_LEVEL2_EXTERNAL_PAGES * TXM_MAXIMUM_MODULES) + + +/* Define the port-extensions to the module manager instance structure. */ + +#define TXM_MODULE_MANAGER_PORT_EXTENSION \ + ULONG txm_module_instance_asid; \ + ULONG *txm_external_page_table[TXM_MODULE_LEVEL2_EXTERNAL_PAGES]; + +/* Define the memory fault information structure that is populated when a memory fault occurs. */ + + +typedef struct TXM_MODULE_MANAGER_MEMORY_FAULT_INFO_STRUCT +{ + TX_THREAD *txm_module_manager_memory_fault_info_thread_ptr; + VOID *txm_module_manager_memory_fault_info_code_location; + ULONG txm_module_manager_memory_fault_info_dfar; + ULONG txm_module_manager_memory_fault_info_dfsr; + ULONG txm_module_manager_memory_fault_info_ifar; + ULONG txm_module_manager_memory_fault_info_ifsr; + ULONG txm_module_manager_memory_fault_info_sp; + ULONG txm_module_manager_memory_fault_info_r0; + ULONG txm_module_manager_memory_fault_info_r1; + ULONG txm_module_manager_memory_fault_info_r2; + ULONG txm_module_manager_memory_fault_info_r3; + ULONG txm_module_manager_memory_fault_info_r4; + ULONG txm_module_manager_memory_fault_info_r5; + ULONG txm_module_manager_memory_fault_info_r6; + ULONG txm_module_manager_memory_fault_info_r7; + ULONG txm_module_manager_memory_fault_info_r8; + ULONG txm_module_manager_memory_fault_info_r9; + ULONG txm_module_manager_memory_fault_info_r10; + ULONG txm_module_manager_memory_fault_info_r11; + ULONG txm_module_manager_memory_fault_info_r12; + ULONG txm_module_manager_memory_fault_info_lr; + ULONG txm_module_manager_memory_fault_info_cpsr; +} TXM_MODULE_MANAGER_MEMORY_FAULT_INFO; + + +#define TXM_MODULE_MANAGER_FAULT_INFO \ + TXM_MODULE_MANAGER_MEMORY_FAULT_INFO _txm_module_manager_memory_fault_info; + +/* Define the macro to check the stack available in dispatch. */ +#define TXM_MODULE_MANAGER_CHECK_STACK_AVAILABLE + + +/* Define the macro to check the code alignment. */ + +#define TXM_MODULE_MANAGER_CHECK_CODE_ALIGNMENT(module_location, code_alignment) \ + { \ + ULONG temp; \ + temp = (ULONG) module_location; \ + temp = temp & (TXM_MODULE_MEMORY_ALIGNMENT - 1); \ + if (temp) \ + { \ + _tx_mutex_put(&_txm_module_manager_mutex); \ + return(TXM_MODULE_ALIGNMENT_ERROR); \ + } \ + } + + +/* Define the macro to adjust the alignment and size for code/data areas. */ + +#define TXM_MODULE_MANAGER_ALIGNMENT_ADJUST(module_preamble, code_size, code_alignment, data_size, data_alignment) _txm_module_manager_alignment_adjust(module_preamble, &code_size, &code_alignment, &data_size, &data_alignment); + + +/* Define the macro to adjust the symbols in the module preamble. */ + +#define TXM_MODULE_MANAGER_CALCULATE_ADJUSTMENTS(properties, shell_function_adjust, start_function_adjust, stop_function_adjust, callback_function_adjust) \ + if ((properties & TXM_MODULE_COMPILER_MASK) == TXM_MODULE_IAR_COMPILER) \ + { \ + shell_function_adjust = TXM_MODULE_IAR_SHELL_ADJUST; \ + start_function_adjust = TXM_MODULE_IAR_START_ADJUST; \ + stop_function_adjust = TXM_MODULE_IAR_STOP_ADJUST; \ + callback_function_adjust = TXM_MODULE_IAR_CALLBACK_ADJUST; \ + } \ + else if ((properties & TXM_MODULE_COMPILER_MASK) == TXM_MODULE_RVDS_COMPILER) \ + { \ + shell_function_adjust = TXM_MODULE_RVDS_SHELL_ADJUST; \ + start_function_adjust = TXM_MODULE_RVDS_START_ADJUST; \ + stop_function_adjust = TXM_MODULE_RVDS_STOP_ADJUST; \ + callback_function_adjust = TXM_MODULE_RVDS_CALLBACK_ADJUST; \ + } \ + else \ + { \ + shell_function_adjust = TXM_MODULE_GNU_SHELL_ADJUST; \ + start_function_adjust = TXM_MODULE_GNU_START_ADJUST; \ + stop_function_adjust = TXM_MODULE_GNU_STOP_ADJUST; \ + callback_function_adjust = TXM_MODULE_GNU_CALLBACK_ADJUST; \ + } + + +/* Define the macro to populate the thread control block with module port-specific information. */ + +#define TXM_MODULE_MANAGER_THREAD_SETUP(thread_ptr, module_instance) \ + thread_ptr -> tx_thread_module_current_user_mode = module_instance -> txm_module_instance_property_flags & TXM_MODULE_MEMORY_PROTECTION; \ + thread_ptr -> tx_thread_module_user_mode = module_instance -> txm_module_instance_property_flags & TXM_MODULE_MEMORY_PROTECTION; \ + if (thread_ptr -> tx_thread_module_user_mode) \ + { \ + thread_entry_info -> txm_module_thread_entry_info_kernel_call_dispatcher = _txm_module_manager_user_mode_entry; \ + } \ + else \ + { \ + thread_entry_info -> txm_module_thread_entry_info_kernel_call_dispatcher = _txm_module_manager_kernel_dispatch; \ + } + + +/* Define the macro to populate the module control block with module port-specific information. + If memory protection is enabled, set up the MMU registers. +*/ +#define TXM_MODULE_MANAGER_MODULE_SETUP(module_instance) \ + if (module_instance -> txm_module_instance_property_flags & TXM_MODULE_MEMORY_PROTECTION) \ + { \ + _txm_module_manager_mm_register_setup(module_instance); \ + } \ + else \ + { \ + /* Do nothing. */ \ + } + +/* Define the macro to perform port-specific functions when unloading the module. */ +#define TXM_MODULE_MANAGER_MODULE_UNLOAD(module_instance) \ + _txm_level2_page_clear(module_instance); \ + _txm_module_manager_remove_asid(module_instance); + +/* Define the macros to perform port-specific checks when passing pointers to the kernel. */ + +/* Define macro to make sure object is inside the module's data or shared memory. */ +#define TXM_MODULE_MANAGER_CHECK_INSIDE_DATA(module_instance, obj_ptr, obj_size) \ + _txm_module_manager_inside_data_check((ULONG) obj_ptr) + + +/* Define some internal prototypes to this module port. */ + +#ifndef TX_SOURCE_CODE +#define txm_module_manager_memory_fault_notify _txm_module_manager_memory_fault_notify +#define txm_module_manager_mm_initialize _txm_module_manager_mm_initialize +#endif + + +#define TXM_MODULE_MANAGER_ADDITIONAL_PROTOTYPES \ +VOID _txm_module_manager_alignment_adjust(TXM_MODULE_PREAMBLE *module_preamble, ULONG *code_size, ULONG *code_alignment, ULONG *data_size, ULONG *data_alignment); \ +ULONG _txm_module_manager_data_pointer_check(ULONG pointer); \ +VOID _txm_module_manager_memory_fault_handler(VOID); \ +UINT _txm_module_manager_memory_fault_notify(VOID (*notify_function)(TX_THREAD *, TXM_MODULE_INSTANCE *)); \ +UINT _txm_module_manager_mm_initialize(VOID); \ +VOID _txm_module_manager_mm_register_setup(TXM_MODULE_INSTANCE *module_instance); \ +VOID _txm_level2_page_clear(TXM_MODULE_INSTANCE *module_instance); \ +VOID _txm_module_manager_remove_asid(TXM_MODULE_INSTANCE *module_instance); \ +UINT _txm_module_manager_inside_data_check(ULONG pointer); + +#define TXM_MODULE_MANAGER_VERSION_ID \ +CHAR _txm_module_manager_version_id[] = \ + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-A7/MMU/iar Version 6.2.1 *"; + +#endif + diff --git a/ports_module/cortex_a7/iar/module_lib/src/txm_module_thread_shell_entry.c b/ports_module/cortex_a7/iar/module_lib/src/txm_module_thread_shell_entry.c new file mode 100644 index 00000000..d28c17b7 --- /dev/null +++ b/ports_module/cortex_a7/iar/module_lib/src/txm_module_thread_shell_entry.c @@ -0,0 +1,176 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#ifndef TXM_MODULE +#define TXM_MODULE +#endif + +#ifndef TX_SOURCE_CODE +#define TX_SOURCE_CODE +#endif + + +/* Include necessary system files. */ + +#include "txm_module.h" +#include "tx_thread.h" + + +/* Define the global module entry pointer from the start thread of the module. */ + +TXM_MODULE_THREAD_ENTRY_INFO *_txm_module_entry_info; + + +/* Define the dispatch function pointer used in the module implementation. */ + +ULONG (*_txm_module_kernel_call_dispatcher)(ULONG kernel_request, ULONG param_1, ULONG param_2, ULONG param3); + + + +/* Define the IAR startup code that clears the uninitialized global data and sets up the + preset global variables. */ + +extern VOID __iar_data_init3(VOID); + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_thread_shell_entry Cortex-A7/MMU/IAR */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function calls the specified entry function of the thread. It */ +/* also provides a place for the thread's entry function to return. */ +/* If the thread returns, this function places the thread in a */ +/* "COMPLETED" state. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Pointer to current thread */ +/* thread_info Pointer to thread entry info */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* __iar_data_init3 IAR global initialization function*/ +/* thread_entry Thread's entry function */ +/* tx_thread_resume Resume the module callback thread */ +/* _txm_module_thread_system_suspend Module thread suspension routine */ +/* */ +/* CALLED BY */ +/* */ +/* Initial thread stack frame */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_ENTRY_INFO *thread_info) +{ + +#ifndef TX_DISABLE_NOTIFY_CALLBACKS + VOID (*entry_exit_notify)(TX_THREAD *, UINT); +#endif + + + /* Determine if this is the start thread. If so, we must prepare the module for + execution. If not, simply skip the C startup code. */ + if (thread_info -> txm_module_thread_entry_info_start_thread) + { + /* Initialize the IAR C environment. */ + __iar_data_init3(); + + /* Save the entry info pointer, for later use. */ + _txm_module_entry_info = thread_info; + + /* Save the kernel function dispatch address. This is used to make all resident calls from + the module. */ + _txm_module_kernel_call_dispatcher = thread_info -> txm_module_thread_entry_info_kernel_call_dispatcher; + + /* Ensure that we have a valid pointer. */ + while (!_txm_module_kernel_call_dispatcher) + { + /* Loop here, if an error is present getting the dispatch function pointer! + An error here typically indicates the resident portion of _tx_thread_schedule + is not supporting the trap to obtain the function pointer. */ + } + + /* Resume the module's callback thread, already created in the manager. */ + _txe_thread_resume(thread_info -> txm_module_thread_entry_info_callback_request_thread); + } + +#ifndef TX_DISABLE_NOTIFY_CALLBACKS + + /* Pickup the entry/exit application callback routine. */ + entry_exit_notify = thread_info -> txm_module_thread_entry_info_exit_notify; + + /* Determine if an application callback routine is specified. */ + if (entry_exit_notify != TX_NULL) + { + + /* Yes, notify application that this thread has been entered! */ + (entry_exit_notify)(thread_ptr, TX_THREAD_ENTRY); + } +#endif + + /* Call current thread's entry function. */ + (thread_info -> txm_module_thread_entry_info_entry) (thread_info -> txm_module_thread_entry_info_parameter); + + /* Suspend thread with a "completed" state. */ + + +#ifndef TX_DISABLE_NOTIFY_CALLBACKS + + /* Pickup the entry/exit application callback routine again. */ + entry_exit_notify = thread_info -> txm_module_thread_entry_info_exit_notify; + + /* Determine if an application callback routine is specified. */ + if (entry_exit_notify != TX_NULL) + { + + /* Yes, notify application that this thread has exited! */ + (entry_exit_notify)(thread_ptr, TX_THREAD_EXIT); + } +#endif + + /* Call actual thread suspension routine. */ + _txm_module_thread_system_suspend(thread_ptr); + +#ifdef TX_SAFETY_CRITICAL + + /* If we ever get here, raise safety critical exception. */ + TX_SAFETY_CRITICAL_EXCEPTION(__FILE__, __LINE__, 0); +#endif +} + diff --git a/ports_module/cortex_a7/iar/module_manager/src/tx_iar.c b/ports_module/cortex_a7/iar/module_manager/src/tx_iar.c new file mode 100644 index 00000000..11fcefb3 --- /dev/null +++ b/ports_module/cortex_a7/iar/module_manager/src/tx_iar.c @@ -0,0 +1,804 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** IAR Multithreaded Library Support */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Define IAR library for tools prior to version 8. */ + +#if (__VER__ < 8000000) + + +/* IAR version 7 and below. */ + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_initialize.h" +#include "tx_thread.h" +#include "tx_mutex.h" + + +/* This implementation requires that the following macros are defined in the + tx_port.h file and <yvals.h> is included with the following code segments: + +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT +#include <yvals.h> +#endif + +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT +#define TX_THREAD_EXTENSION_2 VOID *tx_thread_iar_tls_pointer; +#else +#define TX_THREAD_EXTENSION_2 +#endif + +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) __iar_dlib_perthread_deallocate(thread_ptr -> tx_thread_iar_tls_pointer); \ + thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; +#define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION __iar_dlib_perthread_access(0); +#else +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#endif + + This should be done automatically if TX_ENABLE_IAR_LIBRARY_SUPPORT is defined while building the ThreadX library and the + application. + + Finally, the project options General Options -> Library Configuration should have the "Enable thread support in library" box selected. +*/ + +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT + +#include <yvals.h> + + +#if _MULTI_THREAD + +TX_MUTEX __tx_iar_system_lock_mutexes[_MAX_LOCK]; +UINT __tx_iar_system_lock_next_free_mutex = 0; + + +/* Define error counters, just for debug purposes. */ + +UINT __tx_iar_system_lock_no_mutexes; +UINT __tx_iar_system_lock_internal_errors; +UINT __tx_iar_system_lock_isr_caller; + + +/* Define the TLS access function for the IAR library. */ + +void _DLIB_TLS_MEMORY *__iar_dlib_perthread_access(void _DLIB_TLS_MEMORY *symbp) +{ + +char _DLIB_TLS_MEMORY *p = 0; + + /* Is there a current thread? */ + if (_tx_thread_current_ptr) + p = (char _DLIB_TLS_MEMORY *) _tx_thread_current_ptr -> tx_thread_iar_tls_pointer; + else + p = (void _DLIB_TLS_MEMORY *) __segment_begin("__DLIB_PERTHREAD"); + p += __IAR_DLIB_PERTHREAD_SYMBOL_OFFSET(symbp); + return (void _DLIB_TLS_MEMORY *) p; +} + + +/* Define mutexes for IAR library. */ + +void __iar_system_Mtxinit(__iar_Rmtx *m) +{ + +UINT i; +UINT status; +TX_MUTEX *mutex_ptr; + + + /* First, find a free mutex in the list. */ + for (i = 0; i < _MAX_LOCK; i++) + { + + /* Setup a pointer to the start of the next free mutex. */ + mutex_ptr = &__tx_iar_system_lock_mutexes[__tx_iar_system_lock_next_free_mutex++]; + + /* Check for wrap-around on the next free mutex. */ + if (__tx_iar_system_lock_next_free_mutex >= _MAX_LOCK) + { + + /* Yes, set the free index back to 0. */ + __tx_iar_system_lock_next_free_mutex = 0; + } + + /* Is this mutex free? */ + if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) + { + + /* Yes, this mutex is free, get out of the loop! */ + break; + } + } + + /* Determine if a free mutex was found. */ + if (i >= _MAX_LOCK) + { + + /* Error! No more free mutexes! */ + + /* Increment the no mutexes error counter. */ + __tx_iar_system_lock_no_mutexes++; + + /* Set return pointer to NULL. */ + *m = TX_NULL; + + /* Return. */ + return; + } + + /* Now create the ThreadX mutex for the IAR library. */ + status = _tx_mutex_create(mutex_ptr, "IAR System Library Lock", TX_NO_INHERIT); + + /* Determine if the creation was successful. */ + if (status == TX_SUCCESS) + { + + /* Yes, successful creation, return mutex pointer. */ + *m = (VOID *) mutex_ptr; + } + else + { + + /* Increment the internal error counter. */ + __tx_iar_system_lock_internal_errors++; + + /* Return a NULL pointer to indicate an error. */ + *m = TX_NULL; + } +} + +void __iar_system_Mtxdst(__iar_Rmtx *m) +{ + + /* Simply delete the mutex. */ + _tx_mutex_delete((TX_MUTEX *) *m); +} + +void __iar_system_Mtxlock(__iar_Rmtx *m) +{ + +UINT status; + + + /* Determine the caller's context. Mutex locks are only available from initialization and + threads. */ + if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) + { + + /* Get the mutex. */ + status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); + + /* Check the status of the mutex release. */ + if (status) + { + + /* Internal error, increment the counter. */ + __tx_iar_system_lock_internal_errors++; + } + } + else + { + + /* Increment the ISR caller error. */ + __tx_iar_system_lock_isr_caller++; + } +} + +void __iar_system_Mtxunlock(__iar_Rmtx *m) +{ + +UINT status; + + + /* Determine the caller's context. Mutex unlocks are only available from initialization and + threads. */ + if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) + { + + /* Release the mutex. */ + status = _tx_mutex_put((TX_MUTEX *) *m); + + /* Check the status of the mutex release. */ + if (status) + { + + /* Internal error, increment the counter. */ + __tx_iar_system_lock_internal_errors++; + } + } + else + { + + /* Increment the ISR caller error. */ + __tx_iar_system_lock_isr_caller++; + } +} + + +#if _DLIB_FILE_DESCRIPTOR + +TX_MUTEX __tx_iar_file_lock_mutexes[_MAX_FLOCK]; +UINT __tx_iar_file_lock_next_free_mutex = 0; + + +/* Define error counters, just for debug purposes. */ + +UINT __tx_iar_file_lock_no_mutexes; +UINT __tx_iar_file_lock_internal_errors; +UINT __tx_iar_file_lock_isr_caller; + + +void __iar_file_Mtxinit(__iar_Rmtx *m) +{ + +UINT i; +UINT status; +TX_MUTEX *mutex_ptr; + + + /* First, find a free mutex in the list. */ + for (i = 0; i < _MAX_FLOCK; i++) + { + + /* Setup a pointer to the start of the next free mutex. */ + mutex_ptr = &__tx_iar_file_lock_mutexes[__tx_iar_file_lock_next_free_mutex++]; + + /* Check for wrap-around on the next free mutex. */ + if (__tx_iar_file_lock_next_free_mutex >= _MAX_LOCK) + { + + /* Yes, set the free index back to 0. */ + __tx_iar_file_lock_next_free_mutex = 0; + } + + /* Is this mutex free? */ + if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) + { + + /* Yes, this mutex is free, get out of the loop! */ + break; + } + } + + /* Determine if a free mutex was found. */ + if (i >= _MAX_LOCK) + { + + /* Error! No more free mutexes! */ + + /* Increment the no mutexes error counter. */ + __tx_iar_file_lock_no_mutexes++; + + /* Set return pointer to NULL. */ + *m = TX_NULL; + + /* Return. */ + return; + } + + /* Now create the ThreadX mutex for the IAR library. */ + status = _tx_mutex_create(mutex_ptr, "IAR File Library Lock", TX_NO_INHERIT); + + /* Determine if the creation was successful. */ + if (status == TX_SUCCESS) + { + + /* Yes, successful creation, return mutex pointer. */ + *m = (VOID *) mutex_ptr; + } + else + { + + /* Increment the internal error counter. */ + __tx_iar_file_lock_internal_errors++; + + /* Return a NULL pointer to indicate an error. */ + *m = TX_NULL; + } +} + +void __iar_file_Mtxdst(__iar_Rmtx *m) +{ + + /* Simply delete the mutex. */ + _tx_mutex_delete((TX_MUTEX *) *m); +} + +void __iar_file_Mtxlock(__iar_Rmtx *m) +{ + +UINT status; + + + /* Determine the caller's context. Mutex locks are only available from initialization and + threads. */ + if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) + { + + /* Get the mutex. */ + status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); + + /* Check the status of the mutex release. */ + if (status) + { + + /* Internal error, increment the counter. */ + __tx_iar_file_lock_internal_errors++; + } + } + else + { + + /* Increment the ISR caller error. */ + __tx_iar_file_lock_isr_caller++; + } +} + +void __iar_file_Mtxunlock(__iar_Rmtx *m) +{ + +UINT status; + + + /* Determine the caller's context. Mutex unlocks are only available from initialization and + threads. */ + if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) + { + + /* Release the mutex. */ + status = _tx_mutex_put((TX_MUTEX *) *m); + + /* Check the status of the mutex release. */ + if (status) + { + + /* Internal error, increment the counter. */ + __tx_iar_file_lock_internal_errors++; + } + } + else + { + + /* Increment the ISR caller error. */ + __tx_iar_file_lock_isr_caller++; + } +} +#endif /* _DLIB_FILE_DESCRIPTOR */ + +#endif /* _MULTI_THREAD */ + +#endif /* TX_ENABLE_IAR_LIBRARY_SUPPORT */ + +#else /* IAR version 8 and above. */ + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_initialize.h" +#include "tx_thread.h" +#include "tx_mutex.h" + +/* This implementation requires that the following macros are defined in the + tx_port.h file and <yvals.h> is included with the following code segments: + +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT +#include <yvals.h> +#endif + +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT +#define TX_THREAD_EXTENSION_2 VOID *tx_thread_iar_tls_pointer; +#else +#define TX_THREAD_EXTENSION_2 +#endif + +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT +void *_tx_iar_create_per_thread_tls_area(void); +void _tx_iar_destroy_per_thread_tls_area(void *tls_ptr); +void __iar_Initlocks(void); + +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) do {__iar_dlib_perthread_deallocate(thread_ptr -> tx_thread_iar_tls_pointer); \ + thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; } while(0); +#define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION do {__iar_Initlocks();} while(0); +#else +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#endif + + This should be done automatically if TX_ENABLE_IAR_LIBRARY_SUPPORT is defined while building the ThreadX library and the + application. + + Finally, the project options General Options -> Library Configuration should have the "Enable thread support in library" box selected. +*/ + +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT + +#include <DLib_threads.h> + + +void * __aeabi_read_tp(); + +void* _tx_iar_create_per_thread_tls_area(); +void _tx_iar_destroy_per_thread_tls_area(void *tls_ptr); + +#pragma section="__iar_tls$$DATA" + +/* Define the TLS access function for the IAR library. */ +void * __aeabi_read_tp(void) +{ + void *p = 0; + TX_THREAD *thread_ptr = _tx_thread_current_ptr; + if (thread_ptr) + { + p = thread_ptr->tx_thread_iar_tls_pointer; + } + else + { + p = __section_begin("__iar_tls$$DATA"); + } + return p; +} + +/* Define the TLS creation and destruction to use malloc/free. */ + +void* _tx_iar_create_per_thread_tls_area() +{ + UINT tls_size = __iar_tls_size(); + + /* Get memory for TLS. */ + void *p = malloc(tls_size); + + /* Initialize TLS-area and run constructors for objects in TLS */ + __iar_tls_init(p); + return p; +} + +void _tx_iar_destroy_per_thread_tls_area(void *tls_ptr) +{ + /* Destroy objects living in TLS */ + __call_thread_dtors(); + free(tls_ptr); +} + +#ifndef _MAX_LOCK +#define _MAX_LOCK 4 +#endif + +static TX_MUTEX __tx_iar_system_lock_mutexes[_MAX_LOCK]; +static UINT __tx_iar_system_lock_next_free_mutex = 0; + + +/* Define error counters, just for debug purposes. */ + +UINT __tx_iar_system_lock_no_mutexes; +UINT __tx_iar_system_lock_internal_errors; +UINT __tx_iar_system_lock_isr_caller; + + +/* Define mutexes for IAR library. */ + +void __iar_system_Mtxinit(__iar_Rmtx *m) +{ + +UINT i; +UINT status; +TX_MUTEX *mutex_ptr; + + + /* First, find a free mutex in the list. */ + for (i = 0; i < _MAX_LOCK; i++) + { + + /* Setup a pointer to the start of the next free mutex. */ + mutex_ptr = &__tx_iar_system_lock_mutexes[__tx_iar_system_lock_next_free_mutex++]; + + /* Check for wrap-around on the next free mutex. */ + if (__tx_iar_system_lock_next_free_mutex >= _MAX_LOCK) + { + + /* Yes, set the free index back to 0. */ + __tx_iar_system_lock_next_free_mutex = 0; + } + + /* Is this mutex free? */ + if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) + { + + /* Yes, this mutex is free, get out of the loop! */ + break; + } + } + + /* Determine if a free mutex was found. */ + if (i >= _MAX_LOCK) + { + + /* Error! No more free mutexes! */ + + /* Increment the no mutexes error counter. */ + __tx_iar_system_lock_no_mutexes++; + + /* Set return pointer to NULL. */ + *m = TX_NULL; + + /* Return. */ + return; + } + + /* Now create the ThreadX mutex for the IAR library. */ + status = _tx_mutex_create(mutex_ptr, "IAR System Library Lock", TX_NO_INHERIT); + + /* Determine if the creation was successful. */ + if (status == TX_SUCCESS) + { + + /* Yes, successful creation, return mutex pointer. */ + *m = (VOID *) mutex_ptr; + } + else + { + + /* Increment the internal error counter. */ + __tx_iar_system_lock_internal_errors++; + + /* Return a NULL pointer to indicate an error. */ + *m = TX_NULL; + } +} + +void __iar_system_Mtxdst(__iar_Rmtx *m) +{ + + /* Simply delete the mutex. */ + _tx_mutex_delete((TX_MUTEX *) *m); +} + +void __iar_system_Mtxlock(__iar_Rmtx *m) +{ + if (*m) + { + UINT status; + + /* Determine the caller's context. Mutex locks are only available from initialization and + threads. */ + if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) + { + + /* Get the mutex. */ + status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); + + /* Check the status of the mutex release. */ + if (status) + { + + /* Internal error, increment the counter. */ + __tx_iar_system_lock_internal_errors++; + } + } + else + { + + /* Increment the ISR caller error. */ + __tx_iar_system_lock_isr_caller++; + } + } +} + +void __iar_system_Mtxunlock(__iar_Rmtx *m) +{ + if (*m) + { + UINT status; + + /* Determine the caller's context. Mutex unlocks are only available from initialization and + threads. */ + if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) + { + + /* Release the mutex. */ + status = _tx_mutex_put((TX_MUTEX *) *m); + + /* Check the status of the mutex release. */ + if (status) + { + + /* Internal error, increment the counter. */ + __tx_iar_system_lock_internal_errors++; + } + } + else + { + + /* Increment the ISR caller error. */ + __tx_iar_system_lock_isr_caller++; + } + } +} + + +#if _DLIB_FILE_DESCRIPTOR + +#include <stdio.h> /* Added to get access to FOPEN_MAX */ +#ifndef _MAX_FLOCK +#define _MAX_FLOCK FOPEN_MAX /* Define _MAX_FLOCK as the maximum number of open files */ +#endif + + +TX_MUTEX __tx_iar_file_lock_mutexes[_MAX_FLOCK]; +UINT __tx_iar_file_lock_next_free_mutex = 0; + + +/* Define error counters, just for debug purposes. */ + +UINT __tx_iar_file_lock_no_mutexes; +UINT __tx_iar_file_lock_internal_errors; +UINT __tx_iar_file_lock_isr_caller; + + +void __iar_file_Mtxinit(__iar_Rmtx *m) +{ + +UINT i; +UINT status; +TX_MUTEX *mutex_ptr; + + + /* First, find a free mutex in the list. */ + for (i = 0; i < _MAX_FLOCK; i++) + { + + /* Setup a pointer to the start of the next free mutex. */ + mutex_ptr = &__tx_iar_file_lock_mutexes[__tx_iar_file_lock_next_free_mutex++]; + + /* Check for wrap-around on the next free mutex. */ + if (__tx_iar_file_lock_next_free_mutex >= _MAX_LOCK) + { + + /* Yes, set the free index back to 0. */ + __tx_iar_file_lock_next_free_mutex = 0; + } + + /* Is this mutex free? */ + if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) + { + + /* Yes, this mutex is free, get out of the loop! */ + break; + } + } + + /* Determine if a free mutex was found. */ + if (i >= _MAX_LOCK) + { + + /* Error! No more free mutexes! */ + + /* Increment the no mutexes error counter. */ + __tx_iar_file_lock_no_mutexes++; + + /* Set return pointer to NULL. */ + *m = TX_NULL; + + /* Return. */ + return; + } + + /* Now create the ThreadX mutex for the IAR library. */ + status = _tx_mutex_create(mutex_ptr, "IAR File Library Lock", TX_NO_INHERIT); + + /* Determine if the creation was successful. */ + if (status == TX_SUCCESS) + { + + /* Yes, successful creation, return mutex pointer. */ + *m = (VOID *) mutex_ptr; + } + else + { + + /* Increment the internal error counter. */ + __tx_iar_file_lock_internal_errors++; + + /* Return a NULL pointer to indicate an error. */ + *m = TX_NULL; + } +} + +void __iar_file_Mtxdst(__iar_Rmtx *m) +{ + + /* Simply delete the mutex. */ + _tx_mutex_delete((TX_MUTEX *) *m); +} + +void __iar_file_Mtxlock(__iar_Rmtx *m) +{ + +UINT status; + + + /* Determine the caller's context. Mutex locks are only available from initialization and + threads. */ + if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) + { + + /* Get the mutex. */ + status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); + + /* Check the status of the mutex release. */ + if (status) + { + + /* Internal error, increment the counter. */ + __tx_iar_file_lock_internal_errors++; + } + } + else + { + + /* Increment the ISR caller error. */ + __tx_iar_file_lock_isr_caller++; + } +} + +void __iar_file_Mtxunlock(__iar_Rmtx *m) +{ + +UINT status; + + + /* Determine the caller's context. Mutex unlocks are only available from initialization and + threads. */ + if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) + { + + /* Release the mutex. */ + status = _tx_mutex_put((TX_MUTEX *) *m); + + /* Check the status of the mutex release. */ + if (status) + { + + /* Internal error, increment the counter. */ + __tx_iar_file_lock_internal_errors++; + } + } + else + { + + /* Increment the ISR caller error. */ + __tx_iar_file_lock_isr_caller++; + } +} +#endif /* _DLIB_FILE_DESCRIPTOR */ + +#endif /* TX_ENABLE_IAR_LIBRARY_SUPPORT */ + +#endif /* IAR version 8 and above. */ diff --git a/ports_module/cortex_a7/iar/module_manager/src/tx_thread_context_restore.s b/ports_module/cortex_a7/iar/module_manager/src/tx_thread_context_restore.s new file mode 100644 index 00000000..a332a862 --- /dev/null +++ b/ports_module/cortex_a7/iar/module_manager/src/tx_thread_context_restore.s @@ -0,0 +1,252 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; + + +IRQ_MODE EQU 0x12 ; IRQ mode +SVC_MODE EQU 0x13 ; SVC mode +SYS_MODE EQU 0x1F ; SYS mode +THUMB_MASK EQU 0x20 ; Thumb bit mask + +#ifdef TX_ENABLE_FIQ_SUPPORT +DISABLE_INTS EQU 0xC0 ; Disable IRQ & FIQ interrupts +#else +DISABLE_INTS EQU 0x80 ; Disable IRQ interrupts +#endif +; +; + EXTERN _tx_thread_system_state + EXTERN _tx_thread_current_ptr + EXTERN _tx_thread_execute_ptr + EXTERN _tx_timer_time_slice + EXTERN _tx_thread_schedule + EXTERN _tx_thread_preempt_disable +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + EXTERN _tx_execution_isr_exit +#endif +; +; + +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_context_restore Cortex-A7/MMU/IAR */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* Scott Larson, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function restores the interrupt context if it is processing a */ +;/* nested interrupt. If not, it returns to the interrupt thread if no */ +;/* preemption is necessary. Otherwise, if preemption is necessary or */ +;/* if no thread was running, the function returns to the scheduler. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_schedule Thread scheduling routine */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs Interrupt Service Routines */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 Scott Larson Initial Version 6.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_context_restore(VOID) +;{ + RSEG .text:CODE:NOROOT(2) + PUBLIC _tx_thread_context_restore + ARM +_tx_thread_context_restore +; +; /* Lockout interrupts. */ +; +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if ; Disable IRQ and FIQ interrupts +#else + CPSID i ; Disable IRQ interrupts +#endif + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR exit function to indicate an ISR is complete. */ +; + BL _tx_execution_isr_exit ; Call the ISR exit function +#endif +; +; /* Determine if interrupts are nested. */ +; if (--_tx_thread_system_state) +; { +; + LDR r3, =_tx_thread_system_state ; Pickup address of system state var + LDR r2, [r3, #0] ; Pickup system state + SUB r2, r2, #1 ; Decrement the counter + STR r2, [r3, #0] ; Store the counter + CMP r2, #0 ; Was this the first interrupt? + BEQ __tx_thread_not_nested_restore ; If so, not a nested restore +; +; /* Interrupts are nested. */ +; +; /* Just recover the saved registers and return to the point of +; interrupt. */ +; + LDMIA sp!, {r0, r10, r12, lr} ; Recover SPSR, POI, and scratch regs + MSR SPSR_cxsf, r0 ; Put SPSR back + LDMIA sp!, {r0-r3} ; Recover r0-r3 + MOVS pc, lr ; Return to point of interrupt +; +; } +__tx_thread_not_nested_restore +; +; /* Determine if a thread was interrupted and no preemption is required. */ +; else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr)) +; || (_tx_thread_preempt_disable)) +; { +; + LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr + LDR r0, [r1, #0] ; Pickup actual current thread pointer + CMP r0, #0 ; Is it NULL? + BEQ __tx_thread_idle_system_restore ; Yes, idle system was interrupted +; + LDR r3, =_tx_thread_preempt_disable ; Pickup preempt disable address + LDR r2, [r3, #0] ; Pickup actual preempt disable flag + CMP r2, #0 ; Is it set? + BNE __tx_thread_no_preempt_restore ; Yes, don't preempt this thread + LDR r3, =_tx_thread_execute_ptr ; Pickup address of execute thread ptr + LDR r2, [r3, #0] ; Pickup actual execute thread pointer + CMP r0, r2 ; Is the same thread highest priority? + BNE __tx_thread_preempt_restore ; No, preemption needs to happen +; +; +__tx_thread_no_preempt_restore +; +; /* Restore interrupted thread or ISR. */ +; +; /* Pickup the saved stack pointer. */ +; tmp_ptr = _tx_thread_current_ptr -> tx_thread_stack_ptr; +; +; /* Recover the saved context and return to the point of interrupt. */ +; + LDMIA sp!, {r0, r10, r12, lr} ; Recover SPSR, POI, and scratch regs + MSR SPSR_cxsf, r0 ; Put SPSR back + LDMIA sp!, {r0-r3} ; Recover r0-r3 + MOVS pc, lr ; Return to point of interrupt +; +; } +; else +; { +__tx_thread_preempt_restore +; + LDMIA sp!, {r3, r10, r12, lr} ; Recover temporarily saved registers + MOV r1, lr ; Save lr (point of interrupt) + CPS #SYS_MODE ; Enter SYS mode + STR r1, [sp, #-4]! ; Save point of interrupt on thread's stack + STMDB sp!, {r4-r12, lr} ; Save upper half of registers on thread's stack + MOV r4, r3 ; Save SPSR in r4 + CPS #IRQ_MODE ; Enter IRQ mode + LDMIA sp!, {r0-r3} ; Recover r0-r3 + CPS #SYS_MODE ; Enter SYS mode + STMDB sp!, {r0-r3} ; Save r0-r3 on thread's stack + + LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr + LDR r0, [r1, #0] ; Pickup current thread pointer + +#ifdef __ARMVFP__ + LDR r2, [r0, #144] ; Pickup the VFP enabled flag + CMP r2, #0 ; Is the VFP enabled? + BEQ _tx_skip_irq_vfp_save ; No, skip VFP IRQ save + VMRS r2, FPSCR ; Pickup the FPSCR + STR r2, [sp, #-4]! ; Save FPSCR + VSTMDB sp!, {D16-D31} ; Save D16-D31 + VSTMDB sp!, {D0-D15} ; Save D0-D15 +_tx_skip_irq_vfp_save +#endif + + MOV r3, #1 ; Build interrupt stack type + STMDB sp!, {r3, r4} ; Save interrupt stack type and SPSR + STR sp, [r0, #8] ; Save stack pointer in thread control + ; block +; +; /* Save the remaining time-slice and disable it. */ +; if (_tx_timer_time_slice) +; { +; + LDR r3, =_tx_timer_time_slice ; Pickup time-slice variable address + LDR r2, [r3, #0] ; Pickup time-slice + CMP r2, #0 ; Is it active? + BEQ __tx_thread_dont_save_ts ; No, don't save it +; +; _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice; +; _tx_timer_time_slice = 0; +; + STR r2, [r0, #24] ; Save thread's time-slice + MOV r2, #0 ; Clear value + STR r2, [r3, #0] ; Disable global time-slice flag +; +; } +__tx_thread_dont_save_ts +; +; +; /* Clear the current task pointer. */ +; _tx_thread_current_ptr = TX_NULL; +; + MOV r0, #0 ; NULL value + STR r0, [r1, #0] ; Clear current thread pointer +; +; /* Return to the scheduler. */ +; _tx_thread_schedule(); +; + CPS #IRQ_MODE ; Enter IRQ mode + MRS r1, SPSR ; Get SPSR + ORR r1, r1, #SYS_MODE ; Change to SYS Mode + BIC r1, r1, #THUMB_MASK ; Clear thumb bit + MSR SPSR_cxsf, r1 ; Put SYS Mode in SPSR + LDR lr, =_tx_thread_schedule ; Load scheduler address + MOVS pc, lr ; Return to scheduler +; } +; +__tx_thread_idle_system_restore +; +; /* Just return back to the scheduler! */ +; + LDR lr, =_tx_thread_schedule ; Load scheduler address + MOVS pc, lr ; Return to scheduler +;} +; + END + diff --git a/ports_module/cortex_a7/iar/module_manager/src/tx_thread_context_save.s b/ports_module/cortex_a7/iar/module_manager/src/tx_thread_context_save.s new file mode 100644 index 00000000..8daa4306 --- /dev/null +++ b/ports_module/cortex_a7/iar/module_manager/src/tx_thread_context_save.s @@ -0,0 +1,192 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; + + EXTERN _tx_thread_system_state + EXTERN _tx_thread_current_ptr + EXTERN __tx_irq_processing_return +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + EXTERN _tx_execution_isr_enter +#endif +; +; + +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_context_save Cortex-A7/IAR */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function saves the context of an executing thread in the */ +;/* beginning of interrupt processing. The function also ensures that */ +;/* the system stack is used upon return to the calling ISR. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_context_save(VOID) +;{ + RSEG .text:CODE:NOROOT(2) + PUBLIC _tx_thread_context_save + ARM +_tx_thread_context_save +; +; /* Upon entry to this routine, it is assumed that IRQ interrupts are locked +; out, we are in IRQ mode, and all registers are intact. */ +; +; /* Check for a nested interrupt condition. */ +; if (_tx_thread_system_state++) +; { +; + STMDB sp!, {r0-r3} ; Save some working registers +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if ; Disable FIQ interrupts +#endif + LDR r3, =_tx_thread_system_state ; Pickup address of system state var + LDR r2, [r3, #0] ; Pickup system state + CMP r2, #0 ; Is this the first interrupt? + BEQ __tx_thread_not_nested_save ; Yes, not a nested context save +; +; /* Nested interrupt condition. */ +; + ADD r2, r2, #1 ; Increment the interrupt counter + STR r2, [r3, #0] ; Store it back in the variable +; +; /* Save the rest of the scratch registers on the stack and return to the +; calling ISR. */ +; + MRS r0, SPSR ; Pickup saved SPSR + SUB lr, lr, #4 ; Adjust point of interrupt + STMDB sp!, {r0, r10, r12, lr} ; Store other registers +; +; /* Return to the ISR. */ +; + MOV r10, #0 ; Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR enter function to indicate an ISR is executing. */ +; + PUSH {lr} ; Save ISR lr + BL _tx_execution_isr_enter ; Call the ISR enter function + POP {lr} ; Recover ISR lr +#endif + + B __tx_irq_processing_return ; Continue IRQ processing +; +__tx_thread_not_nested_save +; } +; +; /* Otherwise, not nested, check to see if a thread was running. */ +; else if (_tx_thread_current_ptr) +; { +; + ADD r2, r2, #1 ; Increment the interrupt counter + STR r2, [r3, #0] ; Store it back in the variable + LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr + LDR r0, [r1, #0] ; Pickup current thread pointer + CMP r0, #0 ; Is it NULL? + BEQ __tx_thread_idle_system_save ; If so, interrupt occurred in + ; scheduling loop - nothing needs saving! +; +; /* Save minimal context of interrupted thread. */ +; + MRS r2, SPSR ; Pickup saved SPSR + SUB lr, lr, #4 ; Adjust point of interrupt + STMDB sp!, {r2, r10, r12, lr} ; Store other registers +; +; /* Save the current stack pointer in the thread's control block. */ +; _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; +; +; /* Switch to the system stack. */ +; sp = _tx_thread_system_stack_ptr; +; + MOV r10, #0 ; Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR enter function to indicate an ISR is executing. */ +; + PUSH {lr} ; Save ISR lr + BL _tx_execution_isr_enter ; Call the ISR enter function + POP {lr} ; Recover ISR lr +#endif + + B __tx_irq_processing_return ; Continue IRQ processing +; +; } +; else +; { +; +__tx_thread_idle_system_save +; +; /* Interrupt occurred in the scheduling loop. */ +; +; /* Not much to do here, just adjust the stack pointer, and return to IRQ +; processing. */ +; + MOV r10, #0 ; Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR enter function to indicate an ISR is executing. */ +; + PUSH {lr} ; Save ISR lr + BL _tx_execution_isr_enter ; Call the ISR enter function + POP {lr} ; Recover ISR lr +#endif + + ADD sp, sp, #16 ; Recover saved registers + B __tx_irq_processing_return ; Continue IRQ processing +; +; } +;} +; + END + diff --git a/ports_module/cortex_a7/iar/module_manager/src/tx_thread_fiq_context_restore.s b/ports_module/cortex_a7/iar/module_manager/src/tx_thread_fiq_context_restore.s new file mode 100644 index 00000000..96844809 --- /dev/null +++ b/ports_module/cortex_a7/iar/module_manager/src/tx_thread_fiq_context_restore.s @@ -0,0 +1,246 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ + +SVC_MODE EQU 0xD3 ; SVC mode +FIQ_MODE EQU 0xD1 ; FIQ mode +MODE_MASK EQU 0x1F ; Mode mask +IRQ_MODE_BITS EQU 0x12 ; IRQ mode bits +; +; + EXTERN _tx_thread_system_state + EXTERN _tx_thread_current_ptr + EXTERN _tx_thread_system_stack_ptr + EXTERN _tx_thread_execute_ptr + EXTERN _tx_timer_time_slice + EXTERN _tx_thread_schedule + EXTERN _tx_thread_preempt_disable +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + EXTERN _tx_execution_isr_exit +#endif + +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_fiq_context_restore Cortex-A7/IAR */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function restores the fiq interrupt context when processing a */ +;/* nested interrupt. If not, it returns to the interrupt thread if no */ +;/* preemption is necessary. Otherwise, if preemption is necessary or */ +;/* if no thread was running, the function returns to the scheduler. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_schedule Thread scheduling routine */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* FIQ ISR Interrupt Service Routines */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_fiq_context_restore(VOID) +;{ + RSEG .text:CODE:NOROOT(2) + PUBLIC _tx_thread_fiq_context_restore + ARM +_tx_thread_fiq_context_restore +; +; /* Lockout interrupts. */ +; + CPSID if ; Disable IRQ and FIQ interrupts + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR exit function to indicate an ISR is complete. */ +; + BL _tx_execution_isr_exit ; Call the ISR exit function +#endif +; +; /* Determine if interrupts are nested. */ +; if (--_tx_thread_system_state) +; { +; + LDR r3, =_tx_thread_system_state ; Pickup address of system state var + LDR r2, [r3] ; Pickup system state + SUB r2, r2, #1 ; Decrement the counter + STR r2, [r3] ; Store the counter + CMP r2, #0 ; Was this the first interrupt? + BEQ __tx_thread_fiq_not_nested_restore ; If so, not a nested restore +; +; /* Interrupts are nested. */ +; +; /* Just recover the saved registers and return to the point of +; interrupt. */ +; + LDMIA sp!, {r0, r10, r12, lr} ; Recover SPSR, POI, and scratch regs + MSR SPSR_cxsf, r0 ; Put SPSR back + LDMIA sp!, {r0-r3} ; Recover r0-r3 + MOVS pc, lr ; Return to point of interrupt +; +; } +__tx_thread_fiq_not_nested_restore +; +; /* Determine if a thread was interrupted and no preemption is required. */ +; else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr)) +; || (_tx_thread_preempt_disable)) +; { +; + LDR r1, [sp] ; Pickup the saved SPSR + MOV r2, #MODE_MASK ; Build mask to isolate the interrupted mode + AND r1, r1, r2 ; Isolate mode bits + CMP r1, #IRQ_MODE_BITS ; Was an interrupt taken in IRQ mode before we + ; got to context save? */ + BEQ __tx_thread_fiq_no_preempt_restore ; Yes, just go back to point of interrupt + + + LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr + LDR r0, [r1] ; Pickup actual current thread pointer + CMP r0, #0 ; Is it NULL? + BEQ __tx_thread_fiq_idle_system_restore ; Yes, idle system was interrupted + + LDR r3, =_tx_thread_preempt_disable ; Pickup preempt disable address + LDR r2, [r3] ; Pickup actual preempt disable flag + CMP r2, #0 ; Is it set? + BNE __tx_thread_fiq_no_preempt_restore ; Yes, don't preempt this thread + LDR r3, =_tx_thread_execute_ptr ; Pickup address of execute thread ptr + LDR r2, [r3] ; Pickup actual execute thread pointer + CMP r0, r2 ; Is the same thread highest priority? + BNE __tx_thread_fiq_preempt_restore ; No, preemption needs to happen + + +__tx_thread_fiq_no_preempt_restore +; +; /* Restore interrupted thread or ISR. */ +; +; /* Pickup the saved stack pointer. */ +; tmp_ptr = _tx_thread_current_ptr -> tx_thread_stack_ptr; +; +; /* Recover the saved context and return to the point of interrupt. */ +; + LDMIA sp!, {r0, lr} ; Recover SPSR, POI, and scratch regs + MSR SPSR_cxsf, r0 ; Put SPSR back + LDMIA sp!, {r0-r3} ; Recover r0-r3 + MOVS pc, lr ; Return to point of interrupt +; +; } +; else +; { +__tx_thread_fiq_preempt_restore +; + LDMIA sp!, {r3, lr} ; Recover temporarily saved registers + MOV r1, lr ; Save lr (point of interrupt) + MOV r2, #SVC_MODE ; Build SVC mode CPSR + MSR CPSR_c, r2 ; Enter SVC mode + STR r1, [sp, #-4]! ; Save point of interrupt + STMDB sp!, {r4-r12, lr} ; Save upper half of registers + MOV r4, r3 ; Save SPSR in r4 + MOV r2, #FIQ_MODE ; Build FIQ mode CPSR + MSR CPSR_c, r2 ; Re-enter FIQ mode + LDMIA sp!, {r0-r3} ; Recover r0-r3 + MOV r5, #SVC_MODE ; Build SVC mode CPSR + MSR CPSR_c, r5 ; Enter SVC mode + STMDB sp!, {r0-r3} ; Save r0-r3 on thread's stack + + LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr + LDR r0, [r1] ; Pickup current thread pointer + +#ifdef __TARGET_FPU_VFP + LDR r2, [r0, #144] ; Pickup the VFP enabled flag + CMP r2, #0 ; Is the VFP enabled? + BEQ _tx_skip_fiq_vfp_save ; No, skip VFP FIQ save + VMRS r2, FPSCR ; Pickup the FPSCR + STR r2, [sp, #-4]! ; Save FPSCR + VSTMDB sp!, {D16-D31} ; Save D16-D31 + VSTMDB sp!, {D0-D15} ; Save D0-D15 +_tx_skip_fiq_vfp_save +#endif + + MOV r3, #1 ; Build interrupt stack type + STMDB sp!, {r3, r4} ; Save interrupt stack type and SPSR + STR sp, [r0, #8] ; Save stack pointer in thread control + ; block +; +; /* Save the remaining time-slice and disable it. */ +; if (_tx_timer_time_slice) +; { +; + LDR r3, =_tx_timer_time_slice ; Pickup time-slice variable address + LDR r2, [r3] ; Pickup time-slice + CMP r2, #0 ; Is it active? + BEQ __tx_thread_fiq_dont_save_ts ; No, don't save it +; +; _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice; +; _tx_timer_time_slice = 0; +; + STR r2, [r0, #24] ; Save thread's time-slice + MOV r2, #0 ; Clear value + STR r2, [r3] ; Disable global time-slice flag +; +; } +__tx_thread_fiq_dont_save_ts +; +; +; /* Clear the current task pointer. */ +; _tx_thread_current_ptr = TX_NULL; +; + MOV r0, #0 ; NULL value + STR r0, [r1] ; Clear current thread pointer +; +; /* Return to the scheduler. */ +; _tx_thread_schedule(); +; + B _tx_thread_schedule ; Return to scheduler +; } +; +__tx_thread_fiq_idle_system_restore +; +; /* Just return back to the scheduler! */ +; + ADD sp, sp, #24 ; Recover FIQ stack space + MOV r3, #SVC_MODE ; Build SVC mode CPSR + MSR CPSR_c, r3 ; Enter SVC mode + B _tx_thread_schedule ; Return to scheduler +; +;} +; + END + diff --git a/ports_module/cortex_a7/iar/module_manager/src/tx_thread_fiq_context_save.s b/ports_module/cortex_a7/iar/module_manager/src/tx_thread_fiq_context_save.s new file mode 100644 index 00000000..4f0b6cf7 --- /dev/null +++ b/ports_module/cortex_a7/iar/module_manager/src/tx_thread_fiq_context_save.s @@ -0,0 +1,192 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ + + EXTERN _tx_thread_system_state + EXTERN _tx_thread_current_ptr + EXTERN __tx_fiq_processing_return +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + EXTERN _tx_execution_isr_enter +#endif + +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_fiq_context_save Cortex-A7/IAR */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function saves the context of an executing thread in the */ +;/* beginning of interrupt processing. The function also ensures that */ +;/* the system stack is used upon return to the calling ISR. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* */ +;/**************************************************************************/ +; VOID _tx_thread_fiq_context_save(VOID) +;{ + RSEG .text:CODE:NOROOT(2) + PUBLIC _tx_thread_fiq_context_save + ARM +_tx_thread_fiq_context_save +; +; /* Upon entry to this routine, it is assumed that IRQ interrupts are locked +; out, we are in IRQ mode, and all registers are intact. */ +; +; /* Check for a nested interrupt condition. */ +; if (_tx_thread_system_state++) +; { +; + STMDB sp!, {r0-r3} ; Save some working registers + LDR r3, =_tx_thread_system_state ; Pickup address of system state var + LDR r2, [r3] ; Pickup system state + CMP r2, #0 ; Is this the first interrupt? + BEQ __tx_thread_fiq_not_nested_save ; Yes, not a nested context save +; +; /* Nested interrupt condition. */ +; + ADD r2, r2, #1 ; Increment the interrupt counter + STR r2, [r3] ; Store it back in the variable +; +; /* Save the rest of the scratch registers on the stack and return to the +; calling ISR. */ +; + MRS r0, SPSR ; Pickup saved SPSR + SUB lr, lr, #4 ; Adjust point of interrupt + STMDB sp!, {r0, r10, r12, lr} ; Store other registers +; +; /* Return to the ISR. */ +; + MOV r10, #0 ; Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR enter function to indicate an ISR is executing. */ +; + PUSH {lr} ; Save ISR lr + BL _tx_execution_isr_enter ; Call the ISR enter function + POP {lr} ; Recover ISR lr +#endif + + B __tx_fiq_processing_return ; Continue FIQ processing +; +__tx_thread_fiq_not_nested_save +; } +; +; /* Otherwise, not nested, check to see if a thread was running. */ +; else if (_tx_thread_current_ptr) +; { +; + ADD r2, r2, #1 ; Increment the interrupt counter + STR r2, [r3] ; Store it back in the variable + LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr + LDR r0, [r1] ; Pickup current thread pointer + CMP r0, #0 ; Is it NULL? + BEQ __tx_thread_fiq_idle_system_save ; If so, interrupt occurred in +; ; scheduling loop - nothing needs saving! +; +; /* Save minimal context of interrupted thread. */ +; + MRS r2, SPSR ; Pickup saved SPSR + SUB lr, lr, #4 ; Adjust point of interrupt + STMDB sp!, {r2, lr} ; Store other registers, Note that we don't +; ; need to save sl and ip since FIQ has +; ; copies of these registers. Nested +; ; interrupt processing does need to save +; ; these registers. +; +; /* Save the current stack pointer in the thread's control block. */ +; _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; +; +; /* Switch to the system stack. */ +; sp = _tx_thread_system_stack_ptr; +; + MOV r10, #0 ; Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR enter function to indicate an ISR is executing. */ +; + PUSH {lr} ; Save ISR lr + BL _tx_execution_isr_enter ; Call the ISR enter function + POP {lr} ; Recover ISR lr +#endif + + B __tx_fiq_processing_return ; Continue FIQ processing +; +; } +; else +; { +; +__tx_thread_fiq_idle_system_save +; +; /* Interrupt occurred in the scheduling loop. */ +; +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR enter function to indicate an ISR is executing. */ +; + PUSH {lr} ; Save ISR lr + BL _tx_execution_isr_enter ; Call the ISR enter function + POP {lr} ; Recover ISR lr +#endif +; +; /* Not much to do here, save the current SPSR and LR for possible +; use in IRQ interrupted in idle system conditions, and return to +; FIQ interrupt processing. */ +; + MRS r0, SPSR ; Pickup saved SPSR + SUB lr, lr, #4 ; Adjust point of interrupt + STMDB sp!, {r0, lr} ; Store other registers that will get used +; ; or stripped off the stack in context +; ; restore + B __tx_fiq_processing_return ; Continue FIQ processing +; +; } +;} +; + END + diff --git a/ports_module/cortex_a7/iar/module_manager/src/tx_thread_fiq_nesting_end.s b/ports_module/cortex_a7/iar/module_manager/src/tx_thread_fiq_nesting_end.s new file mode 100644 index 00000000..7f4cd145 --- /dev/null +++ b/ports_module/cortex_a7/iar/module_manager/src/tx_thread_fiq_nesting_end.s @@ -0,0 +1,101 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ + +#ifdef TX_ENABLE_FIQ_SUPPORT +DISABLE_INTS EQU 0xC0 ; Disable IRQ & FIQ interrupts +#else +DISABLE_INTS EQU 0x80 ; Disable IRQ interrupts +#endif +MODE_MASK EQU 0x1F ; Mode mask +FIQ_MODE_BITS EQU 0x11 ; FIQ mode bits + +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_fiq_nesting_end Cortex-A7/IAR */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is called by the application from FIQ mode after */ +;/* _tx_thread_fiq_nesting_start has been called and switches the FIQ */ +;/* processing from system mode back to FIQ mode prior to the ISR */ +;/* calling _tx_thread_fiq_context_restore. Note that this function */ +;/* assumes the system stack pointer is in the same position after */ +;/* nesting start function was called. */ +;/* */ +;/* This function assumes that the system mode stack pointer was setup */ +;/* during low-level initialization (tx_initialize_low_level.s). */ +;/* */ +;/* This function returns with FIQ interrupts disabled. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_fiq_nesting_end(VOID) +;{ + RSEG .text:CODE:NOROOT(2) + PUBLIC _tx_thread_fiq_nesting_end + ARM +_tx_thread_fiq_nesting_end + MOV r3,lr ; Save ISR return address + MRS r0, CPSR ; Pickup the CPSR + ORR r0, r0, #DISABLE_INTS ; Build disable interrupt value + MSR CPSR_c, r0 ; Disable interrupts + LDMIA sp!, {r1, lr} ; Pickup saved lr (and r1 throw-away for + ; 8-byte alignment logic) + BIC r0, r0, #MODE_MASK ; Clear mode bits + ORR r0, r0, #FIQ_MODE_BITS ; Build IRQ mode CPSR + MSR CPSR_c, r0 ; Re-enter IRQ mode +#ifdef INTER + BX r3 ; Return to caller +#else + MOV pc, r3 ; Return to caller +#endif +;} +; + END + diff --git a/ports_module/cortex_a7/iar/module_manager/src/tx_thread_fiq_nesting_start.s b/ports_module/cortex_a7/iar/module_manager/src/tx_thread_fiq_nesting_start.s new file mode 100644 index 00000000..7b8beef2 --- /dev/null +++ b/ports_module/cortex_a7/iar/module_manager/src/tx_thread_fiq_nesting_start.s @@ -0,0 +1,94 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ + +FIQ_DISABLE EQU 0x40 ; FIQ disable bit +MODE_MASK EQU 0x1F ; Mode mask +SYS_MODE_BITS EQU 0x1F ; System mode bits + +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_fiq_nesting_start Cortex-A7/IAR */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is called by the application from FIQ mode after */ +;/* _tx_thread_fiq_context_save has been called and switches the FIQ */ +;/* processing to the system mode so nested FIQ interrupt processing */ +;/* is possible (system mode has its own "lr" register). Note that */ +;/* this function assumes that the system mode stack pointer was setup */ +;/* during low-level initialization (tx_initialize_low_level.s). */ +;/* */ +;/* This function returns with FIQ interrupts enabled. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_fiq_nesting_start(VOID) +;{ + RSEG .text:CODE:NOROOT(2) + EXPORT _tx_thread_fiq_nesting_start + ARM +_tx_thread_fiq_nesting_start + MOV r3,lr ; Save ISR return address + MRS r0, CPSR ; Pickup the CPSR + BIC r0, r0, #MODE_MASK ; Clear the mode bits + ORR r0, r0, #SYS_MODE_BITS ; Build system mode CPSR + MSR CPSR_c, r0 ; Enter system mode + STMDB sp!, {r1, lr} ; Push the system mode lr on the system mode stack + ; and push r1 just to keep 8-byte alignment + BIC r0, r0, #FIQ_DISABLE ; Build enable FIQ CPSR + MSR CPSR_c, r0 ; Enter system mode +#ifdef INTER + BX r3 ; Return to caller +#else + MOV pc, r3 ; Return to caller +#endif +;} +; + END + diff --git a/ports_module/cortex_a7/iar/module_manager/src/tx_thread_interrupt_control.s b/ports_module/cortex_a7/iar/module_manager/src/tx_thread_interrupt_control.s new file mode 100644 index 00000000..f237cc35 --- /dev/null +++ b/ports_module/cortex_a7/iar/module_manager/src/tx_thread_interrupt_control.s @@ -0,0 +1,92 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; + +#ifdef TX_ENABLE_FIQ_SUPPORT +INT_MASK EQU 0xC0 ; Interrupt bit mask +#else +INT_MASK EQU 0x80 ; Interrupt bit mask +#endif +; +; + +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_control Cortex-A7/IAR */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is responsible for changing the interrupt lockout */ +;/* posture of the system. */ +;/* */ +;/* INPUT */ +;/* */ +;/* new_posture New interrupt lockout posture */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* old_posture Old interrupt lockout posture */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* */ +;/**************************************************************************/ +;UINT _tx_thread_interrupt_control(UINT new_posture) +;{ + RSEG .text:CODE:NOROOT(2) + PUBLIC _tx_thread_interrupt_control + ARM +_tx_thread_interrupt_control +; +; /* Pickup current interrupt lockout posture. */ +; + MRS r3, CPSR ; Pickup current CPSR + BIC r1, r3, #INT_MASK ; Clear interrupt lockout bits + ORR r1, r1, r0 ; Or-in new interrupt lockout bits +; +; /* Apply the new interrupt posture. */ +; + MSR CPSR_cxsf, r1 ; Setup new CPSR + AND r0, r3, #INT_MASK ; Return previous interrupt mask + BX lr ; Return to caller +; +;} +; + END + diff --git a/ports_module/cortex_a7/iar/module_manager/src/tx_thread_interrupt_disable.s b/ports_module/cortex_a7/iar/module_manager/src/tx_thread_interrupt_disable.s new file mode 100644 index 00000000..360764e0 --- /dev/null +++ b/ports_module/cortex_a7/iar/module_manager/src/tx_thread_interrupt_disable.s @@ -0,0 +1,88 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ + + +DISABLE_INTS DEFINE 0x80 ; IRQ interrupts disabled + + +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_disable Cortex-A7/IAR */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is responsible for disabling interrupts */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* old_posture Old interrupt lockout posture */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* */ +;/**************************************************************************/ +;UINT _tx_thread_interrupt_disable(VOID) +;{ + RSEG .text:CODE:NOROOT(2) + PUBLIC _tx_thread_interrupt_disable + ARM +_tx_thread_interrupt_disable +; +; /* Pickup current interrupt lockout posture. */ +; + MRS r0, CPSR ; Pickup current CPSR +; +; /* Mask interrupts. */ +; +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if ; Disable IRQ and FIQ +#else + CPSID i ; Disable IRQ +#endif + + BX lr ; Return to caller + +;} +; + END + diff --git a/ports_module/cortex_a7/iar/module_manager/src/tx_thread_interrupt_restore.s b/ports_module/cortex_a7/iar/module_manager/src/tx_thread_interrupt_restore.s new file mode 100644 index 00000000..bbd940e3 --- /dev/null +++ b/ports_module/cortex_a7/iar/module_manager/src/tx_thread_interrupt_restore.s @@ -0,0 +1,81 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ + + + +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_restore Cortex-A7/IAR */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is responsible for restoring interrupts to the state */ +;/* returned by a previous _tx_thread_interrupt_disable call. */ +;/* */ +;/* INPUT */ +;/* */ +;/* old_posture Old interrupt lockout posture */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* */ +;/**************************************************************************/ +;void _tx_thread_interrupt_restore(UINT old_posture) +;{ + RSEG .text:CODE:NOROOT(2) + PUBLIC _tx_thread_interrupt_restore + ARM +_tx_thread_interrupt_restore +; +; /* Apply the new interrupt posture. */ +; + MSR CPSR_cxsf, r0 ; Setup new CPSR +#ifdef TX_THUMB + BX lr ; Return to caller +#else + MOV pc, lr ; Return to caller +#endif +;} +; + END + diff --git a/ports_module/cortex_a7/iar/module_manager/src/tx_thread_irq_nesting_end.s b/ports_module/cortex_a7/iar/module_manager/src/tx_thread_irq_nesting_end.s new file mode 100644 index 00000000..fcfd3796 --- /dev/null +++ b/ports_module/cortex_a7/iar/module_manager/src/tx_thread_irq_nesting_end.s @@ -0,0 +1,101 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ + + + + +#ifdef TX_ENABLE_FIQ_SUPPORT +DISABLE_INTS EQU 0xC0 ; Disable IRQ & FIQ interrupts +#else +DISABLE_INTS EQU 0x80 ; Disable IRQ interrupts +#endif +MODE_MASK EQU 0x1F ; Mode mask +IRQ_MODE_BITS EQU 0x12 ; IRQ mode bits +; + + +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_irq_nesting_end Cortex-A7/IAR */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is called by the application from IRQ mode after */ +;/* _tx_thread_irq_nesting_start has been called and switches the IRQ */ +;/* processing from system mode back to IRQ mode prior to the ISR */ +;/* calling _tx_thread_context_restore. Note that this function */ +;/* assumes the system stack pointer is in the same position after */ +;/* nesting start function was called. */ +;/* */ +;/* This function assumes that the system mode stack pointer was setup */ +;/* during low-level initialization (tx_initialize_low_level.s). */ +;/* */ +;/* This function returns with IRQ interrupts disabled. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_irq_nesting_end(VOID) +;{ + RSEG .text:CODE:NOROOT(2) + PUBLIC _tx_thread_irq_nesting_end + ARM +_tx_thread_irq_nesting_end + MOV r3,lr ; Save ISR return address + MRS r0, CPSR ; Pickup the CPSR + ORR r0, r0, #DISABLE_INTS ; Build disable interrupt value + MSR CPSR_c, r0 ; Disable interrupts + LDMIA sp!, {r1, lr} ; Pickup saved lr (and r1 throw-away for + ; 8-byte alignment logic) + BIC r0, r0, #MODE_MASK ; Clear mode bits + ORR r0, r0, #IRQ_MODE_BITS ; Build IRQ mode CPSR + MSR CPSR_c, r0 ; Re-enter IRQ mode + BX r3 ; Return to caller +;} + END + diff --git a/ports_module/cortex_a7/iar/module_manager/src/tx_thread_irq_nesting_start.s b/ports_module/cortex_a7/iar/module_manager/src/tx_thread_irq_nesting_start.s new file mode 100644 index 00000000..471fa268 --- /dev/null +++ b/ports_module/cortex_a7/iar/module_manager/src/tx_thread_irq_nesting_start.s @@ -0,0 +1,94 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ + + + +IRQ_DISABLE EQU 0x80 ; IRQ disable bit +MODE_MASK EQU 0x1F ; Mode mask +SYS_MODE_BITS EQU 0x1F ; System mode bits + + +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_irq_nesting_start Cortex-A7/IAR */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is called by the application from IRQ mode after */ +;/* _tx_thread_context_save has been called and switches the IRQ */ +;/* processing to the system mode so nested IRQ interrupt processing */ +;/* is possible (system mode has its own "lr" register). Note that */ +;/* this function assumes that the system mode stack pointer was setup */ +;/* during low-level initialization (tx_initialize_low_level.s). */ +;/* */ +;/* This function returns with IRQ interrupts enabled. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_irq_nesting_start(VOID) +;{ + RSEG .text:CODE:NOROOT(2) + PUBLIC _tx_thread_irq_nesting_start + ARM +_tx_thread_irq_nesting_start + MOV r3, lr ; Save ISR return address + MRS r0, CPSR ; Pickup the CPSR + BIC r0, r0, #MODE_MASK ; Clear the mode bits + ORR r0, r0, #SYS_MODE_BITS ; Build system mode CPSR + MSR CPSR_c, r0 ; Enter system mode + STMDB sp!, {r1, lr} ; Push the system mode lr on the system mode stack + ; and push r1 just to keep 8-byte alignment + BIC r0, r0, #IRQ_DISABLE ; Build enable IRQ CPSR + MSR CPSR_c, r0 ; Enter system mode + BX r3 ; Return to caller + +;} +; + END + diff --git a/ports_module/cortex_a7/iar/module_manager/src/tx_thread_schedule.s b/ports_module/cortex_a7/iar/module_manager/src/tx_thread_schedule.s new file mode 100644 index 00000000..378a5336 --- /dev/null +++ b/ports_module/cortex_a7/iar/module_manager/src/tx_thread_schedule.s @@ -0,0 +1,452 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; + EXTERN _tx_thread_execute_ptr + EXTERN _tx_thread_current_ptr + EXTERN _tx_timer_time_slice +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + EXTERN _tx_execution_thread_enter +#endif + +IRQ_MODE EQU 0xD2 ; IRQ mode +USR_MODE EQU 0x10 ; USR mode +SVC_MODE EQU 0x13 ; SVC mode +SYS_MODE EQU 0x1F ; SYS mode + +#ifdef TX_ENABLE_FIQ_SUPPORT +ENABLE_INTS EQU 0xC0 ; IRQ & FIQ Interrupts enabled mask +#else +ENABLE_INTS EQU 0x80 ; IRQ Interrupts enabled mask +#endif + +MODE_MASK EQU 0x1F ; Mode mask +THUMB_MASK EQU 0x20 ; Thumb bit mask + + EXTERN _txm_system_mode_enter + EXTERN _txm_system_mode_exit + EXTERN _txm_ttbr1_page_table + + + +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_schedule Cortex-A7/MMU/IAR */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* Scott Larson, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function waits for a thread control block pointer to appear in */ +;/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ +;/* in the variable, the corresponding thread is resumed. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_initialize_kernel_enter ThreadX entry function */ +;/* _tx_thread_system_return Return to system from thread */ +;/* _tx_thread_context_restore Restore thread's context */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 Scott Larson Initial Version 6.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_schedule(VOID) +;{ + RSEG .text:CODE:NOROOT(2) + PUBLIC _tx_thread_schedule + ARM +_tx_thread_schedule + + ; Enter the scheduler. + SVC 0 + + ; We should never get here - ever! +_tx_scheduler_fault__ + B _tx_scheduler_fault__ +;} +; **************************************************************************** + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; SWI_Handler +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + + RSEG .text:CODE:NOROOT(2) + PUBLIC SWI_Handler + ARM +SWI_Handler + + STMFD sp!, {r0-r3, r12, lr} ; Store the registers + MOV r1, sp ; Set pointer to parameters + MRS r0, spsr ; Get spsr + STMFD sp!, {r0, r3} ; Store spsr onto stack and another + ; register to maintain 8-byte-aligned stack + TST r0, #THUMB_MASK ; Occurred in Thumb state? + LDRNEH r0, [lr,#-2] ; Yes: Load halfword and... + BICNE r0, r0, #0xFF00 ; ...extract comment field + LDREQ r0, [lr,#-4] ; No: Load word and... + BICEQ r0, r0, #0xFF000000 ; ...extract comment field + + ; r0 now contains SVC number + ; r1 now contains pointer to stacked registers + + ; + ; The service call is handled here + ; + + CMP r0, #0 ; Is it a schedule request? + BEQ _tx_handler_svc_schedule ; Yes, go there + + CMP r0, #1 ; Is it a system mode enter request? + BEQ _tx_handler_svc_super_enter ; Yes, go there + + CMP r0, #2 ; Is it a system mode exit request? + BEQ _tx_handler_svc_super_exit ; Yes, go there + + LDR r2, =0x123456 + CMP r0, r2 ; Is it an ARM request? + BEQ _tx_handler_svc_arm ; Yes, go there + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; Unknown SVC argument +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + ; Unrecognized service call +_tx_handler_svc_unrecognized + +_tx_handler_svc_unrecognized_loop ; We should never get here + B _tx_handler_svc_unrecognized_loop + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; SVC 1 +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + ; At this point we have an SVC 1, which means we are entering + ; supervisor mode to service a kernel call. +_tx_handler_svc_super_enter + ; Make sure that we have been called from the system mode enter location (security) + LDR r2, =_txm_system_mode_enter ; Load the address of the known call point + SUB r1, lr, #4 ; Calculate the address of the actual call + CMP r1, r2 ; Did we come from txm_module_manager_user_mode_entry? + BNE _tx_handler_svc_unrecognized ; Return to where we came + + ; Clear the user mode flag in the thread structure + LDR r1, =_tx_thread_current_ptr ; Load the current thread pointer address + LDR r2, [r1] ; Load current thread location from the pointer (pointer indirection) + MOV r1, #0 ; Load the new user mode flag value (user mode flag clear -> not user mode -> system) + STR r1, [r2, #0x9C] ; Clear the current user mode selection for thread + + ; Now we enter the system mode and return + LDMFD sp!, {r0, r3} ; Get spsr from the stack + BIC r0, r0, #MODE_MASK ; clear mode field + ORR r0, r0, #SYS_MODE ; system mode code + MSR SPSR_cxsf, r0 ; Restore the spsr + + LDR r1, [r2, #0xA8] ; Load the module kernel stack pointer + CPS #SYS_MODE ; Switch to SYS mode + MOV r3, sp ; Grab thread stack pointer + MOV sp, r1 ; Set SP to kernel stack pointer + CPS #SVC_MODE ; Switch back to SVC mode + STR r3, [r2, #0xB0] ; Save thread stack pointer +#ifndef TXM_MODULE_KERNEL_STACK_MAINTENANCE_DISABLE + LDR r3, [r2, #0xAC] ; Load the module kernel stack size + STR r3, [r2, #20] ; Set stack size + LDRD r0, r1, [r2, #0xA4] ; Load the module kernel stack start and end + STRD r0, r1, [r2, #0x0C] ; Set stack start and end +#endif + LDMFD sp!, {r0-r3, r12, pc}^ ; Restore the registers and return + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; SVC 2 +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + ; At this point we have an SVC 2, which means we are exiting + ; supervisor mode after servicing a kernel call. +_tx_handler_svc_super_exit + ; Make sure that we have been called from the system mode exit location (security) + LDR r2, =_txm_system_mode_exit ; Load the address of the known call point + SUB r1, lr, #4 ; Calculate the address of the actual call + CMP r1, r2 ; Did we come from txm_module_manager_user_mode_entry? + BNE _tx_handler_svc_unrecognized ; Return to where we came + + ; Set the user mode flag into the thread structure + LDR r1, =_tx_thread_current_ptr ; Load the current thread pointer address + LDR r2, [r1] ; Load the current thread location from the pointer (pointer indirection) + MOV r1, #1 ; Load the new user mode flag value (user mode enabled -> not system anymore) + STR r1, [r2, #0x9C] ; Clear the current user mode selection for thread + + ; Now we enter user mode (exit the system mode) and return + LDMFD sp!, {r0, r3} ; Get spsr from the stack + BIC r0, r0, #MODE_MASK ; clear mode field + ORR r0, r0, #USR_MODE ; user mode code + MSR SPSR_cxsf, r0 ; Restore the spsr + + LDR r1, [r2, #0xB0] ; Load the module thread stack pointer + CPS #SYS_MODE ; Switch to SYS mode + MOV sp, r1 ; Set SP back to thread stack pointer + CPS #SVC_MODE ; Switch back to SVC mode +#ifndef TXM_MODULE_KERNEL_STACK_MAINTENANCE_DISABLE + LDR r3, [r2, #0xBC] ; Load the module thread stack size + STR r3, [r2, #20] ; Set stack size + LDRD r0, r1, [r2, #0xB4] ; Load the module thread stack start and end + STRD r0, r1, [r2, #0x0C] ; Set stack start and end +#endif + LDMFD sp!, {r0-r3, r12, pc}^ ; Restore the registers and return + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; ARM Semihosting +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +_tx_handler_svc_arm + + ; *** TODO: handle semihosting requests or ARM angel requests *** + + ; just return + LDMFD sp!, {r0, r3} ; Get spsr from the stack + MSR SPSR_cxsf, r0 ; Restore the spsr + LDMFD sp!, {r0-r3, r12, pc}^ ; Restore the registers and return + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; SVC 0 +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + ; At this point we have an SVC 0: enter the scheduler. +_tx_handler_svc_schedule + + LDMFD sp!, {r0, r3} ; Get spsr from stack + MSR SPSR_cxsf, r0 ; Restore spsr + LDMFD sp!, {r0-r3, r12, lr} ; Restore the registers + + ; This code waits for a thread control block pointer to appear in + ; the _tx_thread_execute_ptr variable. Once a thread pointer appears + ; in the variable, the corresponding thread is resumed. +; +; /* Enable interrupts. */ +; + CPSIE i ; Enable IRQ interrupts + +; +; /* Wait for a thread to execute. */ +; do +; { + LDR r1, =_tx_thread_execute_ptr ; Address of thread execute ptr +; +__tx_thread_schedule_loop + LDR r0, [r1, #0] ; Pickup next thread to execute + CMP r0, #0 ; Is it NULL? + BEQ __tx_thread_schedule_loop ; If so, keep looking for a thread +; +; } +; while(_tx_thread_execute_ptr == TX_NULL); +; +; /* Yes! We have a thread to execute. Lockout interrupts and +; transfer control to it. */ +; + CPSID i ; Disable interrupts +; +; /* Setup the current thread pointer. */ +; _tx_thread_current_ptr = _tx_thread_execute_ptr; +; + LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread + STR r0, [r1, #0] ; Setup current thread pointer +; +; /* Increment the run count for this thread. */ +; _tx_thread_current_ptr -> tx_thread_run_count++; +; + LDR r2, [r0, #4] ; Pickup run counter + LDR r3, [r0, #24] ; Pickup time-slice for this thread + ADD r2, r2, #1 ; Increment thread run-counter + STR r2, [r0, #4] ; Store the new run counter +; +; /* Setup time-slice, if present. */ +; _tx_timer_time_slice = _tx_thread_current_ptr -> tx_thread_time_slice; +; + LDR r2, =_tx_timer_time_slice ; Pickup address of time slice variable + STR r3, [r2, #0] ; Setup time-slice +; +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the thread entry function to indicate the thread is executing. */ +; + MOV r5, r0 ; Save r0 + BL _tx_execution_thread_enter ; Call the thread execution enter function + MOV r0, r5 ; Restore r0 +#endif + + ; Determine if an interrupt frame or a synchronous task suspension frame is present. + CPS #SYS_MODE ; Enter SYS mode + LDR sp, [r0, #8] ; Switch to thread stack pointer + LDMIA sp!, {r4, r5} ; Pickup the stack type and saved CPSR + CPS #SVC_MODE ; Enter SVC mode + + ; ************************************************************************** + ; Set up MMU for module. + LDR r2, [r0, #0x94] ; Pickup the module pointer + CMP r2, #0 ; Valid module pointer? + LDRNE r2, [r2, #0x64] ; Load ASID + ; Otherwise, ASID 0 & master table will be loaded. + ; Is ASID already loaded? + MRC p15, 0, r1, c13, c0, 1 ; Read CONTEXTIDR into r1 + CMP r1, r2 + ; If so, skip MMU setup. + BEQ _tx_skip_mmu_update + ; New ASID & TTBR values to load + DSB + ISB + ; Load new ASID and TTBR + LDR r1, =_txm_ttbr1_page_table ; Load master TTBR + ORR r1, r1, #0x48 ; OR it with #TTBR0_ATTRIBUTES + MCR p15, 0, r1, c2, c0, 0 ; Change TTBR to master + ISB + DSB + MCR p15, 0, r2, c13, c0, 1 ; Change ASID to new value + ISB + ; Change TTBR to new value + MOV r3, #14 + ADD r1, r1, r2, LSL r3 + MCR p15, 0, r1, c2, c0, 0 ; Change TTBR to new value + + ; refresh TLB + MOV r2, #0 + DSB + MCR p15, 0, r2, c8, c7, 0 ; Invalidate entire unified TLB + MCR p15, 0, r2, c7, c5, 0 ; Invalidate all instruction caches to PoU + MCR p15, 0, r2, c7, c5, 6 ; Invalidate branch predictor + DSB + ISB + + ;test address translation + ;mcr p15, 0, r0, c7, c8, 0 + +_tx_skip_mmu_update + ; ************************************************************************** + + CMP r4, #0 ; Check for synchronous context switch + BEQ _tx_solicited_return + + MSR SPSR_cxsf, r5 ; Setup SPSR for return + LDR r1, [r0, #8] ; Get thread SP + LDR lr, [r1, #0x40] ; Get thread PC + CPS #SYS_MODE ; Enter SYS mode + +#ifdef __ARMVFP__ + LDR r2, [r0, #144] ; Pickup the VFP enabled flag + CMP r2, #0 ; Is the VFP enabled? + BEQ _tx_skip_interrupt_vfp_restore ; No, skip VFP interrupt restore + VLDMIA sp!, {D0-D15} ; Recover D0-D15 + VLDMIA sp!, {D16-D31} ; Recover D16-D31 + LDR r4, [sp], #4 ; Pickup FPSCR + VMSR FPSCR, r4 ; Restore FPSCR + CPS #SVC_MODE ; Enter SVC mode + LDR lr, [r1, #0x144] ; Get thread PC + CPS #SYS_MODE ; Enter SYS mode +_tx_skip_interrupt_vfp_restore +#endif + + LDMIA sp!, {r0-r12, lr} ; Restore registers + ADD sp, sp, #4 ; Fix stack pointer + CPS #SVC_MODE ; Enter SVC mode + SUBS pc, lr, #0 ; Return to point of thread interrupt + +_tx_solicited_return + MOV r2, r5 ; Move CPSR to scratch register + CPS #SYS_MODE ; Enter SYS mode + +#ifdef __ARMVFP__ + LDR r1, [r0, #144] ; Pickup the VFP enabled flag + CMP r1, #0 ; Is the VFP enabled? + BEQ _tx_skip_solicited_vfp_restore ; No, skip VFP solicited restore + VLDMIA sp!, {D8-D15} ; Recover D8-D15 + VLDMIA sp!, {D16-D31} ; Recover D16-D31 + LDR r4, [sp], #4 ; Pickup FPSCR + VMSR FPSCR, r4 ; Restore FPSCR +_tx_skip_solicited_vfp_restore +#endif + + LDMIA sp!, {r4-r11, lr} ; Restore registers + MOV r1, lr ; Copy lr to r1 to preserve across mode change + CPS #SVC_MODE ; Enter SVC mode + MSR SPSR_cxsf, r2 ; Recover CPSR + SUBS pc, r1, #0 ; Return to thread synchronously + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; End SWI_Handler +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +#ifdef __ARMVFP__ + PUBLIC tx_thread_vfp_enable + ARM +tx_thread_vfp_enable??rA +tx_thread_vfp_enable + MRS r2, CPSR ; Pickup the CPSR +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if ; Disable IRQ and FIQ interrupts +#else + CPSID i ; Disable IRQ interrupts +#endif + LDR r0, =_tx_thread_current_ptr ; Build current thread pointer address + LDR r1, [r0] ; Pickup current thread pointer + CMP r1, #0 ; Check for NULL thread pointer + BEQ __tx_no_thread_to_enable ; If NULL, skip VFP enable + MOV r0, #1 ; Build enable value + STR r0, [r1, #144] ; Set the VFP enable flag (tx_thread_vfp_enable field in TX_THREAD) +__tx_no_thread_to_enable + MSR CPSR_cxsf, r2 ; Recover CPSR + BX LR ; Return to caller + + PUBLIC tx_thread_vfp_disable + ARM +tx_thread_vfp_disable + MRS r2, CPSR ; Pickup the CPSR +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if ; Disable IRQ and FIQ interrupts +#else + CPSID i ; Disable IRQ interrupts +#endif + LDR r0, =_tx_thread_current_ptr ; Build current thread pointer address + LDR r1, [r0] ; Pickup current thread pointer + CMP r1, #0 ; Check for NULL thread pointer + BEQ __tx_no_thread_to_disable ; If NULL, skip VFP disable + MOV r0, #0 ; Build disable value + STR r0, [r1, #144] ; Clear the VFP enable flag (tx_thread_vfp_enable field in TX_THREAD) +__tx_no_thread_to_disable + MSR CPSR_cxsf, r2 ; Recover CPSR + BX LR ; Return to caller +#endif + + END + diff --git a/ports_module/cortex_a7/iar/module_manager/src/tx_thread_stack_build.s b/ports_module/cortex_a7/iar/module_manager/src/tx_thread_stack_build.s new file mode 100644 index 00000000..dcde4147 --- /dev/null +++ b/ports_module/cortex_a7/iar/module_manager/src/tx_thread_stack_build.s @@ -0,0 +1,153 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ + +SVC_MODE EQU 0x13 ; SVC mode +SYS_MODE EQU 0x1F ; SYS mode +#ifdef TX_ENABLE_FIQ_SUPPORT +CPSR_MASK EQU 0xDF ; Mask initial CPSR, IRQ & FIQ ints enabled +#else +CPSR_MASK EQU 0x9F ; Mask initial CPSR, IRQ ints enabled +#endif + +THUMB_MASK EQU 0x20 ; Thumb bit (5) of CPSR/SPSR + + +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_stack_build Cortex-A7/MMU/IAR */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* Scott Larson, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function builds a stack frame on the supplied thread's stack. */ +;/* The stack frame results in a fake interrupt return to the supplied */ +;/* function pointer. */ +;/* */ +;/* INPUT */ +;/* */ +;/* thread_ptr Pointer to thread control blk */ +;/* function_ptr Pointer to return function */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_thread_create Create thread service */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 Scott Larson Initial Version 6.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) +;{ + RSEG .text:CODE:NOROOT(2) + PUBLIC _tx_thread_stack_build + ARM +_tx_thread_stack_build +; +; +; /* Build a fake interrupt frame. The form of the fake interrupt stack +; on the Cortex-A7 should look like the following after it is built: +; +; Stack Top: 1 Interrupt stack frame type +; CPSR Initial value for CPSR +; a1 (r0) Initial value for a1 +; a2 (r1) Initial value for a2 +; a3 (r2) Initial value for a3 +; a4 (r3) Initial value for a4 +; v1 (r4) Initial value for v1 +; v2 (r5) Initial value for v2 +; v3 (r6) Initial value for v3 +; v4 (r7) Initial value for v4 +; v5 (r8) Initial value for v5 +; sb (r9) Initial value for sb +; sl (r10) Initial value for sl +; fp (r11) Initial value for fp +; ip (r12) Initial value for ip +; lr (r14) Initial value for lr +; pc (r15) Initial value for pc +; 0 For stack backtracing +; +; Stack Bottom: (higher memory address) */ +; + LDR r2, [r0, #16] ; Pickup end of stack area + BIC r2, r2, #7 ; Ensure 8-byte alignment + SUB r2, r2, #76 ; Allocate space for the stack frame +; +; /* Actually build the stack frame. */ +; + MOV r3, #1 ; Build interrupt stack type + STR r3, [r2, #0] ; Store stack type + MOV r3, #0 ; Build initial register value + STR r3, [r2, #8] ; Store initial r0 + STR r3, [r2, #12] ; Store initial r1 + STR r3, [r2, #16] ; Store initial r2 + STR r3, [r2, #20] ; Store initial r3 + STR r3, [r2, #24] ; Store initial r4 + STR r3, [r2, #28] ; Store initial r5 + STR r3, [r2, #32] ; Store initial r6 + STR r3, [r2, #36] ; Store initial r7 + STR r3, [r2, #40] ; Store initial r8 + STR r3, [r2, #44] ; Store initial r9 + LDR r3, [r0, #12] ; Pickup stack starting address + STR r3, [r2, #48] ; Store initial r10 (sl) + MOV r3, #0 ; Build initial register value + STR r3, [r2, #52] ; Store initial r11 + STR r3, [r2, #56] ; Store initial r12 + STR r3, [r2, #60] ; Store initial lr + STR r1, [r2, #64] ; Store initial pc + STR r3, [r2, #68] ; 0 for back-trace + + MRS r3, CPSR ; Pickup CPSR + BIC r3, r3, #CPSR_MASK ; Mask mode bits of CPSR + ORR r3, r3, #SYS_MODE ; Build CPSR, SYS mode, interrupts enabled + BIC r3, r3, #THUMB_MASK ; Clear Thumb bit by default + AND r1, r1, #1 ; Determine if the entry function is in Thumb mode + CMP r1, #1 ; Is the Thumb bit set? + ORREQ r3, r3, #THUMB_MASK ; Yes, set the Thumb bit + STR r3, [r2, #4] ; Store initial CPSR +; +; /* Setup stack pointer. */ +; thread_ptr -> tx_thread_stack_ptr = r2; +; + STR r2, [r0, #8] ; Save stack pointer in thread's + ; control block + BX lr ; Return to caller + + +;} + END + diff --git a/ports_module/cortex_a7/iar/module_manager/src/tx_thread_system_return.s b/ports_module/cortex_a7/iar/module_manager/src/tx_thread_system_return.s new file mode 100644 index 00000000..b52a15b1 --- /dev/null +++ b/ports_module/cortex_a7/iar/module_manager/src/tx_thread_system_return.s @@ -0,0 +1,148 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ + + EXTERN _tx_thread_current_ptr + EXTERN _tx_timer_time_slice + EXTERN _tx_thread_schedule +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + EXTERN _tx_execution_thread_exit +#endif + +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_system_return Cortex-A7/IAR */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is target processor specific. It is used to transfer */ +;/* control from a thread back to the ThreadX system. Only a */ +;/* minimal context is saved since the compiler assumes temp registers */ +;/* are going to get slicked by a function call anyway. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_schedule Thread scheduling loop */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ThreadX components */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_system_return(VOID) +;{ + RSEG .text:CODE:NOROOT(2) + PUBLIC _tx_thread_system_return + ARM +_tx_thread_system_return + +; /* Save minimal context on the stack. */ +; + STMDB sp!, {r4-r11, lr} ; Save minimal context + LDR r5, =_tx_thread_current_ptr ; Pickup address of current ptr + LDR r6, [r5, #0] ; Pickup current thread pointer + +#ifdef __ARMVFP__ + LDR r0, [r6, #144] ; Pickup the VFP enabled flag + CMP r0, #0 ; Is the VFP enabled? + BEQ _tx_skip_solicited_vfp_save ; No, skip VFP solicited save + VMRS r4, FPSCR ; Pickup the FPSCR + STR r4, [sp, #-4]! ; Save FPSCR + VSTMDB sp!, {D16-D31} ; Save D16-D31 + VSTMDB sp!, {D8-D15} ; Save D8-D15 +_tx_skip_solicited_vfp_save +#endif + + MOV r0, #0 ; Build a solicited stack type + MRS r1, CPSR ; Pickup the CPSR + STMDB sp!, {r0-r1} ; Save type and CPSR +; +; /* Lockout interrupts. */ +; +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if ; Disable IRQ and FIQ interrupts +#else + CPSID i ; Disable IRQ interrupts +#endif + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the thread exit function to indicate the thread is no longer executing. */ +; + BL _tx_execution_thread_exit ; Call the thread exit function +#endif + LDR r2, =_tx_timer_time_slice ; Pickup address of time slice + LDR r1, [r2, #0] ; Pickup current time slice +; +; /* Save current stack and switch to system stack. */ +; _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; +; sp = _tx_thread_system_stack_ptr; +; + STR sp, [r6, #8] ; Save thread stack pointer +; +; /* Determine if the time-slice is active. */ +; if (_tx_timer_time_slice) +; { +; + MOV r4, #0 ; Build clear value + CMP r1, #0 ; Is a time-slice active? + BEQ __tx_thread_dont_save_ts ; No, don't save the time-slice +; +; /* Save the current remaining time-slice. */ +; _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice; +; _tx_timer_time_slice = 0; +; + STR r4, [r2, #0] ; Clear time-slice + STR r1, [r6, #24] ; Store current time-slice +; +; } +__tx_thread_dont_save_ts +; +; /* Clear the current thread pointer. */ +; _tx_thread_current_ptr = TX_NULL; +; + STR r4, [r5, #0] ; Clear current thread pointer + + B _tx_thread_schedule ; Jump to scheduler! +; +;} + END + diff --git a/ports_module/cortex_a7/iar/module_manager/src/tx_thread_vectored_context_save.s b/ports_module/cortex_a7/iar/module_manager/src/tx_thread_vectored_context_save.s new file mode 100644 index 00000000..202ab5d4 --- /dev/null +++ b/ports_module/cortex_a7/iar/module_manager/src/tx_thread_vectored_context_save.s @@ -0,0 +1,173 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ + + EXTERN _tx_thread_system_state + EXTERN _tx_thread_current_ptr +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + EXTERN _tx_execution_isr_enter +#endif + +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_vectored_context_save Cortex-A7/IAR */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function saves the context of an executing thread in the */ +;/* beginning of interrupt processing. The function also ensures that */ +;/* the system stack is used upon return to the calling ISR. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_vectored_context_save(VOID) +;{ + RSEG .text:CODE:NOROOT(2) + PUBLIC _tx_thread_vectored_context_save + ARM +_tx_thread_vectored_context_save +; +; /* Upon entry to this routine, it is assumed that IRQ interrupts are locked +; out, we are in IRQ mode, and all registers are intact. */ +; +; /* Check for a nested interrupt condition. */ +; if (_tx_thread_system_state++) +; { +; +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if ; Disable IRQ and FIQ interrupts +#endif + LDR r3, =_tx_thread_system_state ; Pickup address of system state var + LDR r2, [r3, #0] ; Pickup system state + CMP r2, #0 ; Is this the first interrupt? + BEQ __tx_thread_not_nested_save ; Yes, not a nested context save +; +; /* Nested interrupt condition. */ +; + ADD r2, r2, #1 ; Increment the interrupt counter + STR r2, [r3, #0] ; Store it back in the variable +; +; /* Note: Minimal context of interrupted thread is already saved. */ +; +; /* Return to the ISR. */ +; + MOV r10, #0 ; Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR enter function to indicate an ISR is executing. */ +; + PUSH {lr} ; Save ISR lr + BL _tx_execution_isr_enter ; Call the ISR enter function + POP {lr} ; Recover ISR lr +#endif + + BX lr ; Return to caller +; +__tx_thread_not_nested_save +; } +; +; /* Otherwise, not nested, check to see if a thread was running. */ +; else if (_tx_thread_current_ptr) +; { +; + ADD r2, r2, #1 ; Increment the interrupt counter + STR r2, [r3, #0] ; Store it back in the variable + LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr + LDR r0, [r1, #0] ; Pickup current thread pointer + CMP r0, #0 ; Is it NULL? + BEQ __tx_thread_idle_system_save ; If so, interrupt occurred in + ; scheduling loop - nothing needs saving! +; +; /* Note: Minimal context of interrupted thread is already saved. */ +; +; /* Save the current stack pointer in the thread's control block. */ +; _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; +; +; /* Switch to the system stack. */ +; sp = _tx_thread_system_stack_ptr; +; + MOV r10, #0 ; Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR enter function to indicate an ISR is executing. */ +; + PUSH {lr} ; Save ISR lr + BL _tx_execution_isr_enter ; Call the ISR enter function + POP {lr} ; Recover ISR lr +#endif + + BX lr ; Return to caller + +__tx_thread_idle_system_save +; +; /* Interrupt occurred in the scheduling loop. */ +; +; /* Not much to do here, just adjust the stack pointer, and return to IRQ +; processing. */ +; + MOV r10, #0 ; Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR enter function to indicate an ISR is executing. */ +; + PUSH {lr} ; Save ISR lr + BL _tx_execution_isr_enter ; Call the ISR enter function + POP {lr} ; Recover ISR lr +#endif + + ADD sp, sp, #32 ; Recover saved registers + BX lr ; Return to caller + +; } +;} + + END + diff --git a/ports_module/cortex_a7/iar/module_manager/src/tx_timer_interrupt.s b/ports_module/cortex_a7/iar/module_manager/src/tx_timer_interrupt.s new file mode 100644 index 00000000..29e1c9be --- /dev/null +++ b/ports_module/cortex_a7/iar/module_manager/src/tx_timer_interrupt.s @@ -0,0 +1,245 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Timer */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ + +;Define Assembly language external references... +; + EXTERN _tx_timer_time_slice + EXTERN _tx_timer_system_clock + EXTERN _tx_timer_current_ptr + EXTERN _tx_timer_list_start + EXTERN _tx_timer_list_end + EXTERN _tx_timer_expired_time_slice + EXTERN _tx_timer_expired + EXTERN _tx_thread_time_slice + EXTERN _tx_timer_expiration_process +; +; +; +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_timer_interrupt Cortex-A7/IAR */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function processes the hardware timer interrupt. This */ +;/* processing includes incrementing the system clock and checking for */ +;/* time slice and/or timer expiration. If either is found, the */ +;/* interrupt context save/restore functions are called along with the */ +;/* expiration functions. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_timer_expiration_process Timer expiration processing */ +;/* _tx_thread_time_slice Time slice interrupted thread */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* interrupt vector */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_timer_interrupt(VOID) +;{ + RSEG .text:CODE:NOROOT(2) + PUBLIC _tx_timer_interrupt + ARM +_tx_timer_interrupt +; +; /* Upon entry to this routine, it is assumed that context save has already +; been called, and therefore the compiler scratch registers are available +; for use. */ +; +; /* Increment the system clock. */ +; _tx_timer_system_clock++; +; + LDR r1, =_tx_timer_system_clock ; Pickup address of system clock + LDR r0, [r1, #0] ; Pickup system clock + ADD r0, r0, #1 ; Increment system clock + STR r0, [r1, #0] ; Store new system clock +; +; /* Test for time-slice expiration. */ +; if (_tx_timer_time_slice) +; { +; + LDR r3, =_tx_timer_time_slice ; Pickup address of time-slice + LDR r2, [r3, #0] ; Pickup time-slice + CMP r2, #0 ; Is it non-active? + BEQ __tx_timer_no_time_slice ; Yes, skip time-slice processing +; +; /* Decrement the time_slice. */ +; _tx_timer_time_slice--; +; + SUB r2, r2, #1 ; Decrement the time-slice + STR r2, [r3, #0] ; Store new time-slice value +; +; /* Check for expiration. */ +; if (__tx_timer_time_slice == 0) +; + CMP r2, #0 ; Has it expired? + BNE __tx_timer_no_time_slice ; No, skip expiration processing +; +; /* Set the time-slice expired flag. */ +; _tx_timer_expired_time_slice = TX_TRUE; +; + LDR r3, =_tx_timer_expired_time_slice ; Pickup address of expired flag + MOV r0, #1 ; Build expired value + STR r0, [r3, #0] ; Set time-slice expiration flag +; +; } +; +__tx_timer_no_time_slice +; +; /* Test for timer expiration. */ +; if (*_tx_timer_current_ptr) +; { +; + LDR r1, =_tx_timer_current_ptr ; Pickup current timer pointer addr + LDR r0, [r1, #0] ; Pickup current timer + LDR r2, [r0, #0] ; Pickup timer list entry + CMP r2, #0 ; Is there anything in the list? + BEQ __tx_timer_no_timer ; No, just increment the timer +; +; /* Set expiration flag. */ +; _tx_timer_expired = TX_TRUE; +; + LDR r3, =_tx_timer_expired ; Pickup expiration flag address + MOV r2, #1 ; Build expired value + STR r2, [r3, #0] ; Set expired flag + B __tx_timer_done ; Finished timer processing +; +; } +; else +; { +__tx_timer_no_timer +; +; /* No timer expired, increment the timer pointer. */ +; _tx_timer_current_ptr++; +; + ADD r0, r0, #4 ; Move to next timer +; +; /* Check for wrap-around. */ +; if (_tx_timer_current_ptr == _tx_timer_list_end) +; + LDR r3, =_tx_timer_list_end ; Pickup addr of timer list end + LDR r2, [r3, #0] ; Pickup list end + CMP r0, r2 ; Are we at list end? + BNE __tx_timer_skip_wrap ; No, skip wrap-around logic +; +; /* Wrap to beginning of list. */ +; _tx_timer_current_ptr = _tx_timer_list_start; +; + LDR r3, =_tx_timer_list_start ; Pickup addr of timer list start + LDR r0, [r3, #0] ; Set current pointer to list start +; +__tx_timer_skip_wrap +; + STR r0, [r1, #0] ; Store new current timer pointer +; } +; +__tx_timer_done +; +; +; /* See if anything has expired. */ +; if ((_tx_timer_expired_time_slice) || (_tx_timer_expired)) +; { +; + LDR r3, =_tx_timer_expired_time_slice ; Pickup addr of expired flag + LDR r2, [r3, #0] ; Pickup time-slice expired flag + CMP r2, #0 ; Did a time-slice expire? + BNE __tx_something_expired ; If non-zero, time-slice expired + LDR r1, =_tx_timer_expired ; Pickup addr of other expired flag + LDR r0, [r1, #0] ; Pickup timer expired flag + CMP r0, #0 ; Did a timer expire? + BEQ __tx_timer_nothing_expired ; No, nothing expired +; +__tx_something_expired +; +; + STMDB sp!, {r0, lr} ; Save the lr register on the stack + ; and save r0 just to keep 8-byte alignment +; +; /* Did a timer expire? */ +; if (_tx_timer_expired) +; { +; + LDR r1, =_tx_timer_expired ; Pickup addr of expired flag + LDR r0, [r1, #0] ; Pickup timer expired flag + CMP r0, #0 ; Check for timer expiration + BEQ __tx_timer_dont_activate ; If not set, skip timer activation +; +; /* Process timer expiration. */ +; _tx_timer_expiration_process(); +; + BL _tx_timer_expiration_process ; Call the timer expiration handling routine +; +; } +__tx_timer_dont_activate +; +; /* Did time slice expire? */ +; if (_tx_timer_expired_time_slice) +; { +; + LDR r3, =_tx_timer_expired_time_slice ; Pickup addr of time-slice expired + LDR r2, [r3, #0] ; Pickup the actual flag + CMP r2, #0 ; See if the flag is set + BEQ __tx_timer_not_ts_expiration ; No, skip time-slice processing +; +; /* Time slice interrupted thread. */ +; _tx_thread_time_slice(); + + BL _tx_thread_time_slice ; Call time-slice processing +; +; } +; +__tx_timer_not_ts_expiration +; + LDMIA sp!, {r0, lr} ; Recover lr register (r0 is just there for + ; the 8-byte stack alignment +; +; } +; +__tx_timer_nothing_expired +; + BX lr ; Return to caller +; +;} + END + diff --git a/ports_module/cortex_a7/iar/module_manager/src/txm_module_manager_alignment_adjust.c b/ports_module/cortex_a7/iar/module_manager/src/txm_module_manager_alignment_adjust.c new file mode 100644 index 00000000..cdbfc2c7 --- /dev/null +++ b/ports_module/cortex_a7/iar/module_manager/src/txm_module_manager_alignment_adjust.c @@ -0,0 +1,90 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + +#include "tx_api.h" +#include "txm_module.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_alignment_adjust Cortex-A7/MMU/IAR */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function adjusts the alignment and size of the code and data */ +/* section for a given module implementation. */ +/* */ +/* INPUT */ +/* */ +/* code_size Size of the code area (updated) */ +/* code_alignment Code area alignment (updated) */ +/* data_size Size of data area (updated) */ +/* data_alignment Data area alignment (updated) */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Initial thread stack frame */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +VOID _txm_module_manager_alignment_adjust(TXM_MODULE_PREAMBLE *module_preamble, ULONG *code_size, ULONG *code_alignment, ULONG *data_size, ULONG *data_alignment) +{ + +ULONG local_code_size; +ULONG local_code_alignment; +ULONG local_data_size; +ULONG local_data_alignment; + + + /* Copy the input parameters into local variables for ease of use. */ + local_code_size = *code_size; + local_code_alignment = TXM_MODULE_MEMORY_ALIGNMENT; + local_data_size = *data_size; + local_data_alignment = TXM_MODULE_MEMORY_ALIGNMENT; + + /* Return all the information to the caller. */ + *code_size = ((local_code_size + TXM_MODULE_MEMORY_ALIGNMENT - 1)/TXM_MODULE_MEMORY_ALIGNMENT) * TXM_MODULE_MEMORY_ALIGNMENT; + *code_alignment = local_code_alignment; + *data_size = ((local_data_size + TXM_MODULE_MEMORY_ALIGNMENT - 1)/TXM_MODULE_MEMORY_ALIGNMENT) * TXM_MODULE_MEMORY_ALIGNMENT; + *data_alignment = local_data_alignment; +} diff --git a/ports_module/cortex_a7/iar/module_manager/src/txm_module_manager_external_memory_enable.c b/ports_module/cortex_a7/iar/module_manager/src/txm_module_manager_external_memory_enable.c new file mode 100644 index 00000000..1fa2f9db --- /dev/null +++ b/ports_module/cortex_a7/iar/module_manager/src/txm_module_manager_external_memory_enable.c @@ -0,0 +1,483 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + +#include "tx_api.h" +#include "tx_mutex.h" +#include "tx_queue.h" +#include "tx_thread.h" +#include "txm_module.h" + +/* External page tables. */ +extern ULONG _txm_level2_external_page_pool[TXM_LEVEL2_EXTERNAL_POOL_PAGES][TXM_LEVEL_2_PAGE_TABLE_ENTRIES]; +extern ULONG _txm_ttbr1_page_table[TXM_MAXIMUM_MODULES][TXM_MASTER_PAGE_TABLE_ENTRIES]; + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_level2_page_get Cortex-A7/MMU/AC5 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function gets an available L2 page table and places it in the */ +/* module external page table list. */ +/* */ +/* INPUT */ +/* */ +/* module_instance Module instance pointer */ +/* page_addr Address of L2 page */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _txm_module_manager_external_memory_enable */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +ULONG _txm_level2_page_get(TXM_MODULE_INSTANCE *module_instance, ULONG *page_addr) +{ + +UINT i; +UINT status; +UINT table_index; +UINT pool_index; + + /* Default status to success. */ + status = TX_SUCCESS; + + /* Find first free table slot in module control block. */ + for(i = 0; i < TXM_MODULE_LEVEL2_EXTERNAL_PAGES; i++) + { + if(module_instance->txm_external_page_table[i] == TX_NULL) + { + table_index = i; + break; + } + } + + if(i >= TXM_MODULE_LEVEL2_EXTERNAL_PAGES) + { + status = TXM_MODULE_EXTERNAL_MEMORY_ENABLE_ERROR; + } + + else + { + /* Find first free table in pool. */ + for(i = 0; i < TXM_LEVEL2_EXTERNAL_POOL_PAGES; i++) + { + if(_txm_level2_external_page_pool[i][0] == (ULONG) TX_NULL) + { + pool_index = i; + break; + } + } + + if(i >= TXM_LEVEL2_EXTERNAL_POOL_PAGES) + { + status = TXM_MODULE_EXTERNAL_MEMORY_ENABLE_ERROR; + } + } + + + if(status == TX_SUCCESS) + { + /* Place page address in table slot. Return page address. */ + module_instance->txm_external_page_table[table_index] = _txm_level2_external_page_pool[pool_index]; + *page_addr = (ULONG)_txm_level2_external_page_pool[pool_index]; + } + + return(status); +} + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_level2_page_clear Cortex-A7/MMU/IAR */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function clears the first entry in a L2 page table and clears */ +/* the table entry from the module external page table list. */ +/* */ +/* INPUT */ +/* */ +/* module_instance Module instance pointer */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* TXM_MODULE_MANAGER_MODULE_UNLOAD */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +VOID _txm_level2_page_clear(TXM_MODULE_INSTANCE *module_instance) +{ +UINT i; + + /* Clear table slots and zero out L2 entry. */ + for(i = 0; i < TXM_MODULE_LEVEL2_EXTERNAL_PAGES; i++) + { + if(module_instance->txm_external_page_table[i]) + { + *(ULONG *)module_instance->txm_external_page_table[i] = (ULONG)TX_NULL; + module_instance->txm_external_page_table[i] = TX_NULL; + } + } +} + + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_external_memory_enable Cortex-A7/MMU/IAR */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function creates an entry in the MMU table for a shared */ +/* memory space. */ +/* */ +/* INPUT */ +/* */ +/* module_instance Module instance pointer */ +/* start_address Start address of memory */ +/* length Length of external memory */ +/* attributes Memory attributes */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* _tx_mutex_get Get protection mutex */ +/* _tx_mutex_put Release protection mutex */ +/* TX_MEMSET Fill memory with constant */ +/* _txm_level2_page_get Get L2 page table */ +/* */ +/* CALLED BY */ +/* */ +/* Application code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +UINT _txm_module_manager_external_memory_enable( TXM_MODULE_INSTANCE *module_instance, + VOID *start_address, + ULONG length, + UINT attributes) +{ + +ULONG start_addr = (ULONG) start_address; +ULONG end_addr; +ULONG mmu_l1_entries; +ULONG mmu_l2_entries = 0; +ULONG level1_index; +ULONG level2_index; +ULONG temp_index; +ULONG temp_addr; +ULONG page_addr; +ULONG asid; +ULONG level1_attributes; +ULONG level2_attributes; +UINT status; +UINT i; + + /* Determine if the module manager has not been initialized yet. */ + if (_txm_module_manager_ready != TX_TRUE) + { + /* Module manager has not been initialized. */ + return(TX_NOT_AVAILABLE); + } + + /* Determine if the module is valid. */ + if (module_instance == TX_NULL) + { + /* Invalid module pointer. */ + return(TX_PTR_ERROR); + } + + /* Get module manager protection mutex. */ + _tx_mutex_get(&_txm_module_manager_mutex, TX_WAIT_FOREVER); + + /* Determine if the module instance is valid. */ + if (module_instance -> txm_module_instance_id != TXM_MODULE_ID) + { + /* Release the protection mutex. */ + _tx_mutex_put(&_txm_module_manager_mutex); + + /* Invalid module pointer. */ + return(TX_PTR_ERROR); + } + + /* Determine if the module instance is in the loaded state. */ + if (module_instance -> txm_module_instance_state != TXM_MODULE_LOADED) + { + /* Release the protection mutex. */ + _tx_mutex_put(&_txm_module_manager_mutex); + + /* Return error if the module is not ready. */ + return(TX_START_ERROR); + } + + /* Determine if the module instance is memory protected. */ + if (module_instance -> txm_module_instance_asid == 0) + { + /* Release the protection mutex. */ + _tx_mutex_put(&_txm_module_manager_mutex); + + /* Return error if the module is not protected. */ + return(TXM_MODULE_EXTERNAL_MEMORY_ENABLE_ERROR); + } + + /* Start address must be aligned to MMU block size (4 kB). + Length will be rounded up to 4 kB alignment. */ + if(start_addr & ~TXM_MMU_LEVEL2_MASK) + { + /* Release the protection mutex. */ + _tx_mutex_put(&_txm_module_manager_mutex); + + /* Return alignment error. */ + return(TXM_MODULE_ALIGNMENT_ERROR); + } + + /**************************************************************************/ + /* At this point, we have a valid address. Set up MMU. */ + /**************************************************************************/ + + /* Round length up to 4 kB alignment. */ + if(length & ~TXM_MMU_LEVEL2_MASK) + { + length = ((length + TXM_MODULE_MEMORY_ALIGNMENT - 1)/TXM_MODULE_MEMORY_ALIGNMENT) * TXM_MODULE_MEMORY_ALIGNMENT; + } + + /* Get end address. */ + end_addr = start_addr + length - 1; + + /* How many level 1 table entries does data span? */ + mmu_l1_entries = (end_addr >> TXM_MMU_LEVEL1_PAGE_SHIFT) - (start_addr >> TXM_MMU_LEVEL1_PAGE_SHIFT) + 1; + + /* Add 1 to align. */ + end_addr++; + + /* How many level 2 table entries does data need? + * 0: start and end addresses both aligned. + * 1: either start or end address aligned. + * 2: start and end addresses both not aligned. */ + if(start_addr & ~TXM_MMU_LEVEL1_MASK) + { + /* If start address is not aligned, increment. */ + mmu_l2_entries++; + } + if(end_addr & ~TXM_MMU_LEVEL1_MASK) + { + /* If end address is not aligned, increment. */ + mmu_l2_entries++; + } + + /* Get index into L1 table. */ + level1_index = (start_addr >> TXM_MMU_LEVEL1_PAGE_SHIFT); + + /* Get module ASID. */ + asid = module_instance -> txm_module_instance_asid; + + /* Do start and end entries need level 2 pages? */ + if(mmu_l2_entries > 0) + { + /* Build L2 attributes. */ + level2_attributes = ((attributes & TXM_MMU_ATTRIBUTE_XN) << TXM_MMU_LEVEL2_USER_ATTRIBUTE_XN_SHIFT) | + ((attributes & TXM_MMU_ATTRIBUTE_B) << TXM_MMU_LEVEL2_USER_ATTRIBUTE_B_SHIFT) | + ((attributes & TXM_MMU_ATTRIBUTE_C) << TXM_MMU_LEVEL2_USER_ATTRIBUTE_C_SHIFT) | + ((attributes & TXM_MMU_ATTRIBUTE_AP) << TXM_MMU_LEVEL2_USER_ATTRIBUTE_AP_SHIFT) | + ((attributes & TXM_MMU_ATTRIBUTE_TEX) << TXM_MMU_LEVEL2_USER_ATTRIBUTE_TEX_SHIFT) | + TXM_MMU_LEVEL2_USER_ATTRIBUTE_BASE; + + /* If start_addr is not aligned, we need a L2 page. */ + if(start_addr & ~TXM_MMU_LEVEL1_MASK) + { + + /* Is there already an L2 page in the L1 table? */ + if((_txm_ttbr1_page_table[asid][level1_index] & ~TXM_MMU_LEVEL1_SECOND_MASK) == TXM_MMU_LEVEL1_SECOND_ATTRIBUTES) + { + page_addr = _txm_ttbr1_page_table[asid][level1_index] & TXM_MMU_LEVEL1_SECOND_MASK; + } + else + { + /* Get L2 table from pool. */ + status = _txm_level2_page_get(module_instance, &page_addr); + + if(status != TX_SUCCESS) + { + /* Release the protection mutex. */ + _tx_mutex_put(&_txm_module_manager_mutex); + + return(TXM_MODULE_EXTERNAL_MEMORY_ENABLE_ERROR); + } + + /* Clear L2 table. */ + TX_MEMSET((void *)page_addr, 0, TXM_LEVEL_2_PAGE_TABLE_ENTRIES); + + /* Put L2 page in L1 table. */ + _txm_ttbr1_page_table[asid][level1_index] = (page_addr & TXM_MMU_LEVEL1_SECOND_MASK) | TXM_MMU_LEVEL1_SECOND_ATTRIBUTES; + } + + /* Decrement number of L1 entries remaining. */ + mmu_l1_entries--; + + /* Set up L2 start table. */ + /* Determine how many entries in L2 table. */ + if((end_addr >> TXM_MMU_LEVEL1_PAGE_SHIFT) - (start_addr >> TXM_MMU_LEVEL1_PAGE_SHIFT)) + { + /* End address goes to next L1 page (or beyond). */ + temp_addr = ((start_addr >> TXM_MMU_LEVEL1_PAGE_SHIFT) + 1) << (TXM_MMU_LEVEL1_PAGE_SHIFT); + mmu_l2_entries = (temp_addr - start_addr) >> TXM_MMU_LEVEL2_PAGE_SHIFT; + } + else + { + /* End address is on the same L1 page. */ + mmu_l2_entries = (end_addr >> TXM_MMU_LEVEL2_PAGE_SHIFT) - (start_addr >> TXM_MMU_LEVEL2_PAGE_SHIFT); + } + + /* Insert module settings into start table. */ + level2_index = ((start_addr & ~TXM_MMU_LEVEL1_MASK) >> TXM_MMU_LEVEL2_PAGE_SHIFT); + for(i = 0; i < mmu_l2_entries; i++, level2_index++) + { + ((ULONG *) page_addr)[level2_index] = (start_addr & TXM_MMU_LEVEL1_MASK) | (level2_index << TXM_MMU_LEVEL2_PAGE_SHIFT) | level2_attributes; + } + + level1_index++; + } + + /* Does last entry need a level 2 page? */ + /* If end_address is not aligned, we need a L2 page. */ + if((end_addr & ~TXM_MMU_LEVEL1_MASK) && (mmu_l1_entries != 0)) + { + /* Get index into L1 table. */ + temp_index = (end_addr >> TXM_MMU_LEVEL1_PAGE_SHIFT); + + /* Is there already an L2 page in the L1 table? */ + if((_txm_ttbr1_page_table[asid][temp_index] & ~TXM_MMU_LEVEL1_SECOND_MASK) == TXM_MMU_LEVEL1_SECOND_ATTRIBUTES) + { + page_addr = _txm_ttbr1_page_table[asid][temp_index] & TXM_MMU_LEVEL1_SECOND_MASK; + } + else + { + /* Get L2 table from pool. */ + status = _txm_level2_page_get(module_instance, &page_addr); + + if(status != TX_SUCCESS) + { + /* Release the protection mutex. */ + _tx_mutex_put(&_txm_module_manager_mutex); + + return(TXM_MODULE_EXTERNAL_MEMORY_ENABLE_ERROR); + } + + /* Clear L2 table. */ + TX_MEMSET((void *)page_addr, 0, TXM_LEVEL_2_PAGE_TABLE_ENTRIES); + + /* Put L2 page in L1 table. */ + _txm_ttbr1_page_table[asid][temp_index] = (page_addr & TXM_MMU_LEVEL1_SECOND_MASK) | TXM_MMU_LEVEL1_SECOND_ATTRIBUTES; + } + + /* Decrement number of L1 entries remaining. */ + mmu_l1_entries--; + + /* Determine how many entries in L2 table. */ + mmu_l2_entries = ((end_addr & ~TXM_MMU_LEVEL1_MASK) >> TXM_MMU_LEVEL2_PAGE_SHIFT); + + /* Set up L2 end table. */ + for(i = 0; i < mmu_l2_entries; i++) + { + ((ULONG *) page_addr)[i] = (end_addr & TXM_MMU_LEVEL1_MASK) | (i << TXM_MMU_LEVEL2_PAGE_SHIFT) | level2_attributes; + } + } + } + + /* Fill any L1 entries between start and end pages of module data range. */ + for(i = 0; i < mmu_l1_entries; i++, level1_index++) + { + /* Build L1 attributes. */ + level1_attributes = ((attributes & TXM_MMU_ATTRIBUTE_XN) << TXM_MMU_LEVEL1_USER_ATTRIBUTE_XN_SHIFT) | + ((attributes & TXM_MMU_ATTRIBUTE_B) << TXM_MMU_LEVEL1_USER_ATTRIBUTE_B_SHIFT) | + ((attributes & TXM_MMU_ATTRIBUTE_C) << TXM_MMU_LEVEL1_USER_ATTRIBUTE_C_SHIFT) | + ((attributes & TXM_MMU_ATTRIBUTE_AP) << TXM_MMU_LEVEL1_USER_ATTRIBUTE_AP_SHIFT) | + ((attributes & TXM_MMU_ATTRIBUTE_TEX) << TXM_MMU_LEVEL1_USER_ATTRIBUTE_TEX_SHIFT) | + TXM_MMU_LEVEL1_USER_ATTRIBUTE_BASE; + + /* Place address and attributes in table. */ + _txm_ttbr1_page_table[asid][level1_index] = (level1_index << TXM_MMU_LEVEL1_PAGE_SHIFT) | level1_attributes; + } + + + /* Release the protection mutex. */ + _tx_mutex_put(&_txm_module_manager_mutex); + + /* Return success. */ + return(TX_SUCCESS); +} diff --git a/ports_module/cortex_a7/iar/module_manager/src/txm_module_manager_memory_fault_handler.c b/ports_module/cortex_a7/iar/module_manager/src/txm_module_manager_memory_fault_handler.c new file mode 100644 index 00000000..d63dedf0 --- /dev/null +++ b/ports_module/cortex_a7/iar/module_manager/src/txm_module_manager_memory_fault_handler.c @@ -0,0 +1,112 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + +#include "tx_api.h" +#include "tx_thread.h" +#include "txm_module.h" + + +/* Define the user's fault notification callback function pointer. This is + setup via the txm_module_manager_memory_fault_notify API. */ + +VOID (*_txm_module_manager_fault_notify)(TX_THREAD *, TXM_MODULE_INSTANCE *); + + +/* Define a macro that can be used to allocate global variables useful to + store information about the last fault. This macro is defined in + txm_module_port.h and is usually populated in the assembly language + fault handling prior to the code calling _txm_module_manager_memory_fault_handler. */ + +TXM_MODULE_MANAGER_FAULT_INFO + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_memory_fault_handler Cortex-A7/MMU/IAR */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function handles a fault associated with a memory protected */ +/* module. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_terminate Terminate thread */ +/* */ +/* CALLED BY */ +/* */ +/* Fault handler */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +VOID _txm_module_manager_memory_fault_handler(VOID) +{ + +TXM_MODULE_INSTANCE *module_instance_ptr; +TX_THREAD *thread_ptr; + + + /* Pickup the current thread. */ + thread_ptr = _tx_thread_current_ptr; + + /* Initialize the module instance pointer to NULL. */ + module_instance_ptr = TX_NULL; + + /* Is there a thread? */ + if (thread_ptr) + { + /* Pickup the module instance. */ + module_instance_ptr = thread_ptr -> tx_thread_module_instance_ptr; + + /* Terminate the current thread. */ + _tx_thread_terminate(_tx_thread_current_ptr); + } + + /* Determine if there is a user memory fault notification callback. */ + if (_txm_module_manager_fault_notify) + { + /* Yes, call the user's notification memory fault callback. */ + (_txm_module_manager_fault_notify)(thread_ptr, module_instance_ptr); + } +} + diff --git a/ports_module/cortex_a7/iar/module_manager/src/txm_module_manager_memory_fault_notify.c b/ports_module/cortex_a7/iar/module_manager/src/txm_module_manager_memory_fault_notify.c new file mode 100644 index 00000000..7cbd22fc --- /dev/null +++ b/ports_module/cortex_a7/iar/module_manager/src/txm_module_manager_memory_fault_notify.c @@ -0,0 +1,84 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + +#include "tx_api.h" +#include "tx_thread.h" +#include "txm_module.h" + + +/* Define the external user's fault notification callback function pointer. This is + setup via the txm_module_manager_memory_fault_notify API. */ + +extern VOID (*_txm_module_manager_fault_notify)(TX_THREAD *, TXM_MODULE_INSTANCE *); + + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_memory_fault_notify Cortex-A7/MMU/IAR */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function registers an application callback when/if a memory */ +/* fault occurs. The supplied thread is automatically terminated, but */ +/* any other threads in the same module may still execute. */ +/* */ +/* INPUT */ +/* */ +/* notify_function Memory fault notification */ +/* function, NULL disables. */ +/* */ +/* OUTPUT */ +/* */ +/* status Completion status */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +UINT _txm_module_manager_memory_fault_notify(VOID (*notify_function)(TX_THREAD *, TXM_MODULE_INSTANCE *)) +{ + /* Setup notification function. */ + _txm_module_manager_fault_notify = notify_function; + + /* Return success. */ + return(TX_SUCCESS); +} diff --git a/ports_module/cortex_a7/iar/module_manager/src/txm_module_manager_mm_initialize.c b/ports_module/cortex_a7/iar/module_manager/src/txm_module_manager_mm_initialize.c new file mode 100644 index 00000000..18b20506 --- /dev/null +++ b/ports_module/cortex_a7/iar/module_manager/src/txm_module_manager_mm_initialize.c @@ -0,0 +1,304 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + +#include "tx_api.h" +#include "txm_module.h" + +#define CACHE_DISABLED 0x12 +#define SDRAM_START 0x00000000 +#define SDRAM_END 0x1fffffff +#define CACHE_WRITEBACK 0x1e + +#define SECTION_DESCRIPTOR 0x00000002 +#define DACR_CLIENT_MODE 0x55555555 + + +/*** Page table attributes TTBR0 *********************************************** +* IRGN = 01 - Normal memory, Inner Write-Back Write-Allocate Cacheable +* S - non-shareable +* RGN = 01 - Normal memory, Outer Write-Back Write-Allocate Cacheable +* NOS - outer-shareable +*******************************************************************************/ +#define TTBR0_ATTRIBUTES 0x48 + + + +/* ASID table, index is ASID number and contents hold pointer to module. */ +TXM_MODULE_INSTANCE *_txm_asid_table[TXM_ASID_TABLE_LENGTH]; + +/* Master page table, 2^14 (16kB) alignment. + * First table is the master level 1 table, the rest are for each module. */ +#pragma data_alignment=16384 +ULONG _txm_ttbr1_page_table[TXM_MAXIMUM_MODULES][TXM_MASTER_PAGE_TABLE_ENTRIES]; + +/* Module start and end level 2 page tables, 2^10 (1kB) alignment. + * First set of 4 tables are the master level 2 tables, the rest are for each module. + * Each module needs two L2 tables for code and two L2 tables for data. */ +#pragma data_alignment=1024 +ULONG _txm_level2_module_page_table[TXM_MAXIMUM_MODULES * 4][TXM_LEVEL_2_PAGE_TABLE_ENTRIES]; + +/* Module external memory level 2 page tables, 2^10 (1kB) alignment. */ +#pragma data_alignment=1024 +ULONG _txm_level2_external_page_pool[TXM_LEVEL2_EXTERNAL_POOL_PAGES][TXM_LEVEL_2_PAGE_TABLE_ENTRIES]; + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_mm_initialize Cortex-A7/MMU/IAR */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function performs the initial set up of the the A7 MMU. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +UINT _txm_module_manager_mm_initialize(VOID) +{ + +#ifdef TXM_MODULE_MEMORY_PROTECTION_ENABLED + UINT i; + ULONG cp15reg; + UINT user_mode_index; + UINT counter_limit; + + /* Clear ASID table. */ + for (i = 0; i < TXM_ASID_TABLE_LENGTH; i++) + { + _txm_asid_table[i] = 0; + } + _txm_asid_table[0] = (TXM_MODULE_INSTANCE *)TXM_ASID_RESERVED; + + + /********************************************************************************/ + /* This is an example showing how to set up the cache attributes. */ + /********************************************************************************/ + +/******************************************************************************* +* PAGE TABLE generation +* Generate the page tables +* Build a flat translation table for the whole address space. +* ie: Create 4096 1MB sections from 0x000xxxxx to 0xFFFxxxxx +* 31 20|19 18|17|16| 15|14 12|11 10|9|8 5|4 |3 2|1 0| +* |base address | 0 0|nG| S|AP2|TEX |AP |P|Domain|XN|CB |1 0| +* +* Bits[31:20] - Top 12 bits of VA is pointer into table +* nG[17]=0 - Non global, enables matching against ASID in the TLB when set. +* S[16]=0 - Indicates normal memory is shared when set. +* AP2[15]=0 +* TEX[14:12]=000 +* AP[11:10]=11 - Configure for full read/write access in all modes +* IMPP[9]=0 - Ignored +* Domain[5:8]=1111 - Set all pages to use domain 15 +* XN[4]=0 - Execute never disabled +* CB[3:2]= 00 - Set attributes to Strongly-ordered memory. +* (except for the descriptor where code segment is based, +* see below) +* Bits[1:0]=10 - Indicate entry is a 1MB section +*******************************************************************************/ + +/* ---- Parameter setting to level1 descriptor (bits 19:0) ---- */ +/* setting for Strongly-ordered memory + B-00000000000000000000010111100010 */ +#define TTB_PARA_STRGLY 0x05E2 + +/* setting for Outer and inner not cache normal memory + B-00000000000000000001010111100010 */ +#define TTB_PARA_NORMAL_NOT_CACHE 0x15E2 + +/* setting for Outer and inner write back, write allocate normal memory + (Cacheable) + B-00000000000000000001010111101110 */ +#define TTB_PARA_NORMAL_CACHE 0x15EE //0x15EE + +/* In this chip (RZA1) there are the following 12 sections with the defined memory size (MB) */ +#define M_SIZE_NOR 128 /* [Area00] CS0, CS1 area (for NOR flash) */ +#define M_SIZE_SDRAM 128 /* [Area01] CS2, CS3 area (for SDRAM) */ +#define M_SIZE_CS45 128 /* [Area02] CS4, CS5 area */ +#define M_SIZE_SPI 128 /* [Area03] SPI, SP2 area (for Serial flash) */ +#define M_SIZE_RAM 10 /* [Area04] Internal RAM */ +#define M_SIZE_IO_1 502 /* [Area05] I/O area 1 */ +#define M_SIZE_NOR_M 128 /* [Area06] CS0, CS1 area (for NOR flash) (mirror) */ +#define M_SIZE_SDRAM_M 128 /* [Area07] CS2, CS3 area (for SDRAM) (mirror) */ +#define M_SIZE_CS45_M 128 /* [Area08] CS4, CS5 area (mirror) */ +#define M_SIZE_SPI_M 128 /* [Area09] SPI, SP2 area (for Serial flash) (mirror) */ +#define M_SIZE_RAM_M 10 /* [Area10] Internal RAM (mirror) */ +#define M_SIZE_IO_2 2550 /* [Area11] I/O area 2 */ +/* Should add to: 4096 */ + + counter_limit = M_SIZE_NOR; + for (i = 0; i < counter_limit; i++) + { + _txm_ttbr1_page_table[TXM_MASTER_PAGE_TABLE_INDEX][i] = (i << TXM_MMU_LEVEL1_PAGE_SHIFT) | TTB_PARA_NORMAL_CACHE; + } + + counter_limit += M_SIZE_SDRAM; + for (; i < counter_limit; i++) + { + _txm_ttbr1_page_table[TXM_MASTER_PAGE_TABLE_INDEX][i] = (i << TXM_MMU_LEVEL1_PAGE_SHIFT) | TTB_PARA_NORMAL_CACHE; + } + + counter_limit += M_SIZE_CS45; + for (; i < counter_limit; i++) + { + _txm_ttbr1_page_table[TXM_MASTER_PAGE_TABLE_INDEX][i] = (i << TXM_MMU_LEVEL1_PAGE_SHIFT) | TTB_PARA_STRGLY; + } + + counter_limit += M_SIZE_SPI; + for (; i < counter_limit; i++) + { + _txm_ttbr1_page_table[TXM_MASTER_PAGE_TABLE_INDEX][i] = (i << TXM_MMU_LEVEL1_PAGE_SHIFT) | TTB_PARA_NORMAL_CACHE; + } + + counter_limit += M_SIZE_RAM; + for (; i < counter_limit; i++) + { + _txm_ttbr1_page_table[TXM_MASTER_PAGE_TABLE_INDEX][i] = (i << TXM_MMU_LEVEL1_PAGE_SHIFT) | TTB_PARA_NORMAL_CACHE; + } + + counter_limit += M_SIZE_IO_1; + for (; i < counter_limit; i++) + { + _txm_ttbr1_page_table[TXM_MASTER_PAGE_TABLE_INDEX][i] = (i << TXM_MMU_LEVEL1_PAGE_SHIFT) | TTB_PARA_STRGLY; + } + + counter_limit += M_SIZE_NOR_M; + for (; i < counter_limit; i++) + { + _txm_ttbr1_page_table[TXM_MASTER_PAGE_TABLE_INDEX][i] = (i << TXM_MMU_LEVEL1_PAGE_SHIFT) | TTB_PARA_NORMAL_NOT_CACHE; + } + + counter_limit += M_SIZE_SDRAM_M; + for (; i < counter_limit; i++) + { + _txm_ttbr1_page_table[TXM_MASTER_PAGE_TABLE_INDEX][i] = (i << TXM_MMU_LEVEL1_PAGE_SHIFT) | TTB_PARA_NORMAL_NOT_CACHE; + } + + counter_limit += M_SIZE_CS45_M; + for (; i < counter_limit; i++) + { + _txm_ttbr1_page_table[TXM_MASTER_PAGE_TABLE_INDEX][i] = (i << TXM_MMU_LEVEL1_PAGE_SHIFT) | TTB_PARA_STRGLY; + } + + counter_limit += M_SIZE_SPI_M; + for (; i < counter_limit; i++) + { + _txm_ttbr1_page_table[TXM_MASTER_PAGE_TABLE_INDEX][i] = (i << TXM_MMU_LEVEL1_PAGE_SHIFT) | TTB_PARA_NORMAL_NOT_CACHE; + } + + counter_limit += M_SIZE_RAM_M; + for (; i < counter_limit; i++) + { + _txm_ttbr1_page_table[TXM_MASTER_PAGE_TABLE_INDEX][i] = (i << TXM_MMU_LEVEL1_PAGE_SHIFT) | TTB_PARA_NORMAL_NOT_CACHE; + } + + counter_limit += M_SIZE_IO_2; + for (; i < counter_limit; i++) + { + _txm_ttbr1_page_table[TXM_MASTER_PAGE_TABLE_INDEX][i] = (i << TXM_MMU_LEVEL1_PAGE_SHIFT) | TTB_PARA_STRGLY; + } + + /********************************************************************************/ + /* This is the end of the example showing how to set up the cache attributes. */ + /********************************************************************************/ + + + /* Clear ASID. */ + cp15reg = 0; + asm volatile ("mcr p15, 0, %0, c13, c0, 1" : : "r"(cp15reg) : ); + asm("isb"); + + /* Put the page table address in TTBR. */ + cp15reg = (int)(VOID*)_txm_ttbr1_page_table; + cp15reg |= TTBR0_ATTRIBUTES; + asm volatile ("mcr p15, 0, %0, c2, c0, 0" : : "r"(cp15reg) : ); + + /* Set the domain to client mode. */ + cp15reg = DACR_CLIENT_MODE; + asm volatile ("mcr p15, 0, %0, c3, c0, 0" : : "r"(cp15reg) : ); + + +/* Level 2 small page attributes: normal memory, cache & buffer enabled, priviledged access. */ +#define TTB_LEVEL2_NORMAL_CACHE 0x05E + +/* Level 2 clear AP attributes mask. */ +#define TTB_LEVEL2_AP_CLEAR_MASK 0xFFFFFFCF + +/* Attributes for user mode table entry in level 2 table. */ +#define TTB_LEVEL2_USER_MODE_ENTRY 0x06E + + /* Set up Level 2 table for user to kernel mode entry trampoline. */ + /* Find which table entry _txm_module_manager_user_mode_entry is in. */ + user_mode_index = (ULONG)_txm_module_manager_user_mode_entry >> TXM_MMU_LEVEL1_PAGE_SHIFT; + /* Fill table. */ + for (i = 0; i < TXM_LEVEL_2_PAGE_TABLE_ENTRIES; i++) + { + _txm_level2_module_page_table[TXM_MASTER_PAGE_TABLE_INDEX][i] = ((ULONG)_txm_module_manager_user_mode_entry & TXM_MMU_LEVEL1_MASK) | (i << TXM_MMU_LEVEL2_PAGE_SHIFT) | TTB_LEVEL2_NORMAL_CACHE; + } + + /* Enter Level 2 table in to master table. */ + _txm_ttbr1_page_table[TXM_MASTER_PAGE_TABLE_INDEX][user_mode_index] = ((ULONG)_txm_level2_module_page_table & TXM_MMU_LEVEL1_SECOND_MASK) | TXM_MMU_LEVEL1_SECOND_ATTRIBUTES; + + /* Find level 2 entry that holds _txm_module_manager_user_mode_entry. */ + user_mode_index = ((ULONG)_txm_module_manager_user_mode_entry & ~TXM_MMU_LEVEL1_MASK) >> TXM_MMU_LEVEL2_PAGE_SHIFT; + + /* Set attribute bits for the user mode entry page. */ + _txm_level2_module_page_table[TXM_MASTER_PAGE_TABLE_INDEX][user_mode_index] = (_txm_level2_module_page_table[TXM_MASTER_PAGE_TABLE_INDEX][user_mode_index] & TTB_LEVEL2_AP_CLEAR_MASK) | TTB_LEVEL2_USER_MODE_ENTRY; + + /* Enable the MMU. */ + asm volatile ("mrc p15, 0, %0, c1, c0, 0" : "=r"(cp15reg) : : ); + cp15reg |= 0x1; + asm volatile ("mcr p15, 0, %0, c1, c0, 0" : : "r"(cp15reg) : ); + + return(TX_SUCCESS); + +#else + return(TX_FEATURE_NOT_ENABLED); +#endif +} diff --git a/ports_module/cortex_a7/iar/module_manager/src/txm_module_manager_mm_register_setup.c b/ports_module/cortex_a7/iar/module_manager/src/txm_module_manager_mm_register_setup.c new file mode 100644 index 00000000..2dd195bf --- /dev/null +++ b/ports_module/cortex_a7/iar/module_manager/src/txm_module_manager_mm_register_setup.c @@ -0,0 +1,589 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + +#include "tx_api.h" +#include "txm_module.h" + + +extern TXM_MODULE_INSTANCE *_txm_asid_table[TXM_ASID_TABLE_LENGTH]; +extern ULONG _txm_level2_module_page_table[TXM_MAXIMUM_MODULES][TXM_LEVEL_2_PAGE_TABLE_ENTRIES]; +extern ULONG _txm_ttbr1_page_table[TXM_MAXIMUM_MODULES][TXM_MASTER_PAGE_TABLE_ENTRIES]; + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_inside_data_check Cortex-A7/MMU/IAR */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function determines if pointer is within the module's data or */ +/* shared memory. */ +/* */ +/* INPUT */ +/* */ +/* pointer Data pointer */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* TXM_MODULE_MANAGER_DATA_POINTER_CHECK */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +UINT _txm_module_manager_inside_data_check(ULONG pointer) +{ + +ULONG translation; + + /* ATS1CUR operation on address supplied in pointer, Stage 1 unprivileged read. */ + asm("MCR p15, 0, %0, c7, c8, 2" : : "r"(pointer) : ); + asm("ISB"); /* Ensure completion of the MCR write to CP15. */ + asm("MRC p15, 0, %0, c7, c4, 0" : "=r"(translation) : : ); /* Read result from 32-bit PAR into translation. */ + + if (translation & TXM_ADDRESS_TRANSLATION_FAULT_BIT) + { + return(TX_FALSE); + } + + return(TX_TRUE); +} + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_assign_asid Cortex-A7/MMU/IAR */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function assigns an Application Specific ID (ASID) to a */ +/* module. */ +/* */ +/* INPUT */ +/* */ +/* module_instance Pointer to module instance */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _txm_module_manager_mm_register_setup */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +UINT _txm_module_manager_assign_asid(TXM_MODULE_INSTANCE *module_instance) +{ +UINT i = 1; + + /* Find first non-zero ASID, starting at index 1. */ + while(i < TXM_ASID_TABLE_LENGTH) + { + if(_txm_asid_table[i] != 0) + { + i++; + } + else + { + module_instance -> txm_module_instance_asid = i; + _txm_asid_table[i] = module_instance; + return(TX_SUCCESS); + } + } + + return(TXM_MODULE_ASID_ERROR); +} + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_remove_asid Cortex-A7/MMU/IAR */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function removes a module from the ASID list. */ +/* */ +/* INPUT */ +/* */ +/* module_instance Pointer to module instance */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* TXM_MODULE_MANAGER_MODULE_UNLOAD */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +VOID _txm_module_manager_remove_asid(TXM_MODULE_INSTANCE *module_instance) +{ + if(module_instance -> txm_module_instance_asid) + { + _txm_asid_table[module_instance -> txm_module_instance_asid] = 0; + } +} + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_mm_register_setup Cortex-A7/MMU/IAR */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function sets up the Cortex-A7 MMU register definitions based */ +/* on the module's memory characteristics. */ +/* */ +/* INPUT */ +/* */ +/* module_instance Pointer to module instance */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _txm_module_manager_assign_asid */ +/* */ +/* CALLED BY */ +/* */ +/* TXM_MODULE_MANAGER_MODULE_SETUP */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +VOID _txm_module_manager_mm_register_setup(TXM_MODULE_INSTANCE *module_instance) +{ +#ifdef TXM_MODULE_MEMORY_PROTECTION_ENABLED + +ULONG start_address; +ULONG end_address; +ULONG mmu_l1_entries; +ULONG mmu_l2_entries = 0; +ULONG level1_index; +ULONG level2_index; +ULONG temp_index; +ULONG temp_address; +ULONG l2_address; +ULONG attributes = 0; +ULONG asid; +UINT i; + + + /* Assign an ASID to this module. */ + _txm_module_manager_assign_asid(module_instance); + + asid = module_instance -> txm_module_instance_asid; + + /* Copy master level 1 page table to module's page table. */ + for(i = 0; i < TXM_MASTER_PAGE_TABLE_ENTRIES; i++) + { + _txm_ttbr1_page_table[asid][i] = _txm_ttbr1_page_table[TXM_MASTER_PAGE_TABLE_INDEX][i]; + } + + /* Clear level 2 tables. */ + for(i = 0; i < TXM_LEVEL_2_PAGE_TABLE_ENTRIES; i++) + { + _txm_level2_module_page_table[asid + TXM_MODULE_CODE_PAGE_TABLE_START_OFFSET][i] = 0; + _txm_level2_module_page_table[asid + TXM_MODULE_CODE_PAGE_TABLE_END_OFFSET][i] = 0; + _txm_level2_module_page_table[asid + TXM_MODULE_DATA_PAGE_TABLE_START_OFFSET][i] = 0; + _txm_level2_module_page_table[asid + TXM_MODULE_DATA_PAGE_TABLE_END_OFFSET][i] = 0; + } + + /* Get code start and end addresses. */ + start_address = (ULONG)module_instance -> txm_module_instance_code_start; + /* Extend end address to end of page (TXM_MODULE_MEMORY_ALIGNMENT-1). */ + end_address = ((((ULONG)module_instance -> txm_module_instance_code_end) + TXM_MODULE_MEMORY_ALIGNMENT-1) & ~((ULONG)TXM_MODULE_MEMORY_ALIGNMENT-1)) - 1; + + /* How many level 1 table entries does code span? */ + mmu_l1_entries = (end_address >> TXM_MMU_LEVEL1_PAGE_SHIFT) - (start_address >> TXM_MMU_LEVEL1_PAGE_SHIFT) + 1; + + /* Add 1 to align. */ + end_address++; + + /* How many level 2 table entries does code need? + * 0: start and end addresses both aligned. + * 1: either start or end address aligned. + * 2: start and end addresses both not aligned. */ + if(start_address & ~TXM_MMU_LEVEL1_MASK) + { + /* If start address is not aligned, increment. */ + mmu_l2_entries++; + } + if(end_address & ~TXM_MMU_LEVEL1_MASK) + { + /* If end address is not aligned, increment. */ + mmu_l2_entries++; + } + + /* Get index into L1 table. */ + level1_index = (start_address >> TXM_MMU_LEVEL1_PAGE_SHIFT); + + /* Set up level 1 table. */ + /* Do start and end entries need level 2 pages? */ + if(mmu_l2_entries > 0) + { + /* If start_address is not aligned, we need a L2 page. */ + if(start_address & ~TXM_MMU_LEVEL1_MASK) + { + /* Is there already a pointer to an L2 page in the L1 table? If bit 0 is set, there is. */ + if(_txm_ttbr1_page_table[asid][level1_index] & 0x01) + { + /* Get L2 page address from L1 table. */ + l2_address = _txm_ttbr1_page_table[asid][level1_index] & TXM_MMU_LEVEL1_SECOND_MASK; + + /* Copy the existing L2 page into the module L2 page. */ + for(i = 0; i < TXM_LEVEL_2_PAGE_TABLE_ENTRIES; i++) + { + _txm_level2_module_page_table[asid + TXM_MODULE_CODE_PAGE_TABLE_START_OFFSET][i] = ((ULONG *) l2_address)[i] | TXM_MMU_LEVEL2_USER_ATTRIBUTE_BASE; + } + } + else + { + /* Translate attributes from L1 entry to an L2 entry. */ + attributes = (((_txm_ttbr1_page_table[asid][level1_index] & TXM_MMU_LEVEL1_ATTRIBUTE_XN_MASK) >> TXM_MMU_LEVEL1_ATTRIBUTE_XN_SHIFT) << TXM_MMU_LEVEL2_ATTRIBUTE_XN_SHIFT) | + (((_txm_ttbr1_page_table[asid][level1_index] & TXM_MMU_LEVEL1_ATTRIBUTE_B_MASK) >> TXM_MMU_LEVEL1_ATTRIBUTE_B_SHIFT) << TXM_MMU_LEVEL2_ATTRIBUTE_B_SHIFT) | + (((_txm_ttbr1_page_table[asid][level1_index] & TXM_MMU_LEVEL1_ATTRIBUTE_C_MASK) >> TXM_MMU_LEVEL1_ATTRIBUTE_C_SHIFT) << TXM_MMU_LEVEL2_ATTRIBUTE_C_SHIFT) | + (((_txm_ttbr1_page_table[asid][level1_index] & TXM_MMU_LEVEL1_ATTRIBUTE_AP_MASK) >> TXM_MMU_LEVEL1_ATTRIBUTE_AP_SHIFT) << TXM_MMU_LEVEL2_ATTRIBUTE_AP_SHIFT) | + (((_txm_ttbr1_page_table[asid][level1_index] & TXM_MMU_LEVEL1_ATTRIBUTE_TEX_MASK) >> TXM_MMU_LEVEL1_ATTRIBUTE_TEX_SHIFT) << TXM_MMU_LEVEL2_ATTRIBUTE_TEX_SHIFT) | + TXM_MMU_LEVEL2_USER_ATTRIBUTE_BASE; + + /* Build L2 page with attributes inherited from L1 entry. */ + for(i = 0; i < TXM_LEVEL_2_PAGE_TABLE_ENTRIES; i++) + { + _txm_level2_module_page_table[asid + TXM_MODULE_CODE_PAGE_TABLE_START_OFFSET][i] = ((ULONG)start_address & TXM_MMU_LEVEL1_MASK) | (i << TXM_MMU_LEVEL2_PAGE_SHIFT) | attributes; + } + } + + /* Put L2 page in L1 table. */ + _txm_ttbr1_page_table[asid][level1_index] = ((ULONG)_txm_level2_module_page_table[asid + TXM_MODULE_CODE_PAGE_TABLE_START_OFFSET] & TXM_MMU_LEVEL1_SECOND_MASK) | TXM_MMU_LEVEL1_SECOND_ATTRIBUTES; + + /* Decrement number of L1 entries remaining. */ + mmu_l1_entries--; + + /* Set up L2 start table. */ + /* Determine how many entries in L2 table. */ + if((end_address >> TXM_MMU_LEVEL1_PAGE_SHIFT) - (start_address >> TXM_MMU_LEVEL1_PAGE_SHIFT)) + { + /* End address goes to next L1 page (or beyond). */ + temp_address = ((start_address >> TXM_MMU_LEVEL1_PAGE_SHIFT) + 1) << (TXM_MMU_LEVEL1_PAGE_SHIFT); + mmu_l2_entries = (temp_address - start_address) >> TXM_MMU_LEVEL2_PAGE_SHIFT; + } + else + { + /* End address is on the same L1 page. */ + mmu_l2_entries = (end_address >> TXM_MMU_LEVEL2_PAGE_SHIFT) - (start_address >> TXM_MMU_LEVEL2_PAGE_SHIFT); + } + + /* Insert module settings into start table. */ + level2_index = ((start_address & ~TXM_MMU_LEVEL1_MASK) >> TXM_MMU_LEVEL2_PAGE_SHIFT); + for(i = 0; i < mmu_l2_entries; i++, level2_index++) + { + _txm_level2_module_page_table[asid + TXM_MODULE_CODE_PAGE_TABLE_START_OFFSET][level2_index] = ((ULONG)start_address & TXM_MMU_LEVEL1_MASK) | (level2_index << TXM_MMU_LEVEL2_PAGE_SHIFT) | TXM_MMU_LEVEL2_CODE_ATTRIBUTES; + } + + level1_index++; + } + + /* Does last entry need a level 2 page? */ + /* If end_address is not aligned, we need a L2 page. */ + if((end_address & ~TXM_MMU_LEVEL1_MASK) && (mmu_l1_entries != 0)) + { + /* Get index into L1 table. */ + temp_index = (end_address >> TXM_MMU_LEVEL1_PAGE_SHIFT); + + /* Is there already a pointer to an L2 page in the L1 table? If bit 0 is set, there is. */ + if(_txm_ttbr1_page_table[asid][temp_index] & 0x01) + { + /* Get L2 page address from L1 table. */ + l2_address = _txm_ttbr1_page_table[asid][temp_index] & TXM_MMU_LEVEL1_SECOND_MASK; + + /* Copy the existing L2 page into the module L2 page. */ + for(i = 0; i < TXM_LEVEL_2_PAGE_TABLE_ENTRIES; i++) + { + _txm_level2_module_page_table[asid + TXM_MODULE_CODE_PAGE_TABLE_END_OFFSET][i] = ((ULONG *) l2_address)[i] | TXM_MMU_LEVEL2_USER_ATTRIBUTE_BASE; + } + } + else + { + /* Translate attributes from L1 entry to an L2 entry. */ + attributes = (((_txm_ttbr1_page_table[asid][temp_index] & TXM_MMU_LEVEL1_ATTRIBUTE_XN_MASK) >> TXM_MMU_LEVEL1_ATTRIBUTE_XN_SHIFT) << TXM_MMU_LEVEL2_ATTRIBUTE_XN_SHIFT) | + (((_txm_ttbr1_page_table[asid][temp_index] & TXM_MMU_LEVEL1_ATTRIBUTE_B_MASK) >> TXM_MMU_LEVEL1_ATTRIBUTE_B_SHIFT) << TXM_MMU_LEVEL2_ATTRIBUTE_B_SHIFT) | + (((_txm_ttbr1_page_table[asid][temp_index] & TXM_MMU_LEVEL1_ATTRIBUTE_C_MASK) >> TXM_MMU_LEVEL1_ATTRIBUTE_C_SHIFT) << TXM_MMU_LEVEL2_ATTRIBUTE_C_SHIFT) | + (((_txm_ttbr1_page_table[asid][temp_index] & TXM_MMU_LEVEL1_ATTRIBUTE_AP_MASK) >> TXM_MMU_LEVEL1_ATTRIBUTE_AP_SHIFT) << TXM_MMU_LEVEL2_ATTRIBUTE_AP_SHIFT) | + (((_txm_ttbr1_page_table[asid][temp_index] & TXM_MMU_LEVEL1_ATTRIBUTE_TEX_MASK) >> TXM_MMU_LEVEL1_ATTRIBUTE_TEX_SHIFT) << TXM_MMU_LEVEL2_ATTRIBUTE_TEX_SHIFT) | + TXM_MMU_LEVEL2_USER_ATTRIBUTE_BASE; + + /* Build L2 page with attributes inherited from L1 entry. */ + for(i = 0; i < TXM_LEVEL_2_PAGE_TABLE_ENTRIES; i++) + { + _txm_level2_module_page_table[asid + TXM_MODULE_CODE_PAGE_TABLE_END_OFFSET][i] = ((ULONG)start_address & TXM_MMU_LEVEL1_MASK) | (i << TXM_MMU_LEVEL2_PAGE_SHIFT) | attributes; + } + } + + /* Put L2 page in L1 table. */ + _txm_ttbr1_page_table[asid][temp_index] = ((ULONG)_txm_level2_module_page_table[asid + TXM_MODULE_CODE_PAGE_TABLE_END_OFFSET] & TXM_MMU_LEVEL1_SECOND_MASK) | TXM_MMU_LEVEL1_SECOND_ATTRIBUTES; + + /* Decrement number of L1 entries remaining. */ + mmu_l1_entries--; + + /* Determine how many entries in L2 table. */ + mmu_l2_entries = ((end_address & ~TXM_MMU_LEVEL1_MASK) >> TXM_MMU_LEVEL2_PAGE_SHIFT); + + /* Set up L2 end table. */ + for(i = 0; i < mmu_l2_entries; i++) + { + _txm_level2_module_page_table[asid + TXM_MODULE_CODE_PAGE_TABLE_END_OFFSET][i] = ((ULONG)end_address & TXM_MMU_LEVEL1_MASK) | (i << TXM_MMU_LEVEL2_PAGE_SHIFT) | TXM_MMU_LEVEL2_CODE_ATTRIBUTES; + } + } + } + + /* Fill any L1 entries between start and end pages of module code range. */ + for(i = 0; i < mmu_l1_entries; i++, level1_index++) + { + /* Place address and attributes in table. */ + _txm_ttbr1_page_table[asid][level1_index] = (level1_index << TXM_MMU_LEVEL1_PAGE_SHIFT) | TXM_MMU_LEVEL1_CODE_ATTRIBUTES; + } + + /**************************************************************************/ + /* At this point, code protection is set up. */ + /* Data protection is set up below. */ + /**************************************************************************/ + + /* Get data start and end addresses. */ + start_address = (ULONG)module_instance -> txm_module_instance_data_start; + end_address = (ULONG)module_instance -> txm_module_instance_data_end; + + /* How many level 1 table entries does data span? */ + mmu_l1_entries = (end_address >> TXM_MMU_LEVEL1_PAGE_SHIFT) - (start_address >> TXM_MMU_LEVEL1_PAGE_SHIFT) + 1; + + /* Add 1 to align. */ + end_address++; + + /* How many level 2 table entries does data need? + * 0: start and end addresses both aligned. + * 1: either start or end address aligned. + * 2: start and end addresses both not aligned. */ + if(start_address & ~TXM_MMU_LEVEL1_MASK) + { + /* If start address is not aligned, increment. */ + mmu_l2_entries++; + } + if(end_address & ~TXM_MMU_LEVEL1_MASK) + { + /* If end address is not aligned, increment. */ + mmu_l2_entries++; + } + + /* Get index into L1 table. */ + level1_index = (start_address >> TXM_MMU_LEVEL1_PAGE_SHIFT); + + /* Set up level 1 table. */ + /* Do start and end entries need level 2 pages? */ + if(mmu_l2_entries > 0) + { + /* If start_address is not aligned, we need a L2 page. */ + if(start_address & ~TXM_MMU_LEVEL1_MASK) + { + /* Is there already a pointer to an L2 page in the L1 table? If bit 0 is set, there is. */ + if(_txm_ttbr1_page_table[asid][level1_index] & 0x01) + { + /* Get L2 page address from L1 table. */ + l2_address = _txm_ttbr1_page_table[asid][level1_index] & TXM_MMU_LEVEL1_SECOND_MASK; + + /* Copy the existing L2 page into the module L2 page. */ + for(i = 0; i < TXM_LEVEL_2_PAGE_TABLE_ENTRIES; i++) + { + _txm_level2_module_page_table[asid + TXM_MODULE_DATA_PAGE_TABLE_START_OFFSET][i] = ((ULONG *) l2_address)[i] | TXM_MMU_LEVEL2_USER_ATTRIBUTE_BASE; + } + } + else + { + /* Translate attributes from L1 entry to an L2 entry. */ + attributes = (((_txm_ttbr1_page_table[asid][level1_index] & TXM_MMU_LEVEL1_ATTRIBUTE_XN_MASK) >> TXM_MMU_LEVEL1_ATTRIBUTE_XN_SHIFT) << TXM_MMU_LEVEL2_ATTRIBUTE_XN_SHIFT) | + (((_txm_ttbr1_page_table[asid][level1_index] & TXM_MMU_LEVEL1_ATTRIBUTE_B_MASK) >> TXM_MMU_LEVEL1_ATTRIBUTE_B_SHIFT) << TXM_MMU_LEVEL2_ATTRIBUTE_B_SHIFT) | + (((_txm_ttbr1_page_table[asid][level1_index] & TXM_MMU_LEVEL1_ATTRIBUTE_C_MASK) >> TXM_MMU_LEVEL1_ATTRIBUTE_C_SHIFT) << TXM_MMU_LEVEL2_ATTRIBUTE_C_SHIFT) | + (((_txm_ttbr1_page_table[asid][level1_index] & TXM_MMU_LEVEL1_ATTRIBUTE_AP_MASK) >> TXM_MMU_LEVEL1_ATTRIBUTE_AP_SHIFT) << TXM_MMU_LEVEL2_ATTRIBUTE_AP_SHIFT) | + (((_txm_ttbr1_page_table[asid][level1_index] & TXM_MMU_LEVEL1_ATTRIBUTE_TEX_MASK) >> TXM_MMU_LEVEL1_ATTRIBUTE_TEX_SHIFT) << TXM_MMU_LEVEL2_ATTRIBUTE_TEX_SHIFT) | + TXM_MMU_LEVEL2_USER_ATTRIBUTE_BASE; + + /* Build L2 page with attributes inherited from L1 entry. */ + for(i = 0; i < TXM_LEVEL_2_PAGE_TABLE_ENTRIES; i++) + { + _txm_level2_module_page_table[asid + TXM_MODULE_DATA_PAGE_TABLE_START_OFFSET][i] = ((ULONG)start_address & TXM_MMU_LEVEL1_MASK) | (i << TXM_MMU_LEVEL2_PAGE_SHIFT) | attributes; + } + } + + /* Put L2 page in L1 table. */ + _txm_ttbr1_page_table[asid][level1_index] = ((ULONG)_txm_level2_module_page_table[asid + TXM_MODULE_DATA_PAGE_TABLE_START_OFFSET] & TXM_MMU_LEVEL1_SECOND_MASK) | TXM_MMU_LEVEL1_SECOND_ATTRIBUTES; + + /* Decrement number of L1 entries remaining. */ + mmu_l1_entries--; + + /* Set up L2 start table. */ + /* Determine how many entries in L2 table. */ + if((end_address >> TXM_MMU_LEVEL1_PAGE_SHIFT) - (start_address >> TXM_MMU_LEVEL1_PAGE_SHIFT)) + { + /* End address goes to next L1 page (or beyond). */ + temp_address = ((start_address >> TXM_MMU_LEVEL1_PAGE_SHIFT) + 1) << (TXM_MMU_LEVEL1_PAGE_SHIFT); + mmu_l2_entries = (temp_address - start_address) >> TXM_MMU_LEVEL2_PAGE_SHIFT; + } + else + { + /* End address is on the same L1 page. */ + mmu_l2_entries = (end_address >> TXM_MMU_LEVEL2_PAGE_SHIFT) - (start_address >> TXM_MMU_LEVEL2_PAGE_SHIFT); + } + + /* Insert module settings into start table. */ + level2_index = ((start_address & ~TXM_MMU_LEVEL1_MASK) >> TXM_MMU_LEVEL2_PAGE_SHIFT); + for(i = 0; i < mmu_l2_entries; i++, level2_index++) + { + _txm_level2_module_page_table[asid + TXM_MODULE_DATA_PAGE_TABLE_START_OFFSET][level2_index] = ((ULONG)start_address & TXM_MMU_LEVEL1_MASK) | (level2_index << TXM_MMU_LEVEL2_PAGE_SHIFT) | TXM_MMU_LEVEL2_DATA_ATTRIBUTES; + } + + level1_index++; + } + + /* Does last entry need a level 2 page? */ + /* If end_address is not aligned, we need a L2 page. */ + if((end_address & ~TXM_MMU_LEVEL1_MASK) && (mmu_l1_entries != 0)) + { + /* Get index into L1 table. */ + temp_index = (end_address >> TXM_MMU_LEVEL1_PAGE_SHIFT); + + /* Is there already a pointer to an L2 page in the L1 table? If bit 0 is set, there is. */ + if(_txm_ttbr1_page_table[asid][temp_index] & 0x01) + { + /* Get L2 page address from L1 table. */ + l2_address = _txm_ttbr1_page_table[asid][temp_index] & TXM_MMU_LEVEL1_SECOND_MASK; + + /* Copy the existing L2 page into the module L2 page. */ + for(i = 0; i < TXM_LEVEL_2_PAGE_TABLE_ENTRIES; i++) + { + _txm_level2_module_page_table[asid + TXM_MODULE_DATA_PAGE_TABLE_END_OFFSET][i] = ((ULONG *) l2_address)[i] | TXM_MMU_LEVEL2_USER_ATTRIBUTE_BASE; + } + } + else + { + /* Translate attributes from L1 entry to an L2 entry. */ + attributes = (((_txm_ttbr1_page_table[asid][temp_index] & TXM_MMU_LEVEL1_ATTRIBUTE_XN_MASK) >> TXM_MMU_LEVEL1_ATTRIBUTE_XN_SHIFT) << TXM_MMU_LEVEL2_ATTRIBUTE_XN_SHIFT) | + (((_txm_ttbr1_page_table[asid][temp_index] & TXM_MMU_LEVEL1_ATTRIBUTE_B_MASK) >> TXM_MMU_LEVEL1_ATTRIBUTE_B_SHIFT) << TXM_MMU_LEVEL2_ATTRIBUTE_B_SHIFT) | + (((_txm_ttbr1_page_table[asid][temp_index] & TXM_MMU_LEVEL1_ATTRIBUTE_C_MASK) >> TXM_MMU_LEVEL1_ATTRIBUTE_C_SHIFT) << TXM_MMU_LEVEL2_ATTRIBUTE_C_SHIFT) | + (((_txm_ttbr1_page_table[asid][temp_index] & TXM_MMU_LEVEL1_ATTRIBUTE_AP_MASK) >> TXM_MMU_LEVEL1_ATTRIBUTE_AP_SHIFT) << TXM_MMU_LEVEL2_ATTRIBUTE_AP_SHIFT) | + (((_txm_ttbr1_page_table[asid][temp_index] & TXM_MMU_LEVEL1_ATTRIBUTE_TEX_MASK) >> TXM_MMU_LEVEL1_ATTRIBUTE_TEX_SHIFT) << TXM_MMU_LEVEL2_ATTRIBUTE_TEX_SHIFT) | + TXM_MMU_LEVEL2_USER_ATTRIBUTE_BASE; + + /* Build L2 page with attributes inherited from L1 entry. */ + for(i = 0; i < TXM_LEVEL_2_PAGE_TABLE_ENTRIES; i++) + { + _txm_level2_module_page_table[asid + TXM_MODULE_DATA_PAGE_TABLE_END_OFFSET][i] = ((ULONG)start_address & TXM_MMU_LEVEL1_MASK) | (i << TXM_MMU_LEVEL2_PAGE_SHIFT) | attributes; + } + } + + /* Put L2 page in L1 table. */ + _txm_ttbr1_page_table[asid][temp_index] = ((ULONG)_txm_level2_module_page_table[asid + TXM_MODULE_DATA_PAGE_TABLE_END_OFFSET] & TXM_MMU_LEVEL1_SECOND_MASK) | TXM_MMU_LEVEL1_SECOND_ATTRIBUTES; + + /* Decrement number of L1 entries remaining. */ + mmu_l1_entries--; + + /* Determine how many entries in L2 table. */ + mmu_l2_entries = ((end_address & ~TXM_MMU_LEVEL1_MASK) >> TXM_MMU_LEVEL2_PAGE_SHIFT); + + /* Set up L2 end table. */ + for(i = 0; i < mmu_l2_entries; i++) + { + _txm_level2_module_page_table[asid + TXM_MODULE_DATA_PAGE_TABLE_END_OFFSET][i] = ((ULONG)end_address & TXM_MMU_LEVEL1_MASK) | (i << TXM_MMU_LEVEL2_PAGE_SHIFT) | TXM_MMU_LEVEL2_DATA_ATTRIBUTES; + } + } + } + + /* Fill any L1 entries between start and end pages of module data range. */ + for(i = 0; i < mmu_l1_entries; i++, level1_index++) + { + /* Place address and attributes in table. */ + _txm_ttbr1_page_table[asid][level1_index] = (level1_index << TXM_MMU_LEVEL1_PAGE_SHIFT) | TXM_MMU_LEVEL1_DATA_ATTRIBUTES; + } + +#endif +} diff --git a/ports_module/cortex_a7/iar/module_manager/src/txm_module_manager_thread_stack_build.s b/ports_module/cortex_a7/iar/module_manager/src/txm_module_manager_thread_stack_build.s new file mode 100644 index 00000000..46ff4ec7 --- /dev/null +++ b/ports_module/cortex_a7/iar/module_manager/src/txm_module_manager_thread_stack_build.s @@ -0,0 +1,151 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Module Manager */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ + +; +THUMB_MASK EQU 0x20 ; Thumb bit (5) of CPSR/SPSR +USR_MODE EQU 0x10 ; USR mode +SYS_MODE EQU 0x1F ; SYS mode +#ifdef TX_ENABLE_FIQ_SUPPORT +CPSR_MASK EQU 0xDF ; Mask initial CPSR, IRQ & FIQ ints enabled +#else +CPSR_MASK EQU 0x9F ; Mask initial CPSR, IRQ ints enabled +#endif + +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _txm_module_manager_thread_stack_build Cortex-A7/MMU/IAR */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* Scott Larson, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function builds a stack frame on the supplied thread's stack. */ +;/* The stack frame results in a fake interrupt return to the supplied */ +;/* function pointer. */ +;/* */ +;/* INPUT */ +;/* */ +;/* thread_ptr Pointer to thread control blk */ +;/* function_ptr Pointer to return function */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_thread_create Create thread service */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 Scott Larson Initial Version 6.1 */ +;/* */ +;/**************************************************************************/ +;VOID _txm_module_manager_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(TX_THREAD *, TXM_MODULE_INSTANCE *)) +;{ + RSEG .text:CODE:NOROOT(2) + PUBLIC _txm_module_manager_thread_stack_build + ARM +_txm_module_manager_thread_stack_build +; +; +; /* Build a fake interrupt frame. The form of the fake interrupt stack +; on the Cortex-A7 should look like the following after it is built: +; +; Stack Top: 1 Interrupt stack frame type +; CPSR Initial value for CPSR +; r0 Initial value for r0 +; r1 Initial value for r1 +; r2 Initial value for r2 +; r3 Initial value for r3 +; r4 Initial value for r4 +; r5 Initial value for r5 +; r6 Initial value for r6 +; r7 Initial value for r7 +; r8 Initial value for r8 +; r9 Initial value for r9 +; r10 Initial value for r10 +; r11 Initial value for r11 +; r12 Initial value for r12 +; lr Initial value for lr (r14) +; pc Initial value for pc (r15) +; 0 For stack backtracing +; +; Stack Bottom: (higher memory address) */ +; + LDR r2, [r0, #16] ; Pickup end of stack area + BIC r2, r2, #7 ; Ensure 8-byte alignment + SUB r2, r2, #76 ; Allocate space for the stack frame +; +; /* Actually build the stack frame. */ +; + MOV r3, #1 ; Build interrupt stack type + STR r3, [r2, #0] ; Store stack type + STR r0, [r2, #8] ; Store initial r0 (thread pointer) + LDR r3, [r0, #8] ; Pickup thread info pointer (it's in the stack pointer location right now) + STR r3, [r2, #12] ; Store initial r1 + LDR r3, [r3, #8] ; Pickup data base register + STR r3, [r2, #44] ; Store initial r9 + MOV r3, #0 ; Build initial register value + STR r3, [r2, #16] ; Store initial r2 + STR r3, [r2, #20] ; Store initial r3 + STR r3, [r2, #24] ; Store initial r4 + STR r3, [r2, #28] ; Store initial r5 + STR r3, [r2, #32] ; Store initial r6 + STR r3, [r2, #36] ; Store initial r7 + STR r3, [r2, #40] ; Store initial r8 + LDR r3, [r0, #12] ; Pickup stack starting address + STR r3, [r2, #48] ; Store initial r10 (sl) + MOV r3, #0 ; Build initial register value + STR r3, [r2, #52] ; Store initial r11 + STR r3, [r2, #56] ; Store initial r12 + STR r3, [r2, #60] ; Store initial lr + STR r1, [r2, #64] ; Store initial pc + STR r3, [r2, #68] ; 0 for back-trace + MRS r3, CPSR ; Pickup CPSR + BIC r3, r3, #CPSR_MASK ; Mask mode bits of CPSR + TST r1, #1 ; Test if THUMB bit set in initial PC + ORRNE r3, r3, #THUMB_MASK ; Set T bit if set + LDR r1, [r0, #156] ; Load tx_thread_module_current_user_mode + TST r1, #1 ; Test if the flag is set + ORREQ r3, r3, #SYS_MODE ; Flag not set: Build CPSR, SYS mode, IRQ enabled + ORRNE r3, r3, #USR_MODE ; Flag set: Build CPSR, USR mode, IRQ enabled + STR r3, [r2, #4] ; Store initial CPSR +; +; /* Setup stack pointer. */ +; thread_ptr -> tx_thread_stack_ptr = r2; +; + STR r2, [r0, #8] ; Save stack pointer in thread's control block + BX lr ; Return to caller +;} + END + diff --git a/ports_module/cortex_a7/iar/module_manager/src/txm_module_manager_user_mode_entry.s b/ports_module/cortex_a7/iar/module_manager/src/txm_module_manager_user_mode_entry.s new file mode 100644 index 00000000..501c79bb --- /dev/null +++ b/ports_module/cortex_a7/iar/module_manager/src/txm_module_manager_user_mode_entry.s @@ -0,0 +1,96 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Module Manager */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; + EXTERN _tx_thread_current_ptr + EXTERN _txm_module_manager_kernel_dispatch + + +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* tx Cortex-A7/MMU/IAR */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* Scott Larson, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function allows modules to enter kernel mode. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* SVC 1 Enter kernel mode */ +;/* SVC 2 Exit kernel mode */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Modules in user mode */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 Scott Larson Initial Version 6.1 */ +;/* */ +;/**************************************************************************/ + RSEG .text:CODE:NOROOT(2) + PUBLIC _txm_module_manager_user_mode_entry + ARM +_txm_module_manager_user_mode_entry + + PUBLIC _txm_system_mode_enter + ARM +_txm_system_mode_enter + SVC 1 ; Get out of user mode +_txm_module_priv + ; At this point, we are in system mode. + ; Save LR (and r3 for 8 byte aligned stack) and call the kernel dispatch function. + PUSH {r3, lr} + BL _txm_module_manager_kernel_dispatch + POP {r3, lr} + + PUBLIC _txm_system_mode_exit + ARM +_txm_system_mode_exit + ; Trap to restore user mode while inside of ThreadX + SVC 2 + + BX lr ; Return to the caller + NOP + NOP + + ; Fill up 4kB page. + SECTION page_align:CONST:ROOT(2) + +_txm_module_manager_user_mode_end + + END |