diff options
| author | Yuxin Zhou <[email protected]> | 2021-10-14 00:51:26 +0000 |
|---|---|---|
| committer | Yuxin Zhou <[email protected]> | 2021-10-14 00:51:26 +0000 |
| commit | 1af8404c54f9c8d3caa2ac3523c2a5f014aecb1c (patch) | |
| tree | 93e4f4d64ec8c21c01b77f19b8e7326e85227e3d /ports_module | |
| parent | 215df45d4b59d4ce8606a88f566d1d426e64a84c (diff) | |
Release 6.1.9
Diffstat (limited to 'ports_module')
347 files changed, 12277 insertions, 5651 deletions
diff --git a/ports_module/cortex_a35/ac6/inc/tx_port.h b/ports_module/cortex_a35/ac6/inc/tx_port.h index ae951986..f772c52c 100644 --- a/ports_module/cortex_a35/ac6/inc/tx_port.h +++ b/ports_module/cortex_a35/ac6/inc/tx_port.h @@ -387,7 +387,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Modules Cortex-A35/AC6 Version 6.1.3 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Modules Cortex-A35/AC6 Version 6.1.9 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_module/cortex_a35/ac6/inc/txm_module_port.h b/ports_module/cortex_a35/ac6/inc/txm_module_port.h index adbef2de..e74c9c3f 100644 --- a/ports_module/cortex_a35/ac6/inc/txm_module_port.h +++ b/ports_module/cortex_a35/ac6/inc/txm_module_port.h @@ -279,6 +279,6 @@ ALIGN_TYPE _txm_module_manager_port_dispatch(TXM_MODULE_INSTANCE *module_instanc #define TXM_MODULE_MANAGER_VERSION_ID \ CHAR _txm_module_manager_version_id[] = \ - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-A35/AC6 Version 6.1.3 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-A35/AC6 Version 6.1.9 *"; #endif diff --git a/ports_module/cortex_a35/gnu/inc/tx_port.h b/ports_module/cortex_a35/gnu/inc/tx_port.h index e01f26d1..0a25293e 100644 --- a/ports_module/cortex_a35/gnu/inc/tx_port.h +++ b/ports_module/cortex_a35/gnu/inc/tx_port.h @@ -387,7 +387,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Modules Cortex-A35/GNU Version 6.1.3 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Modules Cortex-A35/GNU Version 6.1.9 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_module/cortex_a35/gnu/inc/txm_module_port.h b/ports_module/cortex_a35/gnu/inc/txm_module_port.h index ea6cf2fc..c594439c 100644 --- a/ports_module/cortex_a35/gnu/inc/txm_module_port.h +++ b/ports_module/cortex_a35/gnu/inc/txm_module_port.h @@ -279,6 +279,6 @@ ALIGN_TYPE _txm_module_manager_port_dispatch(TXM_MODULE_INSTANCE *module_instanc #define TXM_MODULE_MANAGER_VERSION_ID \ CHAR _txm_module_manager_version_id[] = \ - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-A35/GNU Version 6.1.3 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-A35/GNU Version 6.1.9 *"; #endif diff --git a/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx/.cproject b/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx/.cproject index b109c4c5..40b668c4 100644 --- a/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx/.cproject +++ b/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx/.cproject @@ -31,7 +31,7 @@ <option id="com.arm.toolchain.v6.base.options.target.cpu_fpu.1337922098" superClass="com.arm.toolchain.v6.base.options.target.cpu_fpu" useByScannerDiscovery="false" value="Cortex-A35.AArch64.ARMv8.Neon.Crypto" valueType="string"/> - <option id="com.arm.toolchain.v6.base.options.debug.level.1596377417" superClass="com.arm.toolchain.v6.base.options.debug.level" value="com.arm.tool.c.compiler.v6.base.options.debug.level.std" valueType="enumerated"/> + <option id="com.arm.toolchain.v6.base.options.debug.level.1596377417" name="Debug Level" superClass="com.arm.toolchain.v6.base.options.debug.level" value="com.arm.tool.c.compiler.v6.base.options.debug.level.std" valueType="enumerated"/> <targetPlatform id="com.arm.toolchain.v6.base.var.arm_compiler_6-6.1592753597.2060144338" name=""/> diff --git a/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx/sample_threadx.c b/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx/sample_threadx.c index 139a848c..9d1733a5 100644 --- a/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx/sample_threadx.c +++ b/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx/sample_threadx.c @@ -1,5 +1,5 @@ /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight - threads of different priorities, using a message queue, semaphore, mutex, event flags group, + threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ #include "tx_api.h" @@ -104,41 +104,41 @@ CHAR *pointer = TX_NULL; tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create the main thread. */ - tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 1. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 1 and 2. These threads pass information through a ThreadX + /* Create threads 1 and 2. These threads pass information through a ThreadX message queue. It is also interesting to note that these threads have a time slice. */ tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, DEMO_STACK_SIZE, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); - + /* Allocate the stack for thread 2. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, - pointer, DEMO_STACK_SIZE, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 3. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. An interesting thing here is that both threads share the same instruction area. */ - tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 4. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 5. */ @@ -146,23 +146,23 @@ CHAR *pointer = TX_NULL; /* Create thread 5. This thread simply pends on an event flag which will be set by thread_0. */ - tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 6. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ - tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 7. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the message queue. */ @@ -264,11 +264,11 @@ UINT status; /* Retrieve a message from the queue. */ status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); - /* Check completion status and make sure the message is what we + /* Check completion status and make sure the message is what we expected. */ if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) break; - + /* Otherwise, all is okay. Increment the received message count. */ thread_2_messages_received++; } @@ -327,7 +327,7 @@ ULONG actual_flags; thread_5_counter++; /* Wait for event flag 0. */ - status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, &actual_flags, TX_WAIT_FOREVER); /* Check status. */ @@ -380,7 +380,7 @@ UINT status; if (status != TX_SUCCESS) break; - /* Release the mutex again. This will actually + /* Release the mutex again. This will actually release ownership since it was obtained twice. */ status = tx_mutex_put(&mutex_0); diff --git a/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx/startup.S b/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx/startup.S index eea65315..a66c56e2 100644 --- a/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx/startup.S +++ b/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx/startup.S @@ -328,7 +328,7 @@ el1_entry_aarch64: // // Cortex-A processors automatically invalidate their caches on reset // (unless suppressed with the DBGL1RSTDISABLE or L2RSTDISABLE pins). - // It is therefore not necessary for software to invalidate the caches + // It is therefore not necessary for software to invalidate the caches // on startup, however, this is done here in case of a warm reset. bl InvalidateUDCaches tlbi VMALLE1 @@ -800,4 +800,4 @@ __user_setup_stackheap: ADRP X0, Image$$ARM_LIB_HEAP$$ZI$$Base ADRP X2, Image$$ARM_LIB_HEAP$$ZI$$Limit RET - + diff --git a/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx_module/sample_threadx_module.c b/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx_module/sample_threadx_module.c index a974cdf1..e94ac221 100644 --- a/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx_module/sample_threadx_module.c +++ b/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx_module/sample_threadx_module.c @@ -1,5 +1,5 @@ -/* This is a small demo of the high-performance ThreadX kernel running as a module. It includes - examples of eight threads of different priorities, using a message queue, semaphore, mutex, +/* This is a small demo of the high-performance ThreadX kernel running as a module. It includes + examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ /* Specify that this is a module! */ @@ -20,7 +20,7 @@ #define DEMO_QUEUE_SIZE 100 -/* Define the pool space in the bss section of the module. ULONG is used to +/* Define the pool space in the bss section of the module. ULONG is used to get the word alignment. */ ULONG demo_module_pool_space[DEMO_BYTE_POOL_SIZE / sizeof(ULONG)]; @@ -103,7 +103,7 @@ CHAR *pointer; /* Allocate all the objects. In MMU mode, modules cannot allocate control blocks within - their own memory area so they cannot corrupt the resident portion of ThreadX by overwriting + their own memory area so they cannot corrupt the resident portion of ThreadX by overwriting the control block(s). */ status = txm_module_object_allocate((void*)&thread_0, sizeof(TX_THREAD)); while (status != TX_SUCCESS); @@ -133,7 +133,7 @@ CHAR *pointer; while (status != TX_SUCCESS); status = txm_module_object_allocate((void*)&block_pool_0, sizeof(TX_BLOCK_POOL)); while (status != TX_SUCCESS); - + /* Create a byte memory pool from which to allocate the thread stacks. */ status = tx_byte_pool_create(byte_pool_0, "module byte pool 0", demo_module_pool_space, DEMO_BYTE_POOL_SIZE); @@ -193,7 +193,7 @@ CHAR *pointer; /* Create the main thread. */ status = tx_thread_create(thread_0, "module thread 0", thread_0_entry, 0, - pointer, DEMO_STACK_SIZE, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); while (status != TX_SUCCESS); @@ -201,11 +201,11 @@ CHAR *pointer; status = tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); while (status != TX_SUCCESS); - /* Create threads 1 and 2. These threads pass information through a ThreadX + /* Create threads 1 and 2. These threads pass information through a ThreadX message queue. It is also interesting to note that these threads have a time slice. */ status = tx_thread_create(thread_1, "module thread 1", thread_1_entry, 1, - pointer, DEMO_STACK_SIZE, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); while (status != TX_SUCCESS); @@ -214,7 +214,7 @@ CHAR *pointer; while (status != TX_SUCCESS); status = tx_thread_create(thread_2, "module thread 2", thread_2_entry, 2, - pointer, DEMO_STACK_SIZE, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); while (status != TX_SUCCESS); @@ -222,10 +222,10 @@ CHAR *pointer; status = tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); while (status != TX_SUCCESS); - /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. An interesting thing here is that both threads share the same instruction area. */ status = tx_thread_create(thread_3, "module thread 3", thread_3_and_4_entry, 3, - pointer, DEMO_STACK_SIZE, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); while (status != TX_SUCCESS); @@ -234,7 +234,7 @@ CHAR *pointer; while (status != TX_SUCCESS); status = tx_thread_create(thread_4, "module thread 4", thread_3_and_4_entry, 4, - pointer, DEMO_STACK_SIZE, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); while (status != TX_SUCCESS); @@ -245,7 +245,7 @@ CHAR *pointer; /* Create thread 5. This thread simply pends on an event flag which will be set by thread_0. */ status = tx_thread_create(thread_5, "module thread 5", thread_5_entry, 5, - pointer, DEMO_STACK_SIZE, + pointer, DEMO_STACK_SIZE, 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); while (status != TX_SUCCESS); @@ -255,7 +255,7 @@ CHAR *pointer; /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ status = tx_thread_create(thread_6, "module thread 6", thread_6_and_7_entry, 6, - pointer, DEMO_STACK_SIZE, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); while (status != TX_SUCCESS); @@ -264,7 +264,7 @@ CHAR *pointer; while (status != TX_SUCCESS); status = tx_thread_create(thread_7, "module thread 7", thread_6_and_7_entry, 7, - pointer, DEMO_STACK_SIZE, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); while (status != TX_SUCCESS); } @@ -276,7 +276,7 @@ void thread_0_entry(ULONG thread_input) { UINT status; - + /* This thread simply sits in while-forever-sleep loop. */ while(1) { @@ -286,7 +286,7 @@ UINT status; /* Sleep for 10 ticks. */ tx_thread_sleep(10); - + /* Set event flag 0 to wakeup thread 5. */ status = tx_event_flags_set(event_flags_0, 0x1, TX_OR); @@ -338,11 +338,11 @@ UINT status; /* Retrieve a message from the queue. */ status = tx_queue_receive(queue_0, &received_message, TX_WAIT_FOREVER); - /* Check completion status and make sure the message is what we + /* Check completion status and make sure the message is what we expected. */ if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) break; - + /* Otherwise, all is okay. Increment the received message count. */ thread_2_messages_received++; } @@ -401,7 +401,7 @@ ULONG actual_flags; thread_5_counter++; /* Wait for event flag 0. */ - status = tx_event_flags_get(event_flags_0, 0x1, TX_OR_CLEAR, + status = tx_event_flags_get(event_flags_0, 0x1, TX_OR_CLEAR, &actual_flags, TX_WAIT_FOREVER); /* Check status. */ @@ -454,7 +454,7 @@ UINT status; if (status != TX_SUCCESS) break; - /* Release the mutex again. This will actually + /* Release the mutex again. This will actually release ownership since it was obtained twice. */ status = tx_mutex_put(mutex_0); diff --git a/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx_module/txm_module_preamble.S b/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx_module/txm_module_preamble.S index f05656c3..ad75e134 100644 --- a/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx_module/txm_module_preamble.S +++ b/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx_module/txm_module_preamble.S @@ -1,7 +1,7 @@ .text .align 4 .section Init - + // External references .global _txm_module_thread_shell_entry .global _txm_module_callback_request_thread_entry diff --git a/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx_module_manager/.cproject b/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx_module_manager/.cproject index 1eba821f..7ff6378d 100644 --- a/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx_module_manager/.cproject +++ b/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx_module_manager/.cproject @@ -103,7 +103,7 @@ </option> - <option id="com.arm.tool.assembler.v6.base.option.force.preproc.70495432" superClass="com.arm.tool.assembler.v6.base.option.force.preproc" useByScannerDiscovery="false" value="true" valueType="boolean"/> + <option id="com.arm.tool.assembler.v6.base.option.force.preproc.70495432" name="Preprocess input files (-x assembler-with-cpp)" superClass="com.arm.tool.assembler.v6.base.option.force.preproc" useByScannerDiscovery="false" value="true" valueType="boolean"/> <inputType id="com.arm.tool.assembler.v6.base.input.1024953339" superClass="com.arm.tool.assembler.v6.base.input"/> diff --git a/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager.c b/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager.c index c7296646..c0772002 100644 --- a/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager.c +++ b/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager.c @@ -115,7 +115,7 @@ void module_manager_entry(ULONG thread_input) /* Load the module with absolute address linkage, in this example it is placed there by the multiple image download. */ txm_module_manager_absolute_load(&my_module, "my module", (void *) MODULE_CODE); - + /* Start the module. */ txm_module_manager_start(&my_module); @@ -127,10 +127,10 @@ void module_manager_entry(ULONG thread_input) tx_thread_sleep(10); } } - + /* Stop the module. */ txm_module_manager_stop(&my_module); - + /* Unload the module. */ txm_module_manager_unload(&my_module); @@ -139,11 +139,11 @@ void module_manager_entry(ULONG thread_input) /* Start the module again. */ txm_module_manager_start(&my_module); - + /* Now just spin... */ while(1) { - + tx_thread_sleep(10); } } diff --git a/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx_module_manager/startup.S b/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx_module_manager/startup.S index eea65315..a66c56e2 100644 --- a/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx_module_manager/startup.S +++ b/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx_module_manager/startup.S @@ -328,7 +328,7 @@ el1_entry_aarch64: // // Cortex-A processors automatically invalidate their caches on reset // (unless suppressed with the DBGL1RSTDISABLE or L2RSTDISABLE pins). - // It is therefore not necessary for software to invalidate the caches + // It is therefore not necessary for software to invalidate the caches // on startup, however, this is done here in case of a warm reset. bl InvalidateUDCaches tlbi VMALLE1 @@ -800,4 +800,4 @@ __user_setup_stackheap: ADRP X0, Image$$ARM_LIB_HEAP$$ZI$$Base ADRP X2, Image$$ARM_LIB_HEAP$$ZI$$Limit RET - + diff --git a/ports_module/cortex_a35_smp/ac6/example_build/tx/.cproject b/ports_module/cortex_a35_smp/ac6/example_build/tx/.cproject index e31673c3..b5457c00 100644 --- a/ports_module/cortex_a35_smp/ac6/example_build/tx/.cproject +++ b/ports_module/cortex_a35_smp/ac6/example_build/tx/.cproject @@ -200,78 +200,6 @@ <storageModule moduleId="org.eclipse.cdt.core.externalSettings"/> </cconfiguration> - - <cconfiguration id="com.arm.eclipse.build.config.v6.lib.release.base.597173224"> - - <storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.arm.eclipse.build.config.v6.lib.release.base.597173224" moduleId="org.eclipse.cdt.core.settings" name="Release"> - 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Lamie Modified comment(s), added */ +/* symbol ULONG64_DEFINED, */ +/* resulting in version 6.1.9 */ /* */ /**************************************************************************/ @@ -152,7 +155,7 @@ typedef unsigned int ULONG; typedef unsigned long long ULONG64; typedef short SHORT; typedef unsigned short USHORT; - +#define ULONG64_DEFINED /* Override the alignment type to use 64-bit alignment and storage for pointers. */ @@ -441,7 +444,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Modules Cortex-A35-SMP/AC6 Version 6.1.3 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Modules Cortex-A35-SMP/AC6 Version 6.1.9 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_module/cortex_a35_smp/ac6/inc/txm_module_port.h b/ports_module/cortex_a35_smp/ac6/inc/txm_module_port.h index 84d87ace..234510b8 100644 --- a/ports_module/cortex_a35_smp/ac6/inc/txm_module_port.h +++ b/ports_module/cortex_a35_smp/ac6/inc/txm_module_port.h @@ -274,6 +274,6 @@ ALIGN_TYPE _txm_module_manager_port_dispatch(TXM_MODULE_INSTANCE *module_instanc #define TXM_MODULE_MANAGER_VERSION_ID \ CHAR _txm_module_manager_version_id[] = \ - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-A35/AC6 Version 6.1.3 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-A35/AC6 Version 6.1.9 *"; #endif diff --git a/ports_module/cortex_a35_smp/ac6/module_lib/src/txm_module_thread_shell_entry.c b/ports_module/cortex_a35_smp/ac6/module_lib/src/txm_module_thread_shell_entry.c index 6153e2f7..3c5e7881 100644 --- a/ports_module/cortex_a35_smp/ac6/module_lib/src/txm_module_thread_shell_entry.c +++ b/ports_module/cortex_a35_smp/ac6/module_lib/src/txm_module_thread_shell_entry.c @@ -121,7 +121,7 @@ VOID (*entry_exit_notify)(TX_THREAD *notify_thread_ptr, UINT type); An error here typically indicates the resident portion of _tx_thread_schedule is not supporting the trap to obtain the function pointer. */ } - + /* Resume the module's callback thread, already created in the manager. */ _txe_thread_resume(thread_info -> txm_module_thread_entry_info_callback_request_thread); } diff --git a/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_smp_core_get.S b/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_smp_core_get.S index 66532220..066f5cb1 100644 --- a/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_smp_core_get.S +++ b/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_smp_core_get.S @@ -28,7 +28,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_smp_core_get Cortex-A35-SMP/AC6 */ -/* 6.1 */ +/* 6.1.9 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -58,17 +58,28 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 10-15-2021 Andres Mlinar Updated comments, */ +/* added ARMv8.2-A support, */ +/* resulting in version 6.1.9 */ /* */ /**************************************************************************/ .global _tx_thread_smp_core_get .type _tx_thread_smp_core_get, @function _tx_thread_smp_core_get: MRS x0, MPIDR_EL1 // Pickup the core ID +#ifdef TX_ARMV8_2 +#if TX_THREAD_SMP_CLUSTERS > 1 + UBFX x1, x0, #16, #8 // Isolate cluster ID +#endif + UBFX x0, x0, #8, #8 // Isolate core ID +#else #if TX_THREAD_SMP_CLUSTERS > 1 UBFX x1, x0, #8, #8 // Isolate cluster ID #endif UBFX x0, x0, #0, #8 // Isolate core ID +#endif #if TX_THREAD_SMP_CLUSTERS > 1 ADDS x0, x0, x1, LSL #2 // Calculate CPU ID #endif RET + diff --git a/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_smp_protect.S b/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_smp_protect.S index a5070681..92c1702b 100644 --- a/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_smp_protect.S +++ b/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_smp_protect.S @@ -32,7 +32,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_smp_protect Cortex-A35-SMP/AC6 */ -/* 6.1 */ +/* 6.1.9 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -64,6 +64,10 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 10-15-2021 Andres Mlinar Updated comments, */ +/* added ARMv8.2-A support, */ +/* improved SMP code, */ +/* resulting in version 6.1.9 */ /* */ /**************************************************************************/ .global _tx_thread_smp_protect @@ -78,10 +82,17 @@ _tx_thread_smp_protect: /* Pickup the CPU ID. */ MRS x1, MPIDR_EL1 // Pickup the core ID +#ifdef TX_ARMV8_2 +#if TX_THREAD_SMP_CLUSTERS > 1 + UBFX x7, x1, #16, #8 // Isolate cluster ID +#endif + UBFX x1, x1, #8, #8 // Isolate core ID +#else #if TX_THREAD_SMP_CLUSTERS > 1 UBFX x7, x1, #8, #8 // Isolate cluster ID #endif UBFX x1, x1, #0, #8 // Isolate core ID +#endif #if TX_THREAD_SMP_CLUSTERS > 1 ADDS x1, x1, x7, LSL #2 // Calculate CPU ID #endif @@ -163,7 +174,7 @@ _list_not_empty: // if (_tx_thread_smp_protection.tx_thread_smp_protect_in_force == 0) // { - LDR w3, [x2, #0] // Pickup the protection flag + LDAXR w3, [x2, #0] // Pickup the protection flag CMP w3, #0 BNE _start_waiting // No, protection not available @@ -171,7 +182,9 @@ _list_not_empty: // _tx_thread_smp_protection.tx_thread_smp_protect_in_force = 1; MOV w3, #1 // Build lock value - STR w3, [x2, #0] // Store lock value + STXR w4, w3, [x2, #0] // Attempt to get the protection + CMP w4, #0 + BNE _start_waiting // Did it fail? DMB ISH // /* Got the lock. */ @@ -217,7 +230,7 @@ _already_in_list0: /* Restore interrupts. */ MSR DAIF, x0 // Restore interrupts - ISB // + ISB // #ifdef TX_ENABLE_WFE WFE // Go into standby #endif @@ -236,10 +249,17 @@ _try_to_get_lock: /* Pickup the CPU ID. */ MRS x1, MPIDR_EL1 // Pickup the core ID +#ifdef TX_ARMV8_2 +#if TX_THREAD_SMP_CLUSTERS > 1 + UBFX x7, x1, #16, #8 // Isolate cluster ID +#endif + UBFX x1, x1, #8, #8 // Isolate core ID +#else #if TX_THREAD_SMP_CLUSTERS > 1 UBFX x7, x1, #8, #8 // Isolate cluster ID #endif UBFX x1, x1, #0, #8 // Isolate core ID +#endif #if TX_THREAD_SMP_CLUSTERS > 1 ADDS x1, x1, x7, LSL #2 // Calculate CPU ID #endif @@ -257,7 +277,7 @@ _try_to_get_lock: /* Are we at the front of the list? */ // if (this_core == _tx_thread_smp_protect_wait_list[_tx_thread_smp_protect_wait_list_head]) - // {/ + // { LDR x3, =_tx_thread_smp_protect_wait_list_head // Get the address of the head LDR w3, [x3] // Get the value of the head @@ -271,7 +291,7 @@ _try_to_get_lock: // if (_tx_thread_smp_protection.tx_thread_smp_protect_in_force == 0) // { - LDR w3, [x2, #0] // Pickup the protection flag + LDAXR w3, [x2, #0] // Pickup the protection flag CMP w3, #0 BNE _did_not_get_lock // No, protection not available @@ -279,7 +299,9 @@ _try_to_get_lock: // _tx_thread_smp_protection.tx_thread_smp_protect_in_force = 1; MOV w3, #1 // Build lock value - STR w3, [x2, #0] // Store lock value + STXR w4, w3, [x2, #0] // Attempt to get the protection + CMP w4, #0 + BNE _did_not_get_lock // Did it fail? DMB ISH // /* Got the lock. */ @@ -328,7 +350,7 @@ _already_in_list1: /* Restore interrupts and try again. */ MSR DAIF, x0 // Restore interrupts - ISB // + ISB // #ifdef TX_ENABLE_WFE WFE // Go into standby #endif @@ -349,4 +371,3 @@ _got_lock_after_waiting: _return: RET - diff --git a/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_smp_protection_wait_list_macros.h b/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_smp_protection_wait_list_macros.h index 5c33d940..c56c8d38 100644 --- a/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_smp_protection_wait_list_macros.h +++ b/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_smp_protection_wait_list_macros.h @@ -23,12 +23,12 @@ .macro _tx_thread_smp_protect_lock_got /* Set the currently owned core. */ - /* _tx_thread_smp_protection.tx_thread_smp_protect_core = this_core; */ + // _tx_thread_smp_protection.tx_thread_smp_protect_core = this_core; STR w1, [x2, #4] // Store this core /* Increment the protection count. */ - /* _tx_thread_smp_protection.tx_thread_smp_protect_count++; */ + // _tx_thread_smp_protection.tx_thread_smp_protect_count++; LDR w3, [x2, #8] // Pickup ownership count ADD w3, w3, #1 // Increment ownership count @@ -40,7 +40,7 @@ .macro _tx_thread_smp_protect_remove_from_front_of_list /* Remove ourselves from the list. */ - /* _tx_thread_smp_protect_wait_list[_tx_thread_smp_protect_wait_list_head++] = 0xFFFFFFFF; */ + // _tx_thread_smp_protect_wait_list[_tx_thread_smp_protect_wait_list_head++] = 0xFFFFFFFF; MOV w3, #0xFFFFFFFF // Build the invalid core value LDR x4, =_tx_thread_smp_protect_wait_list_head // Get the address of the head @@ -50,53 +50,55 @@ ADD w5, w5, #1 // Increment the head /* Did we wrap? */ - /* if (_tx_thread_smp_protect_wait_list_head == TX_THREAD_SMP_MAX_CORES + 1) - { */ + // if (_tx_thread_smp_protect_wait_list_head == TX_THREAD_SMP_MAX_CORES + 1) + // { LDR x3, =_tx_thread_smp_protect_wait_list_size // Load address of core list size LDR w3, [x3] // Load the max cores value CMP w5, w3 // Compare the head to it BNE _store_new_head\@ // Are we at the max? - /* _tx_thread_smp_protect_wait_list_head = 0; */ + // _tx_thread_smp_protect_wait_list_head = 0; EOR w5, w5, w5 // We're at the max. Set it to zero - /* } */ + // } _store_new_head\@: STR w5, [x4] // Store the new head /* We have the lock! */ - /* return; */ + DMB ISH // Ensure write to protection finishes + + // return; .endm .macro _tx_thread_smp_protect_wait_list_lock_get -/* VOID _tx_thread_smp_protect_wait_list_lock_get() -{ */ +// VOID _tx_thread_smp_protect_wait_list_lock_get() +// { /* We do this until we have the lock. */ - /* while (1) - { */ + // while (1) + // { _tx_thread_smp_protect_wait_list_lock_get__try_to_get_lock\@: - /* Is the list lock available? */ - /* _tx_thread_smp_protect_wait_list_lock_protect_in_force = load_exclusive(&_tx_thread_smp_protect_wait_list_lock_protect_in_force); */ + // Is the list lock available? */ + // _tx_thread_smp_protect_wait_list_lock_protect_in_force = load_exclusive(&_tx_thread_smp_protect_wait_list_lock_protect_in_force); LDR x1, =_tx_thread_smp_protect_wait_list_lock_protect_in_force LDAXR w2, [x1] // Pickup the protection flag - /* if (protect_in_force == 0) - { */ + // if (protect_in_force == 0) + // { CMP w2, #0 BNE _tx_thread_smp_protect_wait_list_lock_get__try_to_get_lock\@ // No, protection not available /* Try to get the list. */ - /* int status = store_exclusive(&_tx_thread_smp_protect_wait_list_lock_protect_in_force, 1); */ + // int status = store_exclusive(&_tx_thread_smp_protect_wait_list_lock_protect_in_force, 1); MOV w2, #1 // Build lock value STXR w3, w2, [x1] // Attempt to get the protection @@ -107,17 +109,17 @@ _tx_thread_smp_protect_wait_list_lock_get__try_to_get_lock\@: BNE _tx_thread_smp_protect_wait_list_lock_get__try_to_get_lock\@ // Did it fail? If so, try again. /* We have the lock! */ - /* return; */ + // return; .endm .macro _tx_thread_smp_protect_wait_list_add -/* VOID _tx_thread_smp_protect_wait_list_add(UINT new_core) -{ */ +// VOID _tx_thread_smp_protect_wait_list_add(UINT new_core) +// { /* We're about to modify the list, so get the list lock. */ - /* _tx_thread_smp_protect_wait_list_lock_get(); */ + // _tx_thread_smp_protect_wait_list_lock_get(); STP x1, x2, [sp, #-16]! // Save registers we'll be using @@ -126,7 +128,7 @@ _tx_thread_smp_protect_wait_list_lock_get__try_to_get_lock\@: LDP x1, x2, [sp], #16 /* Add this core. */ - /* _tx_thread_smp_protect_wait_list[_tx_thread_smp_protect_wait_list_tail++] = new_core; */ + // _tx_thread_smp_protect_wait_list[_tx_thread_smp_protect_wait_list_tail++] = new_core; LDR x3, =_tx_thread_smp_protect_wait_list_tail // Get the address of the tail LDR w4, [x3] // Get the value of tail @@ -135,64 +137,66 @@ _tx_thread_smp_protect_wait_list_lock_get__try_to_get_lock\@: ADD w4, w4, #1 // Increment the tail /* Did we wrap? */ - /* if (_tx_thread_smp_protect_wait_list_tail == _tx_thread_smp_protect_wait_list_size) - { */ + // if (_tx_thread_smp_protect_wait_list_tail == _tx_thread_smp_protect_wait_list_size) + // { LDR x5, =_tx_thread_smp_protect_wait_list_size // Load max cores address LDR w5, [x5] // Load max cores value CMP w4, w5 // Compare max cores to tail BNE _tx_thread_smp_protect_wait_list_add__no_wrap\@ // Did we wrap? - /* _tx_thread_smp_protect_wait_list_tail = 0; */ + // _tx_thread_smp_protect_wait_list_tail = 0; MOV w4, #0 - /* } */ + // } _tx_thread_smp_protect_wait_list_add__no_wrap\@: STR w4, [x3] // Store the new tail value. + DMB ISH // Ensure that accesses to shared resource have completed /* Release the list lock. */ - /* _tx_thread_smp_protect_wait_list_lock_protect_in_force = 0; */ + // _tx_thread_smp_protect_wait_list_lock_protect_in_force = 0; MOV w3, #0 // Build lock value LDR x4, =_tx_thread_smp_protect_wait_list_lock_protect_in_force STR w3, [x4] // Store the new value + DMB ISH // Ensure write to protection finishes .endm .macro _tx_thread_smp_protect_wait_list_remove -/* VOID _tx_thread_smp_protect_wait_list_remove(UINT core) -{ */ +// VOID _tx_thread_smp_protect_wait_list_remove(UINT core) +// { /* Get the core index. */ - /* UINT core_index; - for (core_index = 0;; core_index++) */ + // UINT core_index; + // for (core_index = 0;; core_index++) EOR w4, w4, w4 // Clear for 'core_index' LDR x2, =_tx_thread_smp_protect_wait_list // Get the address of the list - /* { */ + // { _tx_thread_smp_protect_wait_list_remove__check_cur_core\@: /* Is this the core? */ - /* if (_tx_thread_smp_protect_wait_list[core_index] == core) - { - break; */ + // if (_tx_thread_smp_protect_wait_list[core_index] == core) + // { + // break; LDR w3, [x2, x4, LSL #2] // Get the value at the current index CMP w3, w8 // Did we find the core? BEQ _tx_thread_smp_protect_wait_list_remove__found_core\@ - /* } */ + // } ADD w4, w4, #1 // Increment cur index B _tx_thread_smp_protect_wait_list_remove__check_cur_core\@ // Restart the loop - /* } */ + // } _tx_thread_smp_protect_wait_list_remove__found_core\@: @@ -200,15 +204,15 @@ _tx_thread_smp_protect_wait_list_remove__found_core\@: core could be simultaneously adding (a core is simultaneously trying to get the inter-core lock) or removing (a core is simultaneously being preempted, like what is currently happening). */ - /* _tx_thread_smp_protect_wait_list_lock_get(); */ + // _tx_thread_smp_protect_wait_list_lock_get(); MOV x6, x1 _tx_thread_smp_protect_wait_list_lock_get MOV x1, x6 /* We remove by shifting. */ - /* while (core_index != _tx_thread_smp_protect_wait_list_tail) - { */ + // while (core_index != _tx_thread_smp_protect_wait_list_tail) + // { _tx_thread_smp_protect_wait_list_remove__compare_index_to_tail\@: @@ -217,76 +221,78 @@ _tx_thread_smp_protect_wait_list_remove__compare_index_to_tail\@: CMP w4, w2 // Compare cur index and tail BEQ _tx_thread_smp_protect_wait_list_remove__removed\@ - /* UINT next_index = core_index + 1; */ + // UINT next_index = core_index + 1; MOV w2, w4 // Move current index to next index register ADD w2, w2, #1 // Add 1 - /* if (next_index == _tx_thread_smp_protect_wait_list_size) - { */ + // if (next_index == _tx_thread_smp_protect_wait_list_size) + // { LDR x3, =_tx_thread_smp_protect_wait_list_size LDR w3, [x3] CMP w2, w3 BNE _tx_thread_smp_protect_wait_list_remove__next_index_no_wrap\@ - /* next_index = 0; */ + // next_index = 0; MOV w2, #0 - /* } */ + // } _tx_thread_smp_protect_wait_list_remove__next_index_no_wrap\@: - /* list_cores[core_index] = list_cores[next_index]; */ + // list_cores[core_index] = list_cores[next_index]; LDR x5, =_tx_thread_smp_protect_wait_list // Get the address of the list LDR w3, [x5, x2, LSL #2] // Get the value at the next index STR w3, [x5, x4, LSL #2] // Store the value at the current index - /* core_index = next_index; */ + // core_index = next_index; MOV w4, w2 B _tx_thread_smp_protect_wait_list_remove__compare_index_to_tail\@ - /* } */ + // } _tx_thread_smp_protect_wait_list_remove__removed\@: /* Now update the tail. */ - /* if (_tx_thread_smp_protect_wait_list_tail == 0) - { */ + // if (_tx_thread_smp_protect_wait_list_tail == 0) + // { LDR x5, =_tx_thread_smp_protect_wait_list_tail // Load tail address LDR w4, [x5] // Load tail value CMP w4, #0 BNE _tx_thread_smp_protect_wait_list_remove__tail_not_zero\@ - /* _tx_thread_smp_protect_wait_list_tail = _tx_thread_smp_protect_wait_list_size; */ + // _tx_thread_smp_protect_wait_list_tail = _tx_thread_smp_protect_wait_list_size; LDR x2, =_tx_thread_smp_protect_wait_list_size LDR w4, [x2] - /* } */ + // } _tx_thread_smp_protect_wait_list_remove__tail_not_zero\@: - /* _tx_thread_smp_protect_wait_list_tail--; */ + // _tx_thread_smp_protect_wait_list_tail--; SUB w4, w4, #1 STR w4, [x5] // Store new tail value + DMB ISH // Ensure that accesses to shared resource have completed /* Release the list lock. */ - /* _tx_thread_smp_protect_wait_list_lock_protect_in_force = 0; */ + // _tx_thread_smp_protect_wait_list_lock_protect_in_force = 0; MOV w2, #0 // Build lock value LDR x4, =_tx_thread_smp_protect_wait_list_lock_protect_in_force // Load lock address STR w2, [x4] // Store the new value + DMB ISH // Ensure write to protection finishes /* We're no longer waiting. Note that this should be zero since, again, this function is only called when a thread preemption is occurring. */ - /* _tx_thread_smp_protect_wait_counts[core]--; */ + // _tx_thread_smp_protect_wait_counts[core]--; LDR x4, =_tx_thread_smp_protect_wait_counts // Load wait list counts LDR w2, [x4, x8, LSL #2] // Load waiting value SUB w2, w2, #1 // Subtract 1 diff --git a/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_smp_unprotect.S b/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_smp_unprotect.S index a689ae8b..ff8df7db 100644 --- a/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_smp_unprotect.S +++ b/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_smp_unprotect.S @@ -28,7 +28,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_smp_unprotect Cortex-A35-SMP/AC6 */ -/* 6.1 */ +/* 6.1.9 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -61,6 +61,9 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 10-15-2021 Andres Mlinar Updated comments, */ +/* added ARMv8.2-A support, */ +/* resulting in version 6.1.9 */ /* */ /**************************************************************************/ .global _tx_thread_smp_unprotect @@ -69,10 +72,17 @@ _tx_thread_smp_unprotect: MSR DAIFSet, 0x3 // Lockout interrupts MRS x1, MPIDR_EL1 // Pickup the core ID +#ifdef TX_ARMV8_2 +#if TX_THREAD_SMP_CLUSTERS > 1 + UBFX x2, x1, #16, #8 // Isolate cluster ID +#endif + UBFX x1, x1, #8, #8 // Isolate core ID +#else #if TX_THREAD_SMP_CLUSTERS > 1 UBFX x2, x1, #8, #8 // Isolate cluster ID #endif UBFX x1, x1, #0, #8 // Isolate core ID +#endif #if TX_THREAD_SMP_CLUSTERS > 1 ADDS x1, x1, x2, LSL #2 // Calculate CPU ID #endif @@ -114,4 +124,3 @@ _still_protected: #endif MSR DAIF, x0 // Restore interrupt posture RET - diff --git a/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_timeout.c b/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_timeout.c index c8710f9d..00f48e14 100644 --- a/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_timeout.c +++ b/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_timeout.c @@ -12,8 +12,8 @@ /**************************************************************************/ /**************************************************************************/ -/** */ -/** ThreadX Component */ +/** */ +/** ThreadX Component */ /** */ /** Thread */ /** */ @@ -79,7 +79,7 @@ VOID _tx_thread_timeout(ULONG timeout_input) TX_INTERRUPT_SAVE_AREA -TX_THREAD *thread_ptr; +TX_THREAD *thread_ptr; VOID (*suspend_cleanup)(struct TX_THREAD_STRUCT *suspend_thread_ptr, ULONG suspension_sequence); ULONG suspension_sequence; @@ -126,7 +126,7 @@ ULONG suspension_sequence; /* Increment the number of timeouts for this thread. */ thread_ptr -> tx_thread_performance_timeout_count++; #endif - + /* Pickup the cleanup routine address. */ suspend_cleanup = thread_ptr -> tx_thread_suspend_cleanup; @@ -162,4 +162,3 @@ ULONG suspension_sequence; #endif } } - diff --git a/ports_module/cortex_a35_smp/ac6/module_manager/src/txm_module_manager_port_dispatch.c b/ports_module/cortex_a35_smp/ac6/module_manager/src/txm_module_manager_port_dispatch.c index 39dccb14..4d8b7724 100644 --- a/ports_module/cortex_a35_smp/ac6/module_manager/src/txm_module_manager_port_dispatch.c +++ b/ports_module/cortex_a35_smp/ac6/module_manager/src/txm_module_manager_port_dispatch.c @@ -80,6 +80,6 @@ ALIGN_TYPE return_value = TX_NOT_AVAILABLE; break; } } - + return(return_value); } diff --git a/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx/GICv3.h b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx/GICv3.h index 23bc7fd8..dfe37586 100644 --- a/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx/GICv3.h +++ b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx/GICv3.h @@ -3,7 +3,7 @@ * * Copyright (c) 2014-2017 Arm Limited (or its affiliates). All rights reserved. * Use, modification and redistribution of this file is subject to your possession of a - * valid End User License Agreement for the Arm Product of which these examples are part of + * valid End User License Agreement for the Arm Product of which these examples are part of * and your compliance with all applicable terms and conditions of such licence agreement. */ #ifndef GICV3_h diff --git a/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx/GICv3_aliases.h b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx/GICv3_aliases.h index 0928d14c..826ba973 100644 --- a/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx/GICv3_aliases.h +++ b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx/GICv3_aliases.h @@ -3,7 +3,7 @@ // // Copyright (c) 2016-2017 Arm Limited (or its affiliates). All rights reserved. // Use, modification and redistribution of this file is subject to your possession of a -// valid End User License Agreement for the Arm Product of which these examples are part of +// valid End User License Agreement for the Arm Product of which these examples are part of // and your compliance with all applicable terms and conditions of such licence agreement. // diff --git a/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx/GICv3_gicc.h b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx/GICv3_gicc.h index 2b8a2d3e..998d92b5 100644 --- a/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx/GICv3_gicc.h +++ b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx/GICv3_gicc.h @@ -3,7 +3,7 @@ * * Copyright (c) 2014-2017 Arm Limited (or its affiliates). All rights reserved. * Use, modification and redistribution of this file is subject to your possession of a - * valid End User License Agreement for the Arm Product of which these examples are part of + * valid End User License Agreement for the Arm Product of which these examples are part of * and your compliance with all applicable terms and conditions of such licence agreement. */ #ifndef GICV3_gicc_h diff --git a/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx/GICv3_gicd.c b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx/GICv3_gicd.c index 2cf9e843..464ecced 100644 --- a/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx/GICv3_gicd.c +++ b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx/GICv3_gicd.c @@ -3,7 +3,7 @@ * * Copyright (c) 2014-2017 Arm Limited (or its affiliates). All rights reserved. * Use, modification and redistribution of this file is subject to your possession of a - * valid End User License Agreement for the Arm Product of which these examples are part of + * valid End User License Agreement for the Arm Product of which these examples are part of * and your compliance with all applicable terms and conditions of such licence agreement. */ #include <stdint.h> diff --git a/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx/GICv3_gicr.c b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx/GICv3_gicr.c index ef5c8925..e4645084 100644 --- a/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx/GICv3_gicr.c +++ b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx/GICv3_gicr.c @@ -3,7 +3,7 @@ * * Copyright (c) 2014-2018 Arm Limited (or its affiliates). All rights reserved. * Use, modification and redistribution of this file is subject to your possession of a - * valid End User License Agreement for the Arm Product of which these examples are part of + * valid End User License Agreement for the Arm Product of which these examples are part of * and your compliance with all applicable terms and conditions of such licence agreement. */ #include "GICv3.h" diff --git a/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx/MP_Mutexes.S b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx/MP_Mutexes.S index 77fa0a0f..7b63558e 100644 --- a/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx/MP_Mutexes.S +++ b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx/MP_Mutexes.S @@ -3,7 +3,7 @@ // // Copyright (c) 2012-2017 Arm Limited (or its affiliates). All rights reserved. // Use, modification and redistribution of this file is subject to your possession of a -// valid End User License Agreement for the Arm Product of which these examples are part of +// valid End User License Agreement for the Arm Product of which these examples are part of // and your compliance with all applicable terms and conditions of such licence agreement. // diff --git a/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx/PPM_AEM.h b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx/PPM_AEM.h index 52c9a0fe..f7501eeb 100644 --- a/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx/PPM_AEM.h +++ b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx/PPM_AEM.h @@ -3,7 +3,7 @@ // // Copyright (c) 2012-2017 Arm Limited (or its affiliates). All rights reserved. // Use, modification and redistribution of this file is subject to your possession of a -// valid End User License Agreement for the Arm Product of which these examples are part of +// valid End User License Agreement for the Arm Product of which these examples are part of // and your compliance with all applicable terms and conditions of such licence agreement. // diff --git a/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx/sample_threadx.c b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx/sample_threadx.c index 139a848c..9d1733a5 100644 --- a/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx/sample_threadx.c +++ b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx/sample_threadx.c @@ -1,5 +1,5 @@ /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight - threads of different priorities, using a message queue, semaphore, mutex, event flags group, + threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ #include "tx_api.h" @@ -104,41 +104,41 @@ CHAR *pointer = TX_NULL; tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create the main thread. */ - tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 1. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 1 and 2. These threads pass information through a ThreadX + /* Create threads 1 and 2. These threads pass information through a ThreadX message queue. It is also interesting to note that these threads have a time slice. */ tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, DEMO_STACK_SIZE, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); - + /* Allocate the stack for thread 2. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, - pointer, DEMO_STACK_SIZE, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 3. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. An interesting thing here is that both threads share the same instruction area. */ - tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 4. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 5. */ @@ -146,23 +146,23 @@ CHAR *pointer = TX_NULL; /* Create thread 5. This thread simply pends on an event flag which will be set by thread_0. */ - tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 6. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ - tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 7. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the message queue. */ @@ -264,11 +264,11 @@ UINT status; /* Retrieve a message from the queue. */ status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); - /* Check completion status and make sure the message is what we + /* Check completion status and make sure the message is what we expected. */ if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) break; - + /* Otherwise, all is okay. Increment the received message count. */ thread_2_messages_received++; } @@ -327,7 +327,7 @@ ULONG actual_flags; thread_5_counter++; /* Wait for event flag 0. */ - status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, &actual_flags, TX_WAIT_FOREVER); /* Check status. */ @@ -380,7 +380,7 @@ UINT status; if (status != TX_SUCCESS) break; - /* Release the mutex again. This will actually + /* Release the mutex again. This will actually release ownership since it was obtained twice. */ status = tx_mutex_put(&mutex_0); diff --git a/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx/sp804_timer.c b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx/sp804_timer.c index 4dc009b2..c2ce6faa 100644 --- a/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx/sp804_timer.c +++ b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx/sp804_timer.c @@ -3,7 +3,7 @@ // // Copyright (c) 2009-2017 Arm Limited (or its affiliates). All rights reserved. // Use, modification and redistribution of this file is subject to your possession of a -// valid End User License Agreement for the Arm Product of which these examples are part of +// valid End User License Agreement for the Arm Product of which these examples are part of // and your compliance with all applicable terms and conditions of such licence agreement. // ------------------------------------------------------------ diff --git a/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx/sp804_timer.h b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx/sp804_timer.h index 777062cc..4d423904 100644 --- a/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx/sp804_timer.h +++ b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx/sp804_timer.h @@ -4,7 +4,7 @@ // // Copyright (c) 2009-2017 Arm Limited (or its affiliates). All rights reserved. // Use, modification and redistribution of this file is subject to your possession of a -// valid End User License Agreement for the Arm Product of which these examples are part of +// valid End User License Agreement for the Arm Product of which these examples are part of // and your compliance with all applicable terms and conditions of such licence agreement. // ------------------------------------------------------------ diff --git a/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx/startup.S b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx/startup.S index 53f02e37..2d59722d 100644 --- a/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx/startup.S +++ b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx/startup.S @@ -7,7 +7,7 @@ // // Copyright (c) 2014-2017 Arm Limited (or its affiliates). All rights reserved. // Use, modification and redistribution of this file is subject to your possession of a -// valid End User License Agreement for the Arm Product of which these examples are part of +// valid End User License Agreement for the Arm Product of which these examples are part of // and your compliance with all applicable terms and conditions of such licence agreement. // ------------------------------------------------------------ @@ -326,7 +326,7 @@ el1_entry_aarch64: // // Cortex-A processors automatically invalidate their caches on reset // (unless suppressed with the DBGL1RSTDISABLE or L2RSTDISABLE pins). - // It is therefore not necessary for software to invalidate the caches + // It is therefore not necessary for software to invalidate the caches // on startup, however, this is done here in case of a warm reset. bl InvalidateUDCaches tlbi VMALLE1 @@ -685,7 +685,7 @@ nol2setup: bic x1, x1, #SCTLR_ELx_A // Disable alignment fault checking. To enable, change bic to orr msr SCTLR_EL1, x1 isb - + // // The Arm Architecture Reference Manual for Armv8-A states: // @@ -740,7 +740,7 @@ arg0: bl main b exit // Will not return - + // ------------------------------------------------------------ // EL1 - secondary CPU init code // @@ -795,4 +795,4 @@ loop_wfi: // Branch to thread start // //B MainApp - + diff --git a/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx/v8_aarch64.S b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx/v8_aarch64.S index d86fecb6..f39eca6c 100644 --- a/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx/v8_aarch64.S +++ b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx/v8_aarch64.S @@ -3,7 +3,7 @@ // // Copyright (c) 2012-2018 Arm Limited (or its affiliates). All rights reserved. // Use, modification and redistribution of this file is subject to your possession of a -// valid End User License Agreement for the Arm Product of which these examples are part of +// valid End User License Agreement for the Arm Product of which these examples are part of // and your compliance with all applicable terms and conditions of such licence agreement. // ------------------------------------------------------------ diff --git a/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx/v8_mmu.h b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx/v8_mmu.h index 0185feba..dbf903ca 100644 --- a/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx/v8_mmu.h +++ b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx/v8_mmu.h @@ -3,7 +3,7 @@ // // Copyright (c) 2012-2016 Arm Limited (or its affiliates). All rights reserved. // Use, modification and redistribution of this file is subject to your possession of a -// valid End User License Agreement for the Arm Product of which these examples are part of +// valid End User License Agreement for the Arm Product of which these examples are part of // and your compliance with all applicable terms and conditions of such licence agreement. // diff --git a/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx/v8_system.h b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx/v8_system.h index ff96deff..a62d2a33 100644 --- a/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx/v8_system.h +++ b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx/v8_system.h @@ -3,7 +3,7 @@ // // Copyright (c) 2012-2016 Arm Limited (or its affiliates). All rights reserved. // Use, modification and redistribution of this file is subject to your possession of a -// valid End User License Agreement for the Arm Product of which these examples are part of +// valid End User License Agreement for the Arm Product of which these examples are part of // and your compliance with all applicable terms and conditions of such licence agreement. // diff --git a/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx/v8_utils.S b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx/v8_utils.S index f0fcef26..888892a0 100644 --- a/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx/v8_utils.S +++ b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx/v8_utils.S @@ -3,7 +3,7 @@ // // Copyright (c) 2013-2017 Arm Limited (or its affiliates). All rights reserved. // Use, modification and redistribution of this file is subject to your possession of a -// valid End User License Agreement for the Arm Product of which these examples are part of +// valid End User License Agreement for the Arm Product of which these examples are part of // and your compliance with all applicable terms and conditions of such licence agreement. // diff --git a/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx/vectors.S b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx/vectors.S index 9e60e001..7784f98e 100644 --- a/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx/vectors.S +++ b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx/vectors.S @@ -3,7 +3,7 @@ // // Copyright (c) 2014-2016 Arm Limited (or its affiliates). All rights reserved. // Use, modification and redistribution of this file is subject to your possession of a -// valid End User License Agreement for the Arm Product of which these examples are part of +// valid End User License Agreement for the Arm Product of which these examples are part of // and your compliance with all applicable terms and conditions of such licence agreement. // ------------------------------------------------------------ diff --git a/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module/gcc_setup.s b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module/gcc_setup.s index 7c454996..e0569f71 100644 --- a/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module/gcc_setup.s +++ b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module/gcc_setup.s @@ -17,7 +17,7 @@ _gcc_setup: ldr x9, =__RAM_segment_start__ /* Copy GOT table. */ - + ldr x0, =__got_load_start__ sub x0 ,x0, x3 add x0, x0, x5 @@ -51,7 +51,7 @@ got_setup_done: /* Copy initialised sections into RAM if required. */ - + ldr x0, =__data_load_start__ sub x0, x0, x3 add x0, x0, x5 @@ -62,9 +62,9 @@ got_setup_done: sub x2, x2, x4 add x2, x2, x9 bl crt0_memory_copy - + /* Zero bss. */ - + ldr x0, =__bss_start__ sub x0, x0, x4 add x0, x0, x9 @@ -88,12 +88,12 @@ got_setup_done: str x2, [x0] add x0, x0, #4 str x1, [x0] - + ldr x30, [sp] // Restore other preserved registers add sp, sp, 16 ret // Return to caller - + /* Startup helper functions. */ @@ -126,4 +126,4 @@ memory_set_done: /* Setup attibutes of heap section so it doesn't take up room in the elf file */ .section .heap, "wa", %nobits - + diff --git a/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module/sample_threadx_module.c b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module/sample_threadx_module.c index a974cdf1..e94ac221 100644 --- a/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module/sample_threadx_module.c +++ b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module/sample_threadx_module.c @@ -1,5 +1,5 @@ -/* This is a small demo of the high-performance ThreadX kernel running as a module. It includes - examples of eight threads of different priorities, using a message queue, semaphore, mutex, +/* This is a small demo of the high-performance ThreadX kernel running as a module. It includes + examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ /* Specify that this is a module! */ @@ -20,7 +20,7 @@ #define DEMO_QUEUE_SIZE 100 -/* Define the pool space in the bss section of the module. ULONG is used to +/* Define the pool space in the bss section of the module. ULONG is used to get the word alignment. */ ULONG demo_module_pool_space[DEMO_BYTE_POOL_SIZE / sizeof(ULONG)]; @@ -103,7 +103,7 @@ CHAR *pointer; /* Allocate all the objects. In MMU mode, modules cannot allocate control blocks within - their own memory area so they cannot corrupt the resident portion of ThreadX by overwriting + their own memory area so they cannot corrupt the resident portion of ThreadX by overwriting the control block(s). */ status = txm_module_object_allocate((void*)&thread_0, sizeof(TX_THREAD)); while (status != TX_SUCCESS); @@ -133,7 +133,7 @@ CHAR *pointer; while (status != TX_SUCCESS); status = txm_module_object_allocate((void*)&block_pool_0, sizeof(TX_BLOCK_POOL)); while (status != TX_SUCCESS); - + /* Create a byte memory pool from which to allocate the thread stacks. */ status = tx_byte_pool_create(byte_pool_0, "module byte pool 0", demo_module_pool_space, DEMO_BYTE_POOL_SIZE); @@ -193,7 +193,7 @@ CHAR *pointer; /* Create the main thread. */ status = tx_thread_create(thread_0, "module thread 0", thread_0_entry, 0, - pointer, DEMO_STACK_SIZE, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); while (status != TX_SUCCESS); @@ -201,11 +201,11 @@ CHAR *pointer; status = tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); while (status != TX_SUCCESS); - /* Create threads 1 and 2. These threads pass information through a ThreadX + /* Create threads 1 and 2. These threads pass information through a ThreadX message queue. It is also interesting to note that these threads have a time slice. */ status = tx_thread_create(thread_1, "module thread 1", thread_1_entry, 1, - pointer, DEMO_STACK_SIZE, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); while (status != TX_SUCCESS); @@ -214,7 +214,7 @@ CHAR *pointer; while (status != TX_SUCCESS); status = tx_thread_create(thread_2, "module thread 2", thread_2_entry, 2, - pointer, DEMO_STACK_SIZE, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); while (status != TX_SUCCESS); @@ -222,10 +222,10 @@ CHAR *pointer; status = tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); while (status != TX_SUCCESS); - /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. An interesting thing here is that both threads share the same instruction area. */ status = tx_thread_create(thread_3, "module thread 3", thread_3_and_4_entry, 3, - pointer, DEMO_STACK_SIZE, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); while (status != TX_SUCCESS); @@ -234,7 +234,7 @@ CHAR *pointer; while (status != TX_SUCCESS); status = tx_thread_create(thread_4, "module thread 4", thread_3_and_4_entry, 4, - pointer, DEMO_STACK_SIZE, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); while (status != TX_SUCCESS); @@ -245,7 +245,7 @@ CHAR *pointer; /* Create thread 5. This thread simply pends on an event flag which will be set by thread_0. */ status = tx_thread_create(thread_5, "module thread 5", thread_5_entry, 5, - pointer, DEMO_STACK_SIZE, + pointer, DEMO_STACK_SIZE, 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); while (status != TX_SUCCESS); @@ -255,7 +255,7 @@ CHAR *pointer; /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ status = tx_thread_create(thread_6, "module thread 6", thread_6_and_7_entry, 6, - pointer, DEMO_STACK_SIZE, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); while (status != TX_SUCCESS); @@ -264,7 +264,7 @@ CHAR *pointer; while (status != TX_SUCCESS); status = tx_thread_create(thread_7, "module thread 7", thread_6_and_7_entry, 7, - pointer, DEMO_STACK_SIZE, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); while (status != TX_SUCCESS); } @@ -276,7 +276,7 @@ void thread_0_entry(ULONG thread_input) { UINT status; - + /* This thread simply sits in while-forever-sleep loop. */ while(1) { @@ -286,7 +286,7 @@ UINT status; /* Sleep for 10 ticks. */ tx_thread_sleep(10); - + /* Set event flag 0 to wakeup thread 5. */ status = tx_event_flags_set(event_flags_0, 0x1, TX_OR); @@ -338,11 +338,11 @@ UINT status; /* Retrieve a message from the queue. */ status = tx_queue_receive(queue_0, &received_message, TX_WAIT_FOREVER); - /* Check completion status and make sure the message is what we + /* Check completion status and make sure the message is what we expected. */ if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) break; - + /* Otherwise, all is okay. Increment the received message count. */ thread_2_messages_received++; } @@ -401,7 +401,7 @@ ULONG actual_flags; thread_5_counter++; /* Wait for event flag 0. */ - status = tx_event_flags_get(event_flags_0, 0x1, TX_OR_CLEAR, + status = tx_event_flags_get(event_flags_0, 0x1, TX_OR_CLEAR, &actual_flags, TX_WAIT_FOREVER); /* Check status. */ @@ -454,7 +454,7 @@ UINT status; if (status != TX_SUCCESS) break; - /* Release the mutex again. This will actually + /* Release the mutex again. This will actually release ownership since it was obtained twice. */ status = tx_mutex_put(mutex_0); diff --git a/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module/txm_module_preamble.S b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module/txm_module_preamble.S index cce29ef8..e41ac007 100644 --- a/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module/txm_module_preamble.S +++ b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module/txm_module_preamble.S @@ -1,6 +1,6 @@ .section .txm_module_preamble .align 4 - + // External references .global _txm_module_thread_shell_entry .global _txm_module_callback_request_thread_entry diff --git a/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module_manager/GICv3.h b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module_manager/GICv3.h index 23bc7fd8..dfe37586 100644 --- a/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module_manager/GICv3.h +++ b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module_manager/GICv3.h @@ -3,7 +3,7 @@ * * Copyright (c) 2014-2017 Arm Limited (or its affiliates). All rights reserved. * Use, modification and redistribution of this file is subject to your possession of a - * valid End User License Agreement for the Arm Product of which these examples are part of + * valid End User License Agreement for the Arm Product of which these examples are part of * and your compliance with all applicable terms and conditions of such licence agreement. */ #ifndef GICV3_h diff --git a/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module_manager/GICv3_aliases.h b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module_manager/GICv3_aliases.h index 0928d14c..826ba973 100644 --- a/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module_manager/GICv3_aliases.h +++ b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module_manager/GICv3_aliases.h @@ -3,7 +3,7 @@ // // Copyright (c) 2016-2017 Arm Limited (or its affiliates). All rights reserved. // Use, modification and redistribution of this file is subject to your possession of a -// valid End User License Agreement for the Arm Product of which these examples are part of +// valid End User License Agreement for the Arm Product of which these examples are part of // and your compliance with all applicable terms and conditions of such licence agreement. // diff --git a/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module_manager/GICv3_gicc.h b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module_manager/GICv3_gicc.h index 2b8a2d3e..998d92b5 100644 --- a/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module_manager/GICv3_gicc.h +++ b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module_manager/GICv3_gicc.h @@ -3,7 +3,7 @@ * * Copyright (c) 2014-2017 Arm Limited (or its affiliates). All rights reserved. * Use, modification and redistribution of this file is subject to your possession of a - * valid End User License Agreement for the Arm Product of which these examples are part of + * valid End User License Agreement for the Arm Product of which these examples are part of * and your compliance with all applicable terms and conditions of such licence agreement. */ #ifndef GICV3_gicc_h diff --git a/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module_manager/GICv3_gicd.c b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module_manager/GICv3_gicd.c index 2cf9e843..464ecced 100644 --- a/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module_manager/GICv3_gicd.c +++ b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module_manager/GICv3_gicd.c @@ -3,7 +3,7 @@ * * Copyright (c) 2014-2017 Arm Limited (or its affiliates). All rights reserved. * Use, modification and redistribution of this file is subject to your possession of a - * valid End User License Agreement for the Arm Product of which these examples are part of + * valid End User License Agreement for the Arm Product of which these examples are part of * and your compliance with all applicable terms and conditions of such licence agreement. */ #include <stdint.h> diff --git a/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module_manager/GICv3_gicr.c b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module_manager/GICv3_gicr.c index ef5c8925..e4645084 100644 --- a/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module_manager/GICv3_gicr.c +++ b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module_manager/GICv3_gicr.c @@ -3,7 +3,7 @@ * * Copyright (c) 2014-2018 Arm Limited (or its affiliates). All rights reserved. * Use, modification and redistribution of this file is subject to your possession of a - * valid End User License Agreement for the Arm Product of which these examples are part of + * valid End User License Agreement for the Arm Product of which these examples are part of * and your compliance with all applicable terms and conditions of such licence agreement. */ #include "GICv3.h" diff --git a/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module_manager/MP_Mutexes.S b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module_manager/MP_Mutexes.S index 77fa0a0f..7b63558e 100644 --- a/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module_manager/MP_Mutexes.S +++ b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module_manager/MP_Mutexes.S @@ -3,7 +3,7 @@ // // Copyright (c) 2012-2017 Arm Limited (or its affiliates). All rights reserved. // Use, modification and redistribution of this file is subject to your possession of a -// valid End User License Agreement for the Arm Product of which these examples are part of +// valid End User License Agreement for the Arm Product of which these examples are part of // and your compliance with all applicable terms and conditions of such licence agreement. // diff --git a/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module_manager/PPM_AEM.h b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module_manager/PPM_AEM.h index 52c9a0fe..f7501eeb 100644 --- a/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module_manager/PPM_AEM.h +++ b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module_manager/PPM_AEM.h @@ -3,7 +3,7 @@ // // Copyright (c) 2012-2017 Arm Limited (or its affiliates). All rights reserved. // Use, modification and redistribution of this file is subject to your possession of a -// valid End User License Agreement for the Arm Product of which these examples are part of +// valid End User License Agreement for the Arm Product of which these examples are part of // and your compliance with all applicable terms and conditions of such licence agreement. // diff --git a/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module_manager/sample_threadx_module_manager.c b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module_manager/sample_threadx_module_manager.c index c7296646..c0772002 100644 --- a/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module_manager/sample_threadx_module_manager.c +++ b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module_manager/sample_threadx_module_manager.c @@ -115,7 +115,7 @@ void module_manager_entry(ULONG thread_input) /* Load the module with absolute address linkage, in this example it is placed there by the multiple image download. */ txm_module_manager_absolute_load(&my_module, "my module", (void *) MODULE_CODE); - + /* Start the module. */ txm_module_manager_start(&my_module); @@ -127,10 +127,10 @@ void module_manager_entry(ULONG thread_input) tx_thread_sleep(10); } } - + /* Stop the module. */ txm_module_manager_stop(&my_module); - + /* Unload the module. */ txm_module_manager_unload(&my_module); @@ -139,11 +139,11 @@ void module_manager_entry(ULONG thread_input) /* Start the module again. */ txm_module_manager_start(&my_module); - + /* Now just spin... */ while(1) { - + tx_thread_sleep(10); } } diff --git a/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module_manager/sp804_timer.c b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module_manager/sp804_timer.c index 4dc009b2..c2ce6faa 100644 --- a/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module_manager/sp804_timer.c +++ b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module_manager/sp804_timer.c @@ -3,7 +3,7 @@ // // Copyright (c) 2009-2017 Arm Limited (or its affiliates). All rights reserved. // Use, modification and redistribution of this file is subject to your possession of a -// valid End User License Agreement for the Arm Product of which these examples are part of +// valid End User License Agreement for the Arm Product of which these examples are part of // and your compliance with all applicable terms and conditions of such licence agreement. // ------------------------------------------------------------ diff --git a/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module_manager/sp804_timer.h b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module_manager/sp804_timer.h index 777062cc..4d423904 100644 --- a/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module_manager/sp804_timer.h +++ b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module_manager/sp804_timer.h @@ -4,7 +4,7 @@ // // Copyright (c) 2009-2017 Arm Limited (or its affiliates). All rights reserved. // Use, modification and redistribution of this file is subject to your possession of a -// valid End User License Agreement for the Arm Product of which these examples are part of +// valid End User License Agreement for the Arm Product of which these examples are part of // and your compliance with all applicable terms and conditions of such licence agreement. // ------------------------------------------------------------ diff --git a/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module_manager/startup.S b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module_manager/startup.S index 53f02e37..2d59722d 100644 --- a/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module_manager/startup.S +++ b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module_manager/startup.S @@ -7,7 +7,7 @@ // // Copyright (c) 2014-2017 Arm Limited (or its affiliates). All rights reserved. // Use, modification and redistribution of this file is subject to your possession of a -// valid End User License Agreement for the Arm Product of which these examples are part of +// valid End User License Agreement for the Arm Product of which these examples are part of // and your compliance with all applicable terms and conditions of such licence agreement. // ------------------------------------------------------------ @@ -326,7 +326,7 @@ el1_entry_aarch64: // // Cortex-A processors automatically invalidate their caches on reset // (unless suppressed with the DBGL1RSTDISABLE or L2RSTDISABLE pins). - // It is therefore not necessary for software to invalidate the caches + // It is therefore not necessary for software to invalidate the caches // on startup, however, this is done here in case of a warm reset. bl InvalidateUDCaches tlbi VMALLE1 @@ -685,7 +685,7 @@ nol2setup: bic x1, x1, #SCTLR_ELx_A // Disable alignment fault checking. To enable, change bic to orr msr SCTLR_EL1, x1 isb - + // // The Arm Architecture Reference Manual for Armv8-A states: // @@ -740,7 +740,7 @@ arg0: bl main b exit // Will not return - + // ------------------------------------------------------------ // EL1 - secondary CPU init code // @@ -795,4 +795,4 @@ loop_wfi: // Branch to thread start // //B MainApp - + diff --git a/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module_manager/v8_aarch64.S b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module_manager/v8_aarch64.S index d86fecb6..f39eca6c 100644 --- a/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module_manager/v8_aarch64.S +++ b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module_manager/v8_aarch64.S @@ -3,7 +3,7 @@ // // Copyright (c) 2012-2018 Arm Limited (or its affiliates). All rights reserved. // Use, modification and redistribution of this file is subject to your possession of a -// valid End User License Agreement for the Arm Product of which these examples are part of +// valid End User License Agreement for the Arm Product of which these examples are part of // and your compliance with all applicable terms and conditions of such licence agreement. // ------------------------------------------------------------ diff --git a/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module_manager/v8_mmu.h b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module_manager/v8_mmu.h index 0185feba..dbf903ca 100644 --- a/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module_manager/v8_mmu.h +++ b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module_manager/v8_mmu.h @@ -3,7 +3,7 @@ // // Copyright (c) 2012-2016 Arm Limited (or its affiliates). All rights reserved. // Use, modification and redistribution of this file is subject to your possession of a -// valid End User License Agreement for the Arm Product of which these examples are part of +// valid End User License Agreement for the Arm Product of which these examples are part of // and your compliance with all applicable terms and conditions of such licence agreement. // diff --git a/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module_manager/v8_system.h b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module_manager/v8_system.h index ff96deff..a62d2a33 100644 --- a/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module_manager/v8_system.h +++ b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module_manager/v8_system.h @@ -3,7 +3,7 @@ // // Copyright (c) 2012-2016 Arm Limited (or its affiliates). All rights reserved. // Use, modification and redistribution of this file is subject to your possession of a -// valid End User License Agreement for the Arm Product of which these examples are part of +// valid End User License Agreement for the Arm Product of which these examples are part of // and your compliance with all applicable terms and conditions of such licence agreement. // diff --git a/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module_manager/v8_utils.S b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module_manager/v8_utils.S index f0fcef26..888892a0 100644 --- a/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module_manager/v8_utils.S +++ b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module_manager/v8_utils.S @@ -3,7 +3,7 @@ // // Copyright (c) 2013-2017 Arm Limited (or its affiliates). All rights reserved. // Use, modification and redistribution of this file is subject to your possession of a -// valid End User License Agreement for the Arm Product of which these examples are part of +// valid End User License Agreement for the Arm Product of which these examples are part of // and your compliance with all applicable terms and conditions of such licence agreement. // diff --git a/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module_manager/vectors.S b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module_manager/vectors.S index 9e60e001..7784f98e 100644 --- a/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module_manager/vectors.S +++ b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module_manager/vectors.S @@ -3,7 +3,7 @@ // // Copyright (c) 2014-2016 Arm Limited (or its affiliates). All rights reserved. // Use, modification and redistribution of this file is subject to your possession of a -// valid End User License Agreement for the Arm Product of which these examples are part of +// valid End User License Agreement for the Arm Product of which these examples are part of // and your compliance with all applicable terms and conditions of such licence agreement. // ------------------------------------------------------------ diff --git a/ports_module/cortex_a35_smp/gnu/inc/tx_port.h b/ports_module/cortex_a35_smp/gnu/inc/tx_port.h index fe98f3cc..33c403d2 100644 --- a/ports_module/cortex_a35_smp/gnu/inc/tx_port.h +++ b/ports_module/cortex_a35_smp/gnu/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h Cortex-A35-SMP/GNU */ -/* 6.1.3 */ +/* 6.1.9 */ /* */ /* AUTHOR */ /* */ @@ -48,6 +48,9 @@ /* DATE NAME DESCRIPTION */ /* */ /* 12-31-2020 Andres Mlinar Initial Version 6.1.3 */ +/* 10-15-2021 William E. Lamie Modified comment(s), added */ +/* symbol ULONG64_DEFINED, */ +/* resulting in version 6.1.9 */ /* */ /**************************************************************************/ @@ -152,7 +155,7 @@ typedef unsigned int ULONG; typedef unsigned long long ULONG64; typedef short SHORT; typedef unsigned short USHORT; - +#define ULONG64_DEFINED /* Override the alignment type to use 64-bit alignment and storage for pointers. */ @@ -441,7 +444,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Modules Cortex-A35-SMP/GNU Version 6.1.3 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Modules Cortex-A35-SMP/GNU Version 6.1.9 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_module/cortex_a35_smp/gnu/inc/txm_module_port.h b/ports_module/cortex_a35_smp/gnu/inc/txm_module_port.h index 604b801a..ee279ca1 100644 --- a/ports_module/cortex_a35_smp/gnu/inc/txm_module_port.h +++ b/ports_module/cortex_a35_smp/gnu/inc/txm_module_port.h @@ -274,6 +274,6 @@ ALIGN_TYPE _txm_module_manager_port_dispatch(TXM_MODULE_INSTANCE *module_instanc #define TXM_MODULE_MANAGER_VERSION_ID \ CHAR _txm_module_manager_version_id[] = \ - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-A35/GNU Version 6.1.3 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-A35/GNU Version 6.1.9 *"; #endif diff --git a/ports_module/cortex_a35_smp/gnu/module_lib/src/txm_module_thread_shell_entry.c b/ports_module/cortex_a35_smp/gnu/module_lib/src/txm_module_thread_shell_entry.c index 1427d7fd..d9d057c5 100644 --- a/ports_module/cortex_a35_smp/gnu/module_lib/src/txm_module_thread_shell_entry.c +++ b/ports_module/cortex_a35_smp/gnu/module_lib/src/txm_module_thread_shell_entry.c @@ -121,7 +121,7 @@ VOID (*entry_exit_notify)(TX_THREAD *notify_thread_ptr, UINT type); An error here typically indicates the resident portion of _tx_thread_schedule is not supporting the trap to obtain the function pointer. */ } - + /* Resume the module's callback thread, already created in the manager. */ _txe_thread_resume(thread_info -> txm_module_thread_entry_info_callback_request_thread); } diff --git a/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_smp_core_get.S b/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_smp_core_get.S index a2dfb913..654ac7e7 100644 --- a/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_smp_core_get.S +++ b/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_smp_core_get.S @@ -27,8 +27,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_smp_core_get Cortex-A35-SMP/GNU */ -/* 6.1 */ +/* _tx_thread_smp_core_get Cortex-A35-SMP/GCC */ +/* 6.1.9 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -58,17 +58,28 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 10-15-2021 Andres Mlinar Updated comments, */ +/* added ARMv8.2-A support, */ +/* resulting in version 6.1.9 */ /* */ /**************************************************************************/ .global _tx_thread_smp_core_get .type _tx_thread_smp_core_get, @function _tx_thread_smp_core_get: MRS x0, MPIDR_EL1 // Pickup the core ID +#ifdef TX_ARMV8_2 +#if TX_THREAD_SMP_CLUSTERS > 1 + UBFX x1, x0, #16, #8 // Isolate cluster ID +#endif + UBFX x0, x0, #8, #8 // Isolate core ID +#else #if TX_THREAD_SMP_CLUSTERS > 1 UBFX x1, x0, #8, #8 // Isolate cluster ID #endif UBFX x0, x0, #0, #8 // Isolate core ID +#endif #if TX_THREAD_SMP_CLUSTERS > 1 ADDS x0, x0, x1, LSL #2 // Calculate CPU ID #endif RET + diff --git a/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_smp_protect.S b/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_smp_protect.S index cdb23c0b..59bf4ff4 100644 --- a/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_smp_protect.S +++ b/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_smp_protect.S @@ -31,8 +31,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_smp_protect Cortex-A35-SMP/GNU */ -/* 6.1 */ +/* _tx_thread_smp_protect Cortex-A35-SMP/GCC */ +/* 6.1.9 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -64,6 +64,10 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 10-15-2021 Andres Mlinar Updated comments, */ +/* added ARMv8.2-A support, */ +/* improved SMP code, */ +/* resulting in version 6.1.9 */ /* */ /**************************************************************************/ .global _tx_thread_smp_protect @@ -78,10 +82,17 @@ _tx_thread_smp_protect: /* Pickup the CPU ID. */ MRS x1, MPIDR_EL1 // Pickup the core ID +#ifdef TX_ARMV8_2 +#if TX_THREAD_SMP_CLUSTERS > 1 + UBFX x7, x1, #16, #8 // Isolate cluster ID +#endif + UBFX x1, x1, #8, #8 // Isolate core ID +#else #if TX_THREAD_SMP_CLUSTERS > 1 UBFX x7, x1, #8, #8 // Isolate cluster ID #endif UBFX x1, x1, #0, #8 // Isolate core ID +#endif #if TX_THREAD_SMP_CLUSTERS > 1 ADDS x1, x1, x7, LSL #2 // Calculate CPU ID #endif @@ -163,7 +174,7 @@ _list_not_empty: // if (_tx_thread_smp_protection.tx_thread_smp_protect_in_force == 0) // { - LDR w3, [x2, #0] // Pickup the protection flag + LDAXR w3, [x2, #0] // Pickup the protection flag CMP w3, #0 BNE _start_waiting // No, protection not available @@ -171,7 +182,9 @@ _list_not_empty: // _tx_thread_smp_protection.tx_thread_smp_protect_in_force = 1; MOV w3, #1 // Build lock value - STR w3, [x2, #0] // Store lock value + STXR w4, w3, [x2, #0] // Attempt to get the protection + CMP w4, #0 + BNE _start_waiting // Did it fail? DMB ISH // /* Got the lock. */ @@ -217,7 +230,7 @@ _already_in_list0: /* Restore interrupts. */ MSR DAIF, x0 // Restore interrupts - ISB // + ISB // #ifdef TX_ENABLE_WFE WFE // Go into standby #endif @@ -236,10 +249,17 @@ _try_to_get_lock: /* Pickup the CPU ID. */ MRS x1, MPIDR_EL1 // Pickup the core ID +#ifdef TX_ARMV8_2 +#if TX_THREAD_SMP_CLUSTERS > 1 + UBFX x7, x1, #16, #8 // Isolate cluster ID +#endif + UBFX x1, x1, #8, #8 // Isolate core ID +#else #if TX_THREAD_SMP_CLUSTERS > 1 UBFX x7, x1, #8, #8 // Isolate cluster ID #endif UBFX x1, x1, #0, #8 // Isolate core ID +#endif #if TX_THREAD_SMP_CLUSTERS > 1 ADDS x1, x1, x7, LSL #2 // Calculate CPU ID #endif @@ -257,7 +277,7 @@ _try_to_get_lock: /* Are we at the front of the list? */ // if (this_core == _tx_thread_smp_protect_wait_list[_tx_thread_smp_protect_wait_list_head]) - // {/ + // { LDR x3, =_tx_thread_smp_protect_wait_list_head // Get the address of the head LDR w3, [x3] // Get the value of the head @@ -271,7 +291,7 @@ _try_to_get_lock: // if (_tx_thread_smp_protection.tx_thread_smp_protect_in_force == 0) // { - LDR w3, [x2, #0] // Pickup the protection flag + LDAXR w3, [x2, #0] // Pickup the protection flag CMP w3, #0 BNE _did_not_get_lock // No, protection not available @@ -279,7 +299,9 @@ _try_to_get_lock: // _tx_thread_smp_protection.tx_thread_smp_protect_in_force = 1; MOV w3, #1 // Build lock value - STR w3, [x2, #0] // Store lock value + STXR w4, w3, [x2, #0] // Attempt to get the protection + CMP w4, #0 + BNE _did_not_get_lock // Did it fail? DMB ISH // /* Got the lock. */ @@ -328,7 +350,7 @@ _already_in_list1: /* Restore interrupts and try again. */ MSR DAIF, x0 // Restore interrupts - ISB // + ISB // #ifdef TX_ENABLE_WFE WFE // Go into standby #endif @@ -349,4 +371,3 @@ _got_lock_after_waiting: _return: RET - diff --git a/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_smp_protection_wait_list_macros.h b/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_smp_protection_wait_list_macros.h index 5c33d940..c56c8d38 100644 --- a/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_smp_protection_wait_list_macros.h +++ b/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_smp_protection_wait_list_macros.h @@ -23,12 +23,12 @@ .macro _tx_thread_smp_protect_lock_got /* Set the currently owned core. */ - /* _tx_thread_smp_protection.tx_thread_smp_protect_core = this_core; */ + // _tx_thread_smp_protection.tx_thread_smp_protect_core = this_core; STR w1, [x2, #4] // Store this core /* Increment the protection count. */ - /* _tx_thread_smp_protection.tx_thread_smp_protect_count++; */ + // _tx_thread_smp_protection.tx_thread_smp_protect_count++; LDR w3, [x2, #8] // Pickup ownership count ADD w3, w3, #1 // Increment ownership count @@ -40,7 +40,7 @@ .macro _tx_thread_smp_protect_remove_from_front_of_list /* Remove ourselves from the list. */ - /* _tx_thread_smp_protect_wait_list[_tx_thread_smp_protect_wait_list_head++] = 0xFFFFFFFF; */ + // _tx_thread_smp_protect_wait_list[_tx_thread_smp_protect_wait_list_head++] = 0xFFFFFFFF; MOV w3, #0xFFFFFFFF // Build the invalid core value LDR x4, =_tx_thread_smp_protect_wait_list_head // Get the address of the head @@ -50,53 +50,55 @@ ADD w5, w5, #1 // Increment the head /* Did we wrap? */ - /* if (_tx_thread_smp_protect_wait_list_head == TX_THREAD_SMP_MAX_CORES + 1) - { */ + // if (_tx_thread_smp_protect_wait_list_head == TX_THREAD_SMP_MAX_CORES + 1) + // { LDR x3, =_tx_thread_smp_protect_wait_list_size // Load address of core list size LDR w3, [x3] // Load the max cores value CMP w5, w3 // Compare the head to it BNE _store_new_head\@ // Are we at the max? - /* _tx_thread_smp_protect_wait_list_head = 0; */ + // _tx_thread_smp_protect_wait_list_head = 0; EOR w5, w5, w5 // We're at the max. Set it to zero - /* } */ + // } _store_new_head\@: STR w5, [x4] // Store the new head /* We have the lock! */ - /* return; */ + DMB ISH // Ensure write to protection finishes + + // return; .endm .macro _tx_thread_smp_protect_wait_list_lock_get -/* VOID _tx_thread_smp_protect_wait_list_lock_get() -{ */ +// VOID _tx_thread_smp_protect_wait_list_lock_get() +// { /* We do this until we have the lock. */ - /* while (1) - { */ + // while (1) + // { _tx_thread_smp_protect_wait_list_lock_get__try_to_get_lock\@: - /* Is the list lock available? */ - /* _tx_thread_smp_protect_wait_list_lock_protect_in_force = load_exclusive(&_tx_thread_smp_protect_wait_list_lock_protect_in_force); */ + // Is the list lock available? */ + // _tx_thread_smp_protect_wait_list_lock_protect_in_force = load_exclusive(&_tx_thread_smp_protect_wait_list_lock_protect_in_force); LDR x1, =_tx_thread_smp_protect_wait_list_lock_protect_in_force LDAXR w2, [x1] // Pickup the protection flag - /* if (protect_in_force == 0) - { */ + // if (protect_in_force == 0) + // { CMP w2, #0 BNE _tx_thread_smp_protect_wait_list_lock_get__try_to_get_lock\@ // No, protection not available /* Try to get the list. */ - /* int status = store_exclusive(&_tx_thread_smp_protect_wait_list_lock_protect_in_force, 1); */ + // int status = store_exclusive(&_tx_thread_smp_protect_wait_list_lock_protect_in_force, 1); MOV w2, #1 // Build lock value STXR w3, w2, [x1] // Attempt to get the protection @@ -107,17 +109,17 @@ _tx_thread_smp_protect_wait_list_lock_get__try_to_get_lock\@: BNE _tx_thread_smp_protect_wait_list_lock_get__try_to_get_lock\@ // Did it fail? If so, try again. /* We have the lock! */ - /* return; */ + // return; .endm .macro _tx_thread_smp_protect_wait_list_add -/* VOID _tx_thread_smp_protect_wait_list_add(UINT new_core) -{ */ +// VOID _tx_thread_smp_protect_wait_list_add(UINT new_core) +// { /* We're about to modify the list, so get the list lock. */ - /* _tx_thread_smp_protect_wait_list_lock_get(); */ + // _tx_thread_smp_protect_wait_list_lock_get(); STP x1, x2, [sp, #-16]! // Save registers we'll be using @@ -126,7 +128,7 @@ _tx_thread_smp_protect_wait_list_lock_get__try_to_get_lock\@: LDP x1, x2, [sp], #16 /* Add this core. */ - /* _tx_thread_smp_protect_wait_list[_tx_thread_smp_protect_wait_list_tail++] = new_core; */ + // _tx_thread_smp_protect_wait_list[_tx_thread_smp_protect_wait_list_tail++] = new_core; LDR x3, =_tx_thread_smp_protect_wait_list_tail // Get the address of the tail LDR w4, [x3] // Get the value of tail @@ -135,64 +137,66 @@ _tx_thread_smp_protect_wait_list_lock_get__try_to_get_lock\@: ADD w4, w4, #1 // Increment the tail /* Did we wrap? */ - /* if (_tx_thread_smp_protect_wait_list_tail == _tx_thread_smp_protect_wait_list_size) - { */ + // if (_tx_thread_smp_protect_wait_list_tail == _tx_thread_smp_protect_wait_list_size) + // { LDR x5, =_tx_thread_smp_protect_wait_list_size // Load max cores address LDR w5, [x5] // Load max cores value CMP w4, w5 // Compare max cores to tail BNE _tx_thread_smp_protect_wait_list_add__no_wrap\@ // Did we wrap? - /* _tx_thread_smp_protect_wait_list_tail = 0; */ + // _tx_thread_smp_protect_wait_list_tail = 0; MOV w4, #0 - /* } */ + // } _tx_thread_smp_protect_wait_list_add__no_wrap\@: STR w4, [x3] // Store the new tail value. + DMB ISH // Ensure that accesses to shared resource have completed /* Release the list lock. */ - /* _tx_thread_smp_protect_wait_list_lock_protect_in_force = 0; */ + // _tx_thread_smp_protect_wait_list_lock_protect_in_force = 0; MOV w3, #0 // Build lock value LDR x4, =_tx_thread_smp_protect_wait_list_lock_protect_in_force STR w3, [x4] // Store the new value + DMB ISH // Ensure write to protection finishes .endm .macro _tx_thread_smp_protect_wait_list_remove -/* VOID _tx_thread_smp_protect_wait_list_remove(UINT core) -{ */ +// VOID _tx_thread_smp_protect_wait_list_remove(UINT core) +// { /* Get the core index. */ - /* UINT core_index; - for (core_index = 0;; core_index++) */ + // UINT core_index; + // for (core_index = 0;; core_index++) EOR w4, w4, w4 // Clear for 'core_index' LDR x2, =_tx_thread_smp_protect_wait_list // Get the address of the list - /* { */ + // { _tx_thread_smp_protect_wait_list_remove__check_cur_core\@: /* Is this the core? */ - /* if (_tx_thread_smp_protect_wait_list[core_index] == core) - { - break; */ + // if (_tx_thread_smp_protect_wait_list[core_index] == core) + // { + // break; LDR w3, [x2, x4, LSL #2] // Get the value at the current index CMP w3, w8 // Did we find the core? BEQ _tx_thread_smp_protect_wait_list_remove__found_core\@ - /* } */ + // } ADD w4, w4, #1 // Increment cur index B _tx_thread_smp_protect_wait_list_remove__check_cur_core\@ // Restart the loop - /* } */ + // } _tx_thread_smp_protect_wait_list_remove__found_core\@: @@ -200,15 +204,15 @@ _tx_thread_smp_protect_wait_list_remove__found_core\@: core could be simultaneously adding (a core is simultaneously trying to get the inter-core lock) or removing (a core is simultaneously being preempted, like what is currently happening). */ - /* _tx_thread_smp_protect_wait_list_lock_get(); */ + // _tx_thread_smp_protect_wait_list_lock_get(); MOV x6, x1 _tx_thread_smp_protect_wait_list_lock_get MOV x1, x6 /* We remove by shifting. */ - /* while (core_index != _tx_thread_smp_protect_wait_list_tail) - { */ + // while (core_index != _tx_thread_smp_protect_wait_list_tail) + // { _tx_thread_smp_protect_wait_list_remove__compare_index_to_tail\@: @@ -217,76 +221,78 @@ _tx_thread_smp_protect_wait_list_remove__compare_index_to_tail\@: CMP w4, w2 // Compare cur index and tail BEQ _tx_thread_smp_protect_wait_list_remove__removed\@ - /* UINT next_index = core_index + 1; */ + // UINT next_index = core_index + 1; MOV w2, w4 // Move current index to next index register ADD w2, w2, #1 // Add 1 - /* if (next_index == _tx_thread_smp_protect_wait_list_size) - { */ + // if (next_index == _tx_thread_smp_protect_wait_list_size) + // { LDR x3, =_tx_thread_smp_protect_wait_list_size LDR w3, [x3] CMP w2, w3 BNE _tx_thread_smp_protect_wait_list_remove__next_index_no_wrap\@ - /* next_index = 0; */ + // next_index = 0; MOV w2, #0 - /* } */ + // } _tx_thread_smp_protect_wait_list_remove__next_index_no_wrap\@: - /* list_cores[core_index] = list_cores[next_index]; */ + // list_cores[core_index] = list_cores[next_index]; LDR x5, =_tx_thread_smp_protect_wait_list // Get the address of the list LDR w3, [x5, x2, LSL #2] // Get the value at the next index STR w3, [x5, x4, LSL #2] // Store the value at the current index - /* core_index = next_index; */ + // core_index = next_index; MOV w4, w2 B _tx_thread_smp_protect_wait_list_remove__compare_index_to_tail\@ - /* } */ + // } _tx_thread_smp_protect_wait_list_remove__removed\@: /* Now update the tail. */ - /* if (_tx_thread_smp_protect_wait_list_tail == 0) - { */ + // if (_tx_thread_smp_protect_wait_list_tail == 0) + // { LDR x5, =_tx_thread_smp_protect_wait_list_tail // Load tail address LDR w4, [x5] // Load tail value CMP w4, #0 BNE _tx_thread_smp_protect_wait_list_remove__tail_not_zero\@ - /* _tx_thread_smp_protect_wait_list_tail = _tx_thread_smp_protect_wait_list_size; */ + // _tx_thread_smp_protect_wait_list_tail = _tx_thread_smp_protect_wait_list_size; LDR x2, =_tx_thread_smp_protect_wait_list_size LDR w4, [x2] - /* } */ + // } _tx_thread_smp_protect_wait_list_remove__tail_not_zero\@: - /* _tx_thread_smp_protect_wait_list_tail--; */ + // _tx_thread_smp_protect_wait_list_tail--; SUB w4, w4, #1 STR w4, [x5] // Store new tail value + DMB ISH // Ensure that accesses to shared resource have completed /* Release the list lock. */ - /* _tx_thread_smp_protect_wait_list_lock_protect_in_force = 0; */ + // _tx_thread_smp_protect_wait_list_lock_protect_in_force = 0; MOV w2, #0 // Build lock value LDR x4, =_tx_thread_smp_protect_wait_list_lock_protect_in_force // Load lock address STR w2, [x4] // Store the new value + DMB ISH // Ensure write to protection finishes /* We're no longer waiting. Note that this should be zero since, again, this function is only called when a thread preemption is occurring. */ - /* _tx_thread_smp_protect_wait_counts[core]--; */ + // _tx_thread_smp_protect_wait_counts[core]--; LDR x4, =_tx_thread_smp_protect_wait_counts // Load wait list counts LDR w2, [x4, x8, LSL #2] // Load waiting value SUB w2, w2, #1 // Subtract 1 diff --git a/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_smp_unprotect.S b/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_smp_unprotect.S index dfd77db1..c53075ae 100644 --- a/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_smp_unprotect.S +++ b/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_smp_unprotect.S @@ -27,8 +27,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_smp_unprotect Cortex-A35-SMP/GNU */ -/* 6.1 */ +/* _tx_thread_smp_unprotect Cortex-A35-SMP/GCC */ +/* 6.1.9 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -61,6 +61,9 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 10-15-2021 Andres Mlinar Updated comments, */ +/* added ARMv8.2-A support, */ +/* resulting in version 6.1.9 */ /* */ /**************************************************************************/ .global _tx_thread_smp_unprotect @@ -69,10 +72,17 @@ _tx_thread_smp_unprotect: MSR DAIFSet, 0x3 // Lockout interrupts MRS x1, MPIDR_EL1 // Pickup the core ID +#ifdef TX_ARMV8_2 +#if TX_THREAD_SMP_CLUSTERS > 1 + UBFX x2, x1, #16, #8 // Isolate cluster ID +#endif + UBFX x1, x1, #8, #8 // Isolate core ID +#else #if TX_THREAD_SMP_CLUSTERS > 1 UBFX x2, x1, #8, #8 // Isolate cluster ID #endif UBFX x1, x1, #0, #8 // Isolate core ID +#endif #if TX_THREAD_SMP_CLUSTERS > 1 ADDS x1, x1, x2, LSL #2 // Calculate CPU ID #endif @@ -114,4 +124,3 @@ _still_protected: #endif MSR DAIF, x0 // Restore interrupt posture RET - diff --git a/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_timeout.c b/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_timeout.c index c8710f9d..00f48e14 100644 --- a/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_timeout.c +++ b/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_timeout.c @@ -12,8 +12,8 @@ /**************************************************************************/ /**************************************************************************/ -/** */ -/** ThreadX Component */ +/** */ +/** ThreadX Component */ /** */ /** Thread */ /** */ @@ -79,7 +79,7 @@ VOID _tx_thread_timeout(ULONG timeout_input) TX_INTERRUPT_SAVE_AREA -TX_THREAD *thread_ptr; +TX_THREAD *thread_ptr; VOID (*suspend_cleanup)(struct TX_THREAD_STRUCT *suspend_thread_ptr, ULONG suspension_sequence); ULONG suspension_sequence; @@ -126,7 +126,7 @@ ULONG suspension_sequence; /* Increment the number of timeouts for this thread. */ thread_ptr -> tx_thread_performance_timeout_count++; #endif - + /* Pickup the cleanup routine address. */ suspend_cleanup = thread_ptr -> tx_thread_suspend_cleanup; @@ -162,4 +162,3 @@ ULONG suspension_sequence; #endif } } - diff --git a/ports_module/cortex_a7/ac5/inc/tx_port.h b/ports_module/cortex_a7/ac5/inc/tx_port.h index 15fdff8c..38cb7a87 100644 --- a/ports_module/cortex_a7/ac5/inc/tx_port.h +++ b/ports_module/cortex_a7/ac5/inc/tx_port.h @@ -345,7 +345,7 @@ void tx_thread_vfp_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-A7/AC5 Version 6.1.6 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-A7/AC5 Version 6.1.9 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_module/cortex_a7/ac5/inc/txm_module_port.h b/ports_module/cortex_a7/ac5/inc/txm_module_port.h index a66673df..bc1aac48 100644 --- a/ports_module/cortex_a7/ac5/inc/txm_module_port.h +++ b/ports_module/cortex_a7/ac5/inc/txm_module_port.h @@ -407,7 +407,7 @@ UINT _txm_module_manager_inside_data_check(ULONG pointer); #define TXM_MODULE_MANAGER_VERSION_ID \ CHAR _txm_module_manager_version_id[] = \ - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-A7/MMU/AC5 Version 6.1 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-A7/MMU/AC5 Version 6.1.9 *"; #endif diff --git a/ports_module/cortex_m23/ac6/inc/tx_port.h b/ports_module/cortex_m23/ac6/inc/tx_port.h index aa34ec45..cf82d164 100644 --- a/ports_module/cortex_m23/ac6/inc/tx_port.h +++ b/ports_module/cortex_m23/ac6/inc/tx_port.h @@ -573,7 +573,7 @@ unsigned int was_masked; #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M23/AC6 Version 6.1.6 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M23/AC6 Version 6.1.9 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports_module/cortex_m23/ac6/inc/txm_module_port.h b/ports_module/cortex_m23/ac6/inc/txm_module_port.h index 16645dbb..cdc1b1bd 100644 --- a/ports_module/cortex_m23/ac6/inc/txm_module_port.h +++ b/ports_module/cortex_m23/ac6/inc/txm_module_port.h @@ -347,6 +347,6 @@ ALIGN_TYPE _txm_module_manager_port_dispatch(TXM_MODULE_INSTANCE *module_instanc #define TXM_MODULE_MANAGER_VERSION_ID \ CHAR _txm_module_manager_version_id[] = \ - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-M23/AC6 Version 6.1.6 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-M23/AC6 Version 6.1.9 *"; #endif diff --git a/ports_module/cortex_m23/gnu/inc/tx_port.h b/ports_module/cortex_m23/gnu/inc/tx_port.h index 83923e7f..eca300d7 100644 --- a/ports_module/cortex_m23/gnu/inc/tx_port.h +++ b/ports_module/cortex_m23/gnu/inc/tx_port.h @@ -483,7 +483,7 @@ unsigned int interrupt_save; #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M23/GNU Version 6.1.6 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M23/GNU Version 6.1.9 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports_module/cortex_m23/gnu/inc/txm_module_port.h b/ports_module/cortex_m23/gnu/inc/txm_module_port.h index 5d2de2a9..9017e38a 100644 --- a/ports_module/cortex_m23/gnu/inc/txm_module_port.h +++ b/ports_module/cortex_m23/gnu/inc/txm_module_port.h @@ -347,6 +347,6 @@ ALIGN_TYPE _txm_module_manager_port_dispatch(TXM_MODULE_INSTANCE *module_instanc #define TXM_MODULE_MANAGER_VERSION_ID \ CHAR _txm_module_manager_version_id[] = \ - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-M23/GNU Version 6.1.6 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-M23/GNU Version 6.1.9 *"; #endif diff --git a/ports_module/cortex_m23/iar/inc/tx_port.h b/ports_module/cortex_m23/iar/inc/tx_port.h index 54c6d6ec..29a4b245 100644 --- a/ports_module/cortex_m23/iar/inc/tx_port.h +++ b/ports_module/cortex_m23/iar/inc/tx_port.h @@ -701,7 +701,7 @@ VOID _tx_thread_interrupt_restore(UIN #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Modules ARMv8-M Version 6.1.6 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Modules ARMv8-M Version 6.1.9 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports_module/cortex_m23/iar/inc/txm_module_port.h b/ports_module/cortex_m23/iar/inc/txm_module_port.h index 2b1729af..088efd4b 100644 --- a/ports_module/cortex_m23/iar/inc/txm_module_port.h +++ b/ports_module/cortex_m23/iar/inc/txm_module_port.h @@ -350,6 +350,6 @@ ALIGN_TYPE _txm_module_manager_port_dispatch(TXM_MODULE_INSTANCE *module_instanc #define TXM_MODULE_MANAGER_VERSION_ID \ CHAR _txm_module_manager_version_id[] = \ - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-M23/IAR Version 6.1.6 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-M23/IAR Version 6.1.9 *"; #endif diff --git a/ports_module/cortex_m3/ac5/inc/tx_port.h b/ports_module/cortex_m3/ac5/inc/tx_port.h index b190243b..a693d09e 100644 --- a/ports_module/cortex_m3/ac5/inc/tx_port.h +++ b/ports_module/cortex_m3/ac5/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h Cortex-M3/AC5 */ -/* 6.1.6 */ +/* 6.1.9 */ /* */ /* AUTHOR */ /* */ @@ -47,10 +47,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ -/* macro definition, */ -/* resulting in version 6.1.6 */ +/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ /* */ /**************************************************************************/ @@ -142,7 +139,7 @@ typedef unsigned short USHORT; /* Define the port specific options for the _tx_build_options variable. This variable indicates how the ThreadX library was built. */ -#define TX_PORT_SPECIFIC_BUILD_OPTIONS 0 +#define TX_PORT_SPECIFIC_BUILD_OPTIONS (0) /* Define the in-line initialization constant so that modules with in-line @@ -344,8 +341,6 @@ void _tx_vfp_access(void); #endif - - /* Define the ThreadX object creation extensions for the remaining objects. */ #define TX_BLOCK_POOL_CREATE_EXTENSION(pool_ptr) @@ -386,7 +381,7 @@ ULONG _tx_misra_ipsr_get(VOID); zero after initialization for Cortex-M ports. */ #ifndef TX_THREAD_SYSTEM_RETURN_CHECK -#define TX_THREAD_SYSTEM_RETURN_CHECK(c) (c) = ((ULONG) _tx_thread_preempt_disable); +#define TX_THREAD_SYSTEM_RETURN_CHECK(c) (c) = ((ULONG) _tx_thread_preempt_disable); #endif @@ -452,11 +447,18 @@ unsigned int was_masked; #endif +/* Define FPU extension for the Cortex-M3. Each is assumed to be called in the context of the executing + thread. These are no longer needed, but are preserved for backward compatibility only. */ + +void tx_thread_fpu_enable(void); +void tx_thread_fpu_disable(void); + + /* Define the version ID of ThreadX. This may be utilized by the application. */ #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M3/AC5 Version 6.1 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M3/AC5 Version 6.1.9 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; @@ -467,7 +469,3 @@ extern CHAR _tx_version_id[]; #endif - - - - diff --git a/ports_module/cortex_m3/ac5/inc/txm_module_port.h b/ports_module/cortex_m3/ac5/inc/txm_module_port.h index 9c2bda5a..d3bcdee8 100644 --- a/ports_module/cortex_m3/ac5/inc/txm_module_port.h +++ b/ports_module/cortex_m3/ac5/inc/txm_module_port.h @@ -25,8 +25,8 @@ /* */ /* APPLICATION INTERFACE DEFINITION RELEASE */ /* */ -/* txm_module_port.h Cortex-M3/MPU/AC5 */ -/* 6.1.6 */ +/* txm_module_port.h Cortex-M3/AC5 */ +/* 6.1.9 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -40,10 +40,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 04-02-2021 Scott Larson Modified comment(s) and */ -/* added check for overflow, */ -/* resulting in version 6.1.6 */ +/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ /* */ /**************************************************************************/ @@ -94,16 +91,26 @@ The following extensions must also be defined in tx_port.h: VOID (*tx_timer_module_expiration_function)(ULONG id); */ - -/* Size of module heap. */ -#define TXM_MODULE_HEAP_SIZE 512 - - /* Define the kernel stack size for a module thread. */ #ifndef TXM_MODULE_KERNEL_STACK_SIZE #define TXM_MODULE_KERNEL_STACK_SIZE 768 #endif +/* For the following 3 access control settings, change TEX and C, B, S (bits 21 through 16 of MPU_RASR) + * to reflect your system memory attributes (cache, shareable, memory type). */ +/* Code region access control: privileged read-only, outer & inner write-back, normal memory, shareable. */ +#ifndef TXM_MODULE_MPU_CODE_ACCESS_CONTROL +#define TXM_MODULE_MPU_CODE_ACCESS_CONTROL 0x06070000 +#endif +/* Data region access control: execute never, read/write, outer & inner write-back, normal memory, shareable. */ +#ifndef TXM_MODULE_MPU_DATA_ACCESS_CONTROL +#define TXM_MODULE_MPU_DATA_ACCESS_CONTROL 0x13070000 +#endif +/* Shared region access control: execute never, read-only, outer & inner write-back, normal memory, shareable. */ +#ifndef TXM_MODULE_MPU_SHARED_ACCESS_CONTROL +#define TXM_MODULE_MPU_SHARED_ACCESS_CONTROL 0x12070000 +#endif + /* Define constants specific to the tools the module can be built with for this particular modules port. */ #define TXM_MODULE_IAR_COMPILER 0x00000000 @@ -154,12 +161,47 @@ The following extensions must also be defined in tx_port.h: /* Define other module port-specific constants. */ -/* Define INLINE_DECLARE to inline for AC5 compiler. */ +/* Define INLINE_DECLARE to inline for ARM compiler. */ #define INLINE_DECLARE inline +#ifdef TXM_MODULE_MANAGER_16_MPU + /* Define the number of MPU entries assigned to the code and data sections. - On Cortex-M3 parts, there are 8 total entries. ThreadX uses one for access + On some Cortex-M7 parts, there are 16 total entries. ThreadX uses one for access + to the kernel entry function, thus 15 remain for code and data protection. */ +#define TXM_MODULE_MPU_TOTAL_ENTRIES 16 +#define TXM_MODULE_MPU_CODE_ENTRIES 4 +#define TXM_MODULE_MPU_DATA_ENTRIES 4 +#define TXM_MODULE_MPU_SHARED_ENTRIES 3 + +#define TXM_MODULE_MPU_KERNEL_ENTRY_INDEX 0 +#define TXM_MODULE_MPU_SHARED_INDEX 9 + +#define TXM_ENABLE_REGION 0x01 + +/* There are 2 registers to set up each MPU region: MPU_RBAR, MPU_RASR. */ +typedef struct TXM_MODULE_MPU_INFO_STRUCT +{ + ULONG txm_module_mpu_region_address; + ULONG txm_module_mpu_region_attribute_size; +} TXM_MODULE_MPU_INFO; +/* Shared memory region attributes. */ +#define TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE 1 +#define TXM_MODULE_MANAGER_ATTRIBUTE_WRITE_MPU_BIT 0x01000000 + +/* Define the port-extensions to the module manager instance structure. */ + +#define TXM_MODULE_MANAGER_PORT_EXTENSION \ + TXM_MODULE_MPU_INFO txm_module_instance_mpu_registers[TXM_MODULE_MPU_TOTAL_ENTRIES]; \ + ULONG txm_module_instance_shared_memory_count; \ + ULONG txm_module_instance_shared_memory_address[TXM_MODULE_MPU_SHARED_ENTRIES]; \ + ULONG txm_module_instance_shared_memory_length[TXM_MODULE_MPU_SHARED_ENTRIES]; + +#else /* TXM_MODULE_MANAGER_16_MPU is not defined */ + +/* Define the number of MPU entries assigned to the code and data sections. + On Cortex-M3, M4, and some M7 parts, there are 8 total entries. ThreadX uses one for access to the kernel entry function, thus 7 remain for code and data protection. */ #define TXM_MODULE_MANAGER_CODE_MPU_ENTRIES 4 #define TXM_MODULE_MANAGER_DATA_MPU_ENTRIES 3 @@ -177,6 +219,7 @@ The following extensions must also be defined in tx_port.h: ULONG txm_module_instance_shared_memory_address; \ ULONG txm_module_instance_shared_memory_length; +#endif /* TXM_MODULE_MANAGER_16_MPU */ /* Define the memory fault information structure that is populated when a memory fault occurs. */ @@ -299,6 +342,10 @@ typedef struct TXM_MODULE_MANAGER_MEMORY_FAULT_INFO_STRUCT /* Define the macros to perform port-specific checks when passing pointers to the kernel. */ /* Define macro to make sure object is inside the module's data. */ +#ifdef TXM_MODULE_MANAGER_16_MPU +#define TXM_MODULE_MANAGER_CHECK_INSIDE_DATA(module_instance, obj_ptr, obj_size) \ + _txm_module_manager_inside_data_check(module_instance, obj_ptr, obj_size) +#else #define TXM_MODULE_MANAGER_CHECK_INSIDE_DATA(module_instance, obj_ptr, obj_size) \ /* Check for overflow. */ \ (((obj_ptr) < ((obj_ptr) + (obj_size))) && \ @@ -308,7 +355,7 @@ typedef struct TXM_MODULE_MANAGER_MEMORY_FAULT_INFO_STRUCT /* Check if it's inside shared memory. */ \ (((obj_ptr) >= (ALIGN_TYPE) module_instance -> txm_module_instance_shared_memory_address) && \ (((obj_ptr) + (obj_size)) <= (ALIGN_TYPE) (module_instance -> txm_module_instance_shared_memory_address + module_instance -> txm_module_instance_shared_memory_length))))) - +#endif /* Define some internal prototypes to this module port. */ @@ -324,10 +371,11 @@ UINT _txm_module_manager_memory_fault_notify(VOID (*notify_function)(TX_THREAD VOID _txm_module_manager_mm_register_setup(TXM_MODULE_INSTANCE *module_instance); \ ULONG _txm_power_of_two_block_size(ULONG size); \ ULONG _txm_module_manager_calculate_srd_bits(ULONG block_size, ULONG length); \ -ULONG _txm_module_manager_region_size_get(ULONG block_size); +ULONG _txm_module_manager_region_size_get(ULONG block_size); \ +UINT _txm_module_manager_inside_data_check(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE obj_ptr, UINT obj_size); #define TXM_MODULE_MANAGER_VERSION_ID \ -CHAR _txm_module_manager_version_id[] = \ - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-M3/MPU/AC5 Version 6.1.8 *"; +CHAR _txm_module_manager_version_id[] = \ + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-M3/AC5 Version 6.1.9 *"; #endif diff --git a/ports_module/cortex_m3/ac5/module_lib/src/txm_module_initialize.S b/ports_module/cortex_m3/ac5/module_lib/src/txm_module_initialize.s index 46343731..39f2d84b 100644 --- a/ports_module/cortex_m3/ac5/module_lib/src/txm_module_initialize.S +++ b/ports_module/cortex_m3/ac5/module_lib/src/txm_module_initialize.s @@ -29,8 +29,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _txm_module_initialize Cortex-M3/MPU/AC5 */ -/* 6.1 */ +/* _txm_module_initialize Cortex-M3/AC5 */ +/* 6.1.9 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -59,7 +59,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ /* */ /**************************************************************************/ // VOID _txm_module_initialize(VOID) diff --git a/ports_module/cortex_m3/ac5/module_lib/src/txm_module_thread_shell_entry.c b/ports_module/cortex_m3/ac5/module_lib/src/txm_module_thread_shell_entry.c index 0dc4f51e..15ac00fa 100644 --- a/ports_module/cortex_m3/ac5/module_lib/src/txm_module_thread_shell_entry.c +++ b/ports_module/cortex_m3/ac5/module_lib/src/txm_module_thread_shell_entry.c @@ -44,7 +44,9 @@ TXM_MODULE_THREAD_ENTRY_INFO *_txm_module_entry_info; ULONG (*_txm_module_kernel_call_dispatcher)(ULONG kernel_request, ULONG param_1, ULONG param_2, ULONG param3); -/* Define the ARM cstartup code. */ +/* Define the startup code that clears the uninitialized global data and sets up the + preset global variables. */ + extern VOID _txm_module_initialize(VOID); __align(8) UCHAR txm_heap[TXM_MODULE_HEAP_SIZE]; @@ -53,15 +55,15 @@ __align(8) UCHAR txm_heap[TXM_MODULE_HEAP_SIZE]; /* */ /* FUNCTION RELEASE */ /* */ -/* _txm_module_thread_shell_entry Cortex-M3/MPU/AC5 */ -/* 6.1 */ +/* _txm_module_thread_shell_entry Cortex-M3/AC5 */ +/* 6.1.9 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ /* */ /* DESCRIPTION */ /* */ -/* This function calls the specified entry function of the thread. It */ +/* This function calls the specified entry function of the thread. It */ /* also provides a place for the thread's entry function to return. */ /* If the thread returns, this function places the thread in a */ /* "COMPLETED" state. */ @@ -90,7 +92,7 @@ __align(8) UCHAR txm_heap[TXM_MODULE_HEAP_SIZE]; /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ /* */ /**************************************************************************/ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_ENTRY_INFO *thread_info) @@ -105,7 +107,7 @@ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_EN execution. If not, simply skip the C startup code. */ if (thread_info -> txm_module_thread_entry_info_start_thread) { - /* Initialize the ARM C environment. */ + /* Initialize the C environment. */ _txm_module_initialize(); /* Save the entry info pointer, for later use. */ @@ -170,4 +172,3 @@ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_EN TX_SAFETY_CRITICAL_EXCEPTION(__FILE__, __LINE__, 0); #endif } - diff --git a/ports_module/cortex_m4/ac5/module_manager/src/tx_thread_context_restore.S b/ports_module/cortex_m3/ac5/module_manager/src/tx_thread_context_restore.s index 1159ea66..aa2f30a4 100644 --- a/ports_module/cortex_m4/ac5/module_manager/src/tx_thread_context_restore.S +++ b/ports_module/cortex_m3/ac5/module_manager/src/tx_thread_context_restore.s @@ -30,8 +30,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_context_restore Cortex-Mx/AC5 */ -/* 6.1.8 */ +/* _tx_thread_context_restore Cortex-M3/AC5 */ +/* 6.1.7 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -61,7 +61,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ +/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ /* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) diff --git a/ports_module/cortex_m7/ac5/module_manager/src/tx_thread_context_save.S b/ports_module/cortex_m3/ac5/module_manager/src/tx_thread_context_save.s index d8ee75a4..78cbc3c9 100644 --- a/ports_module/cortex_m7/ac5/module_manager/src/tx_thread_context_save.S +++ b/ports_module/cortex_m3/ac5/module_manager/src/tx_thread_context_save.s @@ -30,8 +30,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_context_save Cortex-Mx/AC5 */ -/* 6.1.8 */ +/* _tx_thread_context_save Cortex-M3/AC5 */ +/* 6.1.7 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -61,7 +61,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ +/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ /* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) diff --git a/ports_module/cortex_m7/ac5/module_manager/src/tx_thread_interrupt_control.S b/ports_module/cortex_m3/ac5/module_manager/src/tx_thread_interrupt_control.s index 4c5e1c33..bca3df55 100644 --- a/ports_module/cortex_m7/ac5/module_manager/src/tx_thread_interrupt_control.S +++ b/ports_module/cortex_m3/ac5/module_manager/src/tx_thread_interrupt_control.s @@ -25,8 +25,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_interrupt_control Cortex-Mx/AC5 */ -/* 6.1.8 */ +/* _tx_thread_interrupt_control Cortex-M3/AC5 */ +/* 6.1.7 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -56,7 +56,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ +/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ /* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) diff --git a/ports_module/cortex_m3/ac5/module_manager/src/tx_thread_interrupt_disable.S b/ports_module/cortex_m3/ac5/module_manager/src/tx_thread_interrupt_disable.s index 88e6a864..6a9c4c8e 100644 --- a/ports_module/cortex_m3/ac5/module_manager/src/tx_thread_interrupt_disable.S +++ b/ports_module/cortex_m3/ac5/module_manager/src/tx_thread_interrupt_disable.s @@ -25,8 +25,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_interrupt_disable Cortex-Mx/AC5 */ -/* 6.1.8 */ +/* _tx_thread_interrupt_disable Cortex-M3/AC5 */ +/* 6.1.7 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -56,7 +56,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ +/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ /* */ /**************************************************************************/ // UINT _tx_thread_interrupt_disable(VOID) diff --git a/ports_module/cortex_m7/ac5/module_manager/src/tx_thread_interrupt_restore.S b/ports_module/cortex_m3/ac5/module_manager/src/tx_thread_interrupt_restore.s index 22340c21..ca929f18 100644 --- a/ports_module/cortex_m7/ac5/module_manager/src/tx_thread_interrupt_restore.S +++ b/ports_module/cortex_m3/ac5/module_manager/src/tx_thread_interrupt_restore.s @@ -25,8 +25,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_interrupt_restore Cortex-Mx/AC5 */ -/* 6.1.8 */ +/* _tx_thread_interrupt_restore Cortex-M3/AC5 */ +/* 6.1.7 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -56,7 +56,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ +/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ /* */ /**************************************************************************/ // VOID _tx_thread_interrupt_restore(UINT previous_posture) diff --git a/ports_module/cortex_m7/ac5/module_manager/src/tx_thread_schedule.S b/ports_module/cortex_m3/ac5/module_manager/src/tx_thread_schedule.s index 24ea67f8..1048802a 100644 --- a/ports_module/cortex_m7/ac5/module_manager/src/tx_thread_schedule.S +++ b/ports_module/cortex_m3/ac5/module_manager/src/tx_thread_schedule.s @@ -39,8 +39,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_schedule Cortex-M7/MPU/AC5 */ -/* 6.1.7 */ +/* _tx_thread_schedule Cortex-M3/AC5 */ +/* 6.1.9 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -73,15 +73,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 11-09-2020 Scott Larson Modified comment(s), arrange */ -/* code to fix link error when */ -/* VFP is enabled, resulting */ -/* in version 6.1.2 */ -/* 06-02-2021 Scott Larson Fixed extended stack handling */ -/* when calling kernel APIs, */ -/* added support for 8 MPU, */ -/* resulting in version 6.1.7 */ +/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ /* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) @@ -360,7 +352,7 @@ __tx_ts_restore // Use alias registers to quickly load MPU ADD r0, r0, #100 // Build address of MPU register start in thread control block -#ifndef TXM_MODULE_MANAGER_8_MPU +#ifdef TXM_MODULE_MANAGER_16_MPU LDM r0!,{r2-r9} // Load MPU regions 0-3 STM r1,{r2-r9} // Store MPU regions 0-3 LDM r0!,{r2-r9} // Load MPU regions 4-7 diff --git a/ports_module/cortex_m3/ac5/module_manager/src/tx_thread_stack_build.S b/ports_module/cortex_m3/ac5/module_manager/src/tx_thread_stack_build.s index 11effa55..3c263ba8 100644 --- a/ports_module/cortex_m3/ac5/module_manager/src/tx_thread_stack_build.S +++ b/ports_module/cortex_m3/ac5/module_manager/src/tx_thread_stack_build.s @@ -25,8 +25,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_stack_build Cortex-Mx/AC5 */ -/* 6.1.8 */ +/* _tx_thread_stack_build Cortex-M3/AC5 */ +/* 6.1.7 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -58,7 +58,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ +/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ /* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) diff --git a/ports_module/cortex_m7/ac5/module_manager/src/tx_thread_system_return.S b/ports_module/cortex_m3/ac5/module_manager/src/tx_thread_system_return.s index 0ab4ae36..6b7d3ec3 100644 --- a/ports_module/cortex_m7/ac5/module_manager/src/tx_thread_system_return.S +++ b/ports_module/cortex_m3/ac5/module_manager/src/tx_thread_system_return.s @@ -25,8 +25,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_system_return Cortex-Mx/AC5 */ -/* 6.1.8 */ +/* _tx_thread_system_return Cortex-M3/AC5 */ +/* 6.1.7 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -58,7 +58,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ +/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ /* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) diff --git a/ports_module/cortex_m7/ac5/module_manager/src/tx_timer_interrupt.S b/ports_module/cortex_m3/ac5/module_manager/src/tx_timer_interrupt.s index 12fef571..60717ba3 100644 --- a/ports_module/cortex_m7/ac5/module_manager/src/tx_timer_interrupt.S +++ b/ports_module/cortex_m3/ac5/module_manager/src/tx_timer_interrupt.s @@ -39,8 +39,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_timer_interrupt Cortex-Mx/AC5 */ -/* 6.1.8 */ +/* _tx_timer_interrupt Cortex-M3/AC5 */ +/* 6.1.7 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -73,7 +73,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ +/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ /* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) diff --git a/ports_module/cortex_m3/ac5/module_manager/src/txm_module_manager_alignment_adjust.c b/ports_module/cortex_m3/ac5/module_manager/src/txm_module_manager_alignment_adjust.c index acd22562..92e629a8 100644 --- a/ports_module/cortex_m3/ac5/module_manager/src/txm_module_manager_alignment_adjust.c +++ b/ports_module/cortex_m3/ac5/module_manager/src/txm_module_manager_alignment_adjust.c @@ -30,8 +30,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _txm_power_of_two_block_size Cortex-M3/MPU */ -/* 6.1 */ +/* _txm_power_of_two_block_size Cortex-M3 */ +/* 6.1.9 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -61,7 +61,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ /* */ /**************************************************************************/ ULONG _txm_power_of_two_block_size(ULONG size) @@ -93,8 +93,8 @@ ULONG _txm_power_of_two_block_size(ULONG size) /* */ /* FUNCTION RELEASE */ /* */ -/* _txm_module_manager_alignment_adjust Cortex-M3/MPU */ -/* 6.1 */ +/* _txm_module_manager_alignment_adjust Cortex-M3 */ +/* 6.1.9 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -128,7 +128,7 @@ ULONG _txm_power_of_two_block_size(ULONG size) /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ /* */ /**************************************************************************/ VOID _txm_module_manager_alignment_adjust(TXM_MODULE_PREAMBLE *module_preamble, @@ -137,6 +137,53 @@ VOID _txm_module_manager_alignment_adjust(TXM_MODULE_PREAMBLE *module_preamble, ULONG *data_size, ULONG *data_alignment) { +#ifdef TXM_MODULE_MANAGER_16_MPU +ULONG local_code_size; +ULONG local_code_alignment; +ULONG local_data_size; +ULONG local_data_alignment; +ULONG code_size_accum; +ULONG data_size_accum; + + /* Copy the input parameters into local variables for ease of use. */ + local_code_size = *code_size; + local_code_alignment = *code_alignment; + local_data_size = *data_size; + local_data_alignment = *data_alignment; + + /* Determine code block sizes. Minimize the alignment requirement. + There are 4 MPU code entries available. The following is how the code size + will be distributed: + 1. 1/4 of the largest power of two that is greater than or equal to code size. + 2. 1/4 of the largest power of two that is greater than or equal to code size. + 3. Largest power of 2 that fits in the remaining space. + 4. Smallest power of 2 that exceeds the remaining space, minimum 32. */ + local_code_alignment = _txm_power_of_two_block_size(local_code_size) >> 2; + code_size_accum = local_code_alignment + local_code_alignment; + code_size_accum = code_size_accum + (_txm_power_of_two_block_size(local_code_size - code_size_accum) >> 1); + code_size_accum = code_size_accum + _txm_power_of_two_block_size(local_code_size - code_size_accum); + local_code_size = code_size_accum; + + /* Determine data block sizes. Minimize the alignment requirement. + There are 4 MPU data entries available. The following is how the data size + will be distributed: + 1. 1/4 of the largest power of two that is greater than or equal to data size. + 2. 1/4 of the largest power of two that is greater than or equal to data size. + 3. Largest power of 2 that fits in the remaining space. + 4. Smallest power of 2 that exceeds the remaining space, minimum 32. */ + local_data_alignment = _txm_power_of_two_block_size(local_data_size) >> 2; + data_size_accum = local_data_alignment + local_data_alignment; + data_size_accum = data_size_accum + (_txm_power_of_two_block_size(local_data_size - data_size_accum) >> 1); + data_size_accum = data_size_accum + _txm_power_of_two_block_size(local_data_size - data_size_accum); + local_data_size = data_size_accum; + + /* Return all the information to the caller. */ + *code_size = local_code_size; + *code_alignment = local_code_alignment; + *data_size = local_data_size; + *data_alignment = local_data_alignment; + +#else ULONG local_code_size; ULONG local_code_alignment; @@ -396,4 +443,6 @@ ULONG data_size_accum; *code_alignment = local_code_alignment; *data_size = local_data_size; *data_alignment = local_data_alignment; + +#endif } diff --git a/ports_module/cortex_m3/ac5/module_manager/src/txm_module_manager_external_memory_enable.c b/ports_module/cortex_m3/ac5/module_manager/src/txm_module_manager_external_memory_enable.c index 613cb082..cb13e4a6 100644 --- a/ports_module/cortex_m3/ac5/module_manager/src/txm_module_manager_external_memory_enable.c +++ b/ports_module/cortex_m3/ac5/module_manager/src/txm_module_manager_external_memory_enable.c @@ -33,8 +33,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _txm_module_manager_external_memory_enable Cortex-M3/MPU */ -/* 6.1 */ +/* _txm_module_manager_external_memory_enable Cortex-M3 */ +/* 6.1.9 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -70,7 +70,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ /* */ /**************************************************************************/ UINT _txm_module_manager_external_memory_enable(TXM_MODULE_INSTANCE *module_instance, @@ -78,6 +78,117 @@ UINT _txm_module_manager_external_memory_enable(TXM_MODULE_INSTANCE *module_ins ULONG length, UINT attributes) { +#ifdef TXM_MODULE_MANAGER_16_MPU +ULONG block_size; +ULONG region_size; +ULONG srd_bits; +ULONG size_register; +ULONG address; +ULONG shared_index; +ULONG attributes_check = 0; + + /* Determine if the module manager has not been initialized yet. */ + if (_txm_module_manager_ready != TX_TRUE) + { + /* Module manager has not been initialized. */ + return(TX_NOT_AVAILABLE); + } + + /* Determine if the module is valid. */ + if (module_instance == TX_NULL) + { + /* Invalid module pointer. */ + return(TX_PTR_ERROR); + } + + /* Get module manager protection mutex. */ + _tx_mutex_get(&_txm_module_manager_mutex, TX_WAIT_FOREVER); + + /* Determine if the module instance is valid. */ + if (module_instance -> txm_module_instance_id != TXM_MODULE_ID) + { + /* Release the protection mutex. */ + _tx_mutex_put(&_txm_module_manager_mutex); + + /* Invalid module pointer. */ + return(TX_PTR_ERROR); + } + + /* Determine if the module instance is in the loaded state. */ + if (module_instance -> txm_module_instance_state != TXM_MODULE_LOADED) + { + /* Release the protection mutex. */ + _tx_mutex_put(&_txm_module_manager_mutex); + + /* Return error if the module is not ready. */ + return(TX_START_ERROR); + } + + /* Determine if there are shared memory entries available. */ + if(module_instance -> txm_module_instance_shared_memory_count >= TXM_MODULE_MPU_SHARED_ENTRIES) + { + /* Release the protection mutex. */ + _tx_mutex_put(&_txm_module_manager_mutex); + + /* No more entries available. */ + return(TX_NO_MEMORY); + } + + /* Start address and length must adhere to Cortex-M7 MPU. + The address must align with the block size. */ + + block_size = _txm_power_of_two_block_size(length); + address = (ULONG) start_address; + if(address != (address & ~(block_size - 1))) + { + /* Release the protection mutex. */ + _tx_mutex_put(&_txm_module_manager_mutex); + + /* Return alignment error. */ + return(TXM_MODULE_ALIGNMENT_ERROR); + } + + /* At this point, we have a valid address and block size. + Set up MPU registers. */ + + /* Pick up index into shared memory entries. */ + shared_index = TXM_MODULE_MPU_SHARED_INDEX + module_instance -> txm_module_instance_shared_memory_count; + + /* Save address register with address, MPU region, set Valid bit. */ + module_instance -> txm_module_instance_mpu_registers[shared_index].txm_module_mpu_region_address = address | shared_index | 0x10; + + /* Calculate the region size. */ + region_size = (_txm_module_manager_region_size_get(block_size) << 1); + + /* Calculate the subregion bits. */ + srd_bits = _txm_module_manager_calculate_srd_bits(block_size, length); + + /* Generate SRD, size, and enable attributes. */ + size_register = srd_bits | region_size | TXM_ENABLE_REGION | TXM_MODULE_MPU_SHARED_ACCESS_CONTROL; + + /* Check for optional write attribute. */ + if(attributes & TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE) + { + attributes_check = TXM_MODULE_MANAGER_ATTRIBUTE_WRITE_MPU_BIT; + } + + /* Save attribute-size register. */ + module_instance -> txm_module_instance_mpu_registers[shared_index].txm_module_mpu_region_attribute_size = attributes_check | size_register; + + /* Keep track of shared memory address and length in module instance. */ + module_instance -> txm_module_instance_shared_memory_address[module_instance -> txm_module_instance_shared_memory_count] = address; + module_instance -> txm_module_instance_shared_memory_length[module_instance -> txm_module_instance_shared_memory_count] = length; + + /* Increment counter. */ + module_instance -> txm_module_instance_shared_memory_count++; + + /* Release the protection mutex. */ + _tx_mutex_put(&_txm_module_manager_mutex); + + /* Return success. */ + return(TX_SUCCESS); + +#else ULONG block_size; ULONG region_size; @@ -179,4 +290,6 @@ TXM_MODULE_PREAMBLE *module_preamble; /* Return success. */ return(TX_SUCCESS); + +#endif } diff --git a/ports_module/cortex_m3/ac5/module_manager/src/txm_module_manager_memory_fault_handler.c b/ports_module/cortex_m3/ac5/module_manager/src/txm_module_manager_memory_fault_handler.c index b435d107..bcaa98aa 100644 --- a/ports_module/cortex_m3/ac5/module_manager/src/txm_module_manager_memory_fault_handler.c +++ b/ports_module/cortex_m3/ac5/module_manager/src/txm_module_manager_memory_fault_handler.c @@ -45,8 +45,8 @@ TXM_MODULE_MANAGER_FAULT_INFO /* */ /* FUNCTION RELEASE */ /* */ -/* _txm_module_manager_memory_fault_handler Cortex-M3/MPU/AC6 */ -/* 6.1 */ +/* _txm_module_manager_memory_fault_handler Cortex-M3 */ +/* 6.1.9 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -76,7 +76,7 @@ TXM_MODULE_MANAGER_FAULT_INFO /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ /* */ /**************************************************************************/ VOID _txm_module_manager_memory_fault_handler(VOID) diff --git a/ports_module/cortex_m3/ac5/module_manager/src/txm_module_manager_memory_fault_notify.c b/ports_module/cortex_m3/ac5/module_manager/src/txm_module_manager_memory_fault_notify.c index 8a40b3ac..dac86312 100644 --- a/ports_module/cortex_m3/ac5/module_manager/src/txm_module_manager_memory_fault_notify.c +++ b/ports_module/cortex_m3/ac5/module_manager/src/txm_module_manager_memory_fault_notify.c @@ -38,8 +38,8 @@ extern VOID (*_txm_module_manager_fault_notify)(TX_THREAD *, TXM_MODULE_INSTA /* */ /* FUNCTION RELEASE */ /* */ -/* _txm_module_manager_memory_fault_notify Cortex-M3/MPU/AC5 */ -/* 6.1 */ +/* _txm_module_manager_memory_fault_notify Cortex-M3 */ +/* 6.1.9 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -71,7 +71,7 @@ extern VOID (*_txm_module_manager_fault_notify)(TX_THREAD *, TXM_MODULE_INSTA /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ /* */ /**************************************************************************/ UINT _txm_module_manager_memory_fault_notify(VOID (*notify_function)(TX_THREAD *, TXM_MODULE_INSTANCE *)) diff --git a/ports_module/cortex_m3/ac5/module_manager/src/txm_module_manager_mm_register_setup.c b/ports_module/cortex_m3/ac5/module_manager/src/txm_module_manager_mm_register_setup.c index cc0cbd5f..48a14571 100644 --- a/ports_module/cortex_m3/ac5/module_manager/src/txm_module_manager_mm_register_setup.c +++ b/ports_module/cortex_m3/ac5/module_manager/src/txm_module_manager_mm_register_setup.c @@ -30,8 +30,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _txm_module_manager_region_size_get Cortex-M3/MPU */ -/* 6.1 */ +/* _txm_module_manager_region_size_get Cortex-M3 */ +/* 6.1.9 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -61,7 +61,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ /* */ /**************************************************************************/ ULONG _txm_module_manager_region_size_get(ULONG block_size) @@ -152,8 +152,8 @@ ULONG return_value; /* */ /* FUNCTION RELEASE */ /* */ -/* _txm_module_manager_calculate_srd_bits Cortex-M3/MPU */ -/* 6.1 */ +/* _txm_module_manager_calculate_srd_bits Cortex-M3 */ +/* 6.1.9 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -184,7 +184,7 @@ ULONG return_value; /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ /* */ /**************************************************************************/ ULONG _txm_module_manager_calculate_srd_bits(ULONG block_size, ULONG length) @@ -230,16 +230,48 @@ UINT srd_bit_index; /* */ /* FUNCTION RELEASE */ /* */ -/* _txm_module_manager_mm_register_setup Cortex-M3/MPU */ -/* 6.1 */ +/* _txm_module_manager_mm_register_setup Cortex-M3 */ +/* 6.1.9 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ /* */ /* DESCRIPTION */ /* */ -/* This function sets up the Cortex-M3 MPU register definitions based */ -/* on the module's memory characteristics. */ +/* This function sets up the MPU register definitions based on the */ +/* module's memory characteristics. */ +/* */ +/* Default MPU layout: */ +/* Entry Description */ +/* 0 Kernel mode entry */ +/* 1 Module code region */ +/* 2 Module code region */ +/* 3 Module code region */ +/* 4 Module code region */ +/* 5 Module data region */ +/* 6 Module data region */ +/* 7 Module data region */ +/* */ +/* If TXM_MODULE_MANAGER_16_MPU is defined, there are 16 MPU slots. */ +/* MPU layout for the Cortex-M7: */ +/* Entry Description */ +/* 0 Kernel mode entry */ +/* 1 Module code region */ +/* 2 Module code region */ +/* 3 Module code region */ +/* 4 Module code region */ +/* 5 Module data region */ +/* 6 Module data region */ +/* 7 Module data region */ +/* 8 Module data region */ +/* 9 Module shared memory region */ +/* 10 Module shared memory region */ +/* 11 Module shared memory region */ +/* 12 Unused region */ +/* 13 Unused region */ +/* 14 Unused region */ +/* 15 Unused region */ +/* */ /* */ /* INPUT */ /* */ @@ -261,11 +293,181 @@ UINT srd_bit_index; /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ /* */ /**************************************************************************/ VOID _txm_module_manager_mm_register_setup(TXM_MODULE_INSTANCE *module_instance) { +#ifdef TXM_MODULE_MANAGER_16_MPU + +ULONG code_address; +ULONG code_size; +ULONG data_address; +ULONG data_size; +ULONG start_stop_stack_size; +ULONG callback_stack_size; +ULONG block_size; +ULONG region_size; +ULONG srd_bits = 0; +UINT mpu_table_index; +UINT i; + + + /* Setup the first MPU region for kernel mode entry. */ + /* Set address register to user mode entry function address, which is guaranteed to be at least 32-byte aligned. + Mask address to proper range, region 0, set Valid bit. */ + module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MPU_KERNEL_ENTRY_INDEX].txm_module_mpu_region_address = ((ULONG) _txm_module_manager_user_mode_entry & 0xFFFFFFE0) | 0x10; + /* Set the attributes, size (32 bytes) and enable bit. */ + module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MPU_KERNEL_ENTRY_INDEX].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_CODE_ACCESS_CONTROL | (_txm_module_manager_region_size_get(32) << 1) | TXM_ENABLE_REGION; + /* End of kernel mode entry setup. */ + + /* Setup code protection. */ + + /* Initialize the MPU table index. */ + mpu_table_index = 1; + + /* Pickup code starting address and actual size. */ + code_address = (ULONG) module_instance -> txm_module_instance_code_start; + code_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_code_size; + + /* Determine code block sizes. Minimize the alignment requirement. + There are 4 MPU code entries available. The following is how the code size + will be distributed: + 1. 1/4 of the largest power of two that is greater than or equal to code size. + 2. 1/4 of the largest power of two that is greater than or equal to code size. + 3. Largest power of 2 that fits in the remaining space. + 4. Smallest power of 2 that exceeds the remaining space, minimum 32. */ + + /* Now loop through to setup MPU protection for the code area. */ + for (i = 0; i < TXM_MODULE_MPU_CODE_ENTRIES; i++) + { + /* First two MPU blocks are 1/4 of the largest power of two + that is greater than or equal to code size. */ + if (i < 2) + { + block_size = _txm_power_of_two_block_size(code_size) >> 2; + } + + /* Third MPU block is the largest power of 2 that fits in the remaining space. */ + else if (i == 2) + { + /* Subtract (block_size*2) from code_size to calculate remaining space. */ + code_size = code_size - (block_size << 1); + block_size = _txm_power_of_two_block_size(code_size) >> 1; + } + + /* Last MPU block is the smallest power of 2 that exceeds the remaining space, minimum 32. */ + else + { + /* Calculate remaining space. */ + code_size = code_size - block_size; + block_size = _txm_power_of_two_block_size(code_size); + srd_bits = _txm_module_manager_calculate_srd_bits(block_size, code_size); + } + + /* Calculate the region size information. */ + region_size = (_txm_module_manager_region_size_get(block_size) << 1); + + /* Build the base address register with address, MPU region, set Valid bit. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_address = (code_address & ~(block_size - 1)) | mpu_table_index | 0x10; + /* Build the attribute-size register with permissions, SRD, size, enable. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_CODE_ACCESS_CONTROL | srd_bits | region_size | TXM_ENABLE_REGION; + + /* Adjust the code address. */ + code_address = code_address + block_size; + + /* Increment MPU table index. */ + mpu_table_index++; + } + /* End of code protection. */ + + /* Setup data protection. */ + + /* Reset SRD bitfield. */ + srd_bits = 0; + + /* Pickup data starting address and actual size. */ + data_address = (ULONG) module_instance -> txm_module_instance_data_start; + + /* Adjust the size of the module elements to be aligned to the default alignment. We do this + so that when we partition the allocated memory, we can simply place these regions right beside + each other without having to align their pointers. Note this only works when they all have + the same alignment. */ + + data_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_data_size; + start_stop_stack_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_start_stop_stack_size; + callback_stack_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_callback_stack_size; + + data_size = ((data_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; + + start_stop_stack_size = ((start_stop_stack_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; + + callback_stack_size = ((callback_stack_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; + + /* Update the data size to include thread stacks. */ + data_size = data_size + start_stop_stack_size + callback_stack_size; + + /* Determine data block sizes. Minimize the alignment requirement. + There are 4 MPU data entries available. The following is how the data size + will be distributed: + 1. 1/4 of the largest power of two that is greater than or equal to data size. + 2. 1/4 of the largest power of two that is greater than or equal to data size. + 3. Largest power of 2 that fits in the remaining space. + 4. Smallest power of 2 that exceeds the remaining space, minimum 32. */ + + /* Now loop through to setup MPU protection for the data area. */ + for (i = 0; i < TXM_MODULE_MPU_DATA_ENTRIES; i++) + { + /* First two MPU blocks are 1/4 of the largest power of two + that is greater than or equal to data size. */ + if (i < 2) + { + block_size = _txm_power_of_two_block_size(data_size) >> 2; + } + + /* Third MPU block is the largest power of 2 that fits in the remaining space. */ + else if (i == 2) + { + /* Subtract (block_size*2) from data_size to calculate remaining space. */ + data_size = data_size - (block_size << 1); + block_size = _txm_power_of_two_block_size(data_size) >> 1; + } + + /* Last MPU block is the smallest power of 2 that exceeds the remaining space, minimum 32. */ + else + { + /* Calculate remaining space. */ + data_size = data_size - block_size; + block_size = _txm_power_of_two_block_size(data_size); + srd_bits = _txm_module_manager_calculate_srd_bits(block_size, data_size); + } + + /* Calculate the region size information. */ + region_size = (_txm_module_manager_region_size_get(block_size) << 1); + + /* Build the base address register with address, MPU region, set Valid bit. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_address = (data_address & ~(block_size - 1)) | mpu_table_index | 0x10; + /* Build the attribute-size register with permissions, SRD, size, enable. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_DATA_ACCESS_CONTROL | srd_bits | region_size | TXM_ENABLE_REGION; + + /* Adjust the data address. */ + data_address = data_address + block_size; + + /* Increment MPU table index. */ + mpu_table_index++; + } + + /* Setup MPU for the remaining regions. */ + while (mpu_table_index < TXM_MODULE_MPU_TOTAL_ENTRIES) + { + /* Build the base address register with address, MPU region, set Valid bit. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_address = mpu_table_index | 0x10; + + /* Increment MPU table index. */ + mpu_table_index++; + } + +#else ULONG code_address; ULONG code_size; @@ -382,7 +584,7 @@ UINT i; for (i = 0; i < TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1; i++) { /* Build the base address register. */ - base_address_register = code_address & ~(block_size - 1) | mpu_register | 0x10; + base_address_register = (code_address & ~(block_size - 1)) | mpu_register | 0x10; /* Check if SRD bits need to be set. */ if (code_size < block_size) @@ -509,4 +711,87 @@ UINT i; /* Increment the MPU register index. */ mpu_register++; } + +#endif +} + +#ifdef TXM_MODULE_MANAGER_16_MPU +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_inside_data_check Cortex-M3 */ +/* 6.1.9 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks if the specified object is inside shared */ +/* memory. */ +/* */ +/* INPUT */ +/* */ +/* module_instance Pointer to module instance */ +/* obj_ptr Pointer to the object */ +/* obj_size Size of the object */ +/* */ +/* OUTPUT */ +/* */ +/* Whether the object is inside the shared memory region. */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Module dispatch check functions */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ +/* */ +/**************************************************************************/ +UINT _txm_module_manager_inside_data_check(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE obj_ptr, UINT obj_size) +{ + +UINT shared_memory_index; +UINT num_shared_memory_mpu_entries; +ALIGN_TYPE shared_memory_address_start; +ALIGN_TYPE shared_memory_address_end; + + /* Check for overflow. */ + if ((obj_ptr) > ((obj_ptr) + (obj_size))) + { + return(TX_FALSE); + } + + /* Check if the object is inside the module data. */ + if ((obj_ptr >= (ALIGN_TYPE) module_instance -> txm_module_instance_data_start) && + ((obj_ptr + obj_size) <= ((ALIGN_TYPE) module_instance -> txm_module_instance_data_end + 1))) + { + return(TX_TRUE); + } + + /* Check if the object is inside the shared memory. */ + num_shared_memory_mpu_entries = module_instance -> txm_module_instance_shared_memory_count; + for (shared_memory_index = 0; shared_memory_index < num_shared_memory_mpu_entries; shared_memory_index++) + { + + shared_memory_address_start = (ALIGN_TYPE) module_instance -> txm_module_instance_shared_memory_address[shared_memory_index]; + shared_memory_address_end = shared_memory_address_start + module_instance -> txm_module_instance_shared_memory_length[shared_memory_index]; + + if ((obj_ptr >= (ALIGN_TYPE) shared_memory_address_start) && + ((obj_ptr + obj_size) <= (ALIGN_TYPE) shared_memory_address_end)) + { + return(TX_TRUE); + } + } + + return(TX_FALSE); } +#endif diff --git a/ports_module/cortex_m3/ac5/module_manager/src/txm_module_manager_thread_stack_build.S b/ports_module/cortex_m3/ac5/module_manager/src/txm_module_manager_thread_stack_build.s index 91d808e4..4b2b878a 100644 --- a/ports_module/cortex_m3/ac5/module_manager/src/txm_module_manager_thread_stack_build.S +++ b/ports_module/cortex_m3/ac5/module_manager/src/txm_module_manager_thread_stack_build.s @@ -26,8 +26,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _txm_module_manager_thread_stack_build Cortex-M3/MPU/AC5 */ -/* 6.1 */ +/* _txm_module_manager_thread_stack_build Cortex-M3/AC5 */ +/* 6.1.9 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -59,7 +59,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ /* */ /**************************************************************************/ // VOID _txm_module_manager_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(TX_THREAD *, TXM_MODULE_INSTANCE *)) @@ -71,7 +71,7 @@ _txm_module_manager_thread_stack_build on the Cortex-M should look like the following after it is built: Stack Top: - LR Interrupted LR (LR at time of PENDSV) + lr Interrupted lr (lr at time of PENDSV) r4 Initial value for r4 r5 Initial value for r5 r6 Initial value for r6 diff --git a/ports_module/cortex_m3/ac5/module_manager/src/txm_module_manager_user_mode_entry.S b/ports_module/cortex_m3/ac5/module_manager/src/txm_module_manager_user_mode_entry.s index 86620955..6b9d8cc9 100644 --- a/ports_module/cortex_m3/ac5/module_manager/src/txm_module_manager_user_mode_entry.S +++ b/ports_module/cortex_m3/ac5/module_manager/src/txm_module_manager_user_mode_entry.s @@ -10,57 +10,57 @@ /**************************************************************************/ -/**************************************************************************/ -/**************************************************************************/ -/** */ -/** ThreadX Component */ -/** */ -/** Module Manager */ -/** */ -/**************************************************************************/ -/**************************************************************************/ +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ IMPORT _txm_module_manager_kernel_dispatch IMPORT _tx_thread_current_ptr AREA ||.text||, CODE, READONLY, ALIGN=5 THUMB -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* _txm_module_manager_user_mode_entry Cortex-M3/MPU/AC5 */ -/* 6.1 */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_user_mode_entry Cortex-M3/AC5 */ +/* 6.1.9 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ /* */ -/* DESCRIPTION */ -/* */ -/* This function allows modules to enter kernel mode. */ -/* */ -/* INPUT */ -/* */ -/* None */ -/* */ -/* OUTPUT */ -/* */ -/* None */ -/* */ -/* CALLS */ -/* */ -/* SVC 1 Enter kernel mode */ -/* SVC 2 Exit kernel mode */ -/* */ -/* CALLED BY */ -/* */ -/* Modules in user mode */ -/* */ -/* RELEASE HISTORY */ -/* */ +/* DESCRIPTION */ +/* */ +/* This function allows modules to enter kernel mode. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* SVC 1 Enter kernel mode */ +/* SVC 2 Exit kernel mode */ +/* */ +/* CALLED BY */ +/* */ +/* Modules in user mode */ +/* */ +/* RELEASE HISTORY */ +/* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ /* */ /**************************************************************************/ // VOID _txm_module_manager_user_mode_entry(VOID) diff --git a/ports_module/cortex_m3/ac6/inc/tx_port.h b/ports_module/cortex_m3/ac6/inc/tx_port.h index 58db3ea3..6f4ebb5b 100644 --- a/ports_module/cortex_m3/ac6/inc/tx_port.h +++ b/ports_module/cortex_m3/ac6/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h Cortex-M3/AC6 */ -/* 6.1 */ +/* 6.1.9 */ /* */ /* AUTHOR */ /* */ @@ -47,10 +47,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ -/* macro definition, */ -/* resulting in version 6.1.6 */ +/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ /* */ /**************************************************************************/ @@ -142,7 +139,7 @@ typedef unsigned short USHORT; /* Define the port specific options for the _tx_build_options variable. This variable indicates how the ThreadX library was built. */ -#define TX_PORT_SPECIFIC_BUILD_OPTIONS 0 +#define TX_PORT_SPECIFIC_BUILD_OPTIONS (0) /* Define the in-line initialization constant so that modules with in-line @@ -218,9 +215,140 @@ typedef unsigned short USHORT; #define TX_THREAD_CREATE_EXTENSION(thread_ptr) #define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#ifdef TX_ENABLE_FPU_SUPPORT + + +#ifdef TX_MISRA_ENABLE + +ULONG _tx_misra_control_get(void); +void _tx_misra_control_set(ULONG value); +ULONG _tx_misra_fpccr_get(void); +void _tx_misra_vfp_touch(void); + +#else + +__attribute__( ( always_inline ) ) static inline ULONG __get_control(void) +{ + +ULONG control_value; + + __asm__ volatile (" MRS %0,CONTROL ": "=r" (control_value) ); + return(control_value); +} + + +__attribute__( ( always_inline ) ) static inline void __set_control(ULONG control_value) +{ + + __asm__ volatile (" MSR CONTROL,%0": : "r" (control_value): "memory" ); +} + + +#endif + + +/* A completed thread falls into _thread_shell_entry and we can simply deactivate the FPU via CONTROL.FPCA + in order to ensure no lazy stacking will occur. */ + +#ifndef TX_MISRA_ENABLE + +#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) { \ + ULONG _tx_vfp_state; \ + _tx_vfp_state = __get_control(); \ + _tx_vfp_state = _tx_vfp_state & ~((ULONG) 0x4); \ + __set_control(_tx_vfp_state); \ + } +#else + +#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) { \ + ULONG _tx_vfp_state; \ + _tx_vfp_state = _tx_misra_control_get(); \ + _tx_vfp_state = _tx_vfp_state & ~((ULONG) 0x4); \ + _tx_misra_control_set(_tx_vfp_state); \ + } + +#endif + + +/* A thread can be terminated by another thread, so we first check if it's self-terminating and not in an ISR. + If so, deactivate the FPU via CONTROL.FPCA. Otherwise we are in an interrupt or another thread is terminating + this one, so if the FPCCR.LSPACT bit is set, we need to save the CONTROL.FPCA state, touch the FPU to flush + the lazy FPU save, then restore the CONTROL.FPCA state. */ + +#ifndef TX_MISRA_ENABLE + + +#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) { \ + ULONG _tx_system_state; \ + _tx_system_state = TX_THREAD_GET_SYSTEM_STATE(); \ + if ((_tx_system_state == ((ULONG) 0)) && ((thread_ptr) == _tx_thread_current_ptr)) \ + { \ + ULONG _tx_vfp_state; \ + _tx_vfp_state = __get_control(); \ + _tx_vfp_state = _tx_vfp_state & ~((ULONG) 0x4); \ + __set_control(_tx_vfp_state); \ + } \ + else \ + { \ + ULONG _tx_fpccr; \ + _tx_fpccr = *((ULONG *) 0xE000EF34); \ + _tx_fpccr = _tx_fpccr & ((ULONG) 0x01); \ + if (_tx_fpccr == ((ULONG) 0x01)) \ + { \ + ULONG _tx_vfp_state; \ + _tx_vfp_state = __get_control(); \ + _tx_vfp_state = _tx_vfp_state & ((ULONG) 0x4); \ + __asm__ volatile ("vmov.f32 s0, s0"); \ + if (_tx_vfp_state == ((ULONG) 0)) \ + { \ + _tx_vfp_state = __get_control(); \ + _tx_vfp_state = _tx_vfp_state & ~((ULONG) 0x4); \ + __set_control(_tx_vfp_state); \ + } \ + } \ + } \ + } +#else + +#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) { \ + ULONG _tx_system_state; \ + _tx_system_state = TX_THREAD_GET_SYSTEM_STATE(); \ + if ((_tx_system_state == ((ULONG) 0)) && ((thread_ptr) == _tx_thread_current_ptr)) \ + { \ + ULONG _tx_vfp_state; \ + _tx_vfp_state = _tx_misra_control_get(); \ + _tx_vfp_state = _tx_vfp_state & ~((ULONG) 0x4); \ + _tx_misra_control_set(_tx_vfp_state); \ + } \ + else \ + { \ + ULONG _tx_fpccr; \ + _tx_fpccr = _tx_misra_fpccr_get(); \ + _tx_fpccr = _tx_fpccr & ((ULONG) 0x01); \ + if (_tx_fpccr == ((ULONG) 0x01)) \ + { \ + ULONG _tx_vfp_state; \ + _tx_vfp_state = _tx_misra_control_get(); \ + _tx_vfp_state = _tx_vfp_state & ((ULONG) 0x4); \ + _tx_misra_vfp_touch(); \ + if (_tx_vfp_state == ((ULONG) 0)) \ + { \ + _tx_vfp_state = _tx_misra_control_get(); \ + _tx_vfp_state = _tx_vfp_state & ~((ULONG) 0x4); \ + _tx_misra_control_set(_tx_vfp_state); \ + } \ + } \ + } \ + } +#endif + +#else + #define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) #define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) +#endif + /* Define the ThreadX object creation extensions for the remaining objects. */ @@ -274,6 +402,7 @@ ULONG _tx_misra_ipsr_get(VOID); #define TX_THREAD_SYSTEM_RETURN_CHECK(c) (c) = ((ULONG) _tx_thread_preempt_disable); #endif + /* Define the macro to ensure _tx_thread_preempt_disable is set early in initialization in order to prevent early scheduling on Cortex-M parts. */ @@ -368,11 +497,18 @@ unsigned int interrupt_save; #endif +/* Define FPU extension for the Cortex-M7. Each is assumed to be called in the context of the executing + thread. These are no longer needed, but are preserved for backward compatibility only. */ + +void tx_thread_fpu_enable(void); +void tx_thread_fpu_disable(void); + + /* Define the version ID of ThreadX. This may be utilized by the application. */ #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M3/AC6 Version 6.1.6 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M3/AC6 Version 6.1.9 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_module/cortex_m3/ac6/inc/txm_module_port.h b/ports_module/cortex_m3/ac6/inc/txm_module_port.h index 82b9721c..8dba095c 100644 --- a/ports_module/cortex_m3/ac6/inc/txm_module_port.h +++ b/ports_module/cortex_m3/ac6/inc/txm_module_port.h @@ -25,8 +25,8 @@ /* */ /* APPLICATION INTERFACE DEFINITION RELEASE */ /* */ -/* txm_module_port.h Cortex-M3/MPU/AC6 */ -/* 6.1.6 */ +/* txm_module_port.h Cortex-M3/AC6 */ +/* 6.1.9 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -40,10 +40,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Andres Mlinar Initial Version 6.1 */ -/* 04-02-2021 Scott Larson Modified comment(s) and */ -/* added check for overflow, */ -/* resulting in version 6.1.6 */ +/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ /* */ /**************************************************************************/ @@ -94,16 +91,26 @@ The following extensions must also be defined in tx_port.h: VOID (*tx_timer_module_expiration_function)(ULONG id); */ - -/* Size of module heap. */ -#define TXM_MODULE_HEAP_SIZE 512 - - /* Define the kernel stack size for a module thread. */ #ifndef TXM_MODULE_KERNEL_STACK_SIZE #define TXM_MODULE_KERNEL_STACK_SIZE 768 #endif +/* For the following 3 access control settings, change TEX and C, B, S (bits 21 through 16 of MPU_RASR) + * to reflect your system memory attributes (cache, shareable, memory type). */ +/* Code region access control: privileged read-only, outer & inner write-back, normal memory, shareable. */ +#ifndef TXM_MODULE_MPU_CODE_ACCESS_CONTROL +#define TXM_MODULE_MPU_CODE_ACCESS_CONTROL 0x06070000 +#endif +/* Data region access control: execute never, read/write, outer & inner write-back, normal memory, shareable. */ +#ifndef TXM_MODULE_MPU_DATA_ACCESS_CONTROL +#define TXM_MODULE_MPU_DATA_ACCESS_CONTROL 0x13070000 +#endif +/* Shared region access control: execute never, read-only, outer & inner write-back, normal memory, shareable. */ +#ifndef TXM_MODULE_MPU_SHARED_ACCESS_CONTROL +#define TXM_MODULE_MPU_SHARED_ACCESS_CONTROL 0x12070000 +#endif + /* Define constants specific to the tools the module can be built with for this particular modules port. */ #define TXM_MODULE_IAR_COMPILER 0x00000000 @@ -154,12 +161,47 @@ The following extensions must also be defined in tx_port.h: /* Define other module port-specific constants. */ -/* Define INLINE_DECLARE to inline for AC6 compiler. */ +/* Define INLINE_DECLARE to inline for ARM compiler. */ #define INLINE_DECLARE inline +#ifdef TXM_MODULE_MANAGER_16_MPU + /* Define the number of MPU entries assigned to the code and data sections. - On Cortex-M3 parts, there are 8 total entries. ThreadX uses one for access + On some Cortex-M7 parts, there are 16 total entries. ThreadX uses one for access + to the kernel entry function, thus 15 remain for code and data protection. */ +#define TXM_MODULE_MPU_TOTAL_ENTRIES 16 +#define TXM_MODULE_MPU_CODE_ENTRIES 4 +#define TXM_MODULE_MPU_DATA_ENTRIES 4 +#define TXM_MODULE_MPU_SHARED_ENTRIES 3 + +#define TXM_MODULE_MPU_KERNEL_ENTRY_INDEX 0 +#define TXM_MODULE_MPU_SHARED_INDEX 9 + +#define TXM_ENABLE_REGION 0x01 + +/* There are 2 registers to set up each MPU region: MPU_RBAR, MPU_RASR. */ +typedef struct TXM_MODULE_MPU_INFO_STRUCT +{ + ULONG txm_module_mpu_region_address; + ULONG txm_module_mpu_region_attribute_size; +} TXM_MODULE_MPU_INFO; +/* Shared memory region attributes. */ +#define TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE 1 +#define TXM_MODULE_MANAGER_ATTRIBUTE_WRITE_MPU_BIT 0x01000000 + +/* Define the port-extensions to the module manager instance structure. */ + +#define TXM_MODULE_MANAGER_PORT_EXTENSION \ + TXM_MODULE_MPU_INFO txm_module_instance_mpu_registers[TXM_MODULE_MPU_TOTAL_ENTRIES]; \ + ULONG txm_module_instance_shared_memory_count; \ + ULONG txm_module_instance_shared_memory_address[TXM_MODULE_MPU_SHARED_ENTRIES]; \ + ULONG txm_module_instance_shared_memory_length[TXM_MODULE_MPU_SHARED_ENTRIES]; + +#else /* TXM_MODULE_MANAGER_16_MPU is not defined */ + +/* Define the number of MPU entries assigned to the code and data sections. + On Cortex-M3, M4, and some M7 parts, there are 8 total entries. ThreadX uses one for access to the kernel entry function, thus 7 remain for code and data protection. */ #define TXM_MODULE_MANAGER_CODE_MPU_ENTRIES 4 #define TXM_MODULE_MANAGER_DATA_MPU_ENTRIES 3 @@ -177,6 +219,7 @@ The following extensions must also be defined in tx_port.h: ULONG txm_module_instance_shared_memory_address; \ ULONG txm_module_instance_shared_memory_length; +#endif /* TXM_MODULE_MANAGER_16_MPU */ /* Define the memory fault information structure that is populated when a memory fault occurs. */ @@ -299,6 +342,10 @@ typedef struct TXM_MODULE_MANAGER_MEMORY_FAULT_INFO_STRUCT /* Define the macros to perform port-specific checks when passing pointers to the kernel. */ /* Define macro to make sure object is inside the module's data. */ +#ifdef TXM_MODULE_MANAGER_16_MPU +#define TXM_MODULE_MANAGER_CHECK_INSIDE_DATA(module_instance, obj_ptr, obj_size) \ + _txm_module_manager_inside_data_check(module_instance, obj_ptr, obj_size) +#else #define TXM_MODULE_MANAGER_CHECK_INSIDE_DATA(module_instance, obj_ptr, obj_size) \ /* Check for overflow. */ \ (((obj_ptr) < ((obj_ptr) + (obj_size))) && \ @@ -308,7 +355,7 @@ typedef struct TXM_MODULE_MANAGER_MEMORY_FAULT_INFO_STRUCT /* Check if it's inside shared memory. */ \ (((obj_ptr) >= (ALIGN_TYPE) module_instance -> txm_module_instance_shared_memory_address) && \ (((obj_ptr) + (obj_size)) <= (ALIGN_TYPE) (module_instance -> txm_module_instance_shared_memory_address + module_instance -> txm_module_instance_shared_memory_length))))) - +#endif /* Define some internal prototypes to this module port. */ @@ -324,10 +371,11 @@ UINT _txm_module_manager_memory_fault_notify(VOID (*notify_function)(TX_THREAD VOID _txm_module_manager_mm_register_setup(TXM_MODULE_INSTANCE *module_instance); \ ULONG _txm_power_of_two_block_size(ULONG size); \ ULONG _txm_module_manager_calculate_srd_bits(ULONG block_size, ULONG length); \ -ULONG _txm_module_manager_region_size_get(ULONG block_size); +ULONG _txm_module_manager_region_size_get(ULONG block_size); \ +UINT _txm_module_manager_inside_data_check(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE obj_ptr, UINT obj_size); #define TXM_MODULE_MANAGER_VERSION_ID \ -CHAR _txm_module_manager_version_id[] = \ - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-M3/MPU/AC6 Version 6.1.8 *"; +CHAR _txm_module_manager_version_id[] = \ + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-M3/AC6 Version 6.1.9 *"; #endif diff --git a/ports_module/cortex_m3/ac6/module_lib/src/txm_module_initialize.S b/ports_module/cortex_m3/ac6/module_lib/src/txm_module_initialize.S index cc4bdcc1..488002a4 100644 --- a/ports_module/cortex_m3/ac6/module_lib/src/txm_module_initialize.S +++ b/ports_module/cortex_m3/ac6/module_lib/src/txm_module_initialize.S @@ -32,8 +32,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _txm_module_initialize Cortex-M4/MPU/AC6 */ -/* 6.1 */ +/* _txm_module_initialize Cortex-M3/AC6 */ +/* 6.1.9 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -62,7 +62,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Andres Mlinar Initial Version 6.1 */ +/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ /* */ /**************************************************************************/ // VOID _txm_module_initialize(VOID) diff --git a/ports_module/cortex_m3/ac6/module_lib/src/txm_module_thread_shell_entry.c b/ports_module/cortex_m3/ac6/module_lib/src/txm_module_thread_shell_entry.c index e6ebe65f..20bb514d 100644 --- a/ports_module/cortex_m3/ac6/module_lib/src/txm_module_thread_shell_entry.c +++ b/ports_module/cortex_m3/ac6/module_lib/src/txm_module_thread_shell_entry.c @@ -44,7 +44,9 @@ TXM_MODULE_THREAD_ENTRY_INFO *_txm_module_entry_info; ULONG (*_txm_module_kernel_call_dispatcher)(ULONG kernel_request, ULONG param_1, ULONG param_2, ULONG param3); -/* Define the ARM cstartup code. */ +/* Define the startup code that clears the uninitialized global data and sets up the + preset global variables. */ + extern VOID _txm_module_initialize(VOID); @@ -52,15 +54,15 @@ extern VOID _txm_module_initialize(VOID); /* */ /* FUNCTION RELEASE */ /* */ -/* _txm_module_thread_shell_entry Cortex-M3/MPU/AC6 */ -/* 6.1 */ +/* _txm_module_thread_shell_entry Cortex-M3/AC6 */ +/* 6.1.9 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ /* */ /* DESCRIPTION */ /* */ -/* This function calls the specified entry function of the thread. It */ +/* This function calls the specified entry function of the thread. It */ /* also provides a place for the thread's entry function to return. */ /* If the thread returns, this function places the thread in a */ /* "COMPLETED" state. */ @@ -89,7 +91,7 @@ extern VOID _txm_module_initialize(VOID); /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ /* */ /**************************************************************************/ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_ENTRY_INFO *thread_info) @@ -104,7 +106,7 @@ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_EN execution. If not, simply skip the C startup code. */ if (thread_info -> txm_module_thread_entry_info_start_thread) { - /* Initialize the ARM C environment. */ + /* Initialize the C environment. */ _txm_module_initialize(); /* Save the entry info pointer, for later use. */ @@ -169,4 +171,3 @@ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_EN TX_SAFETY_CRITICAL_EXCEPTION(__FILE__, __LINE__, 0); #endif } - diff --git a/ports_module/cortex_m3/ac6/module_manager/src/tx_thread_context_restore.S b/ports_module/cortex_m3/ac6/module_manager/src/tx_thread_context_restore.S index 17a79b0f..9dbe0204 100644 --- a/ports_module/cortex_m3/ac6/module_manager/src/tx_thread_context_restore.S +++ b/ports_module/cortex_m3/ac6/module_manager/src/tx_thread_context_restore.S @@ -31,8 +31,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_context_restore Cortex-Mx/AC6 */ -/* 6.1.8 */ +/* _tx_thread_context_restore Cortex-M3/AC6 */ +/* 6.1.7 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -62,7 +62,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ +/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ /* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) diff --git a/ports_module/cortex_m3/ac6/module_manager/src/tx_thread_context_save.S b/ports_module/cortex_m3/ac6/module_manager/src/tx_thread_context_save.S index 511ca82e..5061b512 100644 --- a/ports_module/cortex_m3/ac6/module_manager/src/tx_thread_context_save.S +++ b/ports_module/cortex_m3/ac6/module_manager/src/tx_thread_context_save.S @@ -30,8 +30,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_context_save Cortex-Mx/AC6 */ -/* 6.1.8 */ +/* _tx_thread_context_save Cortex-M3/AC6 */ +/* 6.1.7 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -61,7 +61,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ +/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ /* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) diff --git a/ports_module/cortex_m3/ac6/module_manager/src/tx_thread_interrupt_control.S b/ports_module/cortex_m3/ac6/module_manager/src/tx_thread_interrupt_control.S index 07d2a131..1f6a3f11 100644 --- a/ports_module/cortex_m3/ac6/module_manager/src/tx_thread_interrupt_control.S +++ b/ports_module/cortex_m3/ac6/module_manager/src/tx_thread_interrupt_control.S @@ -27,8 +27,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_interrupt_control Cortex-Mx/AC6 */ -/* 6.1.8 */ +/* _tx_thread_interrupt_control Cortex-M3/AC6 */ +/* 6.1.7 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -58,7 +58,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ +/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ /* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) diff --git a/ports_module/cortex_m3/ac6/module_manager/src/tx_thread_interrupt_disable.S b/ports_module/cortex_m3/ac6/module_manager/src/tx_thread_interrupt_disable.S new file mode 100644 index 00000000..93159485 --- /dev/null +++ b/ports_module/cortex_m3/ac6/module_manager/src/tx_thread_interrupt_disable.S @@ -0,0 +1,79 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + .text 32 + .align 4 + .syntax unified +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_interrupt_disable Cortex-M3/AC6 */ +/* 6.1.7 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is responsible for disabling interrupts and returning */ +/* the previous interrupt lockout posture. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* old_posture Old interrupt lockout posture */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ +/* */ +/**************************************************************************/ +// UINT _tx_thread_interrupt_disable(VOID) +// { + .global _tx_thread_interrupt_disable + .thumb_func +_tx_thread_interrupt_disable: + /* Return current interrupt lockout posture. */ +#ifdef TX_PORT_USE_BASEPRI + MRS r0, BASEPRI + LDR r1, =TX_PORT_BASEPRI + MSR BASEPRI, r1 +#else + MRS r0, PRIMASK + CPSID i +#endif + BX lr +// } diff --git a/ports_module/cortex_m3/ac6/module_manager/src/tx_thread_interrupt_restore.S b/ports_module/cortex_m3/ac6/module_manager/src/tx_thread_interrupt_restore.S new file mode 100644 index 00000000..c060ec5f --- /dev/null +++ b/ports_module/cortex_m3/ac6/module_manager/src/tx_thread_interrupt_restore.S @@ -0,0 +1,76 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + .text 32 + .align 4 + .syntax unified +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_interrupt_restore Cortex-M3/AC6 */ +/* 6.1.7 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is responsible for restoring the previous */ +/* interrupt lockout posture. */ +/* */ +/* INPUT */ +/* */ +/* previous_posture Previous interrupt posture */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ +/* */ +/**************************************************************************/ +// VOID _tx_thread_interrupt_restore(UINT previous_posture) +// { + .global _tx_thread_interrupt_restore + .thumb_func +_tx_thread_interrupt_restore: + /* Restore previous interrupt lockout posture. */ +#ifdef TX_PORT_USE_BASEPRI + MSR BASEPRI, r0 +#else + MSR PRIMASK, r0 +#endif + BX lr +// } diff --git a/ports_module/cortex_m3/ac6/module_manager/src/tx_thread_schedule.S b/ports_module/cortex_m3/ac6/module_manager/src/tx_thread_schedule.S index 345ab227..081e5c35 100644 --- a/ports_module/cortex_m3/ac6/module_manager/src/tx_thread_schedule.S +++ b/ports_module/cortex_m3/ac6/module_manager/src/tx_thread_schedule.S @@ -23,7 +23,6 @@ .global _tx_thread_current_ptr .global _tx_thread_execute_ptr .global _tx_timer_time_slice - .global _tx_thread_system_stack_ptr .global _tx_thread_preempt_disable .global _txm_module_manager_memory_fault_handler .global _txm_module_manager_memory_fault_info @@ -42,8 +41,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_schedule Cortex-M3/MPU/AC6 */ -/* 6.1 */ +/* _tx_thread_schedule Cortex-M3/AC6 */ +/* 6.1.9 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -76,7 +75,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ /* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) @@ -95,8 +94,14 @@ _tx_thread_schedule: LDR r2, =_tx_thread_preempt_disable // Build address of preempt disable flag STR r0, [r2, #0] // Clear preempt disable flag - /* Enable memory fault registers. */ +#ifdef __ARM_FP + /* Clear CONTROL.FPCA bit so VFP registers aren't unnecessarily stacked. */ + MRS r0, CONTROL // Pickup current CONTROL register + BIC r0, r0, #4 // Clear the FPCA bit + MSR CONTROL, r0 // Setup new CONTROL register +#endif + /* Enable memory fault registers. */ LDR r0, =0xE000ED24 // Build SHCSR address LDR r1, =0x70000 // Enable Usage, Bus, and MemManage faults STR r1, [r0] // @@ -188,6 +193,13 @@ UsageFault_Handler: // Bit 7 = 1 -> MMFAR is valid STRB r1, [r0] // Clear the MMFSR +#ifdef __ARM_FP + LDR r0, =0xE000EF34 // Cleanup FPU context: Load FPCCR address + LDR r1, [r0] // Load FPCCR + BIC r1, r1, #1 // Clear the lazy preservation active bit + STR r1, [r0] // Store the value +#endif + BL _txm_module_manager_memory_fault_handler // Call memory manager fault handler #if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) @@ -214,9 +226,10 @@ UsageFault_Handler: /* Generic context PendSV handler. */ .global PendSV_Handler + .global __tx_PendSVHandler + .syntax unified .thumb_func PendSV_Handler: - .global __tx_PendSVHandler .thumb_func __tx_PendSVHandler: @@ -247,6 +260,12 @@ __tx_ts_handler: STR r3, [r0] // Set _tx_thread_current_ptr to NULL MRS r12, PSP // Pickup PSP pointer (thread's stack pointer) STMDB r12!, {r4-r11} // Save its remaining registers +#ifdef __ARM_FP + TST LR, #0x10 // Determine if the VFP extended frame is present + BNE _skip_vfp_save + VSTMDB r12!,{s16-s31} // Yes, save additional VFP registers +_skip_vfp_save: +#endif LDR r4, =_tx_timer_time_slice // Build address of time-slice variable STMDB r12!, {LR} // Save LR on the stack @@ -272,16 +291,42 @@ __tx_ts_new: CPSID i // Disable interrupts LDR r1, [r2] // Is there another thread ready to execute? - CBZ r1, __tx_ts_wait // No, skip to the wait processing + CBNZ r1, __tx_ts_restore // Yes, schedule it - /* Yes, another thread is ready for else, make the current thread the new thread. */ + /* The following is the idle wait processing... in this case, no threads are ready for execution and the + system will simply be idle until an interrupt occurs that makes a thread ready. Note that interrupts + are disabled to allow use of WFI for waiting for a thread to arrive. */ + +__tx_ts_wait: + CPSID i // Disable interrupts + LDR r1, [r2] // Pickup the next thread to execute pointer + CBNZ r1, __tx_ts_ready // If non-NULL, a new thread is ready! +#ifdef TX_ENABLE_WFI + DSB // Ensure no outstanding memory transactions + WFI // Wait for interrupt + ISB // Ensure pipeline is flushed +#endif + CPSIE i // Enable interrupts + B __tx_ts_wait // Loop to continue waiting + + /* At this point, we have a new thread ready to go. Clear any newly pended PendSV - since we are + already in the handler! */ + +__tx_ts_ready: + MOV r7, #0x08000000 // Build clear PendSV value + MOV r8, #0xE000E000 // Build base NVIC address + STR r7, [r8, #0xD04] // Clear any PendSV + +__tx_ts_restore: + + /* A thread is ready, make the current thread the new thread + and enable interrupts. */ STR r1, [r0] // Setup the current thread pointer to the new thread CPSIE i // Enable interrupts /* Increment the thread run count. */ -__tx_ts_restore: LDR r7, [r1, #4] // Pickup the current thread run count LDR r4, =_tx_timer_time_slice // Build address of time-slice variable LDR r5, [r1, #24] // Pickup thread's current time-slice @@ -320,15 +365,32 @@ __tx_ts_restore: // Use alias registers to quickly load MPU ADD r0, r0, #100 // Build address of MPU register start in thread control block +#ifdef TXM_MODULE_MANAGER_16_MPU + LDM r0!,{r2-r9} // Load MPU regions 0-3 + STM r1,{r2-r9} // Store MPU regions 0-3 + LDM r0!,{r2-r9} // Load MPU regions 4-7 + STM r1,{r2-r9} // Store MPU regions 4-7 + LDM r0!,{r2-r9} // Load MPU regions 8-11 + STM r1,{r2-r9} // Store MPU regions 8-11 + LDM r0,{r2-r9} // Load MPU regions 12-15 + STM r1,{r2-r9} // Store MPU regions 12-15 +#else LDM r0!,{r2-r9} // Load first four MPU regions STM r1,{r2-r9} // Store first four MPU regions LDM r0,{r2-r9} // Load second four MPU regions STM r1,{r2-r9} // Store second four MPU regions +#endif LDR r0, =0xE000ED94 // Build MPU control reg address MOV r1, #5 // Build enable value with background region enabled STR r1, [r0] // Enable MPU skip_mpu_setup: LDMIA r12!, {LR} // Pickup LR +#ifdef __ARM_FP + TST LR, #0x10 // Determine if the VFP extended frame is present + BNE _skip_vfp_restore // If not, skip VFP restore + VLDMIA r12!, {s16-s31} // Yes, restore additional VFP registers +_skip_vfp_restore: +#endif LDMIA r12!, {r4-r11} // Recover thread's registers MSR PSP, r12 // Setup the thread's stack pointer @@ -336,51 +398,6 @@ skip_mpu_setup: BX lr // Return to thread! - /* The following is the idle wait processing... in this case, no threads are ready for execution and the - system will simply be idle until an interrupt occurs that makes a thread ready. Note that interrupts - are disabled to allow use of WFI for waiting for a thread to arrive. */ - -__tx_ts_wait: - CPSID i // Disable interrupts - LDR r1, [r2] // Pickup the next thread to execute pointer - STR r1, [r0] // Store it in the current pointer - CBNZ r1, __tx_ts_ready // If non-NULL, a new thread is ready! - -#ifdef TX_LOW_POWER - PUSH {r0-r3} - BL tx_low_power_enter // Possibly enter low power mode - POP {r0-r3} -#endif - -#ifdef TX_ENABLE_WFI - DSB // Ensure no outstanding memory transactions - WFI // Wait for interrupt - ISB // Ensure pipeline is flushed -#endif - -#ifdef TX_LOW_POWER - PUSH {r0-r3} - BL tx_low_power_exit // Exit low power mode - POP {r0-r3} -#endif - - CPSIE i // Enable interrupts - B __tx_ts_wait // Loop to continue waiting - - /* At this point, we have a new thread ready to go. Clear any newly pended PendSV - since we are - already in the handler! */ - -__tx_ts_ready: - MOV r7, #0x08000000 // Build clear PendSV value - MOV r8, #0xE000E000 // Build base NVIC address - STR r7, [r8, #0xD04] // Clear any PendSV - - /* Re-enable interrupts and restore new thread. */ - - CPSIE i // Enable interrupts - B __tx_ts_restore // Restore the thread -// } - /* SVC Handler. */ @@ -404,7 +421,6 @@ __tx_SVCallHandler: the kernel from a module thread with user mode selected. */ LDR r2, =_txm_module_priv // Load address of where we should have come from - // Subtract 1 because of THUMB mode. CMP r1, r2 // Did we come from user_mode_entry? IT NE // If no (not equal), then... BXNE lr // return from where we came. @@ -433,7 +449,16 @@ __tx_SVCallHandler: #endif MRS r3, PSP // Pickup thread stack pointer +#ifdef __ARM_FP + TST lr, #0x10 // Test for extended module stack + ITT EQ + ORREQ r3, r3, #1 // If so, set LSB in thread stack pointer to indicate extended frame + ORREQ lr, lr, #0x10 // Set bit, return with standard frame +#endif STR r3, [r2, #0xB0] // Save thread stack pointer +#ifdef __ARM_FP + BIC r3, #1 // Clear possibly OR'd bit +#endif /* Build kernel stack by copying thread stack two registers at a time */ ADD r3, r3, #32 // Start at bottom of hardware stack @@ -456,7 +481,6 @@ _tx_skip_kernel_stack_enter: _tx_thread_user_return: LDR r2, =_txm_module_user_mode_exit // Load address of where we should have come from - // Subtract 1 because of THUMB mode. CMP r1, r2 // Did we come from user_mode_exit? IT NE // If no (not equal), then... BXNE lr // return from where we came @@ -480,8 +504,38 @@ _tx_thread_user_return: STR r1, [r2, #16] // Set stack end STR r3, [r2, #20] // Set stack size #endif + +#ifdef __ARM_FP + /* If lazy stacking is pending, check if it can be cleared. + if(LSPACT && tx_thread_module_stack_start < FPCAR && FPCAR < tx_thread_module_stack_end) + then clear LSPACT. */ + LDR r3, =0xE000EF34 // Address of FPCCR + LDR r3, [r3] // Load FPCCR + TST r3, #1 // Check if LSPACT is set + BEQ _tx_no_lazy_clear // if clear, move on + LDR r1, =0xE000EF38 // Address of FPCAR + LDR r1, [r1] // Load FPCAR + LDR r0, [r2, #0xA4] // Load kernel stack start + CMP r1, r0 // If FPCAR < start, move on + BLO _tx_no_lazy_clear + LDR r0, [r2, #0xA8] // Load kernel stack end + CMP r0, r1 // If end < FPCAR, move on + BLO _tx_no_lazy_clear + BIC r3, #1 // Clear LSPACT + LDR r1, =0xE000EF34 // Address of FPCCR + STR r3, [r1] // Save updated FPCCR +_tx_no_lazy_clear: +#endif + LDR r0, [r2, #0xB0] // Load the module thread stack pointer MRS r3, PSP // Pickup kernel stack pointer +#ifdef __ARM_FP + TST r0, #1 // Is module stack extended? + ITTE NE // If so... + BICNE lr, #0x10 // Clear bit, return with extended frame + BICNE r0, #1 // Clear bit that indicates extended module frame + ORREQ lr, lr, #0x10 // Else set bit, return with standard frame +#endif /* Copy kernel hardware stack to module thread stack. */ LDM r3!, {r1-r2} @@ -535,3 +589,19 @@ _txm_module_user_mode_exit: NOP NOP // } + +#ifdef __ARM_FP + + .global tx_thread_fpu_enable + .thumb_func +tx_thread_fpu_enable: + .global tx_thread_fpu_disable + .thumb_func +tx_thread_fpu_disable: + + /* Automatic VPF logic is supported, this function is present only for + backward compatibility purposes and therefore simply returns. */ + + BX LR // Return to caller + +#endif diff --git a/ports_module/cortex_m3/ac6/module_manager/src/tx_thread_stack_build.S b/ports_module/cortex_m3/ac6/module_manager/src/tx_thread_stack_build.S index d50f9243..70aec7a7 100644 --- a/ports_module/cortex_m3/ac6/module_manager/src/tx_thread_stack_build.S +++ b/ports_module/cortex_m3/ac6/module_manager/src/tx_thread_stack_build.S @@ -27,8 +27,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_stack_build Cortex-Mx/AC6 */ -/* 6.1.8 */ +/* _tx_thread_stack_build Cortex-M3/AC6 */ +/* 6.1.7 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -60,7 +60,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ +/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ /* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) diff --git a/ports_module/cortex_m3/ac6/module_manager/src/tx_thread_system_return.S b/ports_module/cortex_m3/ac6/module_manager/src/tx_thread_system_return.S index 6560db62..3a24f007 100644 --- a/ports_module/cortex_m3/ac6/module_manager/src/tx_thread_system_return.S +++ b/ports_module/cortex_m3/ac6/module_manager/src/tx_thread_system_return.S @@ -27,8 +27,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_system_return Cortex-Mx/AC6 */ -/* 6.1.8 */ +/* _tx_thread_system_return Cortex-M3/AC6 */ +/* 6.1.7 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -60,7 +60,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ +/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ /* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) diff --git a/ports_module/cortex_m3/ac6/module_manager/src/tx_timer_interrupt.S b/ports_module/cortex_m3/ac6/module_manager/src/tx_timer_interrupt.S index 46f54da0..752e337f 100644 --- a/ports_module/cortex_m3/ac6/module_manager/src/tx_timer_interrupt.S +++ b/ports_module/cortex_m3/ac6/module_manager/src/tx_timer_interrupt.S @@ -37,8 +37,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_timer_interrupt Cortex-Mx/AC6 */ -/* 6.1.8 */ +/* _tx_timer_interrupt Cortex-M3/AC6 */ +/* 6.1.7 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -71,7 +71,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ +/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ /* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) diff --git a/ports_module/cortex_m3/ac6/module_manager/src/txm_module_manager_alignment_adjust.c b/ports_module/cortex_m3/ac6/module_manager/src/txm_module_manager_alignment_adjust.c index 85f06b66..92e629a8 100644 --- a/ports_module/cortex_m3/ac6/module_manager/src/txm_module_manager_alignment_adjust.c +++ b/ports_module/cortex_m3/ac6/module_manager/src/txm_module_manager_alignment_adjust.c @@ -30,8 +30,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _txm_power_of_two_block_size Cortex-M3/MPU/AC6 */ -/* 6.1 */ +/* _txm_power_of_two_block_size Cortex-M3 */ +/* 6.1.9 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -61,7 +61,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ /* */ /**************************************************************************/ ULONG _txm_power_of_two_block_size(ULONG size) @@ -93,8 +93,8 @@ ULONG _txm_power_of_two_block_size(ULONG size) /* */ /* FUNCTION RELEASE */ /* */ -/* _txm_module_manager_alignment_adjust Cortex-M3/MPU/AC6 */ -/* 6.1 */ +/* _txm_module_manager_alignment_adjust Cortex-M3 */ +/* 6.1.9 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -128,7 +128,7 @@ ULONG _txm_power_of_two_block_size(ULONG size) /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ /* */ /**************************************************************************/ VOID _txm_module_manager_alignment_adjust(TXM_MODULE_PREAMBLE *module_preamble, @@ -137,6 +137,53 @@ VOID _txm_module_manager_alignment_adjust(TXM_MODULE_PREAMBLE *module_preamble, ULONG *data_size, ULONG *data_alignment) { +#ifdef TXM_MODULE_MANAGER_16_MPU +ULONG local_code_size; +ULONG local_code_alignment; +ULONG local_data_size; +ULONG local_data_alignment; +ULONG code_size_accum; +ULONG data_size_accum; + + /* Copy the input parameters into local variables for ease of use. */ + local_code_size = *code_size; + local_code_alignment = *code_alignment; + local_data_size = *data_size; + local_data_alignment = *data_alignment; + + /* Determine code block sizes. Minimize the alignment requirement. + There are 4 MPU code entries available. The following is how the code size + will be distributed: + 1. 1/4 of the largest power of two that is greater than or equal to code size. + 2. 1/4 of the largest power of two that is greater than or equal to code size. + 3. Largest power of 2 that fits in the remaining space. + 4. Smallest power of 2 that exceeds the remaining space, minimum 32. */ + local_code_alignment = _txm_power_of_two_block_size(local_code_size) >> 2; + code_size_accum = local_code_alignment + local_code_alignment; + code_size_accum = code_size_accum + (_txm_power_of_two_block_size(local_code_size - code_size_accum) >> 1); + code_size_accum = code_size_accum + _txm_power_of_two_block_size(local_code_size - code_size_accum); + local_code_size = code_size_accum; + + /* Determine data block sizes. Minimize the alignment requirement. + There are 4 MPU data entries available. The following is how the data size + will be distributed: + 1. 1/4 of the largest power of two that is greater than or equal to data size. + 2. 1/4 of the largest power of two that is greater than or equal to data size. + 3. Largest power of 2 that fits in the remaining space. + 4. Smallest power of 2 that exceeds the remaining space, minimum 32. */ + local_data_alignment = _txm_power_of_two_block_size(local_data_size) >> 2; + data_size_accum = local_data_alignment + local_data_alignment; + data_size_accum = data_size_accum + (_txm_power_of_two_block_size(local_data_size - data_size_accum) >> 1); + data_size_accum = data_size_accum + _txm_power_of_two_block_size(local_data_size - data_size_accum); + local_data_size = data_size_accum; + + /* Return all the information to the caller. */ + *code_size = local_code_size; + *code_alignment = local_code_alignment; + *data_size = local_data_size; + *data_alignment = local_data_alignment; + +#else ULONG local_code_size; ULONG local_code_alignment; @@ -396,4 +443,6 @@ ULONG data_size_accum; *code_alignment = local_code_alignment; *data_size = local_data_size; *data_alignment = local_data_alignment; + +#endif } diff --git a/ports_module/cortex_m3/ac6/module_manager/src/txm_module_manager_external_memory_enable.c b/ports_module/cortex_m3/ac6/module_manager/src/txm_module_manager_external_memory_enable.c index 0e57c7c1..cb13e4a6 100644 --- a/ports_module/cortex_m3/ac6/module_manager/src/txm_module_manager_external_memory_enable.c +++ b/ports_module/cortex_m3/ac6/module_manager/src/txm_module_manager_external_memory_enable.c @@ -33,8 +33,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _txm_module_manager_external_memory_enable Cortex-M3/MPU/AC6 */ -/* 6.1 */ +/* _txm_module_manager_external_memory_enable Cortex-M3 */ +/* 6.1.9 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -70,7 +70,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ /* */ /**************************************************************************/ UINT _txm_module_manager_external_memory_enable(TXM_MODULE_INSTANCE *module_instance, @@ -78,6 +78,117 @@ UINT _txm_module_manager_external_memory_enable(TXM_MODULE_INSTANCE *module_ins ULONG length, UINT attributes) { +#ifdef TXM_MODULE_MANAGER_16_MPU +ULONG block_size; +ULONG region_size; +ULONG srd_bits; +ULONG size_register; +ULONG address; +ULONG shared_index; +ULONG attributes_check = 0; + + /* Determine if the module manager has not been initialized yet. */ + if (_txm_module_manager_ready != TX_TRUE) + { + /* Module manager has not been initialized. */ + return(TX_NOT_AVAILABLE); + } + + /* Determine if the module is valid. */ + if (module_instance == TX_NULL) + { + /* Invalid module pointer. */ + return(TX_PTR_ERROR); + } + + /* Get module manager protection mutex. */ + _tx_mutex_get(&_txm_module_manager_mutex, TX_WAIT_FOREVER); + + /* Determine if the module instance is valid. */ + if (module_instance -> txm_module_instance_id != TXM_MODULE_ID) + { + /* Release the protection mutex. */ + _tx_mutex_put(&_txm_module_manager_mutex); + + /* Invalid module pointer. */ + return(TX_PTR_ERROR); + } + + /* Determine if the module instance is in the loaded state. */ + if (module_instance -> txm_module_instance_state != TXM_MODULE_LOADED) + { + /* Release the protection mutex. */ + _tx_mutex_put(&_txm_module_manager_mutex); + + /* Return error if the module is not ready. */ + return(TX_START_ERROR); + } + + /* Determine if there are shared memory entries available. */ + if(module_instance -> txm_module_instance_shared_memory_count >= TXM_MODULE_MPU_SHARED_ENTRIES) + { + /* Release the protection mutex. */ + _tx_mutex_put(&_txm_module_manager_mutex); + + /* No more entries available. */ + return(TX_NO_MEMORY); + } + + /* Start address and length must adhere to Cortex-M7 MPU. + The address must align with the block size. */ + + block_size = _txm_power_of_two_block_size(length); + address = (ULONG) start_address; + if(address != (address & ~(block_size - 1))) + { + /* Release the protection mutex. */ + _tx_mutex_put(&_txm_module_manager_mutex); + + /* Return alignment error. */ + return(TXM_MODULE_ALIGNMENT_ERROR); + } + + /* At this point, we have a valid address and block size. + Set up MPU registers. */ + + /* Pick up index into shared memory entries. */ + shared_index = TXM_MODULE_MPU_SHARED_INDEX + module_instance -> txm_module_instance_shared_memory_count; + + /* Save address register with address, MPU region, set Valid bit. */ + module_instance -> txm_module_instance_mpu_registers[shared_index].txm_module_mpu_region_address = address | shared_index | 0x10; + + /* Calculate the region size. */ + region_size = (_txm_module_manager_region_size_get(block_size) << 1); + + /* Calculate the subregion bits. */ + srd_bits = _txm_module_manager_calculate_srd_bits(block_size, length); + + /* Generate SRD, size, and enable attributes. */ + size_register = srd_bits | region_size | TXM_ENABLE_REGION | TXM_MODULE_MPU_SHARED_ACCESS_CONTROL; + + /* Check for optional write attribute. */ + if(attributes & TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE) + { + attributes_check = TXM_MODULE_MANAGER_ATTRIBUTE_WRITE_MPU_BIT; + } + + /* Save attribute-size register. */ + module_instance -> txm_module_instance_mpu_registers[shared_index].txm_module_mpu_region_attribute_size = attributes_check | size_register; + + /* Keep track of shared memory address and length in module instance. */ + module_instance -> txm_module_instance_shared_memory_address[module_instance -> txm_module_instance_shared_memory_count] = address; + module_instance -> txm_module_instance_shared_memory_length[module_instance -> txm_module_instance_shared_memory_count] = length; + + /* Increment counter. */ + module_instance -> txm_module_instance_shared_memory_count++; + + /* Release the protection mutex. */ + _tx_mutex_put(&_txm_module_manager_mutex); + + /* Return success. */ + return(TX_SUCCESS); + +#else ULONG block_size; ULONG region_size; @@ -179,4 +290,6 @@ TXM_MODULE_PREAMBLE *module_preamble; /* Return success. */ return(TX_SUCCESS); + +#endif } diff --git a/ports_module/cortex_m3/ac6/module_manager/src/txm_module_manager_memory_fault_handler.c b/ports_module/cortex_m3/ac6/module_manager/src/txm_module_manager_memory_fault_handler.c index b435d107..bcaa98aa 100644 --- a/ports_module/cortex_m3/ac6/module_manager/src/txm_module_manager_memory_fault_handler.c +++ b/ports_module/cortex_m3/ac6/module_manager/src/txm_module_manager_memory_fault_handler.c @@ -45,8 +45,8 @@ TXM_MODULE_MANAGER_FAULT_INFO /* */ /* FUNCTION RELEASE */ /* */ -/* _txm_module_manager_memory_fault_handler Cortex-M3/MPU/AC6 */ -/* 6.1 */ +/* _txm_module_manager_memory_fault_handler Cortex-M3 */ +/* 6.1.9 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -76,7 +76,7 @@ TXM_MODULE_MANAGER_FAULT_INFO /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ /* */ /**************************************************************************/ VOID _txm_module_manager_memory_fault_handler(VOID) diff --git a/ports_module/cortex_m3/ac6/module_manager/src/txm_module_manager_memory_fault_notify.c b/ports_module/cortex_m3/ac6/module_manager/src/txm_module_manager_memory_fault_notify.c index f83a982f..dac86312 100644 --- a/ports_module/cortex_m3/ac6/module_manager/src/txm_module_manager_memory_fault_notify.c +++ b/ports_module/cortex_m3/ac6/module_manager/src/txm_module_manager_memory_fault_notify.c @@ -38,8 +38,8 @@ extern VOID (*_txm_module_manager_fault_notify)(TX_THREAD *, TXM_MODULE_INSTA /* */ /* FUNCTION RELEASE */ /* */ -/* _txm_module_manager_memory_fault_notify Cortex-M3/MPU/AC6 */ -/* 6.1 */ +/* _txm_module_manager_memory_fault_notify Cortex-M3 */ +/* 6.1.9 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -71,7 +71,7 @@ extern VOID (*_txm_module_manager_fault_notify)(TX_THREAD *, TXM_MODULE_INSTA /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ /* */ /**************************************************************************/ UINT _txm_module_manager_memory_fault_notify(VOID (*notify_function)(TX_THREAD *, TXM_MODULE_INSTANCE *)) diff --git a/ports_module/cortex_m3/ac6/module_manager/src/txm_module_manager_mm_register_setup.c b/ports_module/cortex_m3/ac6/module_manager/src/txm_module_manager_mm_register_setup.c index a2e4dfa1..48a14571 100644 --- a/ports_module/cortex_m3/ac6/module_manager/src/txm_module_manager_mm_register_setup.c +++ b/ports_module/cortex_m3/ac6/module_manager/src/txm_module_manager_mm_register_setup.c @@ -30,8 +30,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _txm_module_manager_region_size_get Cortex-M3/MPU */ -/* 6.1 */ +/* _txm_module_manager_region_size_get Cortex-M3 */ +/* 6.1.9 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -61,7 +61,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ /* */ /**************************************************************************/ ULONG _txm_module_manager_region_size_get(ULONG block_size) @@ -152,8 +152,8 @@ ULONG return_value; /* */ /* FUNCTION RELEASE */ /* */ -/* _txm_module_manager_calculate_srd_bits Cortex-M3/MPU/AC6 */ -/* 6.1 */ +/* _txm_module_manager_calculate_srd_bits Cortex-M3 */ +/* 6.1.9 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -184,7 +184,7 @@ ULONG return_value; /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ /* */ /**************************************************************************/ ULONG _txm_module_manager_calculate_srd_bits(ULONG block_size, ULONG length) @@ -230,16 +230,48 @@ UINT srd_bit_index; /* */ /* FUNCTION RELEASE */ /* */ -/* _txm_module_manager_mm_register_setup Cortex-M3/MPU */ -/* 6.1 */ +/* _txm_module_manager_mm_register_setup Cortex-M3 */ +/* 6.1.9 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ /* */ /* DESCRIPTION */ /* */ -/* This function sets up the Cortex-M3 MPU register definitions based */ -/* on the module's memory characteristics. */ +/* This function sets up the MPU register definitions based on the */ +/* module's memory characteristics. */ +/* */ +/* Default MPU layout: */ +/* Entry Description */ +/* 0 Kernel mode entry */ +/* 1 Module code region */ +/* 2 Module code region */ +/* 3 Module code region */ +/* 4 Module code region */ +/* 5 Module data region */ +/* 6 Module data region */ +/* 7 Module data region */ +/* */ +/* If TXM_MODULE_MANAGER_16_MPU is defined, there are 16 MPU slots. */ +/* MPU layout for the Cortex-M7: */ +/* Entry Description */ +/* 0 Kernel mode entry */ +/* 1 Module code region */ +/* 2 Module code region */ +/* 3 Module code region */ +/* 4 Module code region */ +/* 5 Module data region */ +/* 6 Module data region */ +/* 7 Module data region */ +/* 8 Module data region */ +/* 9 Module shared memory region */ +/* 10 Module shared memory region */ +/* 11 Module shared memory region */ +/* 12 Unused region */ +/* 13 Unused region */ +/* 14 Unused region */ +/* 15 Unused region */ +/* */ /* */ /* INPUT */ /* */ @@ -261,11 +293,181 @@ UINT srd_bit_index; /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ /* */ /**************************************************************************/ VOID _txm_module_manager_mm_register_setup(TXM_MODULE_INSTANCE *module_instance) { +#ifdef TXM_MODULE_MANAGER_16_MPU + +ULONG code_address; +ULONG code_size; +ULONG data_address; +ULONG data_size; +ULONG start_stop_stack_size; +ULONG callback_stack_size; +ULONG block_size; +ULONG region_size; +ULONG srd_bits = 0; +UINT mpu_table_index; +UINT i; + + + /* Setup the first MPU region for kernel mode entry. */ + /* Set address register to user mode entry function address, which is guaranteed to be at least 32-byte aligned. + Mask address to proper range, region 0, set Valid bit. */ + module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MPU_KERNEL_ENTRY_INDEX].txm_module_mpu_region_address = ((ULONG) _txm_module_manager_user_mode_entry & 0xFFFFFFE0) | 0x10; + /* Set the attributes, size (32 bytes) and enable bit. */ + module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MPU_KERNEL_ENTRY_INDEX].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_CODE_ACCESS_CONTROL | (_txm_module_manager_region_size_get(32) << 1) | TXM_ENABLE_REGION; + /* End of kernel mode entry setup. */ + + /* Setup code protection. */ + + /* Initialize the MPU table index. */ + mpu_table_index = 1; + + /* Pickup code starting address and actual size. */ + code_address = (ULONG) module_instance -> txm_module_instance_code_start; + code_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_code_size; + + /* Determine code block sizes. Minimize the alignment requirement. + There are 4 MPU code entries available. The following is how the code size + will be distributed: + 1. 1/4 of the largest power of two that is greater than or equal to code size. + 2. 1/4 of the largest power of two that is greater than or equal to code size. + 3. Largest power of 2 that fits in the remaining space. + 4. Smallest power of 2 that exceeds the remaining space, minimum 32. */ + + /* Now loop through to setup MPU protection for the code area. */ + for (i = 0; i < TXM_MODULE_MPU_CODE_ENTRIES; i++) + { + /* First two MPU blocks are 1/4 of the largest power of two + that is greater than or equal to code size. */ + if (i < 2) + { + block_size = _txm_power_of_two_block_size(code_size) >> 2; + } + + /* Third MPU block is the largest power of 2 that fits in the remaining space. */ + else if (i == 2) + { + /* Subtract (block_size*2) from code_size to calculate remaining space. */ + code_size = code_size - (block_size << 1); + block_size = _txm_power_of_two_block_size(code_size) >> 1; + } + + /* Last MPU block is the smallest power of 2 that exceeds the remaining space, minimum 32. */ + else + { + /* Calculate remaining space. */ + code_size = code_size - block_size; + block_size = _txm_power_of_two_block_size(code_size); + srd_bits = _txm_module_manager_calculate_srd_bits(block_size, code_size); + } + + /* Calculate the region size information. */ + region_size = (_txm_module_manager_region_size_get(block_size) << 1); + + /* Build the base address register with address, MPU region, set Valid bit. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_address = (code_address & ~(block_size - 1)) | mpu_table_index | 0x10; + /* Build the attribute-size register with permissions, SRD, size, enable. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_CODE_ACCESS_CONTROL | srd_bits | region_size | TXM_ENABLE_REGION; + + /* Adjust the code address. */ + code_address = code_address + block_size; + + /* Increment MPU table index. */ + mpu_table_index++; + } + /* End of code protection. */ + + /* Setup data protection. */ + + /* Reset SRD bitfield. */ + srd_bits = 0; + + /* Pickup data starting address and actual size. */ + data_address = (ULONG) module_instance -> txm_module_instance_data_start; + + /* Adjust the size of the module elements to be aligned to the default alignment. We do this + so that when we partition the allocated memory, we can simply place these regions right beside + each other without having to align their pointers. Note this only works when they all have + the same alignment. */ + + data_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_data_size; + start_stop_stack_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_start_stop_stack_size; + callback_stack_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_callback_stack_size; + + data_size = ((data_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; + + start_stop_stack_size = ((start_stop_stack_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; + + callback_stack_size = ((callback_stack_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; + + /* Update the data size to include thread stacks. */ + data_size = data_size + start_stop_stack_size + callback_stack_size; + + /* Determine data block sizes. Minimize the alignment requirement. + There are 4 MPU data entries available. The following is how the data size + will be distributed: + 1. 1/4 of the largest power of two that is greater than or equal to data size. + 2. 1/4 of the largest power of two that is greater than or equal to data size. + 3. Largest power of 2 that fits in the remaining space. + 4. Smallest power of 2 that exceeds the remaining space, minimum 32. */ + + /* Now loop through to setup MPU protection for the data area. */ + for (i = 0; i < TXM_MODULE_MPU_DATA_ENTRIES; i++) + { + /* First two MPU blocks are 1/4 of the largest power of two + that is greater than or equal to data size. */ + if (i < 2) + { + block_size = _txm_power_of_two_block_size(data_size) >> 2; + } + + /* Third MPU block is the largest power of 2 that fits in the remaining space. */ + else if (i == 2) + { + /* Subtract (block_size*2) from data_size to calculate remaining space. */ + data_size = data_size - (block_size << 1); + block_size = _txm_power_of_two_block_size(data_size) >> 1; + } + + /* Last MPU block is the smallest power of 2 that exceeds the remaining space, minimum 32. */ + else + { + /* Calculate remaining space. */ + data_size = data_size - block_size; + block_size = _txm_power_of_two_block_size(data_size); + srd_bits = _txm_module_manager_calculate_srd_bits(block_size, data_size); + } + + /* Calculate the region size information. */ + region_size = (_txm_module_manager_region_size_get(block_size) << 1); + + /* Build the base address register with address, MPU region, set Valid bit. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_address = (data_address & ~(block_size - 1)) | mpu_table_index | 0x10; + /* Build the attribute-size register with permissions, SRD, size, enable. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_DATA_ACCESS_CONTROL | srd_bits | region_size | TXM_ENABLE_REGION; + + /* Adjust the data address. */ + data_address = data_address + block_size; + + /* Increment MPU table index. */ + mpu_table_index++; + } + + /* Setup MPU for the remaining regions. */ + while (mpu_table_index < TXM_MODULE_MPU_TOTAL_ENTRIES) + { + /* Build the base address register with address, MPU region, set Valid bit. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_address = mpu_table_index | 0x10; + + /* Increment MPU table index. */ + mpu_table_index++; + } + +#else ULONG code_address; ULONG code_size; @@ -382,7 +584,7 @@ UINT i; for (i = 0; i < TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1; i++) { /* Build the base address register. */ - base_address_register = code_address & ~(block_size - 1) | mpu_register | 0x10; + base_address_register = (code_address & ~(block_size - 1)) | mpu_register | 0x10; /* Check if SRD bits need to be set. */ if (code_size < block_size) @@ -509,4 +711,87 @@ UINT i; /* Increment the MPU register index. */ mpu_register++; } + +#endif +} + +#ifdef TXM_MODULE_MANAGER_16_MPU +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_inside_data_check Cortex-M3 */ +/* 6.1.9 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks if the specified object is inside shared */ +/* memory. */ +/* */ +/* INPUT */ +/* */ +/* module_instance Pointer to module instance */ +/* obj_ptr Pointer to the object */ +/* obj_size Size of the object */ +/* */ +/* OUTPUT */ +/* */ +/* Whether the object is inside the shared memory region. */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Module dispatch check functions */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ +/* */ +/**************************************************************************/ +UINT _txm_module_manager_inside_data_check(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE obj_ptr, UINT obj_size) +{ + +UINT shared_memory_index; +UINT num_shared_memory_mpu_entries; +ALIGN_TYPE shared_memory_address_start; +ALIGN_TYPE shared_memory_address_end; + + /* Check for overflow. */ + if ((obj_ptr) > ((obj_ptr) + (obj_size))) + { + return(TX_FALSE); + } + + /* Check if the object is inside the module data. */ + if ((obj_ptr >= (ALIGN_TYPE) module_instance -> txm_module_instance_data_start) && + ((obj_ptr + obj_size) <= ((ALIGN_TYPE) module_instance -> txm_module_instance_data_end + 1))) + { + return(TX_TRUE); + } + + /* Check if the object is inside the shared memory. */ + num_shared_memory_mpu_entries = module_instance -> txm_module_instance_shared_memory_count; + for (shared_memory_index = 0; shared_memory_index < num_shared_memory_mpu_entries; shared_memory_index++) + { + + shared_memory_address_start = (ALIGN_TYPE) module_instance -> txm_module_instance_shared_memory_address[shared_memory_index]; + shared_memory_address_end = shared_memory_address_start + module_instance -> txm_module_instance_shared_memory_length[shared_memory_index]; + + if ((obj_ptr >= (ALIGN_TYPE) shared_memory_address_start) && + ((obj_ptr + obj_size) <= (ALIGN_TYPE) shared_memory_address_end)) + { + return(TX_TRUE); + } + } + + return(TX_FALSE); } +#endif diff --git a/ports_module/cortex_m3/ac6/module_manager/src/txm_module_manager_thread_stack_build.S b/ports_module/cortex_m3/ac6/module_manager/src/txm_module_manager_thread_stack_build.S index 9d0b5a06..4b4969e8 100644 --- a/ports_module/cortex_m3/ac6/module_manager/src/txm_module_manager_thread_stack_build.S +++ b/ports_module/cortex_m3/ac6/module_manager/src/txm_module_manager_thread_stack_build.S @@ -27,8 +27,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _txm_module_manager_thread_stack_build Cortex-M3/MPU/AC6 */ -/* 6.1 */ +/* _txm_module_manager_thread_stack_build Cortex-M3/AC6 */ +/* 6.1.9 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -60,7 +60,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ /* */ /**************************************************************************/ // VOID _txm_module_manager_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(TX_THREAD *, TXM_MODULE_INSTANCE *)) diff --git a/ports_module/cortex_m3/gnu/inc/tx_port.h b/ports_module/cortex_m3/gnu/inc/tx_port.h index 8d6be046..a3f91e24 100644 --- a/ports_module/cortex_m3/gnu/inc/tx_port.h +++ b/ports_module/cortex_m3/gnu/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h Cortex-M3/GNU */ -/* 6.1 */ +/* 6.1.9 */ /* */ /* AUTHOR */ /* */ @@ -47,10 +47,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ -/* macro definition, */ -/* resulting in version 6.1.6 */ +/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ /* */ /**************************************************************************/ @@ -116,7 +113,7 @@ typedef unsigned short USHORT; #endif -/* Define various constants for the ThreadX Cortex-M7 port. */ +/* Define various constants for the ThreadX Cortex-M3 port. */ #define TX_INT_DISABLE 1 /* Disable interrupts */ #define TX_INT_ENABLE 0 /* Enable interrupts */ @@ -142,7 +139,7 @@ typedef unsigned short USHORT; /* Define the port specific options for the _tx_build_options variable. This variable indicates how the ThreadX library was built. */ -#define TX_PORT_SPECIFIC_BUILD_OPTIONS 0 +#define TX_PORT_SPECIFIC_BUILD_OPTIONS (0) /* Define the in-line initialization constant so that modules with in-line @@ -217,8 +214,140 @@ typedef unsigned short USHORT; #define TX_THREAD_CREATE_EXTENSION(thread_ptr) #define TX_THREAD_DELETE_EXTENSION(thread_ptr) + +#ifdef TX_ENABLE_FPU_SUPPORT + + +#ifdef TX_MISRA_ENABLE + +ULONG _tx_misra_control_get(void); +void _tx_misra_control_set(ULONG value); +ULONG _tx_misra_fpccr_get(void); +void _tx_misra_vfp_touch(void); + +#else + +__attribute__( ( always_inline ) ) static inline ULONG __get_control(void) +{ + +ULONG control_value; + + __asm__ volatile (" MRS %0,CONTROL ": "=r" (control_value) ); + return(control_value); +} + + +__attribute__( ( always_inline ) ) static inline void __set_control(ULONG control_value) +{ + + __asm__ volatile (" MSR CONTROL,%0": : "r" (control_value): "memory" ); +} + + +#endif + + +/* A completed thread falls into _thread_shell_entry and we can simply deactivate the FPU via CONTROL.FPCA + in order to ensure no lazy stacking will occur. */ + +#ifndef TX_MISRA_ENABLE + +#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) { \ + ULONG _tx_vfp_state; \ + _tx_vfp_state = __get_control(); \ + _tx_vfp_state = _tx_vfp_state & ~((ULONG) 0x4); \ + __set_control(_tx_vfp_state); \ + } +#else + +#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) { \ + ULONG _tx_vfp_state; \ + _tx_vfp_state = _tx_misra_control_get(); \ + _tx_vfp_state = _tx_vfp_state & ~((ULONG) 0x4); \ + _tx_misra_control_set(_tx_vfp_state); \ + } + +#endif + + +/* A thread can be terminated by another thread, so we first check if it's self-terminating and not in an ISR. + If so, deactivate the FPU via CONTROL.FPCA. Otherwise we are in an interrupt or another thread is terminating + this one, so if the FPCCR.LSPACT bit is set, we need to save the CONTROL.FPCA state, touch the FPU to flush + the lazy FPU save, then restore the CONTROL.FPCA state. */ + +#ifndef TX_MISRA_ENABLE + + +#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) { \ + ULONG _tx_system_state; \ + _tx_system_state = TX_THREAD_GET_SYSTEM_STATE(); \ + if ((_tx_system_state == ((ULONG) 0)) && ((thread_ptr) == _tx_thread_current_ptr)) \ + { \ + ULONG _tx_vfp_state; \ + _tx_vfp_state = __get_control(); \ + _tx_vfp_state = _tx_vfp_state & ~((ULONG) 0x4); \ + __set_control(_tx_vfp_state); \ + } \ + else \ + { \ + ULONG _tx_fpccr; \ + _tx_fpccr = *((ULONG *) 0xE000EF34); \ + _tx_fpccr = _tx_fpccr & ((ULONG) 0x01); \ + if (_tx_fpccr == ((ULONG) 0x01)) \ + { \ + ULONG _tx_vfp_state; \ + _tx_vfp_state = __get_control(); \ + _tx_vfp_state = _tx_vfp_state & ((ULONG) 0x4); \ + __asm__ volatile ("vmov.f32 s0, s0"); \ + if (_tx_vfp_state == ((ULONG) 0)) \ + { \ + _tx_vfp_state = __get_control(); \ + _tx_vfp_state = _tx_vfp_state & ~((ULONG) 0x4); \ + __set_control(_tx_vfp_state); \ + } \ + } \ + } \ + } +#else + +#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) { \ + ULONG _tx_system_state; \ + _tx_system_state = TX_THREAD_GET_SYSTEM_STATE(); \ + if ((_tx_system_state == ((ULONG) 0)) && ((thread_ptr) == _tx_thread_current_ptr)) \ + { \ + ULONG _tx_vfp_state; \ + _tx_vfp_state = _tx_misra_control_get(); \ + _tx_vfp_state = _tx_vfp_state & ~((ULONG) 0x4); \ + _tx_misra_control_set(_tx_vfp_state); \ + } \ + else \ + { \ + ULONG _tx_fpccr; \ + _tx_fpccr = _tx_misra_fpccr_get(); \ + _tx_fpccr = _tx_fpccr & ((ULONG) 0x01); \ + if (_tx_fpccr == ((ULONG) 0x01)) \ + { \ + ULONG _tx_vfp_state; \ + _tx_vfp_state = _tx_misra_control_get(); \ + _tx_vfp_state = _tx_vfp_state & ((ULONG) 0x4); \ + _tx_misra_vfp_touch(); \ + if (_tx_vfp_state == ((ULONG) 0)) \ + { \ + _tx_vfp_state = _tx_misra_control_get(); \ + _tx_vfp_state = _tx_vfp_state & ~((ULONG) 0x4); \ + _tx_misra_control_set(_tx_vfp_state); \ + } \ + } \ + } \ + } +#endif + +#else + #define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) -#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) +#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) + +#endif /* Define the ThreadX object creation extensions for the remaining objects. */ @@ -273,6 +402,7 @@ ULONG _tx_misra_ipsr_get(VOID); #define TX_THREAD_SYSTEM_RETURN_CHECK(c) (c) = ((ULONG) _tx_thread_preempt_disable); #endif + /* Define the macro to ensure _tx_thread_preempt_disable is set early in initialization in order to prevent early scheduling on Cortex-M parts. */ @@ -361,19 +491,21 @@ unsigned int interrupt_save; #endif +/* Define FPU extension for the Cortex-M7. Each is assumed to be called in the context of the executing + thread. This is for legacy only, and not needed any longer. */ + +void tx_thread_fpu_enable(void); +void tx_thread_fpu_disable(void); + + /* Define the version ID of ThreadX. This may be utilized by the application. */ #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M3/GNU Version 6.1.6 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M3/GNU Version 6.1.9 *"; #else extern CHAR _tx_version_id[]; #endif #endif - - - - - diff --git a/ports_module/cortex_m3/gnu/inc/txm_module_port.h b/ports_module/cortex_m3/gnu/inc/txm_module_port.h index 01102ffa..58ed9614 100644 --- a/ports_module/cortex_m3/gnu/inc/txm_module_port.h +++ b/ports_module/cortex_m3/gnu/inc/txm_module_port.h @@ -25,8 +25,8 @@ /* */ /* APPLICATION INTERFACE DEFINITION RELEASE */ /* */ -/* txm_module_port.h Cortex-M3/MPU/GNU */ -/* 6.1.6 */ +/* txm_module_port.h Cortex-M3/GNU */ +/* 6.1.9 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -40,10 +40,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 04-02-2021 Scott Larson Modified comment(s) and */ -/* added check for overflow, */ -/* resulting in version 6.1.6 */ +/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ /* */ /**************************************************************************/ @@ -94,16 +91,26 @@ The following extensions must also be defined in tx_port.h: VOID (*tx_timer_module_expiration_function)(ULONG id); */ - -/* Size of module heap. */ -#define TXM_MODULE_HEAP_SIZE 512 - - /* Define the kernel stack size for a module thread. */ #ifndef TXM_MODULE_KERNEL_STACK_SIZE #define TXM_MODULE_KERNEL_STACK_SIZE 768 #endif +/* For the following 3 access control settings, change TEX and C, B, S (bits 21 through 16 of MPU_RASR) + * to reflect your system memory attributes (cache, shareable, memory type). */ +/* Code region access control: privileged read-only, outer & inner write-back, normal memory, shareable. */ +#ifndef TXM_MODULE_MPU_CODE_ACCESS_CONTROL +#define TXM_MODULE_MPU_CODE_ACCESS_CONTROL 0x06070000 +#endif +/* Data region access control: execute never, read/write, outer & inner write-back, normal memory, shareable. */ +#ifndef TXM_MODULE_MPU_DATA_ACCESS_CONTROL +#define TXM_MODULE_MPU_DATA_ACCESS_CONTROL 0x13070000 +#endif +/* Shared region access control: execute never, read-only, outer & inner write-back, normal memory, shareable. */ +#ifndef TXM_MODULE_MPU_SHARED_ACCESS_CONTROL +#define TXM_MODULE_MPU_SHARED_ACCESS_CONTROL 0x12070000 +#endif + /* Define constants specific to the tools the module can be built with for this particular modules port. */ #define TXM_MODULE_IAR_COMPILER 0x00000000 @@ -158,8 +165,43 @@ The following extensions must also be defined in tx_port.h: #define INLINE_DECLARE inline +#ifdef TXM_MODULE_MANAGER_16_MPU + /* Define the number of MPU entries assigned to the code and data sections. - On Cortex-M3 parts, there are 8 total entries. ThreadX uses one for access + On some Cortex-M7 parts, there are 16 total entries. ThreadX uses one for access + to the kernel entry function, thus 15 remain for code and data protection. */ +#define TXM_MODULE_MPU_TOTAL_ENTRIES 16 +#define TXM_MODULE_MPU_CODE_ENTRIES 4 +#define TXM_MODULE_MPU_DATA_ENTRIES 4 +#define TXM_MODULE_MPU_SHARED_ENTRIES 3 + +#define TXM_MODULE_MPU_KERNEL_ENTRY_INDEX 0 +#define TXM_MODULE_MPU_SHARED_INDEX 9 + +#define TXM_ENABLE_REGION 0x01 + +/* There are 2 registers to set up each MPU region: MPU_RBAR, MPU_RASR. */ +typedef struct TXM_MODULE_MPU_INFO_STRUCT +{ + ULONG txm_module_mpu_region_address; + ULONG txm_module_mpu_region_attribute_size; +} TXM_MODULE_MPU_INFO; +/* Shared memory region attributes. */ +#define TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE 1 +#define TXM_MODULE_MANAGER_ATTRIBUTE_WRITE_MPU_BIT 0x01000000 + +/* Define the port-extensions to the module manager instance structure. */ + +#define TXM_MODULE_MANAGER_PORT_EXTENSION \ + TXM_MODULE_MPU_INFO txm_module_instance_mpu_registers[TXM_MODULE_MPU_TOTAL_ENTRIES]; \ + ULONG txm_module_instance_shared_memory_count; \ + ULONG txm_module_instance_shared_memory_address[TXM_MODULE_MPU_SHARED_ENTRIES]; \ + ULONG txm_module_instance_shared_memory_length[TXM_MODULE_MPU_SHARED_ENTRIES]; + +#else /* TXM_MODULE_MANAGER_16_MPU is not defined */ + +/* Define the number of MPU entries assigned to the code and data sections. + On Cortex-M3, M4, and some M7 parts, there are 8 total entries. ThreadX uses one for access to the kernel entry function, thus 7 remain for code and data protection. */ #define TXM_MODULE_MANAGER_CODE_MPU_ENTRIES 4 #define TXM_MODULE_MANAGER_DATA_MPU_ENTRIES 3 @@ -177,6 +219,7 @@ The following extensions must also be defined in tx_port.h: ULONG txm_module_instance_shared_memory_address; \ ULONG txm_module_instance_shared_memory_length; +#endif /* TXM_MODULE_MANAGER_16_MPU */ /* Define the memory fault information structure that is populated when a memory fault occurs. */ @@ -299,6 +342,10 @@ typedef struct TXM_MODULE_MANAGER_MEMORY_FAULT_INFO_STRUCT /* Define the macros to perform port-specific checks when passing pointers to the kernel. */ /* Define macro to make sure object is inside the module's data. */ +#ifdef TXM_MODULE_MANAGER_16_MPU +#define TXM_MODULE_MANAGER_CHECK_INSIDE_DATA(module_instance, obj_ptr, obj_size) \ + _txm_module_manager_inside_data_check(module_instance, obj_ptr, obj_size) +#else #define TXM_MODULE_MANAGER_CHECK_INSIDE_DATA(module_instance, obj_ptr, obj_size) \ /* Check for overflow. */ \ (((obj_ptr) < ((obj_ptr) + (obj_size))) && \ @@ -308,7 +355,7 @@ typedef struct TXM_MODULE_MANAGER_MEMORY_FAULT_INFO_STRUCT /* Check if it's inside shared memory. */ \ (((obj_ptr) >= (ALIGN_TYPE) module_instance -> txm_module_instance_shared_memory_address) && \ (((obj_ptr) + (obj_size)) <= (ALIGN_TYPE) (module_instance -> txm_module_instance_shared_memory_address + module_instance -> txm_module_instance_shared_memory_length))))) - +#endif /* Define some internal prototypes to this module port. */ @@ -324,10 +371,11 @@ UINT _txm_module_manager_memory_fault_notify(VOID (*notify_function)(TX_THREAD VOID _txm_module_manager_mm_register_setup(TXM_MODULE_INSTANCE *module_instance); \ ULONG _txm_power_of_two_block_size(ULONG size); \ ULONG _txm_module_manager_calculate_srd_bits(ULONG block_size, ULONG length); \ -ULONG _txm_module_manager_region_size_get(ULONG block_size); +ULONG _txm_module_manager_region_size_get(ULONG block_size); \ +UINT _txm_module_manager_inside_data_check(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE obj_ptr, UINT obj_size); #define TXM_MODULE_MANAGER_VERSION_ID \ -CHAR _txm_module_manager_version_id[] = \ - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-M3/MPU/GNU Version 6.1.8 *"; +CHAR _txm_module_manager_version_id[] = \ + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-M3/GNU Version 6.1.9 *"; #endif diff --git a/ports_module/cortex_m3/gnu/module_lib/src/txm_module_thread_shell_entry.c b/ports_module/cortex_m3/gnu/module_lib/src/txm_module_thread_shell_entry.c index 87b73b9b..f6248204 100644 --- a/ports_module/cortex_m3/gnu/module_lib/src/txm_module_thread_shell_entry.c +++ b/ports_module/cortex_m3/gnu/module_lib/src/txm_module_thread_shell_entry.c @@ -44,7 +44,7 @@ TXM_MODULE_THREAD_ENTRY_INFO *_txm_module_entry_info; ULONG (*_txm_module_kernel_call_dispatcher)(ULONG kernel_request, ULONG param_1, ULONG param_2, ULONG param3); -/* Define the GCC startup code that clears the uninitialized global data and sets up the +/* Define the startup code that clears the uninitialized global data and sets up the preset global variables. */ extern VOID _gcc_setup(TXM_MODULE_INSTANCE *); @@ -54,15 +54,15 @@ extern VOID _gcc_setup(TXM_MODULE_INSTANCE *); /* */ /* FUNCTION RELEASE */ /* */ -/* _txm_module_thread_shell_entry Cortex-M3/MPU/GNU */ -/* 6.1 */ +/* _txm_module_thread_shell_entry Cortex-M3/GNU */ +/* 6.1.9 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ /* */ /* DESCRIPTION */ /* */ -/* This function calls the specified entry function of the thread. It */ +/* This function calls the specified entry function of the thread. It */ /* also provides a place for the thread's entry function to return. */ /* If the thread returns, this function places the thread in a */ /* "COMPLETED" state. */ @@ -78,7 +78,7 @@ extern VOID _gcc_setup(TXM_MODULE_INSTANCE *); /* */ /* CALLS */ /* */ -/* _gcc_setup GNU global init function */ +/* _gcc_setup cstartup initialization */ /* thread_entry Thread's entry function */ /* tx_thread_resume Resume the module callback thread */ /* _txm_module_thread_system_suspend Module thread suspension routine */ @@ -91,7 +91,7 @@ extern VOID _gcc_setup(TXM_MODULE_INSTANCE *); /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ /* */ /**************************************************************************/ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_ENTRY_INFO *thread_info) @@ -106,7 +106,7 @@ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_EN execution. If not, simply skip the C startup code. */ if (thread_info -> txm_module_thread_entry_info_start_thread) { - /* Initialize the GNU C environment. */ + /* Initialize the C environment. */ _gcc_setup(thread_info -> txm_module_thread_entry_info_code_base_address); /* Save the entry info pointer, for later use. */ @@ -171,4 +171,3 @@ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_EN TX_SAFETY_CRITICAL_EXCEPTION(__FILE__, __LINE__, 0); #endif } - diff --git a/ports_module/cortex_m3/gnu/module_manager/src/tx_thread_context_restore.S b/ports_module/cortex_m3/gnu/module_manager/src/tx_thread_context_restore.S index e445e690..4b62c21c 100644 --- a/ports_module/cortex_m3/gnu/module_manager/src/tx_thread_context_restore.S +++ b/ports_module/cortex_m3/gnu/module_manager/src/tx_thread_context_restore.S @@ -31,8 +31,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_context_restore Cortex-Mx/GNU */ -/* 6.1.8 */ +/* _tx_thread_context_restore Cortex-M3/GNU */ +/* 6.1.7 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -62,7 +62,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ +/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ /* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) diff --git a/ports_module/cortex_m3/gnu/module_manager/src/tx_thread_context_save.S b/ports_module/cortex_m3/gnu/module_manager/src/tx_thread_context_save.S index e4f2778a..13283881 100644 --- a/ports_module/cortex_m3/gnu/module_manager/src/tx_thread_context_save.S +++ b/ports_module/cortex_m3/gnu/module_manager/src/tx_thread_context_save.S @@ -27,8 +27,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_context_save Cortex-Mx/GNU */ -/* 6.1.8 */ +/* _tx_thread_context_save Cortex-M3/GNU */ +/* 6.1.7 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -58,7 +58,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ +/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ /* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) diff --git a/ports_module/cortex_m3/gnu/module_manager/src/tx_thread_interrupt_control.S b/ports_module/cortex_m3/gnu/module_manager/src/tx_thread_interrupt_control.S index 99e14c06..309053a8 100644 --- a/ports_module/cortex_m3/gnu/module_manager/src/tx_thread_interrupt_control.S +++ b/ports_module/cortex_m3/gnu/module_manager/src/tx_thread_interrupt_control.S @@ -27,8 +27,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_interrupt_control Cortex-Mx/GNU */ -/* 6.1.8 */ +/* _tx_thread_interrupt_control Cortex-M3/GNU */ +/* 6.1.7 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -58,7 +58,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ +/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ /* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) diff --git a/ports_module/cortex_m3/gnu/module_manager/src/tx_thread_interrupt_disable.S b/ports_module/cortex_m3/gnu/module_manager/src/tx_thread_interrupt_disable.S new file mode 100644 index 00000000..7da1fe8a --- /dev/null +++ b/ports_module/cortex_m3/gnu/module_manager/src/tx_thread_interrupt_disable.S @@ -0,0 +1,79 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + .text 32 + .align 4 + .syntax unified +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_interrupt_disable Cortex-M3/GNU */ +/* 6.1.7 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is responsible for disabling interrupts and returning */ +/* the previous interrupt lockout posture. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* old_posture Old interrupt lockout posture */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ +/* */ +/**************************************************************************/ +// UINT _tx_thread_interrupt_disable(VOID) +// { + .global _tx_thread_interrupt_disable + .thumb_func +_tx_thread_interrupt_disable: + /* Return current interrupt lockout posture. */ +#ifdef TX_PORT_USE_BASEPRI + MRS r0, BASEPRI + LDR r1, =TX_PORT_BASEPRI + MSR BASEPRI, r1 +#else + MRS r0, PRIMASK + CPSID i +#endif + BX lr +// } diff --git a/ports_module/cortex_m3/gnu/module_manager/src/tx_thread_interrupt_restore.S b/ports_module/cortex_m3/gnu/module_manager/src/tx_thread_interrupt_restore.S new file mode 100644 index 00000000..136b56b7 --- /dev/null +++ b/ports_module/cortex_m3/gnu/module_manager/src/tx_thread_interrupt_restore.S @@ -0,0 +1,76 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + .text 32 + .align 4 + .syntax unified +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_interrupt_restore Cortex-M3/GNU */ +/* 6.1.7 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is responsible for restoring the previous */ +/* interrupt lockout posture. */ +/* */ +/* INPUT */ +/* */ +/* previous_posture Previous interrupt posture */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ +/* */ +/**************************************************************************/ +// VOID _tx_thread_interrupt_restore(UINT previous_posture) +// { + .global _tx_thread_interrupt_restore + .thumb_func +_tx_thread_interrupt_restore: + /* Restore previous interrupt lockout posture. */ +#ifdef TX_PORT_USE_BASEPRI + MSR BASEPRI, r0 +#else + MSR PRIMASK, r0 +#endif + BX lr +// } diff --git a/ports_module/cortex_m3/gnu/module_manager/src/tx_thread_schedule.S b/ports_module/cortex_m3/gnu/module_manager/src/tx_thread_schedule.S index c0aaaec9..02ef7522 100644 --- a/ports_module/cortex_m3/gnu/module_manager/src/tx_thread_schedule.S +++ b/ports_module/cortex_m3/gnu/module_manager/src/tx_thread_schedule.S @@ -39,8 +39,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_schedule Cortex-M3/MPU/GNU */ -/* 6.1 */ +/* _tx_thread_schedule Cortex-M3/GNU */ +/* 6.1.9 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -73,7 +73,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ /* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) @@ -92,8 +92,14 @@ _tx_thread_schedule: LDR r2, =_tx_thread_preempt_disable // Build address of preempt disable flag STR r0, [r2, #0] // Clear preempt disable flag - /* Enable memory fault registers. */ +#ifdef __ARM_PCS_VFP + /* Clear CONTROL.FPCA bit so VFP registers aren't unnecessarily stacked. */ + MRS r0, CONTROL // Pickup current CONTROL register + BIC r0, r0, #4 // Clear the FPCA bit + MSR CONTROL, r0 // Setup new CONTROL register +#endif + /* Enable memory fault registers. */ LDR r0, =0xE000ED24 // Build SHCSR address LDR r1, =0x70000 // Enable Usage, Bus, and MemManage faults STR r1, [r0] // @@ -185,6 +191,13 @@ UsageFault_Handler: // Bit 7 = 1 -> MMFAR is valid STRB r1, [r0] // Clear the MMFSR +#ifdef __ARM_PCS_VFP + LDR r0, =0xE000EF34 // Cleanup FPU context: Load FPCCR address + LDR r1, [r0] // Load FPCCR + BIC r1, r1, #1 // Clear the lazy preservation active bit + STR r1, [r0] // Store the value +#endif + BL _txm_module_manager_memory_fault_handler // Call memory manager fault handler #if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) @@ -245,6 +258,12 @@ __tx_ts_handler: STR r3, [r0] // Set _tx_thread_current_ptr to NULL MRS r12, PSP // Pickup PSP pointer (thread's stack pointer) STMDB r12!, {r4-r11} // Save its remaining registers +#ifdef __ARM_PCS_VFP + TST LR, #0x10 // Determine if the VFP extended frame is present + BNE _skip_vfp_save + VSTMDB r12!,{s16-s31} // Yes, save additional VFP registers +_skip_vfp_save: +#endif LDR r4, =_tx_timer_time_slice // Build address of time-slice variable STMDB r12!, {LR} // Save LR on the stack @@ -270,16 +289,42 @@ __tx_ts_new: CPSID i // Disable interrupts LDR r1, [r2] // Is there another thread ready to execute? - CBZ r1, __tx_ts_wait // No, skip to the wait processing + CBNZ r1, __tx_ts_restore // Yes, schedule it + + /* The following is the idle wait processing... in this case, no threads are ready for execution and the + system will simply be idle until an interrupt occurs that makes a thread ready. Note that interrupts + are disabled to allow use of WFI for waiting for a thread to arrive. */ + +__tx_ts_wait: + CPSID i // Disable interrupts + LDR r1, [r2] // Pickup the next thread to execute pointer + CBNZ r1, __tx_ts_ready // If non-NULL, a new thread is ready! +#ifdef TX_ENABLE_WFI + DSB // Ensure no outstanding memory transactions + WFI // Wait for interrupt + ISB // Ensure pipeline is flushed +#endif + CPSIE i // Enable interrupts + B __tx_ts_wait // Loop to continue waiting + + /* At this point, we have a new thread ready to go. Clear any newly pended PendSV - since we are + already in the handler! */ + +__tx_ts_ready: + MOV r7, #0x08000000 // Build clear PendSV value + MOV r8, #0xE000E000 // Build base NVIC address + STR r7, [r8, #0xD04] // Clear any PendSV + +__tx_ts_restore: - /* Yes, another thread is ready for else, make the current thread the new thread. */ + /* A thread is ready, make the current thread the new thread + and enable interrupts. */ STR r1, [r0] // Setup the current thread pointer to the new thread CPSIE i // Enable interrupts /* Increment the thread run count. */ -__tx_ts_restore: LDR r7, [r1, #4] // Pickup the current thread run count LDR r4, =_tx_timer_time_slice // Build address of time-slice variable LDR r5, [r1, #24] // Pickup thread's current time-slice @@ -318,15 +363,32 @@ __tx_ts_restore: // Use alias registers to quickly load MPU ADD r0, r0, #100 // Build address of MPU register start in thread control block +#ifdef TXM_MODULE_MANAGER_16_MPU + LDM r0!,{r2-r9} // Load MPU regions 0-3 + STM r1,{r2-r9} // Store MPU regions 0-3 + LDM r0!,{r2-r9} // Load MPU regions 4-7 + STM r1,{r2-r9} // Store MPU regions 4-7 + LDM r0!,{r2-r9} // Load MPU regions 8-11 + STM r1,{r2-r9} // Store MPU regions 8-11 + LDM r0,{r2-r9} // Load MPU regions 12-15 + STM r1,{r2-r9} // Store MPU regions 12-15 +#else LDM r0!,{r2-r9} // Load first four MPU regions STM r1,{r2-r9} // Store first four MPU regions LDM r0,{r2-r9} // Load second four MPU regions STM r1,{r2-r9} // Store second four MPU regions +#endif LDR r0, =0xE000ED94 // Build MPU control reg address MOV r1, #5 // Build enable value with background region enabled STR r1, [r0] // Enable MPU skip_mpu_setup: LDMIA r12!, {LR} // Pickup LR +#ifdef __ARM_PCS_VFP + TST LR, #0x10 // Determine if the VFP extended frame is present + BNE _skip_vfp_restore // If not, skip VFP restore + VLDMIA r12!, {s16-s31} // Yes, restore additional VFP registers +_skip_vfp_restore: +#endif LDMIA r12!, {r4-r11} // Recover thread's registers MSR PSP, r12 // Setup the thread's stack pointer @@ -334,51 +396,6 @@ skip_mpu_setup: BX lr // Return to thread! - /* The following is the idle wait processing... in this case, no threads are ready for execution and the - system will simply be idle until an interrupt occurs that makes a thread ready. Note that interrupts - are disabled to allow use of WFI for waiting for a thread to arrive. */ - -__tx_ts_wait: - CPSID i // Disable interrupts - LDR r1, [r2] // Pickup the next thread to execute pointer - STR r1, [r0] // Store it in the current pointer - CBNZ r1, __tx_ts_ready // If non-NULL, a new thread is ready! - -#ifdef TX_LOW_POWER - PUSH {r0-r3} - BL tx_low_power_enter // Possibly enter low power mode - POP {r0-r3} -#endif - -#ifdef TX_ENABLE_WFI - DSB // Ensure no outstanding memory transactions - WFI // Wait for interrupt - ISB // Ensure pipeline is flushed -#endif - -#ifdef TX_LOW_POWER - PUSH {r0-r3} - BL tx_low_power_exit // Exit low power mode - POP {r0-r3} -#endif - - CPSIE i // Enable interrupts - B __tx_ts_wait // Loop to continue waiting - - /* At this point, we have a new thread ready to go. Clear any newly pended PendSV - since we are - already in the handler! */ - -__tx_ts_ready: - MOV r7, #0x08000000 // Build clear PendSV value - MOV r8, #0xE000E000 // Build base NVIC address - STR r7, [r8, #0xD04] // Clear any PendSV - - /* Re-enable interrupts and restore new thread. */ - - CPSIE i // Enable interrupts - B __tx_ts_restore // Restore the thread -// } - /* SVC Handler. */ @@ -403,7 +420,6 @@ __tx_SVCallHandler: the kernel from a module thread with user mode selected. */ LDR r2, =_txm_module_priv // Load address of where we should have come from - // Subtract 1 because of THUMB mode. CMP r1, r2 // Did we come from user_mode_entry? IT NE // If no (not equal), then... BXNE lr // return from where we came. @@ -432,7 +448,16 @@ __tx_SVCallHandler: #endif MRS r3, PSP // Pickup thread stack pointer +#ifdef __ARM_PCS_VFP + TST lr, #0x10 // Test for extended module stack + ITT EQ + ORREQ r3, r3, #1 // If so, set LSB in thread stack pointer to indicate extended frame + ORREQ lr, lr, #0x10 // Set bit, return with standard frame +#endif STR r3, [r2, #0xB0] // Save thread stack pointer +#ifdef __ARM_PCS_VFP + BIC r3, #1 // Clear possibly OR'd bit +#endif /* Build kernel stack by copying thread stack two registers at a time */ ADD r3, r3, #32 // Start at bottom of hardware stack @@ -455,7 +480,6 @@ _tx_skip_kernel_stack_enter: _tx_thread_user_return: LDR r2, =_txm_module_user_mode_exit // Load address of where we should have come from - // Subtract 1 because of THUMB mode. CMP r1, r2 // Did we come from user_mode_exit? IT NE // If no (not equal), then... BXNE lr // return from where we came @@ -479,8 +503,38 @@ _tx_thread_user_return: STR r1, [r2, #16] // Set stack end STR r3, [r2, #20] // Set stack size #endif + +#ifdef __ARM_PCS_VFP + /* If lazy stacking is pending, check if it can be cleared. + if(LSPACT && tx_thread_module_stack_start < FPCAR && FPCAR < tx_thread_module_stack_end) + then clear LSPACT. */ + LDR r3, =0xE000EF34 // Address of FPCCR + LDR r3, [r3] // Load FPCCR + TST r3, #1 // Check if LSPACT is set + BEQ _tx_no_lazy_clear // if clear, move on + LDR r1, =0xE000EF38 // Address of FPCAR + LDR r1, [r1] // Load FPCAR + LDR r0, [r2, #0xA4] // Load kernel stack start + CMP r1, r0 // If FPCAR < start, move on + BLO _tx_no_lazy_clear + LDR r0, [r2, #0xA8] // Load kernel stack end + CMP r0, r1 // If end < FPCAR, move on + BLO _tx_no_lazy_clear + BIC r3, #1 // Clear LSPACT + LDR r1, =0xE000EF34 // Address of FPCCR + STR r3, [r1] // Save updated FPCCR +_tx_no_lazy_clear: +#endif + LDR r0, [r2, #0xB0] // Load the module thread stack pointer MRS r3, PSP // Pickup kernel stack pointer +#ifdef __ARM_PCS_VFP + TST r0, #1 // Is module stack extended? + ITTE NE // If so... + BICNE lr, #0x10 // Clear bit, return with extended frame + BICNE r0, #1 // Clear bit that indicates extended module frame + ORREQ lr, lr, #0x10 // Else set bit, return with standard frame +#endif /* Copy kernel hardware stack to module thread stack. */ LDM r3!, {r1-r2} @@ -534,3 +588,19 @@ _txm_module_user_mode_exit: NOP NOP // } + +#ifdef __ARM_PCS_VFP + + .global tx_thread_fpu_enable + .thumb_func +tx_thread_fpu_enable: + .global tx_thread_fpu_disable + .thumb_func +tx_thread_fpu_disable: + + /* Automatic VPF logic is supported, this function is present only for + backward compatibility purposes and therefore simply returns. */ + + BX LR // Return to caller + +#endif diff --git a/ports_module/cortex_m3/gnu/module_manager/src/tx_thread_stack_build.S b/ports_module/cortex_m3/gnu/module_manager/src/tx_thread_stack_build.S index d0246c13..e6a1da3f 100644 --- a/ports_module/cortex_m3/gnu/module_manager/src/tx_thread_stack_build.S +++ b/ports_module/cortex_m3/gnu/module_manager/src/tx_thread_stack_build.S @@ -27,8 +27,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_stack_build Cortex-Mx/GNU */ -/* 6.1.8 */ +/* _tx_thread_stack_build Cortex-M3/GNU */ +/* 6.1.7 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -60,7 +60,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ +/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ /* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) diff --git a/ports_module/cortex_m3/gnu/module_manager/src/tx_thread_system_return.S b/ports_module/cortex_m3/gnu/module_manager/src/tx_thread_system_return.S index 1f20e1a6..8a1f4a29 100644 --- a/ports_module/cortex_m3/gnu/module_manager/src/tx_thread_system_return.S +++ b/ports_module/cortex_m3/gnu/module_manager/src/tx_thread_system_return.S @@ -27,8 +27,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_system_return Cortex-Mx/GNU */ -/* 6.1.8 */ +/* _tx_thread_system_return Cortex-M3/GNU */ +/* 6.1.7 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -60,7 +60,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ +/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ /* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) diff --git a/ports_module/cortex_m3/gnu/module_manager/src/tx_timer_interrupt.S b/ports_module/cortex_m3/gnu/module_manager/src/tx_timer_interrupt.S index 9551a2b2..2edd6db1 100644 --- a/ports_module/cortex_m3/gnu/module_manager/src/tx_timer_interrupt.S +++ b/ports_module/cortex_m3/gnu/module_manager/src/tx_timer_interrupt.S @@ -37,8 +37,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_timer_interrupt Cortex-Mx/GNU */ -/* 6.1.8 */ +/* _tx_timer_interrupt Cortex-M3/GNU */ +/* 6.1.7 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -71,7 +71,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ +/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ /* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) diff --git a/ports_module/cortex_m3/gnu/module_manager/src/txm_module_manager_alignment_adjust.c b/ports_module/cortex_m3/gnu/module_manager/src/txm_module_manager_alignment_adjust.c index a4d86f6d..92e629a8 100644 --- a/ports_module/cortex_m3/gnu/module_manager/src/txm_module_manager_alignment_adjust.c +++ b/ports_module/cortex_m3/gnu/module_manager/src/txm_module_manager_alignment_adjust.c @@ -30,8 +30,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _txm_power_of_two_block_size Cortex-M3/MPU/GNU */ -/* 6.1 */ +/* _txm_power_of_two_block_size Cortex-M3 */ +/* 6.1.9 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -61,7 +61,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ /* */ /**************************************************************************/ ULONG _txm_power_of_two_block_size(ULONG size) @@ -93,8 +93,8 @@ ULONG _txm_power_of_two_block_size(ULONG size) /* */ /* FUNCTION RELEASE */ /* */ -/* _txm_module_manager_alignment_adjust Cortex-M3/MPU/GNU */ -/* 6.1 */ +/* _txm_module_manager_alignment_adjust Cortex-M3 */ +/* 6.1.9 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -128,7 +128,7 @@ ULONG _txm_power_of_two_block_size(ULONG size) /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ /* */ /**************************************************************************/ VOID _txm_module_manager_alignment_adjust(TXM_MODULE_PREAMBLE *module_preamble, @@ -137,6 +137,53 @@ VOID _txm_module_manager_alignment_adjust(TXM_MODULE_PREAMBLE *module_preamble, ULONG *data_size, ULONG *data_alignment) { +#ifdef TXM_MODULE_MANAGER_16_MPU +ULONG local_code_size; +ULONG local_code_alignment; +ULONG local_data_size; +ULONG local_data_alignment; +ULONG code_size_accum; +ULONG data_size_accum; + + /* Copy the input parameters into local variables for ease of use. */ + local_code_size = *code_size; + local_code_alignment = *code_alignment; + local_data_size = *data_size; + local_data_alignment = *data_alignment; + + /* Determine code block sizes. Minimize the alignment requirement. + There are 4 MPU code entries available. The following is how the code size + will be distributed: + 1. 1/4 of the largest power of two that is greater than or equal to code size. + 2. 1/4 of the largest power of two that is greater than or equal to code size. + 3. Largest power of 2 that fits in the remaining space. + 4. Smallest power of 2 that exceeds the remaining space, minimum 32. */ + local_code_alignment = _txm_power_of_two_block_size(local_code_size) >> 2; + code_size_accum = local_code_alignment + local_code_alignment; + code_size_accum = code_size_accum + (_txm_power_of_two_block_size(local_code_size - code_size_accum) >> 1); + code_size_accum = code_size_accum + _txm_power_of_two_block_size(local_code_size - code_size_accum); + local_code_size = code_size_accum; + + /* Determine data block sizes. Minimize the alignment requirement. + There are 4 MPU data entries available. The following is how the data size + will be distributed: + 1. 1/4 of the largest power of two that is greater than or equal to data size. + 2. 1/4 of the largest power of two that is greater than or equal to data size. + 3. Largest power of 2 that fits in the remaining space. + 4. Smallest power of 2 that exceeds the remaining space, minimum 32. */ + local_data_alignment = _txm_power_of_two_block_size(local_data_size) >> 2; + data_size_accum = local_data_alignment + local_data_alignment; + data_size_accum = data_size_accum + (_txm_power_of_two_block_size(local_data_size - data_size_accum) >> 1); + data_size_accum = data_size_accum + _txm_power_of_two_block_size(local_data_size - data_size_accum); + local_data_size = data_size_accum; + + /* Return all the information to the caller. */ + *code_size = local_code_size; + *code_alignment = local_code_alignment; + *data_size = local_data_size; + *data_alignment = local_data_alignment; + +#else ULONG local_code_size; ULONG local_code_alignment; @@ -396,4 +443,6 @@ ULONG data_size_accum; *code_alignment = local_code_alignment; *data_size = local_data_size; *data_alignment = local_data_alignment; + +#endif } diff --git a/ports_module/cortex_m3/gnu/module_manager/src/txm_module_manager_external_memory_enable.c b/ports_module/cortex_m3/gnu/module_manager/src/txm_module_manager_external_memory_enable.c index 22eca632..cb13e4a6 100644 --- a/ports_module/cortex_m3/gnu/module_manager/src/txm_module_manager_external_memory_enable.c +++ b/ports_module/cortex_m3/gnu/module_manager/src/txm_module_manager_external_memory_enable.c @@ -33,8 +33,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _txm_module_manager_external_memory_enable Cortex-M3/MPU/GNU */ -/* 6.1 */ +/* _txm_module_manager_external_memory_enable Cortex-M3 */ +/* 6.1.9 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -70,7 +70,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ /* */ /**************************************************************************/ UINT _txm_module_manager_external_memory_enable(TXM_MODULE_INSTANCE *module_instance, @@ -78,6 +78,117 @@ UINT _txm_module_manager_external_memory_enable(TXM_MODULE_INSTANCE *module_ins ULONG length, UINT attributes) { +#ifdef TXM_MODULE_MANAGER_16_MPU +ULONG block_size; +ULONG region_size; +ULONG srd_bits; +ULONG size_register; +ULONG address; +ULONG shared_index; +ULONG attributes_check = 0; + + /* Determine if the module manager has not been initialized yet. */ + if (_txm_module_manager_ready != TX_TRUE) + { + /* Module manager has not been initialized. */ + return(TX_NOT_AVAILABLE); + } + + /* Determine if the module is valid. */ + if (module_instance == TX_NULL) + { + /* Invalid module pointer. */ + return(TX_PTR_ERROR); + } + + /* Get module manager protection mutex. */ + _tx_mutex_get(&_txm_module_manager_mutex, TX_WAIT_FOREVER); + + /* Determine if the module instance is valid. */ + if (module_instance -> txm_module_instance_id != TXM_MODULE_ID) + { + /* Release the protection mutex. */ + _tx_mutex_put(&_txm_module_manager_mutex); + + /* Invalid module pointer. */ + return(TX_PTR_ERROR); + } + + /* Determine if the module instance is in the loaded state. */ + if (module_instance -> txm_module_instance_state != TXM_MODULE_LOADED) + { + /* Release the protection mutex. */ + _tx_mutex_put(&_txm_module_manager_mutex); + + /* Return error if the module is not ready. */ + return(TX_START_ERROR); + } + + /* Determine if there are shared memory entries available. */ + if(module_instance -> txm_module_instance_shared_memory_count >= TXM_MODULE_MPU_SHARED_ENTRIES) + { + /* Release the protection mutex. */ + _tx_mutex_put(&_txm_module_manager_mutex); + + /* No more entries available. */ + return(TX_NO_MEMORY); + } + + /* Start address and length must adhere to Cortex-M7 MPU. + The address must align with the block size. */ + + block_size = _txm_power_of_two_block_size(length); + address = (ULONG) start_address; + if(address != (address & ~(block_size - 1))) + { + /* Release the protection mutex. */ + _tx_mutex_put(&_txm_module_manager_mutex); + + /* Return alignment error. */ + return(TXM_MODULE_ALIGNMENT_ERROR); + } + + /* At this point, we have a valid address and block size. + Set up MPU registers. */ + + /* Pick up index into shared memory entries. */ + shared_index = TXM_MODULE_MPU_SHARED_INDEX + module_instance -> txm_module_instance_shared_memory_count; + + /* Save address register with address, MPU region, set Valid bit. */ + module_instance -> txm_module_instance_mpu_registers[shared_index].txm_module_mpu_region_address = address | shared_index | 0x10; + + /* Calculate the region size. */ + region_size = (_txm_module_manager_region_size_get(block_size) << 1); + + /* Calculate the subregion bits. */ + srd_bits = _txm_module_manager_calculate_srd_bits(block_size, length); + + /* Generate SRD, size, and enable attributes. */ + size_register = srd_bits | region_size | TXM_ENABLE_REGION | TXM_MODULE_MPU_SHARED_ACCESS_CONTROL; + + /* Check for optional write attribute. */ + if(attributes & TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE) + { + attributes_check = TXM_MODULE_MANAGER_ATTRIBUTE_WRITE_MPU_BIT; + } + + /* Save attribute-size register. */ + module_instance -> txm_module_instance_mpu_registers[shared_index].txm_module_mpu_region_attribute_size = attributes_check | size_register; + + /* Keep track of shared memory address and length in module instance. */ + module_instance -> txm_module_instance_shared_memory_address[module_instance -> txm_module_instance_shared_memory_count] = address; + module_instance -> txm_module_instance_shared_memory_length[module_instance -> txm_module_instance_shared_memory_count] = length; + + /* Increment counter. */ + module_instance -> txm_module_instance_shared_memory_count++; + + /* Release the protection mutex. */ + _tx_mutex_put(&_txm_module_manager_mutex); + + /* Return success. */ + return(TX_SUCCESS); + +#else ULONG block_size; ULONG region_size; @@ -179,4 +290,6 @@ TXM_MODULE_PREAMBLE *module_preamble; /* Return success. */ return(TX_SUCCESS); + +#endif } diff --git a/ports_module/cortex_m3/gnu/module_manager/src/txm_module_manager_memory_fault_handler.c b/ports_module/cortex_m3/gnu/module_manager/src/txm_module_manager_memory_fault_handler.c index 39db82f1..bcaa98aa 100644 --- a/ports_module/cortex_m3/gnu/module_manager/src/txm_module_manager_memory_fault_handler.c +++ b/ports_module/cortex_m3/gnu/module_manager/src/txm_module_manager_memory_fault_handler.c @@ -45,8 +45,8 @@ TXM_MODULE_MANAGER_FAULT_INFO /* */ /* FUNCTION RELEASE */ /* */ -/* _txm_module_manager_memory_fault_handler Cortex-M3/MPU/GNU */ -/* 6.1 */ +/* _txm_module_manager_memory_fault_handler Cortex-M3 */ +/* 6.1.9 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -76,7 +76,7 @@ TXM_MODULE_MANAGER_FAULT_INFO /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ /* */ /**************************************************************************/ VOID _txm_module_manager_memory_fault_handler(VOID) diff --git a/ports_module/cortex_m3/gnu/module_manager/src/txm_module_manager_memory_fault_notify.c b/ports_module/cortex_m3/gnu/module_manager/src/txm_module_manager_memory_fault_notify.c index 9af12b84..dac86312 100644 --- a/ports_module/cortex_m3/gnu/module_manager/src/txm_module_manager_memory_fault_notify.c +++ b/ports_module/cortex_m3/gnu/module_manager/src/txm_module_manager_memory_fault_notify.c @@ -38,8 +38,8 @@ extern VOID (*_txm_module_manager_fault_notify)(TX_THREAD *, TXM_MODULE_INSTA /* */ /* FUNCTION RELEASE */ /* */ -/* _txm_module_manager_memory_fault_notify Cortex-M3/MPU/GNU */ -/* 6.1 */ +/* _txm_module_manager_memory_fault_notify Cortex-M3 */ +/* 6.1.9 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -71,7 +71,7 @@ extern VOID (*_txm_module_manager_fault_notify)(TX_THREAD *, TXM_MODULE_INSTA /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ /* */ /**************************************************************************/ UINT _txm_module_manager_memory_fault_notify(VOID (*notify_function)(TX_THREAD *, TXM_MODULE_INSTANCE *)) diff --git a/ports_module/cortex_m3/gnu/module_manager/src/txm_module_manager_mm_register_setup.c b/ports_module/cortex_m3/gnu/module_manager/src/txm_module_manager_mm_register_setup.c index f302903c..48a14571 100644 --- a/ports_module/cortex_m3/gnu/module_manager/src/txm_module_manager_mm_register_setup.c +++ b/ports_module/cortex_m3/gnu/module_manager/src/txm_module_manager_mm_register_setup.c @@ -30,8 +30,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _txm_module_manager_region_size_get Cortex-M3/MPU/GNU */ -/* 6.1 */ +/* _txm_module_manager_region_size_get Cortex-M3 */ +/* 6.1.9 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -61,7 +61,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ /* */ /**************************************************************************/ ULONG _txm_module_manager_region_size_get(ULONG block_size) @@ -152,8 +152,8 @@ ULONG return_value; /* */ /* FUNCTION RELEASE */ /* */ -/* _txm_module_manager_calculate_srd_bits Cortex-M3/MPU/GNU */ -/* 6.1 */ +/* _txm_module_manager_calculate_srd_bits Cortex-M3 */ +/* 6.1.9 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -184,7 +184,7 @@ ULONG return_value; /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ /* */ /**************************************************************************/ ULONG _txm_module_manager_calculate_srd_bits(ULONG block_size, ULONG length) @@ -230,16 +230,48 @@ UINT srd_bit_index; /* */ /* FUNCTION RELEASE */ /* */ -/* _txm_module_manager_mm_register_setup Cortex-M3/MPU/GNU */ -/* 6.1 */ +/* _txm_module_manager_mm_register_setup Cortex-M3 */ +/* 6.1.9 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ /* */ /* DESCRIPTION */ /* */ -/* This function sets up the Cortex-M3 MPU register definitions based */ -/* on the module's memory characteristics. */ +/* This function sets up the MPU register definitions based on the */ +/* module's memory characteristics. */ +/* */ +/* Default MPU layout: */ +/* Entry Description */ +/* 0 Kernel mode entry */ +/* 1 Module code region */ +/* 2 Module code region */ +/* 3 Module code region */ +/* 4 Module code region */ +/* 5 Module data region */ +/* 6 Module data region */ +/* 7 Module data region */ +/* */ +/* If TXM_MODULE_MANAGER_16_MPU is defined, there are 16 MPU slots. */ +/* MPU layout for the Cortex-M7: */ +/* Entry Description */ +/* 0 Kernel mode entry */ +/* 1 Module code region */ +/* 2 Module code region */ +/* 3 Module code region */ +/* 4 Module code region */ +/* 5 Module data region */ +/* 6 Module data region */ +/* 7 Module data region */ +/* 8 Module data region */ +/* 9 Module shared memory region */ +/* 10 Module shared memory region */ +/* 11 Module shared memory region */ +/* 12 Unused region */ +/* 13 Unused region */ +/* 14 Unused region */ +/* 15 Unused region */ +/* */ /* */ /* INPUT */ /* */ @@ -261,11 +293,181 @@ UINT srd_bit_index; /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ /* */ /**************************************************************************/ VOID _txm_module_manager_mm_register_setup(TXM_MODULE_INSTANCE *module_instance) { +#ifdef TXM_MODULE_MANAGER_16_MPU + +ULONG code_address; +ULONG code_size; +ULONG data_address; +ULONG data_size; +ULONG start_stop_stack_size; +ULONG callback_stack_size; +ULONG block_size; +ULONG region_size; +ULONG srd_bits = 0; +UINT mpu_table_index; +UINT i; + + + /* Setup the first MPU region for kernel mode entry. */ + /* Set address register to user mode entry function address, which is guaranteed to be at least 32-byte aligned. + Mask address to proper range, region 0, set Valid bit. */ + module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MPU_KERNEL_ENTRY_INDEX].txm_module_mpu_region_address = ((ULONG) _txm_module_manager_user_mode_entry & 0xFFFFFFE0) | 0x10; + /* Set the attributes, size (32 bytes) and enable bit. */ + module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MPU_KERNEL_ENTRY_INDEX].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_CODE_ACCESS_CONTROL | (_txm_module_manager_region_size_get(32) << 1) | TXM_ENABLE_REGION; + /* End of kernel mode entry setup. */ + + /* Setup code protection. */ + + /* Initialize the MPU table index. */ + mpu_table_index = 1; + + /* Pickup code starting address and actual size. */ + code_address = (ULONG) module_instance -> txm_module_instance_code_start; + code_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_code_size; + + /* Determine code block sizes. Minimize the alignment requirement. + There are 4 MPU code entries available. The following is how the code size + will be distributed: + 1. 1/4 of the largest power of two that is greater than or equal to code size. + 2. 1/4 of the largest power of two that is greater than or equal to code size. + 3. Largest power of 2 that fits in the remaining space. + 4. Smallest power of 2 that exceeds the remaining space, minimum 32. */ + + /* Now loop through to setup MPU protection for the code area. */ + for (i = 0; i < TXM_MODULE_MPU_CODE_ENTRIES; i++) + { + /* First two MPU blocks are 1/4 of the largest power of two + that is greater than or equal to code size. */ + if (i < 2) + { + block_size = _txm_power_of_two_block_size(code_size) >> 2; + } + + /* Third MPU block is the largest power of 2 that fits in the remaining space. */ + else if (i == 2) + { + /* Subtract (block_size*2) from code_size to calculate remaining space. */ + code_size = code_size - (block_size << 1); + block_size = _txm_power_of_two_block_size(code_size) >> 1; + } + + /* Last MPU block is the smallest power of 2 that exceeds the remaining space, minimum 32. */ + else + { + /* Calculate remaining space. */ + code_size = code_size - block_size; + block_size = _txm_power_of_two_block_size(code_size); + srd_bits = _txm_module_manager_calculate_srd_bits(block_size, code_size); + } + + /* Calculate the region size information. */ + region_size = (_txm_module_manager_region_size_get(block_size) << 1); + + /* Build the base address register with address, MPU region, set Valid bit. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_address = (code_address & ~(block_size - 1)) | mpu_table_index | 0x10; + /* Build the attribute-size register with permissions, SRD, size, enable. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_CODE_ACCESS_CONTROL | srd_bits | region_size | TXM_ENABLE_REGION; + + /* Adjust the code address. */ + code_address = code_address + block_size; + + /* Increment MPU table index. */ + mpu_table_index++; + } + /* End of code protection. */ + + /* Setup data protection. */ + + /* Reset SRD bitfield. */ + srd_bits = 0; + + /* Pickup data starting address and actual size. */ + data_address = (ULONG) module_instance -> txm_module_instance_data_start; + + /* Adjust the size of the module elements to be aligned to the default alignment. We do this + so that when we partition the allocated memory, we can simply place these regions right beside + each other without having to align their pointers. Note this only works when they all have + the same alignment. */ + + data_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_data_size; + start_stop_stack_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_start_stop_stack_size; + callback_stack_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_callback_stack_size; + + data_size = ((data_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; + + start_stop_stack_size = ((start_stop_stack_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; + + callback_stack_size = ((callback_stack_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; + + /* Update the data size to include thread stacks. */ + data_size = data_size + start_stop_stack_size + callback_stack_size; + + /* Determine data block sizes. Minimize the alignment requirement. + There are 4 MPU data entries available. The following is how the data size + will be distributed: + 1. 1/4 of the largest power of two that is greater than or equal to data size. + 2. 1/4 of the largest power of two that is greater than or equal to data size. + 3. Largest power of 2 that fits in the remaining space. + 4. Smallest power of 2 that exceeds the remaining space, minimum 32. */ + + /* Now loop through to setup MPU protection for the data area. */ + for (i = 0; i < TXM_MODULE_MPU_DATA_ENTRIES; i++) + { + /* First two MPU blocks are 1/4 of the largest power of two + that is greater than or equal to data size. */ + if (i < 2) + { + block_size = _txm_power_of_two_block_size(data_size) >> 2; + } + + /* Third MPU block is the largest power of 2 that fits in the remaining space. */ + else if (i == 2) + { + /* Subtract (block_size*2) from data_size to calculate remaining space. */ + data_size = data_size - (block_size << 1); + block_size = _txm_power_of_two_block_size(data_size) >> 1; + } + + /* Last MPU block is the smallest power of 2 that exceeds the remaining space, minimum 32. */ + else + { + /* Calculate remaining space. */ + data_size = data_size - block_size; + block_size = _txm_power_of_two_block_size(data_size); + srd_bits = _txm_module_manager_calculate_srd_bits(block_size, data_size); + } + + /* Calculate the region size information. */ + region_size = (_txm_module_manager_region_size_get(block_size) << 1); + + /* Build the base address register with address, MPU region, set Valid bit. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_address = (data_address & ~(block_size - 1)) | mpu_table_index | 0x10; + /* Build the attribute-size register with permissions, SRD, size, enable. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_DATA_ACCESS_CONTROL | srd_bits | region_size | TXM_ENABLE_REGION; + + /* Adjust the data address. */ + data_address = data_address + block_size; + + /* Increment MPU table index. */ + mpu_table_index++; + } + + /* Setup MPU for the remaining regions. */ + while (mpu_table_index < TXM_MODULE_MPU_TOTAL_ENTRIES) + { + /* Build the base address register with address, MPU region, set Valid bit. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_address = mpu_table_index | 0x10; + + /* Increment MPU table index. */ + mpu_table_index++; + } + +#else ULONG code_address; ULONG code_size; @@ -382,7 +584,7 @@ UINT i; for (i = 0; i < TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1; i++) { /* Build the base address register. */ - base_address_register = code_address & ~(block_size - 1) | mpu_register | 0x10; + base_address_register = (code_address & ~(block_size - 1)) | mpu_register | 0x10; /* Check if SRD bits need to be set. */ if (code_size < block_size) @@ -509,4 +711,87 @@ UINT i; /* Increment the MPU register index. */ mpu_register++; } + +#endif +} + +#ifdef TXM_MODULE_MANAGER_16_MPU +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_inside_data_check Cortex-M3 */ +/* 6.1.9 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks if the specified object is inside shared */ +/* memory. */ +/* */ +/* INPUT */ +/* */ +/* module_instance Pointer to module instance */ +/* obj_ptr Pointer to the object */ +/* obj_size Size of the object */ +/* */ +/* OUTPUT */ +/* */ +/* Whether the object is inside the shared memory region. */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Module dispatch check functions */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ +/* */ +/**************************************************************************/ +UINT _txm_module_manager_inside_data_check(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE obj_ptr, UINT obj_size) +{ + +UINT shared_memory_index; +UINT num_shared_memory_mpu_entries; +ALIGN_TYPE shared_memory_address_start; +ALIGN_TYPE shared_memory_address_end; + + /* Check for overflow. */ + if ((obj_ptr) > ((obj_ptr) + (obj_size))) + { + return(TX_FALSE); + } + + /* Check if the object is inside the module data. */ + if ((obj_ptr >= (ALIGN_TYPE) module_instance -> txm_module_instance_data_start) && + ((obj_ptr + obj_size) <= ((ALIGN_TYPE) module_instance -> txm_module_instance_data_end + 1))) + { + return(TX_TRUE); + } + + /* Check if the object is inside the shared memory. */ + num_shared_memory_mpu_entries = module_instance -> txm_module_instance_shared_memory_count; + for (shared_memory_index = 0; shared_memory_index < num_shared_memory_mpu_entries; shared_memory_index++) + { + + shared_memory_address_start = (ALIGN_TYPE) module_instance -> txm_module_instance_shared_memory_address[shared_memory_index]; + shared_memory_address_end = shared_memory_address_start + module_instance -> txm_module_instance_shared_memory_length[shared_memory_index]; + + if ((obj_ptr >= (ALIGN_TYPE) shared_memory_address_start) && + ((obj_ptr + obj_size) <= (ALIGN_TYPE) shared_memory_address_end)) + { + return(TX_TRUE); + } + } + + return(TX_FALSE); } +#endif diff --git a/ports_module/cortex_m3/gnu/module_manager/src/txm_module_manager_thread_stack_build.s b/ports_module/cortex_m3/gnu/module_manager/src/txm_module_manager_thread_stack_build.s index d2d13132..3d38bf3d 100644 --- a/ports_module/cortex_m3/gnu/module_manager/src/txm_module_manager_thread_stack_build.s +++ b/ports_module/cortex_m3/gnu/module_manager/src/txm_module_manager_thread_stack_build.s @@ -27,8 +27,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _txm_module_manager_thread_stack_build Cortex-M3/MPU/GNU */ -/* 6.1 */ +/* _txm_module_manager_thread_stack_build Cortex-M3/GNU */ +/* 6.1.9 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -60,7 +60,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ /* */ /**************************************************************************/ // VOID _txm_module_manager_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(TX_THREAD *, TXM_MODULE_INSTANCE *)) diff --git a/ports_module/cortex_m3/iar/inc/tx_port.h b/ports_module/cortex_m3/iar/inc/tx_port.h index 83017f77..9353ac8e 100644 --- a/ports_module/cortex_m3/iar/inc/tx_port.h +++ b/ports_module/cortex_m3/iar/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h Cortex-M3/IAR */ -/* 6.1 */ +/* 6.1.9 */ /* */ /* AUTHOR */ /* */ @@ -47,7 +47,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ /* */ /**************************************************************************/ @@ -75,16 +75,17 @@ #include <yvals.h> #endif + /* Define ThreadX basic types for this port. */ #define VOID void typedef char CHAR; typedef unsigned char UCHAR; -typedef signed int INT; +typedef int INT; typedef unsigned int UINT; -typedef signed long LONG; +typedef long LONG; typedef unsigned long ULONG; -typedef signed short SHORT; +typedef short SHORT; typedef unsigned short USHORT; @@ -126,7 +127,7 @@ typedef unsigned short USHORT; For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock source constants would be: -#define TX_TRACE_TIME_SOURCE *((ULONG *) 0x0a800024UL) +#define TX_TRACE_TIME_SOURCE *((ULONG *) 0x0a800024) #define TX_TRACE_TIME_MASK 0x0000FFFFUL */ @@ -179,8 +180,8 @@ ULONG _tx_misra_time_stamp_get(VOID); for the multiple macros is so that backward compatibility can be maintained with existing ThreadX kernel awareness modules. */ -#define TX_THREAD_EXTENSION_0 -#define TX_THREAD_EXTENSION_1 +#define TX_THREAD_EXTENSION_0 +#define TX_THREAD_EXTENSION_1 #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT #define TX_THREAD_EXTENSION_2 VOID *tx_thread_module_instance_ptr; \ VOID *tx_thread_module_entry_info_ptr; \ @@ -218,17 +219,21 @@ ULONG _tx_misra_time_stamp_get(VOID); unsigned long long tx_thread_execution_time_last_start; #endif + /* Define the port extensions of the remaining ThreadX objects. */ #define TX_BLOCK_POOL_EXTENSION #define TX_BYTE_POOL_EXTENSION +#define TX_MUTEX_EXTENSION #define TX_EVENT_FLAGS_GROUP_EXTENSION VOID *tx_event_flags_group_module_instance; \ VOID (*tx_event_flags_group_set_module_notify)(struct TX_EVENT_FLAGS_GROUP_STRUCT *group_ptr); -#define TX_MUTEX_EXTENSION + #define TX_QUEUE_EXTENSION VOID *tx_queue_module_instance; \ VOID (*tx_queue_send_module_notify)(struct TX_QUEUE_STRUCT *queue_ptr); + #define TX_SEMAPHORE_EXTENSION VOID *tx_semaphore_module_instance; \ VOID (*tx_semaphore_put_module_notify)(struct TX_SEMAPHORE_STRUCT *semaphore_ptr); + #define TX_TIMER_EXTENSION VOID *tx_timer_module_instance; \ VOID (*tx_timer_module_expiration_function)(ULONG id); @@ -244,6 +249,7 @@ ULONG _tx_misra_time_stamp_get(VOID); /* Define the macros for processing extensions in tx_thread_create, tx_thread_delete, tx_thread_shell_entry, and tx_thread_terminate. */ + #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT #if (__VER__ < 8000000) #define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); @@ -264,8 +270,118 @@ void __iar_Initlocks(void); #define TX_THREAD_CREATE_EXTENSION(thread_ptr) #define TX_THREAD_DELETE_EXTENSION(thread_ptr) #endif + + +#ifdef __ARMVFP__ + +#ifdef TX_MISRA_ENABLE + +ULONG _tx_misra_control_get(void); +void _tx_misra_control_set(ULONG value); +ULONG _tx_misra_fpccr_get(void); +void _tx_misra_vfp_touch(void); + +#endif + +/* A completed thread falls into _thread_shell_entry and we can simply deactivate the FPU via CONTROL.FPCA + in order to ensure no lazy stacking will occur. */ + +#ifndef TX_MISRA_ENABLE + +#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) { \ + ULONG _tx_vfp_state; \ + _tx_vfp_state = __get_CONTROL(); \ + _tx_vfp_state = _tx_vfp_state & ~((ULONG) 0x4); \ + __set_CONTROL(_tx_vfp_state); \ + } +#else + +#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) { \ + ULONG _tx_vfp_state; \ + _tx_vfp_state = _tx_misra_control_get(); \ + _tx_vfp_state = _tx_vfp_state & ~((ULONG) 0x4); \ + _tx_misra_control_set(_tx_vfp_state); \ + } + +#endif + +/* A thread can be terminated by another thread, so we first check if it's self-terminating and not in an ISR. + If so, deactivate the FPU via CONTROL.FPCA. Otherwise we are in an interrupt or another thread is terminating + this one, so if the FPCCR.LSPACT bit is set, we need to save the CONTROL.FPCA state, touch the FPU to flush + the lazy FPU save, then restore the CONTROL.FPCA state. */ + +#ifndef TX_MISRA_ENABLE + +#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) { \ + ULONG _tx_system_state; \ + _tx_system_state = TX_THREAD_GET_SYSTEM_STATE(); \ + if ((_tx_system_state == ((ULONG) 0)) && ((thread_ptr) == _tx_thread_current_ptr)) \ + { \ + ULONG _tx_vfp_state; \ + _tx_vfp_state = __get_CONTROL(); \ + _tx_vfp_state = _tx_vfp_state & ~((ULONG) 0x4); \ + __set_CONTROL(_tx_vfp_state); \ + } \ + else \ + { \ + ULONG _tx_fpccr; \ + _tx_fpccr = *((ULONG *) 0xE000EF34); \ + _tx_fpccr = _tx_fpccr & ((ULONG) 0x01); \ + if (_tx_fpccr == ((ULONG) 0x01)) \ + { \ + ULONG _tx_vfp_state; \ + _tx_vfp_state = __get_CONTROL(); \ + _tx_vfp_state = _tx_vfp_state & ((ULONG) 0x4); \ + __asm volatile ("vmov.f32 s0, s0"); \ + if (_tx_vfp_state == ((ULONG) 0)) \ + { \ + _tx_vfp_state = __get_CONTROL(); \ + _tx_vfp_state = _tx_vfp_state & ~((ULONG) 0x4); \ + __set_CONTROL(_tx_vfp_state); \ + } \ + } \ + } \ + } +#else + +#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) { \ + ULONG _tx_system_state; \ + _tx_system_state = TX_THREAD_GET_SYSTEM_STATE(); \ + if ((_tx_system_state == ((ULONG) 0)) && ((thread_ptr) == _tx_thread_current_ptr)) \ + { \ + ULONG _tx_vfp_state; \ + _tx_vfp_state = _tx_misra_control_get(); \ + _tx_vfp_state = _tx_vfp_state & ~((ULONG) 0x4); \ + _tx_misra_control_set(_tx_vfp_state); \ + } \ + else \ + { \ + ULONG _tx_fpccr; \ + _tx_fpccr = _tx_misra_fpccr_get(); \ + _tx_fpccr = _tx_fpccr & ((ULONG) 0x01); \ + if (_tx_fpccr == ((ULONG) 0x01)) \ + { \ + ULONG _tx_vfp_state; \ + _tx_vfp_state = _tx_misra_control_get(); \ + _tx_vfp_state = _tx_vfp_state & ((ULONG) 0x4); \ + _tx_misra_vfp_touch(); \ + if (_tx_vfp_state == ((ULONG) 0)) \ + { \ + _tx_vfp_state = _tx_misra_control_get(); \ + _tx_vfp_state = _tx_vfp_state & ~((ULONG) 0x4); \ + _tx_misra_control_set(_tx_vfp_state); \ + } \ + } \ + } \ + } +#endif + +#else + #define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) -#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) +#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) + +#endif /* Define the ThreadX object creation extensions for the remaining objects. */ @@ -323,11 +439,11 @@ ULONG _tx_misra_ipsr_get(VOID); lowest bit set. */ #ifndef TX_DISABLE_INLINE - + #define TX_LOWEST_SET_BIT_CALCULATE(m, b) (b) = (UINT)__CLZ(__RBIT((m))); #endif - + /* Define ThreadX interrupt lockout and restore macros for protection on access of critical kernel information. The restore interrupt macro must @@ -372,6 +488,13 @@ __istate_t interrupt_save; #endif +/* Define FPU extension for the Cortex-M7. Each is assumed to be called in the context of the executing + thread. These are no longer needed, but are preserved for backward compatibility only. */ + +void tx_thread_fpu_enable(void); +void tx_thread_fpu_disable(void); + + /* Define the interrupt lockout macros for each ThreadX object. */ #define TX_BLOCK_POOL_DISABLE TX_DISABLE @@ -386,7 +509,7 @@ __istate_t interrupt_save; #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M3/IAR Version 6.1 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M3/IAR Version 6.x *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; @@ -397,8 +520,3 @@ extern CHAR _tx_version_id[]; #endif - - - - - diff --git a/ports_module/cortex_m3/iar/inc/txm_module_port.h b/ports_module/cortex_m3/iar/inc/txm_module_port.h index a2d7354b..8e69b96b 100644 --- a/ports_module/cortex_m3/iar/inc/txm_module_port.h +++ b/ports_module/cortex_m3/iar/inc/txm_module_port.h @@ -25,8 +25,8 @@ /* */ /* APPLICATION INTERFACE DEFINITION RELEASE */ /* */ -/* txm_module_port.h Cortex-M3/MPU/IAR */ -/* 6.1.6 */ +/* txm_module_port.h Cortex-M3/IAR */ +/* 6.1.9 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -40,10 +40,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 04-02-2021 Scott Larson Modified comment(s) and */ -/* added check for overflow, */ -/* resulting in version 6.1.6 */ +/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ /* */ /**************************************************************************/ @@ -95,16 +92,26 @@ The following extensions must also be defined in tx_port.h: VOID (*tx_timer_module_expiration_function)(ULONG id); */ - -/* Size of module heap. */ -#define TXM_MODULE_HEAP_SIZE 512 - - /* Define the kernel stack size for a module thread. */ #ifndef TXM_MODULE_KERNEL_STACK_SIZE #define TXM_MODULE_KERNEL_STACK_SIZE 768 #endif +/* For the following 3 access control settings, change TEX and C, B, S (bits 21 through 16 of MPU_RASR) + * to reflect your system memory attributes (cache, shareable, memory type). */ +/* Code region access control: privileged read-only, outer & inner write-back, normal memory, shareable. */ +#ifndef TXM_MODULE_MPU_CODE_ACCESS_CONTROL +#define TXM_MODULE_MPU_CODE_ACCESS_CONTROL 0x06070000 +#endif +/* Data region access control: execute never, read/write, outer & inner write-back, normal memory, shareable. */ +#ifndef TXM_MODULE_MPU_DATA_ACCESS_CONTROL +#define TXM_MODULE_MPU_DATA_ACCESS_CONTROL 0x13070000 +#endif +/* Shared region access control: execute never, read-only, outer & inner write-back, normal memory, shareable. */ +#ifndef TXM_MODULE_MPU_SHARED_ACCESS_CONTROL +#define TXM_MODULE_MPU_SHARED_ACCESS_CONTROL 0x12070000 +#endif + /* Define constants specific to the tools the module can be built with for this particular modules port. */ #define TXM_MODULE_IAR_COMPILER 0x00000000 @@ -159,8 +166,43 @@ The following extensions must also be defined in tx_port.h: #define INLINE_DECLARE inline +#ifdef TXM_MODULE_MANAGER_16_MPU + /* Define the number of MPU entries assigned to the code and data sections. - On Cortex-M3 parts, there are 8 total entries. ThreadX uses one for access + On some Cortex-M7 parts, there are 16 total entries. ThreadX uses one for access + to the kernel entry function, thus 15 remain for code and data protection. */ +#define TXM_MODULE_MPU_TOTAL_ENTRIES 16 +#define TXM_MODULE_MPU_CODE_ENTRIES 4 +#define TXM_MODULE_MPU_DATA_ENTRIES 4 +#define TXM_MODULE_MPU_SHARED_ENTRIES 3 + +#define TXM_MODULE_MPU_KERNEL_ENTRY_INDEX 0 +#define TXM_MODULE_MPU_SHARED_INDEX 9 + +#define TXM_ENABLE_REGION 0x01 + +/* There are 2 registers to set up each MPU region: MPU_RBAR, MPU_RASR. */ +typedef struct TXM_MODULE_MPU_INFO_STRUCT +{ + ULONG txm_module_mpu_region_address; + ULONG txm_module_mpu_region_attribute_size; +} TXM_MODULE_MPU_INFO; +/* Shared memory region attributes. */ +#define TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE 1 +#define TXM_MODULE_MANAGER_ATTRIBUTE_WRITE_MPU_BIT 0x01000000 + +/* Define the port-extensions to the module manager instance structure. */ + +#define TXM_MODULE_MANAGER_PORT_EXTENSION \ + TXM_MODULE_MPU_INFO txm_module_instance_mpu_registers[TXM_MODULE_MPU_TOTAL_ENTRIES]; \ + ULONG txm_module_instance_shared_memory_count; \ + ULONG txm_module_instance_shared_memory_address[TXM_MODULE_MPU_SHARED_ENTRIES]; \ + ULONG txm_module_instance_shared_memory_length[TXM_MODULE_MPU_SHARED_ENTRIES]; + +#else /* TXM_MODULE_MANAGER_16_MPU is not defined */ + +/* Define the number of MPU entries assigned to the code and data sections. + On Cortex-M3, M4, and some M7 parts, there are 8 total entries. ThreadX uses one for access to the kernel entry function, thus 7 remain for code and data protection. */ #define TXM_MODULE_MANAGER_CODE_MPU_ENTRIES 4 #define TXM_MODULE_MANAGER_DATA_MPU_ENTRIES 3 @@ -178,6 +220,7 @@ The following extensions must also be defined in tx_port.h: ULONG txm_module_instance_shared_memory_address; \ ULONG txm_module_instance_shared_memory_length; +#endif /* TXM_MODULE_MANAGER_16_MPU */ /* Define the memory fault information structure that is populated when a memory fault occurs. */ @@ -300,6 +343,10 @@ typedef struct TXM_MODULE_MANAGER_MEMORY_FAULT_INFO_STRUCT /* Define the macros to perform port-specific checks when passing pointers to the kernel. */ /* Define macro to make sure object is inside the module's data. */ +#ifdef TXM_MODULE_MANAGER_16_MPU +#define TXM_MODULE_MANAGER_CHECK_INSIDE_DATA(module_instance, obj_ptr, obj_size) \ + _txm_module_manager_inside_data_check(module_instance, obj_ptr, obj_size) +#else #define TXM_MODULE_MANAGER_CHECK_INSIDE_DATA(module_instance, obj_ptr, obj_size) \ /* Check for overflow. */ \ (((obj_ptr) < ((obj_ptr) + (obj_size))) && \ @@ -309,7 +356,7 @@ typedef struct TXM_MODULE_MANAGER_MEMORY_FAULT_INFO_STRUCT /* Check if it's inside shared memory. */ \ (((obj_ptr) >= (ALIGN_TYPE) module_instance -> txm_module_instance_shared_memory_address) && \ (((obj_ptr) + (obj_size)) <= (ALIGN_TYPE) (module_instance -> txm_module_instance_shared_memory_address + module_instance -> txm_module_instance_shared_memory_length))))) - +#endif /* Define some internal prototypes to this module port. */ @@ -325,10 +372,11 @@ UINT _txm_module_manager_memory_fault_notify(VOID (*notify_function)(TX_THREAD VOID _txm_module_manager_mm_register_setup(TXM_MODULE_INSTANCE *module_instance); \ ULONG _txm_power_of_two_block_size(ULONG size); \ ULONG _txm_module_manager_calculate_srd_bits(ULONG block_size, ULONG length); \ -ULONG _txm_module_manager_region_size_get(ULONG block_size); +ULONG _txm_module_manager_region_size_get(ULONG block_size); \ +UINT _txm_module_manager_inside_data_check(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE obj_ptr, UINT obj_size); #define TXM_MODULE_MANAGER_VERSION_ID \ -CHAR _txm_module_manager_version_id[] = \ - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-M3/MPU/IAR Version 6.1.8 *"; +CHAR _txm_module_manager_version_id[] = \ + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-M3/IAR Version 6.x *"; #endif diff --git a/ports_module/cortex_m3/iar/module_lib/src/txm_module_thread_shell_entry.c b/ports_module/cortex_m3/iar/module_lib/src/txm_module_thread_shell_entry.c index 40355375..d2b39756 100644 --- a/ports_module/cortex_m3/iar/module_lib/src/txm_module_thread_shell_entry.c +++ b/ports_module/cortex_m3/iar/module_lib/src/txm_module_thread_shell_entry.c @@ -44,7 +44,7 @@ TXM_MODULE_THREAD_ENTRY_INFO *_txm_module_entry_info; ULONG (*_txm_module_kernel_call_dispatcher)(ULONG kernel_request, ULONG param_1, ULONG param_2, ULONG param3); -/* Define the IAR startup code that clears the uninitialized global data and sets up the +/* Define the startup code that clears the uninitialized global data and sets up the preset global variables. */ extern VOID __iar_data_init3(VOID); @@ -54,15 +54,15 @@ extern VOID __iar_data_init3(VOID); /* */ /* FUNCTION RELEASE */ /* */ -/* _txm_module_thread_shell_entry Cortex-M3/MPU/IAR */ -/* 6.1 */ +/* _txm_module_thread_shell_entry Cortex-M3/IAR */ +/* 6.1.9 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ /* */ /* DESCRIPTION */ /* */ -/* This function calls the specified entry function of the thread. It */ +/* This function calls the specified entry function of the thread. It */ /* also provides a place for the thread's entry function to return. */ /* If the thread returns, this function places the thread in a */ /* "COMPLETED" state. */ @@ -78,7 +78,7 @@ extern VOID __iar_data_init3(VOID); /* */ /* CALLS */ /* */ -/* __iar_data_init3 IAR global initialization function*/ +/* __iar_data_init3 cstartup initialization */ /* thread_entry Thread's entry function */ /* tx_thread_resume Resume the module callback thread */ /* _txm_module_thread_system_suspend Module thread suspension routine */ @@ -91,7 +91,7 @@ extern VOID __iar_data_init3(VOID); /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ /* */ /**************************************************************************/ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_ENTRY_INFO *thread_info) @@ -106,7 +106,7 @@ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_EN execution. If not, simply skip the C startup code. */ if (thread_info -> txm_module_thread_entry_info_start_thread) { - /* Initialize the IAR C environment. */ + /* Initialize the C environment. */ __iar_data_init3(); /* Save the entry info pointer, for later use. */ @@ -171,4 +171,3 @@ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_EN TX_SAFETY_CRITICAL_EXCEPTION(__FILE__, __LINE__, 0); #endif } - diff --git a/ports_module/cortex_m3/iar/module_manager/src/tx_thread_context_restore.s b/ports_module/cortex_m3/iar/module_manager/src/tx_thread_context_restore.s index 0a188df9..992585eb 100644 --- a/ports_module/cortex_m3/iar/module_manager/src/tx_thread_context_restore.s +++ b/ports_module/cortex_m3/iar/module_manager/src/tx_thread_context_restore.s @@ -27,8 +27,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_context_restore Cortex-Mx/IAR */ -/* 6.1.8 */ +/* _tx_thread_context_restore Cortex-M3/IAR */ +/* 6.1.7 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -58,7 +58,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ +/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ /* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) diff --git a/ports_module/cortex_m3/iar/module_manager/src/tx_thread_context_save.s b/ports_module/cortex_m3/iar/module_manager/src/tx_thread_context_save.s index e71ae496..cae664e0 100644 --- a/ports_module/cortex_m3/iar/module_manager/src/tx_thread_context_save.s +++ b/ports_module/cortex_m3/iar/module_manager/src/tx_thread_context_save.s @@ -27,8 +27,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_context_save Cortex-Mx/IAR */ -/* 6.1.8 */ +/* _tx_thread_context_save Cortex-M3/IAR */ +/* 6.1.7 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -58,7 +58,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ +/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ /* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) diff --git a/ports_module/cortex_m3/iar/module_manager/src/tx_thread_interrupt_control.s b/ports_module/cortex_m3/iar/module_manager/src/tx_thread_interrupt_control.s index c0d9d095..8886a66b 100644 --- a/ports_module/cortex_m3/iar/module_manager/src/tx_thread_interrupt_control.s +++ b/ports_module/cortex_m3/iar/module_manager/src/tx_thread_interrupt_control.s @@ -26,8 +26,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_interrupt_control Cortex-Mx/IAR */ -/* 6.1.8 */ +/* _tx_thread_interrupt_control Cortex-M3/IAR */ +/* 6.1.7 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -57,7 +57,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ +/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ /* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) diff --git a/ports_module/cortex_m3/iar/module_manager/src/tx_thread_interrupt_disable.s b/ports_module/cortex_m3/iar/module_manager/src/tx_thread_interrupt_disable.s index 86fcf188..d27465a3 100644 --- a/ports_module/cortex_m3/iar/module_manager/src/tx_thread_interrupt_disable.s +++ b/ports_module/cortex_m3/iar/module_manager/src/tx_thread_interrupt_disable.s @@ -26,8 +26,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_interrupt_disable Cortex-Mx/IAR */ -/* 6.1.8 */ +/* _tx_thread_interrupt_disable Cortex-M3/IAR */ +/* 6.1.7 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -57,7 +57,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ +/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ /* */ /**************************************************************************/ // UINT _tx_thread_interrupt_disable(VOID) diff --git a/ports_module/cortex_m3/iar/module_manager/src/tx_thread_interrupt_restore.s b/ports_module/cortex_m3/iar/module_manager/src/tx_thread_interrupt_restore.s index f9603de1..9f4525f0 100644 --- a/ports_module/cortex_m3/iar/module_manager/src/tx_thread_interrupt_restore.s +++ b/ports_module/cortex_m3/iar/module_manager/src/tx_thread_interrupt_restore.s @@ -26,8 +26,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_interrupt_restore Cortex-Mx/IAR */ -/* 6.1.8 */ +/* _tx_thread_interrupt_restore Cortex-M3/IAR */ +/* 6.1.7 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -57,7 +57,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ +/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ /* */ /**************************************************************************/ // VOID _tx_thread_interrupt_restore(UINT previous_posture) diff --git a/ports_module/cortex_m3/iar/module_manager/src/tx_thread_schedule.s b/ports_module/cortex_m3/iar/module_manager/src/tx_thread_schedule.s index ec87d06e..d6bd477c 100644 --- a/ports_module/cortex_m3/iar/module_manager/src/tx_thread_schedule.s +++ b/ports_module/cortex_m3/iar/module_manager/src/tx_thread_schedule.s @@ -35,8 +35,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_schedule Cortex-M3/MPU/IAR */ -/* 6.1 */ +/* _tx_thread_schedule Cortex-M3/IAR */ +/* 6.1.9 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -69,7 +69,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ /* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) @@ -87,8 +87,14 @@ _tx_thread_schedule: LDR r2, =_tx_thread_preempt_disable // Build address of preempt disable flag STR r0, [r2, #0] // Clear preempt disable flag - /* Enable memory fault registers. */ +#ifdef __ARMVFP__ + /* Clear CONTROL.FPCA bit so VFP registers aren't unnecessarily stacked. */ + MRS r0, CONTROL // Pickup current CONTROL register + BIC r0, r0, #4 // Clear the FPCA bit + MSR CONTROL, r0 // Setup new CONTROL register +#endif + /* Enable memory fault registers. */ LDR r0, =0xE000ED24 // Build SHCSR address LDR r1, =0x70000 // Enable Usage, Bus, and MemManage faults STR r1, [r0] // @@ -178,6 +184,13 @@ UsageFault_Handler: // Bit 7 = 1 -> MMFAR is valid STRB r1, [r0] // Clear the MMFSR +#ifdef __ARMVFP__ + LDR r0, =0xE000EF34 // Cleanup FPU context: Load FPCCR address + LDR r1, [r0] // Load FPCCR + BIC r1, r1, #1 // Clear the lazy preservation active bit + STR r1, [r0] // Store the value +#endif + BL _txm_module_manager_memory_fault_handler // Call memory manager fault handler #if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) @@ -235,6 +248,12 @@ __tx_ts_handler: STR r3, [r0] // Set _tx_thread_current_ptr to NULL MRS r12, PSP // Pickup PSP pointer (thread's stack pointer) STMDB r12!, {r4-r11} // Save its remaining registers +#ifdef __ARMVFP__ + TST LR, #0x10 // Determine if the VFP extended frame is present + BNE _skip_vfp_save + VSTMDB r12!,{s16-s31} // Yes, save additional VFP registers +_skip_vfp_save: +#endif LDR r4, =_tx_timer_time_slice // Build address of time-slice variable STMDB r12!, {LR} // Save LR on the stack @@ -260,16 +279,42 @@ __tx_ts_new: CPSID i // Disable interrupts LDR r1, [r2] // Is there another thread ready to execute? - CBZ r1, __tx_ts_wait // No, skip to the wait processing + CBNZ r1, __tx_ts_restore // Yes, schedule it + + /* The following is the idle wait processing... in this case, no threads are ready for execution and the + system will simply be idle until an interrupt occurs that makes a thread ready. Note that interrupts + are disabled to allow use of WFI for waiting for a thread to arrive. */ + +__tx_ts_wait: + CPSID i // Disable interrupts + LDR r1, [r2] // Pickup the next thread to execute pointer + CBNZ r1, __tx_ts_ready // If non-NULL, a new thread is ready! +#ifdef TX_ENABLE_WFI + DSB // Ensure no outstanding memory transactions + WFI // Wait for interrupt + ISB // Ensure pipeline is flushed +#endif + CPSIE i // Enable interrupts + B __tx_ts_wait // Loop to continue waiting - /* Yes, another thread is ready for else, make the current thread the new thread. */ + /* At this point, we have a new thread ready to go. Clear any newly pended PendSV - since we are + already in the handler! */ + +__tx_ts_ready: + MOV r7, #0x08000000 // Build clear PendSV value + MOV r8, #0xE000E000 // Build base NVIC address + STR r7, [r8, #0xD04] // Clear any PendSV + +__tx_ts_restore: + + /* A thread is ready, make the current thread the new thread + and enable interrupts. */ STR r1, [r0] // Setup the current thread pointer to the new thread CPSIE i // Enable interrupts /* Increment the thread run count. */ -__tx_ts_restore: LDR r7, [r1, #4] // Pickup the current thread run count LDR r4, =_tx_timer_time_slice // Build address of time-slice variable LDR r5, [r1, #24] // Pickup thread's current time-slice @@ -308,15 +353,32 @@ __tx_ts_restore: // Use alias registers to quickly load MPU ADD r0, r0, #100 // Build address of MPU register start in thread control block +#ifdef TXM_MODULE_MANAGER_16_MPU + LDM r0!,{r2-r9} // Load MPU regions 0-3 + STM r1,{r2-r9} // Store MPU regions 0-3 + LDM r0!,{r2-r9} // Load MPU regions 4-7 + STM r1,{r2-r9} // Store MPU regions 4-7 + LDM r0!,{r2-r9} // Load MPU regions 8-11 + STM r1,{r2-r9} // Store MPU regions 8-11 + LDM r0,{r2-r9} // Load MPU regions 12-15 + STM r1,{r2-r9} // Store MPU regions 12-15 +#else LDM r0!,{r2-r9} // Load first four MPU regions STM r1,{r2-r9} // Store first four MPU regions LDM r0,{r2-r9} // Load second four MPU regions STM r1,{r2-r9} // Store second four MPU regions +#endif LDR r0, =0xE000ED94 // Build MPU control reg address MOV r1, #5 // Build enable value with background region enabled STR r1, [r0] // Enable MPU skip_mpu_setup: LDMIA r12!, {LR} // Pickup LR +#ifdef __ARMVFP__ + TST LR, #0x10 // Determine if the VFP extended frame is present + BNE _skip_vfp_restore // If not, skip VFP restore + VLDMIA r12!, {s16-s31} // Yes, restore additional VFP registers +_skip_vfp_restore: +#endif LDMIA r12!, {r4-r11} // Recover thread's registers MSR PSP, r12 // Setup the thread's stack pointer @@ -324,51 +386,6 @@ skip_mpu_setup: BX lr // Return to thread! - /* The following is the idle wait processing... in this case, no threads are ready for execution and the - system will simply be idle until an interrupt occurs that makes a thread ready. Note that interrupts - are disabled to allow use of WFI for waiting for a thread to arrive. */ - -__tx_ts_wait: - CPSID i // Disable interrupts - LDR r1, [r2] // Pickup the next thread to execute pointer - STR r1, [r0] // Store it in the current pointer - CBNZ r1, __tx_ts_ready // If non-NULL, a new thread is ready! - -#ifdef TX_LOW_POWER - PUSH {r0-r3} - BL tx_low_power_enter // Possibly enter low power mode - POP {r0-r3} -#endif - -#ifdef TX_ENABLE_WFI - DSB // Ensure no outstanding memory transactions - WFI // Wait for interrupt - ISB // Ensure pipeline is flushed -#endif - -#ifdef TX_LOW_POWER - PUSH {r0-r3} - BL tx_low_power_exit // Exit low power mode - POP {r0-r3} -#endif - - CPSIE i // Enable interrupts - B __tx_ts_wait // Loop to continue waiting - - /* At this point, we have a new thread ready to go. Clear any newly pended PendSV - since we are - already in the handler! */ - -__tx_ts_ready: - MOV r7, #0x08000000 // Build clear PendSV value - MOV r8, #0xE000E000 // Build base NVIC address - STR r7, [r8, #0xD04] // Clear any PendSV - - /* Re-enable interrupts and restore new thread. */ - - CPSIE i // Enable interrupts - B __tx_ts_restore // Restore the thread -// } - /* SVC Handler. */ @@ -419,7 +436,16 @@ __tx_SVCallHandler: #endif MRS r3, PSP // Pickup thread stack pointer +#ifdef __ARMVFP__ + TST lr, #0x10 // Test for extended module stack + ITT EQ + ORREQ r3, r3, #1 // If so, set LSB in thread stack pointer to indicate extended frame + ORREQ lr, lr, #0x10 // Set bit, return with standard frame +#endif STR r3, [r2, #0xB0] // Save thread stack pointer +#ifdef __ARMVFP__ + BIC r3, #1 // Clear possibly OR'd bit +#endif /* Build kernel stack by copying thread stack two registers at a time */ ADD r3, r3, #32 // Start at bottom of hardware stack @@ -466,8 +492,38 @@ _tx_thread_user_return: STR r1, [r2, #16] // Set stack end STR r3, [r2, #20] // Set stack size #endif + +#ifdef __ARMVFP__ + /* If lazy stacking is pending, check if it can be cleared. + if(LSPACT && tx_thread_module_stack_start < FPCAR && FPCAR < tx_thread_module_stack_end) + then clear LSPACT. */ + LDR r3, =0xE000EF34 // Address of FPCCR + LDR r3, [r3] // Load FPCCR + TST r3, #1 // Check if LSPACT is set + BEQ _tx_no_lazy_clear // if clear, move on + LDR r1, =0xE000EF38 // Address of FPCAR + LDR r1, [r1] // Load FPCAR + LDR r0, [r2, #0xA4] // Load kernel stack start + CMP r1, r0 // If FPCAR < start, move on + BLO _tx_no_lazy_clear + LDR r0, [r2, #0xA8] // Load kernel stack end + CMP r0, r1 // If end < FPCAR, move on + BLO _tx_no_lazy_clear + BIC r3, #1 // Clear LSPACT + LDR r1, =0xE000EF34 // Address of FPCCR + STR r3, [r1] // Save updated FPCCR +_tx_no_lazy_clear: +#endif + LDR r0, [r2, #0xB0] // Load the module thread stack pointer MRS r3, PSP // Pickup kernel stack pointer +#ifdef __ARMVFP__ + TST r0, #1 // Is module stack extended? + ITTE NE // If so... + BICNE lr, #0x10 // Clear bit, return with extended frame + BICNE r0, #1 // Clear bit that indicates extended module frame + ORREQ lr, lr, #0x10 // Else set bit, return with standard frame +#endif /* Copy kernel hardware stack to module thread stack. */ LDM r3!, {r1-r2} @@ -521,4 +577,18 @@ _txm_module_user_mode_exit: NOP NOP // } + +#ifdef __ARMVFP__ + + PUBLIC tx_thread_fpu_enable +tx_thread_fpu_enable: + PUBLIC tx_thread_fpu_disable +tx_thread_fpu_disable: + + /* Automatic VPF logic is supported, this function is present only for + backward compatibility purposes and therefore simply returns. */ + + BX LR // Return to caller + +#endif END diff --git a/ports_module/cortex_m3/iar/module_manager/src/tx_thread_stack_build.s b/ports_module/cortex_m3/iar/module_manager/src/tx_thread_stack_build.s index dcc82bf6..5005363e 100644 --- a/ports_module/cortex_m3/iar/module_manager/src/tx_thread_stack_build.s +++ b/ports_module/cortex_m3/iar/module_manager/src/tx_thread_stack_build.s @@ -26,8 +26,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_stack_build Cortex-Mx/IAR */ -/* 6.1.8 */ +/* _tx_thread_stack_build Cortex-M3/IAR */ +/* 6.1.7 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -59,7 +59,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ +/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ /* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) diff --git a/ports_module/cortex_m3/iar/module_manager/src/tx_thread_system_return.s b/ports_module/cortex_m3/iar/module_manager/src/tx_thread_system_return.s index 4c5cb6fb..0c2ae9bf 100644 --- a/ports_module/cortex_m3/iar/module_manager/src/tx_thread_system_return.s +++ b/ports_module/cortex_m3/iar/module_manager/src/tx_thread_system_return.s @@ -26,8 +26,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_system_return Cortex-Mx/IAR */ -/* 6.1.8 */ +/* _tx_thread_system_return Cortex-M3/IAR */ +/* 6.1.7 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -59,7 +59,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ +/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ /* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) diff --git a/ports_module/cortex_m3/iar/module_manager/src/tx_timer_interrupt.s b/ports_module/cortex_m3/iar/module_manager/src/tx_timer_interrupt.s index aa209956..13427464 100644 --- a/ports_module/cortex_m3/iar/module_manager/src/tx_timer_interrupt.s +++ b/ports_module/cortex_m3/iar/module_manager/src/tx_timer_interrupt.s @@ -39,8 +39,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_timer_interrupt Cortex-Mx/IAR */ -/* 6.1.8 */ +/* _tx_timer_interrupt Cortex-M3/IAR */ +/* 6.1.7 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -73,7 +73,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ +/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ /* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) diff --git a/ports_module/cortex_m3/iar/module_manager/src/txm_module_manager_alignment_adjust.c b/ports_module/cortex_m3/iar/module_manager/src/txm_module_manager_alignment_adjust.c index 173cd9ca..92e629a8 100644 --- a/ports_module/cortex_m3/iar/module_manager/src/txm_module_manager_alignment_adjust.c +++ b/ports_module/cortex_m3/iar/module_manager/src/txm_module_manager_alignment_adjust.c @@ -30,8 +30,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _txm_power_of_two_block_size Cortex-M3/MPU/IAR */ -/* 6.1 */ +/* _txm_power_of_two_block_size Cortex-M3 */ +/* 6.1.9 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -61,7 +61,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ /* */ /**************************************************************************/ ULONG _txm_power_of_two_block_size(ULONG size) @@ -93,8 +93,8 @@ ULONG _txm_power_of_two_block_size(ULONG size) /* */ /* FUNCTION RELEASE */ /* */ -/* _txm_module_manager_alignment_adjust Cortex-M3/MPU/IAR */ -/* 6.1 */ +/* _txm_module_manager_alignment_adjust Cortex-M3 */ +/* 6.1.9 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -128,7 +128,7 @@ ULONG _txm_power_of_two_block_size(ULONG size) /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ /* */ /**************************************************************************/ VOID _txm_module_manager_alignment_adjust(TXM_MODULE_PREAMBLE *module_preamble, @@ -137,6 +137,53 @@ VOID _txm_module_manager_alignment_adjust(TXM_MODULE_PREAMBLE *module_preamble, ULONG *data_size, ULONG *data_alignment) { +#ifdef TXM_MODULE_MANAGER_16_MPU +ULONG local_code_size; +ULONG local_code_alignment; +ULONG local_data_size; +ULONG local_data_alignment; +ULONG code_size_accum; +ULONG data_size_accum; + + /* Copy the input parameters into local variables for ease of use. */ + local_code_size = *code_size; + local_code_alignment = *code_alignment; + local_data_size = *data_size; + local_data_alignment = *data_alignment; + + /* Determine code block sizes. Minimize the alignment requirement. + There are 4 MPU code entries available. The following is how the code size + will be distributed: + 1. 1/4 of the largest power of two that is greater than or equal to code size. + 2. 1/4 of the largest power of two that is greater than or equal to code size. + 3. Largest power of 2 that fits in the remaining space. + 4. Smallest power of 2 that exceeds the remaining space, minimum 32. */ + local_code_alignment = _txm_power_of_two_block_size(local_code_size) >> 2; + code_size_accum = local_code_alignment + local_code_alignment; + code_size_accum = code_size_accum + (_txm_power_of_two_block_size(local_code_size - code_size_accum) >> 1); + code_size_accum = code_size_accum + _txm_power_of_two_block_size(local_code_size - code_size_accum); + local_code_size = code_size_accum; + + /* Determine data block sizes. Minimize the alignment requirement. + There are 4 MPU data entries available. The following is how the data size + will be distributed: + 1. 1/4 of the largest power of two that is greater than or equal to data size. + 2. 1/4 of the largest power of two that is greater than or equal to data size. + 3. Largest power of 2 that fits in the remaining space. + 4. Smallest power of 2 that exceeds the remaining space, minimum 32. */ + local_data_alignment = _txm_power_of_two_block_size(local_data_size) >> 2; + data_size_accum = local_data_alignment + local_data_alignment; + data_size_accum = data_size_accum + (_txm_power_of_two_block_size(local_data_size - data_size_accum) >> 1); + data_size_accum = data_size_accum + _txm_power_of_two_block_size(local_data_size - data_size_accum); + local_data_size = data_size_accum; + + /* Return all the information to the caller. */ + *code_size = local_code_size; + *code_alignment = local_code_alignment; + *data_size = local_data_size; + *data_alignment = local_data_alignment; + +#else ULONG local_code_size; ULONG local_code_alignment; @@ -396,4 +443,6 @@ ULONG data_size_accum; *code_alignment = local_code_alignment; *data_size = local_data_size; *data_alignment = local_data_alignment; + +#endif } diff --git a/ports_module/cortex_m3/iar/module_manager/src/txm_module_manager_external_memory_enable.c b/ports_module/cortex_m3/iar/module_manager/src/txm_module_manager_external_memory_enable.c index 2f6b20bd..cb13e4a6 100644 --- a/ports_module/cortex_m3/iar/module_manager/src/txm_module_manager_external_memory_enable.c +++ b/ports_module/cortex_m3/iar/module_manager/src/txm_module_manager_external_memory_enable.c @@ -33,8 +33,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _txm_module_manager_external_memory_enable Cortex-M3/MPU/IAR */ -/* 6.1 */ +/* _txm_module_manager_external_memory_enable Cortex-M3 */ +/* 6.1.9 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -70,7 +70,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ /* */ /**************************************************************************/ UINT _txm_module_manager_external_memory_enable(TXM_MODULE_INSTANCE *module_instance, @@ -78,6 +78,117 @@ UINT _txm_module_manager_external_memory_enable(TXM_MODULE_INSTANCE *module_ins ULONG length, UINT attributes) { +#ifdef TXM_MODULE_MANAGER_16_MPU +ULONG block_size; +ULONG region_size; +ULONG srd_bits; +ULONG size_register; +ULONG address; +ULONG shared_index; +ULONG attributes_check = 0; + + /* Determine if the module manager has not been initialized yet. */ + if (_txm_module_manager_ready != TX_TRUE) + { + /* Module manager has not been initialized. */ + return(TX_NOT_AVAILABLE); + } + + /* Determine if the module is valid. */ + if (module_instance == TX_NULL) + { + /* Invalid module pointer. */ + return(TX_PTR_ERROR); + } + + /* Get module manager protection mutex. */ + _tx_mutex_get(&_txm_module_manager_mutex, TX_WAIT_FOREVER); + + /* Determine if the module instance is valid. */ + if (module_instance -> txm_module_instance_id != TXM_MODULE_ID) + { + /* Release the protection mutex. */ + _tx_mutex_put(&_txm_module_manager_mutex); + + /* Invalid module pointer. */ + return(TX_PTR_ERROR); + } + + /* Determine if the module instance is in the loaded state. */ + if (module_instance -> txm_module_instance_state != TXM_MODULE_LOADED) + { + /* Release the protection mutex. */ + _tx_mutex_put(&_txm_module_manager_mutex); + + /* Return error if the module is not ready. */ + return(TX_START_ERROR); + } + + /* Determine if there are shared memory entries available. */ + if(module_instance -> txm_module_instance_shared_memory_count >= TXM_MODULE_MPU_SHARED_ENTRIES) + { + /* Release the protection mutex. */ + _tx_mutex_put(&_txm_module_manager_mutex); + + /* No more entries available. */ + return(TX_NO_MEMORY); + } + + /* Start address and length must adhere to Cortex-M7 MPU. + The address must align with the block size. */ + + block_size = _txm_power_of_two_block_size(length); + address = (ULONG) start_address; + if(address != (address & ~(block_size - 1))) + { + /* Release the protection mutex. */ + _tx_mutex_put(&_txm_module_manager_mutex); + + /* Return alignment error. */ + return(TXM_MODULE_ALIGNMENT_ERROR); + } + + /* At this point, we have a valid address and block size. + Set up MPU registers. */ + + /* Pick up index into shared memory entries. */ + shared_index = TXM_MODULE_MPU_SHARED_INDEX + module_instance -> txm_module_instance_shared_memory_count; + + /* Save address register with address, MPU region, set Valid bit. */ + module_instance -> txm_module_instance_mpu_registers[shared_index].txm_module_mpu_region_address = address | shared_index | 0x10; + + /* Calculate the region size. */ + region_size = (_txm_module_manager_region_size_get(block_size) << 1); + + /* Calculate the subregion bits. */ + srd_bits = _txm_module_manager_calculate_srd_bits(block_size, length); + + /* Generate SRD, size, and enable attributes. */ + size_register = srd_bits | region_size | TXM_ENABLE_REGION | TXM_MODULE_MPU_SHARED_ACCESS_CONTROL; + + /* Check for optional write attribute. */ + if(attributes & TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE) + { + attributes_check = TXM_MODULE_MANAGER_ATTRIBUTE_WRITE_MPU_BIT; + } + + /* Save attribute-size register. */ + module_instance -> txm_module_instance_mpu_registers[shared_index].txm_module_mpu_region_attribute_size = attributes_check | size_register; + + /* Keep track of shared memory address and length in module instance. */ + module_instance -> txm_module_instance_shared_memory_address[module_instance -> txm_module_instance_shared_memory_count] = address; + module_instance -> txm_module_instance_shared_memory_length[module_instance -> txm_module_instance_shared_memory_count] = length; + + /* Increment counter. */ + module_instance -> txm_module_instance_shared_memory_count++; + + /* Release the protection mutex. */ + _tx_mutex_put(&_txm_module_manager_mutex); + + /* Return success. */ + return(TX_SUCCESS); + +#else ULONG block_size; ULONG region_size; @@ -179,4 +290,6 @@ TXM_MODULE_PREAMBLE *module_preamble; /* Return success. */ return(TX_SUCCESS); + +#endif } diff --git a/ports_module/cortex_m3/iar/module_manager/src/txm_module_manager_memory_fault_handler.c b/ports_module/cortex_m3/iar/module_manager/src/txm_module_manager_memory_fault_handler.c index 8fdeb79f..bcaa98aa 100644 --- a/ports_module/cortex_m3/iar/module_manager/src/txm_module_manager_memory_fault_handler.c +++ b/ports_module/cortex_m3/iar/module_manager/src/txm_module_manager_memory_fault_handler.c @@ -45,8 +45,8 @@ TXM_MODULE_MANAGER_FAULT_INFO /* */ /* FUNCTION RELEASE */ /* */ -/* _txm_module_manager_memory_fault_handler Cortex-M3/MPU/IAR */ -/* 6.1 */ +/* _txm_module_manager_memory_fault_handler Cortex-M3 */ +/* 6.1.9 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -76,7 +76,7 @@ TXM_MODULE_MANAGER_FAULT_INFO /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ /* */ /**************************************************************************/ VOID _txm_module_manager_memory_fault_handler(VOID) diff --git a/ports_module/cortex_m3/iar/module_manager/src/txm_module_manager_memory_fault_notify.c b/ports_module/cortex_m3/iar/module_manager/src/txm_module_manager_memory_fault_notify.c index 8df56b6a..dac86312 100644 --- a/ports_module/cortex_m3/iar/module_manager/src/txm_module_manager_memory_fault_notify.c +++ b/ports_module/cortex_m3/iar/module_manager/src/txm_module_manager_memory_fault_notify.c @@ -38,8 +38,8 @@ extern VOID (*_txm_module_manager_fault_notify)(TX_THREAD *, TXM_MODULE_INSTA /* */ /* FUNCTION RELEASE */ /* */ -/* _txm_module_manager_memory_fault_notify Cortex-M3/MPU/IAR */ -/* 6.1 */ +/* _txm_module_manager_memory_fault_notify Cortex-M3 */ +/* 6.1.9 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -71,7 +71,7 @@ extern VOID (*_txm_module_manager_fault_notify)(TX_THREAD *, TXM_MODULE_INSTA /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ /* */ /**************************************************************************/ UINT _txm_module_manager_memory_fault_notify(VOID (*notify_function)(TX_THREAD *, TXM_MODULE_INSTANCE *)) diff --git a/ports_module/cortex_m3/iar/module_manager/src/txm_module_manager_mm_register_setup.c b/ports_module/cortex_m3/iar/module_manager/src/txm_module_manager_mm_register_setup.c index c51db309..48a14571 100644 --- a/ports_module/cortex_m3/iar/module_manager/src/txm_module_manager_mm_register_setup.c +++ b/ports_module/cortex_m3/iar/module_manager/src/txm_module_manager_mm_register_setup.c @@ -30,8 +30,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _txm_module_manager_region_size_get Cortex-M3/MPU/IAR */ -/* 6.1 */ +/* _txm_module_manager_region_size_get Cortex-M3 */ +/* 6.1.9 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -61,7 +61,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ /* */ /**************************************************************************/ ULONG _txm_module_manager_region_size_get(ULONG block_size) @@ -152,8 +152,8 @@ ULONG return_value; /* */ /* FUNCTION RELEASE */ /* */ -/* _txm_module_manager_calculate_srd_bits Cortex-M3/MPU/IAR */ -/* 6.1 */ +/* _txm_module_manager_calculate_srd_bits Cortex-M3 */ +/* 6.1.9 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -184,7 +184,7 @@ ULONG return_value; /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ /* */ /**************************************************************************/ ULONG _txm_module_manager_calculate_srd_bits(ULONG block_size, ULONG length) @@ -230,16 +230,48 @@ UINT srd_bit_index; /* */ /* FUNCTION RELEASE */ /* */ -/* _txm_module_manager_mm_register_setup Cortex-M3/MPU/IAR */ -/* 6.1 */ +/* _txm_module_manager_mm_register_setup Cortex-M3 */ +/* 6.1.9 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ /* */ /* DESCRIPTION */ /* */ -/* This function sets up the Cortex-M3 MPU register definitions based */ -/* on the module's memory characteristics. */ +/* This function sets up the MPU register definitions based on the */ +/* module's memory characteristics. */ +/* */ +/* Default MPU layout: */ +/* Entry Description */ +/* 0 Kernel mode entry */ +/* 1 Module code region */ +/* 2 Module code region */ +/* 3 Module code region */ +/* 4 Module code region */ +/* 5 Module data region */ +/* 6 Module data region */ +/* 7 Module data region */ +/* */ +/* If TXM_MODULE_MANAGER_16_MPU is defined, there are 16 MPU slots. */ +/* MPU layout for the Cortex-M7: */ +/* Entry Description */ +/* 0 Kernel mode entry */ +/* 1 Module code region */ +/* 2 Module code region */ +/* 3 Module code region */ +/* 4 Module code region */ +/* 5 Module data region */ +/* 6 Module data region */ +/* 7 Module data region */ +/* 8 Module data region */ +/* 9 Module shared memory region */ +/* 10 Module shared memory region */ +/* 11 Module shared memory region */ +/* 12 Unused region */ +/* 13 Unused region */ +/* 14 Unused region */ +/* 15 Unused region */ +/* */ /* */ /* INPUT */ /* */ @@ -261,11 +293,181 @@ UINT srd_bit_index; /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ /* */ /**************************************************************************/ VOID _txm_module_manager_mm_register_setup(TXM_MODULE_INSTANCE *module_instance) { +#ifdef TXM_MODULE_MANAGER_16_MPU + +ULONG code_address; +ULONG code_size; +ULONG data_address; +ULONG data_size; +ULONG start_stop_stack_size; +ULONG callback_stack_size; +ULONG block_size; +ULONG region_size; +ULONG srd_bits = 0; +UINT mpu_table_index; +UINT i; + + + /* Setup the first MPU region for kernel mode entry. */ + /* Set address register to user mode entry function address, which is guaranteed to be at least 32-byte aligned. + Mask address to proper range, region 0, set Valid bit. */ + module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MPU_KERNEL_ENTRY_INDEX].txm_module_mpu_region_address = ((ULONG) _txm_module_manager_user_mode_entry & 0xFFFFFFE0) | 0x10; + /* Set the attributes, size (32 bytes) and enable bit. */ + module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MPU_KERNEL_ENTRY_INDEX].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_CODE_ACCESS_CONTROL | (_txm_module_manager_region_size_get(32) << 1) | TXM_ENABLE_REGION; + /* End of kernel mode entry setup. */ + + /* Setup code protection. */ + + /* Initialize the MPU table index. */ + mpu_table_index = 1; + + /* Pickup code starting address and actual size. */ + code_address = (ULONG) module_instance -> txm_module_instance_code_start; + code_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_code_size; + + /* Determine code block sizes. Minimize the alignment requirement. + There are 4 MPU code entries available. The following is how the code size + will be distributed: + 1. 1/4 of the largest power of two that is greater than or equal to code size. + 2. 1/4 of the largest power of two that is greater than or equal to code size. + 3. Largest power of 2 that fits in the remaining space. + 4. Smallest power of 2 that exceeds the remaining space, minimum 32. */ + + /* Now loop through to setup MPU protection for the code area. */ + for (i = 0; i < TXM_MODULE_MPU_CODE_ENTRIES; i++) + { + /* First two MPU blocks are 1/4 of the largest power of two + that is greater than or equal to code size. */ + if (i < 2) + { + block_size = _txm_power_of_two_block_size(code_size) >> 2; + } + + /* Third MPU block is the largest power of 2 that fits in the remaining space. */ + else if (i == 2) + { + /* Subtract (block_size*2) from code_size to calculate remaining space. */ + code_size = code_size - (block_size << 1); + block_size = _txm_power_of_two_block_size(code_size) >> 1; + } + + /* Last MPU block is the smallest power of 2 that exceeds the remaining space, minimum 32. */ + else + { + /* Calculate remaining space. */ + code_size = code_size - block_size; + block_size = _txm_power_of_two_block_size(code_size); + srd_bits = _txm_module_manager_calculate_srd_bits(block_size, code_size); + } + + /* Calculate the region size information. */ + region_size = (_txm_module_manager_region_size_get(block_size) << 1); + + /* Build the base address register with address, MPU region, set Valid bit. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_address = (code_address & ~(block_size - 1)) | mpu_table_index | 0x10; + /* Build the attribute-size register with permissions, SRD, size, enable. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_CODE_ACCESS_CONTROL | srd_bits | region_size | TXM_ENABLE_REGION; + + /* Adjust the code address. */ + code_address = code_address + block_size; + + /* Increment MPU table index. */ + mpu_table_index++; + } + /* End of code protection. */ + + /* Setup data protection. */ + + /* Reset SRD bitfield. */ + srd_bits = 0; + + /* Pickup data starting address and actual size. */ + data_address = (ULONG) module_instance -> txm_module_instance_data_start; + + /* Adjust the size of the module elements to be aligned to the default alignment. We do this + so that when we partition the allocated memory, we can simply place these regions right beside + each other without having to align their pointers. Note this only works when they all have + the same alignment. */ + + data_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_data_size; + start_stop_stack_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_start_stop_stack_size; + callback_stack_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_callback_stack_size; + + data_size = ((data_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; + + start_stop_stack_size = ((start_stop_stack_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; + + callback_stack_size = ((callback_stack_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; + + /* Update the data size to include thread stacks. */ + data_size = data_size + start_stop_stack_size + callback_stack_size; + + /* Determine data block sizes. Minimize the alignment requirement. + There are 4 MPU data entries available. The following is how the data size + will be distributed: + 1. 1/4 of the largest power of two that is greater than or equal to data size. + 2. 1/4 of the largest power of two that is greater than or equal to data size. + 3. Largest power of 2 that fits in the remaining space. + 4. Smallest power of 2 that exceeds the remaining space, minimum 32. */ + + /* Now loop through to setup MPU protection for the data area. */ + for (i = 0; i < TXM_MODULE_MPU_DATA_ENTRIES; i++) + { + /* First two MPU blocks are 1/4 of the largest power of two + that is greater than or equal to data size. */ + if (i < 2) + { + block_size = _txm_power_of_two_block_size(data_size) >> 2; + } + + /* Third MPU block is the largest power of 2 that fits in the remaining space. */ + else if (i == 2) + { + /* Subtract (block_size*2) from data_size to calculate remaining space. */ + data_size = data_size - (block_size << 1); + block_size = _txm_power_of_two_block_size(data_size) >> 1; + } + + /* Last MPU block is the smallest power of 2 that exceeds the remaining space, minimum 32. */ + else + { + /* Calculate remaining space. */ + data_size = data_size - block_size; + block_size = _txm_power_of_two_block_size(data_size); + srd_bits = _txm_module_manager_calculate_srd_bits(block_size, data_size); + } + + /* Calculate the region size information. */ + region_size = (_txm_module_manager_region_size_get(block_size) << 1); + + /* Build the base address register with address, MPU region, set Valid bit. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_address = (data_address & ~(block_size - 1)) | mpu_table_index | 0x10; + /* Build the attribute-size register with permissions, SRD, size, enable. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_DATA_ACCESS_CONTROL | srd_bits | region_size | TXM_ENABLE_REGION; + + /* Adjust the data address. */ + data_address = data_address + block_size; + + /* Increment MPU table index. */ + mpu_table_index++; + } + + /* Setup MPU for the remaining regions. */ + while (mpu_table_index < TXM_MODULE_MPU_TOTAL_ENTRIES) + { + /* Build the base address register with address, MPU region, set Valid bit. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_address = mpu_table_index | 0x10; + + /* Increment MPU table index. */ + mpu_table_index++; + } + +#else ULONG code_address; ULONG code_size; @@ -382,7 +584,7 @@ UINT i; for (i = 0; i < TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1; i++) { /* Build the base address register. */ - base_address_register = code_address & ~(block_size - 1) | mpu_register | 0x10; + base_address_register = (code_address & ~(block_size - 1)) | mpu_register | 0x10; /* Check if SRD bits need to be set. */ if (code_size < block_size) @@ -509,4 +711,87 @@ UINT i; /* Increment the MPU register index. */ mpu_register++; } + +#endif +} + +#ifdef TXM_MODULE_MANAGER_16_MPU +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_inside_data_check Cortex-M3 */ +/* 6.1.9 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks if the specified object is inside shared */ +/* memory. */ +/* */ +/* INPUT */ +/* */ +/* module_instance Pointer to module instance */ +/* obj_ptr Pointer to the object */ +/* obj_size Size of the object */ +/* */ +/* OUTPUT */ +/* */ +/* Whether the object is inside the shared memory region. */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Module dispatch check functions */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ +/* */ +/**************************************************************************/ +UINT _txm_module_manager_inside_data_check(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE obj_ptr, UINT obj_size) +{ + +UINT shared_memory_index; +UINT num_shared_memory_mpu_entries; +ALIGN_TYPE shared_memory_address_start; +ALIGN_TYPE shared_memory_address_end; + + /* Check for overflow. */ + if ((obj_ptr) > ((obj_ptr) + (obj_size))) + { + return(TX_FALSE); + } + + /* Check if the object is inside the module data. */ + if ((obj_ptr >= (ALIGN_TYPE) module_instance -> txm_module_instance_data_start) && + ((obj_ptr + obj_size) <= ((ALIGN_TYPE) module_instance -> txm_module_instance_data_end + 1))) + { + return(TX_TRUE); + } + + /* Check if the object is inside the shared memory. */ + num_shared_memory_mpu_entries = module_instance -> txm_module_instance_shared_memory_count; + for (shared_memory_index = 0; shared_memory_index < num_shared_memory_mpu_entries; shared_memory_index++) + { + + shared_memory_address_start = (ALIGN_TYPE) module_instance -> txm_module_instance_shared_memory_address[shared_memory_index]; + shared_memory_address_end = shared_memory_address_start + module_instance -> txm_module_instance_shared_memory_length[shared_memory_index]; + + if ((obj_ptr >= (ALIGN_TYPE) shared_memory_address_start) && + ((obj_ptr + obj_size) <= (ALIGN_TYPE) shared_memory_address_end)) + { + return(TX_TRUE); + } + } + + return(TX_FALSE); } +#endif diff --git a/ports_module/cortex_m3/iar/module_manager/src/txm_module_manager_thread_stack_build.s b/ports_module/cortex_m3/iar/module_manager/src/txm_module_manager_thread_stack_build.s index 4c0a49ec..6dbf1c16 100644 --- a/ports_module/cortex_m3/iar/module_manager/src/txm_module_manager_thread_stack_build.s +++ b/ports_module/cortex_m3/iar/module_manager/src/txm_module_manager_thread_stack_build.s @@ -26,8 +26,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _txm_module_manager_thread_stack_build Cortex-M3/MPU/IAR */ -/* 6.1 */ +/* _txm_module_manager_thread_stack_build Cortex-M3/IAR */ +/* 6.1.9 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -59,7 +59,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ /* */ /**************************************************************************/ // VOID _txm_module_manager_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(TX_THREAD *, TXM_MODULE_INSTANCE *)) diff --git a/ports_module/cortex_m33/ac6/inc/tx_port.h b/ports_module/cortex_m33/ac6/inc/tx_port.h index 70f2d34b..d16017af 100644 --- a/ports_module/cortex_m33/ac6/inc/tx_port.h +++ b/ports_module/cortex_m33/ac6/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h Cortex-M33/AC6 */ -/* 6.1.7 */ +/* 6.1.9 */ /* */ /* AUTHOR */ /* */ @@ -55,6 +55,9 @@ /* added symbol to enable */ /* stack error handler, */ /* resulting in version 6.1.7 */ +/* 10-15-2021 William E. Lamie Modified comment(s), added */ +/* symbol ULONG64_DEFINED, */ +/* resulting in version 6.1.9 */ /* */ /**************************************************************************/ @@ -88,6 +91,7 @@ typedef unsigned long ULONG; typedef unsigned long long ULONG64; typedef short SHORT; typedef unsigned short USHORT; +#define ULONG64_DEFINED /* Function prototypes for this port. */ struct TX_THREAD_STRUCT; @@ -579,7 +583,7 @@ unsigned int was_masked; #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M33/AC6 Version 6.1.6 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M33/AC6 Version 6.1.9 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports_module/cortex_m33/ac6/inc/txm_module_port.h b/ports_module/cortex_m33/ac6/inc/txm_module_port.h index 6b846e72..7c5cd693 100644 --- a/ports_module/cortex_m33/ac6/inc/txm_module_port.h +++ b/ports_module/cortex_m33/ac6/inc/txm_module_port.h @@ -349,6 +349,6 @@ ALIGN_TYPE _txm_module_manager_port_dispatch(TXM_MODULE_INSTANCE *module_instanc #define TXM_MODULE_MANAGER_VERSION_ID \ CHAR _txm_module_manager_version_id[] = \ - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-M33/MPU/AC6 Version 6.1.3 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-M33/MPU/AC6 Version 6.1.9 *"; #endif diff --git a/ports_module/cortex_m33/gnu/inc/tx_port.h b/ports_module/cortex_m33/gnu/inc/tx_port.h index 0856a16f..ade416e5 100644 --- a/ports_module/cortex_m33/gnu/inc/tx_port.h +++ b/ports_module/cortex_m33/gnu/inc/tx_port.h @@ -701,7 +701,7 @@ VOID _tx_thread_interrupt_restore(UIN #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARMv8-M Version 6.1.5 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARMv8-M Version 6.1.9 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports_module/cortex_m33/gnu/inc/txm_module_port.h b/ports_module/cortex_m33/gnu/inc/txm_module_port.h index ad7604e0..7ae91c24 100644 --- a/ports_module/cortex_m33/gnu/inc/txm_module_port.h +++ b/ports_module/cortex_m33/gnu/inc/txm_module_port.h @@ -349,6 +349,6 @@ ALIGN_TYPE _txm_module_manager_port_dispatch(TXM_MODULE_INSTANCE *module_instanc #define TXM_MODULE_MANAGER_VERSION_ID \ CHAR _txm_module_manager_version_id[] = \ - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-M33/MPU/GNU Version 6.1.5 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-M33/MPU/GNU Version 6.1.9 *"; #endif diff --git a/ports_module/cortex_m33/iar/inc/tx_port.h b/ports_module/cortex_m33/iar/inc/tx_port.h index 99962029..487bc71b 100644 --- a/ports_module/cortex_m33/iar/inc/tx_port.h +++ b/ports_module/cortex_m33/iar/inc/tx_port.h @@ -701,7 +701,7 @@ VOID _tx_thread_interrupt_restore(UIN #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Modules ARMv8-M Version 6.1.5 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Modules ARMv8-M Version 6.1.9 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports_module/cortex_m33/iar/inc/txm_module_port.h b/ports_module/cortex_m33/iar/inc/txm_module_port.h index 1126935a..ae37777e 100644 --- a/ports_module/cortex_m33/iar/inc/txm_module_port.h +++ b/ports_module/cortex_m33/iar/inc/txm_module_port.h @@ -350,6 +350,6 @@ ALIGN_TYPE _txm_module_manager_port_dispatch(TXM_MODULE_INSTANCE *module_instanc #define TXM_MODULE_MANAGER_VERSION_ID \ CHAR _txm_module_manager_version_id[] = \ - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-M33/MPU/IAR Version 6.1.5 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-M33/MPU/IAR Version 6.1.9 *"; #endif diff --git a/ports_module/cortex_m4/ac5/inc/tx_port.h b/ports_module/cortex_m4/ac5/inc/tx_port.h index ebe5e751..78434fb6 100644 --- a/ports_module/cortex_m4/ac5/inc/tx_port.h +++ b/ports_module/cortex_m4/ac5/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h Cortex-M4/AC5 */ -/* 6.1.6 */ +/* 6.1.9 */ /* */ /* AUTHOR */ /* */ @@ -47,10 +47,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ -/* macro definition, */ -/* resulting in version 6.1.6 */ +/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ /* */ /**************************************************************************/ @@ -142,7 +139,7 @@ typedef unsigned short USHORT; /* Define the port specific options for the _tx_build_options variable. This variable indicates how the ThreadX library was built. */ -#define TX_PORT_SPECIFIC_BUILD_OPTIONS 0 +#define TX_PORT_SPECIFIC_BUILD_OPTIONS (0) /* Define the in-line initialization constant so that modules with in-line @@ -344,8 +341,6 @@ void _tx_vfp_access(void); #endif - - /* Define the ThreadX object creation extensions for the remaining objects. */ #define TX_BLOCK_POOL_CREATE_EXTENSION(pool_ptr) @@ -386,7 +381,7 @@ ULONG _tx_misra_ipsr_get(VOID); zero after initialization for Cortex-M ports. */ #ifndef TX_THREAD_SYSTEM_RETURN_CHECK -#define TX_THREAD_SYSTEM_RETURN_CHECK(c) (c) = ((ULONG) _tx_thread_preempt_disable); +#define TX_THREAD_SYSTEM_RETURN_CHECK(c) (c) = ((ULONG) _tx_thread_preempt_disable); #endif @@ -452,7 +447,7 @@ unsigned int was_masked; #endif -/* Define FPU extension for the Cortex-M4. Each is assumed to be called in the context of the executing +/* Define FPU extension for the Cortex-M4. Each is assumed to be called in the context of the executing thread. These are no longer needed, but are preserved for backward compatibility only. */ void tx_thread_fpu_enable(void); @@ -463,7 +458,7 @@ void tx_thread_fpu_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M4/AC5 Version 6.1 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M4/AC5 Version 6.1.9 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; @@ -474,7 +469,3 @@ extern CHAR _tx_version_id[]; #endif - - - - diff --git a/ports_module/cortex_m4/ac5/inc/txm_module_port.h b/ports_module/cortex_m4/ac5/inc/txm_module_port.h index 443935e7..d4eeb650 100644 --- a/ports_module/cortex_m4/ac5/inc/txm_module_port.h +++ b/ports_module/cortex_m4/ac5/inc/txm_module_port.h @@ -25,8 +25,8 @@ /* */ /* APPLICATION INTERFACE DEFINITION RELEASE */ /* */ -/* txm_module_port.h Cortex-M4/MPU/AC5 */ -/* 6.1.6 */ +/* txm_module_port.h Cortex-M4/AC5 */ +/* 6.1.9 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -40,13 +40,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 11-09-2020 Scott Larson Modified comment(s), */ -/* increase kernel stack size, */ -/* resulting in version 6.1.2 */ -/* 04-02-2021 Scott Larson Modified comment(s), */ -/* added check for overflow, */ -/* resulting in version 6.1.6 */ +/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ /* */ /**************************************************************************/ @@ -97,11 +91,6 @@ The following extensions must also be defined in tx_port.h: VOID (*tx_timer_module_expiration_function)(ULONG id); */ - -/* Size of module heap. */ -#define TXM_MODULE_HEAP_SIZE 512 - - /* Define the kernel stack size for a module thread. */ #ifndef TXM_MODULE_KERNEL_STACK_SIZE #define TXM_MODULE_KERNEL_STACK_SIZE 768 @@ -176,8 +165,43 @@ The following extensions must also be defined in tx_port.h: #define INLINE_DECLARE inline +#ifdef TXM_MODULE_MANAGER_16_MPU + /* Define the number of MPU entries assigned to the code and data sections. - On Cortex-M4 parts, there are 8 total entries. ThreadX uses one for access + On some Cortex-M7 parts, there are 16 total entries. ThreadX uses one for access + to the kernel entry function, thus 15 remain for code and data protection. */ +#define TXM_MODULE_MPU_TOTAL_ENTRIES 16 +#define TXM_MODULE_MPU_CODE_ENTRIES 4 +#define TXM_MODULE_MPU_DATA_ENTRIES 4 +#define TXM_MODULE_MPU_SHARED_ENTRIES 3 + +#define TXM_MODULE_MPU_KERNEL_ENTRY_INDEX 0 +#define TXM_MODULE_MPU_SHARED_INDEX 9 + +#define TXM_ENABLE_REGION 0x01 + +/* There are 2 registers to set up each MPU region: MPU_RBAR, MPU_RASR. */ +typedef struct TXM_MODULE_MPU_INFO_STRUCT +{ + ULONG txm_module_mpu_region_address; + ULONG txm_module_mpu_region_attribute_size; +} TXM_MODULE_MPU_INFO; +/* Shared memory region attributes. */ +#define TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE 1 +#define TXM_MODULE_MANAGER_ATTRIBUTE_WRITE_MPU_BIT 0x01000000 + +/* Define the port-extensions to the module manager instance structure. */ + +#define TXM_MODULE_MANAGER_PORT_EXTENSION \ + TXM_MODULE_MPU_INFO txm_module_instance_mpu_registers[TXM_MODULE_MPU_TOTAL_ENTRIES]; \ + ULONG txm_module_instance_shared_memory_count; \ + ULONG txm_module_instance_shared_memory_address[TXM_MODULE_MPU_SHARED_ENTRIES]; \ + ULONG txm_module_instance_shared_memory_length[TXM_MODULE_MPU_SHARED_ENTRIES]; + +#else /* TXM_MODULE_MANAGER_16_MPU is not defined */ + +/* Define the number of MPU entries assigned to the code and data sections. + On Cortex-M3, M4, and some M7 parts, there are 8 total entries. ThreadX uses one for access to the kernel entry function, thus 7 remain for code and data protection. */ #define TXM_MODULE_MANAGER_CODE_MPU_ENTRIES 4 #define TXM_MODULE_MANAGER_DATA_MPU_ENTRIES 3 @@ -195,6 +219,7 @@ The following extensions must also be defined in tx_port.h: ULONG txm_module_instance_shared_memory_address; \ ULONG txm_module_instance_shared_memory_length; +#endif /* TXM_MODULE_MANAGER_16_MPU */ /* Define the memory fault information structure that is populated when a memory fault occurs. */ @@ -317,6 +342,10 @@ typedef struct TXM_MODULE_MANAGER_MEMORY_FAULT_INFO_STRUCT /* Define the macros to perform port-specific checks when passing pointers to the kernel. */ /* Define macro to make sure object is inside the module's data. */ +#ifdef TXM_MODULE_MANAGER_16_MPU +#define TXM_MODULE_MANAGER_CHECK_INSIDE_DATA(module_instance, obj_ptr, obj_size) \ + _txm_module_manager_inside_data_check(module_instance, obj_ptr, obj_size) +#else #define TXM_MODULE_MANAGER_CHECK_INSIDE_DATA(module_instance, obj_ptr, obj_size) \ /* Check for overflow. */ \ (((obj_ptr) < ((obj_ptr) + (obj_size))) && \ @@ -326,7 +355,7 @@ typedef struct TXM_MODULE_MANAGER_MEMORY_FAULT_INFO_STRUCT /* Check if it's inside shared memory. */ \ (((obj_ptr) >= (ALIGN_TYPE) module_instance -> txm_module_instance_shared_memory_address) && \ (((obj_ptr) + (obj_size)) <= (ALIGN_TYPE) (module_instance -> txm_module_instance_shared_memory_address + module_instance -> txm_module_instance_shared_memory_length))))) - +#endif /* Define some internal prototypes to this module port. */ @@ -342,10 +371,11 @@ UINT _txm_module_manager_memory_fault_notify(VOID (*notify_function)(TX_THREAD VOID _txm_module_manager_mm_register_setup(TXM_MODULE_INSTANCE *module_instance); \ ULONG _txm_power_of_two_block_size(ULONG size); \ ULONG _txm_module_manager_calculate_srd_bits(ULONG block_size, ULONG length); \ -ULONG _txm_module_manager_region_size_get(ULONG block_size); +ULONG _txm_module_manager_region_size_get(ULONG block_size); \ +UINT _txm_module_manager_inside_data_check(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE obj_ptr, UINT obj_size); #define TXM_MODULE_MANAGER_VERSION_ID \ CHAR _txm_module_manager_version_id[] = \ - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-M4/MPU/AC5 Version 6.1.2 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-M4/AC5 Version 6.1.9 *"; #endif diff --git a/ports_module/cortex_m7/ac5/module_lib/src/txm_module_initialize.S b/ports_module/cortex_m4/ac5/module_lib/src/txm_module_initialize.s index fc9f21f2..1883ad7b 100644 --- a/ports_module/cortex_m7/ac5/module_lib/src/txm_module_initialize.S +++ b/ports_module/cortex_m4/ac5/module_lib/src/txm_module_initialize.s @@ -29,8 +29,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _txm_module_initialize Cortex-M7/MPU/AC5 */ -/* 6.1.2 */ +/* _txm_module_initialize Cortex-M4/AC5 */ +/* 6.1.9 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -59,9 +59,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 11-09-2020 Scott Larson Modified comment(s), */ -/* resulting in version 6.1.2 */ +/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ /* */ /**************************************************************************/ // VOID _txm_module_initialize(VOID) diff --git a/ports_module/cortex_m4/ac5/module_lib/src/txm_module_thread_shell_entry.c b/ports_module/cortex_m4/ac5/module_lib/src/txm_module_thread_shell_entry.c index 33b1e5a5..a537bb0a 100644 --- a/ports_module/cortex_m4/ac5/module_lib/src/txm_module_thread_shell_entry.c +++ b/ports_module/cortex_m4/ac5/module_lib/src/txm_module_thread_shell_entry.c @@ -44,7 +44,9 @@ TXM_MODULE_THREAD_ENTRY_INFO *_txm_module_entry_info; ULONG (*_txm_module_kernel_call_dispatcher)(ULONG kernel_request, ULONG param_1, ULONG param_2, ULONG param3); -/* Define the ARM cstartup code. */ +/* Define the startup code that clears the uninitialized global data and sets up the + preset global variables. */ + extern VOID _txm_module_initialize(VOID); __align(8) UCHAR txm_heap[TXM_MODULE_HEAP_SIZE]; @@ -53,15 +55,15 @@ __align(8) UCHAR txm_heap[TXM_MODULE_HEAP_SIZE]; /* */ /* FUNCTION RELEASE */ /* */ -/* _txm_module_thread_shell_entry Cortex-M4/MPU/AC5 */ -/* 6.1 */ +/* _txm_module_thread_shell_entry Cortex-M4/AC5 */ +/* 6.1.9 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ /* */ /* DESCRIPTION */ /* */ -/* This function calls the specified entry function of the thread. It */ +/* This function calls the specified entry function of the thread. It */ /* also provides a place for the thread's entry function to return. */ /* If the thread returns, this function places the thread in a */ /* "COMPLETED" state. */ @@ -90,7 +92,7 @@ __align(8) UCHAR txm_heap[TXM_MODULE_HEAP_SIZE]; /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ /* */ /**************************************************************************/ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_ENTRY_INFO *thread_info) @@ -105,7 +107,7 @@ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_EN execution. If not, simply skip the C startup code. */ if (thread_info -> txm_module_thread_entry_info_start_thread) { - /* Initialize the ARM C environment. */ + /* Initialize the C environment. */ _txm_module_initialize(); /* Save the entry info pointer, for later use. */ @@ -170,4 +172,3 @@ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_EN TX_SAFETY_CRITICAL_EXCEPTION(__FILE__, __LINE__, 0); #endif } - diff --git a/ports_module/cortex_m3/ac5/module_manager/src/tx_thread_context_restore.S b/ports_module/cortex_m4/ac5/module_manager/src/tx_thread_context_restore.s index 1159ea66..8576cae4 100644 --- a/ports_module/cortex_m3/ac5/module_manager/src/tx_thread_context_restore.S +++ b/ports_module/cortex_m4/ac5/module_manager/src/tx_thread_context_restore.s @@ -30,8 +30,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_context_restore Cortex-Mx/AC5 */ -/* 6.1.8 */ +/* _tx_thread_context_restore Cortex-M4/AC5 */ +/* 6.1.7 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -61,7 +61,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ +/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ /* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) diff --git a/ports_module/cortex_m3/ac5/module_manager/src/tx_thread_context_save.S b/ports_module/cortex_m4/ac5/module_manager/src/tx_thread_context_save.s index d8ee75a4..4fded670 100644 --- a/ports_module/cortex_m3/ac5/module_manager/src/tx_thread_context_save.S +++ b/ports_module/cortex_m4/ac5/module_manager/src/tx_thread_context_save.s @@ -30,8 +30,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_context_save Cortex-Mx/AC5 */ -/* 6.1.8 */ +/* _tx_thread_context_save Cortex-M4/AC5 */ +/* 6.1.7 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -61,7 +61,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ +/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ /* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) diff --git a/ports_module/cortex_m4/ac5/module_manager/src/tx_thread_interrupt_control.S b/ports_module/cortex_m4/ac5/module_manager/src/tx_thread_interrupt_control.s index 4c5e1c33..7f66f181 100644 --- a/ports_module/cortex_m4/ac5/module_manager/src/tx_thread_interrupt_control.S +++ b/ports_module/cortex_m4/ac5/module_manager/src/tx_thread_interrupt_control.s @@ -25,8 +25,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_interrupt_control Cortex-Mx/AC5 */ -/* 6.1.8 */ +/* _tx_thread_interrupt_control Cortex-M4/AC5 */ +/* 6.1.7 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -56,7 +56,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ +/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ /* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) diff --git a/ports_module/cortex_m4/ac5/module_manager/src/tx_thread_interrupt_disable.S b/ports_module/cortex_m4/ac5/module_manager/src/tx_thread_interrupt_disable.s index 88e6a864..4712f26b 100644 --- a/ports_module/cortex_m4/ac5/module_manager/src/tx_thread_interrupt_disable.S +++ b/ports_module/cortex_m4/ac5/module_manager/src/tx_thread_interrupt_disable.s @@ -25,8 +25,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_interrupt_disable Cortex-Mx/AC5 */ -/* 6.1.8 */ +/* _tx_thread_interrupt_disable Cortex-M4/AC5 */ +/* 6.1.7 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -56,7 +56,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ +/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ /* */ /**************************************************************************/ // UINT _tx_thread_interrupt_disable(VOID) diff --git a/ports_module/cortex_m3/ac5/module_manager/src/tx_thread_interrupt_restore.S b/ports_module/cortex_m4/ac5/module_manager/src/tx_thread_interrupt_restore.s index 22340c21..a30922c3 100644 --- a/ports_module/cortex_m3/ac5/module_manager/src/tx_thread_interrupt_restore.S +++ b/ports_module/cortex_m4/ac5/module_manager/src/tx_thread_interrupt_restore.s @@ -25,8 +25,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_interrupt_restore Cortex-Mx/AC5 */ -/* 6.1.8 */ +/* _tx_thread_interrupt_restore Cortex-M4/AC5 */ +/* 6.1.7 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -56,7 +56,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ +/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ /* */ /**************************************************************************/ // VOID _tx_thread_interrupt_restore(UINT previous_posture) diff --git a/ports_module/cortex_m4/ac5/module_manager/src/tx_thread_schedule.S b/ports_module/cortex_m4/ac5/module_manager/src/tx_thread_schedule.s index 71275358..bd2f6f25 100644 --- a/ports_module/cortex_m4/ac5/module_manager/src/tx_thread_schedule.S +++ b/ports_module/cortex_m4/ac5/module_manager/src/tx_thread_schedule.s @@ -39,8 +39,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_schedule Cortex-M4/MPU/AC5 */ -/* 6.1.7 */ +/* _tx_thread_schedule Cortex-M4/AC5 */ +/* 6.1.9 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -73,14 +73,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 11-09-2020 Scott Larson Modified comment(s), arrange */ -/* code to fix link error when */ -/* VFP is enabled, resulting */ -/* in version 6.1.2 */ -/* 06-02-2021 Scott Larson Fixed extended stack handling */ -/* when calling kernel APIs, */ -/* resulting in version 6.1.7 */ +/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ /* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) @@ -359,10 +352,21 @@ __tx_ts_restore // Use alias registers to quickly load MPU ADD r0, r0, #100 // Build address of MPU register start in thread control block +#ifdef TXM_MODULE_MANAGER_16_MPU + LDM r0!,{r2-r9} // Load MPU regions 0-3 + STM r1,{r2-r9} // Store MPU regions 0-3 + LDM r0!,{r2-r9} // Load MPU regions 4-7 + STM r1,{r2-r9} // Store MPU regions 4-7 + LDM r0!,{r2-r9} // Load MPU regions 8-11 + STM r1,{r2-r9} // Store MPU regions 8-11 + LDM r0,{r2-r9} // Load MPU regions 12-15 + STM r1,{r2-r9} // Store MPU regions 12-15 +#else LDM r0!,{r2-r9} // Load first four MPU regions STM r1,{r2-r9} // Store first four MPU regions LDM r0,{r2-r9} // Load second four MPU regions STM r1,{r2-r9} // Store second four MPU regions +#endif LDR r0, =0xE000ED94 // Build MPU control reg address MOV r1, #5 // Build enable value with background region enabled STR r1, [r0] // Enable MPU diff --git a/ports_module/cortex_m7/ac5/module_manager/src/tx_thread_stack_build.S b/ports_module/cortex_m4/ac5/module_manager/src/tx_thread_stack_build.s index 11effa55..6336aad6 100644 --- a/ports_module/cortex_m7/ac5/module_manager/src/tx_thread_stack_build.S +++ b/ports_module/cortex_m4/ac5/module_manager/src/tx_thread_stack_build.s @@ -25,8 +25,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_stack_build Cortex-Mx/AC5 */ -/* 6.1.8 */ +/* _tx_thread_stack_build Cortex-M4/AC5 */ +/* 6.1.7 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -58,7 +58,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ +/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ /* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) diff --git a/ports_module/cortex_m3/ac5/module_manager/src/tx_thread_system_return.S b/ports_module/cortex_m4/ac5/module_manager/src/tx_thread_system_return.s index 0ab4ae36..9e28a138 100644 --- a/ports_module/cortex_m3/ac5/module_manager/src/tx_thread_system_return.S +++ b/ports_module/cortex_m4/ac5/module_manager/src/tx_thread_system_return.s @@ -25,8 +25,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_system_return Cortex-Mx/AC5 */ -/* 6.1.8 */ +/* _tx_thread_system_return Cortex-M4/AC5 */ +/* 6.1.7 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -58,7 +58,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ +/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ /* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) diff --git a/ports_module/cortex_m3/ac5/module_manager/src/tx_timer_interrupt.S b/ports_module/cortex_m4/ac5/module_manager/src/tx_timer_interrupt.s index 12fef571..7e694b07 100644 --- a/ports_module/cortex_m3/ac5/module_manager/src/tx_timer_interrupt.S +++ b/ports_module/cortex_m4/ac5/module_manager/src/tx_timer_interrupt.s @@ -39,8 +39,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_timer_interrupt Cortex-Mx/AC5 */ -/* 6.1.8 */ +/* _tx_timer_interrupt Cortex-M4/AC5 */ +/* 6.1.7 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -73,7 +73,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ +/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ /* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) diff --git a/ports_module/cortex_m4/ac5/module_manager/src/txm_module_manager_alignment_adjust.c b/ports_module/cortex_m4/ac5/module_manager/src/txm_module_manager_alignment_adjust.c index f91a8fae..65e04cc1 100644 --- a/ports_module/cortex_m4/ac5/module_manager/src/txm_module_manager_alignment_adjust.c +++ b/ports_module/cortex_m4/ac5/module_manager/src/txm_module_manager_alignment_adjust.c @@ -30,8 +30,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _txm_power_of_two_block_size Cortex-M4/MPU/AC5 */ -/* 6.1 */ +/* _txm_power_of_two_block_size Cortex-M4 */ +/* 6.1.9 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -61,7 +61,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ /* */ /**************************************************************************/ ULONG _txm_power_of_two_block_size(ULONG size) @@ -93,8 +93,8 @@ ULONG _txm_power_of_two_block_size(ULONG size) /* */ /* FUNCTION RELEASE */ /* */ -/* _txm_module_manager_alignment_adjust Cortex-M4/MPU/AC5 */ -/* 6.1 */ +/* _txm_module_manager_alignment_adjust Cortex-M4 */ +/* 6.1.9 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -128,7 +128,7 @@ ULONG _txm_power_of_two_block_size(ULONG size) /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ /* */ /**************************************************************************/ VOID _txm_module_manager_alignment_adjust(TXM_MODULE_PREAMBLE *module_preamble, @@ -137,6 +137,53 @@ VOID _txm_module_manager_alignment_adjust(TXM_MODULE_PREAMBLE *module_preamble, ULONG *data_size, ULONG *data_alignment) { +#ifdef TXM_MODULE_MANAGER_16_MPU +ULONG local_code_size; +ULONG local_code_alignment; +ULONG local_data_size; +ULONG local_data_alignment; +ULONG code_size_accum; +ULONG data_size_accum; + + /* Copy the input parameters into local variables for ease of use. */ + local_code_size = *code_size; + local_code_alignment = *code_alignment; + local_data_size = *data_size; + local_data_alignment = *data_alignment; + + /* Determine code block sizes. Minimize the alignment requirement. + There are 4 MPU code entries available. The following is how the code size + will be distributed: + 1. 1/4 of the largest power of two that is greater than or equal to code size. + 2. 1/4 of the largest power of two that is greater than or equal to code size. + 3. Largest power of 2 that fits in the remaining space. + 4. Smallest power of 2 that exceeds the remaining space, minimum 32. */ + local_code_alignment = _txm_power_of_two_block_size(local_code_size) >> 2; + code_size_accum = local_code_alignment + local_code_alignment; + code_size_accum = code_size_accum + (_txm_power_of_two_block_size(local_code_size - code_size_accum) >> 1); + code_size_accum = code_size_accum + _txm_power_of_two_block_size(local_code_size - code_size_accum); + local_code_size = code_size_accum; + + /* Determine data block sizes. Minimize the alignment requirement. + There are 4 MPU data entries available. The following is how the data size + will be distributed: + 1. 1/4 of the largest power of two that is greater than or equal to data size. + 2. 1/4 of the largest power of two that is greater than or equal to data size. + 3. Largest power of 2 that fits in the remaining space. + 4. Smallest power of 2 that exceeds the remaining space, minimum 32. */ + local_data_alignment = _txm_power_of_two_block_size(local_data_size) >> 2; + data_size_accum = local_data_alignment + local_data_alignment; + data_size_accum = data_size_accum + (_txm_power_of_two_block_size(local_data_size - data_size_accum) >> 1); + data_size_accum = data_size_accum + _txm_power_of_two_block_size(local_data_size - data_size_accum); + local_data_size = data_size_accum; + + /* Return all the information to the caller. */ + *code_size = local_code_size; + *code_alignment = local_code_alignment; + *data_size = local_data_size; + *data_alignment = local_data_alignment; + +#else ULONG local_code_size; ULONG local_code_alignment; @@ -396,4 +443,6 @@ ULONG data_size_accum; *code_alignment = local_code_alignment; *data_size = local_data_size; *data_alignment = local_data_alignment; + +#endif } diff --git a/ports_module/cortex_m4/ac5/module_manager/src/txm_module_manager_external_memory_enable.c b/ports_module/cortex_m4/ac5/module_manager/src/txm_module_manager_external_memory_enable.c index df025827..79af7655 100644 --- a/ports_module/cortex_m4/ac5/module_manager/src/txm_module_manager_external_memory_enable.c +++ b/ports_module/cortex_m4/ac5/module_manager/src/txm_module_manager_external_memory_enable.c @@ -33,8 +33,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _txm_module_manager_external_memory_enable Cortex-M4/MPU/AC5 */ -/* 6.1 */ +/* _txm_module_manager_external_memory_enable Cortex-M4 */ +/* 6.1.9 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -70,7 +70,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ /* */ /**************************************************************************/ UINT _txm_module_manager_external_memory_enable(TXM_MODULE_INSTANCE *module_instance, @@ -78,6 +78,117 @@ UINT _txm_module_manager_external_memory_enable(TXM_MODULE_INSTANCE *module_ins ULONG length, UINT attributes) { +#ifdef TXM_MODULE_MANAGER_16_MPU +ULONG block_size; +ULONG region_size; +ULONG srd_bits; +ULONG size_register; +ULONG address; +ULONG shared_index; +ULONG attributes_check = 0; + + /* Determine if the module manager has not been initialized yet. */ + if (_txm_module_manager_ready != TX_TRUE) + { + /* Module manager has not been initialized. */ + return(TX_NOT_AVAILABLE); + } + + /* Determine if the module is valid. */ + if (module_instance == TX_NULL) + { + /* Invalid module pointer. */ + return(TX_PTR_ERROR); + } + + /* Get module manager protection mutex. */ + _tx_mutex_get(&_txm_module_manager_mutex, TX_WAIT_FOREVER); + + /* Determine if the module instance is valid. */ + if (module_instance -> txm_module_instance_id != TXM_MODULE_ID) + { + /* Release the protection mutex. */ + _tx_mutex_put(&_txm_module_manager_mutex); + + /* Invalid module pointer. */ + return(TX_PTR_ERROR); + } + + /* Determine if the module instance is in the loaded state. */ + if (module_instance -> txm_module_instance_state != TXM_MODULE_LOADED) + { + /* Release the protection mutex. */ + _tx_mutex_put(&_txm_module_manager_mutex); + + /* Return error if the module is not ready. */ + return(TX_START_ERROR); + } + + /* Determine if there are shared memory entries available. */ + if(module_instance -> txm_module_instance_shared_memory_count >= TXM_MODULE_MPU_SHARED_ENTRIES) + { + /* Release the protection mutex. */ + _tx_mutex_put(&_txm_module_manager_mutex); + + /* No more entries available. */ + return(TX_NO_MEMORY); + } + + /* Start address and length must adhere to Cortex-M7 MPU. + The address must align with the block size. */ + + block_size = _txm_power_of_two_block_size(length); + address = (ULONG) start_address; + if(address != (address & ~(block_size - 1))) + { + /* Release the protection mutex. */ + _tx_mutex_put(&_txm_module_manager_mutex); + + /* Return alignment error. */ + return(TXM_MODULE_ALIGNMENT_ERROR); + } + + /* At this point, we have a valid address and block size. + Set up MPU registers. */ + + /* Pick up index into shared memory entries. */ + shared_index = TXM_MODULE_MPU_SHARED_INDEX + module_instance -> txm_module_instance_shared_memory_count; + + /* Save address register with address, MPU region, set Valid bit. */ + module_instance -> txm_module_instance_mpu_registers[shared_index].txm_module_mpu_region_address = address | shared_index | 0x10; + + /* Calculate the region size. */ + region_size = (_txm_module_manager_region_size_get(block_size) << 1); + + /* Calculate the subregion bits. */ + srd_bits = _txm_module_manager_calculate_srd_bits(block_size, length); + + /* Generate SRD, size, and enable attributes. */ + size_register = srd_bits | region_size | TXM_ENABLE_REGION | TXM_MODULE_MPU_SHARED_ACCESS_CONTROL; + + /* Check for optional write attribute. */ + if(attributes & TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE) + { + attributes_check = TXM_MODULE_MANAGER_ATTRIBUTE_WRITE_MPU_BIT; + } + + /* Save attribute-size register. */ + module_instance -> txm_module_instance_mpu_registers[shared_index].txm_module_mpu_region_attribute_size = attributes_check | size_register; + + /* Keep track of shared memory address and length in module instance. */ + module_instance -> txm_module_instance_shared_memory_address[module_instance -> txm_module_instance_shared_memory_count] = address; + module_instance -> txm_module_instance_shared_memory_length[module_instance -> txm_module_instance_shared_memory_count] = length; + + /* Increment counter. */ + module_instance -> txm_module_instance_shared_memory_count++; + + /* Release the protection mutex. */ + _tx_mutex_put(&_txm_module_manager_mutex); + + /* Return success. */ + return(TX_SUCCESS); + +#else ULONG block_size; ULONG region_size; @@ -179,4 +290,6 @@ TXM_MODULE_PREAMBLE *module_preamble; /* Return success. */ return(TX_SUCCESS); + +#endif } diff --git a/ports_module/cortex_m4/ac5/module_manager/src/txm_module_manager_memory_fault_handler.c b/ports_module/cortex_m4/ac5/module_manager/src/txm_module_manager_memory_fault_handler.c index 44c01f1e..47c2b014 100644 --- a/ports_module/cortex_m4/ac5/module_manager/src/txm_module_manager_memory_fault_handler.c +++ b/ports_module/cortex_m4/ac5/module_manager/src/txm_module_manager_memory_fault_handler.c @@ -45,8 +45,8 @@ TXM_MODULE_MANAGER_FAULT_INFO /* */ /* FUNCTION RELEASE */ /* */ -/* _txm_module_manager_memory_fault_handler Cortex-M4/MPU/AC5 */ -/* 6.1 */ +/* _txm_module_manager_memory_fault_handler Cortex-M4 */ +/* 6.1.9 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -76,7 +76,7 @@ TXM_MODULE_MANAGER_FAULT_INFO /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ /* */ /**************************************************************************/ VOID _txm_module_manager_memory_fault_handler(VOID) diff --git a/ports_module/cortex_m4/ac5/module_manager/src/txm_module_manager_memory_fault_notify.c b/ports_module/cortex_m4/ac5/module_manager/src/txm_module_manager_memory_fault_notify.c index e4d38642..ba5f5bd6 100644 --- a/ports_module/cortex_m4/ac5/module_manager/src/txm_module_manager_memory_fault_notify.c +++ b/ports_module/cortex_m4/ac5/module_manager/src/txm_module_manager_memory_fault_notify.c @@ -38,8 +38,8 @@ extern VOID (*_txm_module_manager_fault_notify)(TX_THREAD *, TXM_MODULE_INSTA /* */ /* FUNCTION RELEASE */ /* */ -/* _txm_module_manager_memory_fault_notify Cortex-M4/MPU/AC5 */ -/* 6.1 */ +/* _txm_module_manager_memory_fault_notify Cortex-M4 */ +/* 6.1.9 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -71,7 +71,7 @@ extern VOID (*_txm_module_manager_fault_notify)(TX_THREAD *, TXM_MODULE_INSTA /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ /* */ /**************************************************************************/ UINT _txm_module_manager_memory_fault_notify(VOID (*notify_function)(TX_THREAD *, TXM_MODULE_INSTANCE *)) diff --git a/ports_module/cortex_m4/ac5/module_manager/src/txm_module_manager_mm_register_setup.c b/ports_module/cortex_m4/ac5/module_manager/src/txm_module_manager_mm_register_setup.c index 6fa28af7..dcc8d2aa 100644 --- a/ports_module/cortex_m4/ac5/module_manager/src/txm_module_manager_mm_register_setup.c +++ b/ports_module/cortex_m4/ac5/module_manager/src/txm_module_manager_mm_register_setup.c @@ -30,8 +30,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _txm_module_manager_region_size_get Cortex-M4/MPU/AC5 */ -/* 6.1 */ +/* _txm_module_manager_region_size_get Cortex-M4 */ +/* 6.1.9 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -61,7 +61,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ /* */ /**************************************************************************/ ULONG _txm_module_manager_region_size_get(ULONG block_size) @@ -152,8 +152,8 @@ ULONG return_value; /* */ /* FUNCTION RELEASE */ /* */ -/* _txm_module_manager_calculate_srd_bits Cortex-M4/MPU/AC5 */ -/* 6.1 */ +/* _txm_module_manager_calculate_srd_bits Cortex-M4 */ +/* 6.1.9 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -184,7 +184,7 @@ ULONG return_value; /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ /* */ /**************************************************************************/ ULONG _txm_module_manager_calculate_srd_bits(ULONG block_size, ULONG length) @@ -230,16 +230,48 @@ UINT srd_bit_index; /* */ /* FUNCTION RELEASE */ /* */ -/* _txm_module_manager_mm_register_setup Cortex-M4/MPU/AC5 */ -/* 6.1 */ +/* _txm_module_manager_mm_register_setup Cortex-M4 */ +/* 6.1.9 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ /* */ /* DESCRIPTION */ /* */ -/* This function sets up the Cortex-M4 MPU register definitions based */ -/* on the module's memory characteristics. */ +/* This function sets up the MPU register definitions based on the */ +/* module's memory characteristics. */ +/* */ +/* Default MPU layout: */ +/* Entry Description */ +/* 0 Kernel mode entry */ +/* 1 Module code region */ +/* 2 Module code region */ +/* 3 Module code region */ +/* 4 Module code region */ +/* 5 Module data region */ +/* 6 Module data region */ +/* 7 Module data region */ +/* */ +/* If TXM_MODULE_MANAGER_16_MPU is defined, there are 16 MPU slots. */ +/* MPU layout for the Cortex-M7: */ +/* Entry Description */ +/* 0 Kernel mode entry */ +/* 1 Module code region */ +/* 2 Module code region */ +/* 3 Module code region */ +/* 4 Module code region */ +/* 5 Module data region */ +/* 6 Module data region */ +/* 7 Module data region */ +/* 8 Module data region */ +/* 9 Module shared memory region */ +/* 10 Module shared memory region */ +/* 11 Module shared memory region */ +/* 12 Unused region */ +/* 13 Unused region */ +/* 14 Unused region */ +/* 15 Unused region */ +/* */ /* */ /* INPUT */ /* */ @@ -261,11 +293,181 @@ UINT srd_bit_index; /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ /* */ /**************************************************************************/ VOID _txm_module_manager_mm_register_setup(TXM_MODULE_INSTANCE *module_instance) { +#ifdef TXM_MODULE_MANAGER_16_MPU + +ULONG code_address; +ULONG code_size; +ULONG data_address; +ULONG data_size; +ULONG start_stop_stack_size; +ULONG callback_stack_size; +ULONG block_size; +ULONG region_size; +ULONG srd_bits = 0; +UINT mpu_table_index; +UINT i; + + + /* Setup the first MPU region for kernel mode entry. */ + /* Set address register to user mode entry function address, which is guaranteed to be at least 32-byte aligned. + Mask address to proper range, region 0, set Valid bit. */ + module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MPU_KERNEL_ENTRY_INDEX].txm_module_mpu_region_address = ((ULONG) _txm_module_manager_user_mode_entry & 0xFFFFFFE0) | 0x10; + /* Set the attributes, size (32 bytes) and enable bit. */ + module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MPU_KERNEL_ENTRY_INDEX].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_CODE_ACCESS_CONTROL | (_txm_module_manager_region_size_get(32) << 1) | TXM_ENABLE_REGION; + /* End of kernel mode entry setup. */ + + /* Setup code protection. */ + + /* Initialize the MPU table index. */ + mpu_table_index = 1; + + /* Pickup code starting address and actual size. */ + code_address = (ULONG) module_instance -> txm_module_instance_code_start; + code_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_code_size; + + /* Determine code block sizes. Minimize the alignment requirement. + There are 4 MPU code entries available. The following is how the code size + will be distributed: + 1. 1/4 of the largest power of two that is greater than or equal to code size. + 2. 1/4 of the largest power of two that is greater than or equal to code size. + 3. Largest power of 2 that fits in the remaining space. + 4. Smallest power of 2 that exceeds the remaining space, minimum 32. */ + + /* Now loop through to setup MPU protection for the code area. */ + for (i = 0; i < TXM_MODULE_MPU_CODE_ENTRIES; i++) + { + /* First two MPU blocks are 1/4 of the largest power of two + that is greater than or equal to code size. */ + if (i < 2) + { + block_size = _txm_power_of_two_block_size(code_size) >> 2; + } + + /* Third MPU block is the largest power of 2 that fits in the remaining space. */ + else if (i == 2) + { + /* Subtract (block_size*2) from code_size to calculate remaining space. */ + code_size = code_size - (block_size << 1); + block_size = _txm_power_of_two_block_size(code_size) >> 1; + } + + /* Last MPU block is the smallest power of 2 that exceeds the remaining space, minimum 32. */ + else + { + /* Calculate remaining space. */ + code_size = code_size - block_size; + block_size = _txm_power_of_two_block_size(code_size); + srd_bits = _txm_module_manager_calculate_srd_bits(block_size, code_size); + } + + /* Calculate the region size information. */ + region_size = (_txm_module_manager_region_size_get(block_size) << 1); + + /* Build the base address register with address, MPU region, set Valid bit. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_address = (code_address & ~(block_size - 1)) | mpu_table_index | 0x10; + /* Build the attribute-size register with permissions, SRD, size, enable. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_CODE_ACCESS_CONTROL | srd_bits | region_size | TXM_ENABLE_REGION; + + /* Adjust the code address. */ + code_address = code_address + block_size; + + /* Increment MPU table index. */ + mpu_table_index++; + } + /* End of code protection. */ + + /* Setup data protection. */ + + /* Reset SRD bitfield. */ + srd_bits = 0; + + /* Pickup data starting address and actual size. */ + data_address = (ULONG) module_instance -> txm_module_instance_data_start; + + /* Adjust the size of the module elements to be aligned to the default alignment. We do this + so that when we partition the allocated memory, we can simply place these regions right beside + each other without having to align their pointers. Note this only works when they all have + the same alignment. */ + + data_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_data_size; + start_stop_stack_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_start_stop_stack_size; + callback_stack_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_callback_stack_size; + + data_size = ((data_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; + + start_stop_stack_size = ((start_stop_stack_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; + + callback_stack_size = ((callback_stack_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; + + /* Update the data size to include thread stacks. */ + data_size = data_size + start_stop_stack_size + callback_stack_size; + + /* Determine data block sizes. Minimize the alignment requirement. + There are 4 MPU data entries available. The following is how the data size + will be distributed: + 1. 1/4 of the largest power of two that is greater than or equal to data size. + 2. 1/4 of the largest power of two that is greater than or equal to data size. + 3. Largest power of 2 that fits in the remaining space. + 4. Smallest power of 2 that exceeds the remaining space, minimum 32. */ + + /* Now loop through to setup MPU protection for the data area. */ + for (i = 0; i < TXM_MODULE_MPU_DATA_ENTRIES; i++) + { + /* First two MPU blocks are 1/4 of the largest power of two + that is greater than or equal to data size. */ + if (i < 2) + { + block_size = _txm_power_of_two_block_size(data_size) >> 2; + } + + /* Third MPU block is the largest power of 2 that fits in the remaining space. */ + else if (i == 2) + { + /* Subtract (block_size*2) from data_size to calculate remaining space. */ + data_size = data_size - (block_size << 1); + block_size = _txm_power_of_two_block_size(data_size) >> 1; + } + + /* Last MPU block is the smallest power of 2 that exceeds the remaining space, minimum 32. */ + else + { + /* Calculate remaining space. */ + data_size = data_size - block_size; + block_size = _txm_power_of_two_block_size(data_size); + srd_bits = _txm_module_manager_calculate_srd_bits(block_size, data_size); + } + + /* Calculate the region size information. */ + region_size = (_txm_module_manager_region_size_get(block_size) << 1); + + /* Build the base address register with address, MPU region, set Valid bit. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_address = (data_address & ~(block_size - 1)) | mpu_table_index | 0x10; + /* Build the attribute-size register with permissions, SRD, size, enable. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_DATA_ACCESS_CONTROL | srd_bits | region_size | TXM_ENABLE_REGION; + + /* Adjust the data address. */ + data_address = data_address + block_size; + + /* Increment MPU table index. */ + mpu_table_index++; + } + + /* Setup MPU for the remaining regions. */ + while (mpu_table_index < TXM_MODULE_MPU_TOTAL_ENTRIES) + { + /* Build the base address register with address, MPU region, set Valid bit. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_address = mpu_table_index | 0x10; + + /* Increment MPU table index. */ + mpu_table_index++; + } + +#else ULONG code_address; ULONG code_size; @@ -382,7 +584,7 @@ UINT i; for (i = 0; i < TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1; i++) { /* Build the base address register. */ - base_address_register = code_address & ~(block_size - 1) | mpu_register | 0x10; + base_address_register = (code_address & ~(block_size - 1)) | mpu_register | 0x10; /* Check if SRD bits need to be set. */ if (code_size < block_size) @@ -509,4 +711,87 @@ UINT i; /* Increment the MPU register index. */ mpu_register++; } + +#endif +} + +#ifdef TXM_MODULE_MANAGER_16_MPU +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_inside_data_check Cortex-M4 */ +/* 6.1.9 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks if the specified object is inside shared */ +/* memory. */ +/* */ +/* INPUT */ +/* */ +/* module_instance Pointer to module instance */ +/* obj_ptr Pointer to the object */ +/* obj_size Size of the object */ +/* */ +/* OUTPUT */ +/* */ +/* Whether the object is inside the shared memory region. */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Module dispatch check functions */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ +/* */ +/**************************************************************************/ +UINT _txm_module_manager_inside_data_check(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE obj_ptr, UINT obj_size) +{ + +UINT shared_memory_index; +UINT num_shared_memory_mpu_entries; +ALIGN_TYPE shared_memory_address_start; +ALIGN_TYPE shared_memory_address_end; + + /* Check for overflow. */ + if ((obj_ptr) > ((obj_ptr) + (obj_size))) + { + return(TX_FALSE); + } + + /* Check if the object is inside the module data. */ + if ((obj_ptr >= (ALIGN_TYPE) module_instance -> txm_module_instance_data_start) && + ((obj_ptr + obj_size) <= ((ALIGN_TYPE) module_instance -> txm_module_instance_data_end + 1))) + { + return(TX_TRUE); + } + + /* Check if the object is inside the shared memory. */ + num_shared_memory_mpu_entries = module_instance -> txm_module_instance_shared_memory_count; + for (shared_memory_index = 0; shared_memory_index < num_shared_memory_mpu_entries; shared_memory_index++) + { + + shared_memory_address_start = (ALIGN_TYPE) module_instance -> txm_module_instance_shared_memory_address[shared_memory_index]; + shared_memory_address_end = shared_memory_address_start + module_instance -> txm_module_instance_shared_memory_length[shared_memory_index]; + + if ((obj_ptr >= (ALIGN_TYPE) shared_memory_address_start) && + ((obj_ptr + obj_size) <= (ALIGN_TYPE) shared_memory_address_end)) + { + return(TX_TRUE); + } + } + + return(TX_FALSE); } +#endif diff --git a/ports_module/cortex_m7/ac5/module_manager/src/txm_module_manager_thread_stack_build.S b/ports_module/cortex_m4/ac5/module_manager/src/txm_module_manager_thread_stack_build.s index fd99356d..3270f5ae 100644 --- a/ports_module/cortex_m7/ac5/module_manager/src/txm_module_manager_thread_stack_build.S +++ b/ports_module/cortex_m4/ac5/module_manager/src/txm_module_manager_thread_stack_build.s @@ -26,8 +26,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _txm_module_manager_thread_stack_build Cortex-M7/MPU/AC5 */ -/* 6.1.2 */ +/* _txm_module_manager_thread_stack_build Cortex-M4/AC5 */ +/* 6.1.9 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -59,9 +59,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 11-09-2020 Scott Larson Modified comment(s), */ -/* resulting in version 6.1.2 */ +/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ /* */ /**************************************************************************/ // VOID _txm_module_manager_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(TX_THREAD *, TXM_MODULE_INSTANCE *)) @@ -73,7 +71,7 @@ _txm_module_manager_thread_stack_build on the Cortex-M should look like the following after it is built: Stack Top: - LR Interrupted LR (LR at time of PENDSV) + lr Interrupted lr (lr at time of PENDSV) r4 Initial value for r4 r5 Initial value for r5 r6 Initial value for r6 diff --git a/ports_module/cortex_m7/ac5/module_manager/src/txm_module_manager_user_mode_entry.S b/ports_module/cortex_m4/ac5/module_manager/src/txm_module_manager_user_mode_entry.s index d9719c73..38257cf5 100644 --- a/ports_module/cortex_m7/ac5/module_manager/src/txm_module_manager_user_mode_entry.S +++ b/ports_module/cortex_m4/ac5/module_manager/src/txm_module_manager_user_mode_entry.s @@ -10,59 +10,57 @@ /**************************************************************************/ -/**************************************************************************/ -/**************************************************************************/ -/** */ -/** ThreadX Component */ -/** */ -/** Module Manager */ -/** */ -/**************************************************************************/ -/**************************************************************************/ +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ IMPORT _txm_module_manager_kernel_dispatch IMPORT _tx_thread_current_ptr AREA ||.text||, CODE, READONLY, ALIGN=5 THUMB -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* _txm_module_manager_user_mode_entry Cortex-M7/MPU/AC5 */ -/* 6.1.2 */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_user_mode_entry Cortex-M4/AC5 */ +/* 6.1.9 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ /* */ -/* DESCRIPTION */ -/* */ -/* This function allows modules to enter kernel mode. */ -/* */ -/* INPUT */ -/* */ -/* None */ -/* */ -/* OUTPUT */ -/* */ -/* None */ -/* */ -/* CALLS */ -/* */ -/* SVC 1 Enter kernel mode */ -/* SVC 2 Exit kernel mode */ -/* */ -/* CALLED BY */ -/* */ -/* Modules in user mode */ -/* */ -/* RELEASE HISTORY */ -/* */ +/* DESCRIPTION */ +/* */ +/* This function allows modules to enter kernel mode. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* SVC 1 Enter kernel mode */ +/* SVC 2 Exit kernel mode */ +/* */ +/* CALLED BY */ +/* */ +/* Modules in user mode */ +/* */ +/* RELEASE HISTORY */ +/* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 11-09-2020 Scott Larson Modified comment(s), */ -/* resulting in version 6.1.2 */ +/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ /* */ /**************************************************************************/ // VOID _txm_module_manager_user_mode_entry(VOID) diff --git a/ports_module/cortex_m4/ac6/inc/tx_port.h b/ports_module/cortex_m4/ac6/inc/tx_port.h index 7a5a13a1..c4333fc6 100644 --- a/ports_module/cortex_m4/ac6/inc/tx_port.h +++ b/ports_module/cortex_m4/ac6/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h Cortex-M4/AC6 */ -/* 6.1 */ +/* 6.1.9 */ /* */ /* AUTHOR */ /* */ @@ -47,10 +47,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ -/* macro definition, */ -/* resulting in version 6.1.6 */ +/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ /* */ /**************************************************************************/ @@ -142,7 +139,7 @@ typedef unsigned short USHORT; /* Define the port specific options for the _tx_build_options variable. This variable indicates how the ThreadX library was built. */ -#define TX_PORT_SPECIFIC_BUILD_OPTIONS 0 +#define TX_PORT_SPECIFIC_BUILD_OPTIONS (0) /* Define the in-line initialization constant so that modules with in-line @@ -405,6 +402,7 @@ ULONG _tx_misra_ipsr_get(VOID); #define TX_THREAD_SYSTEM_RETURN_CHECK(c) (c) = ((ULONG) _tx_thread_preempt_disable); #endif + /* Define the macro to ensure _tx_thread_preempt_disable is set early in initialization in order to prevent early scheduling on Cortex-M parts. */ @@ -499,7 +497,7 @@ unsigned int interrupt_save; #endif -/* Define FPU extension for the Cortex-M4. Each is assumed to be called in the context of the executing +/* Define FPU extension for the Cortex-M7. Each is assumed to be called in the context of the executing thread. These are no longer needed, but are preserved for backward compatibility only. */ void tx_thread_fpu_enable(void); @@ -510,7 +508,7 @@ void tx_thread_fpu_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M4/AC6 Version 6.1.6 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M4/AC6 Version 6.1.9 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_module/cortex_m4/ac6/inc/txm_module_port.h b/ports_module/cortex_m4/ac6/inc/txm_module_port.h index 0b144b3b..3ffa5087 100644 --- a/ports_module/cortex_m4/ac6/inc/txm_module_port.h +++ b/ports_module/cortex_m4/ac6/inc/txm_module_port.h @@ -25,8 +25,8 @@ /* */ /* APPLICATION INTERFACE DEFINITION RELEASE */ /* */ -/* txm_module_port.h Cortex-M4/MPU/AC6 */ -/* 6.1.6 */ +/* txm_module_port.h Cortex-M4/AC6 */ +/* 6.1.9 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -40,12 +40,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Andres Mlinar Initial Version 6.1 */ -/* 11-09-2020 Scott Larson Modified comment(s), */ -/* resulting in version 6.1.2 */ -/* 04-02-2021 Scott Larson Modified comment(s), */ -/* added check for overflow, */ -/* resulting in version 6.1.6 */ +/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ /* */ /**************************************************************************/ @@ -101,6 +96,21 @@ The following extensions must also be defined in tx_port.h: #define TXM_MODULE_KERNEL_STACK_SIZE 768 #endif +/* For the following 3 access control settings, change TEX and C, B, S (bits 21 through 16 of MPU_RASR) + * to reflect your system memory attributes (cache, shareable, memory type). */ +/* Code region access control: privileged read-only, outer & inner write-back, normal memory, shareable. */ +#ifndef TXM_MODULE_MPU_CODE_ACCESS_CONTROL +#define TXM_MODULE_MPU_CODE_ACCESS_CONTROL 0x06070000 +#endif +/* Data region access control: execute never, read/write, outer & inner write-back, normal memory, shareable. */ +#ifndef TXM_MODULE_MPU_DATA_ACCESS_CONTROL +#define TXM_MODULE_MPU_DATA_ACCESS_CONTROL 0x13070000 +#endif +/* Shared region access control: execute never, read-only, outer & inner write-back, normal memory, shareable. */ +#ifndef TXM_MODULE_MPU_SHARED_ACCESS_CONTROL +#define TXM_MODULE_MPU_SHARED_ACCESS_CONTROL 0x12070000 +#endif + /* Define constants specific to the tools the module can be built with for this particular modules port. */ #define TXM_MODULE_IAR_COMPILER 0x00000000 @@ -155,8 +165,43 @@ The following extensions must also be defined in tx_port.h: #define INLINE_DECLARE inline +#ifdef TXM_MODULE_MANAGER_16_MPU + +/* Define the number of MPU entries assigned to the code and data sections. + On some Cortex-M7 parts, there are 16 total entries. ThreadX uses one for access + to the kernel entry function, thus 15 remain for code and data protection. */ +#define TXM_MODULE_MPU_TOTAL_ENTRIES 16 +#define TXM_MODULE_MPU_CODE_ENTRIES 4 +#define TXM_MODULE_MPU_DATA_ENTRIES 4 +#define TXM_MODULE_MPU_SHARED_ENTRIES 3 + +#define TXM_MODULE_MPU_KERNEL_ENTRY_INDEX 0 +#define TXM_MODULE_MPU_SHARED_INDEX 9 + +#define TXM_ENABLE_REGION 0x01 + +/* There are 2 registers to set up each MPU region: MPU_RBAR, MPU_RASR. */ +typedef struct TXM_MODULE_MPU_INFO_STRUCT +{ + ULONG txm_module_mpu_region_address; + ULONG txm_module_mpu_region_attribute_size; +} TXM_MODULE_MPU_INFO; +/* Shared memory region attributes. */ +#define TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE 1 +#define TXM_MODULE_MANAGER_ATTRIBUTE_WRITE_MPU_BIT 0x01000000 + +/* Define the port-extensions to the module manager instance structure. */ + +#define TXM_MODULE_MANAGER_PORT_EXTENSION \ + TXM_MODULE_MPU_INFO txm_module_instance_mpu_registers[TXM_MODULE_MPU_TOTAL_ENTRIES]; \ + ULONG txm_module_instance_shared_memory_count; \ + ULONG txm_module_instance_shared_memory_address[TXM_MODULE_MPU_SHARED_ENTRIES]; \ + ULONG txm_module_instance_shared_memory_length[TXM_MODULE_MPU_SHARED_ENTRIES]; + +#else /* TXM_MODULE_MANAGER_16_MPU is not defined */ + /* Define the number of MPU entries assigned to the code and data sections. - On Cortex-M4 parts, there are 8 total entries. ThreadX uses one for access + On Cortex-M3, M4, and some M7 parts, there are 8 total entries. ThreadX uses one for access to the kernel entry function, thus 7 remain for code and data protection. */ #define TXM_MODULE_MANAGER_CODE_MPU_ENTRIES 4 #define TXM_MODULE_MANAGER_DATA_MPU_ENTRIES 3 @@ -174,6 +219,7 @@ The following extensions must also be defined in tx_port.h: ULONG txm_module_instance_shared_memory_address; \ ULONG txm_module_instance_shared_memory_length; +#endif /* TXM_MODULE_MANAGER_16_MPU */ /* Define the memory fault information structure that is populated when a memory fault occurs. */ @@ -296,6 +342,10 @@ typedef struct TXM_MODULE_MANAGER_MEMORY_FAULT_INFO_STRUCT /* Define the macros to perform port-specific checks when passing pointers to the kernel. */ /* Define macro to make sure object is inside the module's data. */ +#ifdef TXM_MODULE_MANAGER_16_MPU +#define TXM_MODULE_MANAGER_CHECK_INSIDE_DATA(module_instance, obj_ptr, obj_size) \ + _txm_module_manager_inside_data_check(module_instance, obj_ptr, obj_size) +#else #define TXM_MODULE_MANAGER_CHECK_INSIDE_DATA(module_instance, obj_ptr, obj_size) \ /* Check for overflow. */ \ (((obj_ptr) < ((obj_ptr) + (obj_size))) && \ @@ -305,7 +355,7 @@ typedef struct TXM_MODULE_MANAGER_MEMORY_FAULT_INFO_STRUCT /* Check if it's inside shared memory. */ \ (((obj_ptr) >= (ALIGN_TYPE) module_instance -> txm_module_instance_shared_memory_address) && \ (((obj_ptr) + (obj_size)) <= (ALIGN_TYPE) (module_instance -> txm_module_instance_shared_memory_address + module_instance -> txm_module_instance_shared_memory_length))))) - +#endif /* Define some internal prototypes to this module port. */ @@ -321,10 +371,11 @@ UINT _txm_module_manager_memory_fault_notify(VOID (*notify_function)(TX_THREAD VOID _txm_module_manager_mm_register_setup(TXM_MODULE_INSTANCE *module_instance); \ ULONG _txm_power_of_two_block_size(ULONG size); \ ULONG _txm_module_manager_calculate_srd_bits(ULONG block_size, ULONG length); \ -ULONG _txm_module_manager_region_size_get(ULONG block_size); +ULONG _txm_module_manager_region_size_get(ULONG block_size); \ +UINT _txm_module_manager_inside_data_check(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE obj_ptr, UINT obj_size); #define TXM_MODULE_MANAGER_VERSION_ID \ CHAR _txm_module_manager_version_id[] = \ - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-M4/MPU/AC6 Version 6.1.2 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-M4/AC6 Version 6.1.9 *"; #endif diff --git a/ports_module/cortex_m4/ac6/module_lib/src/txm_module_initialize.S b/ports_module/cortex_m4/ac6/module_lib/src/txm_module_initialize.S index 639c4208..92291782 100644 --- a/ports_module/cortex_m4/ac6/module_lib/src/txm_module_initialize.S +++ b/ports_module/cortex_m4/ac6/module_lib/src/txm_module_initialize.S @@ -32,8 +32,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _txm_module_initialize Cortex-M4/MPU/AC6 */ -/* 6.1.2 */ +/* _txm_module_initialize Cortex-M4/AC6 */ +/* 6.1.9 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -62,9 +62,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Andres Mlinar Initial Version 6.1 */ -/* 11-09-2020 Scott Larson Modified comment(s), */ -/* resulting in version 6.1.2 */ +/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ /* */ /**************************************************************************/ // VOID _txm_module_initialize(VOID) diff --git a/ports_module/cortex_m4/ac6/module_lib/src/txm_module_thread_shell_entry.c b/ports_module/cortex_m4/ac6/module_lib/src/txm_module_thread_shell_entry.c index 1c51577d..2b191899 100644 --- a/ports_module/cortex_m4/ac6/module_lib/src/txm_module_thread_shell_entry.c +++ b/ports_module/cortex_m4/ac6/module_lib/src/txm_module_thread_shell_entry.c @@ -44,7 +44,9 @@ TXM_MODULE_THREAD_ENTRY_INFO *_txm_module_entry_info; ULONG (*_txm_module_kernel_call_dispatcher)(ULONG kernel_request, ULONG param_1, ULONG param_2, ULONG param3); -/* Define the ARM cstartup code. */ +/* Define the startup code that clears the uninitialized global data and sets up the + preset global variables. */ + extern VOID _txm_module_initialize(VOID); @@ -52,15 +54,15 @@ extern VOID _txm_module_initialize(VOID); /* */ /* FUNCTION RELEASE */ /* */ -/* _txm_module_thread_shell_entry Cortex-M4/MPU/AC6 */ -/* 6.1 */ +/* _txm_module_thread_shell_entry Cortex-M4/AC6 */ +/* 6.1.9 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ /* */ /* DESCRIPTION */ /* */ -/* This function calls the specified entry function of the thread. It */ +/* This function calls the specified entry function of the thread. It */ /* also provides a place for the thread's entry function to return. */ /* If the thread returns, this function places the thread in a */ /* "COMPLETED" state. */ @@ -89,7 +91,7 @@ extern VOID _txm_module_initialize(VOID); /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ /* */ /**************************************************************************/ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_ENTRY_INFO *thread_info) @@ -104,7 +106,7 @@ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_EN execution. If not, simply skip the C startup code. */ if (thread_info -> txm_module_thread_entry_info_start_thread) { - /* Initialize the ARM C environment. */ + /* Initialize the C environment. */ _txm_module_initialize(); /* Save the entry info pointer, for later use. */ @@ -169,4 +171,3 @@ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_EN TX_SAFETY_CRITICAL_EXCEPTION(__FILE__, __LINE__, 0); #endif } - diff --git a/ports_module/cortex_m4/ac6/module_manager/src/tx_thread_context_restore.S b/ports_module/cortex_m4/ac6/module_manager/src/tx_thread_context_restore.S index 17a79b0f..6e1fe7cf 100644 --- a/ports_module/cortex_m4/ac6/module_manager/src/tx_thread_context_restore.S +++ b/ports_module/cortex_m4/ac6/module_manager/src/tx_thread_context_restore.S @@ -31,8 +31,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_context_restore Cortex-Mx/AC6 */ -/* 6.1.8 */ +/* _tx_thread_context_restore Cortex-M4/AC6 */ +/* 6.1.7 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -62,7 +62,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ +/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ /* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) diff --git a/ports_module/cortex_m4/ac6/module_manager/src/tx_thread_context_save.S b/ports_module/cortex_m4/ac6/module_manager/src/tx_thread_context_save.S index 511ca82e..15ad1292 100644 --- a/ports_module/cortex_m4/ac6/module_manager/src/tx_thread_context_save.S +++ b/ports_module/cortex_m4/ac6/module_manager/src/tx_thread_context_save.S @@ -30,8 +30,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_context_save Cortex-Mx/AC6 */ -/* 6.1.8 */ +/* _tx_thread_context_save Cortex-M4/AC6 */ +/* 6.1.7 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -61,7 +61,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ +/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ /* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) diff --git a/ports_module/cortex_m4/ac6/module_manager/src/tx_thread_interrupt_control.S b/ports_module/cortex_m4/ac6/module_manager/src/tx_thread_interrupt_control.S index 07d2a131..b79a59c1 100644 --- a/ports_module/cortex_m4/ac6/module_manager/src/tx_thread_interrupt_control.S +++ b/ports_module/cortex_m4/ac6/module_manager/src/tx_thread_interrupt_control.S @@ -27,8 +27,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_interrupt_control Cortex-Mx/AC6 */ -/* 6.1.8 */ +/* _tx_thread_interrupt_control Cortex-M4/AC6 */ +/* 6.1.7 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -58,7 +58,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ +/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ /* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) diff --git a/ports_module/cortex_m4/ac6/module_manager/src/tx_thread_interrupt_disable.S b/ports_module/cortex_m4/ac6/module_manager/src/tx_thread_interrupt_disable.S new file mode 100644 index 00000000..2adec1d8 --- /dev/null +++ b/ports_module/cortex_m4/ac6/module_manager/src/tx_thread_interrupt_disable.S @@ -0,0 +1,79 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + .text 32 + .align 4 + .syntax unified +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_interrupt_disable Cortex-M4/AC6 */ +/* 6.1.7 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is responsible for disabling interrupts and returning */ +/* the previous interrupt lockout posture. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* old_posture Old interrupt lockout posture */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ +/* */ +/**************************************************************************/ +// UINT _tx_thread_interrupt_disable(VOID) +// { + .global _tx_thread_interrupt_disable + .thumb_func +_tx_thread_interrupt_disable: + /* Return current interrupt lockout posture. */ +#ifdef TX_PORT_USE_BASEPRI + MRS r0, BASEPRI + LDR r1, =TX_PORT_BASEPRI + MSR BASEPRI, r1 +#else + MRS r0, PRIMASK + CPSID i +#endif + BX lr +// } diff --git a/ports_module/cortex_m4/ac6/module_manager/src/tx_thread_interrupt_restore.S b/ports_module/cortex_m4/ac6/module_manager/src/tx_thread_interrupt_restore.S new file mode 100644 index 00000000..a920cdbf --- /dev/null +++ b/ports_module/cortex_m4/ac6/module_manager/src/tx_thread_interrupt_restore.S @@ -0,0 +1,76 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + .text 32 + .align 4 + .syntax unified +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_interrupt_restore Cortex-M4/AC6 */ +/* 6.1.7 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is responsible for restoring the previous */ +/* interrupt lockout posture. */ +/* */ +/* INPUT */ +/* */ +/* previous_posture Previous interrupt posture */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ +/* */ +/**************************************************************************/ +// VOID _tx_thread_interrupt_restore(UINT previous_posture) +// { + .global _tx_thread_interrupt_restore + .thumb_func +_tx_thread_interrupt_restore: + /* Restore previous interrupt lockout posture. */ +#ifdef TX_PORT_USE_BASEPRI + MSR BASEPRI, r0 +#else + MSR PRIMASK, r0 +#endif + BX lr +// } diff --git a/ports_module/cortex_m4/ac6/module_manager/src/tx_thread_schedule.S b/ports_module/cortex_m4/ac6/module_manager/src/tx_thread_schedule.S index ff2cd85a..724ed802 100644 --- a/ports_module/cortex_m4/ac6/module_manager/src/tx_thread_schedule.S +++ b/ports_module/cortex_m4/ac6/module_manager/src/tx_thread_schedule.S @@ -41,8 +41,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_schedule Cortex-M4/MPU/AC6 */ -/* 6.1.7 */ +/* _tx_thread_schedule Cortex-M4/AC6 */ +/* 6.1.9 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -75,14 +75,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 11-09-2020 Scott Larson Modified comment(s), arrange */ -/* code to fix link error when */ -/* VFP is enabled, resulting */ -/* in version 6.1.2 */ -/* 06-02-2021 Scott Larson Fixed extended stack handling */ -/* when calling kernel APIs, */ -/* resulting in version 6.1.7 */ +/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ /* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) @@ -109,7 +102,6 @@ _tx_thread_schedule: #endif /* Enable memory fault registers. */ - LDR r0, =0xE000ED24 // Build SHCSR address LDR r1, =0x70000 // Enable Usage, Bus, and MemManage faults STR r1, [r0] // @@ -373,10 +365,21 @@ __tx_ts_restore: // Use alias registers to quickly load MPU ADD r0, r0, #100 // Build address of MPU register start in thread control block +#ifdef TXM_MODULE_MANAGER_16_MPU + LDM r0!,{r2-r9} // Load MPU regions 0-3 + STM r1,{r2-r9} // Store MPU regions 0-3 + LDM r0!,{r2-r9} // Load MPU regions 4-7 + STM r1,{r2-r9} // Store MPU regions 4-7 + LDM r0!,{r2-r9} // Load MPU regions 8-11 + STM r1,{r2-r9} // Store MPU regions 8-11 + LDM r0,{r2-r9} // Load MPU regions 12-15 + STM r1,{r2-r9} // Store MPU regions 12-15 +#else LDM r0!,{r2-r9} // Load first four MPU regions STM r1,{r2-r9} // Store first four MPU regions LDM r0,{r2-r9} // Load second four MPU regions STM r1,{r2-r9} // Store second four MPU regions +#endif LDR r0, =0xE000ED94 // Build MPU control reg address MOV r1, #5 // Build enable value with background region enabled STR r1, [r0] // Enable MPU @@ -446,13 +449,17 @@ __tx_SVCallHandler: #endif MRS r3, PSP // Pickup thread stack pointer +#ifdef __ARM_FP TST lr, #0x10 // Test for extended module stack ITT EQ ORREQ r3, r3, #1 // If so, set LSB in thread stack pointer to indicate extended frame ORREQ lr, lr, #0x10 // Set bit, return with standard frame +#endif STR r3, [r2, #0xB0] // Save thread stack pointer +#ifdef __ARM_FP BIC r3, #1 // Clear possibly OR'd bit - +#endif + /* Build kernel stack by copying thread stack two registers at a time */ ADD r3, r3, #32 // Start at bottom of hardware stack LDMDB r3!, {r1-r2} @@ -522,11 +529,13 @@ _tx_no_lazy_clear: LDR r0, [r2, #0xB0] // Load the module thread stack pointer MRS r3, PSP // Pickup kernel stack pointer +#ifdef __ARM_FP TST r0, #1 // Is module stack extended? ITTE NE // If so... BICNE lr, #0x10 // Clear bit, return with extended frame BICNE r0, #1 // Clear bit that indicates extended module frame ORREQ lr, lr, #0x10 // Else set bit, return with standard frame +#endif /* Copy kernel hardware stack to module thread stack. */ LDM r3!, {r1-r2} @@ -551,7 +560,7 @@ _tx_skip_kernel_stack_exit: BX lr // Return to thread - /* Kernel entry function from user mode. */ + /* Kernel entry function from user mode. */ .global _txm_module_manager_kernel_dispatch .align 5 diff --git a/ports_module/cortex_m4/ac6/module_manager/src/tx_thread_stack_build.S b/ports_module/cortex_m4/ac6/module_manager/src/tx_thread_stack_build.S index d50f9243..5e4eddb2 100644 --- a/ports_module/cortex_m4/ac6/module_manager/src/tx_thread_stack_build.S +++ b/ports_module/cortex_m4/ac6/module_manager/src/tx_thread_stack_build.S @@ -27,8 +27,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_stack_build Cortex-Mx/AC6 */ -/* 6.1.8 */ +/* _tx_thread_stack_build Cortex-M4/AC6 */ +/* 6.1.7 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -60,7 +60,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ +/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ /* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) diff --git a/ports_module/cortex_m4/ac6/module_manager/src/tx_thread_system_return.S b/ports_module/cortex_m4/ac6/module_manager/src/tx_thread_system_return.S index 6560db62..a8b6dc97 100644 --- a/ports_module/cortex_m4/ac6/module_manager/src/tx_thread_system_return.S +++ b/ports_module/cortex_m4/ac6/module_manager/src/tx_thread_system_return.S @@ -27,8 +27,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_system_return Cortex-Mx/AC6 */ -/* 6.1.8 */ +/* _tx_thread_system_return Cortex-M4/AC6 */ +/* 6.1.7 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -60,7 +60,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ +/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ /* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) diff --git a/ports_module/cortex_m4/ac6/module_manager/src/tx_timer_interrupt.S b/ports_module/cortex_m4/ac6/module_manager/src/tx_timer_interrupt.S index 46f54da0..6116f875 100644 --- a/ports_module/cortex_m4/ac6/module_manager/src/tx_timer_interrupt.S +++ b/ports_module/cortex_m4/ac6/module_manager/src/tx_timer_interrupt.S @@ -37,8 +37,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_timer_interrupt Cortex-Mx/AC6 */ -/* 6.1.8 */ +/* _tx_timer_interrupt Cortex-M4/AC6 */ +/* 6.1.7 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -71,7 +71,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ +/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ /* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) diff --git a/ports_module/cortex_m4/ac6/module_manager/src/txm_module_manager_alignment_adjust.c b/ports_module/cortex_m4/ac6/module_manager/src/txm_module_manager_alignment_adjust.c index 09676039..65e04cc1 100644 --- a/ports_module/cortex_m4/ac6/module_manager/src/txm_module_manager_alignment_adjust.c +++ b/ports_module/cortex_m4/ac6/module_manager/src/txm_module_manager_alignment_adjust.c @@ -30,8 +30,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _txm_power_of_two_block_size Cortex-M4/MPU/AC6 */ -/* 6.1 */ +/* _txm_power_of_two_block_size Cortex-M4 */ +/* 6.1.9 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -61,7 +61,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ /* */ /**************************************************************************/ ULONG _txm_power_of_two_block_size(ULONG size) @@ -93,8 +93,8 @@ ULONG _txm_power_of_two_block_size(ULONG size) /* */ /* FUNCTION RELEASE */ /* */ -/* _txm_module_manager_alignment_adjust Cortex-M4/MPU/AC6 */ -/* 6.1 */ +/* _txm_module_manager_alignment_adjust Cortex-M4 */ +/* 6.1.9 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -128,7 +128,7 @@ ULONG _txm_power_of_two_block_size(ULONG size) /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ /* */ /**************************************************************************/ VOID _txm_module_manager_alignment_adjust(TXM_MODULE_PREAMBLE *module_preamble, @@ -137,6 +137,53 @@ VOID _txm_module_manager_alignment_adjust(TXM_MODULE_PREAMBLE *module_preamble, ULONG *data_size, ULONG *data_alignment) { +#ifdef TXM_MODULE_MANAGER_16_MPU +ULONG local_code_size; +ULONG local_code_alignment; +ULONG local_data_size; +ULONG local_data_alignment; +ULONG code_size_accum; +ULONG data_size_accum; + + /* Copy the input parameters into local variables for ease of use. */ + local_code_size = *code_size; + local_code_alignment = *code_alignment; + local_data_size = *data_size; + local_data_alignment = *data_alignment; + + /* Determine code block sizes. Minimize the alignment requirement. + There are 4 MPU code entries available. The following is how the code size + will be distributed: + 1. 1/4 of the largest power of two that is greater than or equal to code size. + 2. 1/4 of the largest power of two that is greater than or equal to code size. + 3. Largest power of 2 that fits in the remaining space. + 4. Smallest power of 2 that exceeds the remaining space, minimum 32. */ + local_code_alignment = _txm_power_of_two_block_size(local_code_size) >> 2; + code_size_accum = local_code_alignment + local_code_alignment; + code_size_accum = code_size_accum + (_txm_power_of_two_block_size(local_code_size - code_size_accum) >> 1); + code_size_accum = code_size_accum + _txm_power_of_two_block_size(local_code_size - code_size_accum); + local_code_size = code_size_accum; + + /* Determine data block sizes. Minimize the alignment requirement. + There are 4 MPU data entries available. The following is how the data size + will be distributed: + 1. 1/4 of the largest power of two that is greater than or equal to data size. + 2. 1/4 of the largest power of two that is greater than or equal to data size. + 3. Largest power of 2 that fits in the remaining space. + 4. Smallest power of 2 that exceeds the remaining space, minimum 32. */ + local_data_alignment = _txm_power_of_two_block_size(local_data_size) >> 2; + data_size_accum = local_data_alignment + local_data_alignment; + data_size_accum = data_size_accum + (_txm_power_of_two_block_size(local_data_size - data_size_accum) >> 1); + data_size_accum = data_size_accum + _txm_power_of_two_block_size(local_data_size - data_size_accum); + local_data_size = data_size_accum; + + /* Return all the information to the caller. */ + *code_size = local_code_size; + *code_alignment = local_code_alignment; + *data_size = local_data_size; + *data_alignment = local_data_alignment; + +#else ULONG local_code_size; ULONG local_code_alignment; @@ -396,4 +443,6 @@ ULONG data_size_accum; *code_alignment = local_code_alignment; *data_size = local_data_size; *data_alignment = local_data_alignment; + +#endif } diff --git a/ports_module/cortex_m4/ac6/module_manager/src/txm_module_manager_external_memory_enable.c b/ports_module/cortex_m4/ac6/module_manager/src/txm_module_manager_external_memory_enable.c index a8b7c14f..79af7655 100644 --- a/ports_module/cortex_m4/ac6/module_manager/src/txm_module_manager_external_memory_enable.c +++ b/ports_module/cortex_m4/ac6/module_manager/src/txm_module_manager_external_memory_enable.c @@ -33,8 +33,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _txm_module_manager_external_memory_enable Cortex-M4/MPU/AC6 */ -/* 6.1 */ +/* _txm_module_manager_external_memory_enable Cortex-M4 */ +/* 6.1.9 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -70,7 +70,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ /* */ /**************************************************************************/ UINT _txm_module_manager_external_memory_enable(TXM_MODULE_INSTANCE *module_instance, @@ -78,6 +78,117 @@ UINT _txm_module_manager_external_memory_enable(TXM_MODULE_INSTANCE *module_ins ULONG length, UINT attributes) { +#ifdef TXM_MODULE_MANAGER_16_MPU +ULONG block_size; +ULONG region_size; +ULONG srd_bits; +ULONG size_register; +ULONG address; +ULONG shared_index; +ULONG attributes_check = 0; + + /* Determine if the module manager has not been initialized yet. */ + if (_txm_module_manager_ready != TX_TRUE) + { + /* Module manager has not been initialized. */ + return(TX_NOT_AVAILABLE); + } + + /* Determine if the module is valid. */ + if (module_instance == TX_NULL) + { + /* Invalid module pointer. */ + return(TX_PTR_ERROR); + } + + /* Get module manager protection mutex. */ + _tx_mutex_get(&_txm_module_manager_mutex, TX_WAIT_FOREVER); + + /* Determine if the module instance is valid. */ + if (module_instance -> txm_module_instance_id != TXM_MODULE_ID) + { + /* Release the protection mutex. */ + _tx_mutex_put(&_txm_module_manager_mutex); + + /* Invalid module pointer. */ + return(TX_PTR_ERROR); + } + + /* Determine if the module instance is in the loaded state. */ + if (module_instance -> txm_module_instance_state != TXM_MODULE_LOADED) + { + /* Release the protection mutex. */ + _tx_mutex_put(&_txm_module_manager_mutex); + + /* Return error if the module is not ready. */ + return(TX_START_ERROR); + } + + /* Determine if there are shared memory entries available. */ + if(module_instance -> txm_module_instance_shared_memory_count >= TXM_MODULE_MPU_SHARED_ENTRIES) + { + /* Release the protection mutex. */ + _tx_mutex_put(&_txm_module_manager_mutex); + + /* No more entries available. */ + return(TX_NO_MEMORY); + } + + /* Start address and length must adhere to Cortex-M7 MPU. + The address must align with the block size. */ + + block_size = _txm_power_of_two_block_size(length); + address = (ULONG) start_address; + if(address != (address & ~(block_size - 1))) + { + /* Release the protection mutex. */ + _tx_mutex_put(&_txm_module_manager_mutex); + + /* Return alignment error. */ + return(TXM_MODULE_ALIGNMENT_ERROR); + } + + /* At this point, we have a valid address and block size. + Set up MPU registers. */ + + /* Pick up index into shared memory entries. */ + shared_index = TXM_MODULE_MPU_SHARED_INDEX + module_instance -> txm_module_instance_shared_memory_count; + + /* Save address register with address, MPU region, set Valid bit. */ + module_instance -> txm_module_instance_mpu_registers[shared_index].txm_module_mpu_region_address = address | shared_index | 0x10; + + /* Calculate the region size. */ + region_size = (_txm_module_manager_region_size_get(block_size) << 1); + + /* Calculate the subregion bits. */ + srd_bits = _txm_module_manager_calculate_srd_bits(block_size, length); + + /* Generate SRD, size, and enable attributes. */ + size_register = srd_bits | region_size | TXM_ENABLE_REGION | TXM_MODULE_MPU_SHARED_ACCESS_CONTROL; + + /* Check for optional write attribute. */ + if(attributes & TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE) + { + attributes_check = TXM_MODULE_MANAGER_ATTRIBUTE_WRITE_MPU_BIT; + } + + /* Save attribute-size register. */ + module_instance -> txm_module_instance_mpu_registers[shared_index].txm_module_mpu_region_attribute_size = attributes_check | size_register; + + /* Keep track of shared memory address and length in module instance. */ + module_instance -> txm_module_instance_shared_memory_address[module_instance -> txm_module_instance_shared_memory_count] = address; + module_instance -> txm_module_instance_shared_memory_length[module_instance -> txm_module_instance_shared_memory_count] = length; + + /* Increment counter. */ + module_instance -> txm_module_instance_shared_memory_count++; + + /* Release the protection mutex. */ + _tx_mutex_put(&_txm_module_manager_mutex); + + /* Return success. */ + return(TX_SUCCESS); + +#else ULONG block_size; ULONG region_size; @@ -179,4 +290,6 @@ TXM_MODULE_PREAMBLE *module_preamble; /* Return success. */ return(TX_SUCCESS); + +#endif } diff --git a/ports_module/cortex_m4/ac6/module_manager/src/txm_module_manager_memory_fault_handler.c b/ports_module/cortex_m4/ac6/module_manager/src/txm_module_manager_memory_fault_handler.c index 6468b4cb..47c2b014 100644 --- a/ports_module/cortex_m4/ac6/module_manager/src/txm_module_manager_memory_fault_handler.c +++ b/ports_module/cortex_m4/ac6/module_manager/src/txm_module_manager_memory_fault_handler.c @@ -45,8 +45,8 @@ TXM_MODULE_MANAGER_FAULT_INFO /* */ /* FUNCTION RELEASE */ /* */ -/* _txm_module_manager_memory_fault_handler Cortex-M4/MPU/AC6 */ -/* 6.1 */ +/* _txm_module_manager_memory_fault_handler Cortex-M4 */ +/* 6.1.9 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -76,7 +76,7 @@ TXM_MODULE_MANAGER_FAULT_INFO /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ /* */ /**************************************************************************/ VOID _txm_module_manager_memory_fault_handler(VOID) diff --git a/ports_module/cortex_m4/ac6/module_manager/src/txm_module_manager_memory_fault_notify.c b/ports_module/cortex_m4/ac6/module_manager/src/txm_module_manager_memory_fault_notify.c index f8689bb9..ba5f5bd6 100644 --- a/ports_module/cortex_m4/ac6/module_manager/src/txm_module_manager_memory_fault_notify.c +++ b/ports_module/cortex_m4/ac6/module_manager/src/txm_module_manager_memory_fault_notify.c @@ -38,8 +38,8 @@ extern VOID (*_txm_module_manager_fault_notify)(TX_THREAD *, TXM_MODULE_INSTA /* */ /* FUNCTION RELEASE */ /* */ -/* _txm_module_manager_memory_fault_notify Cortex-M4/MPU/AC6 */ -/* 6.1 */ +/* _txm_module_manager_memory_fault_notify Cortex-M4 */ +/* 6.1.9 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -71,7 +71,7 @@ extern VOID (*_txm_module_manager_fault_notify)(TX_THREAD *, TXM_MODULE_INSTA /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ /* */ /**************************************************************************/ UINT _txm_module_manager_memory_fault_notify(VOID (*notify_function)(TX_THREAD *, TXM_MODULE_INSTANCE *)) diff --git a/ports_module/cortex_m4/ac6/module_manager/src/txm_module_manager_mm_register_setup.c b/ports_module/cortex_m4/ac6/module_manager/src/txm_module_manager_mm_register_setup.c index 78427ab2..dcc8d2aa 100644 --- a/ports_module/cortex_m4/ac6/module_manager/src/txm_module_manager_mm_register_setup.c +++ b/ports_module/cortex_m4/ac6/module_manager/src/txm_module_manager_mm_register_setup.c @@ -30,8 +30,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _txm_module_manager_region_size_get Cortex-M4/MPU */ -/* 6.1 */ +/* _txm_module_manager_region_size_get Cortex-M4 */ +/* 6.1.9 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -61,7 +61,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ /* */ /**************************************************************************/ ULONG _txm_module_manager_region_size_get(ULONG block_size) @@ -152,8 +152,8 @@ ULONG return_value; /* */ /* FUNCTION RELEASE */ /* */ -/* _txm_module_manager_calculate_srd_bits Cortex-M4/MPU/AC6 */ -/* 6.1 */ +/* _txm_module_manager_calculate_srd_bits Cortex-M4 */ +/* 6.1.9 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -184,7 +184,7 @@ ULONG return_value; /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ /* */ /**************************************************************************/ ULONG _txm_module_manager_calculate_srd_bits(ULONG block_size, ULONG length) @@ -230,16 +230,48 @@ UINT srd_bit_index; /* */ /* FUNCTION RELEASE */ /* */ -/* _txm_module_manager_mm_register_setup Cortex-M4/MPU */ -/* 6.1 */ +/* _txm_module_manager_mm_register_setup Cortex-M4 */ +/* 6.1.9 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ /* */ /* DESCRIPTION */ /* */ -/* This function sets up the Cortex-M4 MPU register definitions based */ -/* on the module's memory characteristics. */ +/* This function sets up the MPU register definitions based on the */ +/* module's memory characteristics. */ +/* */ +/* Default MPU layout: */ +/* Entry Description */ +/* 0 Kernel mode entry */ +/* 1 Module code region */ +/* 2 Module code region */ +/* 3 Module code region */ +/* 4 Module code region */ +/* 5 Module data region */ +/* 6 Module data region */ +/* 7 Module data region */ +/* */ +/* If TXM_MODULE_MANAGER_16_MPU is defined, there are 16 MPU slots. */ +/* MPU layout for the Cortex-M7: */ +/* Entry Description */ +/* 0 Kernel mode entry */ +/* 1 Module code region */ +/* 2 Module code region */ +/* 3 Module code region */ +/* 4 Module code region */ +/* 5 Module data region */ +/* 6 Module data region */ +/* 7 Module data region */ +/* 8 Module data region */ +/* 9 Module shared memory region */ +/* 10 Module shared memory region */ +/* 11 Module shared memory region */ +/* 12 Unused region */ +/* 13 Unused region */ +/* 14 Unused region */ +/* 15 Unused region */ +/* */ /* */ /* INPUT */ /* */ @@ -261,11 +293,181 @@ UINT srd_bit_index; /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ /* */ /**************************************************************************/ VOID _txm_module_manager_mm_register_setup(TXM_MODULE_INSTANCE *module_instance) { +#ifdef TXM_MODULE_MANAGER_16_MPU + +ULONG code_address; +ULONG code_size; +ULONG data_address; +ULONG data_size; +ULONG start_stop_stack_size; +ULONG callback_stack_size; +ULONG block_size; +ULONG region_size; +ULONG srd_bits = 0; +UINT mpu_table_index; +UINT i; + + + /* Setup the first MPU region for kernel mode entry. */ + /* Set address register to user mode entry function address, which is guaranteed to be at least 32-byte aligned. + Mask address to proper range, region 0, set Valid bit. */ + module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MPU_KERNEL_ENTRY_INDEX].txm_module_mpu_region_address = ((ULONG) _txm_module_manager_user_mode_entry & 0xFFFFFFE0) | 0x10; + /* Set the attributes, size (32 bytes) and enable bit. */ + module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MPU_KERNEL_ENTRY_INDEX].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_CODE_ACCESS_CONTROL | (_txm_module_manager_region_size_get(32) << 1) | TXM_ENABLE_REGION; + /* End of kernel mode entry setup. */ + + /* Setup code protection. */ + + /* Initialize the MPU table index. */ + mpu_table_index = 1; + + /* Pickup code starting address and actual size. */ + code_address = (ULONG) module_instance -> txm_module_instance_code_start; + code_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_code_size; + + /* Determine code block sizes. Minimize the alignment requirement. + There are 4 MPU code entries available. The following is how the code size + will be distributed: + 1. 1/4 of the largest power of two that is greater than or equal to code size. + 2. 1/4 of the largest power of two that is greater than or equal to code size. + 3. Largest power of 2 that fits in the remaining space. + 4. Smallest power of 2 that exceeds the remaining space, minimum 32. */ + + /* Now loop through to setup MPU protection for the code area. */ + for (i = 0; i < TXM_MODULE_MPU_CODE_ENTRIES; i++) + { + /* First two MPU blocks are 1/4 of the largest power of two + that is greater than or equal to code size. */ + if (i < 2) + { + block_size = _txm_power_of_two_block_size(code_size) >> 2; + } + + /* Third MPU block is the largest power of 2 that fits in the remaining space. */ + else if (i == 2) + { + /* Subtract (block_size*2) from code_size to calculate remaining space. */ + code_size = code_size - (block_size << 1); + block_size = _txm_power_of_two_block_size(code_size) >> 1; + } + + /* Last MPU block is the smallest power of 2 that exceeds the remaining space, minimum 32. */ + else + { + /* Calculate remaining space. */ + code_size = code_size - block_size; + block_size = _txm_power_of_two_block_size(code_size); + srd_bits = _txm_module_manager_calculate_srd_bits(block_size, code_size); + } + + /* Calculate the region size information. */ + region_size = (_txm_module_manager_region_size_get(block_size) << 1); + + /* Build the base address register with address, MPU region, set Valid bit. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_address = (code_address & ~(block_size - 1)) | mpu_table_index | 0x10; + /* Build the attribute-size register with permissions, SRD, size, enable. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_CODE_ACCESS_CONTROL | srd_bits | region_size | TXM_ENABLE_REGION; + + /* Adjust the code address. */ + code_address = code_address + block_size; + + /* Increment MPU table index. */ + mpu_table_index++; + } + /* End of code protection. */ + + /* Setup data protection. */ + + /* Reset SRD bitfield. */ + srd_bits = 0; + + /* Pickup data starting address and actual size. */ + data_address = (ULONG) module_instance -> txm_module_instance_data_start; + + /* Adjust the size of the module elements to be aligned to the default alignment. We do this + so that when we partition the allocated memory, we can simply place these regions right beside + each other without having to align their pointers. Note this only works when they all have + the same alignment. */ + + data_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_data_size; + start_stop_stack_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_start_stop_stack_size; + callback_stack_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_callback_stack_size; + + data_size = ((data_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; + + start_stop_stack_size = ((start_stop_stack_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; + + callback_stack_size = ((callback_stack_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; + + /* Update the data size to include thread stacks. */ + data_size = data_size + start_stop_stack_size + callback_stack_size; + + /* Determine data block sizes. Minimize the alignment requirement. + There are 4 MPU data entries available. The following is how the data size + will be distributed: + 1. 1/4 of the largest power of two that is greater than or equal to data size. + 2. 1/4 of the largest power of two that is greater than or equal to data size. + 3. Largest power of 2 that fits in the remaining space. + 4. Smallest power of 2 that exceeds the remaining space, minimum 32. */ + + /* Now loop through to setup MPU protection for the data area. */ + for (i = 0; i < TXM_MODULE_MPU_DATA_ENTRIES; i++) + { + /* First two MPU blocks are 1/4 of the largest power of two + that is greater than or equal to data size. */ + if (i < 2) + { + block_size = _txm_power_of_two_block_size(data_size) >> 2; + } + + /* Third MPU block is the largest power of 2 that fits in the remaining space. */ + else if (i == 2) + { + /* Subtract (block_size*2) from data_size to calculate remaining space. */ + data_size = data_size - (block_size << 1); + block_size = _txm_power_of_two_block_size(data_size) >> 1; + } + + /* Last MPU block is the smallest power of 2 that exceeds the remaining space, minimum 32. */ + else + { + /* Calculate remaining space. */ + data_size = data_size - block_size; + block_size = _txm_power_of_two_block_size(data_size); + srd_bits = _txm_module_manager_calculate_srd_bits(block_size, data_size); + } + + /* Calculate the region size information. */ + region_size = (_txm_module_manager_region_size_get(block_size) << 1); + + /* Build the base address register with address, MPU region, set Valid bit. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_address = (data_address & ~(block_size - 1)) | mpu_table_index | 0x10; + /* Build the attribute-size register with permissions, SRD, size, enable. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_DATA_ACCESS_CONTROL | srd_bits | region_size | TXM_ENABLE_REGION; + + /* Adjust the data address. */ + data_address = data_address + block_size; + + /* Increment MPU table index. */ + mpu_table_index++; + } + + /* Setup MPU for the remaining regions. */ + while (mpu_table_index < TXM_MODULE_MPU_TOTAL_ENTRIES) + { + /* Build the base address register with address, MPU region, set Valid bit. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_address = mpu_table_index | 0x10; + + /* Increment MPU table index. */ + mpu_table_index++; + } + +#else ULONG code_address; ULONG code_size; @@ -382,7 +584,7 @@ UINT i; for (i = 0; i < TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1; i++) { /* Build the base address register. */ - base_address_register = code_address & ~(block_size - 1) | mpu_register | 0x10; + base_address_register = (code_address & ~(block_size - 1)) | mpu_register | 0x10; /* Check if SRD bits need to be set. */ if (code_size < block_size) @@ -509,4 +711,87 @@ UINT i; /* Increment the MPU register index. */ mpu_register++; } + +#endif +} + +#ifdef TXM_MODULE_MANAGER_16_MPU +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_inside_data_check Cortex-M4 */ +/* 6.1.9 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks if the specified object is inside shared */ +/* memory. */ +/* */ +/* INPUT */ +/* */ +/* module_instance Pointer to module instance */ +/* obj_ptr Pointer to the object */ +/* obj_size Size of the object */ +/* */ +/* OUTPUT */ +/* */ +/* Whether the object is inside the shared memory region. */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Module dispatch check functions */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ +/* */ +/**************************************************************************/ +UINT _txm_module_manager_inside_data_check(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE obj_ptr, UINT obj_size) +{ + +UINT shared_memory_index; +UINT num_shared_memory_mpu_entries; +ALIGN_TYPE shared_memory_address_start; +ALIGN_TYPE shared_memory_address_end; + + /* Check for overflow. */ + if ((obj_ptr) > ((obj_ptr) + (obj_size))) + { + return(TX_FALSE); + } + + /* Check if the object is inside the module data. */ + if ((obj_ptr >= (ALIGN_TYPE) module_instance -> txm_module_instance_data_start) && + ((obj_ptr + obj_size) <= ((ALIGN_TYPE) module_instance -> txm_module_instance_data_end + 1))) + { + return(TX_TRUE); + } + + /* Check if the object is inside the shared memory. */ + num_shared_memory_mpu_entries = module_instance -> txm_module_instance_shared_memory_count; + for (shared_memory_index = 0; shared_memory_index < num_shared_memory_mpu_entries; shared_memory_index++) + { + + shared_memory_address_start = (ALIGN_TYPE) module_instance -> txm_module_instance_shared_memory_address[shared_memory_index]; + shared_memory_address_end = shared_memory_address_start + module_instance -> txm_module_instance_shared_memory_length[shared_memory_index]; + + if ((obj_ptr >= (ALIGN_TYPE) shared_memory_address_start) && + ((obj_ptr + obj_size) <= (ALIGN_TYPE) shared_memory_address_end)) + { + return(TX_TRUE); + } + } + + return(TX_FALSE); } +#endif diff --git a/ports_module/cortex_m4/ac6/module_manager/src/txm_module_manager_thread_stack_build.S b/ports_module/cortex_m4/ac6/module_manager/src/txm_module_manager_thread_stack_build.S index 7812baf3..121e0c35 100644 --- a/ports_module/cortex_m4/ac6/module_manager/src/txm_module_manager_thread_stack_build.S +++ b/ports_module/cortex_m4/ac6/module_manager/src/txm_module_manager_thread_stack_build.S @@ -27,8 +27,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _txm_module_manager_thread_stack_build Cortex-M4/MPU/AC6 */ -/* 6.1.2 */ +/* _txm_module_manager_thread_stack_build Cortex-M4/AC6 */ +/* 6.1.9 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -60,9 +60,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 11-09-2020 Scott Larson Modified comment(s), */ -/* resulting in version 6.1.2 */ +/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ /* */ /**************************************************************************/ // VOID _txm_module_manager_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(TX_THREAD *, TXM_MODULE_INSTANCE *)) @@ -112,7 +110,7 @@ _txm_module_manager_thread_stack_build: STR r3, [r2, #28] // Store initial r10 STR r3, [r2, #32] // Store initial r11 - /* Hardware stack follows. */ + /* Hardware stack follows. */ STR r0, [r2, #36] // Store initial r0, which is the thread control block diff --git a/ports_module/cortex_m4/gnu/inc/tx_port.h b/ports_module/cortex_m4/gnu/inc/tx_port.h index 4c67e788..986d5051 100644 --- a/ports_module/cortex_m4/gnu/inc/tx_port.h +++ b/ports_module/cortex_m4/gnu/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h Cortex-M4/GNU */ -/* 6.1 */ +/* 6.1.9 */ /* */ /* AUTHOR */ /* */ @@ -47,10 +47,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ -/* macro definition, */ -/* resulting in version 6.1.6 */ +/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ /* */ /**************************************************************************/ @@ -116,7 +113,7 @@ typedef unsigned short USHORT; #endif -/* Define various constants for the ThreadX Cortex-M7 port. */ +/* Define various constants for the ThreadX Cortex-M4 port. */ #define TX_INT_DISABLE 1 /* Disable interrupts */ #define TX_INT_ENABLE 0 /* Enable interrupts */ @@ -142,7 +139,7 @@ typedef unsigned short USHORT; /* Define the port specific options for the _tx_build_options variable. This variable indicates how the ThreadX library was built. */ -#define TX_PORT_SPECIFIC_BUILD_OPTIONS 0 +#define TX_PORT_SPECIFIC_BUILD_OPTIONS (0) /* Define the in-line initialization constant so that modules with in-line @@ -218,7 +215,6 @@ typedef unsigned short USHORT; #define TX_THREAD_CREATE_EXTENSION(thread_ptr) #define TX_THREAD_DELETE_EXTENSION(thread_ptr) - #ifdef TX_ENABLE_FPU_SUPPORT @@ -354,8 +350,6 @@ __attribute__( ( always_inline ) ) static inline void __set_control(ULONG contro #endif - - /* Define the ThreadX object creation extensions for the remaining objects. */ #define TX_BLOCK_POOL_CREATE_EXTENSION(pool_ptr) @@ -408,6 +402,7 @@ ULONG _tx_misra_ipsr_get(VOID); #define TX_THREAD_SYSTEM_RETURN_CHECK(c) (c) = ((ULONG) _tx_thread_preempt_disable); #endif + /* Define the macro to ensure _tx_thread_preempt_disable is set early in initialization in order to prevent early scheduling on Cortex-M parts. */ @@ -496,8 +491,8 @@ unsigned int interrupt_save; #endif -/* Define FPU extension for the Cortex-M4. Each is assumed to be called in the context of the executing - thread. This is for legacy only, and not needed anylonger. */ +/* Define FPU extension for the Cortex-M7. Each is assumed to be called in the context of the executing + thread. This is for legacy only, and not needed any longer. */ void tx_thread_fpu_enable(void); void tx_thread_fpu_disable(void); @@ -507,15 +502,10 @@ void tx_thread_fpu_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M4/GNU Version 6.1.6 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M4/GNU Version 6.1.9 *"; #else extern CHAR _tx_version_id[]; #endif #endif - - - - - diff --git a/ports_module/cortex_m4/gnu/inc/txm_module_port.h b/ports_module/cortex_m4/gnu/inc/txm_module_port.h index 68419fc1..f48c9620 100644 --- a/ports_module/cortex_m4/gnu/inc/txm_module_port.h +++ b/ports_module/cortex_m4/gnu/inc/txm_module_port.h @@ -25,8 +25,8 @@ /* */ /* APPLICATION INTERFACE DEFINITION RELEASE */ /* */ -/* txm_module_port.h Cortex-M4/MPU/GNU */ -/* 6.1.6 */ +/* txm_module_port.h Cortex-M4/GNU */ +/* 6.1.9 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -40,12 +40,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 11-09-2020 Scott Larson Modified comment(s), */ -/* resulting in version 6.1.2 */ -/* 04-02-2021 Scott Larson Modified comment(s), */ -/* added check for overflow, */ -/* resulting in version 6.1.6 */ +/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ /* */ /**************************************************************************/ @@ -101,6 +96,21 @@ The following extensions must also be defined in tx_port.h: #define TXM_MODULE_KERNEL_STACK_SIZE 768 #endif +/* For the following 3 access control settings, change TEX and C, B, S (bits 21 through 16 of MPU_RASR) + * to reflect your system memory attributes (cache, shareable, memory type). */ +/* Code region access control: privileged read-only, outer & inner write-back, normal memory, shareable. */ +#ifndef TXM_MODULE_MPU_CODE_ACCESS_CONTROL +#define TXM_MODULE_MPU_CODE_ACCESS_CONTROL 0x06070000 +#endif +/* Data region access control: execute never, read/write, outer & inner write-back, normal memory, shareable. */ +#ifndef TXM_MODULE_MPU_DATA_ACCESS_CONTROL +#define TXM_MODULE_MPU_DATA_ACCESS_CONTROL 0x13070000 +#endif +/* Shared region access control: execute never, read-only, outer & inner write-back, normal memory, shareable. */ +#ifndef TXM_MODULE_MPU_SHARED_ACCESS_CONTROL +#define TXM_MODULE_MPU_SHARED_ACCESS_CONTROL 0x12070000 +#endif + /* Define constants specific to the tools the module can be built with for this particular modules port. */ #define TXM_MODULE_IAR_COMPILER 0x00000000 @@ -155,8 +165,43 @@ The following extensions must also be defined in tx_port.h: #define INLINE_DECLARE inline +#ifdef TXM_MODULE_MANAGER_16_MPU + +/* Define the number of MPU entries assigned to the code and data sections. + On some Cortex-M7 parts, there are 16 total entries. ThreadX uses one for access + to the kernel entry function, thus 15 remain for code and data protection. */ +#define TXM_MODULE_MPU_TOTAL_ENTRIES 16 +#define TXM_MODULE_MPU_CODE_ENTRIES 4 +#define TXM_MODULE_MPU_DATA_ENTRIES 4 +#define TXM_MODULE_MPU_SHARED_ENTRIES 3 + +#define TXM_MODULE_MPU_KERNEL_ENTRY_INDEX 0 +#define TXM_MODULE_MPU_SHARED_INDEX 9 + +#define TXM_ENABLE_REGION 0x01 + +/* There are 2 registers to set up each MPU region: MPU_RBAR, MPU_RASR. */ +typedef struct TXM_MODULE_MPU_INFO_STRUCT +{ + ULONG txm_module_mpu_region_address; + ULONG txm_module_mpu_region_attribute_size; +} TXM_MODULE_MPU_INFO; +/* Shared memory region attributes. */ +#define TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE 1 +#define TXM_MODULE_MANAGER_ATTRIBUTE_WRITE_MPU_BIT 0x01000000 + +/* Define the port-extensions to the module manager instance structure. */ + +#define TXM_MODULE_MANAGER_PORT_EXTENSION \ + TXM_MODULE_MPU_INFO txm_module_instance_mpu_registers[TXM_MODULE_MPU_TOTAL_ENTRIES]; \ + ULONG txm_module_instance_shared_memory_count; \ + ULONG txm_module_instance_shared_memory_address[TXM_MODULE_MPU_SHARED_ENTRIES]; \ + ULONG txm_module_instance_shared_memory_length[TXM_MODULE_MPU_SHARED_ENTRIES]; + +#else /* TXM_MODULE_MANAGER_16_MPU is not defined */ + /* Define the number of MPU entries assigned to the code and data sections. - On Cortex-M4 parts, there are 8 total entries. ThreadX uses one for access + On Cortex-M3, M4, and some M7 parts, there are 8 total entries. ThreadX uses one for access to the kernel entry function, thus 7 remain for code and data protection. */ #define TXM_MODULE_MANAGER_CODE_MPU_ENTRIES 4 #define TXM_MODULE_MANAGER_DATA_MPU_ENTRIES 3 @@ -174,6 +219,7 @@ The following extensions must also be defined in tx_port.h: ULONG txm_module_instance_shared_memory_address; \ ULONG txm_module_instance_shared_memory_length; +#endif /* TXM_MODULE_MANAGER_16_MPU */ /* Define the memory fault information structure that is populated when a memory fault occurs. */ @@ -296,6 +342,10 @@ typedef struct TXM_MODULE_MANAGER_MEMORY_FAULT_INFO_STRUCT /* Define the macros to perform port-specific checks when passing pointers to the kernel. */ /* Define macro to make sure object is inside the module's data. */ +#ifdef TXM_MODULE_MANAGER_16_MPU +#define TXM_MODULE_MANAGER_CHECK_INSIDE_DATA(module_instance, obj_ptr, obj_size) \ + _txm_module_manager_inside_data_check(module_instance, obj_ptr, obj_size) +#else #define TXM_MODULE_MANAGER_CHECK_INSIDE_DATA(module_instance, obj_ptr, obj_size) \ /* Check for overflow. */ \ (((obj_ptr) < ((obj_ptr) + (obj_size))) && \ @@ -305,7 +355,7 @@ typedef struct TXM_MODULE_MANAGER_MEMORY_FAULT_INFO_STRUCT /* Check if it's inside shared memory. */ \ (((obj_ptr) >= (ALIGN_TYPE) module_instance -> txm_module_instance_shared_memory_address) && \ (((obj_ptr) + (obj_size)) <= (ALIGN_TYPE) (module_instance -> txm_module_instance_shared_memory_address + module_instance -> txm_module_instance_shared_memory_length))))) - +#endif /* Define some internal prototypes to this module port. */ @@ -321,10 +371,11 @@ UINT _txm_module_manager_memory_fault_notify(VOID (*notify_function)(TX_THREAD VOID _txm_module_manager_mm_register_setup(TXM_MODULE_INSTANCE *module_instance); \ ULONG _txm_power_of_two_block_size(ULONG size); \ ULONG _txm_module_manager_calculate_srd_bits(ULONG block_size, ULONG length); \ -ULONG _txm_module_manager_region_size_get(ULONG block_size); +ULONG _txm_module_manager_region_size_get(ULONG block_size); \ +UINT _txm_module_manager_inside_data_check(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE obj_ptr, UINT obj_size); #define TXM_MODULE_MANAGER_VERSION_ID \ CHAR _txm_module_manager_version_id[] = \ - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-M4/MPU/GNU Version 6.1.2 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-M4/GNU Version 6.1.9 *"; #endif diff --git a/ports_module/cortex_m4/gnu/module_lib/src/txm_module_thread_shell_entry.c b/ports_module/cortex_m4/gnu/module_lib/src/txm_module_thread_shell_entry.c index 36f6adb7..e745f914 100644 --- a/ports_module/cortex_m4/gnu/module_lib/src/txm_module_thread_shell_entry.c +++ b/ports_module/cortex_m4/gnu/module_lib/src/txm_module_thread_shell_entry.c @@ -44,7 +44,7 @@ TXM_MODULE_THREAD_ENTRY_INFO *_txm_module_entry_info; ULONG (*_txm_module_kernel_call_dispatcher)(ULONG kernel_request, ULONG param_1, ULONG param_2, ULONG param3); -/* Define the GCC startup code that clears the uninitialized global data and sets up the +/* Define the startup code that clears the uninitialized global data and sets up the preset global variables. */ extern VOID _gcc_setup(TXM_MODULE_INSTANCE *); @@ -54,15 +54,15 @@ extern VOID _gcc_setup(TXM_MODULE_INSTANCE *); /* */ /* FUNCTION RELEASE */ /* */ -/* _txm_module_thread_shell_entry Cortex-M4/MPU/GNU */ -/* 6.1 */ +/* _txm_module_thread_shell_entry Cortex-M4/GNU */ +/* 6.1.9 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ /* */ /* DESCRIPTION */ /* */ -/* This function calls the specified entry function of the thread. It */ +/* This function calls the specified entry function of the thread. It */ /* also provides a place for the thread's entry function to return. */ /* If the thread returns, this function places the thread in a */ /* "COMPLETED" state. */ @@ -78,7 +78,7 @@ extern VOID _gcc_setup(TXM_MODULE_INSTANCE *); /* */ /* CALLS */ /* */ -/* _gcc_setup GNU global init function */ +/* _gcc_setup cstartup initialization */ /* thread_entry Thread's entry function */ /* tx_thread_resume Resume the module callback thread */ /* _txm_module_thread_system_suspend Module thread suspension routine */ @@ -91,7 +91,7 @@ extern VOID _gcc_setup(TXM_MODULE_INSTANCE *); /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ /* */ /**************************************************************************/ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_ENTRY_INFO *thread_info) @@ -106,7 +106,7 @@ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_EN execution. If not, simply skip the C startup code. */ if (thread_info -> txm_module_thread_entry_info_start_thread) { - /* Initialize the GNU C environment. */ + /* Initialize the C environment. */ _gcc_setup(thread_info -> txm_module_thread_entry_info_code_base_address); /* Save the entry info pointer, for later use. */ @@ -171,4 +171,3 @@ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_EN TX_SAFETY_CRITICAL_EXCEPTION(__FILE__, __LINE__, 0); #endif } - diff --git a/ports_module/cortex_m4/gnu/module_manager/src/tx_thread_context_restore.S b/ports_module/cortex_m4/gnu/module_manager/src/tx_thread_context_restore.S index e445e690..852d8302 100644 --- a/ports_module/cortex_m4/gnu/module_manager/src/tx_thread_context_restore.S +++ b/ports_module/cortex_m4/gnu/module_manager/src/tx_thread_context_restore.S @@ -31,8 +31,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_context_restore Cortex-Mx/GNU */ -/* 6.1.8 */ +/* _tx_thread_context_restore Cortex-M4/GNU */ +/* 6.1.7 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -62,7 +62,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ +/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ /* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) diff --git a/ports_module/cortex_m4/gnu/module_manager/src/tx_thread_context_save.S b/ports_module/cortex_m4/gnu/module_manager/src/tx_thread_context_save.S index e4f2778a..1c8a2ebf 100644 --- a/ports_module/cortex_m4/gnu/module_manager/src/tx_thread_context_save.S +++ b/ports_module/cortex_m4/gnu/module_manager/src/tx_thread_context_save.S @@ -27,8 +27,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_context_save Cortex-Mx/GNU */ -/* 6.1.8 */ +/* _tx_thread_context_save Cortex-M4/GNU */ +/* 6.1.7 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -58,7 +58,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ +/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ /* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) diff --git a/ports_module/cortex_m4/gnu/module_manager/src/tx_thread_interrupt_control.S b/ports_module/cortex_m4/gnu/module_manager/src/tx_thread_interrupt_control.S index 99e14c06..30960b56 100644 --- a/ports_module/cortex_m4/gnu/module_manager/src/tx_thread_interrupt_control.S +++ b/ports_module/cortex_m4/gnu/module_manager/src/tx_thread_interrupt_control.S @@ -27,8 +27,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_interrupt_control Cortex-Mx/GNU */ -/* 6.1.8 */ +/* _tx_thread_interrupt_control Cortex-M4/GNU */ +/* 6.1.7 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -58,7 +58,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ +/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ /* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) diff --git a/ports_module/cortex_m4/gnu/module_manager/src/tx_thread_interrupt_disable.S b/ports_module/cortex_m4/gnu/module_manager/src/tx_thread_interrupt_disable.S new file mode 100644 index 00000000..d2945f08 --- /dev/null +++ b/ports_module/cortex_m4/gnu/module_manager/src/tx_thread_interrupt_disable.S @@ -0,0 +1,79 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + .text 32 + .align 4 + .syntax unified +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_interrupt_disable Cortex-M4/GNU */ +/* 6.1.7 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is responsible for disabling interrupts and returning */ +/* the previous interrupt lockout posture. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* old_posture Old interrupt lockout posture */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ +/* */ +/**************************************************************************/ +// UINT _tx_thread_interrupt_disable(VOID) +// { + .global _tx_thread_interrupt_disable + .thumb_func +_tx_thread_interrupt_disable: + /* Return current interrupt lockout posture. */ +#ifdef TX_PORT_USE_BASEPRI + MRS r0, BASEPRI + LDR r1, =TX_PORT_BASEPRI + MSR BASEPRI, r1 +#else + MRS r0, PRIMASK + CPSID i +#endif + BX lr +// } diff --git a/ports_module/cortex_m4/gnu/module_manager/src/tx_thread_interrupt_restore.S b/ports_module/cortex_m4/gnu/module_manager/src/tx_thread_interrupt_restore.S new file mode 100644 index 00000000..a2efd882 --- /dev/null +++ b/ports_module/cortex_m4/gnu/module_manager/src/tx_thread_interrupt_restore.S @@ -0,0 +1,76 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + .text 32 + .align 4 + .syntax unified +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_interrupt_restore Cortex-M4/GNU */ +/* 6.1.7 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is responsible for restoring the previous */ +/* interrupt lockout posture. */ +/* */ +/* INPUT */ +/* */ +/* previous_posture Previous interrupt posture */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ +/* */ +/**************************************************************************/ +// VOID _tx_thread_interrupt_restore(UINT previous_posture) +// { + .global _tx_thread_interrupt_restore + .thumb_func +_tx_thread_interrupt_restore: + /* Restore previous interrupt lockout posture. */ +#ifdef TX_PORT_USE_BASEPRI + MSR BASEPRI, r0 +#else + MSR PRIMASK, r0 +#endif + BX lr +// } diff --git a/ports_module/cortex_m4/gnu/module_manager/src/tx_thread_schedule.S b/ports_module/cortex_m4/gnu/module_manager/src/tx_thread_schedule.S index 8716a253..217a8f60 100644 --- a/ports_module/cortex_m4/gnu/module_manager/src/tx_thread_schedule.S +++ b/ports_module/cortex_m4/gnu/module_manager/src/tx_thread_schedule.S @@ -39,8 +39,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_schedule Cortex-M4/MPU/GNU */ -/* 6.1.7 */ +/* _tx_thread_schedule Cortex-M4/GNU */ +/* 6.1.9 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -73,14 +73,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 11-09-2020 Scott Larson Modified comment(s), arrange */ -/* code to fix link error when */ -/* VFP is enabled, resulting */ -/* in version 6.1.2 */ -/* 06-02-2021 Scott Larson Fixed extended stack handling */ -/* when calling kernel APIs, */ -/* resulting in version 6.1.7 */ +/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ /* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) @@ -99,16 +92,14 @@ _tx_thread_schedule: LDR r2, =_tx_thread_preempt_disable // Build address of preempt disable flag STR r0, [r2, #0] // Clear preempt disable flag - /* Clear CONTROL.FPCA bit so VFP registers aren't unnecessarily stacked. */ - #ifdef __ARM_PCS_VFP + /* Clear CONTROL.FPCA bit so VFP registers aren't unnecessarily stacked. */ MRS r0, CONTROL // Pickup current CONTROL register BIC r0, r0, #4 // Clear the FPCA bit MSR CONTROL, r0 // Setup new CONTROL register #endif /* Enable memory fault registers. */ - LDR r0, =0xE000ED24 // Build SHCSR address LDR r1, =0x70000 // Enable Usage, Bus, and MemManage faults STR r1, [r0] // @@ -372,10 +363,21 @@ __tx_ts_restore: // Use alias registers to quickly load MPU ADD r0, r0, #100 // Build address of MPU register start in thread control block +#ifdef TXM_MODULE_MANAGER_16_MPU + LDM r0!,{r2-r9} // Load MPU regions 0-3 + STM r1,{r2-r9} // Store MPU regions 0-3 + LDM r0!,{r2-r9} // Load MPU regions 4-7 + STM r1,{r2-r9} // Store MPU regions 4-7 + LDM r0!,{r2-r9} // Load MPU regions 8-11 + STM r1,{r2-r9} // Store MPU regions 8-11 + LDM r0,{r2-r9} // Load MPU regions 12-15 + STM r1,{r2-r9} // Store MPU regions 12-15 +#else LDM r0!,{r2-r9} // Load first four MPU regions STM r1,{r2-r9} // Store first four MPU regions LDM r0,{r2-r9} // Load second four MPU regions STM r1,{r2-r9} // Store second four MPU regions +#endif LDR r0, =0xE000ED94 // Build MPU control reg address MOV r1, #5 // Build enable value with background region enabled STR r1, [r0] // Enable MPU @@ -446,12 +448,16 @@ __tx_SVCallHandler: #endif MRS r3, PSP // Pickup thread stack pointer +#ifdef __ARM_PCS_VFP TST lr, #0x10 // Test for extended module stack ITT EQ ORREQ r3, r3, #1 // If so, set LSB in thread stack pointer to indicate extended frame ORREQ lr, lr, #0x10 // Set bit, return with standard frame +#endif STR r3, [r2, #0xB0] // Save thread stack pointer +#ifdef __ARM_PCS_VFP BIC r3, #1 // Clear possibly OR'd bit +#endif /* Build kernel stack by copying thread stack two registers at a time */ ADD r3, r3, #32 // Start at bottom of hardware stack @@ -498,6 +504,7 @@ _tx_thread_user_return: STR r3, [r2, #20] // Set stack size #endif +#ifdef __ARM_PCS_VFP /* If lazy stacking is pending, check if it can be cleared. if(LSPACT && tx_thread_module_stack_start < FPCAR && FPCAR < tx_thread_module_stack_end) then clear LSPACT. */ @@ -517,14 +524,17 @@ _tx_thread_user_return: LDR r1, =0xE000EF34 // Address of FPCCR STR r3, [r1] // Save updated FPCCR _tx_no_lazy_clear: +#endif LDR r0, [r2, #0xB0] // Load the module thread stack pointer MRS r3, PSP // Pickup kernel stack pointer +#ifdef __ARM_PCS_VFP TST r0, #1 // Is module stack extended? ITTE NE // If so... BICNE lr, #0x10 // Clear bit, return with extended frame BICNE r0, #1 // Clear bit that indicates extended module frame ORREQ lr, lr, #0x10 // Else set bit, return with standard frame +#endif /* Copy kernel hardware stack to module thread stack. */ LDM r3!, {r1-r2} @@ -549,7 +559,7 @@ _tx_skip_kernel_stack_exit: BX lr // Return to thread - /* Kernel entry function from user mode. */ + /* Kernel entry function from user mode. */ .global _txm_module_manager_kernel_dispatch .align 5 diff --git a/ports_module/cortex_m4/gnu/module_manager/src/tx_thread_stack_build.S b/ports_module/cortex_m4/gnu/module_manager/src/tx_thread_stack_build.S index d0246c13..536d815b 100644 --- a/ports_module/cortex_m4/gnu/module_manager/src/tx_thread_stack_build.S +++ b/ports_module/cortex_m4/gnu/module_manager/src/tx_thread_stack_build.S @@ -27,8 +27,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_stack_build Cortex-Mx/GNU */ -/* 6.1.8 */ +/* _tx_thread_stack_build Cortex-M4/GNU */ +/* 6.1.7 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -60,7 +60,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ +/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ /* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) diff --git a/ports_module/cortex_m4/gnu/module_manager/src/tx_thread_system_return.S b/ports_module/cortex_m4/gnu/module_manager/src/tx_thread_system_return.S index 1f20e1a6..3783ccd7 100644 --- a/ports_module/cortex_m4/gnu/module_manager/src/tx_thread_system_return.S +++ b/ports_module/cortex_m4/gnu/module_manager/src/tx_thread_system_return.S @@ -27,8 +27,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_system_return Cortex-Mx/GNU */ -/* 6.1.8 */ +/* _tx_thread_system_return Cortex-M4/GNU */ +/* 6.1.7 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -60,7 +60,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ +/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ /* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) diff --git a/ports_module/cortex_m4/gnu/module_manager/src/tx_timer_interrupt.S b/ports_module/cortex_m4/gnu/module_manager/src/tx_timer_interrupt.S index 9551a2b2..810f959e 100644 --- a/ports_module/cortex_m4/gnu/module_manager/src/tx_timer_interrupt.S +++ b/ports_module/cortex_m4/gnu/module_manager/src/tx_timer_interrupt.S @@ -37,8 +37,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_timer_interrupt Cortex-Mx/GNU */ -/* 6.1.8 */ +/* _tx_timer_interrupt Cortex-M4/GNU */ +/* 6.1.7 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -71,7 +71,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ +/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ /* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) diff --git a/ports_module/cortex_m4/gnu/module_manager/src/txm_module_manager_alignment_adjust.c b/ports_module/cortex_m4/gnu/module_manager/src/txm_module_manager_alignment_adjust.c index b6c79053..65e04cc1 100644 --- a/ports_module/cortex_m4/gnu/module_manager/src/txm_module_manager_alignment_adjust.c +++ b/ports_module/cortex_m4/gnu/module_manager/src/txm_module_manager_alignment_adjust.c @@ -30,8 +30,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _txm_power_of_two_block_size Cortex-M4/MPU/GNU */ -/* 6.1 */ +/* _txm_power_of_two_block_size Cortex-M4 */ +/* 6.1.9 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -61,7 +61,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ /* */ /**************************************************************************/ ULONG _txm_power_of_two_block_size(ULONG size) @@ -93,8 +93,8 @@ ULONG _txm_power_of_two_block_size(ULONG size) /* */ /* FUNCTION RELEASE */ /* */ -/* _txm_module_manager_alignment_adjust Cortex-M4/MPU/GNU */ -/* 6.1 */ +/* _txm_module_manager_alignment_adjust Cortex-M4 */ +/* 6.1.9 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -128,7 +128,7 @@ ULONG _txm_power_of_two_block_size(ULONG size) /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ /* */ /**************************************************************************/ VOID _txm_module_manager_alignment_adjust(TXM_MODULE_PREAMBLE *module_preamble, @@ -137,6 +137,53 @@ VOID _txm_module_manager_alignment_adjust(TXM_MODULE_PREAMBLE *module_preamble, ULONG *data_size, ULONG *data_alignment) { +#ifdef TXM_MODULE_MANAGER_16_MPU +ULONG local_code_size; +ULONG local_code_alignment; +ULONG local_data_size; +ULONG local_data_alignment; +ULONG code_size_accum; +ULONG data_size_accum; + + /* Copy the input parameters into local variables for ease of use. */ + local_code_size = *code_size; + local_code_alignment = *code_alignment; + local_data_size = *data_size; + local_data_alignment = *data_alignment; + + /* Determine code block sizes. Minimize the alignment requirement. + There are 4 MPU code entries available. The following is how the code size + will be distributed: + 1. 1/4 of the largest power of two that is greater than or equal to code size. + 2. 1/4 of the largest power of two that is greater than or equal to code size. + 3. Largest power of 2 that fits in the remaining space. + 4. Smallest power of 2 that exceeds the remaining space, minimum 32. */ + local_code_alignment = _txm_power_of_two_block_size(local_code_size) >> 2; + code_size_accum = local_code_alignment + local_code_alignment; + code_size_accum = code_size_accum + (_txm_power_of_two_block_size(local_code_size - code_size_accum) >> 1); + code_size_accum = code_size_accum + _txm_power_of_two_block_size(local_code_size - code_size_accum); + local_code_size = code_size_accum; + + /* Determine data block sizes. Minimize the alignment requirement. + There are 4 MPU data entries available. The following is how the data size + will be distributed: + 1. 1/4 of the largest power of two that is greater than or equal to data size. + 2. 1/4 of the largest power of two that is greater than or equal to data size. + 3. Largest power of 2 that fits in the remaining space. + 4. Smallest power of 2 that exceeds the remaining space, minimum 32. */ + local_data_alignment = _txm_power_of_two_block_size(local_data_size) >> 2; + data_size_accum = local_data_alignment + local_data_alignment; + data_size_accum = data_size_accum + (_txm_power_of_two_block_size(local_data_size - data_size_accum) >> 1); + data_size_accum = data_size_accum + _txm_power_of_two_block_size(local_data_size - data_size_accum); + local_data_size = data_size_accum; + + /* Return all the information to the caller. */ + *code_size = local_code_size; + *code_alignment = local_code_alignment; + *data_size = local_data_size; + *data_alignment = local_data_alignment; + +#else ULONG local_code_size; ULONG local_code_alignment; @@ -396,4 +443,6 @@ ULONG data_size_accum; *code_alignment = local_code_alignment; *data_size = local_data_size; *data_alignment = local_data_alignment; + +#endif } diff --git a/ports_module/cortex_m4/gnu/module_manager/src/txm_module_manager_external_memory_enable.c b/ports_module/cortex_m4/gnu/module_manager/src/txm_module_manager_external_memory_enable.c index c5682545..79af7655 100644 --- a/ports_module/cortex_m4/gnu/module_manager/src/txm_module_manager_external_memory_enable.c +++ b/ports_module/cortex_m4/gnu/module_manager/src/txm_module_manager_external_memory_enable.c @@ -33,8 +33,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _txm_module_manager_external_memory_enable Cortex-M4/MPU/GNU */ -/* 6.1 */ +/* _txm_module_manager_external_memory_enable Cortex-M4 */ +/* 6.1.9 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -70,7 +70,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ /* */ /**************************************************************************/ UINT _txm_module_manager_external_memory_enable(TXM_MODULE_INSTANCE *module_instance, @@ -78,6 +78,117 @@ UINT _txm_module_manager_external_memory_enable(TXM_MODULE_INSTANCE *module_ins ULONG length, UINT attributes) { +#ifdef TXM_MODULE_MANAGER_16_MPU +ULONG block_size; +ULONG region_size; +ULONG srd_bits; +ULONG size_register; +ULONG address; +ULONG shared_index; +ULONG attributes_check = 0; + + /* Determine if the module manager has not been initialized yet. */ + if (_txm_module_manager_ready != TX_TRUE) + { + /* Module manager has not been initialized. */ + return(TX_NOT_AVAILABLE); + } + + /* Determine if the module is valid. */ + if (module_instance == TX_NULL) + { + /* Invalid module pointer. */ + return(TX_PTR_ERROR); + } + + /* Get module manager protection mutex. */ + _tx_mutex_get(&_txm_module_manager_mutex, TX_WAIT_FOREVER); + + /* Determine if the module instance is valid. */ + if (module_instance -> txm_module_instance_id != TXM_MODULE_ID) + { + /* Release the protection mutex. */ + _tx_mutex_put(&_txm_module_manager_mutex); + + /* Invalid module pointer. */ + return(TX_PTR_ERROR); + } + + /* Determine if the module instance is in the loaded state. */ + if (module_instance -> txm_module_instance_state != TXM_MODULE_LOADED) + { + /* Release the protection mutex. */ + _tx_mutex_put(&_txm_module_manager_mutex); + + /* Return error if the module is not ready. */ + return(TX_START_ERROR); + } + + /* Determine if there are shared memory entries available. */ + if(module_instance -> txm_module_instance_shared_memory_count >= TXM_MODULE_MPU_SHARED_ENTRIES) + { + /* Release the protection mutex. */ + _tx_mutex_put(&_txm_module_manager_mutex); + + /* No more entries available. */ + return(TX_NO_MEMORY); + } + + /* Start address and length must adhere to Cortex-M7 MPU. + The address must align with the block size. */ + + block_size = _txm_power_of_two_block_size(length); + address = (ULONG) start_address; + if(address != (address & ~(block_size - 1))) + { + /* Release the protection mutex. */ + _tx_mutex_put(&_txm_module_manager_mutex); + + /* Return alignment error. */ + return(TXM_MODULE_ALIGNMENT_ERROR); + } + + /* At this point, we have a valid address and block size. + Set up MPU registers. */ + + /* Pick up index into shared memory entries. */ + shared_index = TXM_MODULE_MPU_SHARED_INDEX + module_instance -> txm_module_instance_shared_memory_count; + + /* Save address register with address, MPU region, set Valid bit. */ + module_instance -> txm_module_instance_mpu_registers[shared_index].txm_module_mpu_region_address = address | shared_index | 0x10; + + /* Calculate the region size. */ + region_size = (_txm_module_manager_region_size_get(block_size) << 1); + + /* Calculate the subregion bits. */ + srd_bits = _txm_module_manager_calculate_srd_bits(block_size, length); + + /* Generate SRD, size, and enable attributes. */ + size_register = srd_bits | region_size | TXM_ENABLE_REGION | TXM_MODULE_MPU_SHARED_ACCESS_CONTROL; + + /* Check for optional write attribute. */ + if(attributes & TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE) + { + attributes_check = TXM_MODULE_MANAGER_ATTRIBUTE_WRITE_MPU_BIT; + } + + /* Save attribute-size register. */ + module_instance -> txm_module_instance_mpu_registers[shared_index].txm_module_mpu_region_attribute_size = attributes_check | size_register; + + /* Keep track of shared memory address and length in module instance. */ + module_instance -> txm_module_instance_shared_memory_address[module_instance -> txm_module_instance_shared_memory_count] = address; + module_instance -> txm_module_instance_shared_memory_length[module_instance -> txm_module_instance_shared_memory_count] = length; + + /* Increment counter. */ + module_instance -> txm_module_instance_shared_memory_count++; + + /* Release the protection mutex. */ + _tx_mutex_put(&_txm_module_manager_mutex); + + /* Return success. */ + return(TX_SUCCESS); + +#else ULONG block_size; ULONG region_size; @@ -179,4 +290,6 @@ TXM_MODULE_PREAMBLE *module_preamble; /* Return success. */ return(TX_SUCCESS); + +#endif } diff --git a/ports_module/cortex_m4/gnu/module_manager/src/txm_module_manager_memory_fault_handler.c b/ports_module/cortex_m4/gnu/module_manager/src/txm_module_manager_memory_fault_handler.c index 7ba3e553..47c2b014 100644 --- a/ports_module/cortex_m4/gnu/module_manager/src/txm_module_manager_memory_fault_handler.c +++ b/ports_module/cortex_m4/gnu/module_manager/src/txm_module_manager_memory_fault_handler.c @@ -45,8 +45,8 @@ TXM_MODULE_MANAGER_FAULT_INFO /* */ /* FUNCTION RELEASE */ /* */ -/* _txm_module_manager_memory_fault_handler Cortex-M4/MPU/GNU */ -/* 6.1 */ +/* _txm_module_manager_memory_fault_handler Cortex-M4 */ +/* 6.1.9 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -76,7 +76,7 @@ TXM_MODULE_MANAGER_FAULT_INFO /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ /* */ /**************************************************************************/ VOID _txm_module_manager_memory_fault_handler(VOID) diff --git a/ports_module/cortex_m4/gnu/module_manager/src/txm_module_manager_memory_fault_notify.c b/ports_module/cortex_m4/gnu/module_manager/src/txm_module_manager_memory_fault_notify.c index 46ac8d8f..ba5f5bd6 100644 --- a/ports_module/cortex_m4/gnu/module_manager/src/txm_module_manager_memory_fault_notify.c +++ b/ports_module/cortex_m4/gnu/module_manager/src/txm_module_manager_memory_fault_notify.c @@ -38,8 +38,8 @@ extern VOID (*_txm_module_manager_fault_notify)(TX_THREAD *, TXM_MODULE_INSTA /* */ /* FUNCTION RELEASE */ /* */ -/* _txm_module_manager_memory_fault_notify Cortex-M4/MPU/GNU */ -/* 6.1 */ +/* _txm_module_manager_memory_fault_notify Cortex-M4 */ +/* 6.1.9 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -71,7 +71,7 @@ extern VOID (*_txm_module_manager_fault_notify)(TX_THREAD *, TXM_MODULE_INSTA /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ /* */ /**************************************************************************/ UINT _txm_module_manager_memory_fault_notify(VOID (*notify_function)(TX_THREAD *, TXM_MODULE_INSTANCE *)) diff --git a/ports_module/cortex_m4/gnu/module_manager/src/txm_module_manager_mm_register_setup.c b/ports_module/cortex_m4/gnu/module_manager/src/txm_module_manager_mm_register_setup.c index 54e7c87a..dcc8d2aa 100644 --- a/ports_module/cortex_m4/gnu/module_manager/src/txm_module_manager_mm_register_setup.c +++ b/ports_module/cortex_m4/gnu/module_manager/src/txm_module_manager_mm_register_setup.c @@ -30,8 +30,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _txm_module_manager_region_size_get Cortex-M4/MPU/GNU */ -/* 6.1 */ +/* _txm_module_manager_region_size_get Cortex-M4 */ +/* 6.1.9 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -61,7 +61,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ /* */ /**************************************************************************/ ULONG _txm_module_manager_region_size_get(ULONG block_size) @@ -152,8 +152,8 @@ ULONG return_value; /* */ /* FUNCTION RELEASE */ /* */ -/* _txm_module_manager_calculate_srd_bits Cortex-M4/MPU/GNU */ -/* 6.1 */ +/* _txm_module_manager_calculate_srd_bits Cortex-M4 */ +/* 6.1.9 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -184,7 +184,7 @@ ULONG return_value; /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ /* */ /**************************************************************************/ ULONG _txm_module_manager_calculate_srd_bits(ULONG block_size, ULONG length) @@ -230,16 +230,48 @@ UINT srd_bit_index; /* */ /* FUNCTION RELEASE */ /* */ -/* _txm_module_manager_mm_register_setup Cortex-M4/MPU/GNU */ -/* 6.1 */ +/* _txm_module_manager_mm_register_setup Cortex-M4 */ +/* 6.1.9 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ /* */ /* DESCRIPTION */ /* */ -/* This function sets up the Cortex-M4 MPU register definitions based */ -/* on the module's memory characteristics. */ +/* This function sets up the MPU register definitions based on the */ +/* module's memory characteristics. */ +/* */ +/* Default MPU layout: */ +/* Entry Description */ +/* 0 Kernel mode entry */ +/* 1 Module code region */ +/* 2 Module code region */ +/* 3 Module code region */ +/* 4 Module code region */ +/* 5 Module data region */ +/* 6 Module data region */ +/* 7 Module data region */ +/* */ +/* If TXM_MODULE_MANAGER_16_MPU is defined, there are 16 MPU slots. */ +/* MPU layout for the Cortex-M7: */ +/* Entry Description */ +/* 0 Kernel mode entry */ +/* 1 Module code region */ +/* 2 Module code region */ +/* 3 Module code region */ +/* 4 Module code region */ +/* 5 Module data region */ +/* 6 Module data region */ +/* 7 Module data region */ +/* 8 Module data region */ +/* 9 Module shared memory region */ +/* 10 Module shared memory region */ +/* 11 Module shared memory region */ +/* 12 Unused region */ +/* 13 Unused region */ +/* 14 Unused region */ +/* 15 Unused region */ +/* */ /* */ /* INPUT */ /* */ @@ -261,11 +293,181 @@ UINT srd_bit_index; /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ /* */ /**************************************************************************/ VOID _txm_module_manager_mm_register_setup(TXM_MODULE_INSTANCE *module_instance) { +#ifdef TXM_MODULE_MANAGER_16_MPU + +ULONG code_address; +ULONG code_size; +ULONG data_address; +ULONG data_size; +ULONG start_stop_stack_size; +ULONG callback_stack_size; +ULONG block_size; +ULONG region_size; +ULONG srd_bits = 0; +UINT mpu_table_index; +UINT i; + + + /* Setup the first MPU region for kernel mode entry. */ + /* Set address register to user mode entry function address, which is guaranteed to be at least 32-byte aligned. + Mask address to proper range, region 0, set Valid bit. */ + module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MPU_KERNEL_ENTRY_INDEX].txm_module_mpu_region_address = ((ULONG) _txm_module_manager_user_mode_entry & 0xFFFFFFE0) | 0x10; + /* Set the attributes, size (32 bytes) and enable bit. */ + module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MPU_KERNEL_ENTRY_INDEX].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_CODE_ACCESS_CONTROL | (_txm_module_manager_region_size_get(32) << 1) | TXM_ENABLE_REGION; + /* End of kernel mode entry setup. */ + + /* Setup code protection. */ + + /* Initialize the MPU table index. */ + mpu_table_index = 1; + + /* Pickup code starting address and actual size. */ + code_address = (ULONG) module_instance -> txm_module_instance_code_start; + code_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_code_size; + + /* Determine code block sizes. Minimize the alignment requirement. + There are 4 MPU code entries available. The following is how the code size + will be distributed: + 1. 1/4 of the largest power of two that is greater than or equal to code size. + 2. 1/4 of the largest power of two that is greater than or equal to code size. + 3. Largest power of 2 that fits in the remaining space. + 4. Smallest power of 2 that exceeds the remaining space, minimum 32. */ + + /* Now loop through to setup MPU protection for the code area. */ + for (i = 0; i < TXM_MODULE_MPU_CODE_ENTRIES; i++) + { + /* First two MPU blocks are 1/4 of the largest power of two + that is greater than or equal to code size. */ + if (i < 2) + { + block_size = _txm_power_of_two_block_size(code_size) >> 2; + } + + /* Third MPU block is the largest power of 2 that fits in the remaining space. */ + else if (i == 2) + { + /* Subtract (block_size*2) from code_size to calculate remaining space. */ + code_size = code_size - (block_size << 1); + block_size = _txm_power_of_two_block_size(code_size) >> 1; + } + + /* Last MPU block is the smallest power of 2 that exceeds the remaining space, minimum 32. */ + else + { + /* Calculate remaining space. */ + code_size = code_size - block_size; + block_size = _txm_power_of_two_block_size(code_size); + srd_bits = _txm_module_manager_calculate_srd_bits(block_size, code_size); + } + + /* Calculate the region size information. */ + region_size = (_txm_module_manager_region_size_get(block_size) << 1); + + /* Build the base address register with address, MPU region, set Valid bit. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_address = (code_address & ~(block_size - 1)) | mpu_table_index | 0x10; + /* Build the attribute-size register with permissions, SRD, size, enable. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_CODE_ACCESS_CONTROL | srd_bits | region_size | TXM_ENABLE_REGION; + + /* Adjust the code address. */ + code_address = code_address + block_size; + + /* Increment MPU table index. */ + mpu_table_index++; + } + /* End of code protection. */ + + /* Setup data protection. */ + + /* Reset SRD bitfield. */ + srd_bits = 0; + + /* Pickup data starting address and actual size. */ + data_address = (ULONG) module_instance -> txm_module_instance_data_start; + + /* Adjust the size of the module elements to be aligned to the default alignment. We do this + so that when we partition the allocated memory, we can simply place these regions right beside + each other without having to align their pointers. Note this only works when they all have + the same alignment. */ + + data_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_data_size; + start_stop_stack_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_start_stop_stack_size; + callback_stack_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_callback_stack_size; + + data_size = ((data_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; + + start_stop_stack_size = ((start_stop_stack_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; + + callback_stack_size = ((callback_stack_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; + + /* Update the data size to include thread stacks. */ + data_size = data_size + start_stop_stack_size + callback_stack_size; + + /* Determine data block sizes. Minimize the alignment requirement. + There are 4 MPU data entries available. The following is how the data size + will be distributed: + 1. 1/4 of the largest power of two that is greater than or equal to data size. + 2. 1/4 of the largest power of two that is greater than or equal to data size. + 3. Largest power of 2 that fits in the remaining space. + 4. Smallest power of 2 that exceeds the remaining space, minimum 32. */ + + /* Now loop through to setup MPU protection for the data area. */ + for (i = 0; i < TXM_MODULE_MPU_DATA_ENTRIES; i++) + { + /* First two MPU blocks are 1/4 of the largest power of two + that is greater than or equal to data size. */ + if (i < 2) + { + block_size = _txm_power_of_two_block_size(data_size) >> 2; + } + + /* Third MPU block is the largest power of 2 that fits in the remaining space. */ + else if (i == 2) + { + /* Subtract (block_size*2) from data_size to calculate remaining space. */ + data_size = data_size - (block_size << 1); + block_size = _txm_power_of_two_block_size(data_size) >> 1; + } + + /* Last MPU block is the smallest power of 2 that exceeds the remaining space, minimum 32. */ + else + { + /* Calculate remaining space. */ + data_size = data_size - block_size; + block_size = _txm_power_of_two_block_size(data_size); + srd_bits = _txm_module_manager_calculate_srd_bits(block_size, data_size); + } + + /* Calculate the region size information. */ + region_size = (_txm_module_manager_region_size_get(block_size) << 1); + + /* Build the base address register with address, MPU region, set Valid bit. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_address = (data_address & ~(block_size - 1)) | mpu_table_index | 0x10; + /* Build the attribute-size register with permissions, SRD, size, enable. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_DATA_ACCESS_CONTROL | srd_bits | region_size | TXM_ENABLE_REGION; + + /* Adjust the data address. */ + data_address = data_address + block_size; + + /* Increment MPU table index. */ + mpu_table_index++; + } + + /* Setup MPU for the remaining regions. */ + while (mpu_table_index < TXM_MODULE_MPU_TOTAL_ENTRIES) + { + /* Build the base address register with address, MPU region, set Valid bit. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_address = mpu_table_index | 0x10; + + /* Increment MPU table index. */ + mpu_table_index++; + } + +#else ULONG code_address; ULONG code_size; @@ -382,7 +584,7 @@ UINT i; for (i = 0; i < TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1; i++) { /* Build the base address register. */ - base_address_register = code_address & ~(block_size - 1) | mpu_register | 0x10; + base_address_register = (code_address & ~(block_size - 1)) | mpu_register | 0x10; /* Check if SRD bits need to be set. */ if (code_size < block_size) @@ -509,4 +711,87 @@ UINT i; /* Increment the MPU register index. */ mpu_register++; } + +#endif +} + +#ifdef TXM_MODULE_MANAGER_16_MPU +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_inside_data_check Cortex-M4 */ +/* 6.1.9 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks if the specified object is inside shared */ +/* memory. */ +/* */ +/* INPUT */ +/* */ +/* module_instance Pointer to module instance */ +/* obj_ptr Pointer to the object */ +/* obj_size Size of the object */ +/* */ +/* OUTPUT */ +/* */ +/* Whether the object is inside the shared memory region. */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Module dispatch check functions */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ +/* */ +/**************************************************************************/ +UINT _txm_module_manager_inside_data_check(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE obj_ptr, UINT obj_size) +{ + +UINT shared_memory_index; +UINT num_shared_memory_mpu_entries; +ALIGN_TYPE shared_memory_address_start; +ALIGN_TYPE shared_memory_address_end; + + /* Check for overflow. */ + if ((obj_ptr) > ((obj_ptr) + (obj_size))) + { + return(TX_FALSE); + } + + /* Check if the object is inside the module data. */ + if ((obj_ptr >= (ALIGN_TYPE) module_instance -> txm_module_instance_data_start) && + ((obj_ptr + obj_size) <= ((ALIGN_TYPE) module_instance -> txm_module_instance_data_end + 1))) + { + return(TX_TRUE); + } + + /* Check if the object is inside the shared memory. */ + num_shared_memory_mpu_entries = module_instance -> txm_module_instance_shared_memory_count; + for (shared_memory_index = 0; shared_memory_index < num_shared_memory_mpu_entries; shared_memory_index++) + { + + shared_memory_address_start = (ALIGN_TYPE) module_instance -> txm_module_instance_shared_memory_address[shared_memory_index]; + shared_memory_address_end = shared_memory_address_start + module_instance -> txm_module_instance_shared_memory_length[shared_memory_index]; + + if ((obj_ptr >= (ALIGN_TYPE) shared_memory_address_start) && + ((obj_ptr + obj_size) <= (ALIGN_TYPE) shared_memory_address_end)) + { + return(TX_TRUE); + } + } + + return(TX_FALSE); } +#endif diff --git a/ports_module/cortex_m4/gnu/module_manager/src/txm_module_manager_thread_stack_build.s b/ports_module/cortex_m4/gnu/module_manager/src/txm_module_manager_thread_stack_build.s index 4ddbe47a..50ac5be5 100644 --- a/ports_module/cortex_m4/gnu/module_manager/src/txm_module_manager_thread_stack_build.s +++ b/ports_module/cortex_m4/gnu/module_manager/src/txm_module_manager_thread_stack_build.s @@ -27,8 +27,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _txm_module_manager_thread_stack_build Cortex-M4/MPU/GNU */ -/* 6.1.2 */ +/* _txm_module_manager_thread_stack_build Cortex-M4/GNU */ +/* 6.1.9 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -60,9 +60,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 11-09-2020 Scott Larson Modified comment(s), */ -/* resulting in version 6.1.2 */ +/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ /* */ /**************************************************************************/ // VOID _txm_module_manager_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(TX_THREAD *, TXM_MODULE_INSTANCE *)) diff --git a/ports_module/cortex_m4/iar/inc/tx_port.h b/ports_module/cortex_m4/iar/inc/tx_port.h index 6d65baa5..5ca644a6 100644 --- a/ports_module/cortex_m4/iar/inc/tx_port.h +++ b/ports_module/cortex_m4/iar/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h Cortex-M4/IAR */ -/* 6.1 */ +/* 6.1.9 */ /* */ /* AUTHOR */ /* */ @@ -47,7 +47,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ /* */ /**************************************************************************/ @@ -71,7 +71,7 @@ #include <stdlib.h> #include <string.h> #include <intrinsics.h> -#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT #include <yvals.h> #endif @@ -117,7 +117,7 @@ typedef unsigned short USHORT; #endif -/* Define various constants for the ThreadX ARM Cortex-M port. */ +/* Define various constants for the ThreadX Cortex-M4 port. */ #define TX_INT_DISABLE 1 /* Disable interrupts */ #define TX_INT_ENABLE 0 /* Enable interrupts */ @@ -180,8 +180,8 @@ ULONG _tx_misra_time_stamp_get(VOID); for the multiple macros is so that backward compatibility can be maintained with existing ThreadX kernel awareness modules. */ -#define TX_THREAD_EXTENSION_0 -#define TX_THREAD_EXTENSION_1 +#define TX_THREAD_EXTENSION_0 +#define TX_THREAD_EXTENSION_1 #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT #define TX_THREAD_EXTENSION_2 VOID *tx_thread_module_instance_ptr; \ VOID *tx_thread_module_entry_info_ptr; \ @@ -224,13 +224,16 @@ ULONG _tx_misra_time_stamp_get(VOID); #define TX_BLOCK_POOL_EXTENSION #define TX_BYTE_POOL_EXTENSION +#define TX_MUTEX_EXTENSION #define TX_EVENT_FLAGS_GROUP_EXTENSION VOID *tx_event_flags_group_module_instance; \ VOID (*tx_event_flags_group_set_module_notify)(struct TX_EVENT_FLAGS_GROUP_STRUCT *group_ptr); -#define TX_MUTEX_EXTENSION + #define TX_QUEUE_EXTENSION VOID *tx_queue_module_instance; \ VOID (*tx_queue_send_module_notify)(struct TX_QUEUE_STRUCT *queue_ptr); + #define TX_SEMAPHORE_EXTENSION VOID *tx_semaphore_module_instance; \ VOID (*tx_semaphore_put_module_notify)(struct TX_SEMAPHORE_STRUCT *semaphore_ptr); + #define TX_TIMER_EXTENSION VOID *tx_timer_module_instance; \ VOID (*tx_timer_module_expiration_function)(ULONG id); @@ -376,7 +379,7 @@ void _tx_misra_vfp_touch(void); #else #define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) -#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) +#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) #endif @@ -485,7 +488,7 @@ __istate_t interrupt_save; #endif -/* Define FPU extension for the Cortex-M4. Each is assumed to be called in the context of the executing +/* Define FPU extension for the Cortex-M7. Each is assumed to be called in the context of the executing thread. These are no longer needed, but are preserved for backward compatibility only. */ void tx_thread_fpu_enable(void); @@ -506,7 +509,7 @@ void tx_thread_fpu_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M4/IAR Version 6.1 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M4/IAR Version 6.x *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; @@ -517,6 +520,3 @@ extern CHAR _tx_version_id[]; #endif - - - diff --git a/ports_module/cortex_m4/iar/inc/txm_module_port.h b/ports_module/cortex_m4/iar/inc/txm_module_port.h index 6630204f..d9937791 100644 --- a/ports_module/cortex_m4/iar/inc/txm_module_port.h +++ b/ports_module/cortex_m4/iar/inc/txm_module_port.h @@ -25,8 +25,8 @@ /* */ /* APPLICATION INTERFACE DEFINITION RELEASE */ /* */ -/* txm_module_port.h Cortex-M4/MPU/IAR */ -/* 6.1.6 */ +/* txm_module_port.h Cortex-M4/IAR */ +/* 6.1.9 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -40,13 +40,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 11-09-2020 Scott Larson Modified comment(s), */ -/* increase kernel stack size, */ -/* resulting in version 6.1.2 */ -/* 04-02-2021 Scott Larson Modified comment(s), */ -/* added check for overflow, */ -/* resulting in version 6.1.6 */ +/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ /* */ /**************************************************************************/ @@ -103,6 +97,21 @@ The following extensions must also be defined in tx_port.h: #define TXM_MODULE_KERNEL_STACK_SIZE 768 #endif +/* For the following 3 access control settings, change TEX and C, B, S (bits 21 through 16 of MPU_RASR) + * to reflect your system memory attributes (cache, shareable, memory type). */ +/* Code region access control: privileged read-only, outer & inner write-back, normal memory, shareable. */ +#ifndef TXM_MODULE_MPU_CODE_ACCESS_CONTROL +#define TXM_MODULE_MPU_CODE_ACCESS_CONTROL 0x06070000 +#endif +/* Data region access control: execute never, read/write, outer & inner write-back, normal memory, shareable. */ +#ifndef TXM_MODULE_MPU_DATA_ACCESS_CONTROL +#define TXM_MODULE_MPU_DATA_ACCESS_CONTROL 0x13070000 +#endif +/* Shared region access control: execute never, read-only, outer & inner write-back, normal memory, shareable. */ +#ifndef TXM_MODULE_MPU_SHARED_ACCESS_CONTROL +#define TXM_MODULE_MPU_SHARED_ACCESS_CONTROL 0x12070000 +#endif + /* Define constants specific to the tools the module can be built with for this particular modules port. */ #define TXM_MODULE_IAR_COMPILER 0x00000000 @@ -157,8 +166,43 @@ The following extensions must also be defined in tx_port.h: #define INLINE_DECLARE inline +#ifdef TXM_MODULE_MANAGER_16_MPU + +/* Define the number of MPU entries assigned to the code and data sections. + On some Cortex-M7 parts, there are 16 total entries. ThreadX uses one for access + to the kernel entry function, thus 15 remain for code and data protection. */ +#define TXM_MODULE_MPU_TOTAL_ENTRIES 16 +#define TXM_MODULE_MPU_CODE_ENTRIES 4 +#define TXM_MODULE_MPU_DATA_ENTRIES 4 +#define TXM_MODULE_MPU_SHARED_ENTRIES 3 + +#define TXM_MODULE_MPU_KERNEL_ENTRY_INDEX 0 +#define TXM_MODULE_MPU_SHARED_INDEX 9 + +#define TXM_ENABLE_REGION 0x01 + +/* There are 2 registers to set up each MPU region: MPU_RBAR, MPU_RASR. */ +typedef struct TXM_MODULE_MPU_INFO_STRUCT +{ + ULONG txm_module_mpu_region_address; + ULONG txm_module_mpu_region_attribute_size; +} TXM_MODULE_MPU_INFO; +/* Shared memory region attributes. */ +#define TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE 1 +#define TXM_MODULE_MANAGER_ATTRIBUTE_WRITE_MPU_BIT 0x01000000 + +/* Define the port-extensions to the module manager instance structure. */ + +#define TXM_MODULE_MANAGER_PORT_EXTENSION \ + TXM_MODULE_MPU_INFO txm_module_instance_mpu_registers[TXM_MODULE_MPU_TOTAL_ENTRIES]; \ + ULONG txm_module_instance_shared_memory_count; \ + ULONG txm_module_instance_shared_memory_address[TXM_MODULE_MPU_SHARED_ENTRIES]; \ + ULONG txm_module_instance_shared_memory_length[TXM_MODULE_MPU_SHARED_ENTRIES]; + +#else /* TXM_MODULE_MANAGER_16_MPU is not defined */ + /* Define the number of MPU entries assigned to the code and data sections. - On Cortex-M4 parts, there are 8 total entries. ThreadX uses one for access + On Cortex-M3, M4, and some M7 parts, there are 8 total entries. ThreadX uses one for access to the kernel entry function, thus 7 remain for code and data protection. */ #define TXM_MODULE_MANAGER_CODE_MPU_ENTRIES 4 #define TXM_MODULE_MANAGER_DATA_MPU_ENTRIES 3 @@ -176,6 +220,7 @@ The following extensions must also be defined in tx_port.h: ULONG txm_module_instance_shared_memory_address; \ ULONG txm_module_instance_shared_memory_length; +#endif /* TXM_MODULE_MANAGER_16_MPU */ /* Define the memory fault information structure that is populated when a memory fault occurs. */ @@ -298,6 +343,10 @@ typedef struct TXM_MODULE_MANAGER_MEMORY_FAULT_INFO_STRUCT /* Define the macros to perform port-specific checks when passing pointers to the kernel. */ /* Define macro to make sure object is inside the module's data. */ +#ifdef TXM_MODULE_MANAGER_16_MPU +#define TXM_MODULE_MANAGER_CHECK_INSIDE_DATA(module_instance, obj_ptr, obj_size) \ + _txm_module_manager_inside_data_check(module_instance, obj_ptr, obj_size) +#else #define TXM_MODULE_MANAGER_CHECK_INSIDE_DATA(module_instance, obj_ptr, obj_size) \ /* Check for overflow. */ \ (((obj_ptr) < ((obj_ptr) + (obj_size))) && \ @@ -307,7 +356,7 @@ typedef struct TXM_MODULE_MANAGER_MEMORY_FAULT_INFO_STRUCT /* Check if it's inside shared memory. */ \ (((obj_ptr) >= (ALIGN_TYPE) module_instance -> txm_module_instance_shared_memory_address) && \ (((obj_ptr) + (obj_size)) <= (ALIGN_TYPE) (module_instance -> txm_module_instance_shared_memory_address + module_instance -> txm_module_instance_shared_memory_length))))) - +#endif /* Define some internal prototypes to this module port. */ @@ -323,10 +372,11 @@ UINT _txm_module_manager_memory_fault_notify(VOID (*notify_function)(TX_THREAD VOID _txm_module_manager_mm_register_setup(TXM_MODULE_INSTANCE *module_instance); \ ULONG _txm_power_of_two_block_size(ULONG size); \ ULONG _txm_module_manager_calculate_srd_bits(ULONG block_size, ULONG length); \ -ULONG _txm_module_manager_region_size_get(ULONG block_size); +ULONG _txm_module_manager_region_size_get(ULONG block_size); \ +UINT _txm_module_manager_inside_data_check(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE obj_ptr, UINT obj_size); #define TXM_MODULE_MANAGER_VERSION_ID \ CHAR _txm_module_manager_version_id[] = \ - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-M4/MPU/IAR Version 6.1.2 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-M4/IAR Version 6.x *"; #endif diff --git a/ports_module/cortex_m4/iar/module_lib/src/txm_module_thread_shell_entry.c b/ports_module/cortex_m4/iar/module_lib/src/txm_module_thread_shell_entry.c index ac511f35..92cef75d 100644 --- a/ports_module/cortex_m4/iar/module_lib/src/txm_module_thread_shell_entry.c +++ b/ports_module/cortex_m4/iar/module_lib/src/txm_module_thread_shell_entry.c @@ -44,7 +44,7 @@ TXM_MODULE_THREAD_ENTRY_INFO *_txm_module_entry_info; ULONG (*_txm_module_kernel_call_dispatcher)(ULONG kernel_request, ULONG param_1, ULONG param_2, ULONG param3); -/* Define the IAR startup code that clears the uninitialized global data and sets up the +/* Define the startup code that clears the uninitialized global data and sets up the preset global variables. */ extern VOID __iar_data_init3(VOID); @@ -54,15 +54,15 @@ extern VOID __iar_data_init3(VOID); /* */ /* FUNCTION RELEASE */ /* */ -/* _txm_module_thread_shell_entry Cortex-M4/MPU/IAR */ -/* 6.1 */ +/* _txm_module_thread_shell_entry Cortex-M4/IAR */ +/* 6.1.9 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ /* */ /* DESCRIPTION */ /* */ -/* This function calls the specified entry function of the thread. It */ +/* This function calls the specified entry function of the thread. It */ /* also provides a place for the thread's entry function to return. */ /* If the thread returns, this function places the thread in a */ /* "COMPLETED" state. */ @@ -78,7 +78,7 @@ extern VOID __iar_data_init3(VOID); /* */ /* CALLS */ /* */ -/* __iar_data_init3 IAR global initialization function*/ +/* __iar_data_init3 cstartup initialization */ /* thread_entry Thread's entry function */ /* tx_thread_resume Resume the module callback thread */ /* _txm_module_thread_system_suspend Module thread suspension routine */ @@ -91,7 +91,7 @@ extern VOID __iar_data_init3(VOID); /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ /* */ /**************************************************************************/ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_ENTRY_INFO *thread_info) @@ -106,7 +106,7 @@ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_EN execution. If not, simply skip the C startup code. */ if (thread_info -> txm_module_thread_entry_info_start_thread) { - /* Initialize the IAR C environment. */ + /* Initialize the C environment. */ __iar_data_init3(); /* Save the entry info pointer, for later use. */ @@ -171,4 +171,3 @@ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_EN TX_SAFETY_CRITICAL_EXCEPTION(__FILE__, __LINE__, 0); #endif } - diff --git a/ports_module/cortex_m4/iar/module_manager/src/tx_thread_context_restore.s b/ports_module/cortex_m4/iar/module_manager/src/tx_thread_context_restore.s index 0a188df9..0fa97b59 100644 --- a/ports_module/cortex_m4/iar/module_manager/src/tx_thread_context_restore.s +++ b/ports_module/cortex_m4/iar/module_manager/src/tx_thread_context_restore.s @@ -27,8 +27,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_context_restore Cortex-Mx/IAR */ -/* 6.1.8 */ +/* _tx_thread_context_restore Cortex-M4/IAR */ +/* 6.1.7 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -58,7 +58,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ +/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ /* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) diff --git a/ports_module/cortex_m4/iar/module_manager/src/tx_thread_context_save.s b/ports_module/cortex_m4/iar/module_manager/src/tx_thread_context_save.s index e71ae496..e8ea6166 100644 --- a/ports_module/cortex_m4/iar/module_manager/src/tx_thread_context_save.s +++ b/ports_module/cortex_m4/iar/module_manager/src/tx_thread_context_save.s @@ -27,8 +27,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_context_save Cortex-Mx/IAR */ -/* 6.1.8 */ +/* _tx_thread_context_save Cortex-M4/IAR */ +/* 6.1.7 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -58,7 +58,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ +/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ /* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) diff --git a/ports_module/cortex_m4/iar/module_manager/src/tx_thread_interrupt_control.s b/ports_module/cortex_m4/iar/module_manager/src/tx_thread_interrupt_control.s index c0d9d095..04ca281a 100644 --- a/ports_module/cortex_m4/iar/module_manager/src/tx_thread_interrupt_control.s +++ b/ports_module/cortex_m4/iar/module_manager/src/tx_thread_interrupt_control.s @@ -26,8 +26,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_interrupt_control Cortex-Mx/IAR */ -/* 6.1.8 */ +/* _tx_thread_interrupt_control Cortex-M4/IAR */ +/* 6.1.7 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -57,7 +57,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ +/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ /* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) diff --git a/ports_module/cortex_m4/iar/module_manager/src/tx_thread_interrupt_disable.s b/ports_module/cortex_m4/iar/module_manager/src/tx_thread_interrupt_disable.s index 86fcf188..78fd91d2 100644 --- a/ports_module/cortex_m4/iar/module_manager/src/tx_thread_interrupt_disable.s +++ b/ports_module/cortex_m4/iar/module_manager/src/tx_thread_interrupt_disable.s @@ -26,8 +26,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_interrupt_disable Cortex-Mx/IAR */ -/* 6.1.8 */ +/* _tx_thread_interrupt_disable Cortex-M4/IAR */ +/* 6.1.7 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -57,7 +57,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ +/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ /* */ /**************************************************************************/ // UINT _tx_thread_interrupt_disable(VOID) diff --git a/ports_module/cortex_m4/iar/module_manager/src/tx_thread_interrupt_restore.s b/ports_module/cortex_m4/iar/module_manager/src/tx_thread_interrupt_restore.s index f9603de1..2ef3fb36 100644 --- a/ports_module/cortex_m4/iar/module_manager/src/tx_thread_interrupt_restore.s +++ b/ports_module/cortex_m4/iar/module_manager/src/tx_thread_interrupt_restore.s @@ -26,8 +26,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_interrupt_restore Cortex-Mx/IAR */ -/* 6.1.8 */ +/* _tx_thread_interrupt_restore Cortex-M4/IAR */ +/* 6.1.7 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -57,7 +57,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ +/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ /* */ /**************************************************************************/ // VOID _tx_thread_interrupt_restore(UINT previous_posture) diff --git a/ports_module/cortex_m4/iar/module_manager/src/tx_thread_schedule.s b/ports_module/cortex_m4/iar/module_manager/src/tx_thread_schedule.s index a7efd980..56da6a11 100644 --- a/ports_module/cortex_m4/iar/module_manager/src/tx_thread_schedule.s +++ b/ports_module/cortex_m4/iar/module_manager/src/tx_thread_schedule.s @@ -35,8 +35,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_schedule Cortex-M4/MPU/IAR */ -/* 6.1.7 */ +/* _tx_thread_schedule Cortex-M4/IAR */ +/* 6.1.9 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -69,14 +69,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 11-09-2020 Scott Larson Modified comment(s), arrange */ -/* code to fix link error when */ -/* VFP is enabled, resulting */ -/* in version 6.1.2 */ -/* 06-02-2021 Scott Larson Fixed extended stack handling */ -/* when calling kernel APIs, */ -/* resulting in version 6.1.7 */ +/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ /* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) @@ -102,7 +95,6 @@ _tx_thread_schedule: #endif /* Enable memory fault registers. */ - LDR r0, =0xE000ED24 // Build SHCSR address LDR r1, =0x70000 // Enable Usage, Bus, and MemManage faults STR r1, [r0] // @@ -361,10 +353,21 @@ __tx_ts_restore: // Use alias registers to quickly load MPU ADD r0, r0, #100 // Build address of MPU register start in thread control block +#ifdef TXM_MODULE_MANAGER_16_MPU + LDM r0!,{r2-r9} // Load MPU regions 0-3 + STM r1,{r2-r9} // Store MPU regions 0-3 + LDM r0!,{r2-r9} // Load MPU regions 4-7 + STM r1,{r2-r9} // Store MPU regions 4-7 + LDM r0!,{r2-r9} // Load MPU regions 8-11 + STM r1,{r2-r9} // Store MPU regions 8-11 + LDM r0,{r2-r9} // Load MPU regions 12-15 + STM r1,{r2-r9} // Store MPU regions 12-15 +#else LDM r0!,{r2-r9} // Load first four MPU regions STM r1,{r2-r9} // Store first four MPU regions LDM r0,{r2-r9} // Load second four MPU regions STM r1,{r2-r9} // Store second four MPU regions +#endif LDR r0, =0xE000ED94 // Build MPU control reg address MOV r1, #5 // Build enable value with background region enabled STR r1, [r0] // Enable MPU @@ -433,13 +436,17 @@ __tx_SVCallHandler: #endif MRS r3, PSP // Pickup thread stack pointer +#ifdef __ARMVFP__ TST lr, #0x10 // Test for extended module stack ITT EQ ORREQ r3, r3, #1 // If so, set LSB in thread stack pointer to indicate extended frame ORREQ lr, lr, #0x10 // Set bit, return with standard frame +#endif STR r3, [r2, #0xB0] // Save thread stack pointer +#ifdef __ARMVFP__ BIC r3, #1 // Clear possibly OR'd bit - +#endif + /* Build kernel stack by copying thread stack two registers at a time */ ADD r3, r3, #32 // Start at bottom of hardware stack LDMDB r3!, {r1-r2} @@ -486,6 +493,7 @@ _tx_thread_user_return: STR r3, [r2, #20] // Set stack size #endif +#ifdef __ARMVFP__ /* If lazy stacking is pending, check if it can be cleared. if(LSPACT && tx_thread_module_stack_start < FPCAR && FPCAR < tx_thread_module_stack_end) then clear LSPACT. */ @@ -505,14 +513,17 @@ _tx_thread_user_return: LDR r1, =0xE000EF34 // Address of FPCCR STR r3, [r1] // Save updated FPCCR _tx_no_lazy_clear: +#endif LDR r0, [r2, #0xB0] // Load the module thread stack pointer MRS r3, PSP // Pickup kernel stack pointer +#ifdef __ARMVFP__ TST r0, #1 // Is module stack extended? ITTE NE // If so... BICNE lr, #0x10 // Clear bit, return with extended frame BICNE r0, #1 // Clear bit that indicates extended module frame ORREQ lr, lr, #0x10 // Else set bit, return with standard frame +#endif /* Copy kernel hardware stack to module thread stack. */ LDM r3!, {r1-r2} diff --git a/ports_module/cortex_m4/iar/module_manager/src/tx_thread_stack_build.s b/ports_module/cortex_m4/iar/module_manager/src/tx_thread_stack_build.s index dcc82bf6..0a2ee915 100644 --- a/ports_module/cortex_m4/iar/module_manager/src/tx_thread_stack_build.s +++ b/ports_module/cortex_m4/iar/module_manager/src/tx_thread_stack_build.s @@ -26,8 +26,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_stack_build Cortex-Mx/IAR */ -/* 6.1.8 */ +/* _tx_thread_stack_build Cortex-M4/IAR */ +/* 6.1.7 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -59,7 +59,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ +/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ /* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) diff --git a/ports_module/cortex_m4/iar/module_manager/src/tx_thread_system_return.s b/ports_module/cortex_m4/iar/module_manager/src/tx_thread_system_return.s index 4c5cb6fb..b95770d5 100644 --- a/ports_module/cortex_m4/iar/module_manager/src/tx_thread_system_return.s +++ b/ports_module/cortex_m4/iar/module_manager/src/tx_thread_system_return.s @@ -26,8 +26,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_system_return Cortex-Mx/IAR */ -/* 6.1.8 */ +/* _tx_thread_system_return Cortex-M4/IAR */ +/* 6.1.7 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -59,7 +59,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ +/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ /* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) diff --git a/ports_module/cortex_m4/iar/module_manager/src/tx_timer_interrupt.s b/ports_module/cortex_m4/iar/module_manager/src/tx_timer_interrupt.s index aa209956..f99d1755 100644 --- a/ports_module/cortex_m4/iar/module_manager/src/tx_timer_interrupt.s +++ b/ports_module/cortex_m4/iar/module_manager/src/tx_timer_interrupt.s @@ -39,8 +39,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_timer_interrupt Cortex-Mx/IAR */ -/* 6.1.8 */ +/* _tx_timer_interrupt Cortex-M4/IAR */ +/* 6.1.7 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -73,7 +73,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ +/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ /* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) diff --git a/ports_module/cortex_m4/iar/module_manager/src/txm_module_manager_alignment_adjust.c b/ports_module/cortex_m4/iar/module_manager/src/txm_module_manager_alignment_adjust.c index 514a9c6e..65e04cc1 100644 --- a/ports_module/cortex_m4/iar/module_manager/src/txm_module_manager_alignment_adjust.c +++ b/ports_module/cortex_m4/iar/module_manager/src/txm_module_manager_alignment_adjust.c @@ -30,8 +30,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _txm_power_of_two_block_size Cortex-M4/MPU/IAR */ -/* 6.1 */ +/* _txm_power_of_two_block_size Cortex-M4 */ +/* 6.1.9 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -61,7 +61,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ /* */ /**************************************************************************/ ULONG _txm_power_of_two_block_size(ULONG size) @@ -93,8 +93,8 @@ ULONG _txm_power_of_two_block_size(ULONG size) /* */ /* FUNCTION RELEASE */ /* */ -/* _txm_module_manager_alignment_adjust Cortex-M4/MPU/IAR */ -/* 6.1 */ +/* _txm_module_manager_alignment_adjust Cortex-M4 */ +/* 6.1.9 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -128,7 +128,7 @@ ULONG _txm_power_of_two_block_size(ULONG size) /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ /* */ /**************************************************************************/ VOID _txm_module_manager_alignment_adjust(TXM_MODULE_PREAMBLE *module_preamble, @@ -137,6 +137,53 @@ VOID _txm_module_manager_alignment_adjust(TXM_MODULE_PREAMBLE *module_preamble, ULONG *data_size, ULONG *data_alignment) { +#ifdef TXM_MODULE_MANAGER_16_MPU +ULONG local_code_size; +ULONG local_code_alignment; +ULONG local_data_size; +ULONG local_data_alignment; +ULONG code_size_accum; +ULONG data_size_accum; + + /* Copy the input parameters into local variables for ease of use. */ + local_code_size = *code_size; + local_code_alignment = *code_alignment; + local_data_size = *data_size; + local_data_alignment = *data_alignment; + + /* Determine code block sizes. Minimize the alignment requirement. + There are 4 MPU code entries available. The following is how the code size + will be distributed: + 1. 1/4 of the largest power of two that is greater than or equal to code size. + 2. 1/4 of the largest power of two that is greater than or equal to code size. + 3. Largest power of 2 that fits in the remaining space. + 4. Smallest power of 2 that exceeds the remaining space, minimum 32. */ + local_code_alignment = _txm_power_of_two_block_size(local_code_size) >> 2; + code_size_accum = local_code_alignment + local_code_alignment; + code_size_accum = code_size_accum + (_txm_power_of_two_block_size(local_code_size - code_size_accum) >> 1); + code_size_accum = code_size_accum + _txm_power_of_two_block_size(local_code_size - code_size_accum); + local_code_size = code_size_accum; + + /* Determine data block sizes. Minimize the alignment requirement. + There are 4 MPU data entries available. The following is how the data size + will be distributed: + 1. 1/4 of the largest power of two that is greater than or equal to data size. + 2. 1/4 of the largest power of two that is greater than or equal to data size. + 3. Largest power of 2 that fits in the remaining space. + 4. Smallest power of 2 that exceeds the remaining space, minimum 32. */ + local_data_alignment = _txm_power_of_two_block_size(local_data_size) >> 2; + data_size_accum = local_data_alignment + local_data_alignment; + data_size_accum = data_size_accum + (_txm_power_of_two_block_size(local_data_size - data_size_accum) >> 1); + data_size_accum = data_size_accum + _txm_power_of_two_block_size(local_data_size - data_size_accum); + local_data_size = data_size_accum; + + /* Return all the information to the caller. */ + *code_size = local_code_size; + *code_alignment = local_code_alignment; + *data_size = local_data_size; + *data_alignment = local_data_alignment; + +#else ULONG local_code_size; ULONG local_code_alignment; @@ -396,4 +443,6 @@ ULONG data_size_accum; *code_alignment = local_code_alignment; *data_size = local_data_size; *data_alignment = local_data_alignment; + +#endif } diff --git a/ports_module/cortex_m4/iar/module_manager/src/txm_module_manager_external_memory_enable.c b/ports_module/cortex_m4/iar/module_manager/src/txm_module_manager_external_memory_enable.c index 674c7ce6..79af7655 100644 --- a/ports_module/cortex_m4/iar/module_manager/src/txm_module_manager_external_memory_enable.c +++ b/ports_module/cortex_m4/iar/module_manager/src/txm_module_manager_external_memory_enable.c @@ -33,8 +33,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _txm_module_manager_external_memory_enable Cortex-M4/MPU/IAR */ -/* 6.1 */ +/* _txm_module_manager_external_memory_enable Cortex-M4 */ +/* 6.1.9 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -70,7 +70,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ /* */ /**************************************************************************/ UINT _txm_module_manager_external_memory_enable(TXM_MODULE_INSTANCE *module_instance, @@ -78,6 +78,117 @@ UINT _txm_module_manager_external_memory_enable(TXM_MODULE_INSTANCE *module_ins ULONG length, UINT attributes) { +#ifdef TXM_MODULE_MANAGER_16_MPU +ULONG block_size; +ULONG region_size; +ULONG srd_bits; +ULONG size_register; +ULONG address; +ULONG shared_index; +ULONG attributes_check = 0; + + /* Determine if the module manager has not been initialized yet. */ + if (_txm_module_manager_ready != TX_TRUE) + { + /* Module manager has not been initialized. */ + return(TX_NOT_AVAILABLE); + } + + /* Determine if the module is valid. */ + if (module_instance == TX_NULL) + { + /* Invalid module pointer. */ + return(TX_PTR_ERROR); + } + + /* Get module manager protection mutex. */ + _tx_mutex_get(&_txm_module_manager_mutex, TX_WAIT_FOREVER); + + /* Determine if the module instance is valid. */ + if (module_instance -> txm_module_instance_id != TXM_MODULE_ID) + { + /* Release the protection mutex. */ + _tx_mutex_put(&_txm_module_manager_mutex); + + /* Invalid module pointer. */ + return(TX_PTR_ERROR); + } + + /* Determine if the module instance is in the loaded state. */ + if (module_instance -> txm_module_instance_state != TXM_MODULE_LOADED) + { + /* Release the protection mutex. */ + _tx_mutex_put(&_txm_module_manager_mutex); + + /* Return error if the module is not ready. */ + return(TX_START_ERROR); + } + + /* Determine if there are shared memory entries available. */ + if(module_instance -> txm_module_instance_shared_memory_count >= TXM_MODULE_MPU_SHARED_ENTRIES) + { + /* Release the protection mutex. */ + _tx_mutex_put(&_txm_module_manager_mutex); + + /* No more entries available. */ + return(TX_NO_MEMORY); + } + + /* Start address and length must adhere to Cortex-M7 MPU. + The address must align with the block size. */ + + block_size = _txm_power_of_two_block_size(length); + address = (ULONG) start_address; + if(address != (address & ~(block_size - 1))) + { + /* Release the protection mutex. */ + _tx_mutex_put(&_txm_module_manager_mutex); + + /* Return alignment error. */ + return(TXM_MODULE_ALIGNMENT_ERROR); + } + + /* At this point, we have a valid address and block size. + Set up MPU registers. */ + + /* Pick up index into shared memory entries. */ + shared_index = TXM_MODULE_MPU_SHARED_INDEX + module_instance -> txm_module_instance_shared_memory_count; + + /* Save address register with address, MPU region, set Valid bit. */ + module_instance -> txm_module_instance_mpu_registers[shared_index].txm_module_mpu_region_address = address | shared_index | 0x10; + + /* Calculate the region size. */ + region_size = (_txm_module_manager_region_size_get(block_size) << 1); + + /* Calculate the subregion bits. */ + srd_bits = _txm_module_manager_calculate_srd_bits(block_size, length); + + /* Generate SRD, size, and enable attributes. */ + size_register = srd_bits | region_size | TXM_ENABLE_REGION | TXM_MODULE_MPU_SHARED_ACCESS_CONTROL; + + /* Check for optional write attribute. */ + if(attributes & TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE) + { + attributes_check = TXM_MODULE_MANAGER_ATTRIBUTE_WRITE_MPU_BIT; + } + + /* Save attribute-size register. */ + module_instance -> txm_module_instance_mpu_registers[shared_index].txm_module_mpu_region_attribute_size = attributes_check | size_register; + + /* Keep track of shared memory address and length in module instance. */ + module_instance -> txm_module_instance_shared_memory_address[module_instance -> txm_module_instance_shared_memory_count] = address; + module_instance -> txm_module_instance_shared_memory_length[module_instance -> txm_module_instance_shared_memory_count] = length; + + /* Increment counter. */ + module_instance -> txm_module_instance_shared_memory_count++; + + /* Release the protection mutex. */ + _tx_mutex_put(&_txm_module_manager_mutex); + + /* Return success. */ + return(TX_SUCCESS); + +#else ULONG block_size; ULONG region_size; @@ -179,4 +290,6 @@ TXM_MODULE_PREAMBLE *module_preamble; /* Return success. */ return(TX_SUCCESS); + +#endif } diff --git a/ports_module/cortex_m4/iar/module_manager/src/txm_module_manager_memory_fault_handler.c b/ports_module/cortex_m4/iar/module_manager/src/txm_module_manager_memory_fault_handler.c index 98081a32..47c2b014 100644 --- a/ports_module/cortex_m4/iar/module_manager/src/txm_module_manager_memory_fault_handler.c +++ b/ports_module/cortex_m4/iar/module_manager/src/txm_module_manager_memory_fault_handler.c @@ -45,8 +45,8 @@ TXM_MODULE_MANAGER_FAULT_INFO /* */ /* FUNCTION RELEASE */ /* */ -/* _txm_module_manager_memory_fault_handler Cortex-M4/MPU/IAR */ -/* 6.1 */ +/* _txm_module_manager_memory_fault_handler Cortex-M4 */ +/* 6.1.9 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -76,7 +76,7 @@ TXM_MODULE_MANAGER_FAULT_INFO /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ /* */ /**************************************************************************/ VOID _txm_module_manager_memory_fault_handler(VOID) diff --git a/ports_module/cortex_m4/iar/module_manager/src/txm_module_manager_memory_fault_notify.c b/ports_module/cortex_m4/iar/module_manager/src/txm_module_manager_memory_fault_notify.c index 06905f05..ba5f5bd6 100644 --- a/ports_module/cortex_m4/iar/module_manager/src/txm_module_manager_memory_fault_notify.c +++ b/ports_module/cortex_m4/iar/module_manager/src/txm_module_manager_memory_fault_notify.c @@ -38,8 +38,8 @@ extern VOID (*_txm_module_manager_fault_notify)(TX_THREAD *, TXM_MODULE_INSTA /* */ /* FUNCTION RELEASE */ /* */ -/* _txm_module_manager_memory_fault_notify Cortex-M4/MPU/IAR */ -/* 6.1 */ +/* _txm_module_manager_memory_fault_notify Cortex-M4 */ +/* 6.1.9 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -71,7 +71,7 @@ extern VOID (*_txm_module_manager_fault_notify)(TX_THREAD *, TXM_MODULE_INSTA /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ /* */ /**************************************************************************/ UINT _txm_module_manager_memory_fault_notify(VOID (*notify_function)(TX_THREAD *, TXM_MODULE_INSTANCE *)) diff --git a/ports_module/cortex_m4/iar/module_manager/src/txm_module_manager_mm_register_setup.c b/ports_module/cortex_m4/iar/module_manager/src/txm_module_manager_mm_register_setup.c index 7fea500f..dcc8d2aa 100644 --- a/ports_module/cortex_m4/iar/module_manager/src/txm_module_manager_mm_register_setup.c +++ b/ports_module/cortex_m4/iar/module_manager/src/txm_module_manager_mm_register_setup.c @@ -30,8 +30,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _txm_module_manager_region_size_get Cortex-M4/MPU/IAR */ -/* 6.1 */ +/* _txm_module_manager_region_size_get Cortex-M4 */ +/* 6.1.9 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -61,7 +61,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ /* */ /**************************************************************************/ ULONG _txm_module_manager_region_size_get(ULONG block_size) @@ -152,8 +152,8 @@ ULONG return_value; /* */ /* FUNCTION RELEASE */ /* */ -/* _txm_module_manager_calculate_srd_bits Cortex-M4/MPU/IAR */ -/* 6.1 */ +/* _txm_module_manager_calculate_srd_bits Cortex-M4 */ +/* 6.1.9 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -184,7 +184,7 @@ ULONG return_value; /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ /* */ /**************************************************************************/ ULONG _txm_module_manager_calculate_srd_bits(ULONG block_size, ULONG length) @@ -230,16 +230,48 @@ UINT srd_bit_index; /* */ /* FUNCTION RELEASE */ /* */ -/* _txm_module_manager_mm_register_setup Cortex-M4/MPU/IAR */ -/* 6.1 */ +/* _txm_module_manager_mm_register_setup Cortex-M4 */ +/* 6.1.9 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ /* */ /* DESCRIPTION */ /* */ -/* This function sets up the Cortex-M4 MPU register definitions based */ -/* on the module's memory characteristics. */ +/* This function sets up the MPU register definitions based on the */ +/* module's memory characteristics. */ +/* */ +/* Default MPU layout: */ +/* Entry Description */ +/* 0 Kernel mode entry */ +/* 1 Module code region */ +/* 2 Module code region */ +/* 3 Module code region */ +/* 4 Module code region */ +/* 5 Module data region */ +/* 6 Module data region */ +/* 7 Module data region */ +/* */ +/* If TXM_MODULE_MANAGER_16_MPU is defined, there are 16 MPU slots. */ +/* MPU layout for the Cortex-M7: */ +/* Entry Description */ +/* 0 Kernel mode entry */ +/* 1 Module code region */ +/* 2 Module code region */ +/* 3 Module code region */ +/* 4 Module code region */ +/* 5 Module data region */ +/* 6 Module data region */ +/* 7 Module data region */ +/* 8 Module data region */ +/* 9 Module shared memory region */ +/* 10 Module shared memory region */ +/* 11 Module shared memory region */ +/* 12 Unused region */ +/* 13 Unused region */ +/* 14 Unused region */ +/* 15 Unused region */ +/* */ /* */ /* INPUT */ /* */ @@ -261,11 +293,181 @@ UINT srd_bit_index; /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ /* */ /**************************************************************************/ VOID _txm_module_manager_mm_register_setup(TXM_MODULE_INSTANCE *module_instance) { +#ifdef TXM_MODULE_MANAGER_16_MPU + +ULONG code_address; +ULONG code_size; +ULONG data_address; +ULONG data_size; +ULONG start_stop_stack_size; +ULONG callback_stack_size; +ULONG block_size; +ULONG region_size; +ULONG srd_bits = 0; +UINT mpu_table_index; +UINT i; + + + /* Setup the first MPU region for kernel mode entry. */ + /* Set address register to user mode entry function address, which is guaranteed to be at least 32-byte aligned. + Mask address to proper range, region 0, set Valid bit. */ + module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MPU_KERNEL_ENTRY_INDEX].txm_module_mpu_region_address = ((ULONG) _txm_module_manager_user_mode_entry & 0xFFFFFFE0) | 0x10; + /* Set the attributes, size (32 bytes) and enable bit. */ + module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MPU_KERNEL_ENTRY_INDEX].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_CODE_ACCESS_CONTROL | (_txm_module_manager_region_size_get(32) << 1) | TXM_ENABLE_REGION; + /* End of kernel mode entry setup. */ + + /* Setup code protection. */ + + /* Initialize the MPU table index. */ + mpu_table_index = 1; + + /* Pickup code starting address and actual size. */ + code_address = (ULONG) module_instance -> txm_module_instance_code_start; + code_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_code_size; + + /* Determine code block sizes. Minimize the alignment requirement. + There are 4 MPU code entries available. The following is how the code size + will be distributed: + 1. 1/4 of the largest power of two that is greater than or equal to code size. + 2. 1/4 of the largest power of two that is greater than or equal to code size. + 3. Largest power of 2 that fits in the remaining space. + 4. Smallest power of 2 that exceeds the remaining space, minimum 32. */ + + /* Now loop through to setup MPU protection for the code area. */ + for (i = 0; i < TXM_MODULE_MPU_CODE_ENTRIES; i++) + { + /* First two MPU blocks are 1/4 of the largest power of two + that is greater than or equal to code size. */ + if (i < 2) + { + block_size = _txm_power_of_two_block_size(code_size) >> 2; + } + + /* Third MPU block is the largest power of 2 that fits in the remaining space. */ + else if (i == 2) + { + /* Subtract (block_size*2) from code_size to calculate remaining space. */ + code_size = code_size - (block_size << 1); + block_size = _txm_power_of_two_block_size(code_size) >> 1; + } + + /* Last MPU block is the smallest power of 2 that exceeds the remaining space, minimum 32. */ + else + { + /* Calculate remaining space. */ + code_size = code_size - block_size; + block_size = _txm_power_of_two_block_size(code_size); + srd_bits = _txm_module_manager_calculate_srd_bits(block_size, code_size); + } + + /* Calculate the region size information. */ + region_size = (_txm_module_manager_region_size_get(block_size) << 1); + + /* Build the base address register with address, MPU region, set Valid bit. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_address = (code_address & ~(block_size - 1)) | mpu_table_index | 0x10; + /* Build the attribute-size register with permissions, SRD, size, enable. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_CODE_ACCESS_CONTROL | srd_bits | region_size | TXM_ENABLE_REGION; + + /* Adjust the code address. */ + code_address = code_address + block_size; + + /* Increment MPU table index. */ + mpu_table_index++; + } + /* End of code protection. */ + + /* Setup data protection. */ + + /* Reset SRD bitfield. */ + srd_bits = 0; + + /* Pickup data starting address and actual size. */ + data_address = (ULONG) module_instance -> txm_module_instance_data_start; + + /* Adjust the size of the module elements to be aligned to the default alignment. We do this + so that when we partition the allocated memory, we can simply place these regions right beside + each other without having to align their pointers. Note this only works when they all have + the same alignment. */ + + data_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_data_size; + start_stop_stack_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_start_stop_stack_size; + callback_stack_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_callback_stack_size; + + data_size = ((data_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; + + start_stop_stack_size = ((start_stop_stack_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; + + callback_stack_size = ((callback_stack_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; + + /* Update the data size to include thread stacks. */ + data_size = data_size + start_stop_stack_size + callback_stack_size; + + /* Determine data block sizes. Minimize the alignment requirement. + There are 4 MPU data entries available. The following is how the data size + will be distributed: + 1. 1/4 of the largest power of two that is greater than or equal to data size. + 2. 1/4 of the largest power of two that is greater than or equal to data size. + 3. Largest power of 2 that fits in the remaining space. + 4. Smallest power of 2 that exceeds the remaining space, minimum 32. */ + + /* Now loop through to setup MPU protection for the data area. */ + for (i = 0; i < TXM_MODULE_MPU_DATA_ENTRIES; i++) + { + /* First two MPU blocks are 1/4 of the largest power of two + that is greater than or equal to data size. */ + if (i < 2) + { + block_size = _txm_power_of_two_block_size(data_size) >> 2; + } + + /* Third MPU block is the largest power of 2 that fits in the remaining space. */ + else if (i == 2) + { + /* Subtract (block_size*2) from data_size to calculate remaining space. */ + data_size = data_size - (block_size << 1); + block_size = _txm_power_of_two_block_size(data_size) >> 1; + } + + /* Last MPU block is the smallest power of 2 that exceeds the remaining space, minimum 32. */ + else + { + /* Calculate remaining space. */ + data_size = data_size - block_size; + block_size = _txm_power_of_two_block_size(data_size); + srd_bits = _txm_module_manager_calculate_srd_bits(block_size, data_size); + } + + /* Calculate the region size information. */ + region_size = (_txm_module_manager_region_size_get(block_size) << 1); + + /* Build the base address register with address, MPU region, set Valid bit. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_address = (data_address & ~(block_size - 1)) | mpu_table_index | 0x10; + /* Build the attribute-size register with permissions, SRD, size, enable. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_DATA_ACCESS_CONTROL | srd_bits | region_size | TXM_ENABLE_REGION; + + /* Adjust the data address. */ + data_address = data_address + block_size; + + /* Increment MPU table index. */ + mpu_table_index++; + } + + /* Setup MPU for the remaining regions. */ + while (mpu_table_index < TXM_MODULE_MPU_TOTAL_ENTRIES) + { + /* Build the base address register with address, MPU region, set Valid bit. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_address = mpu_table_index | 0x10; + + /* Increment MPU table index. */ + mpu_table_index++; + } + +#else ULONG code_address; ULONG code_size; @@ -382,7 +584,7 @@ UINT i; for (i = 0; i < TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1; i++) { /* Build the base address register. */ - base_address_register = code_address & ~(block_size - 1) | mpu_register | 0x10; + base_address_register = (code_address & ~(block_size - 1)) | mpu_register | 0x10; /* Check if SRD bits need to be set. */ if (code_size < block_size) @@ -509,4 +711,87 @@ UINT i; /* Increment the MPU register index. */ mpu_register++; } + +#endif +} + +#ifdef TXM_MODULE_MANAGER_16_MPU +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_inside_data_check Cortex-M4 */ +/* 6.1.9 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks if the specified object is inside shared */ +/* memory. */ +/* */ +/* INPUT */ +/* */ +/* module_instance Pointer to module instance */ +/* obj_ptr Pointer to the object */ +/* obj_size Size of the object */ +/* */ +/* OUTPUT */ +/* */ +/* Whether the object is inside the shared memory region. */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Module dispatch check functions */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ +/* */ +/**************************************************************************/ +UINT _txm_module_manager_inside_data_check(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE obj_ptr, UINT obj_size) +{ + +UINT shared_memory_index; +UINT num_shared_memory_mpu_entries; +ALIGN_TYPE shared_memory_address_start; +ALIGN_TYPE shared_memory_address_end; + + /* Check for overflow. */ + if ((obj_ptr) > ((obj_ptr) + (obj_size))) + { + return(TX_FALSE); + } + + /* Check if the object is inside the module data. */ + if ((obj_ptr >= (ALIGN_TYPE) module_instance -> txm_module_instance_data_start) && + ((obj_ptr + obj_size) <= ((ALIGN_TYPE) module_instance -> txm_module_instance_data_end + 1))) + { + return(TX_TRUE); + } + + /* Check if the object is inside the shared memory. */ + num_shared_memory_mpu_entries = module_instance -> txm_module_instance_shared_memory_count; + for (shared_memory_index = 0; shared_memory_index < num_shared_memory_mpu_entries; shared_memory_index++) + { + + shared_memory_address_start = (ALIGN_TYPE) module_instance -> txm_module_instance_shared_memory_address[shared_memory_index]; + shared_memory_address_end = shared_memory_address_start + module_instance -> txm_module_instance_shared_memory_length[shared_memory_index]; + + if ((obj_ptr >= (ALIGN_TYPE) shared_memory_address_start) && + ((obj_ptr + obj_size) <= (ALIGN_TYPE) shared_memory_address_end)) + { + return(TX_TRUE); + } + } + + return(TX_FALSE); } +#endif diff --git a/ports_module/cortex_m4/iar/module_manager/src/txm_module_manager_thread_stack_build.s b/ports_module/cortex_m4/iar/module_manager/src/txm_module_manager_thread_stack_build.s index d5fe691d..c914e201 100644 --- a/ports_module/cortex_m4/iar/module_manager/src/txm_module_manager_thread_stack_build.s +++ b/ports_module/cortex_m4/iar/module_manager/src/txm_module_manager_thread_stack_build.s @@ -26,8 +26,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _txm_module_manager_thread_stack_build Cortex-M4/MPU/IAR */ -/* 6.1.2 */ +/* _txm_module_manager_thread_stack_build Cortex-M4/IAR */ +/* 6.1.9 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -59,9 +59,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 11-09-2020 Scott Larson Modified comment(s), */ -/* resulting in version 6.1.2 */ +/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ /* */ /**************************************************************************/ // VOID _txm_module_manager_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(TX_THREAD *, TXM_MODULE_INSTANCE *)) diff --git a/ports_module/cortex_m7/ac5/inc/tx_port.h b/ports_module/cortex_m7/ac5/inc/tx_port.h index ee66d1fe..ff5a57e3 100644 --- a/ports_module/cortex_m7/ac5/inc/tx_port.h +++ b/ports_module/cortex_m7/ac5/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h Cortex-M7/AC5 */ -/* 6.1.6 */ +/* 6.1.9 */ /* */ /* AUTHOR */ /* */ @@ -47,10 +47,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ -/* macro definition, */ -/* resulting in version 6.1.6 */ +/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ /* */ /**************************************************************************/ @@ -142,7 +139,7 @@ typedef unsigned short USHORT; /* Define the port specific options for the _tx_build_options variable. This variable indicates how the ThreadX library was built. */ -#define TX_PORT_SPECIFIC_BUILD_OPTIONS 0 +#define TX_PORT_SPECIFIC_BUILD_OPTIONS (0) /* Define the in-line initialization constant so that modules with in-line @@ -344,8 +341,6 @@ void _tx_vfp_access(void); #endif - - /* Define the ThreadX object creation extensions for the remaining objects. */ #define TX_BLOCK_POOL_CREATE_EXTENSION(pool_ptr) @@ -386,7 +381,7 @@ ULONG _tx_misra_ipsr_get(VOID); zero after initialization for Cortex-M ports. */ #ifndef TX_THREAD_SYSTEM_RETURN_CHECK -#define TX_THREAD_SYSTEM_RETURN_CHECK(c) (c) = ((ULONG) _tx_thread_preempt_disable); +#define TX_THREAD_SYSTEM_RETURN_CHECK(c) (c) = ((ULONG) _tx_thread_preempt_disable); #endif @@ -452,7 +447,7 @@ unsigned int was_masked; #endif -/* Define FPU extension for the Cortex-M7. Each is assumed to be called in the context of the executing +/* Define FPU extension for the Cortex-M7. Each is assumed to be called in the context of the executing thread. These are no longer needed, but are preserved for backward compatibility only. */ void tx_thread_fpu_enable(void); @@ -463,7 +458,7 @@ void tx_thread_fpu_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M7/AC5 Version 6.1 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M7/AC5 Version 6.1.9 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; @@ -474,7 +469,3 @@ extern CHAR _tx_version_id[]; #endif - - - - diff --git a/ports_module/cortex_m7/ac5/inc/txm_module_port.h b/ports_module/cortex_m7/ac5/inc/txm_module_port.h index 7475d6d6..e7a4e826 100644 --- a/ports_module/cortex_m7/ac5/inc/txm_module_port.h +++ b/ports_module/cortex_m7/ac5/inc/txm_module_port.h @@ -25,8 +25,8 @@ /* */ /* APPLICATION INTERFACE DEFINITION RELEASE */ /* */ -/* txm_module_port.h Cortex-M7/MPU/AC5 */ -/* 6.1.7 */ +/* txm_module_port.h Cortex-M7/AC5 */ +/* 6.1.9 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -40,12 +40,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 11-09-2020 Scott Larson Modified comment(s), */ -/* increase kernel stack size, */ -/* resulting in version 6.1.2 */ -/* 06-02-2021 Scott Larson Added support for 8 MPU, */ -/* resulting in version 6.1.7 */ +/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ /* */ /**************************************************************************/ @@ -96,11 +91,6 @@ The following extensions must also be defined in tx_port.h: VOID (*tx_timer_module_expiration_function)(ULONG id); */ - -/* Size of module heap. */ -#define TXM_MODULE_HEAP_SIZE 512 - - /* Define the kernel stack size for a module thread. */ #ifndef TXM_MODULE_KERNEL_STACK_SIZE #define TXM_MODULE_KERNEL_STACK_SIZE 768 @@ -175,10 +165,10 @@ The following extensions must also be defined in tx_port.h: #define INLINE_DECLARE inline -#ifndef TXM_MODULE_MANAGER_8_MPU +#ifdef TXM_MODULE_MANAGER_16_MPU /* Define the number of MPU entries assigned to the code and data sections. - On Cortex-M7 parts, there are 16 total entries. ThreadX uses one for access + On some Cortex-M7 parts, there are 16 total entries. ThreadX uses one for access to the kernel entry function, thus 15 remain for code and data protection. */ #define TXM_MODULE_MPU_TOTAL_ENTRIES 16 #define TXM_MODULE_MPU_CODE_ENTRIES 4 @@ -208,10 +198,10 @@ typedef struct TXM_MODULE_MPU_INFO_STRUCT ULONG txm_module_instance_shared_memory_address[TXM_MODULE_MPU_SHARED_ENTRIES]; \ ULONG txm_module_instance_shared_memory_length[TXM_MODULE_MPU_SHARED_ENTRIES]; -#else /* TXM_MODULE_MANAGER_8_MPU is defined */ +#else /* TXM_MODULE_MANAGER_16_MPU is not defined */ /* Define the number of MPU entries assigned to the code and data sections. - If TXM_MODULE_MANAGER_8_MPU is defined, there are 8 total entries. ThreadX uses one for access + On Cortex-M3, M4, and some M7 parts, there are 8 total entries. ThreadX uses one for access to the kernel entry function, thus 7 remain for code and data protection. */ #define TXM_MODULE_MANAGER_CODE_MPU_ENTRIES 4 #define TXM_MODULE_MANAGER_DATA_MPU_ENTRIES 3 @@ -229,7 +219,7 @@ typedef struct TXM_MODULE_MPU_INFO_STRUCT ULONG txm_module_instance_shared_memory_address; \ ULONG txm_module_instance_shared_memory_length; -#endif /* TXM_MODULE_MANAGER_8_MPU */ +#endif /* TXM_MODULE_MANAGER_16_MPU */ /* Define the memory fault information structure that is populated when a memory fault occurs. */ @@ -352,7 +342,7 @@ typedef struct TXM_MODULE_MANAGER_MEMORY_FAULT_INFO_STRUCT /* Define the macros to perform port-specific checks when passing pointers to the kernel. */ /* Define macro to make sure object is inside the module's data. */ -#ifndef TXM_MODULE_MANAGER_8_MPU +#ifdef TXM_MODULE_MANAGER_16_MPU #define TXM_MODULE_MANAGER_CHECK_INSIDE_DATA(module_instance, obj_ptr, obj_size) \ _txm_module_manager_inside_data_check(module_instance, obj_ptr, obj_size) #else @@ -386,6 +376,6 @@ UINT _txm_module_manager_inside_data_check(TXM_MODULE_INSTANCE *module_instance #define TXM_MODULE_MANAGER_VERSION_ID \ CHAR _txm_module_manager_version_id[] = \ - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-M7/MPU/AC5 Version 6.1.7 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-M7/AC5 Version 6.1.9 *"; #endif diff --git a/ports_module/cortex_m4/ac5/module_lib/src/txm_module_initialize.S b/ports_module/cortex_m7/ac5/module_lib/src/txm_module_initialize.s index f3952da6..4add8e82 100644 --- a/ports_module/cortex_m4/ac5/module_lib/src/txm_module_initialize.S +++ b/ports_module/cortex_m7/ac5/module_lib/src/txm_module_initialize.s @@ -29,8 +29,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _txm_module_initialize Cortex-M4/MPU/AC5 */ -/* 6.1.2 */ +/* _txm_module_initialize Cortex-M7/AC5 */ +/* 6.1.9 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -59,9 +59,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 11-09-2020 Scott Larson Modified comment(s), */ -/* resulting in version 6.1.2 */ +/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ /* */ /**************************************************************************/ // VOID _txm_module_initialize(VOID) diff --git a/ports_module/cortex_m7/ac5/module_lib/src/txm_module_thread_shell_entry.c b/ports_module/cortex_m7/ac5/module_lib/src/txm_module_thread_shell_entry.c index ffb82204..dec1c02f 100644 --- a/ports_module/cortex_m7/ac5/module_lib/src/txm_module_thread_shell_entry.c +++ b/ports_module/cortex_m7/ac5/module_lib/src/txm_module_thread_shell_entry.c @@ -44,7 +44,9 @@ TXM_MODULE_THREAD_ENTRY_INFO *_txm_module_entry_info; ULONG (*_txm_module_kernel_call_dispatcher)(ULONG kernel_request, ULONG param_1, ULONG param_2, ULONG param3); -/* Define the ARM cstartup code. */ +/* Define the startup code that clears the uninitialized global data and sets up the + preset global variables. */ + extern VOID _txm_module_initialize(VOID); __align(8) UCHAR txm_heap[TXM_MODULE_HEAP_SIZE]; @@ -53,15 +55,15 @@ __align(8) UCHAR txm_heap[TXM_MODULE_HEAP_SIZE]; /* */ /* FUNCTION RELEASE */ /* */ -/* _txm_module_thread_shell_entry Cortex-M7/MPU/AC5 */ -/* 6.1 */ +/* _txm_module_thread_shell_entry Cortex-M7/AC5 */ +/* 6.1.9 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ /* */ /* DESCRIPTION */ /* */ -/* This function calls the specified entry function of the thread. It */ +/* This function calls the specified entry function of the thread. It */ /* also provides a place for the thread's entry function to return. */ /* If the thread returns, this function places the thread in a */ /* "COMPLETED" state. */ @@ -90,7 +92,7 @@ __align(8) UCHAR txm_heap[TXM_MODULE_HEAP_SIZE]; /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ /* */ /**************************************************************************/ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_ENTRY_INFO *thread_info) @@ -105,7 +107,7 @@ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_EN execution. If not, simply skip the C startup code. */ if (thread_info -> txm_module_thread_entry_info_start_thread) { - /* Initialize the ARM C environment. */ + /* Initialize the C environment. */ _txm_module_initialize(); /* Save the entry info pointer, for later use. */ @@ -170,4 +172,3 @@ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_EN TX_SAFETY_CRITICAL_EXCEPTION(__FILE__, __LINE__, 0); #endif } - diff --git a/ports_module/cortex_m7/ac5/module_manager/src/tx_thread_context_restore.S b/ports_module/cortex_m7/ac5/module_manager/src/tx_thread_context_restore.s index 1159ea66..48c7afbf 100644 --- a/ports_module/cortex_m7/ac5/module_manager/src/tx_thread_context_restore.S +++ b/ports_module/cortex_m7/ac5/module_manager/src/tx_thread_context_restore.s @@ -30,8 +30,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_context_restore Cortex-Mx/AC5 */ -/* 6.1.8 */ +/* _tx_thread_context_restore Cortex-M7/AC5 */ +/* 6.1.7 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -61,7 +61,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ +/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ /* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) diff --git a/ports_module/cortex_m4/ac5/module_manager/src/tx_thread_context_save.S b/ports_module/cortex_m7/ac5/module_manager/src/tx_thread_context_save.s index d8ee75a4..1230e4e8 100644 --- a/ports_module/cortex_m4/ac5/module_manager/src/tx_thread_context_save.S +++ b/ports_module/cortex_m7/ac5/module_manager/src/tx_thread_context_save.s @@ -30,8 +30,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_context_save Cortex-Mx/AC5 */ -/* 6.1.8 */ +/* _tx_thread_context_save Cortex-M7/AC5 */ +/* 6.1.7 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -61,7 +61,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ +/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ /* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) diff --git a/ports_module/cortex_m3/ac5/module_manager/src/tx_thread_interrupt_control.S b/ports_module/cortex_m7/ac5/module_manager/src/tx_thread_interrupt_control.s index 4c5e1c33..4aec6856 100644 --- a/ports_module/cortex_m3/ac5/module_manager/src/tx_thread_interrupt_control.S +++ b/ports_module/cortex_m7/ac5/module_manager/src/tx_thread_interrupt_control.s @@ -25,8 +25,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_interrupt_control Cortex-Mx/AC5 */ -/* 6.1.8 */ +/* _tx_thread_interrupt_control Cortex-M7/AC5 */ +/* 6.1.7 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -56,7 +56,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ +/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ /* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) diff --git a/ports_module/cortex_m7/ac5/module_manager/src/tx_thread_interrupt_disable.S b/ports_module/cortex_m7/ac5/module_manager/src/tx_thread_interrupt_disable.s index 88e6a864..1e620791 100644 --- a/ports_module/cortex_m7/ac5/module_manager/src/tx_thread_interrupt_disable.S +++ b/ports_module/cortex_m7/ac5/module_manager/src/tx_thread_interrupt_disable.s @@ -25,8 +25,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_interrupt_disable Cortex-Mx/AC5 */ -/* 6.1.8 */ +/* _tx_thread_interrupt_disable Cortex-M7/AC5 */ +/* 6.1.7 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -56,7 +56,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ +/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ /* */ /**************************************************************************/ // UINT _tx_thread_interrupt_disable(VOID) diff --git a/ports_module/cortex_m4/ac5/module_manager/src/tx_thread_interrupt_restore.S b/ports_module/cortex_m7/ac5/module_manager/src/tx_thread_interrupt_restore.s index 22340c21..c3e8e9a7 100644 --- a/ports_module/cortex_m4/ac5/module_manager/src/tx_thread_interrupt_restore.S +++ b/ports_module/cortex_m7/ac5/module_manager/src/tx_thread_interrupt_restore.s @@ -25,8 +25,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_interrupt_restore Cortex-Mx/AC5 */ -/* 6.1.8 */ +/* _tx_thread_interrupt_restore Cortex-M7/AC5 */ +/* 6.1.7 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -56,7 +56,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ +/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ /* */ /**************************************************************************/ // VOID _tx_thread_interrupt_restore(UINT previous_posture) diff --git a/ports_module/cortex_m3/ac5/module_manager/src/tx_thread_schedule.S b/ports_module/cortex_m7/ac5/module_manager/src/tx_thread_schedule.s index a749235a..016cdcae 100644 --- a/ports_module/cortex_m3/ac5/module_manager/src/tx_thread_schedule.S +++ b/ports_module/cortex_m7/ac5/module_manager/src/tx_thread_schedule.s @@ -23,12 +23,11 @@ IMPORT _tx_thread_current_ptr IMPORT _tx_thread_execute_ptr IMPORT _tx_timer_time_slice - IMPORT _tx_thread_system_stack_ptr - IMPORT _tx_thread_preempt_disable #if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) IMPORT _tx_execution_thread_enter IMPORT _tx_execution_thread_exit #endif + IMPORT _tx_thread_preempt_disable IMPORT _txm_module_manager_memory_fault_handler IMPORT _txm_module_manager_memory_fault_info IMPORT _txm_module_priv @@ -40,8 +39,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_schedule Cortex-M3/MPU/AC5 */ -/* 6.1 */ +/* _tx_thread_schedule Cortex-M7/AC5 */ +/* 6.1.9 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -74,7 +73,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ /* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) @@ -92,6 +91,13 @@ _tx_thread_schedule LDR r2, =_tx_thread_preempt_disable // Build address of preempt disable flag STR r0, [r2, #0] // Clear preempt disable flag +#ifdef __TARGET_FPU_VFP + /* Clear CONTROL.FPCA bit so VFP registers aren't unnecessarily stacked. */ + MRS r0, CONTROL // Pickup current CONTROL register + BIC r0, r0, #4 // Clear the FPCA bit + MSR CONTROL, r0 // Setup new CONTROL register +#endif + /* Enable memory fault registers. */ LDR r0, =0xE000ED24 // Build SHCSR address LDR r1, =0x70000 // Enable Usage, Bus, and MemManage faults @@ -177,6 +183,13 @@ MemManage_Handler // Bit 7 = 1 -> MMFAR is valid STRB r1, [r0] // Clear the MMFSR +#ifdef __TARGET_FPU_VFP + LDR r0, =0xE000EF34 // Cleanup FPU context: Load FPCCR address + LDR r1, [r0] // Load FPCCR + BIC r1, r1, #1 // Clear the lazy preservation active bit + STR r1, [r0] // Save FPCCR +#endif + BL _txm_module_manager_memory_fault_handler // Call memory manager fault handler #if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) @@ -234,6 +247,12 @@ __tx_ts_handler STR r3, [r0] // Set _tx_thread_current_ptr to NULL MRS r12, PSP // Pickup PSP pointer (thread's stack pointer) STMDB r12!, {r4-r11} // Save its remaining registers +#ifdef __TARGET_FPU_VFP + TST LR, #0x10 // Determine if the VFP extended frame is present + BNE _skip_vfp_save + VSTMDB r12!,{s16-s31} // Yes, save additional VFP registers +_skip_vfp_save +#endif LDR r4, =_tx_timer_time_slice // Build address of time-slice variable STMDB r12!, {LR} // Save LR on the stack @@ -259,16 +278,42 @@ __tx_ts_new CPSID i // Disable interrupts LDR r1, [r2] // Is there another thread ready to execute? - CBZ r1, __tx_ts_wait // No, skip to the wait processing + CBNZ r1, __tx_ts_restore // Yes, schedule it + + /* The following is the idle wait processing... in this case, no threads are ready for execution and the + system will simply be idle until an interrupt occurs that makes a thread ready. Note that interrupts + are disabled to allow use of WFI for waiting for a thread to arrive. */ + +__tx_ts_wait + CPSID i // Disable interrupts + LDR r1, [r2] // Pickup the next thread to execute pointer + CBNZ r1, __tx_ts_ready // If non-NULL, a new thread is ready! +#ifdef TX_ENABLE_WFI + DSB // Ensure no outstanding memory transactions + WFI // Wait for interrupt + ISB // Ensure pipeline is flushed +#endif + CPSIE i // Enable interrupts + B __tx_ts_wait // Loop to continue waiting - /* Yes, another thread is ready for else, make the current thread the new thread. */ + /* At this point, we have a new thread ready to go. Clear any newly pended PendSV - since we are + already in the handler! */ + +__tx_ts_ready + MOV r7, #0x08000000 // Build clear PendSV value + MOV r8, #0xE000E000 // Build base NVIC address + STR r7, [r8, #0xD04] // Clear any PendSV + +__tx_ts_restore + + /* A thread is ready, make the current thread the new thread + and enable interrupts. */ STR r1, [r0] // Setup the current thread pointer to the new thread CPSIE i // Enable interrupts /* Increment the thread run count. */ -__tx_ts_restore LDR r7, [r1, #4] // Pickup the current thread run count LDR r4, =_tx_timer_time_slice // Build address of time-slice variable LDR r5, [r1, #24] // Pickup thread's current time-slice @@ -307,15 +352,32 @@ __tx_ts_restore // Use alias registers to quickly load MPU ADD r0, r0, #100 // Build address of MPU register start in thread control block +#ifdef TXM_MODULE_MANAGER_16_MPU + LDM r0!,{r2-r9} // Load MPU regions 0-3 + STM r1,{r2-r9} // Store MPU regions 0-3 + LDM r0!,{r2-r9} // Load MPU regions 4-7 + STM r1,{r2-r9} // Store MPU regions 4-7 + LDM r0!,{r2-r9} // Load MPU regions 8-11 + STM r1,{r2-r9} // Store MPU regions 8-11 + LDM r0,{r2-r9} // Load MPU regions 12-15 + STM r1,{r2-r9} // Store MPU regions 12-15 +#else LDM r0!,{r2-r9} // Load first four MPU regions STM r1,{r2-r9} // Store first four MPU regions LDM r0,{r2-r9} // Load second four MPU regions STM r1,{r2-r9} // Store second four MPU regions +#endif LDR r0, =0xE000ED94 // Build MPU control reg address MOV r1, #5 // Build enable value with background region enabled STR r1, [r0] // Enable MPU skip_mpu_setup LDMIA r12!, {LR} // Pickup LR +#ifdef __TARGET_FPU_VFP + TST LR, #0x10 // Determine if the VFP extended frame is present + BNE _skip_vfp_restore // If not, skip VFP restore + VLDMIA r12!, {s16-s31} // Yes, restore additional VFP registers +_skip_vfp_restore +#endif LDMIA r12!, {r4-r11} // Recover thread's registers MSR PSP, r12 // Setup the thread's stack pointer @@ -323,51 +385,6 @@ skip_mpu_setup BX lr // Return to thread! - /* The following is the idle wait processing... in this case, no threads are ready for execution and the - system will simply be idle until an interrupt occurs that makes a thread ready. Note that interrupts - are disabled to allow use of WFI for waiting for a thread to arrive. */ - -__tx_ts_wait - CPSID i // Disable interrupts - LDR r1, [r2] // Pickup the next thread to execute pointer - STR r1, [r0] // Store it in the current pointer - CBNZ r1, __tx_ts_ready // If non-NULL, a new thread is ready! - -#ifdef TX_LOW_POWER - PUSH {r0-r3} - BL tx_low_power_enter // Possibly enter low power mode - POP {r0-r3} -#endif - -#ifdef TX_ENABLE_WFI - DSB // Ensure no outstanding memory transactions - WFI // Wait for interrupt - ISB // Ensure pipeline is flushed -#endif - -#ifdef TX_LOW_POWER - PUSH {r0-r3} - BL tx_low_power_exit // Exit low power mode - POP {r0-r3} -#endif - - CPSIE i // Enable interrupts - B __tx_ts_wait // Loop to continue waiting - - /* At this point, we have a new thread ready to go. Clear any newly pended PendSV - since we are - already in the handler! */ - -__tx_ts_ready - MOV r7, #0x08000000 // Build clear PendSV value - MOV r8, #0xE000E000 // Build base NVIC address - STR r7, [r8, #0xD04] // Clear any PendSV - - /* Re-enable interrupts and restore new thread. */ - - CPSIE i // Enable interrupts - B __tx_ts_restore // Restore the thread -// } - /* SVC Handler. */ @@ -387,8 +404,8 @@ __tx_SVCallHandler /* At this point we have an SVC 1, which means we are entering the kernel from a module thread with user mode selected. */ - LDR r2, =_txm_module_priv // Subtract 1 because of THUMB mode. - SUB r2, r2, #1 // Temporary fix until ARM describes how to load label above correctly. + LDR r2, =_txm_module_priv // Load address of where we should have come from + SUB r2, r2, #1 // Subtract 1 because of THUMB mode. CMP r1, r2 // Did we come from user_mode_entry? IT NE // If no (not equal), then... BXNE lr // return from where we came. @@ -417,7 +434,16 @@ __tx_SVCallHandler #endif MRS r3, PSP // Pickup thread stack pointer +#ifdef __TARGET_FPU_VFP + TST lr, #0x10 // Test for extended module stack + ITT EQ + ORREQ r3, r3, #1 // If so, set LSB in thread stack pointer to indicate extended frame + ORREQ lr, lr, #0x10 // Set bit, return with standard frame +#endif STR r3, [r2, #0xB0] // Save thread stack pointer +#ifdef __TARGET_FPU_VFP + BIC r3, #1 // Clear possibly OR'd bit +#endif /* Build kernel stack by copying thread stack two registers at a time */ ADD r3, r3, #32 // Start at bottom of hardware stack @@ -439,8 +465,8 @@ _tx_skip_kernel_stack_enter BX lr // Return to thread _tx_thread_user_return - LDR r2, =_txm_module_user_mode_exit // Subtract 1 because of THUMB mode. - SUB r2, r2, #1 // Temporary fix until ARM describes how to load label above correctly. + LDR r2, =_txm_module_user_mode_exit // Load address of where we should have come from + SUB r2, r2, #1 // Subtract 1 because of THUMB mode. CMP r1, r2 // Did we come from user_mode_exit? IT NE // If no (not equal), then... BXNE lr // return from where we came @@ -464,8 +490,38 @@ _tx_thread_user_return STR r1, [r2, #16] // Set stack end STR r3, [r2, #20] // Set stack size #endif + +#ifdef __TARGET_FPU_VFP + /* If lazy stacking is pending, check if it can be cleared. + if(LSPACT && tx_thread_module_stack_start < FPCAR && FPCAR < tx_thread_module_stack_end) + then clear LSPACT. */ + LDR r3, =0xE000EF34 // Address of FPCCR + LDR r3, [r3] // Load FPCCR + TST r3, #1 // Check if LSPACT is set + BEQ _tx_no_lazy_clear // if clear, move on + LDR r1, =0xE000EF38 // Address of FPCAR + LDR r1, [r1] // Load FPCAR + LDR r0, [r2, #0xA4] // Load kernel stack start + CMP r1, r0 // If FPCAR < start, move on + BLO _tx_no_lazy_clear + LDR r0, [r2, #0xA8] // Load kernel stack end + CMP r0, r1 // If end < FPCAR, move on + BLO _tx_no_lazy_clear + BIC r3, #1 // Clear LSPACT + LDR r1, =0xE000EF34 // Address of FPCCR + STR r3, [r1] // Save updated FPCCR +_tx_no_lazy_clear: +#endif + LDR r0, [r2, #0xB0] // Load the module thread stack pointer MRS r3, PSP // Pickup kernel stack pointer +#ifdef __TARGET_FPU_VFP + TST r0, #1 // Is module stack extended? + ITTE NE // If so... + BICNE lr, #0x10 // Clear bit, return with extended frame + BICNE r0, #1 // Clear bit that indicates extended module frame + ORREQ lr, lr, #0x10 // Else set bit, return with standard frame +#endif /* Copy kernel hardware stack to module thread stack. */ LDM r3!, {r1-r2} @@ -489,6 +545,23 @@ _tx_skip_kernel_stack_exit MSR CONTROL, r0 // Setup new CONTROL register BX lr // Return to thread +#ifdef __TARGET_FPU_VFP + EXPORT tx_thread_fpu_enable +tx_thread_fpu_enable + EXPORT tx_thread_fpu_disable +tx_thread_fpu_disable + + /* Automatic VPF logic is supported, this function is present only for + backward compatibility purposes and therefore simply returns. */ + + BX LR // Return to caller + + EXPORT _tx_vfp_access +_tx_vfp_access + VMOV.F32 s0, s0 // Simply access the VFP + BX lr // Return to caller + +#endif ALIGN 4 END diff --git a/ports_module/cortex_m4/ac5/module_manager/src/tx_thread_stack_build.S b/ports_module/cortex_m7/ac5/module_manager/src/tx_thread_stack_build.s index 11effa55..6b0a449f 100644 --- a/ports_module/cortex_m4/ac5/module_manager/src/tx_thread_stack_build.S +++ b/ports_module/cortex_m7/ac5/module_manager/src/tx_thread_stack_build.s @@ -25,8 +25,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_stack_build Cortex-Mx/AC5 */ -/* 6.1.8 */ +/* _tx_thread_stack_build Cortex-M7/AC5 */ +/* 6.1.7 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -58,7 +58,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ +/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ /* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) diff --git a/ports_module/cortex_m4/ac5/module_manager/src/tx_thread_system_return.S b/ports_module/cortex_m7/ac5/module_manager/src/tx_thread_system_return.s index 0ab4ae36..26c3d402 100644 --- a/ports_module/cortex_m4/ac5/module_manager/src/tx_thread_system_return.S +++ b/ports_module/cortex_m7/ac5/module_manager/src/tx_thread_system_return.s @@ -25,8 +25,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_system_return Cortex-Mx/AC5 */ -/* 6.1.8 */ +/* _tx_thread_system_return Cortex-M7/AC5 */ +/* 6.1.7 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -58,7 +58,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ +/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ /* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) diff --git a/ports_module/cortex_m4/ac5/module_manager/src/tx_timer_interrupt.S b/ports_module/cortex_m7/ac5/module_manager/src/tx_timer_interrupt.s index 12fef571..38fec7e4 100644 --- a/ports_module/cortex_m4/ac5/module_manager/src/tx_timer_interrupt.S +++ b/ports_module/cortex_m7/ac5/module_manager/src/tx_timer_interrupt.s @@ -39,8 +39,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_timer_interrupt Cortex-Mx/AC5 */ -/* 6.1.8 */ +/* _tx_timer_interrupt Cortex-M7/AC5 */ +/* 6.1.7 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -73,7 +73,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ +/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ /* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) diff --git a/ports_module/cortex_m7/ac5/module_manager/src/txm_module_manager_alignment_adjust.c b/ports_module/cortex_m7/ac5/module_manager/src/txm_module_manager_alignment_adjust.c index 1f650e6a..cbed8f20 100644 --- a/ports_module/cortex_m7/ac5/module_manager/src/txm_module_manager_alignment_adjust.c +++ b/ports_module/cortex_m7/ac5/module_manager/src/txm_module_manager_alignment_adjust.c @@ -30,8 +30,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _txm_power_of_two_block_size Cortex-M7/MPU/AC5 */ -/* 6.1 */ +/* _txm_power_of_two_block_size Cortex-M7 */ +/* 6.1.9 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -61,7 +61,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ /* */ /**************************************************************************/ ULONG _txm_power_of_two_block_size(ULONG size) @@ -93,8 +93,8 @@ ULONG _txm_power_of_two_block_size(ULONG size) /* */ /* FUNCTION RELEASE */ /* */ -/* _txm_module_manager_alignment_adjust Cortex-M7/MPU/AC5 */ -/* 6.1.7 */ +/* _txm_module_manager_alignment_adjust Cortex-M7 */ +/* 6.1.9 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -128,9 +128,7 @@ ULONG _txm_power_of_two_block_size(ULONG size) /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 06-02-2021 Scott Larson Added support for 8 MPU, */ -/* resulting in version 6.1.7 */ +/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ /* */ /**************************************************************************/ VOID _txm_module_manager_alignment_adjust(TXM_MODULE_PREAMBLE *module_preamble, @@ -139,7 +137,7 @@ VOID _txm_module_manager_alignment_adjust(TXM_MODULE_PREAMBLE *module_preamble, ULONG *data_size, ULONG *data_alignment) { -#ifndef TXM_MODULE_MANAGER_8_MPU +#ifdef TXM_MODULE_MANAGER_16_MPU ULONG local_code_size; ULONG local_code_alignment; ULONG local_data_size; diff --git a/ports_module/cortex_m7/ac5/module_manager/src/txm_module_manager_external_memory_enable.c b/ports_module/cortex_m7/ac5/module_manager/src/txm_module_manager_external_memory_enable.c index 36d5fb9c..138a4463 100644 --- a/ports_module/cortex_m7/ac5/module_manager/src/txm_module_manager_external_memory_enable.c +++ b/ports_module/cortex_m7/ac5/module_manager/src/txm_module_manager_external_memory_enable.c @@ -33,8 +33,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _txm_module_manager_external_memory_enable Cortex-M7/MPU/AC5 */ -/* 6.1.7 */ +/* _txm_module_manager_external_memory_enable Cortex-M7 */ +/* 6.1.9 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -60,6 +60,7 @@ /* _tx_mutex_get Get protection mutex */ /* _tx_mutex_put Release protection mutex */ /* _txm_power_of_two_block_size Round length to power of two */ +/* _txm_module_manager_mm_register_setup Reconfigure MPU registers */ /* */ /* CALLED BY */ /* */ @@ -69,9 +70,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 06-02-2021 Scott Larson Added support for 8 MPU, */ -/* resulting in verison 6.1.7 */ +/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ /* */ /**************************************************************************/ UINT _txm_module_manager_external_memory_enable(TXM_MODULE_INSTANCE *module_instance, @@ -79,7 +78,7 @@ UINT _txm_module_manager_external_memory_enable(TXM_MODULE_INSTANCE *module_ins ULONG length, UINT attributes) { -#ifndef TXM_MODULE_MANAGER_8_MPU +#ifdef TXM_MODULE_MANAGER_16_MPU ULONG block_size; ULONG region_size; ULONG srd_bits; diff --git a/ports_module/cortex_m7/ac5/module_manager/src/txm_module_manager_memory_fault_handler.c b/ports_module/cortex_m7/ac5/module_manager/src/txm_module_manager_memory_fault_handler.c index 7f4401c6..4f58261b 100644 --- a/ports_module/cortex_m7/ac5/module_manager/src/txm_module_manager_memory_fault_handler.c +++ b/ports_module/cortex_m7/ac5/module_manager/src/txm_module_manager_memory_fault_handler.c @@ -45,8 +45,8 @@ TXM_MODULE_MANAGER_FAULT_INFO /* */ /* FUNCTION RELEASE */ /* */ -/* _txm_module_manager_memory_fault_handler Cortex-M7/MPU/AC5 */ -/* 6.1 */ +/* _txm_module_manager_memory_fault_handler Cortex-M7 */ +/* 6.1.9 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -76,7 +76,7 @@ TXM_MODULE_MANAGER_FAULT_INFO /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ /* */ /**************************************************************************/ VOID _txm_module_manager_memory_fault_handler(VOID) diff --git a/ports_module/cortex_m7/ac5/module_manager/src/txm_module_manager_memory_fault_notify.c b/ports_module/cortex_m7/ac5/module_manager/src/txm_module_manager_memory_fault_notify.c index acecfef9..8391c1c2 100644 --- a/ports_module/cortex_m7/ac5/module_manager/src/txm_module_manager_memory_fault_notify.c +++ b/ports_module/cortex_m7/ac5/module_manager/src/txm_module_manager_memory_fault_notify.c @@ -38,8 +38,8 @@ extern VOID (*_txm_module_manager_fault_notify)(TX_THREAD *, TXM_MODULE_INSTA /* */ /* FUNCTION RELEASE */ /* */ -/* _txm_module_manager_memory_fault_notify Cortex-M7/MPU/AC5 */ -/* 6.1 */ +/* _txm_module_manager_memory_fault_notify Cortex-M7 */ +/* 6.1.9 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -71,7 +71,7 @@ extern VOID (*_txm_module_manager_fault_notify)(TX_THREAD *, TXM_MODULE_INSTA /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ /* */ /**************************************************************************/ UINT _txm_module_manager_memory_fault_notify(VOID (*notify_function)(TX_THREAD *, TXM_MODULE_INSTANCE *)) diff --git a/ports_module/cortex_m7/ac5/module_manager/src/txm_module_manager_mm_register_setup.c b/ports_module/cortex_m7/ac5/module_manager/src/txm_module_manager_mm_register_setup.c index fdae069b..bfffa5bc 100644 --- a/ports_module/cortex_m7/ac5/module_manager/src/txm_module_manager_mm_register_setup.c +++ b/ports_module/cortex_m7/ac5/module_manager/src/txm_module_manager_mm_register_setup.c @@ -30,8 +30,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _txm_module_manager_region_size_get Cortex-M7/MPU/AC5 */ -/* 6.1 */ +/* _txm_module_manager_region_size_get Cortex-M7 */ +/* 6.1.9 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -61,7 +61,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ /* */ /**************************************************************************/ ULONG _txm_module_manager_region_size_get(ULONG block_size) @@ -152,8 +152,8 @@ ULONG return_value; /* */ /* FUNCTION RELEASE */ /* */ -/* _txm_module_manager_calculate_srd_bits Cortex-M7/MPU/AC5 */ -/* 6.1 */ +/* _txm_module_manager_calculate_srd_bits Cortex-M7 */ +/* 6.1.9 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -184,7 +184,7 @@ ULONG return_value; /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ /* */ /**************************************************************************/ ULONG _txm_module_manager_calculate_srd_bits(ULONG block_size, ULONG length) @@ -230,8 +230,8 @@ UINT srd_bit_index; /* */ /* FUNCTION RELEASE */ /* */ -/* _txm_module_manager_mm_register_setup Cortex-M7/MPU/AC5 */ -/* 6.1 */ +/* _txm_module_manager_mm_register_setup Cortex-M7 */ +/* 6.1.9 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -240,6 +240,19 @@ UINT srd_bit_index; /* */ /* This function sets up the MPU register definitions based on the */ /* module's memory characteristics. */ +/* */ +/* Default MPU layout: */ +/* Entry Description */ +/* 0 Kernel mode entry */ +/* 1 Module code region */ +/* 2 Module code region */ +/* 3 Module code region */ +/* 4 Module code region */ +/* 5 Module data region */ +/* 6 Module data region */ +/* 7 Module data region */ +/* */ +/* If TXM_MODULE_MANAGER_16_MPU is defined, there are 16 MPU slots. */ /* MPU layout for the Cortex-M7: */ /* Entry Description */ /* 0 Kernel mode entry */ @@ -259,7 +272,6 @@ UINT srd_bit_index; /* 14 Unused region */ /* 15 Unused region */ /* */ -/* If TXM_MODULE_MANAGER_8_MPU is defined, there are only 8 MPU slots. */ /* */ /* INPUT */ /* */ @@ -281,14 +293,12 @@ UINT srd_bit_index; /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 06-02-2021 Scott Larson Added support for 8 MPU, */ -/* resulting in version 6.1.7 */ +/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ /* */ /**************************************************************************/ VOID _txm_module_manager_mm_register_setup(TXM_MODULE_INSTANCE *module_instance) { -#ifndef TXM_MODULE_MANAGER_8_MPU +#ifdef TXM_MODULE_MANAGER_16_MPU ULONG code_address; ULONG code_size; @@ -574,7 +584,7 @@ UINT i; for (i = 0; i < TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1; i++) { /* Build the base address register. */ - base_address_register = code_address & ~(block_size - 1) | mpu_register | 0x10; + base_address_register = (code_address & ~(block_size - 1)) | mpu_register | 0x10; /* Check if SRD bits need to be set. */ if (code_size < block_size) @@ -705,13 +715,13 @@ UINT i; #endif } -#ifndef TXM_MODULE_MANAGER_8_MPU +#ifdef TXM_MODULE_MANAGER_16_MPU /**************************************************************************/ /* */ /* FUNCTION RELEASE */ /* */ -/* _txm_module_manager_inside_data_check Cortex-M7/MPU/AC5 */ -/* 6.1.6 */ +/* _txm_module_manager_inside_data_check Cortex-M7 */ +/* 6.1.9 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -743,10 +753,7 @@ UINT i; /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 04-02-2021 Scott Larson Modified comments, added */ -/* check for overflow, */ -/* resulting in version 6.1.6 */ +/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ /* */ /**************************************************************************/ UINT _txm_module_manager_inside_data_check(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE obj_ptr, UINT obj_size) diff --git a/ports_module/cortex_m4/ac5/module_manager/src/txm_module_manager_thread_stack_build.S b/ports_module/cortex_m7/ac5/module_manager/src/txm_module_manager_thread_stack_build.s index 62e944a1..755ada6f 100644 --- a/ports_module/cortex_m4/ac5/module_manager/src/txm_module_manager_thread_stack_build.S +++ b/ports_module/cortex_m7/ac5/module_manager/src/txm_module_manager_thread_stack_build.s @@ -26,8 +26,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _txm_module_manager_thread_stack_build Cortex-M4/MPU/AC5 */ -/* 6.1.2 */ +/* _txm_module_manager_thread_stack_build Cortex-M7/AC5 */ +/* 6.1.9 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -59,9 +59,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 11-09-2020 Scott Larson Modified comment(s), */ -/* resulting in version 6.1.2 */ +/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ /* */ /**************************************************************************/ // VOID _txm_module_manager_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(TX_THREAD *, TXM_MODULE_INSTANCE *)) @@ -73,7 +71,7 @@ _txm_module_manager_thread_stack_build on the Cortex-M should look like the following after it is built: Stack Top: - LR Interrupted LR (LR at time of PENDSV) + lr Interrupted lr (lr at time of PENDSV) r4 Initial value for r4 r5 Initial value for r5 r6 Initial value for r6 diff --git a/ports_module/cortex_m4/ac5/module_manager/src/txm_module_manager_user_mode_entry.S b/ports_module/cortex_m7/ac5/module_manager/src/txm_module_manager_user_mode_entry.s index f9b136a2..b58abad1 100644 --- a/ports_module/cortex_m4/ac5/module_manager/src/txm_module_manager_user_mode_entry.S +++ b/ports_module/cortex_m7/ac5/module_manager/src/txm_module_manager_user_mode_entry.s @@ -10,59 +10,57 @@ /**************************************************************************/ -/**************************************************************************/ -/**************************************************************************/ -/** */ -/** ThreadX Component */ -/** */ -/** Module Manager */ -/** */ -/**************************************************************************/ -/**************************************************************************/ +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ IMPORT _txm_module_manager_kernel_dispatch IMPORT _tx_thread_current_ptr AREA ||.text||, CODE, READONLY, ALIGN=5 THUMB -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* _txm_module_manager_user_mode_entry Cortex-M4/MPU/AC5 */ -/* 6.1.2 */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_user_mode_entry Cortex-M7/AC5 */ +/* 6.1.9 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ /* */ -/* DESCRIPTION */ -/* */ -/* This function allows modules to enter kernel mode. */ -/* */ -/* INPUT */ -/* */ -/* None */ -/* */ -/* OUTPUT */ -/* */ -/* None */ -/* */ -/* CALLS */ -/* */ -/* SVC 1 Enter kernel mode */ -/* SVC 2 Exit kernel mode */ -/* */ -/* CALLED BY */ -/* */ -/* Modules in user mode */ -/* */ -/* RELEASE HISTORY */ -/* */ +/* DESCRIPTION */ +/* */ +/* This function allows modules to enter kernel mode. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* SVC 1 Enter kernel mode */ +/* SVC 2 Exit kernel mode */ +/* */ +/* CALLED BY */ +/* */ +/* Modules in user mode */ +/* */ +/* RELEASE HISTORY */ +/* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 11-09-2020 Scott Larson Modified comment(s), */ -/* resulting in version 6.1.2 */ +/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ /* */ /**************************************************************************/ // VOID _txm_module_manager_user_mode_entry(VOID) diff --git a/ports_module/cortex_m7/ac6/inc/tx_port.h b/ports_module/cortex_m7/ac6/inc/tx_port.h index 57a43e48..c5f6fdd5 100644 --- a/ports_module/cortex_m7/ac6/inc/tx_port.h +++ b/ports_module/cortex_m7/ac6/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h Cortex-M7/AC6 */ -/* 6.1 */ +/* 6.1.9 */ /* */ /* AUTHOR */ /* */ @@ -47,10 +47,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ -/* macro definition, */ -/* resulting in version 6.1.6 */ +/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ /* */ /**************************************************************************/ @@ -142,7 +139,7 @@ typedef unsigned short USHORT; /* Define the port specific options for the _tx_build_options variable. This variable indicates how the ThreadX library was built. */ -#define TX_PORT_SPECIFIC_BUILD_OPTIONS 0 +#define TX_PORT_SPECIFIC_BUILD_OPTIONS (0) /* Define the in-line initialization constant so that modules with in-line @@ -405,6 +402,7 @@ ULONG _tx_misra_ipsr_get(VOID); #define TX_THREAD_SYSTEM_RETURN_CHECK(c) (c) = ((ULONG) _tx_thread_preempt_disable); #endif + /* Define the macro to ensure _tx_thread_preempt_disable is set early in initialization in order to prevent early scheduling on Cortex-M parts. */ @@ -510,7 +508,7 @@ void tx_thread_fpu_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M7/AC6 Version 6.1.6 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M7/AC6 Version 6.1.9 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_module/cortex_m7/ac6/inc/txm_module_port.h b/ports_module/cortex_m7/ac6/inc/txm_module_port.h index 47ec932e..1347c859 100644 --- a/ports_module/cortex_m7/ac6/inc/txm_module_port.h +++ b/ports_module/cortex_m7/ac6/inc/txm_module_port.h @@ -25,8 +25,8 @@ /* */ /* APPLICATION INTERFACE DEFINITION RELEASE */ /* */ -/* txm_module_port.h Cortex-M7/MPU/AC6 */ -/* 6.1.7 */ +/* txm_module_port.h Cortex-M7/AC6 */ +/* 6.1.9 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -40,11 +40,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 11-09-2020 Scott Larson Modified comment(s), */ -/* resulting in version 6.1.2 */ -/* 06-02-2021 Scott Larson Added support for 8 MPU, */ -/* resulting in version 6.1.7 */ +/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ /* */ /**************************************************************************/ @@ -169,10 +165,10 @@ The following extensions must also be defined in tx_port.h: #define INLINE_DECLARE inline -#ifndef TXM_MODULE_MANAGER_8_MPU +#ifdef TXM_MODULE_MANAGER_16_MPU /* Define the number of MPU entries assigned to the code and data sections. - On Cortex-M7 parts, there are 16 total entries. ThreadX uses one for access + On some Cortex-M7 parts, there are 16 total entries. ThreadX uses one for access to the kernel entry function, thus 15 remain for code and data protection. */ #define TXM_MODULE_MPU_TOTAL_ENTRIES 16 #define TXM_MODULE_MPU_CODE_ENTRIES 4 @@ -202,10 +198,10 @@ typedef struct TXM_MODULE_MPU_INFO_STRUCT ULONG txm_module_instance_shared_memory_address[TXM_MODULE_MPU_SHARED_ENTRIES]; \ ULONG txm_module_instance_shared_memory_length[TXM_MODULE_MPU_SHARED_ENTRIES]; -#else /* TXM_MODULE_MANAGER_8_MPU is defined */ +#else /* TXM_MODULE_MANAGER_16_MPU is not defined */ /* Define the number of MPU entries assigned to the code and data sections. - On Cortex-M4 parts, there are 8 total entries. ThreadX uses one for access + On Cortex-M3, M4, and some M7 parts, there are 8 total entries. ThreadX uses one for access to the kernel entry function, thus 7 remain for code and data protection. */ #define TXM_MODULE_MANAGER_CODE_MPU_ENTRIES 4 #define TXM_MODULE_MANAGER_DATA_MPU_ENTRIES 3 @@ -223,7 +219,7 @@ typedef struct TXM_MODULE_MPU_INFO_STRUCT ULONG txm_module_instance_shared_memory_address; \ ULONG txm_module_instance_shared_memory_length; -#endif /* TXM_MODULE_MANAGER_8_MPU */ +#endif /* TXM_MODULE_MANAGER_16_MPU */ /* Define the memory fault information structure that is populated when a memory fault occurs. */ @@ -346,7 +342,7 @@ typedef struct TXM_MODULE_MANAGER_MEMORY_FAULT_INFO_STRUCT /* Define the macros to perform port-specific checks when passing pointers to the kernel. */ /* Define macro to make sure object is inside the module's data. */ -#ifndef TXM_MODULE_MANAGER_8_MPU +#ifdef TXM_MODULE_MANAGER_16_MPU #define TXM_MODULE_MANAGER_CHECK_INSIDE_DATA(module_instance, obj_ptr, obj_size) \ _txm_module_manager_inside_data_check(module_instance, obj_ptr, obj_size) #else @@ -380,6 +376,6 @@ UINT _txm_module_manager_inside_data_check(TXM_MODULE_INSTANCE *module_instance #define TXM_MODULE_MANAGER_VERSION_ID \ CHAR _txm_module_manager_version_id[] = \ - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-M7/MPU/AC6 Version 6.1.7 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-M7/AC6 Version 6.1.9 *"; #endif diff --git a/ports_module/cortex_m7/ac6/module_lib/src/txm_module_initialize.S b/ports_module/cortex_m7/ac6/module_lib/src/txm_module_initialize.S index 7862a799..23fba265 100644 --- a/ports_module/cortex_m7/ac6/module_lib/src/txm_module_initialize.S +++ b/ports_module/cortex_m7/ac6/module_lib/src/txm_module_initialize.S @@ -32,8 +32,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _txm_module_initialize Cortex-M7/MPU/AC6 */ -/* 6.1.2 */ +/* _txm_module_initialize Cortex-M7/AC6 */ +/* 6.1.9 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -62,9 +62,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Andres Mlinar Initial Version 6.1 */ -/* 11-09-2020 Scott Larson Modified comment(s), */ -/* resulting in version 6.1.2 */ +/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ /* */ /**************************************************************************/ // VOID _txm_module_initialize(VOID) diff --git a/ports_module/cortex_m7/ac6/module_lib/src/txm_module_thread_shell_entry.c b/ports_module/cortex_m7/ac6/module_lib/src/txm_module_thread_shell_entry.c index 0aff1526..bb93a625 100644 --- a/ports_module/cortex_m7/ac6/module_lib/src/txm_module_thread_shell_entry.c +++ b/ports_module/cortex_m7/ac6/module_lib/src/txm_module_thread_shell_entry.c @@ -44,7 +44,9 @@ TXM_MODULE_THREAD_ENTRY_INFO *_txm_module_entry_info; ULONG (*_txm_module_kernel_call_dispatcher)(ULONG kernel_request, ULONG param_1, ULONG param_2, ULONG param3); -/* Define the ARM cstartup code. */ +/* Define the startup code that clears the uninitialized global data and sets up the + preset global variables. */ + extern VOID _txm_module_initialize(VOID); @@ -52,15 +54,15 @@ extern VOID _txm_module_initialize(VOID); /* */ /* FUNCTION RELEASE */ /* */ -/* _txm_module_thread_shell_entry Cortex-M7/MPU/AC6 */ -/* 6.1 */ +/* _txm_module_thread_shell_entry Cortex-M7/AC6 */ +/* 6.1.9 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ /* */ /* DESCRIPTION */ /* */ -/* This function calls the specified entry function of the thread. It */ +/* This function calls the specified entry function of the thread. It */ /* also provides a place for the thread's entry function to return. */ /* If the thread returns, this function places the thread in a */ /* "COMPLETED" state. */ @@ -89,7 +91,7 @@ extern VOID _txm_module_initialize(VOID); /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ /* */ /**************************************************************************/ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_ENTRY_INFO *thread_info) @@ -104,7 +106,7 @@ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_EN execution. If not, simply skip the C startup code. */ if (thread_info -> txm_module_thread_entry_info_start_thread) { - /* Initialize the ARM C environment. */ + /* Initialize the C environment. */ _txm_module_initialize(); /* Save the entry info pointer, for later use. */ @@ -169,4 +171,3 @@ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_EN TX_SAFETY_CRITICAL_EXCEPTION(__FILE__, __LINE__, 0); #endif } - diff --git a/ports_module/cortex_m7/ac6/module_manager/src/tx_thread_context_restore.S b/ports_module/cortex_m7/ac6/module_manager/src/tx_thread_context_restore.S index 17a79b0f..341e8a16 100644 --- a/ports_module/cortex_m7/ac6/module_manager/src/tx_thread_context_restore.S +++ b/ports_module/cortex_m7/ac6/module_manager/src/tx_thread_context_restore.S @@ -31,8 +31,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_context_restore Cortex-Mx/AC6 */ -/* 6.1.8 */ +/* _tx_thread_context_restore Cortex-M7/AC6 */ +/* 6.1.7 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -62,7 +62,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ +/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ /* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) diff --git a/ports_module/cortex_m7/ac6/module_manager/src/tx_thread_context_save.S b/ports_module/cortex_m7/ac6/module_manager/src/tx_thread_context_save.S index 511ca82e..62d8b329 100644 --- a/ports_module/cortex_m7/ac6/module_manager/src/tx_thread_context_save.S +++ b/ports_module/cortex_m7/ac6/module_manager/src/tx_thread_context_save.S @@ -30,8 +30,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_context_save Cortex-Mx/AC6 */ -/* 6.1.8 */ +/* _tx_thread_context_save Cortex-M7/AC6 */ +/* 6.1.7 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -61,7 +61,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ +/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ /* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) diff --git a/ports_module/cortex_m7/ac6/module_manager/src/tx_thread_interrupt_control.S b/ports_module/cortex_m7/ac6/module_manager/src/tx_thread_interrupt_control.S index 07d2a131..0843f69e 100644 --- a/ports_module/cortex_m7/ac6/module_manager/src/tx_thread_interrupt_control.S +++ b/ports_module/cortex_m7/ac6/module_manager/src/tx_thread_interrupt_control.S @@ -27,8 +27,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_interrupt_control Cortex-Mx/AC6 */ -/* 6.1.8 */ +/* _tx_thread_interrupt_control Cortex-M7/AC6 */ +/* 6.1.7 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -58,7 +58,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ +/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ /* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) diff --git a/ports_module/cortex_m7/ac6/module_manager/src/tx_thread_interrupt_disable.S b/ports_module/cortex_m7/ac6/module_manager/src/tx_thread_interrupt_disable.S new file mode 100644 index 00000000..3f36a36a --- /dev/null +++ b/ports_module/cortex_m7/ac6/module_manager/src/tx_thread_interrupt_disable.S @@ -0,0 +1,79 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + .text 32 + .align 4 + .syntax unified +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_interrupt_disable Cortex-M7/AC6 */ +/* 6.1.7 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is responsible for disabling interrupts and returning */ +/* the previous interrupt lockout posture. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* old_posture Old interrupt lockout posture */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ +/* */ +/**************************************************************************/ +// UINT _tx_thread_interrupt_disable(VOID) +// { + .global _tx_thread_interrupt_disable + .thumb_func +_tx_thread_interrupt_disable: + /* Return current interrupt lockout posture. */ +#ifdef TX_PORT_USE_BASEPRI + MRS r0, BASEPRI + LDR r1, =TX_PORT_BASEPRI + MSR BASEPRI, r1 +#else + MRS r0, PRIMASK + CPSID i +#endif + BX lr +// } diff --git a/ports_module/cortex_m7/ac6/module_manager/src/tx_thread_interrupt_restore.S b/ports_module/cortex_m7/ac6/module_manager/src/tx_thread_interrupt_restore.S new file mode 100644 index 00000000..924fa21d --- /dev/null +++ b/ports_module/cortex_m7/ac6/module_manager/src/tx_thread_interrupt_restore.S @@ -0,0 +1,76 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + .text 32 + .align 4 + .syntax unified +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_interrupt_restore Cortex-M7/AC6 */ +/* 6.1.7 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is responsible for restoring the previous */ +/* interrupt lockout posture. */ +/* */ +/* INPUT */ +/* */ +/* previous_posture Previous interrupt posture */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ +/* */ +/**************************************************************************/ +// VOID _tx_thread_interrupt_restore(UINT previous_posture) +// { + .global _tx_thread_interrupt_restore + .thumb_func +_tx_thread_interrupt_restore: + /* Restore previous interrupt lockout posture. */ +#ifdef TX_PORT_USE_BASEPRI + MSR BASEPRI, r0 +#else + MSR PRIMASK, r0 +#endif + BX lr +// } diff --git a/ports_module/cortex_m7/ac6/module_manager/src/tx_thread_schedule.S b/ports_module/cortex_m7/ac6/module_manager/src/tx_thread_schedule.S index d0117b6a..106d7e5e 100644 --- a/ports_module/cortex_m7/ac6/module_manager/src/tx_thread_schedule.S +++ b/ports_module/cortex_m7/ac6/module_manager/src/tx_thread_schedule.S @@ -41,8 +41,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_schedule Cortex-M7/MPU/AC6 */ -/* 6.1.7 */ +/* _tx_thread_schedule Cortex-M7/AC6 */ +/* 6.1.9 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -75,15 +75,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 11-09-2020 Scott Larson Modified comment(s), arrange */ -/* code to fix link error when */ -/* VFP is enabled, resulting */ -/* in version 6.1.2 */ -/* 06-02-2021 Scott Larson Fixed extended stack handling */ -/* when calling kernel APIs, */ -/* added support for 8 MPU, */ -/* resulting in version 6.1.7 */ +/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ /* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) @@ -110,7 +102,6 @@ _tx_thread_schedule: #endif /* Enable memory fault registers. */ - LDR r0, =0xE000ED24 // Build SHCSR address LDR r1, =0x70000 // Enable Usage, Bus, and MemManage faults STR r1, [r0] // @@ -374,7 +365,7 @@ __tx_ts_restore: // Use alias registers to quickly load MPU ADD r0, r0, #100 // Build address of MPU register start in thread control block -#ifndef TXM_MODULE_MANAGER_8_MPU +#ifdef TXM_MODULE_MANAGER_16_MPU LDM r0!,{r2-r9} // Load MPU regions 0-3 STM r1,{r2-r9} // Store MPU regions 0-3 LDM r0!,{r2-r9} // Load MPU regions 4-7 @@ -458,13 +449,17 @@ __tx_SVCallHandler: #endif MRS r3, PSP // Pickup thread stack pointer +#ifdef __ARM_FP TST lr, #0x10 // Test for extended module stack ITT EQ ORREQ r3, r3, #1 // If so, set LSB in thread stack pointer to indicate extended frame ORREQ lr, lr, #0x10 // Set bit, return with standard frame +#endif STR r3, [r2, #0xB0] // Save thread stack pointer +#ifdef __ARM_FP BIC r3, #1 // Clear possibly OR'd bit - +#endif + /* Build kernel stack by copying thread stack two registers at a time */ ADD r3, r3, #32 // Start at bottom of hardware stack LDMDB r3!, {r1-r2} @@ -534,11 +529,13 @@ _tx_no_lazy_clear: LDR r0, [r2, #0xB0] // Load the module thread stack pointer MRS r3, PSP // Pickup kernel stack pointer +#ifdef __ARM_FP TST r0, #1 // Is module stack extended? ITTE NE // If so... BICNE lr, #0x10 // Clear bit, return with extended frame BICNE r0, #1 // Clear bit that indicates extended module frame ORREQ lr, lr, #0x10 // Else set bit, return with standard frame +#endif /* Copy kernel hardware stack to module thread stack. */ LDM r3!, {r1-r2} @@ -563,7 +560,7 @@ _tx_skip_kernel_stack_exit: BX lr // Return to thread - /* Kernel entry function from user mode. */ + /* Kernel entry function from user mode. */ .global _txm_module_manager_kernel_dispatch .align 5 diff --git a/ports_module/cortex_m7/ac6/module_manager/src/tx_thread_stack_build.S b/ports_module/cortex_m7/ac6/module_manager/src/tx_thread_stack_build.S index d50f9243..52c2c207 100644 --- a/ports_module/cortex_m7/ac6/module_manager/src/tx_thread_stack_build.S +++ b/ports_module/cortex_m7/ac6/module_manager/src/tx_thread_stack_build.S @@ -27,8 +27,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_stack_build Cortex-Mx/AC6 */ -/* 6.1.8 */ +/* _tx_thread_stack_build Cortex-M7/AC6 */ +/* 6.1.7 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -60,7 +60,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ +/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ /* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) diff --git a/ports_module/cortex_m7/ac6/module_manager/src/tx_thread_system_return.S b/ports_module/cortex_m7/ac6/module_manager/src/tx_thread_system_return.S index 6560db62..c1b3b9e8 100644 --- a/ports_module/cortex_m7/ac6/module_manager/src/tx_thread_system_return.S +++ b/ports_module/cortex_m7/ac6/module_manager/src/tx_thread_system_return.S @@ -27,8 +27,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_system_return Cortex-Mx/AC6 */ -/* 6.1.8 */ +/* _tx_thread_system_return Cortex-M7/AC6 */ +/* 6.1.7 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -60,7 +60,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ +/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ /* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) diff --git a/ports_module/cortex_m7/ac6/module_manager/src/tx_timer_interrupt.S b/ports_module/cortex_m7/ac6/module_manager/src/tx_timer_interrupt.S index 46f54da0..c8ab5724 100644 --- a/ports_module/cortex_m7/ac6/module_manager/src/tx_timer_interrupt.S +++ b/ports_module/cortex_m7/ac6/module_manager/src/tx_timer_interrupt.S @@ -37,8 +37,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_timer_interrupt Cortex-Mx/AC6 */ -/* 6.1.8 */ +/* _tx_timer_interrupt Cortex-M7/AC6 */ +/* 6.1.7 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -71,7 +71,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ +/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ /* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) diff --git a/ports_module/cortex_m7/ac6/module_manager/src/txm_module_manager_alignment_adjust.c b/ports_module/cortex_m7/ac6/module_manager/src/txm_module_manager_alignment_adjust.c index 8b6a8619..cbed8f20 100644 --- a/ports_module/cortex_m7/ac6/module_manager/src/txm_module_manager_alignment_adjust.c +++ b/ports_module/cortex_m7/ac6/module_manager/src/txm_module_manager_alignment_adjust.c @@ -30,8 +30,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _txm_power_of_two_block_size Cortex-M7/MPU/AC6 */ -/* 6.1 */ +/* _txm_power_of_two_block_size Cortex-M7 */ +/* 6.1.9 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -61,7 +61,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ /* */ /**************************************************************************/ ULONG _txm_power_of_two_block_size(ULONG size) @@ -93,8 +93,8 @@ ULONG _txm_power_of_two_block_size(ULONG size) /* */ /* FUNCTION RELEASE */ /* */ -/* _txm_module_manager_alignment_adjust Cortex-M7/MPU/AC6 */ -/* 6.1.7 */ +/* _txm_module_manager_alignment_adjust Cortex-M7 */ +/* 6.1.9 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -128,9 +128,7 @@ ULONG _txm_power_of_two_block_size(ULONG size) /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 06-02-2021 Scott Larson Added support for 8 MPU, */ -/* resulting in version 6.1.7 */ +/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ /* */ /**************************************************************************/ VOID _txm_module_manager_alignment_adjust(TXM_MODULE_PREAMBLE *module_preamble, @@ -139,7 +137,7 @@ VOID _txm_module_manager_alignment_adjust(TXM_MODULE_PREAMBLE *module_preamble, ULONG *data_size, ULONG *data_alignment) { -#ifndef TXM_MODULE_MANAGER_8_MPU +#ifdef TXM_MODULE_MANAGER_16_MPU ULONG local_code_size; ULONG local_code_alignment; ULONG local_data_size; diff --git a/ports_module/cortex_m7/ac6/module_manager/src/txm_module_manager_external_memory_enable.c b/ports_module/cortex_m7/ac6/module_manager/src/txm_module_manager_external_memory_enable.c index 6c9106ce..138a4463 100644 --- a/ports_module/cortex_m7/ac6/module_manager/src/txm_module_manager_external_memory_enable.c +++ b/ports_module/cortex_m7/ac6/module_manager/src/txm_module_manager_external_memory_enable.c @@ -33,8 +33,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _txm_module_manager_external_memory_enable Cortex-M7/MPU/AC6 */ -/* 6.1.7 */ +/* _txm_module_manager_external_memory_enable Cortex-M7 */ +/* 6.1.9 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -60,6 +60,7 @@ /* _tx_mutex_get Get protection mutex */ /* _tx_mutex_put Release protection mutex */ /* _txm_power_of_two_block_size Round length to power of two */ +/* _txm_module_manager_mm_register_setup Reconfigure MPU registers */ /* */ /* CALLED BY */ /* */ @@ -69,9 +70,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 06-02-2021 Scott Larson Added support for 8 MPU, */ -/* resulting in verison 6.1.7 */ +/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ /* */ /**************************************************************************/ UINT _txm_module_manager_external_memory_enable(TXM_MODULE_INSTANCE *module_instance, @@ -79,7 +78,7 @@ UINT _txm_module_manager_external_memory_enable(TXM_MODULE_INSTANCE *module_ins ULONG length, UINT attributes) { -#ifndef TXM_MODULE_MANAGER_8_MPU +#ifdef TXM_MODULE_MANAGER_16_MPU ULONG block_size; ULONG region_size; ULONG srd_bits; diff --git a/ports_module/cortex_m7/ac6/module_manager/src/txm_module_manager_memory_fault_handler.c b/ports_module/cortex_m7/ac6/module_manager/src/txm_module_manager_memory_fault_handler.c index 23153624..4f58261b 100644 --- a/ports_module/cortex_m7/ac6/module_manager/src/txm_module_manager_memory_fault_handler.c +++ b/ports_module/cortex_m7/ac6/module_manager/src/txm_module_manager_memory_fault_handler.c @@ -45,8 +45,8 @@ TXM_MODULE_MANAGER_FAULT_INFO /* */ /* FUNCTION RELEASE */ /* */ -/* _txm_module_manager_memory_fault_handler Cortex-M7/MPU/AC6 */ -/* 6.1 */ +/* _txm_module_manager_memory_fault_handler Cortex-M7 */ +/* 6.1.9 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -76,7 +76,7 @@ TXM_MODULE_MANAGER_FAULT_INFO /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ /* */ /**************************************************************************/ VOID _txm_module_manager_memory_fault_handler(VOID) diff --git a/ports_module/cortex_m7/ac6/module_manager/src/txm_module_manager_memory_fault_notify.c b/ports_module/cortex_m7/ac6/module_manager/src/txm_module_manager_memory_fault_notify.c index 8118f5fd..8391c1c2 100644 --- a/ports_module/cortex_m7/ac6/module_manager/src/txm_module_manager_memory_fault_notify.c +++ b/ports_module/cortex_m7/ac6/module_manager/src/txm_module_manager_memory_fault_notify.c @@ -38,8 +38,8 @@ extern VOID (*_txm_module_manager_fault_notify)(TX_THREAD *, TXM_MODULE_INSTA /* */ /* FUNCTION RELEASE */ /* */ -/* _txm_module_manager_memory_fault_notify Cortex-M7/MPU/AC6 */ -/* 6.1 */ +/* _txm_module_manager_memory_fault_notify Cortex-M7 */ +/* 6.1.9 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -71,7 +71,7 @@ extern VOID (*_txm_module_manager_fault_notify)(TX_THREAD *, TXM_MODULE_INSTA /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ /* */ /**************************************************************************/ UINT _txm_module_manager_memory_fault_notify(VOID (*notify_function)(TX_THREAD *, TXM_MODULE_INSTANCE *)) diff --git a/ports_module/cortex_m7/ac6/module_manager/src/txm_module_manager_mm_register_setup.c b/ports_module/cortex_m7/ac6/module_manager/src/txm_module_manager_mm_register_setup.c index 24265181..bfffa5bc 100644 --- a/ports_module/cortex_m7/ac6/module_manager/src/txm_module_manager_mm_register_setup.c +++ b/ports_module/cortex_m7/ac6/module_manager/src/txm_module_manager_mm_register_setup.c @@ -30,8 +30,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _txm_module_manager_region_size_get Cortex-M7/MPU/AC6 */ -/* 6.1 */ +/* _txm_module_manager_region_size_get Cortex-M7 */ +/* 6.1.9 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -61,7 +61,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ /* */ /**************************************************************************/ ULONG _txm_module_manager_region_size_get(ULONG block_size) @@ -152,8 +152,8 @@ ULONG return_value; /* */ /* FUNCTION RELEASE */ /* */ -/* _txm_module_manager_calculate_srd_bits Cortex-M7/MPU/AC6 */ -/* 6.1 */ +/* _txm_module_manager_calculate_srd_bits Cortex-M7 */ +/* 6.1.9 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -184,7 +184,7 @@ ULONG return_value; /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ /* */ /**************************************************************************/ ULONG _txm_module_manager_calculate_srd_bits(ULONG block_size, ULONG length) @@ -230,8 +230,8 @@ UINT srd_bit_index; /* */ /* FUNCTION RELEASE */ /* */ -/* _txm_module_manager_mm_register_setup Cortex-M7/MPU/AC6 */ -/* 6.1.7 */ +/* _txm_module_manager_mm_register_setup Cortex-M7 */ +/* 6.1.9 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -240,6 +240,19 @@ UINT srd_bit_index; /* */ /* This function sets up the MPU register definitions based on the */ /* module's memory characteristics. */ +/* */ +/* Default MPU layout: */ +/* Entry Description */ +/* 0 Kernel mode entry */ +/* 1 Module code region */ +/* 2 Module code region */ +/* 3 Module code region */ +/* 4 Module code region */ +/* 5 Module data region */ +/* 6 Module data region */ +/* 7 Module data region */ +/* */ +/* If TXM_MODULE_MANAGER_16_MPU is defined, there are 16 MPU slots. */ /* MPU layout for the Cortex-M7: */ /* Entry Description */ /* 0 Kernel mode entry */ @@ -259,7 +272,6 @@ UINT srd_bit_index; /* 14 Unused region */ /* 15 Unused region */ /* */ -/* If TXM_MODULE_MANAGER_8_MPU is defined, there are only 8 MPU slots. */ /* */ /* INPUT */ /* */ @@ -281,14 +293,12 @@ UINT srd_bit_index; /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 06-02-2021 Scott Larson Added support for 8 MPU, */ -/* resulting in version 6.1.7 */ +/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ /* */ /**************************************************************************/ VOID _txm_module_manager_mm_register_setup(TXM_MODULE_INSTANCE *module_instance) { -#ifndef TXM_MODULE_MANAGER_8_MPU +#ifdef TXM_MODULE_MANAGER_16_MPU ULONG code_address; ULONG code_size; @@ -574,7 +584,7 @@ UINT i; for (i = 0; i < TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1; i++) { /* Build the base address register. */ - base_address_register = code_address & ~(block_size - 1) | mpu_register | 0x10; + base_address_register = (code_address & ~(block_size - 1)) | mpu_register | 0x10; /* Check if SRD bits need to be set. */ if (code_size < block_size) @@ -705,13 +715,13 @@ UINT i; #endif } -#ifndef TXM_MODULE_MANAGER_8_MPU +#ifdef TXM_MODULE_MANAGER_16_MPU /**************************************************************************/ /* */ /* FUNCTION RELEASE */ /* */ -/* _txm_module_manager_inside_data_check Cortex-M7/MPU/AC6 */ -/* 6.1.6 */ +/* _txm_module_manager_inside_data_check Cortex-M7 */ +/* 6.1.9 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -743,10 +753,7 @@ UINT i; /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 04-02-2021 Scott Larson Modified comments, added */ -/* check for overflow, */ -/* resulting in version 6.1.6 */ +/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ /* */ /**************************************************************************/ UINT _txm_module_manager_inside_data_check(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE obj_ptr, UINT obj_size) diff --git a/ports_module/cortex_m7/ac6/module_manager/src/txm_module_manager_thread_stack_build.S b/ports_module/cortex_m7/ac6/module_manager/src/txm_module_manager_thread_stack_build.S index b501733f..cc237ae8 100644 --- a/ports_module/cortex_m7/ac6/module_manager/src/txm_module_manager_thread_stack_build.S +++ b/ports_module/cortex_m7/ac6/module_manager/src/txm_module_manager_thread_stack_build.S @@ -27,8 +27,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _txm_module_manager_thread_stack_build Cortex-M7/MPU/AC6 */ -/* 6.1.2 */ +/* _txm_module_manager_thread_stack_build Cortex-M7/AC6 */ +/* 6.1.9 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -60,9 +60,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 11-09-2020 Scott Larson Modified comment(s), */ -/* resulting in version 6.1.2 */ +/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ /* */ /**************************************************************************/ // VOID _txm_module_manager_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(TX_THREAD *, TXM_MODULE_INSTANCE *)) @@ -112,7 +110,7 @@ _txm_module_manager_thread_stack_build: STR r3, [r2, #28] // Store initial r10 STR r3, [r2, #32] // Store initial r11 - /* Hardware stack follows. */ + /* Hardware stack follows. */ STR r0, [r2, #36] // Store initial r0, which is the thread control block diff --git a/ports_module/cortex_m7/gnu/inc/tx_port.h b/ports_module/cortex_m7/gnu/inc/tx_port.h index d0e61b60..b4e27ddf 100644 --- a/ports_module/cortex_m7/gnu/inc/tx_port.h +++ b/ports_module/cortex_m7/gnu/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h Cortex-M7/GNU */ -/* 6.1 */ +/* 6.1.9 */ /* */ /* AUTHOR */ /* */ @@ -47,10 +47,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ -/* macro definition, */ -/* resulting in version 6.1.6 */ +/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ /* */ /**************************************************************************/ @@ -142,7 +139,7 @@ typedef unsigned short USHORT; /* Define the port specific options for the _tx_build_options variable. This variable indicates how the ThreadX library was built. */ -#define TX_PORT_SPECIFIC_BUILD_OPTIONS 0 +#define TX_PORT_SPECIFIC_BUILD_OPTIONS (0) /* Define the in-line initialization constant so that modules with in-line @@ -405,6 +402,7 @@ ULONG _tx_misra_ipsr_get(VOID); #define TX_THREAD_SYSTEM_RETURN_CHECK(c) (c) = ((ULONG) _tx_thread_preempt_disable); #endif + /* Define the macro to ensure _tx_thread_preempt_disable is set early in initialization in order to prevent early scheduling on Cortex-M parts. */ @@ -504,15 +502,10 @@ void tx_thread_fpu_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M7/GNU Version 6.1.6 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M7/GNU Version 6.1.9 *"; #else extern CHAR _tx_version_id[]; #endif #endif - - - - - diff --git a/ports_module/cortex_m7/gnu/inc/txm_module_port.h b/ports_module/cortex_m7/gnu/inc/txm_module_port.h index 04807d75..8731adfe 100644 --- a/ports_module/cortex_m7/gnu/inc/txm_module_port.h +++ b/ports_module/cortex_m7/gnu/inc/txm_module_port.h @@ -25,8 +25,8 @@ /* */ /* APPLICATION INTERFACE DEFINITION RELEASE */ /* */ -/* txm_module_port.h Cortex-M7/MPU/GNU */ -/* 6.1.7 */ +/* txm_module_port.h Cortex-M7/GNU */ +/* 6.1.9 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -40,11 +40,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 11-09-2020 Scott Larson Modified comment(s), */ -/* resulting in version 6.1.2 */ -/* 06-02-2021 Scott Larson Added support for 8 MPU, */ -/* resulting in version 6.1.7 */ +/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ /* */ /**************************************************************************/ @@ -169,10 +165,10 @@ The following extensions must also be defined in tx_port.h: #define INLINE_DECLARE inline -#ifndef TXM_MODULE_MANAGER_8_MPU +#ifdef TXM_MODULE_MANAGER_16_MPU /* Define the number of MPU entries assigned to the code and data sections. - On Cortex-M7 parts, there are 16 total entries. ThreadX uses one for access + On some Cortex-M7 parts, there are 16 total entries. ThreadX uses one for access to the kernel entry function, thus 15 remain for code and data protection. */ #define TXM_MODULE_MPU_TOTAL_ENTRIES 16 #define TXM_MODULE_MPU_CODE_ENTRIES 4 @@ -202,10 +198,10 @@ typedef struct TXM_MODULE_MPU_INFO_STRUCT ULONG txm_module_instance_shared_memory_address[TXM_MODULE_MPU_SHARED_ENTRIES]; \ ULONG txm_module_instance_shared_memory_length[TXM_MODULE_MPU_SHARED_ENTRIES]; -#else /* TXM_MODULE_MANAGER_8_MPU is defined */ +#else /* TXM_MODULE_MANAGER_16_MPU is not defined */ /* Define the number of MPU entries assigned to the code and data sections. - On some Cortex-M7 parts, there are 8 total entries. ThreadX uses one for access + On Cortex-M3, M4, and some M7 parts, there are 8 total entries. ThreadX uses one for access to the kernel entry function, thus 7 remain for code and data protection. */ #define TXM_MODULE_MANAGER_CODE_MPU_ENTRIES 4 #define TXM_MODULE_MANAGER_DATA_MPU_ENTRIES 3 @@ -223,7 +219,7 @@ typedef struct TXM_MODULE_MPU_INFO_STRUCT ULONG txm_module_instance_shared_memory_address; \ ULONG txm_module_instance_shared_memory_length; -#endif /* TXM_MODULE_MANAGER_8_MPU */ +#endif /* TXM_MODULE_MANAGER_16_MPU */ /* Define the memory fault information structure that is populated when a memory fault occurs. */ @@ -346,7 +342,7 @@ typedef struct TXM_MODULE_MANAGER_MEMORY_FAULT_INFO_STRUCT /* Define the macros to perform port-specific checks when passing pointers to the kernel. */ /* Define macro to make sure object is inside the module's data. */ -#ifndef TXM_MODULE_MANAGER_8_MPU +#ifdef TXM_MODULE_MANAGER_16_MPU #define TXM_MODULE_MANAGER_CHECK_INSIDE_DATA(module_instance, obj_ptr, obj_size) \ _txm_module_manager_inside_data_check(module_instance, obj_ptr, obj_size) #else @@ -380,6 +376,6 @@ UINT _txm_module_manager_inside_data_check(TXM_MODULE_INSTANCE *module_instance #define TXM_MODULE_MANAGER_VERSION_ID \ CHAR _txm_module_manager_version_id[] = \ - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-M7/MPU/GNU Version 6.1.7 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-M7/GNU Version 6.1.9 *"; #endif diff --git a/ports_module/cortex_m7/gnu/module_lib/src/txm_module_thread_shell_entry.c b/ports_module/cortex_m7/gnu/module_lib/src/txm_module_thread_shell_entry.c index 1157f057..04153c0e 100644 --- a/ports_module/cortex_m7/gnu/module_lib/src/txm_module_thread_shell_entry.c +++ b/ports_module/cortex_m7/gnu/module_lib/src/txm_module_thread_shell_entry.c @@ -44,7 +44,7 @@ TXM_MODULE_THREAD_ENTRY_INFO *_txm_module_entry_info; ULONG (*_txm_module_kernel_call_dispatcher)(ULONG kernel_request, ULONG param_1, ULONG param_2, ULONG param3); -/* Define the GCC startup code that clears the uninitialized global data and sets up the +/* Define the startup code that clears the uninitialized global data and sets up the preset global variables. */ extern VOID _gcc_setup(TXM_MODULE_INSTANCE *); @@ -54,15 +54,15 @@ extern VOID _gcc_setup(TXM_MODULE_INSTANCE *); /* */ /* FUNCTION RELEASE */ /* */ -/* _txm_module_thread_shell_entry Cortex-M7/MPU/GNU */ -/* 6.1 */ +/* _txm_module_thread_shell_entry Cortex-M7/GNU */ +/* 6.1.9 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ /* */ /* DESCRIPTION */ /* */ -/* This function calls the specified entry function of the thread. It */ +/* This function calls the specified entry function of the thread. It */ /* also provides a place for the thread's entry function to return. */ /* If the thread returns, this function places the thread in a */ /* "COMPLETED" state. */ @@ -78,7 +78,7 @@ extern VOID _gcc_setup(TXM_MODULE_INSTANCE *); /* */ /* CALLS */ /* */ -/* _gcc_setup GNU global init function */ +/* _gcc_setup cstartup initialization */ /* thread_entry Thread's entry function */ /* tx_thread_resume Resume the module callback thread */ /* _txm_module_thread_system_suspend Module thread suspension routine */ @@ -91,7 +91,7 @@ extern VOID _gcc_setup(TXM_MODULE_INSTANCE *); /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ /* */ /**************************************************************************/ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_ENTRY_INFO *thread_info) @@ -106,7 +106,7 @@ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_EN execution. If not, simply skip the C startup code. */ if (thread_info -> txm_module_thread_entry_info_start_thread) { - /* Initialize the GNU C environment. */ + /* Initialize the C environment. */ _gcc_setup(thread_info -> txm_module_thread_entry_info_code_base_address); /* Save the entry info pointer, for later use. */ @@ -171,4 +171,3 @@ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_EN TX_SAFETY_CRITICAL_EXCEPTION(__FILE__, __LINE__, 0); #endif } - diff --git a/ports_module/cortex_m7/gnu/module_manager/src/tx_thread_context_restore.S b/ports_module/cortex_m7/gnu/module_manager/src/tx_thread_context_restore.S index e445e690..888d5442 100644 --- a/ports_module/cortex_m7/gnu/module_manager/src/tx_thread_context_restore.S +++ b/ports_module/cortex_m7/gnu/module_manager/src/tx_thread_context_restore.S @@ -31,8 +31,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_context_restore Cortex-Mx/GNU */ -/* 6.1.8 */ +/* _tx_thread_context_restore Cortex-M7/GNU */ +/* 6.1.7 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -62,7 +62,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ +/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ /* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) diff --git a/ports_module/cortex_m7/gnu/module_manager/src/tx_thread_context_save.S b/ports_module/cortex_m7/gnu/module_manager/src/tx_thread_context_save.S index e4f2778a..6111ffee 100644 --- a/ports_module/cortex_m7/gnu/module_manager/src/tx_thread_context_save.S +++ b/ports_module/cortex_m7/gnu/module_manager/src/tx_thread_context_save.S @@ -27,8 +27,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_context_save Cortex-Mx/GNU */ -/* 6.1.8 */ +/* _tx_thread_context_save Cortex-M7/GNU */ +/* 6.1.7 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -58,7 +58,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ +/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ /* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) diff --git a/ports_module/cortex_m7/gnu/module_manager/src/tx_thread_interrupt_control.S b/ports_module/cortex_m7/gnu/module_manager/src/tx_thread_interrupt_control.S index 99e14c06..2ea849dc 100644 --- a/ports_module/cortex_m7/gnu/module_manager/src/tx_thread_interrupt_control.S +++ b/ports_module/cortex_m7/gnu/module_manager/src/tx_thread_interrupt_control.S @@ -27,8 +27,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_interrupt_control Cortex-Mx/GNU */ -/* 6.1.8 */ +/* _tx_thread_interrupt_control Cortex-M7/GNU */ +/* 6.1.7 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -58,7 +58,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ +/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ /* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) diff --git a/ports_module/cortex_m7/gnu/module_manager/src/tx_thread_interrupt_disable.S b/ports_module/cortex_m7/gnu/module_manager/src/tx_thread_interrupt_disable.S new file mode 100644 index 00000000..16935d55 --- /dev/null +++ b/ports_module/cortex_m7/gnu/module_manager/src/tx_thread_interrupt_disable.S @@ -0,0 +1,79 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + .text 32 + .align 4 + .syntax unified +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_interrupt_disable Cortex-M7/GNU */ +/* 6.1.7 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is responsible for disabling interrupts and returning */ +/* the previous interrupt lockout posture. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* old_posture Old interrupt lockout posture */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ +/* */ +/**************************************************************************/ +// UINT _tx_thread_interrupt_disable(VOID) +// { + .global _tx_thread_interrupt_disable + .thumb_func +_tx_thread_interrupt_disable: + /* Return current interrupt lockout posture. */ +#ifdef TX_PORT_USE_BASEPRI + MRS r0, BASEPRI + LDR r1, =TX_PORT_BASEPRI + MSR BASEPRI, r1 +#else + MRS r0, PRIMASK + CPSID i +#endif + BX lr +// } diff --git a/ports_module/cortex_m7/gnu/module_manager/src/tx_thread_interrupt_restore.S b/ports_module/cortex_m7/gnu/module_manager/src/tx_thread_interrupt_restore.S new file mode 100644 index 00000000..27f8c5bd --- /dev/null +++ b/ports_module/cortex_m7/gnu/module_manager/src/tx_thread_interrupt_restore.S @@ -0,0 +1,76 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + .text 32 + .align 4 + .syntax unified +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_interrupt_restore Cortex-M7/GNU */ +/* 6.1.7 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is responsible for restoring the previous */ +/* interrupt lockout posture. */ +/* */ +/* INPUT */ +/* */ +/* previous_posture Previous interrupt posture */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ +/* */ +/**************************************************************************/ +// VOID _tx_thread_interrupt_restore(UINT previous_posture) +// { + .global _tx_thread_interrupt_restore + .thumb_func +_tx_thread_interrupt_restore: + /* Restore previous interrupt lockout posture. */ +#ifdef TX_PORT_USE_BASEPRI + MSR BASEPRI, r0 +#else + MSR PRIMASK, r0 +#endif + BX lr +// } diff --git a/ports_module/cortex_m7/gnu/module_manager/src/tx_thread_schedule.S b/ports_module/cortex_m7/gnu/module_manager/src/tx_thread_schedule.S index 99eb2544..ccee84bb 100644 --- a/ports_module/cortex_m7/gnu/module_manager/src/tx_thread_schedule.S +++ b/ports_module/cortex_m7/gnu/module_manager/src/tx_thread_schedule.S @@ -39,8 +39,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_schedule Cortex-M7/MPU/GNU */ -/* 6.1.7 */ +/* _tx_thread_schedule Cortex-M7/GNU */ +/* 6.1.9 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -73,15 +73,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 11-09-2020 Scott Larson Modified comment(s), arrange */ -/* code to fix link error when */ -/* VFP is enabled, resulting */ -/* in version 6.1.2 */ -/* 06-02-2021 Scott Larson Fixed extended stack handling */ -/* when calling kernel APIs, */ -/* added support for 8 MPU, */ -/* resulting in version 6.1.7 */ +/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ /* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) @@ -100,16 +92,14 @@ _tx_thread_schedule: LDR r2, =_tx_thread_preempt_disable // Build address of preempt disable flag STR r0, [r2, #0] // Clear preempt disable flag - /* Clear CONTROL.FPCA bit so VFP registers aren't unnecessarily stacked. */ - #ifdef __ARM_PCS_VFP + /* Clear CONTROL.FPCA bit so VFP registers aren't unnecessarily stacked. */ MRS r0, CONTROL // Pickup current CONTROL register BIC r0, r0, #4 // Clear the FPCA bit MSR CONTROL, r0 // Setup new CONTROL register #endif /* Enable memory fault registers. */ - LDR r0, =0xE000ED24 // Build SHCSR address LDR r1, =0x70000 // Enable Usage, Bus, and MemManage faults STR r1, [r0] // @@ -373,7 +363,7 @@ __tx_ts_restore: // Use alias registers to quickly load MPU ADD r0, r0, #100 // Build address of MPU register start in thread control block -#ifndef TXM_MODULE_MANAGER_8_MPU +#ifdef TXM_MODULE_MANAGER_16_MPU LDM r0!,{r2-r9} // Load MPU regions 0-3 STM r1,{r2-r9} // Store MPU regions 0-3 LDM r0!,{r2-r9} // Load MPU regions 4-7 @@ -458,12 +448,16 @@ __tx_SVCallHandler: #endif MRS r3, PSP // Pickup thread stack pointer +#ifdef __ARM_PCS_VFP TST lr, #0x10 // Test for extended module stack ITT EQ ORREQ r3, r3, #1 // If so, set LSB in thread stack pointer to indicate extended frame ORREQ lr, lr, #0x10 // Set bit, return with standard frame +#endif STR r3, [r2, #0xB0] // Save thread stack pointer +#ifdef __ARM_PCS_VFP BIC r3, #1 // Clear possibly OR'd bit +#endif /* Build kernel stack by copying thread stack two registers at a time */ ADD r3, r3, #32 // Start at bottom of hardware stack @@ -510,6 +504,7 @@ _tx_thread_user_return: STR r3, [r2, #20] // Set stack size #endif +#ifdef __ARM_PCS_VFP /* If lazy stacking is pending, check if it can be cleared. if(LSPACT && tx_thread_module_stack_start < FPCAR && FPCAR < tx_thread_module_stack_end) then clear LSPACT. */ @@ -529,14 +524,17 @@ _tx_thread_user_return: LDR r1, =0xE000EF34 // Address of FPCCR STR r3, [r1] // Save updated FPCCR _tx_no_lazy_clear: +#endif LDR r0, [r2, #0xB0] // Load the module thread stack pointer MRS r3, PSP // Pickup kernel stack pointer +#ifdef __ARM_PCS_VFP TST r0, #1 // Is module stack extended? ITTE NE // If so... BICNE lr, #0x10 // Clear bit, return with extended frame BICNE r0, #1 // Clear bit that indicates extended module frame ORREQ lr, lr, #0x10 // Else set bit, return with standard frame +#endif /* Copy kernel hardware stack to module thread stack. */ LDM r3!, {r1-r2} @@ -561,7 +559,7 @@ _tx_skip_kernel_stack_exit: BX lr // Return to thread - /* Kernel entry function from user mode. */ + /* Kernel entry function from user mode. */ .global _txm_module_manager_kernel_dispatch .align 5 diff --git a/ports_module/cortex_m7/gnu/module_manager/src/tx_thread_stack_build.S b/ports_module/cortex_m7/gnu/module_manager/src/tx_thread_stack_build.S index d0246c13..7c2cb83a 100644 --- a/ports_module/cortex_m7/gnu/module_manager/src/tx_thread_stack_build.S +++ b/ports_module/cortex_m7/gnu/module_manager/src/tx_thread_stack_build.S @@ -27,8 +27,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_stack_build Cortex-Mx/GNU */ -/* 6.1.8 */ +/* _tx_thread_stack_build Cortex-M7/GNU */ +/* 6.1.7 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -60,7 +60,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ +/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ /* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) diff --git a/ports_module/cortex_m7/gnu/module_manager/src/tx_thread_system_return.S b/ports_module/cortex_m7/gnu/module_manager/src/tx_thread_system_return.S index 1f20e1a6..307af29e 100644 --- a/ports_module/cortex_m7/gnu/module_manager/src/tx_thread_system_return.S +++ b/ports_module/cortex_m7/gnu/module_manager/src/tx_thread_system_return.S @@ -27,8 +27,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_system_return Cortex-Mx/GNU */ -/* 6.1.8 */ +/* _tx_thread_system_return Cortex-M7/GNU */ +/* 6.1.7 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -60,7 +60,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ +/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ /* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) diff --git a/ports_module/cortex_m7/gnu/module_manager/src/tx_timer_interrupt.S b/ports_module/cortex_m7/gnu/module_manager/src/tx_timer_interrupt.S index 9551a2b2..7cf4d4f3 100644 --- a/ports_module/cortex_m7/gnu/module_manager/src/tx_timer_interrupt.S +++ b/ports_module/cortex_m7/gnu/module_manager/src/tx_timer_interrupt.S @@ -37,8 +37,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_timer_interrupt Cortex-Mx/GNU */ -/* 6.1.8 */ +/* _tx_timer_interrupt Cortex-M7/GNU */ +/* 6.1.7 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -71,7 +71,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ +/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ /* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) diff --git a/ports_module/cortex_m7/gnu/module_manager/src/txm_module_manager_alignment_adjust.c b/ports_module/cortex_m7/gnu/module_manager/src/txm_module_manager_alignment_adjust.c index e5180b13..cbed8f20 100644 --- a/ports_module/cortex_m7/gnu/module_manager/src/txm_module_manager_alignment_adjust.c +++ b/ports_module/cortex_m7/gnu/module_manager/src/txm_module_manager_alignment_adjust.c @@ -30,8 +30,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _txm_power_of_two_block_size Cortex-M7/MPU/GNU */ -/* 6.1 */ +/* _txm_power_of_two_block_size Cortex-M7 */ +/* 6.1.9 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -61,7 +61,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ /* */ /**************************************************************************/ ULONG _txm_power_of_two_block_size(ULONG size) @@ -93,8 +93,8 @@ ULONG _txm_power_of_two_block_size(ULONG size) /* */ /* FUNCTION RELEASE */ /* */ -/* _txm_module_manager_alignment_adjust Cortex-M7/MPU/GNU */ -/* 6.1.7 */ +/* _txm_module_manager_alignment_adjust Cortex-M7 */ +/* 6.1.9 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -128,9 +128,7 @@ ULONG _txm_power_of_two_block_size(ULONG size) /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 06-02-2021 Scott Larson Added support for 8 MPU, */ -/* resulting in version 6.1.7 */ +/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ /* */ /**************************************************************************/ VOID _txm_module_manager_alignment_adjust(TXM_MODULE_PREAMBLE *module_preamble, @@ -139,7 +137,7 @@ VOID _txm_module_manager_alignment_adjust(TXM_MODULE_PREAMBLE *module_preamble, ULONG *data_size, ULONG *data_alignment) { -#ifndef TXM_MODULE_MANAGER_8_MPU +#ifdef TXM_MODULE_MANAGER_16_MPU ULONG local_code_size; ULONG local_code_alignment; ULONG local_data_size; diff --git a/ports_module/cortex_m7/gnu/module_manager/src/txm_module_manager_external_memory_enable.c b/ports_module/cortex_m7/gnu/module_manager/src/txm_module_manager_external_memory_enable.c index 24b0fa4b..138a4463 100644 --- a/ports_module/cortex_m7/gnu/module_manager/src/txm_module_manager_external_memory_enable.c +++ b/ports_module/cortex_m7/gnu/module_manager/src/txm_module_manager_external_memory_enable.c @@ -33,8 +33,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _txm_module_manager_external_memory_enable Cortex-M7/MPU/GNU */ -/* 6.1.7 */ +/* _txm_module_manager_external_memory_enable Cortex-M7 */ +/* 6.1.9 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -60,6 +60,7 @@ /* _tx_mutex_get Get protection mutex */ /* _tx_mutex_put Release protection mutex */ /* _txm_power_of_two_block_size Round length to power of two */ +/* _txm_module_manager_mm_register_setup Reconfigure MPU registers */ /* */ /* CALLED BY */ /* */ @@ -69,9 +70,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 06-02-2021 Scott Larson Added support for 8 MPU, */ -/* resulting in verison 6.1.7 */ +/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ /* */ /**************************************************************************/ UINT _txm_module_manager_external_memory_enable(TXM_MODULE_INSTANCE *module_instance, @@ -79,7 +78,7 @@ UINT _txm_module_manager_external_memory_enable(TXM_MODULE_INSTANCE *module_ins ULONG length, UINT attributes) { -#ifndef TXM_MODULE_MANAGER_8_MPU +#ifdef TXM_MODULE_MANAGER_16_MPU ULONG block_size; ULONG region_size; ULONG srd_bits; diff --git a/ports_module/cortex_m7/gnu/module_manager/src/txm_module_manager_memory_fault_handler.c b/ports_module/cortex_m7/gnu/module_manager/src/txm_module_manager_memory_fault_handler.c index bdeb0af5..4f58261b 100644 --- a/ports_module/cortex_m7/gnu/module_manager/src/txm_module_manager_memory_fault_handler.c +++ b/ports_module/cortex_m7/gnu/module_manager/src/txm_module_manager_memory_fault_handler.c @@ -45,8 +45,8 @@ TXM_MODULE_MANAGER_FAULT_INFO /* */ /* FUNCTION RELEASE */ /* */ -/* _txm_module_manager_memory_fault_handler Cortex-M7/MPU/GNU */ -/* 6.1 */ +/* _txm_module_manager_memory_fault_handler Cortex-M7 */ +/* 6.1.9 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -76,7 +76,7 @@ TXM_MODULE_MANAGER_FAULT_INFO /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ /* */ /**************************************************************************/ VOID _txm_module_manager_memory_fault_handler(VOID) diff --git a/ports_module/cortex_m7/gnu/module_manager/src/txm_module_manager_memory_fault_notify.c b/ports_module/cortex_m7/gnu/module_manager/src/txm_module_manager_memory_fault_notify.c index 6aa8f56f..8391c1c2 100644 --- a/ports_module/cortex_m7/gnu/module_manager/src/txm_module_manager_memory_fault_notify.c +++ b/ports_module/cortex_m7/gnu/module_manager/src/txm_module_manager_memory_fault_notify.c @@ -38,8 +38,8 @@ extern VOID (*_txm_module_manager_fault_notify)(TX_THREAD *, TXM_MODULE_INSTA /* */ /* FUNCTION RELEASE */ /* */ -/* _txm_module_manager_memory_fault_notify Cortex-M7/MPU/GNU */ -/* 6.1 */ +/* _txm_module_manager_memory_fault_notify Cortex-M7 */ +/* 6.1.9 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -71,7 +71,7 @@ extern VOID (*_txm_module_manager_fault_notify)(TX_THREAD *, TXM_MODULE_INSTA /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ /* */ /**************************************************************************/ UINT _txm_module_manager_memory_fault_notify(VOID (*notify_function)(TX_THREAD *, TXM_MODULE_INSTANCE *)) diff --git a/ports_module/cortex_m7/gnu/module_manager/src/txm_module_manager_mm_register_setup.c b/ports_module/cortex_m7/gnu/module_manager/src/txm_module_manager_mm_register_setup.c index c1ff8825..bfffa5bc 100644 --- a/ports_module/cortex_m7/gnu/module_manager/src/txm_module_manager_mm_register_setup.c +++ b/ports_module/cortex_m7/gnu/module_manager/src/txm_module_manager_mm_register_setup.c @@ -30,8 +30,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _txm_module_manager_region_size_get Cortex-M7/MPU/GNU */ -/* 6.1 */ +/* _txm_module_manager_region_size_get Cortex-M7 */ +/* 6.1.9 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -61,7 +61,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ /* */ /**************************************************************************/ ULONG _txm_module_manager_region_size_get(ULONG block_size) @@ -152,8 +152,8 @@ ULONG return_value; /* */ /* FUNCTION RELEASE */ /* */ -/* _txm_module_manager_calculate_srd_bits Cortex-M7/MPU/GNU */ -/* 6.1 */ +/* _txm_module_manager_calculate_srd_bits Cortex-M7 */ +/* 6.1.9 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -184,7 +184,7 @@ ULONG return_value; /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ /* */ /**************************************************************************/ ULONG _txm_module_manager_calculate_srd_bits(ULONG block_size, ULONG length) @@ -230,8 +230,8 @@ UINT srd_bit_index; /* */ /* FUNCTION RELEASE */ /* */ -/* _txm_module_manager_mm_register_setup Cortex-M7/MPU/GNU */ -/* 6.1.7 */ +/* _txm_module_manager_mm_register_setup Cortex-M7 */ +/* 6.1.9 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -240,6 +240,19 @@ UINT srd_bit_index; /* */ /* This function sets up the MPU register definitions based on the */ /* module's memory characteristics. */ +/* */ +/* Default MPU layout: */ +/* Entry Description */ +/* 0 Kernel mode entry */ +/* 1 Module code region */ +/* 2 Module code region */ +/* 3 Module code region */ +/* 4 Module code region */ +/* 5 Module data region */ +/* 6 Module data region */ +/* 7 Module data region */ +/* */ +/* If TXM_MODULE_MANAGER_16_MPU is defined, there are 16 MPU slots. */ /* MPU layout for the Cortex-M7: */ /* Entry Description */ /* 0 Kernel mode entry */ @@ -259,7 +272,6 @@ UINT srd_bit_index; /* 14 Unused region */ /* 15 Unused region */ /* */ -/* If TXM_MODULE_MANAGER_8_MPU is defined, there are only 8 MPU slots. */ /* */ /* INPUT */ /* */ @@ -281,14 +293,12 @@ UINT srd_bit_index; /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 06-02-2021 Scott Larson Added support for 8 MPU, */ -/* resulting in version 6.1.7 */ +/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ /* */ /**************************************************************************/ VOID _txm_module_manager_mm_register_setup(TXM_MODULE_INSTANCE *module_instance) { -#ifndef TXM_MODULE_MANAGER_8_MPU +#ifdef TXM_MODULE_MANAGER_16_MPU ULONG code_address; ULONG code_size; @@ -574,7 +584,7 @@ UINT i; for (i = 0; i < TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1; i++) { /* Build the base address register. */ - base_address_register = code_address & ~(block_size - 1) | mpu_register | 0x10; + base_address_register = (code_address & ~(block_size - 1)) | mpu_register | 0x10; /* Check if SRD bits need to be set. */ if (code_size < block_size) @@ -705,13 +715,13 @@ UINT i; #endif } -#ifndef TXM_MODULE_MANAGER_8_MPU +#ifdef TXM_MODULE_MANAGER_16_MPU /**************************************************************************/ /* */ /* FUNCTION RELEASE */ /* */ -/* _txm_module_manager_inside_data_check Cortex-M7/MPU/GNU */ -/* 6.1.6 */ +/* _txm_module_manager_inside_data_check Cortex-M7 */ +/* 6.1.9 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -743,10 +753,7 @@ UINT i; /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 04-02-2021 Scott Larson Modified comments, added */ -/* check for overflow, */ -/* resulting in version 6.1.6 */ +/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ /* */ /**************************************************************************/ UINT _txm_module_manager_inside_data_check(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE obj_ptr, UINT obj_size) diff --git a/ports_module/cortex_m7/gnu/module_manager/src/txm_module_manager_thread_stack_build.s b/ports_module/cortex_m7/gnu/module_manager/src/txm_module_manager_thread_stack_build.s index 2cb58046..b8c09021 100644 --- a/ports_module/cortex_m7/gnu/module_manager/src/txm_module_manager_thread_stack_build.s +++ b/ports_module/cortex_m7/gnu/module_manager/src/txm_module_manager_thread_stack_build.s @@ -27,8 +27,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _txm_module_manager_thread_stack_build Cortex-M7/MPU/GNU */ -/* 6.1.2 */ +/* _txm_module_manager_thread_stack_build Cortex-M7/GNU */ +/* 6.1.9 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -60,9 +60,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 11-09-2020 Scott Larson Modified comment(s), */ -/* resulting in version 6.1.2 */ +/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ /* */ /**************************************************************************/ // VOID _txm_module_manager_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(TX_THREAD *, TXM_MODULE_INSTANCE *)) diff --git a/ports_module/cortex_m7/iar/inc/tx_port.h b/ports_module/cortex_m7/iar/inc/tx_port.h index c0f84f96..7e935920 100644 --- a/ports_module/cortex_m7/iar/inc/tx_port.h +++ b/ports_module/cortex_m7/iar/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h Cortex-M7/IAR */ -/* 6.1 */ +/* 6.1.9 */ /* */ /* AUTHOR */ /* */ @@ -47,7 +47,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ /* */ /**************************************************************************/ @@ -71,7 +71,7 @@ #include <stdlib.h> #include <string.h> #include <intrinsics.h> -#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT #include <yvals.h> #endif @@ -117,7 +117,7 @@ typedef unsigned short USHORT; #endif -/* Define various constants for the ThreadX Cortex-M3 port. */ +/* Define various constants for the ThreadX Cortex-M7 port. */ #define TX_INT_DISABLE 1 /* Disable interrupts */ #define TX_INT_ENABLE 0 /* Enable interrupts */ @@ -180,8 +180,8 @@ ULONG _tx_misra_time_stamp_get(VOID); for the multiple macros is so that backward compatibility can be maintained with existing ThreadX kernel awareness modules. */ -#define TX_THREAD_EXTENSION_0 -#define TX_THREAD_EXTENSION_1 +#define TX_THREAD_EXTENSION_0 +#define TX_THREAD_EXTENSION_1 #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT #define TX_THREAD_EXTENSION_2 VOID *tx_thread_module_instance_ptr; \ VOID *tx_thread_module_entry_info_ptr; \ @@ -224,13 +224,16 @@ ULONG _tx_misra_time_stamp_get(VOID); #define TX_BLOCK_POOL_EXTENSION #define TX_BYTE_POOL_EXTENSION +#define TX_MUTEX_EXTENSION #define TX_EVENT_FLAGS_GROUP_EXTENSION VOID *tx_event_flags_group_module_instance; \ VOID (*tx_event_flags_group_set_module_notify)(struct TX_EVENT_FLAGS_GROUP_STRUCT *group_ptr); -#define TX_MUTEX_EXTENSION + #define TX_QUEUE_EXTENSION VOID *tx_queue_module_instance; \ VOID (*tx_queue_send_module_notify)(struct TX_QUEUE_STRUCT *queue_ptr); + #define TX_SEMAPHORE_EXTENSION VOID *tx_semaphore_module_instance; \ VOID (*tx_semaphore_put_module_notify)(struct TX_SEMAPHORE_STRUCT *semaphore_ptr); + #define TX_TIMER_EXTENSION VOID *tx_timer_module_instance; \ VOID (*tx_timer_module_expiration_function)(ULONG id); @@ -449,12 +452,6 @@ ULONG _tx_misra_ipsr_get(VOID); is used to define a local function save area for the disable and restore macros. */ -/* The embedded assembler blocks are design so as to be inlinable by the - armlink linker inlining. This requires them to consist of either a - single 32-bit instruction, or either one or two 16-bit instructions - followed by a "BX lr". Note that to reduce the critical region size, the - 16-bit "CPSID i" instruction is preceeded by a 16-bit NOP */ - #ifdef TX_DISABLE_INLINE UINT _tx_thread_interrupt_disable(VOID); @@ -512,7 +509,7 @@ void tx_thread_fpu_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M7/IAR Version 6.1 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M7/IAR Version 6.x *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; @@ -523,6 +520,3 @@ extern CHAR _tx_version_id[]; #endif - - - diff --git a/ports_module/cortex_m7/iar/inc/txm_module_port.h b/ports_module/cortex_m7/iar/inc/txm_module_port.h index 309e29a7..458a610a 100644 --- a/ports_module/cortex_m7/iar/inc/txm_module_port.h +++ b/ports_module/cortex_m7/iar/inc/txm_module_port.h @@ -25,8 +25,8 @@ /* */ /* APPLICATION INTERFACE DEFINITION RELEASE */ /* */ -/* txm_module_port.h Cortex-M7/MPU/IAR */ -/* 6.1.7 */ +/* txm_module_port.h Cortex-M7/IAR */ +/* 6.1.9 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -40,12 +40,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 11-09-2020 Scott Larson Modified comment(s), */ -/* increase kernel stack size, */ -/* resulting in version 6.1.2 */ -/* 06-02-2021 Scott Larson Added support for 8 MPU, */ -/* resulting in version 6.1.7 */ +/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ /* */ /**************************************************************************/ @@ -171,10 +166,10 @@ The following extensions must also be defined in tx_port.h: #define INLINE_DECLARE inline -#ifndef TXM_MODULE_MANAGER_8_MPU +#ifdef TXM_MODULE_MANAGER_16_MPU /* Define the number of MPU entries assigned to the code and data sections. - On Cortex-M7 parts, there are 16 total entries. ThreadX uses one for access + On some Cortex-M7 parts, there are 16 total entries. ThreadX uses one for access to the kernel entry function, thus 15 remain for code and data protection. */ #define TXM_MODULE_MPU_TOTAL_ENTRIES 16 #define TXM_MODULE_MPU_CODE_ENTRIES 4 @@ -204,10 +199,10 @@ typedef struct TXM_MODULE_MPU_INFO_STRUCT ULONG txm_module_instance_shared_memory_address[TXM_MODULE_MPU_SHARED_ENTRIES]; \ ULONG txm_module_instance_shared_memory_length[TXM_MODULE_MPU_SHARED_ENTRIES]; -#else /* TXM_MODULE_MANAGER_8_MPU is defined */ +#else /* TXM_MODULE_MANAGER_16_MPU is not defined */ /* Define the number of MPU entries assigned to the code and data sections. - On some Cortex-M7 parts, there are 8 total entries. ThreadX uses one for access + On Cortex-M3, M4, and some M7 parts, there are 8 total entries. ThreadX uses one for access to the kernel entry function, thus 7 remain for code and data protection. */ #define TXM_MODULE_MANAGER_CODE_MPU_ENTRIES 4 #define TXM_MODULE_MANAGER_DATA_MPU_ENTRIES 3 @@ -225,7 +220,7 @@ typedef struct TXM_MODULE_MPU_INFO_STRUCT ULONG txm_module_instance_shared_memory_address; \ ULONG txm_module_instance_shared_memory_length; -#endif /* TXM_MODULE_MANAGER_8_MPU */ +#endif /* TXM_MODULE_MANAGER_16_MPU */ /* Define the memory fault information structure that is populated when a memory fault occurs. */ @@ -348,7 +343,7 @@ typedef struct TXM_MODULE_MANAGER_MEMORY_FAULT_INFO_STRUCT /* Define the macros to perform port-specific checks when passing pointers to the kernel. */ /* Define macro to make sure object is inside the module's data. */ -#ifndef TXM_MODULE_MANAGER_8_MPU +#ifdef TXM_MODULE_MANAGER_16_MPU #define TXM_MODULE_MANAGER_CHECK_INSIDE_DATA(module_instance, obj_ptr, obj_size) \ _txm_module_manager_inside_data_check(module_instance, obj_ptr, obj_size) #else @@ -382,6 +377,6 @@ UINT _txm_module_manager_inside_data_check(TXM_MODULE_INSTANCE *module_instance #define TXM_MODULE_MANAGER_VERSION_ID \ CHAR _txm_module_manager_version_id[] = \ - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-M7/MPU/IAR Version 6.1.7 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-M7/IAR Version 6.x *"; #endif diff --git a/ports_module/cortex_m7/iar/module_lib/src/txm_module_thread_shell_entry.c b/ports_module/cortex_m7/iar/module_lib/src/txm_module_thread_shell_entry.c index d0ca97e1..5295230f 100644 --- a/ports_module/cortex_m7/iar/module_lib/src/txm_module_thread_shell_entry.c +++ b/ports_module/cortex_m7/iar/module_lib/src/txm_module_thread_shell_entry.c @@ -44,7 +44,7 @@ TXM_MODULE_THREAD_ENTRY_INFO *_txm_module_entry_info; ULONG (*_txm_module_kernel_call_dispatcher)(ULONG kernel_request, ULONG param_1, ULONG param_2, ULONG param3); -/* Define the IAR startup code that clears the uninitialized global data and sets up the +/* Define the startup code that clears the uninitialized global data and sets up the preset global variables. */ extern VOID __iar_data_init3(VOID); @@ -54,15 +54,15 @@ extern VOID __iar_data_init3(VOID); /* */ /* FUNCTION RELEASE */ /* */ -/* _txm_module_thread_shell_entry Cortex-M7/MPU/IAR */ -/* 6.1 */ +/* _txm_module_thread_shell_entry Cortex-M7/IAR */ +/* 6.1.9 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ /* */ /* DESCRIPTION */ /* */ -/* This function calls the specified entry function of the thread. It */ +/* This function calls the specified entry function of the thread. It */ /* also provides a place for the thread's entry function to return. */ /* If the thread returns, this function places the thread in a */ /* "COMPLETED" state. */ @@ -78,7 +78,7 @@ extern VOID __iar_data_init3(VOID); /* */ /* CALLS */ /* */ -/* __iar_data_init3 IAR global initialization function*/ +/* __iar_data_init3 cstartup initialization */ /* thread_entry Thread's entry function */ /* tx_thread_resume Resume the module callback thread */ /* _txm_module_thread_system_suspend Module thread suspension routine */ @@ -91,7 +91,7 @@ extern VOID __iar_data_init3(VOID); /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ /* */ /**************************************************************************/ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_ENTRY_INFO *thread_info) @@ -106,7 +106,7 @@ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_EN execution. If not, simply skip the C startup code. */ if (thread_info -> txm_module_thread_entry_info_start_thread) { - /* Initialize the IAR C environment. */ + /* Initialize the C environment. */ __iar_data_init3(); /* Save the entry info pointer, for later use. */ @@ -171,4 +171,3 @@ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_EN TX_SAFETY_CRITICAL_EXCEPTION(__FILE__, __LINE__, 0); #endif } - diff --git a/ports_module/cortex_m7/iar/module_manager/src/tx_thread_context_restore.s b/ports_module/cortex_m7/iar/module_manager/src/tx_thread_context_restore.s index 0a188df9..2ebc5f54 100644 --- a/ports_module/cortex_m7/iar/module_manager/src/tx_thread_context_restore.s +++ b/ports_module/cortex_m7/iar/module_manager/src/tx_thread_context_restore.s @@ -27,8 +27,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_context_restore Cortex-Mx/IAR */ -/* 6.1.8 */ +/* _tx_thread_context_restore Cortex-M7/IAR */ +/* 6.1.7 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -58,7 +58,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ +/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ /* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) diff --git a/ports_module/cortex_m7/iar/module_manager/src/tx_thread_context_save.s b/ports_module/cortex_m7/iar/module_manager/src/tx_thread_context_save.s index e71ae496..b98aaa74 100644 --- a/ports_module/cortex_m7/iar/module_manager/src/tx_thread_context_save.s +++ b/ports_module/cortex_m7/iar/module_manager/src/tx_thread_context_save.s @@ -27,8 +27,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_context_save Cortex-Mx/IAR */ -/* 6.1.8 */ +/* _tx_thread_context_save Cortex-M7/IAR */ +/* 6.1.7 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -58,7 +58,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ +/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ /* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) diff --git a/ports_module/cortex_m7/iar/module_manager/src/tx_thread_interrupt_control.s b/ports_module/cortex_m7/iar/module_manager/src/tx_thread_interrupt_control.s index c0d9d095..506ef09a 100644 --- a/ports_module/cortex_m7/iar/module_manager/src/tx_thread_interrupt_control.s +++ b/ports_module/cortex_m7/iar/module_manager/src/tx_thread_interrupt_control.s @@ -26,8 +26,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_interrupt_control Cortex-Mx/IAR */ -/* 6.1.8 */ +/* _tx_thread_interrupt_control Cortex-M7/IAR */ +/* 6.1.7 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -57,7 +57,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ +/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ /* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) diff --git a/ports_module/cortex_m7/iar/module_manager/src/tx_thread_interrupt_disable.s b/ports_module/cortex_m7/iar/module_manager/src/tx_thread_interrupt_disable.s index 86fcf188..4cf0a2dd 100644 --- a/ports_module/cortex_m7/iar/module_manager/src/tx_thread_interrupt_disable.s +++ b/ports_module/cortex_m7/iar/module_manager/src/tx_thread_interrupt_disable.s @@ -26,8 +26,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_interrupt_disable Cortex-Mx/IAR */ -/* 6.1.8 */ +/* _tx_thread_interrupt_disable Cortex-M7/IAR */ +/* 6.1.7 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -57,7 +57,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ +/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ /* */ /**************************************************************************/ // UINT _tx_thread_interrupt_disable(VOID) diff --git a/ports_module/cortex_m7/iar/module_manager/src/tx_thread_interrupt_restore.s b/ports_module/cortex_m7/iar/module_manager/src/tx_thread_interrupt_restore.s index f9603de1..27037596 100644 --- a/ports_module/cortex_m7/iar/module_manager/src/tx_thread_interrupt_restore.s +++ b/ports_module/cortex_m7/iar/module_manager/src/tx_thread_interrupt_restore.s @@ -26,8 +26,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_interrupt_restore Cortex-Mx/IAR */ -/* 6.1.8 */ +/* _tx_thread_interrupt_restore Cortex-M7/IAR */ +/* 6.1.7 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -57,7 +57,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ +/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ /* */ /**************************************************************************/ // VOID _tx_thread_interrupt_restore(UINT previous_posture) diff --git a/ports_module/cortex_m7/iar/module_manager/src/tx_thread_schedule.s b/ports_module/cortex_m7/iar/module_manager/src/tx_thread_schedule.s index 5623c560..9162c7ab 100644 --- a/ports_module/cortex_m7/iar/module_manager/src/tx_thread_schedule.s +++ b/ports_module/cortex_m7/iar/module_manager/src/tx_thread_schedule.s @@ -35,8 +35,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_schedule Cortex-M7/MPU/IAR */ -/* 6.1.7 */ +/* _tx_thread_schedule Cortex-M7/IAR */ +/* 6.1.9 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -69,15 +69,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 11-09-2020 Scott Larson Modified comment(s), arrange */ -/* code to fix link error when */ -/* VFP is enabled, resulting */ -/* in version 6.1.2 */ -/* 06-02-2021 Scott Larson Fixed extended stack handling */ -/* when calling kernel APIs, */ -/* added support for 8 MPU, */ -/* resulting in version 6.1.7 */ +/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ /* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) @@ -103,7 +95,6 @@ _tx_thread_schedule: #endif /* Enable memory fault registers. */ - LDR r0, =0xE000ED24 // Build SHCSR address LDR r1, =0x70000 // Enable Usage, Bus, and MemManage faults STR r1, [r0] // @@ -362,7 +353,7 @@ __tx_ts_restore: // Use alias registers to quickly load MPU ADD r0, r0, #100 // Build address of MPU register start in thread control block -#ifndef TXM_MODULE_MANAGER_8_MPU +#ifdef TXM_MODULE_MANAGER_16_MPU LDM r0!,{r2-r9} // Load MPU regions 0-3 STM r1,{r2-r9} // Store MPU regions 0-3 LDM r0!,{r2-r9} // Load MPU regions 4-7 @@ -445,13 +436,17 @@ __tx_SVCallHandler: #endif MRS r3, PSP // Pickup thread stack pointer +#ifdef __ARMVFP__ TST lr, #0x10 // Test for extended module stack ITT EQ ORREQ r3, r3, #1 // If so, set LSB in thread stack pointer to indicate extended frame ORREQ lr, lr, #0x10 // Set bit, return with standard frame +#endif STR r3, [r2, #0xB0] // Save thread stack pointer +#ifdef __ARMVFP__ BIC r3, #1 // Clear possibly OR'd bit - +#endif + /* Build kernel stack by copying thread stack two registers at a time */ ADD r3, r3, #32 // Start at bottom of hardware stack LDMDB r3!, {r1-r2} @@ -498,6 +493,7 @@ _tx_thread_user_return: STR r3, [r2, #20] // Set stack size #endif +#ifdef __ARMVFP__ /* If lazy stacking is pending, check if it can be cleared. if(LSPACT && tx_thread_module_stack_start < FPCAR && FPCAR < tx_thread_module_stack_end) then clear LSPACT. */ @@ -517,14 +513,17 @@ _tx_thread_user_return: LDR r1, =0xE000EF34 // Address of FPCCR STR r3, [r1] // Save updated FPCCR _tx_no_lazy_clear: +#endif LDR r0, [r2, #0xB0] // Load the module thread stack pointer MRS r3, PSP // Pickup kernel stack pointer +#ifdef __ARMVFP__ TST r0, #1 // Is module stack extended? ITTE NE // If so... BICNE lr, #0x10 // Clear bit, return with extended frame BICNE r0, #1 // Clear bit that indicates extended module frame ORREQ lr, lr, #0x10 // Else set bit, return with standard frame +#endif /* Copy kernel hardware stack to module thread stack. */ LDM r3!, {r1-r2} diff --git a/ports_module/cortex_m7/iar/module_manager/src/tx_thread_stack_build.s b/ports_module/cortex_m7/iar/module_manager/src/tx_thread_stack_build.s index dcc82bf6..ee9e07e3 100644 --- a/ports_module/cortex_m7/iar/module_manager/src/tx_thread_stack_build.s +++ b/ports_module/cortex_m7/iar/module_manager/src/tx_thread_stack_build.s @@ -26,8 +26,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_stack_build Cortex-Mx/IAR */ -/* 6.1.8 */ +/* _tx_thread_stack_build Cortex-M7/IAR */ +/* 6.1.7 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -59,7 +59,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ +/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ /* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) diff --git a/ports_module/cortex_m7/iar/module_manager/src/tx_thread_system_return.s b/ports_module/cortex_m7/iar/module_manager/src/tx_thread_system_return.s index 4c5cb6fb..571f9b21 100644 --- a/ports_module/cortex_m7/iar/module_manager/src/tx_thread_system_return.s +++ b/ports_module/cortex_m7/iar/module_manager/src/tx_thread_system_return.s @@ -26,8 +26,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_system_return Cortex-Mx/IAR */ -/* 6.1.8 */ +/* _tx_thread_system_return Cortex-M7/IAR */ +/* 6.1.7 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -59,7 +59,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ +/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ /* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) diff --git a/ports_module/cortex_m7/iar/module_manager/src/tx_timer_interrupt.s b/ports_module/cortex_m7/iar/module_manager/src/tx_timer_interrupt.s index aa209956..7c899085 100644 --- a/ports_module/cortex_m7/iar/module_manager/src/tx_timer_interrupt.s +++ b/ports_module/cortex_m7/iar/module_manager/src/tx_timer_interrupt.s @@ -39,8 +39,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_timer_interrupt Cortex-Mx/IAR */ -/* 6.1.8 */ +/* _tx_timer_interrupt Cortex-M7/IAR */ +/* 6.1.7 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -73,7 +73,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ +/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ /* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) diff --git a/ports_module/cortex_m7/iar/module_manager/src/txm_module_manager_alignment_adjust.c b/ports_module/cortex_m7/iar/module_manager/src/txm_module_manager_alignment_adjust.c index ed5e20e2..cbed8f20 100644 --- a/ports_module/cortex_m7/iar/module_manager/src/txm_module_manager_alignment_adjust.c +++ b/ports_module/cortex_m7/iar/module_manager/src/txm_module_manager_alignment_adjust.c @@ -30,8 +30,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _txm_power_of_two_block_size Cortex-M7/MPU/IAR */ -/* 6.1 */ +/* _txm_power_of_two_block_size Cortex-M7 */ +/* 6.1.9 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -61,7 +61,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ /* */ /**************************************************************************/ ULONG _txm_power_of_two_block_size(ULONG size) @@ -93,8 +93,8 @@ ULONG _txm_power_of_two_block_size(ULONG size) /* */ /* FUNCTION RELEASE */ /* */ -/* _txm_module_manager_alignment_adjust Cortex-M7/MPU/IAR */ -/* 6.1.7 */ +/* _txm_module_manager_alignment_adjust Cortex-M7 */ +/* 6.1.9 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -128,9 +128,7 @@ ULONG _txm_power_of_two_block_size(ULONG size) /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 06-02-2021 Scott Larson Added support for 8 MPU, */ -/* resulting in version 6.1.7 */ +/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ /* */ /**************************************************************************/ VOID _txm_module_manager_alignment_adjust(TXM_MODULE_PREAMBLE *module_preamble, @@ -139,7 +137,7 @@ VOID _txm_module_manager_alignment_adjust(TXM_MODULE_PREAMBLE *module_preamble, ULONG *data_size, ULONG *data_alignment) { -#ifndef TXM_MODULE_MANAGER_8_MPU +#ifdef TXM_MODULE_MANAGER_16_MPU ULONG local_code_size; ULONG local_code_alignment; ULONG local_data_size; diff --git a/ports_module/cortex_m7/iar/module_manager/src/txm_module_manager_external_memory_enable.c b/ports_module/cortex_m7/iar/module_manager/src/txm_module_manager_external_memory_enable.c index 01c7a62c..138a4463 100644 --- a/ports_module/cortex_m7/iar/module_manager/src/txm_module_manager_external_memory_enable.c +++ b/ports_module/cortex_m7/iar/module_manager/src/txm_module_manager_external_memory_enable.c @@ -33,8 +33,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _txm_module_manager_external_memory_enable Cortex-M7/MPU/IAR */ -/* 6.1.7 */ +/* _txm_module_manager_external_memory_enable Cortex-M7 */ +/* 6.1.9 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -60,6 +60,7 @@ /* _tx_mutex_get Get protection mutex */ /* _tx_mutex_put Release protection mutex */ /* _txm_power_of_two_block_size Round length to power of two */ +/* _txm_module_manager_mm_register_setup Reconfigure MPU registers */ /* */ /* CALLED BY */ /* */ @@ -69,9 +70,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 06-02-2021 Scott Larson Added support for 8 MPU, */ -/* resulting in verison 6.1.7 */ +/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ /* */ /**************************************************************************/ UINT _txm_module_manager_external_memory_enable(TXM_MODULE_INSTANCE *module_instance, @@ -79,7 +78,7 @@ UINT _txm_module_manager_external_memory_enable(TXM_MODULE_INSTANCE *module_ins ULONG length, UINT attributes) { -#ifndef TXM_MODULE_MANAGER_8_MPU +#ifdef TXM_MODULE_MANAGER_16_MPU ULONG block_size; ULONG region_size; ULONG srd_bits; diff --git a/ports_module/cortex_m7/iar/module_manager/src/txm_module_manager_memory_fault_handler.c b/ports_module/cortex_m7/iar/module_manager/src/txm_module_manager_memory_fault_handler.c index bfd781f4..4f58261b 100644 --- a/ports_module/cortex_m7/iar/module_manager/src/txm_module_manager_memory_fault_handler.c +++ b/ports_module/cortex_m7/iar/module_manager/src/txm_module_manager_memory_fault_handler.c @@ -45,8 +45,8 @@ TXM_MODULE_MANAGER_FAULT_INFO /* */ /* FUNCTION RELEASE */ /* */ -/* _txm_module_manager_memory_fault_handler Cortex-M7/MPU/IAR */ -/* 6.1 */ +/* _txm_module_manager_memory_fault_handler Cortex-M7 */ +/* 6.1.9 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -76,7 +76,7 @@ TXM_MODULE_MANAGER_FAULT_INFO /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ /* */ /**************************************************************************/ VOID _txm_module_manager_memory_fault_handler(VOID) diff --git a/ports_module/cortex_m7/iar/module_manager/src/txm_module_manager_memory_fault_notify.c b/ports_module/cortex_m7/iar/module_manager/src/txm_module_manager_memory_fault_notify.c index db902739..8391c1c2 100644 --- a/ports_module/cortex_m7/iar/module_manager/src/txm_module_manager_memory_fault_notify.c +++ b/ports_module/cortex_m7/iar/module_manager/src/txm_module_manager_memory_fault_notify.c @@ -38,8 +38,8 @@ extern VOID (*_txm_module_manager_fault_notify)(TX_THREAD *, TXM_MODULE_INSTA /* */ /* FUNCTION RELEASE */ /* */ -/* _txm_module_manager_memory_fault_notify Cortex-M7/MPU/IAR */ -/* 6.1 */ +/* _txm_module_manager_memory_fault_notify Cortex-M7 */ +/* 6.1.9 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -71,7 +71,7 @@ extern VOID (*_txm_module_manager_fault_notify)(TX_THREAD *, TXM_MODULE_INSTA /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ /* */ /**************************************************************************/ UINT _txm_module_manager_memory_fault_notify(VOID (*notify_function)(TX_THREAD *, TXM_MODULE_INSTANCE *)) diff --git a/ports_module/cortex_m7/iar/module_manager/src/txm_module_manager_mm_register_setup.c b/ports_module/cortex_m7/iar/module_manager/src/txm_module_manager_mm_register_setup.c index 97fda4f9..bfffa5bc 100644 --- a/ports_module/cortex_m7/iar/module_manager/src/txm_module_manager_mm_register_setup.c +++ b/ports_module/cortex_m7/iar/module_manager/src/txm_module_manager_mm_register_setup.c @@ -30,8 +30,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _txm_module_manager_region_size_get Cortex-M7/MPU/IAR */ -/* 6.1 */ +/* _txm_module_manager_region_size_get Cortex-M7 */ +/* 6.1.9 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -61,7 +61,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ /* */ /**************************************************************************/ ULONG _txm_module_manager_region_size_get(ULONG block_size) @@ -152,8 +152,8 @@ ULONG return_value; /* */ /* FUNCTION RELEASE */ /* */ -/* _txm_module_manager_calculate_srd_bits Cortex-M7/MPU/IAR */ -/* 6.1 */ +/* _txm_module_manager_calculate_srd_bits Cortex-M7 */ +/* 6.1.9 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -184,7 +184,7 @@ ULONG return_value; /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ /* */ /**************************************************************************/ ULONG _txm_module_manager_calculate_srd_bits(ULONG block_size, ULONG length) @@ -230,16 +230,29 @@ UINT srd_bit_index; /* */ /* FUNCTION RELEASE */ /* */ -/* _txm_module_manager_mm_register_setup Cortex-M7/MPU/IAR */ -/* 6.1.7 */ +/* _txm_module_manager_mm_register_setup Cortex-M7 */ +/* 6.1.9 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ /* */ /* DESCRIPTION */ /* */ -/* This function sets up the Cortex-M7 MPU register definitions based */ -/* on the module's memory characteristics. */ +/* This function sets up the MPU register definitions based on the */ +/* module's memory characteristics. */ +/* */ +/* Default MPU layout: */ +/* Entry Description */ +/* 0 Kernel mode entry */ +/* 1 Module code region */ +/* 2 Module code region */ +/* 3 Module code region */ +/* 4 Module code region */ +/* 5 Module data region */ +/* 6 Module data region */ +/* 7 Module data region */ +/* */ +/* If TXM_MODULE_MANAGER_16_MPU is defined, there are 16 MPU slots. */ /* MPU layout for the Cortex-M7: */ /* Entry Description */ /* 0 Kernel mode entry */ @@ -259,7 +272,6 @@ UINT srd_bit_index; /* 14 Unused region */ /* 15 Unused region */ /* */ -/* If TXM_MODULE_MANAGER_8_MPU is defined, there are only 8 MPU slots. */ /* */ /* INPUT */ /* */ @@ -281,14 +293,12 @@ UINT srd_bit_index; /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 06-02-2021 Scott Larson Added support for 8 MPU, */ -/* resulting in version 6.1.7 */ +/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ /* */ /**************************************************************************/ VOID _txm_module_manager_mm_register_setup(TXM_MODULE_INSTANCE *module_instance) { -#ifndef TXM_MODULE_MANAGER_8_MPU +#ifdef TXM_MODULE_MANAGER_16_MPU ULONG code_address; ULONG code_size; @@ -574,7 +584,7 @@ UINT i; for (i = 0; i < TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1; i++) { /* Build the base address register. */ - base_address_register = code_address & ~(block_size - 1) | mpu_register | 0x10; + base_address_register = (code_address & ~(block_size - 1)) | mpu_register | 0x10; /* Check if SRD bits need to be set. */ if (code_size < block_size) @@ -705,13 +715,13 @@ UINT i; #endif } -#ifndef TXM_MODULE_MANAGER_8_MPU +#ifdef TXM_MODULE_MANAGER_16_MPU /**************************************************************************/ /* */ /* FUNCTION RELEASE */ /* */ -/* _txm_module_manager_inside_data_check Cortex-M7/MPU/IAR */ -/* 6.1.6 */ +/* _txm_module_manager_inside_data_check Cortex-M7 */ +/* 6.1.9 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -743,10 +753,7 @@ UINT i; /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 04-02-2021 Scott Larson Modified comments, added */ -/* check for overflow, */ -/* resulting in version 6.1.6 */ +/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ /* */ /**************************************************************************/ UINT _txm_module_manager_inside_data_check(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE obj_ptr, UINT obj_size) diff --git a/ports_module/cortex_m7/iar/module_manager/src/txm_module_manager_thread_stack_build.s b/ports_module/cortex_m7/iar/module_manager/src/txm_module_manager_thread_stack_build.s index 85fafbc3..70eb2e37 100644 --- a/ports_module/cortex_m7/iar/module_manager/src/txm_module_manager_thread_stack_build.s +++ b/ports_module/cortex_m7/iar/module_manager/src/txm_module_manager_thread_stack_build.s @@ -26,8 +26,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _txm_module_manager_thread_stack_build Cortex-M7/MPU/IAR */ -/* 6.1.2 */ +/* _txm_module_manager_thread_stack_build Cortex-M7/IAR */ +/* 6.1.9 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -59,9 +59,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 11-09-2020 Scott Larson Modified comment(s), */ -/* resulting in version 6.1.2 */ +/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ /* */ /**************************************************************************/ // VOID _txm_module_manager_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(TX_THREAD *, TXM_MODULE_INSTANCE *)) diff --git a/ports_module/cortex_r4/ac6/example_build/sample_threadx_module/.cproject b/ports_module/cortex_r4/ac6/example_build/sample_threadx_module/.cproject index 7f9fcfd7..ee2634f6 100644 --- a/ports_module/cortex_r4/ac6/example_build/sample_threadx_module/.cproject +++ b/ports_module/cortex_r4/ac6/example_build/sample_threadx_module/.cproject @@ -1,153 +1,184 @@ <?xml version="1.0" encoding="UTF-8" standalone="no"?> <?fileVersion 4.0.0?><cproject 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<project id="sample_threadx_module.com.arm.eclipse.build.project.v6.exe.1790254349" name="Executable"/> + + </storageModule> + + <storageModule moduleId="scannerConfiguration"> + + <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/> + + </storageModule> + + <storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/> + + <storageModule moduleId="refreshScope"/> + + <storageModule moduleId="com.arm.projectSettings" version="6.0.0"/> + + <storageModule moduleId="org.eclipse.cdt.make.core.buildtargets"/> + </cproject> diff --git a/ports_module/cortex_r4/ac6/example_build/sample_threadx_module/.project b/ports_module/cortex_r4/ac6/example_build/sample_threadx_module/.project index 1db05610..36efe951 100644 --- a/ports_module/cortex_r4/ac6/example_build/sample_threadx_module/.project +++ b/ports_module/cortex_r4/ac6/example_build/sample_threadx_module/.project @@ -3,8 +3,6 @@ <name>sample_threadx_module</name> <comment></comment> <projects> - <project>tx</project> - <project>txm</project> </projects> <buildSpec> <buildCommand> diff --git a/ports_module/cortex_r4/ac6/example_build/sample_threadx_module/.settings/language.settings.xml b/ports_module/cortex_r4/ac6/example_build/sample_threadx_module/.settings/language.settings.xml deleted file mode 100644 index be74d0a1..00000000 --- a/ports_module/cortex_r4/ac6/example_build/sample_threadx_module/.settings/language.settings.xml +++ /dev/null @@ -1,25 +0,0 @@ -<?xml version="1.0" encoding="UTF-8" standalone="no"?> -<project> - <configuration id="com.arm.eclipse.build.config.v6.exe.debug.1186660388" name="Debug"> - <extension point="org.eclipse.cdt.core.LanguageSettingsProvider"> - <provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/> - <provider-reference id="org.eclipse.cdt.core.ReferencedProjectsLanguageSettingsProvider" ref="shared-provider"/> - <provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/> - <provider class="com.arm.eclipse.builder.armcc.discovery.ArmCompiler6LanguageSettingsProvider" console="false" env-hash="1218969334819235502" id="com.arm.eclipse.builder.armcc.v6.langprovider" keep-relative-paths="false" name="Arm Compiler 6 Built-in Compiler Settings" parameter="${COMMAND} ${FLAGS} -E -P -v -dD "${INPUTS}"" prefer-non-shared="true"> - <language-scope id="org.eclipse.cdt.core.gcc"/> - <language-scope id="org.eclipse.cdt.core.g++"/> - </provider> - </extension> - </configuration> - <configuration id="com.arm.eclipse.build.config.v6.exe.release.1059742195" name="Release"> - <extension point="org.eclipse.cdt.core.LanguageSettingsProvider"> - <provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/> - <provider-reference id="org.eclipse.cdt.core.ReferencedProjectsLanguageSettingsProvider" ref="shared-provider"/> - <provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/> - <provider class="com.arm.eclipse.builder.armcc.discovery.ArmCompiler6LanguageSettingsProvider" console="false" env-hash="1208898303067000398" id="com.arm.eclipse.builder.armcc.v6.langprovider" keep-relative-paths="false" name="Arm Compiler 6 Built-in Compiler Settings" parameter="${COMMAND} ${FLAGS} -E -P -v -dD "${INPUTS}"" prefer-non-shared="true"> - <language-scope id="org.eclipse.cdt.core.gcc"/> - <language-scope id="org.eclipse.cdt.core.g++"/> - </provider> - </extension> - </configuration> -</project> diff --git a/ports_module/cortex_r4/ac6/example_build/sample_threadx_module_manager/.cproject b/ports_module/cortex_r4/ac6/example_build/sample_threadx_module_manager/.cproject index a8065ae9..71818fd9 100644 --- a/ports_module/cortex_r4/ac6/example_build/sample_threadx_module_manager/.cproject +++ b/ports_module/cortex_r4/ac6/example_build/sample_threadx_module_manager/.cproject @@ -1,136 +1,170 @@ <?xml version="1.0" encoding="UTF-8" standalone="no"?> <?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage"> - <storageModule moduleId="org.eclipse.cdt.core.settings"> - <cconfiguration id="com.arm.eclipse.build.config.v6.exe.debug.779721393"> - <storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.arm.eclipse.build.config.v6.exe.debug.779721393" moduleId="org.eclipse.cdt.core.settings" name="Debug"> - <externalSettings> - <externalSetting> - <entry flags="VALUE_WORKSPACE_PATH" kind="includePath" name="/sample_threadx"/> - <entry flags="VALUE_WORKSPACE_PATH" kind="libraryPath" name="/sample_threadx/Debug"/> - <entry flags="RESOLVED" kind="libraryFile" name="sample_threadx" srcPrefixMapping="" srcRootPath=""/> - </externalSetting> - </externalSettings> - <extensions> - <extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/> - <extension id="com.arm.eclipse.builder.armcc.error" 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id="com.arm.tool.c.linker.libs.2083701191" name="User library files" superClass="com.arm.tool.c.linker.libs" useByScannerDiscovery="false" valueType="libs"/> + + <option id="com.arm.tool.c.linker.option.imagemap.1405130028" name="Generate image map (--map)" superClass="com.arm.tool.c.linker.option.imagemap" useByScannerDiscovery="false" value="true" valueType="boolean"/> + + <option id="com.arm.tool.c.linker.option.sizes.1951623263" name="List code and data sizes of output image (--info=sizes)" superClass="com.arm.tool.c.linker.option.sizes" useByScannerDiscovery="false" value="false" valueType="boolean"/> + + <option id="com.arm.tool.c.linker.option.redirectoutput.1115886571" name="Redirect diagnostics output to file (--list)" superClass="com.arm.tool.c.linker.option.redirectoutput" useByScannerDiscovery="false" value="map.map" valueType="string"/> + + <option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.arm.tool.c.linker.implicit.libs.790772204" name="Implicit other library files" superClass="com.arm.tool.c.linker.implicit.libs" valueType="libs"> + + <listOptionValue builtIn="false" value=""${workspace_loc:/tx/Debug/tx.a}""/> + + </option> + + </tool> + + <tool id="com.arm.tool.librarian.v6.base.var.arm_compiler_6-6.552129599" name="Arm Librarian 6" superClass="com.arm.tool.librarian.v6.base.var.arm_compiler_6-6"/> + + </toolChain> + + </folderInfo> + + </configuration> + + </storageModule> + + <storageModule moduleId="org.eclipse.cdt.core.externalSettings"/> + + </cconfiguration> + + </storageModule> + + <storageModule moduleId="cdtBuildSystem" version="4.0.0"> + + <project id="sample_threadx.com.arm.eclipse.build.project.v6.exe.1139105725" name="Executable"/> + + </storageModule> + + <storageModule moduleId="scannerConfiguration"> + + <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/> + + </storageModule> + + <storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/> + + <storageModule moduleId="com.arm.projectSettings" version="6.0.0"/> + + <storageModule moduleId="refreshScope" versionNumber="2"> + + <configuration configurationName="Debug"> + + <resource resourceType="PROJECT" workspacePath="/sample_threadx"/> + + </configuration> + + <configuration configurationName="Release"> + + <resource resourceType="PROJECT" workspacePath="/sample_threadx"/> + + </configuration> + + </storageModule> + + <storageModule moduleId="org.eclipse.cdt.make.core.buildtargets"/> + </cproject> diff --git a/ports_module/cortex_r4/ac6/example_build/sample_threadx_module_manager/.settings/language.settings.xml b/ports_module/cortex_r4/ac6/example_build/sample_threadx_module_manager/.settings/language.settings.xml deleted file mode 100644 index d7138707..00000000 --- a/ports_module/cortex_r4/ac6/example_build/sample_threadx_module_manager/.settings/language.settings.xml +++ /dev/null @@ -1,25 +0,0 @@ -<?xml version="1.0" encoding="UTF-8" standalone="no"?> -<project> - <configuration id="com.arm.eclipse.build.config.v6.exe.debug.779721393" name="Debug"> - <extension point="org.eclipse.cdt.core.LanguageSettingsProvider"> - <provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/> - <provider-reference id="org.eclipse.cdt.core.ReferencedProjectsLanguageSettingsProvider" ref="shared-provider"/> - <provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/> - <provider class="com.arm.eclipse.builder.armcc.discovery.ArmCompiler6LanguageSettingsProvider" console="false" env-hash="1257603729813011790" id="com.arm.eclipse.builder.armcc.v6.langprovider" keep-relative-paths="false" name="Arm Compiler 6 Built-in Compiler Settings" parameter="${COMMAND} ${FLAGS} -E -P -v -dD "${INPUTS}"" prefer-non-shared="true"> - <language-scope id="org.eclipse.cdt.core.gcc"/> - <language-scope id="org.eclipse.cdt.core.g++"/> - </provider> - </extension> - </configuration> - <configuration id="com.arm.eclipse.build.config.v6.exe.release.713968185" name="Release"> - <extension point="org.eclipse.cdt.core.LanguageSettingsProvider"> - <provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/> - <provider-reference id="org.eclipse.cdt.core.ReferencedProjectsLanguageSettingsProvider" ref="shared-provider"/> - <provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/> - <provider class="com.arm.eclipse.builder.armcc.discovery.ArmCompiler6LanguageSettingsProvider" console="false" env-hash="1208898303067000398" id="com.arm.eclipse.builder.armcc.v6.langprovider" keep-relative-paths="false" name="Arm Compiler 6 Built-in Compiler Settings" parameter="${COMMAND} ${FLAGS} -E -P -v -dD "${INPUTS}"" prefer-non-shared="true"> - <language-scope id="org.eclipse.cdt.core.gcc"/> - <language-scope id="org.eclipse.cdt.core.g++"/> - </provider> - </extension> - </configuration> -</project> diff --git a/ports_module/cortex_r4/ac6/example_build/tx/.cproject b/ports_module/cortex_r4/ac6/example_build/tx/.cproject index e8a43e7a..9dfee32b 100644 --- a/ports_module/cortex_r4/ac6/example_build/tx/.cproject +++ b/ports_module/cortex_r4/ac6/example_build/tx/.cproject @@ -1,140 +1,164 @@ <?xml version="1.0" encoding="UTF-8" standalone="no"?> <?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage"> - <storageModule moduleId="org.eclipse.cdt.core.settings"> - <cconfiguration id="com.arm.eclipse.build.config.v6.exe.debug.397785280"> - <storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.arm.eclipse.build.config.v6.exe.debug.397785280" moduleId="org.eclipse.cdt.core.settings" name="Debug"> - <externalSettings> - <externalSetting> - <entry flags="VALUE_WORKSPACE_PATH" kind="includePath" name="/tx"/> - <entry flags="VALUE_WORKSPACE_PATH" kind="libraryPath" name="/tx/Debug"/> - <entry flags="RESOLVED" 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<configuration configurationName="Debug"> + + <resource resourceType="PROJECT" workspacePath="/tx"/> + + </configuration> + + <configuration configurationName="Release"> + + <resource resourceType="PROJECT" workspacePath="/tx"/> + + </configuration> + + </storageModule> + + <storageModule moduleId="com.arm.projectSettings" version="6.0.0"/> + + <storageModule moduleId="org.eclipse.cdt.make.core.buildtargets"/> + </cproject> diff --git a/ports_module/cortex_r4/ac6/example_build/tx/.project b/ports_module/cortex_r4/ac6/example_build/tx/.project index 107bae7f..207f353b 100644 --- a/ports_module/cortex_r4/ac6/example_build/tx/.project +++ b/ports_module/cortex_r4/ac6/example_build/tx/.project @@ -55,7 +55,7 @@ <locationURI>$%7BPARENT-5-PROJECT_LOC%7D/common_modules/module_manager/src</locationURI> </link> <link> - <name>src_port</name> + <name>src_port_module_manager</name> <type>2</type> <locationURI>$%7BPARENT-2-PROJECT_LOC%7D/module_manager/src</locationURI> </link> diff --git a/ports_module/cortex_r4/ac6/example_build/tx/.settings/language.settings.xml b/ports_module/cortex_r4/ac6/example_build/tx/.settings/language.settings.xml deleted file mode 100644 index 8a6b8b17..00000000 --- a/ports_module/cortex_r4/ac6/example_build/tx/.settings/language.settings.xml +++ /dev/null @@ -1,25 +0,0 @@ -<?xml version="1.0" encoding="UTF-8" standalone="no"?> -<project> - <configuration id="com.arm.eclipse.build.config.v6.exe.debug.397785280" name="Debug"> - <extension point="org.eclipse.cdt.core.LanguageSettingsProvider"> - <provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/> - <provider-reference id="org.eclipse.cdt.core.ReferencedProjectsLanguageSettingsProvider" ref="shared-provider"/> - <provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/> - <provider class="com.arm.eclipse.builder.armcc.discovery.ArmCompiler6LanguageSettingsProvider" console="false" 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env-hash="1208898303067000398" id="com.arm.eclipse.builder.armcc.v6.langprovider" keep-relative-paths="false" name="Arm Compiler 6 Built-in Compiler Settings" parameter="${COMMAND} ${FLAGS} -E -P -v -dD "${INPUTS}"" prefer-non-shared="true"> - <language-scope id="org.eclipse.cdt.core.gcc"/> - <language-scope id="org.eclipse.cdt.core.g++"/> - </provider> - </extension> - </configuration> -</project> diff --git a/ports_module/cortex_r4/ac6/example_build/txm/.cproject b/ports_module/cortex_r4/ac6/example_build/txm/.cproject index 562815d3..f9012e60 100644 --- a/ports_module/cortex_r4/ac6/example_build/txm/.cproject +++ b/ports_module/cortex_r4/ac6/example_build/txm/.cproject @@ -1,152 +1,176 @@ <?xml version="1.0" encoding="UTF-8" standalone="no"?> <?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage"> - <storageModule moduleId="org.eclipse.cdt.core.settings"> - <cconfiguration id="com.arm.eclipse.build.config.v6.lib.debug.519865483"> - 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+ + <storageModule moduleId="refreshScope" versionNumber="2"> + + <configuration configurationName="Debug"> + + <resource resourceType="PROJECT" workspacePath="/txm"/> + + </configuration> + + <configuration configurationName="Release"> + + <resource resourceType="PROJECT" workspacePath="/txm"/> + + </configuration> + + </storageModule> + + <storageModule moduleId="org.eclipse.cdt.make.core.buildtargets"/> + + <storageModule moduleId="com.arm.projectSettings" version="6.0.0"/> + </cproject> diff --git a/ports_module/cortex_r4/ac6/example_build/txm/.project b/ports_module/cortex_r4/ac6/example_build/txm/.project index e68229d8..f9008cb4 100644 --- a/ports_module/cortex_r4/ac6/example_build/txm/.project +++ b/ports_module/cortex_r4/ac6/example_build/txm/.project @@ -3,7 +3,6 @@ <name>txm</name> <comment></comment> <projects> - <project>tx</project> </projects> <buildSpec> <buildCommand> diff --git a/ports_module/cortex_r4/ac6/example_build/txm/.settings/language.settings.xml b/ports_module/cortex_r4/ac6/example_build/txm/.settings/language.settings.xml deleted file mode 100644 index 23f4ab94..00000000 --- a/ports_module/cortex_r4/ac6/example_build/txm/.settings/language.settings.xml +++ /dev/null @@ -1,25 +0,0 @@ -<?xml version="1.0" encoding="UTF-8" standalone="no"?> -<project> - <configuration id="com.arm.eclipse.build.config.v6.lib.debug.519865483" name="Debug"> - <extension point="org.eclipse.cdt.core.LanguageSettingsProvider"> - <provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/> - <provider-reference id="org.eclipse.cdt.core.ReferencedProjectsLanguageSettingsProvider" ref="shared-provider"/> - <provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/> - <provider class="com.arm.eclipse.builder.armcc.discovery.ArmCompiler6LanguageSettingsProvider" console="false" env-hash="1219961745659432110" id="com.arm.eclipse.builder.armcc.v6.langprovider" keep-relative-paths="false" name="Arm Compiler 6 Built-in Compiler Settings" parameter="${COMMAND} ${FLAGS} -E -P -v -dD "${INPUTS}"" prefer-non-shared="true"> - <language-scope id="org.eclipse.cdt.core.gcc"/> - <language-scope id="org.eclipse.cdt.core.g++"/> - </provider> - </extension> - </configuration> - <configuration id="com.arm.eclipse.build.config.v6.lib.release.2096916400" name="Release"> - <extension point="org.eclipse.cdt.core.LanguageSettingsProvider"> - <provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/> - <provider-reference id="org.eclipse.cdt.core.ReferencedProjectsLanguageSettingsProvider" ref="shared-provider"/> - <provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/> - <provider class="com.arm.eclipse.builder.armcc.discovery.ArmCompiler6LanguageSettingsProvider" console="false" env-hash="1208898303067000398" id="com.arm.eclipse.builder.armcc.v6.langprovider" keep-relative-paths="false" name="Arm Compiler 6 Built-in Compiler Settings" parameter="${COMMAND} ${FLAGS} -E -P -v -dD "${INPUTS}"" prefer-non-shared="true"> - <language-scope id="org.eclipse.cdt.core.gcc"/> - <language-scope id="org.eclipse.cdt.core.g++"/> - </provider> - </extension> - </configuration> -</project> diff --git a/ports_module/cortex_r4/ac6/inc/tx_port.h b/ports_module/cortex_r4/ac6/inc/tx_port.h index 5f480c29..3fba0f78 100644 --- a/ports_module/cortex_r4/ac6/inc/tx_port.h +++ b/ports_module/cortex_r4/ac6/inc/tx_port.h @@ -346,7 +346,7 @@ void tx_thread_vfp_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-R4/AC6 Version 6.1.6 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-R4/AC6 Version 6.1.9 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_module/cortex_r4/ac6/inc/txm_module_port.h b/ports_module/cortex_r4/ac6/inc/txm_module_port.h index 4ea78729..3f64b4f0 100644 --- a/ports_module/cortex_r4/ac6/inc/txm_module_port.h +++ b/ports_module/cortex_r4/ac6/inc/txm_module_port.h @@ -360,7 +360,7 @@ UINT _txm_module_manager_inside_data_check(TXM_MODULE_INSTANCE *module_instance #define TXM_MODULE_MANAGER_VERSION_ID \ CHAR _txm_module_manager_version_id[] = \ - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-R4/MPU/ARM Version 6.1 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-R4/MPU/ARM Version 6.1.9 *"; #endif diff --git a/ports_module/cortex_r4/iar/example_build/tx.ewd b/ports_module/cortex_r4/iar/example_build/tx.ewd deleted file mode 100644 index 49662d42..00000000 --- a/ports_module/cortex_r4/iar/example_build/tx.ewd +++ /dev/null @@ -1,2974 +0,0 @@ -<?xml version="1.0" encoding="UTF-8"?> -<project> - <fileVersion>3</fileVersion> - <configuration> - <name>Debug</name> - <toolchain> - <name>ARM</name> - </toolchain> - <debug>1</debug> - <settings> - <name>C-SPY</name> - <archiveVersion>2</archiveVersion> - <data> - <version>32</version> - <wantNonLocal>1</wantNonLocal> - <debug>1</debug> - <option> - <name>CInput</name> - <state>1</state> - </option> - <option> - <name>CEndian</name> - <state>1</state> - </option> - <option> - <name>CProcessor</name> - <state>1</state> - </option> - <option> - <name>OCVariant</name> - <state>0</state> - </option> - <option> - <name>MacOverride</name> - <state>0</state> - </option> - <option> - <name>MacFile</name> - <state></state> - </option> - <option> - <name>MemOverride</name> - <state>0</state> - </option> - <option> - <name>MemFile</name> - <state></state> - </option> - <option> - <name>RunToEnable</name> - <state>1</state> - </option> - <option> - <name>RunToName</name> - <state>main</state> - </option> - <option> - <name>CExtraOptionsCheck</name> - <state>0</state> - </option> - <option> - <name>CExtraOptions</name> - <state></state> - </option> - <option> - <name>CFpuProcessor</name> - <state>1</state> - </option> - <option> - <name>OCDDFArgumentProducer</name> - <state></state> - </option> - <option> - <name>OCDownloadSuppressDownload</name> - <state>0</state> - </option> - <option> - <name>OCDownloadVerifyAll</name> - <state>0</state> - </option> - <option> - <name>OCProductVersion</name> - <state>4.11A</state> - </option> - <option> - <name>OCDynDriverList</name> - <state>ARMSIM_ID</state> - </option> - <option> - <name>OCLastSavedByProductVersion</name> - <state>6.20.1.52589</state> - </option> - <option> - <name>UseFlashLoader</name> - <state>0</state> - </option> - <option> - <name>CLowLevel</name> - <state>1</state> - </option> - <option> - <name>OCBE8Slave</name> - <state>1</state> - </option> - <option> - <name>MacFile2</name> - <state></state> - </option> - <option> - <name>CDevice</name> - <state>1</state> - </option> - <option> - <name>FlashLoadersV3</name> - <state>$TOOLKIT_DIR$\config\flashloader\</state> - </option> - <option> - <name>OCImagesSuppressCheck1</name> - <state>0</state> - </option> - <option> - <name>OCImagesPath1</name> - <state></state> - </option> - <option> - <name>OCImagesSuppressCheck2</name> - <state>0</state> - </option> - <option> - <name>OCImagesPath2</name> - <state></state> - </option> - <option> - <name>OCImagesSuppressCheck3</name> - <state>0</state> - </option> - <option> - <name>OCImagesPath3</name> - <state></state> - </option> - <option> - <name>OverrideDefFlashBoard</name> - <state>0</state> - </option> - <option> - <name>OCImagesOffset1</name> - <state></state> - </option> - <option> - <name>OCImagesOffset2</name> - <state></state> - </option> - <option> - <name>OCImagesOffset3</name> - <state></state> - </option> - <option> - <name>OCImagesUse1</name> - <state>0</state> - </option> - <option> - <name>OCImagesUse2</name> - <state>0</state> - </option> - <option> - <name>OCImagesUse3</name> - <state>0</state> - </option> - <option> - <name>OCDeviceConfigMacroFile</name> - <state>1</state> - </option> - <option> - <name>OCDebuggerExtraOption</name> - <state>1</state> - </option> - <option> - <name>OCAllMTBOptions</name> - <state>1</state> - </option> - <option> - <name>OCMulticoreNrOfCores</name> - <state></state> - </option> - <option> - <name>OCMulticoreWorkspace</name> - <state></state> - </option> - <option> - <name>OCMulticoreSlaveProject</name> - <state></state> - </option> - <option> - <name>OCMulticoreSlaveConfiguration</name> - <state></state> - </option> - <option> - <name>OCDownloadExtraImage</name> - <state>1</state> - </option> - <option> - <name>OCAttachSlave</name> - <state>0</state> - </option> - <option> - <name>MassEraseBeforeFlashing</name> - <state>0</state> - </option> - <option> - <name>OCMulticoreNrOfCoresSlave</name> - <state>1</state> - </option> - <option> - <name>OCMulticoreAMPConfigType</name> - <state>0</state> - </option> - <option> - <name>OCMulticoreSessionFile</name> - <state></state> - </option> - <option> - <name>OCTpiuBaseOption</name> - <state>1</state> - </option> - </data> - </settings> - <settings> - <name>ARMSIM_ID</name> - <archiveVersion>2</archiveVersion> - <data> - <version>1</version> - <wantNonLocal>1</wantNonLocal> - <debug>1</debug> - <option> - <name>OCSimDriverInfo</name> - <state>1</state> - </option> - <option> - <name>OCSimEnablePSP</name> - <state>0</state> - </option> - <option> - <name>OCSimPspOverrideConfig</name> - <state>0</state> - </option> - <option> - <name>OCSimPspConfigFile</name> - <state></state> - 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<debug>0</debug> - <option> - <name>OCDriverInfo</name> - <state>1</state> - </option> - <option> - <name>LmiftdiSpeed</name> - <state>500</state> - </option> - <option> - <name>CCLmiftdiDoLogfile</name> - <state>0</state> - </option> - <option> - <name>CCLmiftdiLogFile</name> - <state>$TOOLKIT_DIR$\cspycomm.log</state> - </option> - <option> - <name>CCLmiFtdiInterfaceRadio</name> - <state>0</state> - </option> - <option> - <name>CCLmiFtdiInterfaceCmdLine</name> - <state>0</state> - </option> - </data> - </settings> - <settings> - <name>NULINK_ID</name> - <archiveVersion>2</archiveVersion> - <data> - <version>0</version> - <wantNonLocal>1</wantNonLocal> - <debug>0</debug> - <option> - <name>OCDriverInfo</name> - <state>1</state> - </option> - <option> - <name>DoLogfile</name> - <state>0</state> - </option> - <option> - <name>LogFile</name> - <state>$PROJ_DIR$\cspycomm.log</state> - </option> - </data> - </settings> - <settings> - <name>PEMICRO_ID</name> - <archiveVersion>2</archiveVersion> - <data> - <version>3</version> - <wantNonLocal>1</wantNonLocal> - <debug>0</debug> - <option> - <name>OCDriverInfo</name> - <state>1</state> - </option> - <option> - <name>CCJPEMicroShowSettings</name> - <state>0</state> - </option> - <option> - <name>DoLogfile</name> - <state>0</state> - </option> - <option> - <name>LogFile</name> - <state>$PROJ_DIR$\cspycomm.log</state> - </option> - </data> - </settings> - <settings> - <name>STLINK_ID</name> - <archiveVersion>2</archiveVersion> - <data> - <version>7</version> - <wantNonLocal>1</wantNonLocal> - <debug>0</debug> - <option> - <name>OCDriverInfo</name> - <state>1</state> - </option> - <option> - <name>CCSTLinkInterfaceRadio</name> - <state>0</state> - </option> - <option> - <name>CCSTLinkInterfaceCmdLine</name> - <state>0</state> - </option> - <option> - <name>CCSTLinkResetList</name> - <version>3</version> - <state>0</state> - </option> - <option> - <name>CCCpuClockEdit</name> - <state>72.0</state> - </option> - <option> - <name>CCSwoClockAuto</name> - <state>0</state> - </option> - <option> - <name>CCSwoClockEdit</name> - <state>2000</state> - </option> - <option> - <name>DoLogfile</name> - <state>0</state> - </option> - <option> - <name>LogFile</name> - <state>$PROJ_DIR$\cspycomm.log</state> - </option> - <option> - <name>CCSTLinkDoUpdateBreakpoints</name> - <state>0</state> - </option> - <option> - <name>CCSTLinkUpdateBreakpoints</name> - <state>_call_main</state> - </option> - <option> - <name>CCSTLinkCatchCORERESET</name> - <state>0</state> - </option> - <option> - <name>CCSTLinkCatchMMERR</name> - <state>0</state> - </option> - <option> - <name>CCSTLinkCatchNOCPERR</name> - <state>0</state> - </option> - <option> - <name>CCSTLinkCatchCHRERR</name> - <state>0</state> - </option> - <option> - <name>CCSTLinkCatchSTATERR</name> - <state>0</state> - </option> - <option> - <name>CCSTLinkCatchBUSERR</name> - <state>0</state> - </option> - <option> - <name>CCSTLinkCatchINTERR</name> - <state>0</state> - </option> - <option> - <name>CCSTLinkCatchSFERR</name> - <state>0</state> - </option> - <option> - <name>CCSTLinkCatchHARDERR</name> - <state>0</state> - </option> - <option> - <name>CCSTLinkCatchDummy</name> - <state>0</state> - </option> - <option> - <name>CCSTLinkUsbSerialNo</name> - <state></state> - </option> - <option> - <name>CCSTLinkUsbSerialNoSelect</name> - <state>0</state> - </option> - <option> - <name>CCSTLinkJtagSpeedList</name> - <version>2</version> - <state>0</state> - </option> - <option> - <name>CCSTLinkDAPNumber</name> - <state></state> - </option> - <option> - <name>CCSTLinkDebugAccessPortRadio</name> - <state>0</state> - </option> - <option> - <name>CCSTLinkUseServerSelect</name> - <state>0</state> - </option> - <option> - <name>CCSTLinkProbeList</name> - <version>1</version> - <state>0</state> - </option> - </data> - </settings> - <settings> - <name>THIRDPARTY_ID</name> - <archiveVersion>2</archiveVersion> - <data> - <version>0</version> - <wantNonLocal>1</wantNonLocal> - <debug>0</debug> - <option> - <name>CThirdPartyDriverDll</name> - <state>Browse to your third-party driver</state> - </option> - <option> - <name>CThirdPartyLogFileCheck</name> - <state>0</state> - </option> - <option> - <name>CThirdPartyLogFileEditB</name> - <state>$TOOLKIT_DIR$\cspycomm.log</state> - </option> - <option> - <name>OCDriverInfo</name> - <state>1</state> - </option> - </data> - </settings> - <settings> - <name>TIFET_ID</name> - <archiveVersion>2</archiveVersion> - <data> - <version>1</version> - <wantNonLocal>1</wantNonLocal> - <debug>0</debug> - <option> - <name>OCDriverInfo</name> - <state>1</state> - </option> - <option> - <name>CCMSPFetResetList</name> - <version>0</version> - <state>0</state> - </option> - <option> - <name>CCMSPFetInterfaceRadio</name> - <state>0</state> - </option> - <option> - <name>CCMSPFetInterfaceCmdLine</name> - <state>0</state> - </option> - <option> - <name>CCMSPFetTargetVccTypeDefault</name> - <state>0</state> - </option> - <option> - <name>CCMSPFetTargetVoltage</name> - <state>###Uninitialized###</state> - </option> - <option> - <name>CCMSPFetVCCDefault</name> - <state>1</state> - </option> - <option> - <name>CCMSPFetTargetSettlingtime</name> - <state>0</state> - </option> - <option> - <name>CCMSPFetRadioJtagSpeedType</name> - <state>1</state> - </option> - <option> - <name>CCMSPFetConnection</name> - <version>0</version> - <state>0</state> - </option> - <option> - <name>CCMSPFetUsbComPort</name> - <state>Automatic</state> - </option> - <option> - <name>CCMSPFetAllowAccessToBSL</name> - <state>0</state> - </option> - <option> - <name>CCMSPFetDoLogfile</name> - <state>0</state> - </option> - <option> - <name>CCMSPFetLogFile</name> - <state>$PROJ_DIR$\cspycomm.log</state> - </option> - <option> - <name>CCMSPFetRadioEraseFlash</name> - <state>1</state> - </option> - </data> - </settings> - <settings> - <name>XDS100_ID</name> - <archiveVersion>2</archiveVersion> - <data> - <version>8</version> - <wantNonLocal>1</wantNonLocal> - <debug>0</debug> - <option> - <name>OCDriverInfo</name> - <state>1</state> - </option> - <option> - <name>TIPackageOverride</name> - <state>0</state> - </option> - <option> - <name>TIPackage</name> - <state></state> - </option> - <option> - <name>BoardFile</name> - <state></state> - </option> - <option> - <name>DoLogfile</name> - <state>0</state> - </option> - <option> - <name>LogFile</name> - <state>$PROJ_DIR$\cspycomm.log</state> - </option> - <option> - <name>CCXds100BreakpointRadio</name> - <state>0</state> - </option> - <option> - <name>CCXds100DoUpdateBreakpoints</name> - <state>0</state> - </option> - <option> - <name>CCXds100UpdateBreakpoints</name> - <state>_call_main</state> - </option> - <option> - <name>CCXds100CatchReset</name> - <state>0</state> - </option> - <option> - <name>CCXds100CatchUndef</name> - <state>0</state> - </option> - <option> - <name>CCXds100CatchSWI</name> - <state>0</state> - </option> - <option> - <name>CCXds100CatchData</name> - <state>0</state> - </option> - <option> - <name>CCXds100CatchPrefetch</name> - <state>0</state> - </option> - <option> - <name>CCXds100CatchIRQ</name> - <state>0</state> - </option> - <option> - <name>CCXds100CatchFIQ</name> - <state>0</state> - </option> - <option> - <name>CCXds100CatchCORERESET</name> - <state>0</state> - </option> - <option> - <name>CCXds100CatchMMERR</name> - <state>0</state> - </option> - <option> - <name>CCXds100CatchNOCPERR</name> - <state>0</state> - </option> - <option> - <name>CCXds100CatchCHRERR</name> - <state>0</state> - </option> - <option> - <name>CCXds100CatchSTATERR</name> - <state>0</state> - </option> - <option> - <name>CCXds100CatchBUSERR</name> - <state>0</state> - </option> - <option> - <name>CCXds100CatchINTERR</name> - <state>0</state> - </option> - <option> - <name>CCXds100CatchSFERR</name> - <state>0</state> - </option> - <option> - <name>CCXds100CatchHARDERR</name> - <state>0</state> - </option> - <option> - <name>CCXds100CatchDummy</name> - <state>0</state> - </option> - <option> - <name>CCXds100CpuClockEdit</name> - <state></state> - </option> - <option> - <name>CCXds100SwoClockAuto</name> - <state>0</state> - </option> - <option> - <name>CCXds100SwoClockEdit</name> - <state>1000</state> - </option> - <option> - <name>CCXds100HWResetDelay</name> - <state>0</state> - </option> - <option> - <name>CCXds100ResetList</name> - <version>0</version> - <state>0</state> - </option> - <option> - <name>CCXds100UsbSerialNo</name> - <state></state> - </option> - <option> - <name>CCXds100UsbSerialNoSelect</name> - <state>0</state> - </option> - <option> - <name>CCXds100JtagSpeedList</name> - <version>0</version> - <state>0</state> - </option> - <option> - <name>CCXds100InterfaceRadio</name> - <state>2</state> - </option> - <option> - <name>CCXds100InterfaceCmdLine</name> - <state>0</state> - </option> - <option> - <name>CCXds100ProbeList</name> - <version>0</version> - <state>2</state> - </option> - <option> - <name>CCXds100SWOPortRadio</name> - <state>0</state> - </option> - <option> - <name>CCXds100SWOPort</name> - <state>1</state> - </option> - <option> - <name>CCXDSTargetVccEnable</name> - <state>0</state> - </option> - <option> - <name>CCXDSTargetVoltage</name> - <state>###Uninitialized###</state> - </option> - <option> - <name>OCXDSDigitalStatesConfigFile</name> - <state>1</state> - </option> - </data> - </settings> - <debuggerPlugins> - <plugin> - <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin</file> - <loadFlag>0</loadFlag> - </plugin> - <plugin> - <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin</file> - <loadFlag>0</loadFlag> - </plugin> - <plugin> - <file>$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin</file> - <loadFlag>0</loadFlag> - </plugin> - <plugin> - <file>$TOOLKIT_DIR$\plugins\rtos\FreeRtos\FreeRtosArmPlugin.ENU.ewplugin</file> - <loadFlag>0</loadFlag> - </plugin> - <plugin> - <file>$TOOLKIT_DIR$\plugins\rtos\HWRTOSplugin\HWRTOSplugin.ewplugin</file> - <loadFlag>0</loadFlag> - </plugin> - <plugin> - <file>$TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin</file> - <loadFlag>0</loadFlag> - </plugin> - <plugin> - <file>$TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin2.ENU.ewplugin</file> - <loadFlag>0</loadFlag> - </plugin> - <plugin> - <file>$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin</file> - <loadFlag>0</loadFlag> - </plugin> - <plugin> - <file>$TOOLKIT_DIR$\plugins\rtos\RemedyRtosViewer\RemedyRtosViewer.ewplugin</file> - <loadFlag>0</loadFlag> - </plugin> - <plugin> - <file>$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin</file> - <loadFlag>0</loadFlag> - </plugin> - <plugin> - <file>$TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm8b.ewplugin</file> - <loadFlag>0</loadFlag> - </plugin> - <plugin> - <file>$TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm8bBE.ewplugin</file> - <loadFlag>0</loadFlag> - </plugin> - <plugin> - <file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin</file> - <loadFlag>0</loadFlag> - </plugin> - <plugin> - <file>$TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin</file> - <loadFlag>0</loadFlag> - </plugin> - <plugin> - <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin</file> - <loadFlag>0</loadFlag> - </plugin> - <plugin> - <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin</file> - <loadFlag>0</loadFlag> - </plugin> - <plugin> - <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin</file> - <loadFlag>0</loadFlag> - </plugin> - <plugin> - <file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file> - <loadFlag>0</loadFlag> - </plugin> - <plugin> - <file>$EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin</file> - <loadFlag>0</loadFlag> - </plugin> - <plugin> - <file>$EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin</file> - <loadFlag>0</loadFlag> - </plugin> - </debuggerPlugins> - </configuration> -</project> diff --git a/ports_module/cortex_r4/iar/inc/tx_port.h b/ports_module/cortex_r4/iar/inc/tx_port.h index b653cd20..dc72590a 100644 --- a/ports_module/cortex_r4/iar/inc/tx_port.h +++ b/ports_module/cortex_r4/iar/inc/tx_port.h @@ -395,7 +395,7 @@ void tx_thread_vfp_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-R4/IAR Version 6.1.6 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-R4/IAR Version 6.1.9 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports_module/cortex_r4/iar/inc/txm_module_port.h b/ports_module/cortex_r4/iar/inc/txm_module_port.h index cf504a45..10a00ed7 100644 --- a/ports_module/cortex_r4/iar/inc/txm_module_port.h +++ b/ports_module/cortex_r4/iar/inc/txm_module_port.h @@ -341,7 +341,7 @@ UINT _txm_module_manager_inside_data_check(TXM_MODULE_INSTANCE *module_instance #define TXM_MODULE_MANAGER_VERSION_ID \ CHAR _txm_module_manager_version_id[] = \ - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-R4/MPU/IAR Version 6.1 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-R4/MPU/IAR Version 6.1.9 *"; #endif diff --git a/ports_module/rxv2/iar/example_build/hwsetup.c b/ports_module/rxv2/iar/example_build/hwsetup.c new file mode 100644 index 00000000..ab3e3bac --- /dev/null +++ b/ports_module/rxv2/iar/example_build/hwsetup.c @@ -0,0 +1,189 @@ +/* Adapted for use with IAR Embedded Workbench */ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : hwsetup.c +* Version : 1.0 +* Device(s) : RX +* H/W Platform : RX65N +* Description : Defines the initialisation routines used each time the MCU is restarted. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes <System Includes> , "Project Includes" +***********************************************************************************************************************/ +#include <stdint.h> +#include <intrinsics.h> + +/* Contains delcarations for the functions defined in this file */ +#include "hwsetup.h" + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ +/* Clock configuration function delcaration */ +void operating_frequency_set(void); + +/* MCU I/O port configuration function delcaration */ +//static void output_ports_configure(void); + +/* Interrupt configuration function delcaration */ +static void interrupts_configure(void); + +/* MCU peripheral module configuration function declaration */ +//static void peripheral_modules_enable(void); + + +/******************************************************************************* +* Function name: hardware_setup +* Description : Contains setup functions called at device restart +* Arguments : none +* Return value : none +*******************************************************************************/ +void hardware_setup(void) +{ + operating_frequency_set(); + interrupts_configure(); +} + + + +/******************************************************************************* +* Function name: operating_frequency_set +* Description : Configures the clock settings for each of the device clocks +* Arguments : none +* Return value : none +*******************************************************************************/ +void operating_frequency_set(void) +{ + + /* + Clock Description Frequency + ---------------------------------------- + Input Clock Frequency............ 24 MHz + Divisor.......................... 2 + PLL frequency (x16).............. 192 MHz + Internal Clock Frequency......... 96 MHz + Peripheral Clock Frequency....... 48 MHz + USB Clock Frequency.............. 48 MHz + External Bus Clock Frequency..... 24 MHz */ + + volatile unsigned int i; + + /* Protect off. */ + SYSTEM.PRCR.WORD = 0xA50B; + + /* Uncomment if not using sub-clock */ + //SYSTEM.SOSCCR.BYTE = 0x01; /* stop sub-clock */ + SYSTEM.SOSCCR.BYTE = 0x00; /* Enable sub-clock for RTC */ + + /* Wait 131,072 cycles * 12 MHz = 10.9 ms */ + SYSTEM.MOSCWTCR.BYTE = 0x0D; + + /* x16 @PLL, 2 divisor */ + SYSTEM.PLLCR.WORD = 0x0F01; + + /* EXTAL ON */ + SYSTEM.MOSCCR.BYTE = 0x00; + + /* PLL ON */ + SYSTEM.PLLCR2.BYTE = 0x00; + + for(i = 0;i< 0x168;i++) + { + /* Wait over 12ms */ + __no_operation(); + } + + /* Setup system clocks + SCKCR - System Clock Control Register + b31:b28 FCK[3:0] 0x02 = Flash clock: PLL/4 = (192 / 4) = 48 MHz + b27:b24 ICK[3:0] 0x01 = System clock: PLL/2 = (192 / 2) = 96 MHz + b23 PSTOP1 0x00 = BCLK pin output is enabled + b19:b16 BCK[3:0] 0x03 = BCLK: PLL/8 = 24 MHz + b11:b8 PCKB[3:0] 0x02 = Peripheral clock B: PLL/4 = 48 MHz + */ + SYSTEM.SCKCR.LONG = 0x21031222; /* ICK=PLL/2,BCK,FCK,PCK=PLL/4 */ + + /* Setup IEBUS and USB clocks + SCKCR2 - System Clock Control Register 2 + b7:b4 UCK[3:0] 0x03 = USB clock is PLL/4 = 48 MHz + b3:b0 IEBCK[3:0] 0x01 = IE Bus clock is PLL/2 = 96 MHz + */ + SYSTEM.SCKCR2.WORD = 0x0031; + + /* ICLK, PCLKB, FCLK, BCLK, IECLK, and USBCLK all come from PLL circuit */ + SYSTEM.SCKCR3.WORD = 0x0400; + + /* Protect on. */ + SYSTEM.PRCR.WORD = 0xA500; +} + + +/*********************************************************************************************************************** +* Function name: interrupts_configure +* Description : Configures interrupts used +* Arguments : none +* Return value : none +***********************************************************************************************************************/ +void interrupts_configure(void) +{ + /* Protect off. */ + SYSTEM.PRCR.WORD = 0xA50B; + + /* Enable the bus error interrupt to catch accesses to illegal/reserved areas + of memory. */ + + /* Clear any pending interrupts */ + IR(BSC,BUSERR) = 0; + /* Make this the highest priority interrupt (adjust as necessary for your + application) */ + IPR(BSC,BUSERR) = 0x0F; + /* Enable the interrupt in the ICU */ + IEN(BSC,BUSERR) = 1; + /* Enable illegal address interrupt in the BSC */ + BSC.BEREN.BIT.IGAEN = 1; +} + + +/****************************************************************************** +* Function name: buserr_isr +* Description : Sample ISR for bus error (must do hardware setup first!) +* By default, this demo code enables the Bus Error Interrupt. +* This interrupt will fire if the user tries to access code +* or data from one of the reserved areas in the memory map, +* including the areas covered by disabled chip selects. +* A nop statement is included here as a convenient place +* to set a breakpoint during debugging and development, and +* further handling should be added by the user for their +* application. +* Arguments : none +* Return value : none +******************************************************************************/ +#pragma vector = VECT_BSC_BUSERR +__interrupt void buserr_isr(void) +{ + /* To find the address that was accessed when the bus error occured, read + the register BSC.BERSR2.WORD. The upper 13 bits of this register + contain the upper 13-bits of the offending address (in 512K byte units). + */ + + /* Add your own code here to handle this interrupt */ + __no_operation(); +} diff --git a/ports_module/rxv2/iar/example_build/hwsetup.h b/ports_module/rxv2/iar/example_build/hwsetup.h new file mode 100644 index 00000000..d2bae5f6 --- /dev/null +++ b/ports_module/rxv2/iar/example_build/hwsetup.h @@ -0,0 +1,49 @@ +/* Adapted for use with IAR Embedded Workbench */ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : hwsetup.h +* Version : 1.0 +* Description : Hardware setup header file.. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 26.10.2011 1.00 First Release +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +/* Multiple inclusion prevention macro */ +#ifndef HWSETUP_H +#define HWSETUP_H + +/*********************************************************************************************************************** +Includes <System Includes> , "Project Includes" +***********************************************************************************************************************/ +#include <iorx65n.h> + +/*********************************************************************************************************************** +Exported global functions (to be accessed by other files) +***********************************************************************************************************************/ +/* Hardware setup funtion declaration */ +void hardware_setup(void); + +/* End of multiple inclusion prevention macro */ +#endif diff --git a/ports_module/rxv2/iar/example_build/low_level_init.c b/ports_module/rxv2/iar/example_build/low_level_init.c new file mode 100644 index 00000000..5b89a40a --- /dev/null +++ b/ports_module/rxv2/iar/example_build/low_level_init.c @@ -0,0 +1,43 @@ +/* + * lowinit.c + * + * This module contains the function '__low_level_init', a function + * that is called before the 'main' function of the program. Normally + * low-level initializations - such as setting the prefered interrupt + * level or setting the watchdog - can be performed here. + * + * Note that this function is called before the data segments are + * initialized, this means that this function can't rely on the + * values of global or static variables. + * + * When this function returns zero, the startup code will inhibit the + * initialization of the data segments. The result is faster startup, + * the drawback is that neither global nor static data will be + * initialized. + * + * + * Copyright 2009-2010 IAR Systems AB. + * + * $Revision: 2717 $ + */ + +#pragma language=extended + +#include <iorx65n.h> +#include <intrinsics.h> +#include "hwsetup.h" + +__intrinsic +int __low_level_init ( void ) +{ + hardware_setup(); + + /*==================================*/ + /* Choose if segment initialization */ + /* should be done or not. */ + /* Return: 0 to omit seg_init */ + /* 1 to run seg_init */ + /*==================================*/ + return (1); +} +#pragma language=default diff --git a/ports_module/rxv2/iar/example_build/sample_manager_linker.icf b/ports_module/rxv2/iar/example_build/sample_manager_linker.icf new file mode 100644 index 00000000..b9dbaec1 --- /dev/null +++ b/ports_module/rxv2/iar/example_build/sample_manager_linker.icf @@ -0,0 +1,57 @@ +//----------------------------------------------------------------------------- +// ILINK command file template for the Renesas RX microcontroller R5F565N9 +//----------------------------------------------------------------------------- +define exported symbol __link_file_version_4 = 1; +define memory mem with size = 4G; + +// ID Code Protection +define exported symbol __ID_BYTES_1_4 = 0xFFFFFFFF; +define exported symbol __ID_BYTES_5_8 = 0xFFFFFFFF; +define exported symbol __ID_BYTES_9_12 = 0xFFFFFFFF; +define exported symbol __ID_BYTES_13_16 = 0xFFFFFFFF; + +// Endian Select Register (MDE) +// Choose between Little endian=0xFFFFFFFF or Big endian=0xFFFFFFF8 +define exported symbol __MDES = 0xFFFFFFFF; + +// Option Function Select Register 0 (OFS0) +define exported symbol __OFS0 = 0xFFFFFFFF; + +// Option Function Select Register 1 (OFS1) +define exported symbol __OFS1 = 0xFFFFFFFF; + +define region ROM_region16 = mem:[from 0xFFFF8000 to 0xFFF10000]; +define region RAM_region16 = mem:[from 0x00000004 to 0x0003FFFF]; +define region ROM_region24 = mem:[from 0xFFF00000 to 0xFFF10000]; +define region RAM_region24 = mem:[from 0x00000004 to 0x0003FFFF]; +define region ROM_region32 = mem:[from 0xFFF00000 to 0xFFF10000]; +define region RAM_region32 = mem:[from 0x00000004 to 0x0003FFFF]; + +initialize by copy { rw, ro section D, ro section D_1, ro section D_2 }; +do not initialize { section .*.noinit }; + +define block HEAP with alignment = 4, size = _HEAP_SIZE { }; +define block USTACK with alignment = 4, size = _USTACK_SIZE { }; +define block ISTACK with alignment = 4, size = _ISTACK_SIZE { }; + +define block STACKS with fixed order { block ISTACK, + block USTACK }; +place at address mem:0xFE7F5D00 { ro section .option_mem }; +place at address mem:0xFFFFFF80 { ro section .exceptvect }; +place at address mem:0xFFFFFFFC { ro section .resetvect }; + +"ROM16":place in ROM_region16 { ro section .code16*, + ro section .data16* }; +"RAM16":place in RAM_region16 { rw section .data16*, + rw section __DLIB_PERTHREAD }; +"ROM24":place in ROM_region24 { ro section .code24*, + ro section .data24* }; +"RAM24":place in RAM_region24 { rw section .data24* }; +"ROM32":place in ROM_region32 { ro }; +"RAM32":place in RAM_region32 { rw, + ro section D, + ro section D_1, + ro section D_2, + block HEAP, + block STACKS, + last section FREEMEM }; diff --git a/ports_module/rxv2/iar/example_build/sample_module_linker.icf b/ports_module/rxv2/iar/example_build/sample_module_linker.icf new file mode 100644 index 00000000..b6187731 --- /dev/null +++ b/ports_module/rxv2/iar/example_build/sample_module_linker.icf @@ -0,0 +1,78 @@ +//----------------------------------------------------------------------------- +// ILINK command file template for the Renesas RX microcontroller R5F565N +//----------------------------------------------------------------------------- +define exported symbol __link_file_version_4 = 1; + +define memory mem with size = 4G; + +// ID Code Protection +define exported symbol __ID_BYTES_1_4 = 0xFFFFFFFF; +define exported symbol __ID_BYTES_5_8 = 0xFFFFFFFF; +define exported symbol __ID_BYTES_9_12 = 0xFFFFFFFF; +define exported symbol __ID_BYTES_13_16 = 0xFFFFFFFF; + +// Endian Select Register (MDE) +// Choose between Little endian=0xFFFFFFFF or Big endian=0xFFFFFFF8 +define exported symbol __MDES = 0xFFFFFFFF; + +// Option Function Select Register 0 (OFS0) +define exported symbol __OFS0 = 0xFFFFFFFF; + +// Option Function Select Register 1 (OFS1) +define exported symbol __OFS1 = 0xFFFFFFFF; + +//define region ROM_region16 = mem:[from 0xFFFF8000 to 0xFFFFFFFF]; +define region RAM_region16 = mem:[from 0x00010000 to 0x00017FFF]; +//define region ROM_region24 = mem:[from 0xFFF00000 to 0xFFFFFFFF]; +//define region RAM_region24 = mem:[from 0x00000004 to 0x0001FFFF]; +define region ROM_region32 = mem:[from 0xFFF10400 to 0xFFFFFFFF]; +//define region RAM_region32 = mem:[from 0x00000004 to 0x0001FFFF]; +//define region DATA_FLASH_region = mem:[from 0x00100000 to 0x00107FFF]; + +initialize by copy { rw, ro section D, ro section D_1, ro section D_2 }; +do not initialize { section .*.noinit }; + +define block HEAP with alignment = 4, size = _HEAP_SIZE { }; +//define block USTACK with alignment = 4, size = _USTACK_SIZE { }; +//define block ISTACK with alignment = 4, size = _ISTACK_SIZE { }; + +//define block STACKS with fixed order { block ISTACK, +// block USTACK }; + +//place at address mem:0xFFFFFF80 { ro section .nmivec }; +//"ROM16":place in ROM_region16 { ro section .code16*, +// ro section .data16* }; +//"RAM16":place in RAM_region16 { rw section .data16*, +// rw section __DLIB_PERTHREAD }; +//"ROM24":place in ROM_region24 { ro section .code24*, +// ro section .data24* }; +//"RAM24":place in RAM_region24 { rw section .data24* }; +//"ROM32":place in ROM_region32 { ro }; +//"RAM32":place in RAM_region32 { rw, +// ro section D, +// ro section D_1, +// ro section D_2, +// block HEAP, +// block STACKS, +// last section FREEMEM }; + +//"DATAFLASH":place in DATA_FLASH_region +// { ro section .dataflash* }; + +define movable block ROPI with alignment = 4, fixed order, static base CB +{ + ro object txm_module_preamble_rx65n.o, + ro, + ro data +}; + +define movable block RWPI with alignment = 8, fixed order, static base SB +{ + rw section .sbdata*, + rw section .sbrel*, + rw section __DLIB_PERTHREAD, + block HEAP +}; + +place in ROM_region32 { block ROPI }; +place in RAM_region16 { block RWPI }; diff --git a/ports_module/rxv2/iar/example_build/sample_threadx_module.c b/ports_module/rxv2/iar/example_build/sample_threadx_module.c new file mode 100644 index 00000000..51822c10 --- /dev/null +++ b/ports_module/rxv2/iar/example_build/sample_threadx_module.c @@ -0,0 +1,425 @@ +/* This is a small demo of the high-performance ThreadX kernel running as a module. It includes + examples of eight threads of different priorities, using a message queue, semaphore, mutex, + event flags group, byte pool, and block pool. */ + +/* Specify that this is a module! */ + +#define TXM_MODULE + + +/* Include the ThreadX module definitions. */ + +#include "txm_module.h" + + +/* Define constants. */ + +#define DEMO_STACK_SIZE 1024 +#define DEMO_BYTE_POOL_SIZE 9120 +#define DEMO_BLOCK_POOL_SIZE 100 +#define DEMO_QUEUE_SIZE 100 + + +/* Define the pool space in the bss section of the module. ULONG is used to + get the word alignment. */ + +ULONG demo_module_pool_space[DEMO_BYTE_POOL_SIZE / 4]; + +/* Define the ThreadX object control blocks... */ + +TX_THREAD *thread_0; +TX_THREAD *thread_1; +TX_THREAD *thread_2; +TX_THREAD *thread_3; +TX_THREAD *thread_4; +TX_THREAD *thread_5; +TX_THREAD *thread_6; +TX_THREAD *thread_7; +TX_QUEUE *queue_0; +TX_SEMAPHORE *semaphore_0; +TX_MUTEX *mutex_0; +TX_EVENT_FLAGS_GROUP *event_flags_0; +TX_BYTE_POOL *byte_pool_0; +TX_BLOCK_POOL *block_pool_0; + +/* Define the counters used in the demo application... */ + +ULONG thread_0_counter; +ULONG thread_1_counter; +ULONG thread_1_messages_sent; +ULONG thread_2_counter; +ULONG thread_2_messages_received; +ULONG thread_3_counter; +ULONG thread_4_counter; +ULONG thread_5_counter; +ULONG thread_6_counter; +ULONG thread_7_counter; +ULONG semaphore_0_puts; +ULONG event_0_sets; +ULONG queue_0_sends; + +/* Define thread prototypes. */ + +void thread_0_entry(ULONG thread_input); +void thread_1_entry(ULONG thread_input); +void thread_2_entry(ULONG thread_input); +void thread_3_and_4_entry(ULONG thread_input); +void thread_5_entry(ULONG thread_input); +void thread_6_and_7_entry(ULONG thread_input); + +void semaphore_0_notify(TX_SEMAPHORE *semaphore_ptr) +{ + + if (semaphore_ptr == semaphore_0) + semaphore_0_puts++; +} + + +void event_0_notify(TX_EVENT_FLAGS_GROUP *event_flag_group_ptr) +{ + + if (event_flag_group_ptr == event_flags_0) + event_0_sets++; +} + + +void queue_0_notify(TX_QUEUE *queue_ptr) +{ + + if (queue_ptr == queue_0) + queue_0_sends++; +} + + +/* Define the module start function. */ + +void demo_module_start(ULONG id) +{ + +CHAR *pointer; + + /* Allocate all the objects. In MPU mode, modules cannot allocate control blocks within + their own memory area so they cannot corrupt the resident portion of ThreadX by overwriting + the control block(s). */ + txm_module_object_allocate((void*)&thread_0, sizeof(TX_THREAD)); + txm_module_object_allocate((void*)&thread_1, sizeof(TX_THREAD)); + txm_module_object_allocate((void*)&thread_2, sizeof(TX_THREAD)); + txm_module_object_allocate((void*)&thread_3, sizeof(TX_THREAD)); + txm_module_object_allocate((void*)&thread_4, sizeof(TX_THREAD)); + txm_module_object_allocate((void*)&thread_5, sizeof(TX_THREAD)); + txm_module_object_allocate((void*)&thread_6, sizeof(TX_THREAD)); + txm_module_object_allocate((void*)&thread_7, sizeof(TX_THREAD)); + txm_module_object_allocate((void*)&queue_0, sizeof(TX_QUEUE)); + txm_module_object_allocate((void*)&semaphore_0, sizeof(TX_SEMAPHORE)); + txm_module_object_allocate((void*)&mutex_0, sizeof(TX_MUTEX)); + txm_module_object_allocate((void*)&event_flags_0, sizeof(TX_EVENT_FLAGS_GROUP)); + txm_module_object_allocate((void*)&byte_pool_0, sizeof(TX_BYTE_POOL)); + txm_module_object_allocate((void*)&block_pool_0, sizeof(TX_BLOCK_POOL)); + + + /* Create a byte memory pool from which to allocate the thread stacks. */ + tx_byte_pool_create(byte_pool_0, "module byte pool 0", demo_module_pool_space, DEMO_BYTE_POOL_SIZE); + + /* Put system definition stuff in here, e.g. thread creates and other assorted + create information. */ + + /* Allocate the stack for thread 0. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create the main thread. */ + tx_thread_create(thread_0, "module thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, + 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); + + + /* Allocate the stack for thread 1. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 1 and 2. These threads pass information through a ThreadX + message queue. It is also interesting to note that these threads have a time + slice. */ + tx_thread_create(thread_1, "module thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 2. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(thread_2, "module thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 3. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + An interesting thing here is that both threads share the same instruction area. */ + tx_thread_create(thread_3, "module thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 4. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(thread_4, "module thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 5. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create thread 5. This thread simply pends on an event flag which will be set + by thread_0. */ + tx_thread_create(thread_5, "module thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, + 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 6. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ + tx_thread_create(thread_6, "module thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 7. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(thread_7, "module thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the message queue. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_QUEUE_SIZE*sizeof(ULONG), TX_NO_WAIT); + + /* Create the message queue shared by threads 1 and 2. */ + tx_queue_create(queue_0, "module queue 0", TX_1_ULONG, pointer, DEMO_QUEUE_SIZE*sizeof(ULONG)); + + tx_queue_send_notify(queue_0, queue_0_notify); + + /* Create the semaphore used by threads 3 and 4. */ + tx_semaphore_create(semaphore_0, "module semaphore 0", 1); + + tx_semaphore_put_notify(semaphore_0, semaphore_0_notify); + + /* Create the event flags group used by threads 1 and 5. */ + tx_event_flags_create(event_flags_0, "module event flags 0"); + + tx_event_flags_set_notify(event_flags_0, event_0_notify); + + /* Create the mutex used by thread 6 and 7 without priority inheritance. */ + tx_mutex_create(mutex_0, "module mutex 0", TX_NO_INHERIT); + + /* Allocate the memory for a small block pool. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_BLOCK_POOL_SIZE, TX_NO_WAIT); + + /* Create a block memory pool to allocate a message buffer from. */ + tx_block_pool_create(block_pool_0, "module block pool 0", sizeof(ULONG), pointer, DEMO_BLOCK_POOL_SIZE); + + /* Allocate a block and release the block memory. */ + tx_block_allocate(block_pool_0, (VOID **) &pointer, TX_NO_WAIT); + + /* Release the block back to the pool. */ + tx_block_release(pointer); +} + + +/* Define the test threads. */ + +void thread_0_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sits in while-forever-sleep loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_0_counter++; + + /* Sleep for 10 ticks. */ + tx_thread_sleep(10); + + /* Set event flag 0 to wakeup thread 5. */ + status = tx_event_flags_set(event_flags_0, 0x1, TX_OR); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_1_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sends messages to a queue shared by thread 2. */ + while(1) + { + + /* Increment the thread counter. */ + thread_1_counter++; + + /* Send message to queue 0. */ + status = tx_queue_send(queue_0, &thread_1_messages_sent, TX_WAIT_FOREVER); + + /* Check completion status. */ + if (status != TX_SUCCESS) + break; + + /* Increment the message sent. */ + thread_1_messages_sent++; + } +} + + +void thread_2_entry(ULONG thread_input) +{ + +ULONG received_message; +UINT status; + + /* This thread retrieves messages placed on the queue by thread 1. */ + while(1) + { + /* Write value to shared memory region. */ + // *(ULONG *)0x00020000 = 0xCDCDCDCD; + + /* Increment the thread counter. */ + thread_2_counter++; + + /* Retrieve a message from the queue. */ + status = tx_queue_receive(queue_0, &received_message, TX_WAIT_FOREVER); + + /* Check completion status and make sure the message is what we + expected. */ + if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) + break; + + /* Otherwise, all is okay. Increment the received message count. */ + thread_2_messages_received++; + } +} + + +void thread_3_and_4_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 3 and thread 4. As the loop + below shows, these function compete for ownership of semaphore_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 3) + thread_3_counter++; + else + thread_4_counter++; + + /* Get the semaphore with suspension. */ + status = tx_semaphore_get(semaphore_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the semaphore. */ + tx_thread_sleep(2); + + /* Release the semaphore. */ + status = tx_semaphore_put(semaphore_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_5_entry(ULONG thread_input) +{ + +UINT status; +ULONG actual_flags; + + + /* This thread simply waits for an event in a forever loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_5_counter++; + + /* Wait for event flag 0. */ + status = tx_event_flags_get(event_flags_0, 0x1, TX_OR_CLEAR, + &actual_flags, TX_WAIT_FOREVER); + + /* Check status. */ + if ((status != TX_SUCCESS) || (actual_flags != 0x1)) + break; + } +} + + +void thread_6_and_7_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 6 and thread 7. As the loop + below shows, these function compete for ownership of mutex_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 6) + thread_6_counter++; + else + thread_7_counter++; + + /* Get the mutex with suspension. */ + status = tx_mutex_get(mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Get the mutex again with suspension. This shows + that an owning thread may retrieve the mutex it + owns multiple times. */ + status = tx_mutex_get(mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the mutex. */ + tx_thread_sleep(2); + + /* Release the mutex. */ + status = tx_mutex_put(mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Release the mutex again. This will actually + release ownership since it was obtained twice. */ + status = tx_mutex_put(mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + diff --git a/ports_module/rxv2/iar/example_build/sample_threadx_module_manager.c b/ports_module/rxv2/iar/example_build/sample_threadx_module_manager.c new file mode 100644 index 00000000..4afbbe39 --- /dev/null +++ b/ports_module/rxv2/iar/example_build/sample_threadx_module_manager.c @@ -0,0 +1,113 @@ +/* Small demonstration of the ThreadX module manager. */ + +#include "tx_api.h" +#include "txm_module.h" + + +#define DEMO_STACK_SIZE 1024 + +/* Define the ThreadX object control blocks... */ + +TX_THREAD module_manager; +TXM_MODULE_INSTANCE my_module; + + +/* Define the object pool area. */ + +UCHAR object_memory[8192]; + + +/* Define the count of memory faults. */ + +ULONG memory_faults; + + +/* Define thread prototypes. */ + +void module_manager_entry(ULONG thread_input); + + +/* Define fault handler. */ + +VOID module_fault_handler(TX_THREAD *thread, TXM_MODULE_INSTANCE *module) +{ + + /* Just increment the fault counter. */ + memory_faults++; +} + +/* Define main entry point. */ + +int main() +{ + + /* Enter the ThreadX kernel. */ + tx_kernel_enter(); +} + + +/* Define what the initial system looks like. */ + +void tx_application_define(void *first_unused_memory) +{ + +CHAR *pointer = (CHAR*)first_unused_memory; + + + tx_thread_create(&module_manager, "Module Manager Thread", module_manager_entry, 0, + pointer, DEMO_STACK_SIZE, + 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); + pointer = pointer + DEMO_STACK_SIZE; +} + + + + +/* Define the test threads. */ + +void module_manager_entry(ULONG thread_input) +{ + + /* Initialize the module manager. */ + txm_module_manager_initialize((VOID *) 0x00018000, 0x00008000); + + txm_module_manager_object_pool_create(object_memory, sizeof(object_memory)); + + /* Register a fault handler. */ + txm_module_manager_memory_fault_notify(module_fault_handler); + + /* Load the module that is already there, in this example it is placed there by the multiple image download. */ + txm_module_manager_in_place_load(&my_module, "my module", (VOID *) 0xFFF10400); + + + /* Enable 128 byte read/write shared memory region at 0x00020000. */ + txm_module_manager_external_memory_enable(&my_module, (void *) 0x00020000, 128, TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_READ | TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE); + + /* Start the module. */ + txm_module_manager_start(&my_module); + + /* Sleep for a while.... */ + tx_thread_sleep(1000); + + /* Stop the module. */ + txm_module_manager_stop(&my_module); + + /* Unload the module. */ + txm_module_manager_unload(&my_module); + + /* Load the module that is already there. */ + txm_module_manager_in_place_load(&my_module, "my module", (VOID *) 0xFFF10400); + + /* Set maximum module priority to 5. */ + txm_module_manager_maximum_module_priority_set(&my_module, 5); + + /* Start the module again. */ + txm_module_manager_start(&my_module); + + /* Now just spin... */ + while(1) + { + + tx_thread_sleep(100); + } +} diff --git a/ports_module/rxv2/iar/example_build/tx_initialize_low_level.s b/ports_module/rxv2/iar/example_build/tx_initialize_low_level.s new file mode 100644 index 00000000..d04b99b5 --- /dev/null +++ b/ports_module/rxv2/iar/example_build/tx_initialize_low_level.s @@ -0,0 +1,99 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Initialize */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; + + extern __tx_initialize_unused_memory + + section .text:CODE:ROOT + +; +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_initialize_low_level RXv2/IAR */ +;/* 6.x */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is responsible for any low-level processor */ +;/* initialization, including setting up interrupt vectors, setting */ +;/* up a periodic timer interrupt source, saving the system stack */ +;/* pointer for use in ISR processing later, and finding the first */ +;/* available RAM memory address for tx_application_define. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_initialize_kernel_enter ThreadX entry function */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* xx-xx-xxxx William E. Lamie Initial Version 6.x */ +;/* */ +;/**************************************************************************/ + public __tx_initialize_low_level + +__tx_initialize_low_level: + +; /* Save the first available memory address. */ +; _tx_initialize_unused_memory = (VOID_PTR) &free_mem_start; +; + MOV.L #__tx_free_memory_start, R1 ; Pickup unused memory address + MOV.L #__tx_initialize_unused_memory,R2 + MOV.L R1,[R2] ; Save first free memory address + +; /* Set priority of SWINT to 1. */ + MOV.L #0x87303, r1 + MOV.L #1, r2 + MOV.B r2, [r1] + +; /* Enable SWINT. */ + MOV.L #0x87203, r1 + MOV.B [r1], r2 + OR #(1 << 3), r2 + MOV.B r2, [r1] + + RTS + + section FREEMEM:DATA + public __tx_free_memory_start +__tx_free_memory_start + DS32 4 + + END diff --git a/ports_module/rxv2/iar/example_build/txm_module_preamble.s b/ports_module/rxv2/iar/example_build/txm_module_preamble.s new file mode 100644 index 00000000..bf5bb9fb --- /dev/null +++ b/ports_module/rxv2/iar/example_build/txm_module_preamble.s @@ -0,0 +1,69 @@ + /* Alignment of 4 (16-byte) */ + SECTION .text:CODE (4) + + + /* Define public symbols. */ + + PUBLIC __txm_module_preamble + + + /* Define application-specific start/stop entry points for the module. */ + + EXTERN _demo_module_start + + + /* Define common external refrences. */ + + EXTERN __txm_module_thread_shell_entry + EXTERN __txm_module_callback_request_thread_entry + EXTERN ROPI$$Length + EXTERN RWPI$$Length + + DATA +__txm_module_preamble: + DC32 0x4D4F4455 // Module ID + DC32 0x5 // Module Major Version + DC32 0x6 // Module Minor Version + DC32 32 // Module Preamble Size in 32-bit words + DC32 0x12345678 // Module ID (application defined) + DC32 0x00000007 // Module Properties where: + // Bits 31-24: Compiler ID + // 0 -> IAR + // 1 -> RVDS + // 2 -> GNU + // Bit 0: 0 -> Privileged mode execution + // 1 -> User mode execution + // Bit 1: 0 -> No MPU protection + // 1 -> MPU protection (must have user mode selected) + // Bit 2: 0 -> Disable shared/external memory access + // 1 -> Enable shared/external memory access + DC32 __txm_module_thread_shell_entry - $ // Module Shell Entry Point + DC32 _demo_module_start - $ // Module Start Thread Entry Point + DC32 0 // Module Stop Thread Entry Point + DC32 1 // Module Start/Stop Thread Priority + DC32 1024 // Module Start/Stop Thread Stack Size + DC32 __txm_module_callback_request_thread_entry - $ // Module Callback Thread Entry + DC32 1 // Module Callback Thread Priority + DC32 1024 // Module Callback Thread Stack Size + DC32 ROPI$$Length // Module Code Size + DC32 RWPI$$Length // Module Data Size + DC32 0 // Reserved 0 + DC32 0 // Reserved 1 + DC32 0 // Reserved 2 + DC32 0 // Reserved 3 + DC32 0 // Reserved 4 + DC32 0 // Reserved 5 + DC32 0 // Reserved 6 + DC32 0 // Reserved 7 + DC32 0 // Reserved 8 + DC32 0 // Reserved 9 + DC32 0 // Reserved 10 + DC32 0 // Reserved 11 + DC32 0 // Reserved 12 + DC32 0 // Reserved 13 + DC32 0 // Reserved 14 + DC32 0 // Reserved 15 + + END + + diff --git a/ports_module/rxv2/iar/inc/tx_port.h b/ports_module/rxv2/iar/inc/tx_port.h new file mode 100644 index 00000000..c99acaea --- /dev/null +++ b/ports_module/rxv2/iar/inc/tx_port.h @@ -0,0 +1,292 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Port Specific */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* PORT SPECIFIC C INFORMATION RELEASE */ +/* */ +/* tx_port.h RXv2/IAR */ +/* 6.x */ +/* */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file contains data type definitions that make the ThreadX */ +/* real-time kernel function identically on a variety of different */ +/* processor architectures. For example, the size or number of bits */ +/* in an "int" data type vary between microprocessor architectures and */ +/* even C compilers for the same microprocessor. ThreadX does not */ +/* directly use native C data types. Instead, ThreadX creates its */ +/* own special types that can be mapped to actual data types by this */ +/* file to guarantee consistency in the interface and functionality. */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* xx-xx-xxxx William E. Lamie Initial Version 6.x */ +/* */ +/**************************************************************************/ + +#ifndef TX_PORT_H +#define TX_PORT_H + +#include <string.h> +#include <intrinsics.h> + +/* Determine if the optional ThreadX user define file should be used. */ + +#ifdef TX_INCLUDE_USER_DEFINE_FILE + + +/* Yes, include the user defines in tx_user.h. The defines in this file may + alternately be defined on the command line. */ + +#include "tx_user.h" +#endif + +/* Define ThreadX basic types for this port. */ + +#define VOID void +typedef char CHAR; +typedef unsigned char UCHAR; +typedef int INT; +typedef unsigned int UINT; +typedef long LONG; +typedef unsigned long ULONG; +typedef short SHORT; +typedef unsigned short USHORT; + + +/* Define the priority levels for ThreadX. Legal values range + from 32 to 1024 and MUST be evenly divisible by 32. */ + +#ifndef TX_MAX_PRIORITIES +#define TX_MAX_PRIORITIES 32 +#endif + + +/* Define the minimum stack for a ThreadX thread on this processor. If the size supplied during + thread creation is less than this value, the thread create call will return an error. */ + +#ifndef TX_MINIMUM_STACK +#define TX_MINIMUM_STACK 256 /* Minimum stack size for this port */ +#endif + + +/* Define the system timer thread's default stack size and priority. These are only applicable + if TX_TIMER_PROCESS_IN_ISR is not defined. */ + +#ifndef TX_TIMER_THREAD_STACK_SIZE +#define TX_TIMER_THREAD_STACK_SIZE 1024 /* Default timer thread stack size */ +#endif + +#ifndef TX_TIMER_THREAD_PRIORITY +#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ +#endif + + +#ifndef TX_TRACE_TIME_SOURCE +#define TX_TRACE_TIME_SOURCE ++_tx_trace_simulated_time +#endif +#ifndef TX_TRACE_TIME_MASK +#define TX_TRACE_TIME_MASK 0xFFFFFFFFUL +#endif + + +/* Define the port specific options for the _tx_build_options variable. This variable indicates + how the ThreadX library was built. */ + +#define TX_PORT_SPECIFIC_BUILD_OPTIONS 0 + + +/* Define the in-line initialization constant so that modules with in-line + initialization capabilities can prevent their initialization from being + a function call. */ + +#define TX_INLINE_INITIALIZATION + + +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is + disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack + checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING + define is negated, thereby forcing the stack fill which is necessary for the stack checking + logic. */ + +#ifdef TX_ENABLE_STACK_CHECKING +#undef TX_DISABLE_STACK_FILLING +#endif + + +/* Define the TX_THREAD control block extensions for this port. The main reason + for the multiple macros is so that backward compatibility can be maintained with + existing ThreadX kernel awareness modules. */ + +#define TX_THREAD_EXTENSION_0 +#define TX_THREAD_EXTENSION_1 +#define TX_THREAD_EXTENSION_2 VOID *tx_thread_module_instance_ptr; \ + VOID *tx_thread_module_entry_info_ptr; \ + ULONG tx_thread_module_current_user_mode; \ + ULONG tx_thread_module_user_mode; \ + VOID *tx_thread_module_kernel_stack_start; \ + VOID *tx_thread_module_kernel_stack_end; \ + ULONG tx_thread_module_kernel_stack_size; \ + VOID *tx_thread_module_stack_ptr; \ + VOID *tx_thread_module_stack_start; \ + VOID *tx_thread_module_stack_end; \ + ULONG tx_thread_module_stack_size; \ + VOID *tx_thread_module_reserved; \ + VOID *tx_thread_iar_tls_pointer; +#define TX_THREAD_EXTENSION_3 + + +/* Define the port extensions of the remaining ThreadX objects. */ + +#define TX_BLOCK_POOL_EXTENSION +#define TX_BYTE_POOL_EXTENSION +#define TX_MUTEX_EXTENSION +#define TX_EVENT_FLAGS_GROUP_EXTENSION VOID *tx_event_flags_group_module_instance; \ + VOID (*tx_event_flags_group_set_module_notify)(struct TX_EVENT_FLAGS_GROUP_STRUCT *group_ptr); + +#define TX_QUEUE_EXTENSION VOID *tx_queue_module_instance; \ + VOID (*tx_queue_send_module_notify)(struct TX_QUEUE_STRUCT *queue_ptr); + +#define TX_SEMAPHORE_EXTENSION VOID *tx_semaphore_module_instance; \ + VOID (*tx_semaphore_put_module_notify)(struct TX_SEMAPHORE_STRUCT *semaphore_ptr); + +#define TX_TIMER_EXTENSION VOID *tx_timer_module_instance; \ + VOID (*tx_timer_module_expiration_function)(ULONG id); + + +/* Define the user extension field of the thread control block. Nothing + additional is needed for this port so it is defined as white space. */ + +#ifndef TX_THREAD_USER_EXTENSION +#define TX_THREAD_USER_EXTENSION +#endif + + +/* Define the macros for processing extensions in tx_thread_create, tx_thread_delete, + tx_thread_shell_entry, and tx_thread_terminate. */ + + +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) +#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) + + +/* Define the ThreadX object creation extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_CREATE_EXTENSION(group_ptr) +#define TX_MUTEX_CREATE_EXTENSION(mutex_ptr) +#define TX_QUEUE_CREATE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_CREATE_EXTENSION(semaphore_ptr) +#define TX_TIMER_CREATE_EXTENSION(timer_ptr) + + +/* Define the ThreadX object deletion extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_DELETE_EXTENSION(group_ptr) +#define TX_MUTEX_DELETE_EXTENSION(mutex_ptr) +#define TX_QUEUE_DELETE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_DELETE_EXTENSION(semaphore_ptr) +#define TX_TIMER_DELETE_EXTENSION(timer_ptr) + +/* Define ThreadX interrupt lockout and restore macros for protection on + access of critical kernel information. The restore interrupt macro must + restore the interrupt posture of the running thread prior to the value + present prior to the disable macro. In most cases, the save area macro + is used to define a local function save area for the disable and restore + macros. */ + +#ifdef TX_DISABLE_INLINE + +UINT _tx_thread_interrupt_disable(VOID); +VOID _tx_thread_interrupt_restore(UINT previous_posture); + +#define TX_INTERRUPT_SAVE_AREA register UINT interrupt_save; + +#define TX_DISABLE interrupt_save = _tx_thread_interrupt_disable(); + +#define TX_RESTORE _tx_thread_interrupt_restore(interrupt_save); + +#else + +#define TX_INTERRUPT_SAVE_AREA __istate_t interrupt_save; +#define TX_DISABLE {interrupt_save = __get_interrupt_state();__disable_interrupt();}; +#define TX_RESTORE {__set_interrupt_state(interrupt_save);}; + +#define _tx_thread_system_return _tx_thread_system_return_inline + +static void _tx_thread_system_return_inline(void) +{ + TX_INTERRUPT_SAVE_AREA + + TX_DISABLE + + *((volatile UCHAR *)(0x872E0u)) = 1u; + + TX_RESTORE +} + +#endif + + +#ifndef TX_THREAD_GET_SYSTEM_STATE + +extern volatile ULONG _tx_thread_system_state; +#define TX_THREAD_GET_SYSTEM_STATE() (_tx_thread_system_state | ((~__get_PSW_register()) & (1u << 17u))) +#endif + + + +/* Define the interrupt lockout macros for each ThreadX object. */ + +#define TX_BLOCK_POOL_DISABLE TX_DISABLE +#define TX_BYTE_POOL_DISABLE TX_DISABLE +#define TX_EVENT_FLAGS_GROUP_DISABLE TX_DISABLE +#define TX_MUTEX_DISABLE TX_DISABLE +#define TX_QUEUE_DISABLE TX_DISABLE +#define TX_SEMAPHORE_DISABLE TX_DISABLE + + +/* Define the version ID of ThreadX. This may be utilized by the application. */ + +#ifdef TX_THREAD_INIT +CHAR _tx_version_id[] = + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX RXv2/IAR Version 6.x *"; +#else +extern CHAR _tx_version_id[]; +#endif + + +#endif + diff --git a/ports_module/rxv2/iar/inc/txm_module_port.h b/ports_module/rxv2/iar/inc/txm_module_port.h new file mode 100644 index 00000000..56c8c192 --- /dev/null +++ b/ports_module/rxv2/iar/inc/txm_module_port.h @@ -0,0 +1,401 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* APPLICATION INTERFACE DEFINITION RELEASE */ +/* */ +/* txm_module_port.h RXv2/IAR */ +/* 6.x */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file defines the basic module constants, interface structures, */ +/* and function prototypes. */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* xx-xx-xxxx Scott Larson Initial Version 6.x */ +/* */ +/**************************************************************************/ + +#ifndef TXM_MODULE_PORT_H +#define TXM_MODULE_PORT_H + +/* Determine if the optional Modules user define file should be used. */ + +#ifdef TXM_MODULE_INCLUDE_USER_DEFINE_FILE + + +/* Yes, include the user defines in txm_module_user.h. The defines in this file may + alternately be defined on the command line. */ + +#include "txm_module_user.h" +#endif + +/* It is assumed that the base ThreadX tx_port.h file has been modified to add the + following extensions to the ThreadX thread control block (this code should replace + the corresponding macro define in tx_port.h): + +#define TX_THREAD_EXTENSION_2 VOID *tx_thread_module_instance_ptr; \ + VOID *tx_thread_module_entry_info_ptr; \ + ULONG tx_thread_module_current_user_mode; \ + ULONG tx_thread_module_user_mode; \ + VOID *tx_thread_module_kernel_stack_start; \ + VOID *tx_thread_module_kernel_stack_end; \ + ULONG tx_thread_module_kernel_stack_size; \ + VOID *tx_thread_module_stack_ptr; \ + VOID *tx_thread_module_stack_start; \ + VOID *tx_thread_module_stack_end; \ + ULONG tx_thread_module_stack_size; \ + VOID *tx_thread_module_reserved; \ + VOID *tx_thread_iar_tls_pointer; + +The following extensions must also be defined in tx_port.h: + +#define TX_EVENT_FLAGS_GROUP_EXTENSION VOID *tx_event_flags_group_module_instance; \ + VOID (*tx_event_flags_group_set_module_notify)(struct TX_EVENT_FLAGS_GROUP_STRUCT *group_ptr); + +#define TX_QUEUE_EXTENSION VOID *tx_queue_module_instance; \ + VOID (*tx_queue_send_module_notify)(struct TX_QUEUE_STRUCT *queue_ptr); + +#define TX_SEMAPHORE_EXTENSION VOID *tx_semaphore_module_instance; \ + VOID (*tx_semaphore_put_module_notify)(struct TX_SEMAPHORE_STRUCT *semaphore_ptr); + +#define TX_TIMER_EXTENSION VOID *tx_timer_module_instance; \ + VOID (*tx_timer_module_expiration_function)(ULONG id); +*/ + +#define TXM_MODULE_THREAD_ENTRY_INFO_USER_EXTENSION + +/* Define constants specific to the tools the module can be built with for this particular modules port. */ + +#define TXM_MODULE_IAR_COMPILER 0x00000000 +#define TXM_MODULE_RVDS_COMPILER 0x01000000 +#define TXM_MODULE_GNU_COMPILER 0x02000000 +#define TXM_MODULE_COMPILER_MASK 0xFF000000 +#define TXM_MODULE_OPTIONS_MASK 0x000000FF + + +/* Define the properties for this particular module port. */ + +#define TXM_MODULE_MEMORY_PROTECTION_ENABLED +#ifdef TXM_MODULE_MEMORY_PROTECTION_ENABLED +#define TXM_MODULE_REQUIRE_ALLOCATED_OBJECT_MEMORY +#else +#define TXM_MODULE_REQUIRE_LOCAL_OBJECT_MEMORY +#endif + +#define TXM_MODULE_USER_MODE 0x00000001 +#define TXM_MODULE_MEMORY_PROTECTION 0x00000002 +#define TXM_MODULE_SHARED_EXTERNAL_MEMORY_ACCESS 0x00000004 + +/* Define the kernel stack size for a module thread. */ +#ifndef TXM_MODULE_KERNEL_STACK_SIZE +#define TXM_MODULE_KERNEL_STACK_SIZE 512 +#endif + + +/* Define the supported options for this module. */ + +#define TXM_MODULE_MANAGER_SUPPORTED_OPTIONS (TXM_MODULE_USER_MODE | TXM_MODULE_MEMORY_PROTECTION | TXM_MODULE_SHARED_EXTERNAL_MEMORY_ACCESS) +#define TXM_MODULE_MANAGER_REQUIRED_OPTIONS 0 + + +/* Define offset adjustments according to the compiler used to build the module. */ + +#define TXM_MODULE_IAR_SHELL_ADJUST 24 +#define TXM_MODULE_IAR_START_ADJUST 28 +#define TXM_MODULE_IAR_STOP_ADJUST 32 +#define TXM_MODULE_IAR_CALLBACK_ADJUST 44 + +#define TXM_MODULE_RVDS_SHELL_ADJUST 0 +#define TXM_MODULE_RVDS_START_ADJUST 0 +#define TXM_MODULE_RVDS_STOP_ADJUST 0 +#define TXM_MODULE_RVDS_CALLBACK_ADJUST 0 + +#define TXM_MODULE_GNU_SHELL_ADJUST 24 +#define TXM_MODULE_GNU_START_ADJUST 28 +#define TXM_MODULE_GNU_STOP_ADJUST 32 +#define TXM_MODULE_GNU_CALLBACK_ADJUST 44 + + +/* Define other module port-specific constants. */ + +/* Define INLINE_DECLARE to inline for IAR compiler. */ + +#define INLINE_DECLARE inline + +/* Define the data area alignment mask, must be a power of 2. */ + +#ifndef TXM_MODULE_DATA_ALIGNMENT +#define TXM_MODULE_DATA_ALIGNMENT 16 +#endif + + +/* Define the code area alignment mask, must be a power of 2. */ + +#ifndef TXM_MODULE_CODE_ALIGNMENT +#define TXM_MODULE_CODE_ALIGNMENT 16 +#endif + + +/* Define the number of MPU entries assigned to the code and data sections. */ + +#define TXM_MODULE_MANAGER_CODE_MPU_ENTRIES 2 +#define TXM_MODULE_MANAGER_DATA_MPU_ENTRIES 1 + +/* Total MPU entries available. */ +#define TXM_MODULE_MANAGER_RX_MPU_ENTRIES 8 +#define TXM_MODULE_MANAGER_REGISTERS_PER_MPU_ENTRY 2 +#define TXM_MODULE_MANAGER_MPU_TABLE_SIZE (TXM_MODULE_MANAGER_RX_MPU_ENTRIES * TXM_MODULE_MANAGER_REGISTERS_PER_MPU_ENTRY) + +/* Shared memory MPU index. */ +#define TXM_MODULE_MANAGER_SHARED_MPU_INDEX 6 + +/* Addresses of MPU registers for trampoline protection. */ +#define RSPAGE0 (*(ULONG *) 0x00086400) +#define REPAGE0 (*(ULONG *) 0x00086404) + +/* Shared memory region attributes. */ +#define TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_EXECUTE 1 +#define TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE 2 +#define TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_READ 4 + +#define TXM_MODULE_MANAGER_ATTRIBUTE_EXECUTE_MPU_BIT (TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_EXECUTE << 1) +#define TXM_MODULE_MANAGER_ATTRIBUTE_WRITE_MPU_BIT (TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE << 1) +#define TXM_MODULE_MANAGER_ATTRIBUTE_READ_MPU_BIT (TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_READ << 1) + +/* Define the port-extensions to the module manager instance structure. */ + +#define TXM_MODULE_MANAGER_PORT_EXTENSION \ + ULONG txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_MPU_TABLE_SIZE]; \ + ULONG txm_module_instance_shared_memory_address; \ + ULONG txm_module_instance_shared_memory_length; + + +/* Define the memory fault information structure that is populated when a memory fault occurs. */ + + +typedef struct TXM_MODULE_MANAGER_MEMORY_FAULT_INFO_STRUCT +{ + TX_THREAD *txm_module_manager_memory_fault_info_thread_ptr; + VOID *txm_module_manager_memory_fault_info_code_location; + ULONG txm_module_manager_memory_fault_info_mpests; + ULONG txm_module_manager_memory_fault_info_mpdea; + ULONG txm_module_manager_memory_fault_info_mhiti; + ULONG txm_module_manager_memory_fault_info_mhitd; + ULONG txm_module_manager_memory_fault_info_psw; + ULONG txm_module_manager_memory_fault_info_sp; + ULONG txm_module_manager_memory_fault_info_r1; + ULONG txm_module_manager_memory_fault_info_r2; + ULONG txm_module_manager_memory_fault_info_r3; + ULONG txm_module_manager_memory_fault_info_r4; + ULONG txm_module_manager_memory_fault_info_r5; + ULONG txm_module_manager_memory_fault_info_r6; + ULONG txm_module_manager_memory_fault_info_r7; + ULONG txm_module_manager_memory_fault_info_r8; + ULONG txm_module_manager_memory_fault_info_r9; + ULONG txm_module_manager_memory_fault_info_r10; + ULONG txm_module_manager_memory_fault_info_r11; + ULONG txm_module_manager_memory_fault_info_r12; + ULONG txm_module_manager_memory_fault_info_r13; + ULONG txm_module_manager_memory_fault_info_r14; + ULONG txm_module_manager_memory_fault_info_r15; +} TXM_MODULE_MANAGER_MEMORY_FAULT_INFO; + + +#define TXM_MODULE_MANAGER_FAULT_INFO \ + TXM_MODULE_MANAGER_MEMORY_FAULT_INFO _txm_module_manager_memory_fault_info; + +/* Define the macro to check the stack available in dispatch. */ +//#define TXM_MODULE_MANAGER_CHECK_STACK_AVAILABLE \ +// ULONG stack_available; \ +// __asm("MOV SP, %0" : "=r"(stack_available)); \ +// stack_available -= (ULONG)_tx_thread_current_ptr->tx_thread_stack_start; \ +// if((stack_available < TXM_MODULE_MINIMUM_STACK_AVAILABLE) || \ +// (stack_available > _tx_thread_current_ptr->tx_thread_stack_size)) \ +// { \ +// return(TX_SIZE_ERROR); \ +// } + +/* Define the macro to check the module version ID. */ + +#define TXM_MODULE_MANAGER_CHECK_PROPERTIES(properties) \ + if ((properties & _txm_module_manager_properties_supported) != (properties & ~((ULONG) TXM_MODULE_COMPILER_MASK))) \ + { \ + _tx_mutex_put(&_txm_module_manager_mutex); \ + return(TXM_MODULE_INVALID_PROPERTIES); \ + } \ + if ((_txm_module_manager_properties_required & properties) != _txm_module_manager_properties_required) \ + { \ + _tx_mutex_put(&_txm_module_manager_mutex); \ + return(TXM_MODULE_INVALID_PROPERTIES); \ + } + + +/* Define the macro to check the code alignment. */ + +#define TXM_MODULE_MANAGER_CHECK_CODE_ALIGNMENT(module_location, code_alignment) \ + { \ + ULONG temp; \ + temp = (ULONG) module_location; \ + temp = temp & (code_alignment - 1); \ + if (temp) \ + { \ + _tx_mutex_put(&_txm_module_manager_mutex); \ + return(TXM_MODULE_ALIGNMENT_ERROR); \ + } \ + } + + +/* Define the macro to adjust the alignment and size for code/data areas. */ + +#define TXM_MODULE_MANAGER_ALIGNMENT_ADJUST(module_preamble, code_size, code_alignment, data_size, data_alignment) _txm_module_manager_alignment_adjust(module_preamble, &code_size, &code_alignment, &data_size, &data_alignment); + + +/* Define the macro to adjust the symbols in the module preamble. */ + +#define TXM_MODULE_MANAGER_CALCULATE_ADJUSTMENTS(properties, shell_function_adjust, start_function_adjust, stop_function_adjust, callback_function_adjust) \ + if ((properties & TXM_MODULE_COMPILER_MASK) == TXM_MODULE_IAR_COMPILER) \ + { \ + shell_function_adjust = TXM_MODULE_IAR_SHELL_ADJUST; \ + start_function_adjust = TXM_MODULE_IAR_START_ADJUST - (ULONG)(module_instance -> txm_module_instance_code_start); \ + stop_function_adjust = TXM_MODULE_IAR_STOP_ADJUST - (ULONG)(module_instance -> txm_module_instance_code_start); \ + callback_function_adjust = TXM_MODULE_IAR_CALLBACK_ADJUST - (ULONG)(module_instance -> txm_module_instance_code_start); \ + } \ + else if ((properties & TXM_MODULE_COMPILER_MASK) == TXM_MODULE_RVDS_COMPILER) \ + { \ + shell_function_adjust = TXM_MODULE_RVDS_SHELL_ADJUST; \ + start_function_adjust = TXM_MODULE_RVDS_START_ADJUST; \ + stop_function_adjust = TXM_MODULE_RVDS_STOP_ADJUST; \ + callback_function_adjust = TXM_MODULE_RVDS_CALLBACK_ADJUST; \ + } \ + else \ + { \ + shell_function_adjust = TXM_MODULE_GNU_SHELL_ADJUST; \ + start_function_adjust = TXM_MODULE_GNU_START_ADJUST; \ + stop_function_adjust = TXM_MODULE_GNU_STOP_ADJUST; \ + callback_function_adjust = TXM_MODULE_GNU_CALLBACK_ADJUST; \ + } + + +/* Define the macro to populate the thread control block with module port-specific information. + Check if the module is in user mode and set up txm_module_thread_entry_info_kernel_call_dispatcher accordingly. +*/ +#define TXM_MODULE_MANAGER_THREAD_SETUP(thread_ptr, module_instance) \ + thread_ptr -> tx_thread_module_current_user_mode = module_instance -> txm_module_instance_property_flags & TXM_MODULE_USER_MODE; \ + thread_ptr -> tx_thread_module_user_mode = module_instance -> txm_module_instance_property_flags & TXM_MODULE_USER_MODE; \ + if (thread_ptr -> tx_thread_module_user_mode) \ + { \ + *(ULONG*)&(thread_entry_info -> txm_module_thread_entry_info_kernel_call_dispatcher) = \ + (ULONG)_txm_module_manager_user_mode_entry - (ULONG)module_instance -> txm_module_instance_code_start; \ + } \ + else \ + { \ + *(ULONG*)&(thread_entry_info -> txm_module_thread_entry_info_kernel_call_dispatcher) = \ + (ULONG)_txm_module_manager_kernel_dispatch - (ULONG)module_instance -> txm_module_instance_code_start; \ + } + +/* Define the macro to populate the module control block with module port-specific information. + If memory protection is enabled, set up the MPU registers. +*/ +#define TXM_MODULE_MANAGER_MODULE_SETUP(module_instance) \ + if (module_instance -> txm_module_instance_property_flags & TXM_MODULE_USER_MODE) \ + { \ + if (module_instance -> txm_module_instance_property_flags & TXM_MODULE_MEMORY_PROTECTION) \ + { \ + _txm_module_manager_setup_mpu_registers(module_instance); \ + } \ + } \ + else \ + { \ + /* Do nothing. */ \ + } + +/* Define the macro to perform port-specific functions when unloading the module. */ +/* Nothing needs to be done for this port. */ +#define TXM_MODULE_MANAGER_MODULE_UNLOAD(module_instance) + + +/* Define the macro to perform port-specific functions when passing pointer to kernel. */ +/* Determine if the pointer is within the module's data or shared memory. */ +//#define TXM_MODULE_MANAGER_CHECK_DATA_POINTER(module_instance, pointer) \ +// if ((pointer < (ULONG) module_instance -> txm_module_instance_data_start) || \ +// ((pointer+sizeof(pointer)) > (ULONG) module_instance -> txm_module_instance_data_end)) \ +// { \ +// if((pointer < module_instance -> txm_module_instance_shared_memory_address) || \ +// ((pointer+sizeof(pointer)) > module_instance -> txm_module_instance_shared_memory_address \ +// + module_instance -> txm_module_instance_shared_memory_length)) \ +// { \ +// return(TXM_MODULE_INVALID_MEMORY); \ +// } \ +// } + +/* Define the macro to perform port-specific functions when passing function pointer to kernel. */ +/* Determine if the pointer is within the module's code memory. */ +//#define TXM_MODULE_MANAGER_CHECK_FUNCTION_POINTER(module_instance, pointer) \ +// if (((pointer < sizeof(TXM_MODULE_PREAMBLE)) || \ +// ((pointer+sizeof(pointer)) > ((ULONG) module_instance -> txm_module_instance_code_end - \ +// (ULONG) module_instance -> txm_module_instance_code_start))) \ +// && (pointer != (ULONG) TX_NULL)) \ +// { \ +// return(TX_PTR_ERROR); \ +// } + +/* Define macro to make sure object is inside the module's data. */ +#define TXM_MODULE_MANAGER_CHECK_INSIDE_DATA(module_instance, obj_ptr, obj_size) \ + /* Check for overflow. */ \ + (((obj_ptr) < ((obj_ptr) + (obj_size))) && \ + /* Check if it's inside module data. */ \ + ((((obj_ptr) >= (ALIGN_TYPE) module_instance -> txm_module_instance_data_start) && \ + (((obj_ptr) + (obj_size)) <= ((ALIGN_TYPE) module_instance -> txm_module_instance_data_end + 1))) || \ + /* Check if it's inside shared memory. */ \ + (((obj_ptr) >= (ALIGN_TYPE) module_instance -> txm_module_instance_shared_memory_address) && \ + (((obj_ptr) + (obj_size)) <= (ALIGN_TYPE) (module_instance -> txm_module_instance_shared_memory_address + module_instance -> txm_module_instance_shared_memory_length))))) + + +/* Define some internal prototypes to this module port. */ + +#ifndef TX_SOURCE_CODE +#define txm_module_manager_memory_fault_notify _txm_module_manager_memory_fault_notify +#endif + + +#define TXM_MODULE_MANAGER_ADDITIONAL_PROTOTYPES \ +VOID _txm_module_manager_alignment_adjust(TXM_MODULE_PREAMBLE *module_preamble, ULONG *code_size, ULONG *code_alignment, ULONG *data_size, ULONG *data_alignment); \ +VOID _txm_module_manager_memory_fault_handler(VOID); \ +UINT _txm_module_manager_memory_fault_notify(VOID (*notify_function)(TX_THREAD *, TXM_MODULE_INSTANCE *)); \ +VOID _txm_module_manager_setup_mpu_registers(TXM_MODULE_INSTANCE *module_instance); + + +#define TXM_MODULE_MANAGER_VERSION_ID \ +CHAR _txm_module_manager_version_id[] = \ + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module RXv2/IAR Version 6.x *"; + +#endif diff --git a/ports_module/rxv2/iar/module_lib/src/txm_module_thread_shell_entry.c b/ports_module/rxv2/iar/module_lib/src/txm_module_thread_shell_entry.c new file mode 100644 index 00000000..b6506ba2 --- /dev/null +++ b/ports_module/rxv2/iar/module_lib/src/txm_module_thread_shell_entry.c @@ -0,0 +1,173 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#ifndef TXM_MODULE +#define TXM_MODULE +#endif + +#ifndef TX_SOURCE_CODE +#define TX_SOURCE_CODE +#endif + + +/* Include necessary system files. */ + +#include "txm_module.h" +#include "tx_thread.h" + +/* Define the global module entry pointer from the start thread of the module. */ + +TXM_MODULE_THREAD_ENTRY_INFO *_txm_module_entry_info; + + +/* Define the dispatch function pointer used in the module implementation. */ + +ULONG (*_txm_module_kernel_call_dispatcher)(ULONG kernel_request, ULONG param_1, ULONG param_2, ULONG param3); + + +/* Define the IAR startup code that clears the uninitialized global data and sets up the + preset global variables. */ + +extern VOID __iar_data_init2(VOID); + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_thread_shell_entry RXv2/IAR */ +/* 6.1.9 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function calls the specified entry function of the thread. It */ +/* also provides a place for the thread's entry function to return. */ +/* If the thread returns, this function places the thread in a */ +/* "COMPLETED" state. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Pointer to current thread */ +/* thread_info Pointer to thread entry info */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* __iar_data_init2 IAR global initialization function*/ +/* thread_entry Thread's entry function */ +/* tx_thread_resume Resume the module callback thread */ +/* _txm_module_thread_system_suspend Module thread suspension routine */ +/* */ +/* CALLED BY */ +/* */ +/* Initial thread stack frame */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ +/* */ +/**************************************************************************/ +VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_ENTRY_INFO *thread_info) +{ + +#ifndef TX_DISABLE_NOTIFY_CALLBACKS + VOID (*entry_exit_notify)(TX_THREAD *, UINT); +#endif + + + /* Determine if this is the start thread. If so, we must prepare the module for + execution. If not, simply skip the C startup code. */ + if (thread_info -> txm_module_thread_entry_info_start_thread) + { + /* Initialize the IAR C environment. */ + __iar_data_init2(); + + /* Save the entry info pointer, for later use. */ + _txm_module_entry_info = thread_info; + + /* Save the kernel function dispatch address. This is used to make all resident calls from + the module. */ + _txm_module_kernel_call_dispatcher = thread_info -> txm_module_thread_entry_info_kernel_call_dispatcher; + + /* Ensure that we have a valid pointer. */ + while (!_txm_module_kernel_call_dispatcher) + { + /* Loop here, if an error is present getting the dispatch function pointer! + An error here typically indicates the resident portion of _tx_thread_schedule + is not supporting the trap to obtain the function pointer. */ + } + + /* Resume the module's callback thread, already created in the manager. */ + _txe_thread_resume(thread_info -> txm_module_thread_entry_info_callback_request_thread); + } + +#ifndef TX_DISABLE_NOTIFY_CALLBACKS + + /* Pickup the entry/exit application callback routine. */ + entry_exit_notify = thread_info -> txm_module_thread_entry_info_exit_notify; + + /* Determine if an application callback routine is specified. */ + if (entry_exit_notify != TX_NULL) + { + + /* Yes, notify application that this thread has been entered! */ + (entry_exit_notify)(thread_ptr, TX_THREAD_ENTRY); + } +#endif + + /* Call current thread's entry function. */ + (thread_info -> txm_module_thread_entry_info_entry) (thread_info -> txm_module_thread_entry_info_parameter); + + /* Suspend thread with a "completed" state. */ + + +#ifndef TX_DISABLE_NOTIFY_CALLBACKS + + /* Pickup the entry/exit application callback routine again. */ + entry_exit_notify = thread_info -> txm_module_thread_entry_info_exit_notify; + + /* Determine if an application callback routine is specified. */ + if (entry_exit_notify != TX_NULL) + { + + /* Yes, notify application that this thread has exited! */ + (entry_exit_notify)(thread_ptr, TX_THREAD_EXIT); + } +#endif + + /* Call actual thread suspension routine. */ + _txm_module_thread_system_suspend(thread_ptr); + +#ifdef TX_SAFETY_CRITICAL + + /* If we ever get here, raise safety critical exception. */ + TX_SAFETY_CRITICAL_EXCEPTION(__FILE__, __LINE__, 0); +#endif +} diff --git a/ports_module/rxv2/iar/module_manager/src/tx_initialize_low_level.s b/ports_module/rxv2/iar/module_manager/src/tx_initialize_low_level.s new file mode 100644 index 00000000..612fae3a --- /dev/null +++ b/ports_module/rxv2/iar/module_manager/src/tx_initialize_low_level.s @@ -0,0 +1,101 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Initialize */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + extern __tx_initialize_unused_memory + + section .text:CODE:ROOT + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_initialize_low_level RXv2/IAR */ +/* 6.x */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is responsible for any low-level processor */ +/* initialization, including setting up interrupt vectors, setting */ +/* up a periodic timer interrupt source, saving the system stack */ +/* pointer for use in ISR processing later, and finding the first */ +/* available RAM memory address for tx_application_define. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_initialize_kernel_enter ThreadX entry function */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* xx-xx-xxxx William E. Lamie Initial Version 6.x */ +/* */ +/**************************************************************************/ + public __tx_initialize_low_level + +__tx_initialize_low_level: + + /* Save the first available memory address. */ + // _tx_initialize_unused_memory = (VOID_PTR) &free_mem_start; + + MOV.L #__tx_free_memory_start, R1 // Pick up unused memory address + MOV.L #__tx_initialize_unused_memory,R2 + MOV.L R1,[R2] // Save first free memory address + + /* Set priority of SWINT to 1. */ + MOV.L #0x87303, r1 + MOV.L #1, r2 + MOV.B r2, [r1] + + /* Enable SWINT. */ + MOV.L #0x87203, r1 + MOV.B [r1], r2 + OR #(1 << 3), r2 + MOV.B r2, [r1] + + /* Enable SWINT2. */ + OR #(1 << 2), r2 + MOV.B r2, [r1] + + RTS + + section FREEMEM:DATA + public __tx_free_memory_start +__tx_free_memory_start + DS32 4 + + END diff --git a/ports_module/rxv2/iar/module_manager/src/tx_thread_context_restore.s b/ports_module/rxv2/iar/module_manager/src/tx_thread_context_restore.s new file mode 100644 index 00000000..6ab87d64 --- /dev/null +++ b/ports_module/rxv2/iar/module_manager/src/tx_thread_context_restore.s @@ -0,0 +1,194 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ + + extern __tx_thread_system_state + extern __tx_thread_current_ptr + extern __tx_thread_preempt_disable + extern __tx_thread_execute_ptr + extern __tx_timer_time_slice + extern __tx_thread_schedule + + section .text:CODE:ROOT + +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_context_restore RXv2/IAR */ +;/* 6.x */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function restores the interrupt context if it is processing a */ +;/* nested interrupt. If not, it returns to the interrupt thread if no */ +;/* preemption is necessary. Otherwise, if preemption is necessary or */ +;/* if no thread was running, the function returns to the scheduler. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_schedule Thread scheduling routine */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs Interrupt Service Routines */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* xx-xx-xxxx William E. Lamie Initial Version 6.x */ +;/* */ +;/**************************************************************************/ + public __tx_thread_context_restore + +__tx_thread_context_restore: +; +; /* Lockout interrupts. */ + + CLRPSW I ; disable interrupts + +; /* Determine if interrupts are nested. */ +; if (--_tx_thread_system_state) +; { + + MOV.L #__tx_thread_system_state, R1 + MOV.L [R1], R2 + SUB #1, R2 + MOV.L R2,[R1] + BEQ __tx_thread_not_nested_restore + +; +; /* Interrupts are nested. */ +; +; /* Recover the saved registers from the interrupt stack +; and return to the point of interrupt. */ +; +__tx_thread_nested_restore: + POPC FPSW ; restore FPU status + POPM R14-R15 ; restore R14-R15 + POPM R3-R5 ; restore R3-R5 + POPM R1-R2 ; restore R1-R2 + RTE ; return to point of interrupt, restore PSW including IPL +; } + +__tx_thread_not_nested_restore: +; +; /* Determine if a thread was interrupted and no preemption is required. */ +; else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr) +; || (_tx_thread_preempt_disable)) +; { + + MOV.L #__tx_thread_current_ptr, R1 ; Pickup current thread ptr address + MOV.L [R1], R2 + CMP #0, R2 + BEQ __tx_thread_idle_system_restore + + MOV.L #__tx_thread_preempt_disable, R3 ; pick up preempt disable flag + MOV.L [R3], R3 + CMP #0, R3 + BNE __tx_thread_no_preempt_restore ; if pre-empt disable flag set, we simply return to the original point of interrupt regardless + + MOV.L #__tx_thread_execute_ptr, R3 ; (_tx_thread_current_ptr != _tx_thread_execute_ptr) + CMP [R3], R2 + BNE __tx_thread_preempt_restore ; jump to pre-empt restoring +; +__tx_thread_no_preempt_restore: + SETPSW U ; user stack + POPC FPSW ; restore FPU status + POPM R14-R15 ; restore R14-R15 + POPM R3-R5 ; restore R3-R5 + POPM R1-R2 ; restore R1-R2 + RTE ; return to point of interrupt, restore PSW including IPL + +; } +; else +; { + +__tx_thread_preempt_restore: + +; /* Save the remaining time-slice and disable it. */ +; if (_tx_timer_time_slice) +; { + + MOV.L #__tx_timer_time_slice, R3 ; Pickup time-slice address + MOV.L [R3],R4 ; Pickup actual time-slice + CMP #0, R4 + BEQ __tx_thread_dont_save_ts ; no time slice to save +; +; _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice; +; _tx_timer_time_slice = 0; +; + MOV.L R4,24[R2] ; Save thread's time slice + MOV.L #0,R4 ; Clear value + MOV.L R4,[R3] ; Disable global time slice flag +; } +__tx_thread_dont_save_ts: +; +; /* Now store the remaining registers! */ + + SETPSW U ; user stack + PUSHM R6-R13 + + MVFACGU #0, A1, R4 ; Save accumulators. + MVFACHI #0, A1, R5 + MVFACLO #0, A1, R6 + PUSHM R4-R6 + MVFACGU #0, A0, R4 + MVFACHI #0, A0, R5 + MVFACLO #0, A0, R6 + PUSHM R4-R6 + + MOV.L #1, R3 ; indicate interrupt stack frame + PUSH.L R3 + +; +; /* Clear the current task pointer. */ +; _tx_thread_current_ptr = TX_NULL; +; R1 -> _tx_thread_current_ptr +; R2 -> *_tx_thread_current_ptr + + MOV.L R0,8[R2] ; Save thread's stack pointer in thread control block + MOV.L #0,R2 ; Build NULL value + MOV.L R2,[R1] ; Set current thread to NULL + +; /* Return to the scheduler. */ +; _tx_thread_schedule(); + +__tx_thread_idle_system_restore: + MVTC #0, PSW ; reset interrupt priority level to 0 + BRA __tx_thread_schedule ; jump to scheduler +; } +; +;} +; + END diff --git a/ports_module/rxv2/iar/module_manager/src/tx_thread_context_save.s b/ports_module/rxv2/iar/module_manager/src/tx_thread_context_save.s new file mode 100644 index 00000000..4ee01065 --- /dev/null +++ b/ports_module/rxv2/iar/module_manager/src/tx_thread_context_save.s @@ -0,0 +1,160 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ + + extern __tx_thread_system_state + extern __tx_thread_current_ptr + + section .text:CODE:ROOT +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_context_save RXv2/IAR */ +;/* 6.x */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function saves the context of an executing thread in the */ +;/* beginning of interrupt processing. The function also ensures that */ +;/* the system stack is used upon return to the calling ISR. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* xx-xx-xxxx William E. Lamie Initial Version 6.x */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_context_save(VOID) +;{ + public __tx_thread_context_save + +__tx_thread_context_save: +; +; /* Upon entry to this routine, it is assumed that interrupts are locked +; out and the (interrupt) stack frame looks like the following: +; +; (lower address) SP -> [return address of this call] +; SP+4 -> Saved R1 +; SP+8 -> Saved R2 +; SP+12-> Interrupted PC +; SP+16-> Interrupted PSW +; +; /* Check for a nested interrupt condition. */ +; if (_tx_thread_system_state++) +; { +; + + MOV.L #__tx_thread_system_state, R1 ; pick up address of system state + MOV.L [R1], R2 ; pick up system state + CMP #0, R2 ; 0 -> no nesting + BEQ __tx_thread_not_nested_save +; +; /* Nested interrupt condition. */ +; + ADD #1, r2 ; _tx_thread_system_state++ + MOV.L r2, [r1] + +; +; /* Save the rest of the scratch registers on the interrupt stack and return to the +; calling ISR. */ + POP R1 ; recuperate return address from stack + PUSHM R3-R5 + PUSHM R14-R15 + PUSHC FPSW ; (top) FPSW, R14, R15, R3, R4, R5, R1, R2, PC, PSW (bottom) + JMP R1 ; return address was preserved in R1 + +; +__tx_thread_not_nested_save: +; } +; +; /* Otherwise, not nested, check to see if a thread was running. */ +; else if (_tx_thread_current_ptr) +; { +; + ADD #1, R2 ; _tx_thread_system_state++ + MOV.L R2, [R1] + + MOV.L #__tx_thread_current_ptr, R2 ; Pickup current thread pointer + MOV.L [R2], R2 + CMP #0,R2 ; Is it NULL? + BEQ __tx_thread_idle_system_save ; Yes, idle system is running - idle restore +; +; /* Move stack frame over to the current threads stack. */ +; /* complete stack frame with registers not saved yet (R3-R5, R14-R15, FPSW) */ +; + MVFC USP, R1 ; pick up user stack pointer + MOV.L 16[R0], R2 + MOV.L R2, [-R1] ; save PSW on thread stack + MOV.L 12[R0], R2 + MOV.L R2, [-R1] ; save PC on thread stack + MOV.L 8[R0], R2 + MOV.L R2, [-R1] ; save R2 on thread stack + MOV.L 4[R0], R2 + MOV.L R2, [-R1] ; save R1 on thread stack + MOV.L R5, [-R1] ; save R5 on thread stack + MOV.L R4, [-R1] ; save R4 on thread stack + MOV.L R3, [-R1] ; save R3 on thread stack + MOV.L R15, [-R1] ; save R15 on thread stack + MOV.L R14, [-R1] ; save R14 on thread stack + MVFC FPSW, R3 + MOV.L R3, [-R1] ; save FPSW on thread stack + + POP R2 ; pick up return address from interrupt stack + ADD #16, R0, R0 ; correct interrupt stack pointer back to the bottom + MVTC R1, USP ; set user/thread stack pointer + JMP R2 ; return to ISR + +; } +; else +; { +; +__tx_thread_idle_system_save: +; +; /* Interrupt occurred in the scheduling loop. */ +; + POP R1 ; pick up return address + ADD #16, R0, R0 ; correct interrupt stack pointer back to the bottom (PC), don't care about saved registers + JMP R1 ; return to caller +; +; } +;} + END diff --git a/ports_module/rxv2/iar/module_manager/src/tx_thread_interrupt_control.s b/ports_module/rxv2/iar/module_manager/src/tx_thread_interrupt_control.s new file mode 100644 index 00000000..cfedd4b4 --- /dev/null +++ b/ports_module/rxv2/iar/module_manager/src/tx_thread_interrupt_control.s @@ -0,0 +1,85 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ + + section .text:CODE:ROOT +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_control RXv2/IAR */ +;/* 6.x */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is responsible for changing the interrupt lockout */ +;/* posture of the system. */ +;/* */ +;/* INPUT */ +;/* */ +;/* new_posture New interrupt lockout posture */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* old_posture Old interrupt lockout posture */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* xx-xx-xxxx William E. Lamie Initial Version 6.x */ +;/* */ +;/**************************************************************************/ +;UINT _tx_thread_interrupt_control(UINT new_posture) +;{ + public __tx_thread_interrupt_control +__tx_thread_interrupt_control: +; +; /* Pickup current interrupt lockout posture. */ +; + + MVFC PSW, R2 ; Save PSW to R2 + MOV.L R2, R3 ; Make a copy of PSW in r3 + +; +; /* Apply the new interrupt posture. */ +; + + BTST #16, R1 ; test I bit of PSW of "new posture" + BMNE #16, R2 ; conditionally set I bit of intermediate posture + + MVTC R2, PSW ; save intermediate posture to PSW + + MOV.L R3,R1 ; Get original SR + RTS ; Return to caller +;} + END diff --git a/ports_module/rxv2/iar/module_manager/src/tx_thread_schedule.s b/ports_module/rxv2/iar/module_manager/src/tx_thread_schedule.s new file mode 100644 index 00000000..2056d21b --- /dev/null +++ b/ports_module/rxv2/iar/module_manager/src/tx_thread_schedule.s @@ -0,0 +1,387 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + EXTERN __tx_thread_execute_ptr + EXTERN __tx_thread_current_ptr + EXTERN __tx_timer_time_slice + IMPORT __txm_module_manager_kernel_dispatch + IMPORT __tx_thread_system_state + EXTERN __txm_module_manager_memory_fault_info + EXTERN __txm_module_manager_memory_fault_handler + + section .text:CODE:ROOT + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_schedule RXv2/IAR */ +/* 6.x */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function waits for a thread control block pointer to appear in */ +/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ +/* in the variable, the corresponding thread is resumed. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_initialize_kernel_enter ThreadX entry function */ +/* _tx_thread_system_return Return to system from thread */ +/* _tx_thread_context_restore Restore thread's context */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* xx-xx-xxxx Scott Larson Initial Version 6.x */ +/* */ +/**************************************************************************/ +// VOID _tx_thread_schedule(VOID) +// { + public __tx_thread_schedule +__tx_thread_schedule: + + /* Enable interrupts. */ + + SETPSW I + + /* Wait for a thread to execute. */ + // do + // { + MOV.L #__tx_thread_execute_ptr, R1 // Address of thread to executer ptr +__tx_thread_schedule_loop: + MOV.L [R1],R2 // Pickup next thread to execute + CMP #0,R2 // Is it NULL? + BEQ __tx_thread_schedule_loop // Yes, idle system, keep checking + + // } + // while(_tx_thread_execute_ptr == TX_NULL); + + /* Yes! We have a thread to execute. Lockout interrupts and transfer control to it. */ + + CLRPSW I // disable interrupts + + /* Setup the current thread pointer. */ + // _tx_thread_current_ptr = _tx_thread_execute_ptr; + + MOV.L #__tx_thread_current_ptr, R3 + MOV.L R2,[R3] // Setup current thread pointer + + /* Increment the run count for this thread. */ + // _tx_thread_current_ptr -> tx_thread_run_count++; + + MOV.L 4[R2],R3 // Pickup run count + ADD #1,R3 // Increment run counter + MOV.L R3,4[R2] // Store it back in control block + + /* Setup time-slice, if present. */ + // _tx_timer_time_slice = _tx_thread_current_ptr -> tx_thread_time_slice; + + MOV.L 24[R2],R3 // Pickup thread time-slice + MOV.L #__tx_timer_time_slice,R4 // Pickup pointer to time-slice + MOV.L R3, [R4] // Setup time-slice + + /* Switch to the thread's stack. */ + // SP = _tx_thread_execute_ptr -> tx_thread_stack_ptr; + SETPSW U // user stack mode + MOV.L 8[R2],SP // Pickup stack pointer + + + /* Set up MPU. */ + // Disable MPU + MOV.L #0x00086500,R1 // Pickup MPEN + MOV #0,R3 // Build disable value + MOV.L R3,[R1] // Disable MPU + // Determine if protection for this thread is required + MOV.L 156[R2],R1 // Pickup user_mode + CMP #0,R1 // Is protection required for this thread? + BEQ skip_mpu_setup // No, skip MPU setup + + MOV.L #0x00086408,R1 // Region 1 Start Page Register address + MOV.L 144[R2],R2 // Address of module instance ptr at offset 144 in TCB + ADD #100,R2,R2 // Get address of MPU table in module struct, starting at region 1 + + // Region 0 (Trampoline from User mode to ThreadX) set up in txm_module_manager_setup_mpu_registers.c + + // Build region 1 (User code) + MOV.L [R2+],R4 // Pickup region 1 start page, increment to region 1 end page + MOV.L R4,[R1+] // Setup region 1 start page reg, increment to region 1 end page reg. + MOV.L [R2+],R4 // Pickup region 1 end page, increment to region 2 start page + MOV.L R4,[R1+] // Setup region 1 end page reg, increment to region 2 start page reg. + + // Build region 2 (User data) + MOV.L [R2+],R4 // Pickup region 2 start page, increment to region 2 end page + MOV.L R4,[R1+] // Setup region 2 start page reg, increment to region 2 end page reg. + MOV.L [R2+],R4 // Pickup region 2 end page, increment to region 3 start page + MOV.L R4,[R1+] // Setup region 2 end page reg, increment to region 3 start page reg. + + // Build region 3 (Shared memory) + MOV.L [R2+],R4 // Pickup region 3 start page, increment to region 3 end page + MOV.L R4,[R1+] // Setup region 3 start page reg, increment to region 3 end page reg. + MOV.L [R2+],R4 // Pickup region 3 end page, increment to region 4 start page + MOV.L R4,[R1+] // Setup region 3 end page reg, increment to region 4 start page reg. + + // Region 4-7 unused + + // Setup background region + MOV.L #0x00086504,R1 // Pickup MPBAC + MOV #0,[R1] // Read/Write/Execute prohibited. + // Enable MPU + MOV.L #0x00086500,R1 // Pickup MPEN + MOV #1,[R1] // Enable MPU + +skip_mpu_setup + + + /* Determine if an interrupt frame or a synchronous task suspension frame is present. */ + + POP R1 // Pickup stack type + CMP #1, R1 // Is it an interrupt stack? + BNE __tx_thread_synch_return // No, a synchronous return frame is present. + + POPM R1-R3 // Restore accumulators. + MVTACLO R3, A0 + MVTACHI R2, A0 + MVTACGU R1, A0 + POPM R1-R3 + MVTACLO R3, A1 + MVTACHI R2, A1 + MVTACGU R1, A1 + + POPM R6-R13 // Recover interrupt stack frame + POPC FPSW + POPM R14-R15 + POPM R3-R5 + POPM R1-R2 + RTE // return to point of interrupt, this restores PC and PSW + +__tx_thread_synch_return + POPC PSW + POPM R6-R13 // Recover solicited stack frame + RTS +// } + + extern __tx_thread_context_save + extern __tx_thread_context_restore + +/* Software triggered interrupt used to perform context switches. + The priority of this interrupt is set to the lowest priority within + tx_initialize_low_level() and triggered by ThreadX when calling + _tx_thread_system_return(). */ + + public ___interrupt_27 +___interrupt_27: + + PUSHM R1-R2 + + BSR __tx_thread_context_save + + BRA __tx_thread_context_restore + + +/* You may have to modify BSP to use this handler. + // MPU Memory access violation + PUBLIC ___excep_access_inst + PUBLIC ___violation_handler +___excep_access_inst +___violation_handler + // Disable interrupts + CLRPSW I // disable interrupts + // Save contents of R1 and R2 + PUSH R1 + PUSH R2 + // Increment and save system state + MOV.L #__tx_thread_system_state, R1 // Pickup address of system state + MOV.L [R1], R2 // Pickup system state + ADD #1, R2 // Increment + MOV.L R2, [R1] // Store new system state + + // Now pickup and store all the fault related information. + + MOV.L #__txm_module_manager_memory_fault_info, R1 + MOV.L #__tx_thread_current_ptr, R2 // Build current thread pointer address + MOV.L [R2], R2 // Pickup the current thread pointer + MOV.L R2, 0[R1] // Save current thread pointer in fault info structure + MOV.L 8[SP], R2 // Pickup instruction address at point of fault + MOV.L R2, 4[R1] // Save point of fault + MOV.L #0x0008650C, R2 // Pickup Memory-Protection Error Status Register + MOV.L [R2], 8[R1] // Save MPESTS + MOV.L #0x00086514, R2 // Pickup Data Memory-Protection Error Address Register + MOV.L [R2], 12[R1] // Save MPDEA + MOV.L #0x00086528, R2 // Pickup Instruction Hit Region Register + MOV.L [R2], 16[R1] // Save MHITI + MOV.L #0x0008652C, R2 // Pickup Data Hit Region Register + MOV.L [R2], 20[R1] // Save MHITD + MOV.L 12[SP], R2 // Pickup PSW + MOV.L R2, 24[R1] // Save PSW + MVFC USP, R2 // Pickup user stack pointer + MOV.L R2, 28[R1] // Save user stack pointer + MOV.L R3, 40[R1] // Save R3 + MOV.L R4, 44[R1] // Save R4 + MOV.L R5, 48[R1] // Save R5 + MOV.L R6, 52[R1] // Save R6 + MOV.L R7, 56[R1] // Save R7 + MOV.L R8, 60[R1] // Save R8 + MOV.L R9, 64[R1] // Save R9 + MOV.L R10, 68[R1] // Save R10 + MOV.L R11, 72[R1] // Save R11 + MOV.L R12, 76[R1] // Save R12 + MOV.L R13, 80[R1] // Save R13 + MOV.L R14, 84[R1] // Save R14 + MOV.L R15, 84[R1] // Save R15 + POP R3 // Recall R1 + MOV.L R3, 32[R1] // Save R1 + POP R3 // Recall R2 + MOV.L R3, 36[R1] // Save R2 + + BSR __txm_module_manager_memory_fault_handler // Call memory manager fault handler + + // Decrement and save system state + MOV.L #__tx_thread_system_state, R1 // Pickup address of system state + MOV.L [R1], R2 // Pickup system state + SUB #1, R2 // Decrement + MOV.L R2, [R1] // Store new system state + + MOV.L #__tx_thread_current_ptr, R2 // Pickup address of current thread pointer + MOV.L #0, [R2] // Clear current thread pointer + BRA __tx_thread_schedule // Attempt to schedule the next thread +*/ + + + public ___interrupt_26 +___interrupt_26: + PUBLIC __txm_module_manager_kernel +__txm_module_manager_kernel + + MOV.L [SP], R5 // Get return address + CMP #__txm_module_manager_user_mode_entry+3, R5 // Did we come from user_mode_entry? + BEQ __txm_module_manager_entry // If so, continue. + RTE // If not, then return from where we came. + +__txm_module_manager_entry + // We are entering the kernel from a module thread with user mode selected. + // At this point, we are out of user mode! + // Clear current user mode. + MOV.L #__tx_thread_current_ptr, R5 + MOV [R5],R5 + MOV #0,152[R5] + + // Switch to kernel stack + PUSHM R1-R2 + MVFC USP, R1 // Pickup module thread stack pointer + MOV.L R1, 172[R5] // Save module thread stack pointer + MOV.L 164[R5], R1 // Pickup kernel stack end +#ifndef TXM_MODULE_KERNEL_STACK_MAINTENANCE_DISABLE + MOV.L R1, 16[R5] // Set stack end + MOV.L 160[R5], R2 // Pickup kernel stack start + MOV.L R2, 12[R5] // Set stack start + MOV.L 168[R5], R2 // Pickup kernel stack size + MOV.L R2, 20[R5] // Set stack size +#endif + MVTC R1, USP // Set stack pointer + POPM R1-R2 + + // Modify PSW in ISP to return in supervisor mode and user stack + MOV.L 4[SP], R5 + BCLR #20, R5 + MOV.L R5, 4[SP] + + // Return to user_mode_entry where kernel_dispatch will be called. + RTE + + + + SECTION CODE:CODE (4) // Align 4, smallest page size for MPU is 16 bytes. + ALIGN 4 + PUBLIC __txm_module_manager_user_mode_entry +__txm_module_manager_user_mode_entry + + INT #26 // Enter ThreadX kernel (exit User mode). + + // At this point, we are out of user mode. + // Simply call the kernel dispatch function. + MOV.L #__txm_module_manager_kernel_dispatch,R5 + JSR R5 + + // Restore user mode while inside of ThreadX. + MOV.L #__tx_thread_current_ptr, R5 + MOV [R5],R5 + MOV #1,152[R5] + + // Switch to module thread stack +#ifndef TXM_MODULE_KERNEL_STACK_MAINTENANCE_DISABLE + PUSH R1 + MOV.L 176[R5], R1 // Pickup module thread stack start + MOV.L R1, 12[R5] // Set stack start + MOV.L 180[R5], R1 // Pickup module thread stack end + MOV.L R1, 16[R5] // Set stack end + MOV.L 184[R5], R1 // Pickup kernel stack size + MOV.L R1, 20[R5] // Set stack size + POP R1 +#endif + MOV.L 172[R5], R5 // Pickup module thread stack pointer + MVTC R5, USP // Set stack pointer + + + // USP is set for an RTS, need to set for RTE to set User mode in PSW. + // Push return address on SP + MOV.L [SP],R5 + PUSH R5 + // Set user mode and place PSW in prev position in SP + MVFC PSW,R5 + BSET #20,R5 + MOV.L R5,4[SP] + RTE + + // Fill rest of page with NOPs. + NOP + NOP + NOP + NOP + + NOP + NOP + NOP + NOP + + NOP + NOP + NOP + NOP + + END diff --git a/ports_module/rxv2/iar/module_manager/src/tx_thread_stack_build.s b/ports_module/rxv2/iar/module_manager/src/tx_thread_stack_build.s new file mode 100644 index 00000000..393e3916 --- /dev/null +++ b/ports_module/rxv2/iar/module_manager/src/tx_thread_stack_build.s @@ -0,0 +1,147 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; + + section .text:CODE:ROOT + +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_stack_build RXv2/IAR */ +;/* 6.x */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function builds a stack frame on the supplied thread's stack. */ +;/* The stack frame results in a fake interrupt return to the supplied */ +;/* function pointer. */ +;/* */ +;/* INPUT */ +;/* */ +;/* thread_ptr Pointer to thread control blk */ +;/* function_ptr Pointer to return function */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_thread_create Create thread service */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* xx-xx-xxxx William E. Lamie Initial Version 6.x */ +;/* */ +;/**************************************************************************/ + + public __tx_thread_stack_build + +__tx_thread_stack_build: +; +; +; /* Build an interrupt frame. The form of the fake interrupt stack +; on the Renesas RX should look like the following after it is built: +; +; Stack Top: 1 Interrupt stack frame type +; ACC0 +; ACC1 +; R6 +; R7 +; R8 +; R9 +; R10 +; R11 +; R12 +; R13 +; FPSW +; R14 +; R15 +; R3 +; R4 +; R5 +; R1 +; R2 +; PC +; PSW + +; +; Stack Bottom: (higher memory address) */ +; + MOV.L 16[R1],R3 ; Pickup end of stack area + BCLR #0, R3 ; mask for 4-byte alignment + BCLR #1, R3 +; +; /* Build the stack frame. */ +; + MOV.L #30000h, R4 + MOV.L R4, [-R3] ; initial PSW (SVC mode, U flag set) + MOV.L R2, [-R3] ; initial PC + MOV.L #0, R4 + MOV.L R4,[-R3] ; initial R2 ... + MOV.L R4,[-R3] ; initial R1 ... + MOV.L R4,[-R3] ; initial R5 ... + MOV.L R4,[-R3] ; initial R4 ... + MOV.L R4,[-R3] ; initial R3 ... + MOV.L R4,[-R3] ; initial R15 ... + MOV.L R4,[-R3] ; initial R14 ... + MVFC FPSW, r4 + MOV.L R4, [-R3] ; initial FPSW + MOV.L #0, R4 + MOV.L R4,[-R3] ; initial R13 ... + MOV.L R4,[-R3] ; initial R12 ... + MOV.L R4,[-R3] ; initial R11 ... + MOV.L R4,[-R3] ; initial R10 ... + MOV.L R4,[-R3] ; initial R9 ... + MOV.L R4,[-R3] ; initial R8 ... + MOV.L R4,[-R3] ; initial R7 ... + MOV.L R4,[-R3] ; initial R6 ... + + MOV.L R4,[-R3] ; Accumulator 1 + MOV.L R4,[-R3] + MOV.L R4,[-R3] + + MOV.L R4,[-R3] ; Accumulator 0 + MOV.L R4,[-R3] + MOV.L R4,[-R3] + + MOV.L #1, R4 + MOV.L R4,[-R3] ; indicate interrupt stack frame +; /* Setup stack pointer. */ +; thread_ptr -> tx_thread_stack_ptr = R1; + MOV.L R3, 8[R1] + ; store initial SP in thread control block + RTS + +;} + + END diff --git a/ports_module/rxv2/iar/module_manager/src/tx_thread_system_return.s b/ports_module/rxv2/iar/module_manager/src/tx_thread_system_return.s new file mode 100644 index 00000000..91dd86f2 --- /dev/null +++ b/ports_module/rxv2/iar/module_manager/src/tx_thread_system_return.s @@ -0,0 +1,74 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ + + section .text:CODE:ROOT + +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_system_return RXv2/IAR */ +;/* 6.x */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is target processor specific. It is used to transfer */ +;/* control from a thread back to the system. Only a minimal context */ +;/* is saved since the compiler assumes temp registers are going to get */ +;/* slicked by a function call anyway. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_schedule Thread scheduling loop */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ThreadX components */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* xx-xx-xxxx William E. Lamie Initial Version 6.x */ +;/* */ +;/**************************************************************************/ + + public __tx_thread_system_return + +__tx_thread_system_return: + + BRA __tx_thread_system_return + + RTS + + END diff --git a/ports_module/rxv2/iar/module_manager/src/tx_timer_interrupt.s b/ports_module/rxv2/iar/module_manager/src/tx_timer_interrupt.s new file mode 100644 index 00000000..8fe142e6 --- /dev/null +++ b/ports_module/rxv2/iar/module_manager/src/tx_timer_interrupt.s @@ -0,0 +1,235 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ + + extern __tx_timer_expiration_process + extern __tx_timer_system_clock + extern __tx_timer_expired_time_slice + extern __tx_timer_current_ptr + extern __tx_timer_expired + extern __tx_timer_list_start + extern __tx_timer_time_slice + extern __tx_timer_list_end + extern __tx_thread_time_slice + + section .text:CODE:ROOT + +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_timer_interrupt RXv2/IAR */ +;/* 6.x */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function processes the hardware timer interrupt. This */ +;/* processing includes incrementing the system clock and checking for */ +;/* time slice and/or timer expiration. If either is found, the */ +;/* interrupt context save/restore functions are called along with the */ +;/* expiration functions. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_context_save Save interrupted context */ +;/* _tx_timer_expiration_process Timer expiration processing */ +;/* _tx_thread_time_slice Time slice interrupted thread */ +;/* _tx_thread_context_restore Restore interrupted context */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* interrupt vector */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* xx-xx-xxxx William E. Lamie Initial Version 6.x */ +;/* */ +;/**************************************************************************/ + + public __tx_timer_interrupt +__tx_timer_interrupt: +; +; /* Upon entry to this routine, it is assumed that all interrupts are locked +; out and the stack looks like the following: +; SP+4 -> Interrupted PC +; SP+8-> Interrupted SR +; */ +; +; /* Increment the system clock. */ +; _tx_timer_system_clock++; +; + PUSHM R14-R15 + PUSHM R1-R5 + + MOV.L #__tx_timer_system_clock, R1 ; Pickup address of system clock + MOV.L [R1], R2 ; Pickup system clock + ADD #1, R2 ; Increment system clock + MOV.L R2,[R1] ; Store new system clock +; +; /* Test for time-slice expiration. */ +; if (_tx_timer_time_slice) +; { +; + MOV.L #__tx_timer_time_slice, R1 ; Pickup address of time slice + MOV.L [R1], R2 ; Pickup the current time slice + CMP #0, R2 ; Is a time slice active? + BEQ __tx_timer_no_time_slice ; No, skip timer slice processing +; +; /* Decrement the time_slice. */ +; _tx_timer_time_slice--; +; + SUB #1, R2 ; Decrement the time-slice + MOV.L R2, [R1] ; Store time-slice +; +; /* Check for expiration. */ +; if (__tx_timer_time_slice == 0) +; + CMP #0, R2 ; Has it expired? + BNE __tx_timer_no_time_slice ; No, time-slice has not expired +; +; /* Set the time-slice expired flag. */ +; _tx_timer_expired_time_slice = TX_TRUE; +; + MOV.L #__tx_timer_expired_time_slice, R1 ; Pickup address of expired time-slice + MOV.L #1, R2 ; Build expired value + MOV.L R2, [R1] ; Set expired time slice variable +; } +; +__tx_timer_no_time_slice: +; +; /* Test for timer expiration. */ +; if (*_tx_timer_current_ptr) +; { +; + MOV.L #__tx_timer_current_ptr, R1 ; Pickup address of current timer ptr + MOV.L [R1], R2 ; Pickup current pointer + MOV.L [R2+], R1 ; pickup timer list entry, _tx_timer_current_ptr++ + CMP #0, R1 ; Is timer pointer NULL? + BEQ __tx_timer_no_timer ; Yes, no timer has expired + +; +; /* Set expiration flag. */ +; _tx_timer_expired = TX_TRUE; +; + MOV.L #__tx_timer_expired,R2 ; Build address of expired flag + MOV.L #1, R1 ; Build expired value + MOV.L R1, [R2] + BRA __tx_timer_done ; Finished with timer processing +; +; } +; else +; { +__tx_timer_no_timer: +; +; /* No timer expired, increment the timer pointer. */ +; _tx_timer_current_ptr++; +; +; /* R2 already contains __tx_timer_current_ptr++ */ +; +; /* Check for wrap-around. */ +; if (_tx_timer_current_ptr == _tx_timer_list_end) +; + MOV.L #__tx_timer_list_end, R1 ; Pickup the timer list end ptr + MOV.L [R1], R1 ; Pickup actual timer list end + CMP R1, R2 ; Are we at list end? + BNE __tx_timer_skip_wrap ; No, don't move pointer to the + ; top of the list +; +; /* Wrap to beginning of list. */ +; _tx_timer_current_ptr = _tx_timer_list_start; +; + MOV.L #__tx_timer_list_start, R2 ; Pickup the timer list start ptr + MOV.L [R2], R2 ; Pickup the start of the list +; } +; +__tx_timer_skip_wrap: + MOV.L #__tx_timer_current_ptr,R1 + MOV.L R2, [R1] ; store in updated pointer in _tx_timer_current_ptr + +__tx_timer_done: +; +; /* See if anything has expired. */ +; if ((_tx_timer_expired_time_slice) || (_tx_timer_expired)) +; { +; + MOV.L #__tx_timer_expired_time_slice, R1 ; Pickup expired time slice addr + MOV.L [R1], R1 ; Pickup expired time slice + MOV.L #__tx_timer_expired, R2 ; Pickup expired timer flag address + MOV.L [R2], R2 ; Pickup actual flag + OR R1, R2 ; Or flags together + BEQ __tx_timer_nothing_expired ; If Z set, nothing has expired + +__tx_something_expired: +; /* Did a timer expire? */ +; if (_tx_timer_expired) +; { + MOV.L #__tx_timer_expired,R1 ; Pickup expired flag address + MOV.L [R1], R1 ; Pickup expired flag + CMP #0,R1 ; Is the expired timer flag set? + BEQ __tx_timer_dont_activate ; No, skip timer activation +; +; /* Process timer expiration. */ +; _tx_timer_expiration_process(); +; + BSR __tx_timer_expiration_process ; Call the timer expiration handling routine +; +; } +__tx_timer_dont_activate: +; +; /* Did time slice expire? */ +; if (_tx_timer_expired_time_slice) +; { +; + MOV.L #__tx_timer_expired_time_slice, R1 ; Pickup time-slice expired flag addr + MOV.L [R1], R1 ; Pickup actual flag + CMP #0,R1 ; Has time-slice expired? + BEQ __tx_timer_not_ts_expiration ; No, skip time-slice expiration +; +; /* Time slice interrupted thread. */ +; _tx_thread_time_slice(); + + BSR __tx_thread_time_slice ; Call time-slice processing +; } +; +__tx_timer_not_ts_expiration: + +__tx_timer_nothing_expired: + + POPM R1-R5 + POPM R14-R15 +; + RTS ; return to point of interrupt +; +;} + END
\ No newline at end of file diff --git a/ports_module/rxv2/iar/module_manager/src/txm_module_manager_alignment_adjust.c b/ports_module/rxv2/iar/module_manager/src/txm_module_manager_alignment_adjust.c new file mode 100644 index 00000000..c8dfb729 --- /dev/null +++ b/ports_module/rxv2/iar/module_manager/src/txm_module_manager_alignment_adjust.c @@ -0,0 +1,79 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + +#include "tx_api.h" +#include "txm_module.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_alignment_adjust RXv2/IAR */ +/* 6.1.9 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function adjusts the alignment and size of the code and data */ +/* section for a given module implementation. */ +/* */ +/* INPUT */ +/* */ +/* module_preamble Pointer to module preamble */ +/* code_size Size of the code area (updated) */ +/* code_alignment Code area alignment (updated) */ +/* data_size Size of data area (updated) */ +/* data_alignment Data area alignment (updated) */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Initial thread stack frame */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ +/* */ +/**************************************************************************/ +VOID _txm_module_manager_alignment_adjust(TXM_MODULE_PREAMBLE *module_preamble, + ULONG *code_size, + ULONG *code_alignment, + ULONG *data_size, + ULONG *data_alignment) +{ + + +} diff --git a/ports_module/rxv2/iar/module_manager/src/txm_module_manager_external_memory_enable.c b/ports_module/rxv2/iar/module_manager/src/txm_module_manager_external_memory_enable.c new file mode 100644 index 00000000..dd15ac03 --- /dev/null +++ b/ports_module/rxv2/iar/module_manager/src/txm_module_manager_external_memory_enable.c @@ -0,0 +1,175 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + +#include "tx_api.h" +#include "tx_mutex.h" +#include "tx_queue.h" +#include "tx_thread.h" +#include "txm_module.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_external_memory_enable RXv2/IAR */ +/* 6.1.9 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function creates an entry in the MPU table for a shared */ +/* memory space. */ +/* */ +/* INPUT */ +/* */ +/* module_instance Module instance pointer */ +/* start_address Start address of memory */ +/* length Length of external memory */ +/* attributes Memory attributes (r/w) */ +/* */ +/* OUTPUT */ +/* */ +/* status Completion status */ +/* */ +/* CALLS */ +/* */ +/* _tx_mutex_get Get protection mutex */ +/* _tx_mutex_put Release protection mutex */ +/* _txm_power_of_two_block_size Round length to power of two */ +/* */ +/* CALLED BY */ +/* */ +/* Application code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ +/* */ +/**************************************************************************/ +UINT _txm_module_manager_external_memory_enable(TXM_MODULE_INSTANCE *module_instance, + VOID *start_address, + ULONG length, + UINT attributes) +{ +ULONG address; +UINT attributes_check = 0; +TXM_MODULE_PREAMBLE *module_preamble; + + /* Determine if the module manager has not been initialized yet. */ + if (_txm_module_manager_ready != TX_TRUE) + { + /* Module manager has not been initialized. */ + return(TX_NOT_AVAILABLE); + } + + /* Determine if the module is valid. */ + if (module_instance == TX_NULL) + { + /* Invalid module pointer. */ + return(TX_PTR_ERROR); + } + + /* Get module manager protection mutex. */ + _tx_mutex_get(&_txm_module_manager_mutex, TX_WAIT_FOREVER); + + /* Determine if the module instance is valid. */ + if (module_instance -> txm_module_instance_id != TXM_MODULE_ID) + { + /* Release the protection mutex. */ + _tx_mutex_put(&_txm_module_manager_mutex); + + /* Invalid module pointer. */ + return(TX_PTR_ERROR); + } + + /* Determine if the module instance is in the loaded state. */ + if (module_instance -> txm_module_instance_state != TXM_MODULE_LOADED) + { + /* Release the protection mutex. */ + _tx_mutex_put(&_txm_module_manager_mutex); + + /* Return error if the module is not ready. */ + return(TX_START_ERROR); + } + + /* Check if preamble ext/shared mem property bit set. */ + module_preamble = module_instance -> txm_module_instance_preamble_ptr; + if(!(module_preamble -> txm_module_preamble_property_flags & TXM_MODULE_SHARED_EXTERNAL_MEMORY_ACCESS)) + { + /* Release the protection mutex. */ + _tx_mutex_put(&_txm_module_manager_mutex); + + /* Return error if bit not set. */ + return(TXM_MODULE_INVALID_PROPERTIES); + } + + /* Start address must be 16-byte aligned. */ + address = (ULONG) start_address; + if(address != (address & 0xFFFFFFF0)) + { + /* Release the protection mutex. */ + _tx_mutex_put(&_txm_module_manager_mutex); + + /* Return alignment error. */ + return(TXM_MODULE_ALIGNMENT_ERROR); + } + + /* Check length. */ + + /* At this point, we have a valid address and length. */ + /* Build region start page register. */ + module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_SHARED_MPU_INDEX] = address & 0xFFFFFFF0; + + /* Check for valid attributes. */ + if(attributes & TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_EXECUTE) + { + attributes_check |= TXM_MODULE_MANAGER_ATTRIBUTE_EXECUTE_MPU_BIT; + } + if(attributes & TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE) + { + attributes_check |= TXM_MODULE_MANAGER_ATTRIBUTE_WRITE_MPU_BIT; + } + if(attributes & TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_READ) + { + attributes_check |= TXM_MODULE_MANAGER_ATTRIBUTE_READ_MPU_BIT; + } + + /* Build region end page register with attributes, OR in the Valid bit. */ + module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_SHARED_MPU_INDEX+1] = ((address + length - 1) & 0xFFFFFFF0) | attributes_check | 0x01; + + /* Save address and length in module. */ + module_instance -> txm_module_instance_shared_memory_address = address; + module_instance -> txm_module_instance_shared_memory_length = length; + + /* Release the protection mutex. */ + _tx_mutex_put(&_txm_module_manager_mutex); + + /* Return success. */ + return(TX_SUCCESS); +} diff --git a/ports_module/rxv2/iar/module_manager/src/txm_module_manager_memory_fault_handler.c b/ports_module/rxv2/iar/module_manager/src/txm_module_manager_memory_fault_handler.c new file mode 100644 index 00000000..c207f5fd --- /dev/null +++ b/ports_module/rxv2/iar/module_manager/src/txm_module_manager_memory_fault_handler.c @@ -0,0 +1,110 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + +#include "tx_api.h" +#include "tx_thread.h" +#include "txm_module.h" + + +/* Define the user's fault notification callback function pointer. This is + setup via the txm_module_manager_memory_fault_notify API. */ + +VOID (*_txm_module_manager_fault_notify)(TX_THREAD *, TXM_MODULE_INSTANCE *); + + +/* Define a macro that can be used to allocate global variables useful to + store information about the last fault. This macro is defined in + txm_module_port.h and is usually populated in the assembly language + fault handling prior to the code calling _txm_module_manager_memory_fault_handler. */ + +TXM_MODULE_MANAGER_FAULT_INFO + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_memory_fault_handler RXv2/IAR */ +/* 6.1.9 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function handles a fault associated with a memory protected */ +/* module. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_terminate Terminate thread */ +/* */ +/* CALLED BY */ +/* */ +/* Fault handler */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ +/* */ +/**************************************************************************/ +VOID _txm_module_manager_memory_fault_handler(VOID) +{ + +TXM_MODULE_INSTANCE *module_instance_ptr; +TX_THREAD *thread_ptr; + + /* Pickup the current thread. */ + thread_ptr = _tx_thread_current_ptr; + + /* Initialize the module instance pointer to NULL. */ + module_instance_ptr = TX_NULL; + + /* Is there a thread? */ + if (thread_ptr) + { + /* Pickup the module instance. */ + module_instance_ptr = thread_ptr -> tx_thread_module_instance_ptr; + + /* Terminate the current thread. */ + _tx_thread_terminate(_tx_thread_current_ptr); + } + + /* Determine if there is a user memory fault notification callback. */ + if (_txm_module_manager_fault_notify) + { + /* Yes, call the user's notification memory fault callback. */ + (_txm_module_manager_fault_notify)(thread_ptr, module_instance_ptr); + } +} diff --git a/ports_module/rxv2/iar/module_manager/src/txm_module_manager_memory_fault_notify.c b/ports_module/rxv2/iar/module_manager/src/txm_module_manager_memory_fault_notify.c new file mode 100644 index 00000000..fd06a14f --- /dev/null +++ b/ports_module/rxv2/iar/module_manager/src/txm_module_manager_memory_fault_notify.c @@ -0,0 +1,84 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + +#include "tx_api.h" +#include "tx_thread.h" +#include "txm_module.h" + + +/* Define the external user's fault notification callback function pointer. This is + setup via the txm_module_manager_memory_fault_notify API. */ + +extern VOID (*_txm_module_manager_fault_notify)(TX_THREAD *, TXM_MODULE_INSTANCE *); + + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_memory_fault_notify RXv2/IAR */ +/* 6.1.9 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function registers an application callback when/if a memory */ +/* fault occurs. The supplied thread is automatically terminated, but */ +/* any other threads in the same module may still execute. */ +/* */ +/* INPUT */ +/* */ +/* notify_function Memory fault notification */ +/* function, NULL disables. */ +/* */ +/* OUTPUT */ +/* */ +/* status Completion status */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ +/* */ +/**************************************************************************/ +UINT _txm_module_manager_memory_fault_notify(VOID (*notify_function)(TX_THREAD *, TXM_MODULE_INSTANCE *)) +{ + /* Setup notification function. */ + _txm_module_manager_fault_notify = notify_function; + + /* Return success. */ + return(TX_SUCCESS); +} diff --git a/ports_module/rxv2/iar/module_manager/src/txm_module_manager_setup_mpu_registers.c b/ports_module/rxv2/iar/module_manager/src/txm_module_manager_setup_mpu_registers.c new file mode 100644 index 00000000..19b500de --- /dev/null +++ b/ports_module/rxv2/iar/module_manager/src/txm_module_manager_setup_mpu_registers.c @@ -0,0 +1,107 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + +#include "tx_api.h" +#include "txm_module.h" + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_setup_mpu_registers RXv2/IAR */ +/* 6.1.9 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function sets up the RX MPU register definitions based */ +/* on the module's memory characteristics. */ +/* */ +/* INPUT */ +/* */ +/* module_instance Pointer to module instance */ +/* */ +/* OUTPUT */ +/* */ +/* MPU specifications for module */ +/* */ +/* CALLS */ +/* */ +/* none */ +/* */ +/* CALLED BY */ +/* */ +/* _txm_module_manager_thread_create */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ +/* */ +/**************************************************************************/ +VOID _txm_module_manager_setup_mpu_registers(TXM_MODULE_INSTANCE *module_instance) +{ + +ULONG region_size; +ULONG region_start_page_register; +ULONG region_end_page_register; + + /* Setup region 0 for the ThreadX trampoline code. */ + region_start_page_register = (ULONG) _txm_module_manager_user_mode_entry; + region_start_page_register = region_start_page_register & 0xFFFFFFF0; + module_instance -> txm_module_instance_mpu_registers[0] = region_start_page_register; + /* Region 0 End page is 2 pages away (for a total of 3 pages). + * Set reading permitted, writing prohibited, execution permitted, enable region. */ + module_instance -> txm_module_instance_mpu_registers[1] = (region_start_page_register + 0x20) | 0x0B; + + /* Place the trampoline protection in the MPU registers */ + RSPAGE0 = module_instance -> txm_module_instance_mpu_registers[0]; + REPAGE0 = module_instance -> txm_module_instance_mpu_registers[1]; + + /* Setup region 1 for code area. */ + /* Set reading permitted, writing prohibited, execution permitted, enable region. */ + region_start_page_register = (ULONG) module_instance -> txm_module_instance_code_start; + region_size = (ULONG) module_instance -> txm_module_instance_code_size; + + region_end_page_register = (region_start_page_register + region_size - 1) & 0xFFFFFFF0; + region_start_page_register = region_start_page_register & 0xFFFFFFF0; + + module_instance -> txm_module_instance_mpu_registers[2] = region_start_page_register; + module_instance -> txm_module_instance_mpu_registers[3] = region_end_page_register | 0x0B; + + /* Setup region 2 for data area. */ + /* Set reading permitted, writing permitted, execution prohibited, enable region. */ + region_start_page_register = (ULONG) module_instance -> txm_module_instance_data_start; + region_size = (ULONG) module_instance -> txm_module_instance_data_size; + + region_end_page_register = (region_start_page_register + region_size - 1) & 0xFFFFFFF0; + region_start_page_register = region_start_page_register & 0xFFFFFFF0; + + module_instance -> txm_module_instance_mpu_registers[4] = region_start_page_register; + module_instance -> txm_module_instance_mpu_registers[5] = region_end_page_register | 0x0D; + +} diff --git a/ports_module/rxv2/iar/module_manager/src/txm_module_manager_thread_stack_build.s b/ports_module/rxv2/iar/module_manager/src/txm_module_manager_thread_stack_build.s new file mode 100644 index 00000000..e7df51a1 --- /dev/null +++ b/ports_module/rxv2/iar/module_manager/src/txm_module_manager_thread_stack_build.s @@ -0,0 +1,147 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + SECTION CODE:CODE + ALIGN 2 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_thread_stack_build RXv2/IAR */ +/* 6.x */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function builds a stack frame on the supplied thread's stack. */ +/* The stack frame results in a fake interrupt return to the supplied */ +/* function pointer. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Pointer to thread control blk */ +/* function_ptr Pointer to shell function */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_thread_create Create thread service */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* xx-xx-xxxx Scott Larson Initial Version 6.x */ +/* */ +/**************************************************************************/ +// VOID _txm_module_manager_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(TX_THREAD *, TXM_MODULE_INSTANCE *)) +// { + PUBLIC __txm_module_manager_thread_stack_build +__txm_module_manager_thread_stack_build: + + /* Build an interrupt frame. The form of the fake interrupt stack + on the Renesas RX should look like the following after it is built: + + Stack Top: 1 Interrupt stack frame type + ACC0 + ACC1 + R6 + R7 + R8 + R9 + R10 + R11 + R12 + R13 + FPSW + R14 + R15 + R3 + R4 + R5 + R1 + R2 + PC + PSW + Stack Bottom: (higher memory address) */ + + MOV.L 16[R1],R3 // Pickup end of stack area + BCLR #0, R3 // mask for 4-byte alignment + BCLR #1, R3 + + /* Build the stack frame. */ + + MOV.L #30000h, R4 // make initial PSW (user stack, enable interrupts) + BTST #0,152[R1] // in user mode? + BMC #20,R4 // if user mode, set mode bit of initial PSW + MOV.L R4, [-R3] // initial PSW + MOV.L R2, [-R3] // initial PC + + MOV.L 8[R1], R4 // Pickup thread entry info pointer, which is in the stack pointer position of the thread control block. + // It was setup in the txm_module_manager_thread_create function. It will be overwritten later in this + // function with the actual, initial stack pointer. + MOV.L R4,[-R3] // initial R2, which is the module entry information. + MOV.L R1,[-R3] // initial R1, which is the thread control block. + MOV.L #0, R2 // Clear following registers to 0 + MOV.L R2,[-R3] // initial R5 + MOV.L R2,[-R3] // initial R4 + MOV.L R2,[-R3] // initial R3 + MOV.L R2,[-R3] // initial R15 + MOV.L R2,[-R3] // initial R14 + MVFC FPSW, R2 // pickup FPSW + MOV.L R2, [-R3] // initial FPSW + MOV.L 12[R4], R2 // Pickup code base register from the module information + MOV.L R2,[-R3] // initial R13 + MOV.L 8[R4], R2 // Pickup data base register from the module information + MOV.L R2,[-R3] // initial R12 + MOV.L #0, R4 // Clear following registers to 0 + MOV.L R4,[-R3] // initial R11 + MOV.L R4,[-R3] // initial R10 + MOV.L R4,[-R3] // initial R9 + MOV.L R4,[-R3] // initial R8 + MOV.L R4,[-R3] // initial R7 + MOV.L R4,[-R3] // initial R6 + MOV.L R4,[-R3] // Accumulator 1 + MOV.L R4,[-R3] + MOV.L R4,[-R3] + MOV.L R4,[-R3] // Accumulator 0 + MOV.L R4,[-R3] + MOV.L R4,[-R3] + MOV.L #1, R4 // Make this an interrupt stack frame + MOV.L R4,[-R3] + + /* Save stack pointer. */ + // thread_ptr -> tx_thread_stack_ptr = R3; + + MOV.L R3, 8[R1] // store initial SP in thread control block + RTS +// } + END |