Added a QEMU module execution harness for the Cortex-M3 and M4 ports (#821)dev

No Cortex-M module port ran in CI. gcc_check compiles each port's module manager
sources and links nothing that loads a module, and the host tests under
test/tx/module_manager compile a few portable sources against stubs. A module's
start-up, its kernel calls through the supervisor call, the MPU programming on context
switches and the fault path that terminates a misbehaving module were exercised only
on the Cortex-R52 FVP.

test/tx/cmake/module_qemu is a stand-alone CMake project, like test/tx/cmake/riscv, that
builds the kernel and Module Manager with a module port's headers, builds test modules
position-independent with the port's module linker script, embeds their raw images in
manager images, and registers each image with CTest. A Python runner starts it on
QEMU's MPS2 board for the core, mps2-an385 for cortex_m3 and mps2-an386 for cortex_m4
built for its FPU with the hard-float ABI, and judges the result line the image prints
over semihosting and the exit status it sets. Three images per port: a protected module
loaded, started, exercising queues, semaphores, a worker thread and the timer, stopped
and unloaded twice with its memory returned; the same module faulting on a read of
kernel memory, reported to the fault notification with its module, thread and address
and terminated, then stopped and unloaded; and the module built privileged and
unprotected, whose identical read succeeds. The fault image is also the check that
QEMU's MPU enforces at all. The new module_qemu workflow runs both ports on changes to
common/, common_modules/, the two module ports and the harness, installing QEMU from
the Ubuntu archive through the bounded apt helpers in scripts/tx_ci_common.sh.

Both ports pass 3/3 on QEMU 8.2.2 with Arm GNU 14.3.rel1, using the workflow's commands,
with zero compiler warnings; configure, build and run take 9 seconds for both. The AI
disclosure check passes. The workflow itself has not run on GitHub yet.

Assisted-by: Claude Code (Opus 5.5) <[email protected]>

1 files changed, 77 insertions, 0 deletions

diff --git a/test/tx/cmake/module_qemu/src/manager.ld b/test/tx/cmake/module_qemu/src/manager.ld
new file mode 100644
index 00000000..9f6580e9
--- /dev/null
+++ b/test/tx/cmake/module_qemu/src/manager.ld
@@ -0,0 +1,77 @@
+/***************************************************************************
+ * Copyright (c) 2026 Eclipse ThreadX contributors
+ *
+ * This program and the accompanying materials are made available under the
+ * terms of the MIT License which is available at
+ * https://opensource.org/licenses/MIT.
+ *
+ * AI Disclosure: This file was largely AI-generated by Claude Code (Opus 5.5).
+ * The AI-generated portions may be considered public domain (CC0-1.0)
+ * and not subject to the project's licence. The human contributor has
+ * reviewed and verified that the code is correct.
+ *
+ * SPDX-License-Identifier: MIT and CC0-1.0
+ **************************************************************************/
+
+/* Module manager image for QEMU's MPS2 AN385 and AN386.  Code, read-only data
+   and the embedded module images go in the 4 MB SSRAM1 at address 0, which the
+   board boots from; data, the main stack and the memory ThreadX hands out go
+   in the first megabyte of SSRAM2 at 0x20000000.  The megabyte above that holds
+   the area the manager shares with its modules (module_shared.h), and nothing
+   the linker places reaches it.  */
+
+MEMORY
+{
+    CODE (rx)  : ORIGIN = 0x00000000, LENGTH = 0x00400000
+    RAM  (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00100000
+}
+
+ENTRY(reset_handler)
+
+SECTIONS
+{
+    .vectors :
+    {
+        KEEP(*(.vectors))
+    } > CODE
+
+    .text :
+    {
+        *(.text .text.*)
+        *(.rodata .rodata.*)
+        . = ALIGN(4);
+    } > CODE
+
+    .ARM.exidx :
+    {
+        *(.ARM.exidx*)
+    } > CODE
+
+    __data_load_start__ = LOADADDR(.data);
+
+    .data : ALIGN(4)
+    {
+        __data_start__ = .;
+        *(.data .data.*)
+        . = ALIGN(4);
+        __data_end__ = .;
+    } > RAM AT > CODE
+
+    .bss (NOLOAD) : ALIGN(4)
+    {
+        __bss_start__ = .;
+        *(.bss .bss.*)
+        *(COMMON)
+        . = ALIGN(4);
+        __bss_end__ = .;
+    } > RAM
+
+    .stack (NOLOAD) : ALIGN(8)
+    {
+        __stack_start__ = .;
+        . = . + 2048;
+        __stack_end__ = .;
+    } > RAM
+
+    __RAM_segment_used_end__ = .;
+}