Added a QEMU module execution harness for the Cortex-M3 and M4 ports (#821)dev

No Cortex-M module port ran in CI. gcc_check compiles each port's module manager
sources and links nothing that loads a module, and the host tests under
test/tx/module_manager compile a few portable sources against stubs. A module's
start-up, its kernel calls through the supervisor call, the MPU programming on context
switches and the fault path that terminates a misbehaving module were exercised only
on the Cortex-R52 FVP.

test/tx/cmake/module_qemu is a stand-alone CMake project, like test/tx/cmake/riscv, that
builds the kernel and Module Manager with a module port's headers, builds test modules
position-independent with the port's module linker script, embeds their raw images in
manager images, and registers each image with CTest. A Python runner starts it on
QEMU's MPS2 board for the core, mps2-an385 for cortex_m3 and mps2-an386 for cortex_m4
built for its FPU with the hard-float ABI, and judges the result line the image prints
over semihosting and the exit status it sets. Three images per port: a protected module
loaded, started, exercising queues, semaphores, a worker thread and the timer, stopped
and unloaded twice with its memory returned; the same module faulting on a read of
kernel memory, reported to the fault notification with its module, thread and address
and terminated, then stopped and unloaded; and the module built privileged and
unprotected, whose identical read succeeds. The fault image is also the check that
QEMU's MPU enforces at all. The new module_qemu workflow runs both ports on changes to
common/, common_modules/, the two module ports and the harness, installing QEMU from
the Ubuntu archive through the bounded apt helpers in scripts/tx_ci_common.sh.

Both ports pass 3/3 on QEMU 8.2.2 with Arm GNU 14.3.rel1, using the workflow's commands,
with zero compiler warnings; configure, build and run take 9 seconds for both. The AI
disclosure check passes. The workflow itself has not run on GitHub yet.

Assisted-by: Claude Code (Opus 5.5) <[email protected]>

1 files changed, 93 insertions, 0 deletions

diff --git a/test/tx/cmake/module_qemu/src/startup.S b/test/tx/cmake/module_qemu/src/startup.S
new file mode 100644
index 00000000..f2f8442b
--- /dev/null
+++ b/test/tx/cmake/module_qemu/src/startup.S
@@ -0,0 +1,93 @@
+/***************************************************************************
+ * Copyright (c) 2026 Eclipse ThreadX contributors
+ *
+ * This program and the accompanying materials are made available under the
+ * terms of the MIT License which is available at
+ * https://opensource.org/licenses/MIT.
+ *
+ * AI Disclosure: This file was largely AI-generated by Claude Code (Opus 5.5).
+ * The AI-generated portions may be considered public domain (CC0-1.0)
+ * and not subject to the project's licence. The human contributor has
+ * reviewed and verified that the code is correct.
+ *
+ * SPDX-License-Identifier: MIT and CC0-1.0
+ **************************************************************************/
+
+@ Vector table and reset handler for the module execution harness on QEMU's
+@ MPS2 boards.  The fault vectors go to the module port's handlers, which is
+@ the point: a module's MemManage fault has to reach the Module Manager for the
+@ fault-notification test to mean anything.  HardFault is never expected and
+@ goes to the harness, which reports it and fails the image.
+
+    .syntax unified
+    .thumb
+
+    .section .vectors, "a"
+    .align  2
+    .global _vectors
+_vectors:
+    .word   __stack_end__                   @ Initial main stack pointer
+    .word   reset_handler                   @ Reset
+    .word   harness_unexpected_exception    @ NMI
+    .word   harness_hard_fault              @ HardFault
+    .word   MemManage_Handler               @ MemManage, module port
+    .word   BusFault_Handler                @ BusFault, module port
+    .word   UsageFault_Handler              @ UsageFault, module port
+    .word   0
+    .word   0
+    .word   0
+    .word   0
+    .word   __tx_SVCallHandler              @ SVCall, module port
+    .word   harness_unexpected_exception    @ Debug monitor
+    .word   0
+    .word   __tx_PendSVHandler              @ PendSV, module port
+    .word   __tx_SysTickHandler             @ SysTick, tx_initialize_low_level.S
+    .rept   32
+    .word   harness_unexpected_exception    @ External interrupts, none enabled
+    .endr
+
+    .section .text.reset_handler, "ax"
+    .align  2
+    .global reset_handler
+    .thumb_func
+reset_handler:
+
+    @ Copy initialised data from its load address to RAM.
+
+    LDR     r0, =__data_load_start__
+    LDR     r1, =__data_start__
+    LDR     r2, =__data_end__
+copy_data:
+    CMP     r1, r2
+    BHS     copy_data_done
+    LDR     r3, [r0], #4
+    STR     r3, [r1], #4
+    B       copy_data
+copy_data_done:
+
+    @ Zero the uninitialised data.
+
+    LDR     r1, =__bss_start__
+    LDR     r2, =__bss_end__
+    MOV     r3, #0
+zero_bss:
+    CMP     r1, r2
+    BHS     zero_bss_done
+    STR     r3, [r1], #4
+    B       zero_bss
+zero_bss_done:
+
+#ifdef __ARM_FP
+    @ Grant full access to CP10 and CP11 before anything touches the FPU.
+
+    LDR     r0, =0xE000ED88                 @ CPACR
+    LDR     r1, [r0]
+    ORR     r1, r1, #(0xF << 20)
+    STR     r1, [r0]
+    DSB
+    ISB
+#endif
+
+    BL      main
+reset_hang:
+    B       reset_hang