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/***************************************************************************
* Copyright (c) 2026 Eclipse ThreadX contributors
*
* This program and the accompanying materials are made available under the
* terms of the MIT License which is available at
* https://opensource.org/licenses/MIT.
*
* AI Disclosure: This file was largely AI-generated by Claude Code (Opus 5.5).
* The AI-generated portions may be considered public domain (CC0-1.0)
* and not subject to the project's licence. The human contributor has
* reviewed and verified that the code is correct.
*
* SPDX-License-Identifier: MIT and CC0-1.0
**************************************************************************/
@ Vector table and reset handler for the module execution harness on QEMU's
@ MPS2 boards. The fault vectors go to the module port's handlers, which is
@ the point: a module's MemManage fault has to reach the Module Manager for the
@ fault-notification test to mean anything. HardFault is never expected and
@ goes to the harness, which reports it and fails the image.
.syntax unified
.thumb
.section .vectors, "a"
.align 2
.global _vectors
_vectors:
.word __stack_end__ @ Initial main stack pointer
.word reset_handler @ Reset
.word harness_unexpected_exception @ NMI
.word harness_hard_fault @ HardFault
.word MemManage_Handler @ MemManage, module port
.word BusFault_Handler @ BusFault, module port
.word UsageFault_Handler @ UsageFault, module port
.word 0
.word 0
.word 0
.word 0
.word __tx_SVCallHandler @ SVCall, module port
.word harness_unexpected_exception @ Debug monitor
.word 0
.word __tx_PendSVHandler @ PendSV, module port
.word __tx_SysTickHandler @ SysTick, tx_initialize_low_level.S
.rept 32
.word harness_unexpected_exception @ External interrupts, none enabled
.endr
.section .text.reset_handler, "ax"
.align 2
.global reset_handler
.thumb_func
reset_handler:
@ Copy initialised data from its load address to RAM.
LDR r0, =__data_load_start__
LDR r1, =__data_start__
LDR r2, =__data_end__
copy_data:
CMP r1, r2
BHS copy_data_done
LDR r3, [r0], #4
STR r3, [r1], #4
B copy_data
copy_data_done:
@ Zero the uninitialised data.
LDR r1, =__bss_start__
LDR r2, =__bss_end__
MOV r3, #0
zero_bss:
CMP r1, r2
BHS zero_bss_done
STR r3, [r1], #4
B zero_bss
zero_bss_done:
#ifdef __ARM_FP
@ Grant full access to CP10 and CP11 before anything touches the FPU.
LDR r0, =0xE000ED88 @ CPACR
LDR r1, [r0]
ORR r1, r1, #(0xF << 20)
STR r1, [r0]
DSB
ISB
#endif
BL main
reset_hang:
B reset_hang
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