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-rw-r--r--ports/arm11/iar/example_build/cstartup.s10
-rw-r--r--ports/arm11/iar/example_build/sample_threadx.c46
-rw-r--r--ports/arm11/iar/example_build/tx_initialize_low_level.s128
3 files changed, 89 insertions, 95 deletions
diff --git a/ports/arm11/iar/example_build/cstartup.s b/ports/arm11/iar/example_build/cstartup.s
index b95efc0e..3da2b79d 100644
--- a/ports/arm11/iar/example_build/cstartup.s
+++ b/ports/arm11/iar/example_build/cstartup.s
@@ -1,7 +1,7 @@
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
-;; Part one of the system initialization code,
+;; Part one of the system initialization code,
;; contains low-level
;; initialization.
;;
@@ -71,13 +71,13 @@ FIQ_Addr: DCD __tx_fiq_handler
SECTION .text:CODE:NOROOT(2)
-; PUBLIC ?cstartup
+; PUBLIC ?cstartup
EXTERN ?main
REQUIRE __vector
- ARM
-
-__iar_program_start:
+ ARM
+
+__iar_program_start:
?cstartup:
;
diff --git a/ports/arm11/iar/example_build/sample_threadx.c b/ports/arm11/iar/example_build/sample_threadx.c
index a57d908d..f9d0e94a 100644
--- a/ports/arm11/iar/example_build/sample_threadx.c
+++ b/ports/arm11/iar/example_build/sample_threadx.c
@@ -1,5 +1,5 @@
/* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight
- threads of different priorities, using a message queue, semaphore, mutex, event flags group,
+ threads of different priorities, using a message queue, semaphore, mutex, event flags group,
byte pool, and block pool. */
#include "tx_api.h"
@@ -85,42 +85,42 @@ CHAR *pointer;
tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
/* Create the main thread. */
- tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0,
- pointer, DEMO_STACK_SIZE,
+ tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0,
+ pointer, DEMO_STACK_SIZE,
1, 1, TX_NO_TIME_SLICE, TX_AUTO_START);
/* Allocate the stack for thread 1. */
tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
- /* Create threads 1 and 2. These threads pass information through a ThreadX
+ /* Create threads 1 and 2. These threads pass information through a ThreadX
message queue. It is also interesting to note that these threads have a time
slice. */
- tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1,
- pointer, DEMO_STACK_SIZE,
+ tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1,
+ pointer, DEMO_STACK_SIZE,
16, 16, 4, TX_AUTO_START);
/* Allocate the stack for thread 2. */
tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
- tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2,
- pointer, DEMO_STACK_SIZE,
+ tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2,
+ pointer, DEMO_STACK_SIZE,
16, 16, 4, TX_AUTO_START);
/* Allocate the stack for thread 3. */
tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
- /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore.
+ /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore.
An interesting thing here is that both threads share the same instruction area. */
- tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3,
- pointer, DEMO_STACK_SIZE,
+ tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3,
+ pointer, DEMO_STACK_SIZE,
8, 8, TX_NO_TIME_SLICE, TX_AUTO_START);
/* Allocate the stack for thread 4. */
tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
- tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4,
- pointer, DEMO_STACK_SIZE,
+ tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4,
+ pointer, DEMO_STACK_SIZE,
8, 8, TX_NO_TIME_SLICE, TX_AUTO_START);
/* Allocate the stack for thread 5. */
@@ -128,23 +128,23 @@ CHAR *pointer;
/* Create thread 5. This thread simply pends on an event flag which will be set
by thread_0. */
- tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5,
- pointer, DEMO_STACK_SIZE,
+ tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5,
+ pointer, DEMO_STACK_SIZE,
4, 4, TX_NO_TIME_SLICE, TX_AUTO_START);
/* Allocate the stack for thread 6. */
tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
/* Create threads 6 and 7. These threads compete for a ThreadX mutex. */
- tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6,
- pointer, DEMO_STACK_SIZE,
+ tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6,
+ pointer, DEMO_STACK_SIZE,
8, 8, TX_NO_TIME_SLICE, TX_AUTO_START);
/* Allocate the stack for thread 7. */
tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
- tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7,
- pointer, DEMO_STACK_SIZE,
+ tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7,
+ pointer, DEMO_STACK_SIZE,
8, 8, TX_NO_TIME_SLICE, TX_AUTO_START);
/* Allocate the message queue. */
@@ -247,11 +247,11 @@ UINT status;
/* Retrieve a message from the queue. */
status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER);
- /* Check completion status and make sure the message is what we
+ /* Check completion status and make sure the message is what we
expected. */
if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received))
break;
-
+
/* Otherwise, all is okay. Increment the received message count. */
thread_2_messages_received++;
}
@@ -310,7 +310,7 @@ ULONG actual_flags;
thread_5_counter++;
/* Wait for event flag 0. */
- status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR,
+ status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR,
&actual_flags, TX_WAIT_FOREVER);
/* Check status. */
@@ -363,7 +363,7 @@ UINT status;
if (status != TX_SUCCESS)
break;
- /* Release the mutex again. This will actually
+ /* Release the mutex again. This will actually
release ownership since it was obtained twice. */
status = tx_mutex_put(&mutex_0);
diff --git a/ports/arm11/iar/example_build/tx_initialize_low_level.s b/ports/arm11/iar/example_build/tx_initialize_low_level.s
index 7242cfe4..61d554bc 100644
--- a/ports/arm11/iar/example_build/tx_initialize_low_level.s
+++ b/ports/arm11/iar/example_build/tx_initialize_low_level.s
@@ -1,18 +1,18 @@
;/***************************************************************************
-; * Copyright (c) 2024 Microsoft Corporation
-; *
+; * Copyright (c) 2024 Microsoft Corporation
+; *
; * This program and the accompanying materials are made available under the
; * terms of the MIT License which is available at
; * https://opensource.org/licenses/MIT.
-; *
+; *
; * SPDX-License-Identifier: MIT
; **************************************************************************/
;
;
;/**************************************************************************/
;/**************************************************************************/
-;/** */
-;/** ThreadX Component */
+;/** */
+;/** ThreadX Component */
;/** */
;/** Initialize */
;/** */
@@ -62,7 +62,7 @@ SYS_MODE DEFINE 0xDF ; Disable irq,fiq SYS mode
;
;
;
-;/* Define the FREE_MEM segment that will specify where free memory is
+;/* Define the FREE_MEM segment that will specify where free memory is
; defined. This must also be located in at the end of other RAM segments
; in the linker control file. The value of this segment is what is passed
; to tx_application_define. */
@@ -75,47 +75,41 @@ __tx_free_memory_start
;
;
;
-;/**************************************************************************/
-;/* */
-;/* FUNCTION RELEASE */
-;/* */
-;/* _tx_initialize_low_level ARM11/IAR */
-;/* 6.1 */
-;/* AUTHOR */
-;/* */
-;/* William E. Lamie, Microsoft Corporation */
-;/* */
-;/* DESCRIPTION */
-;/* */
-;/* This function is responsible for any low-level processor */
-;/* initialization, including setting up interrupt vectors, setting */
-;/* up a periodic timer interrupt source, saving the system stack */
-;/* pointer for use in ISR processing later, and finding the first */
-;/* available RAM memory address for tx_application_define. */
-;/* */
-;/* INPUT */
-;/* */
-;/* None */
-;/* */
-;/* OUTPUT */
-;/* */
-;/* None */
-;/* */
-;/* CALLS */
-;/* */
-;/* None */
-;/* */
-;/* CALLED BY */
-;/* */
-;/* _tx_initialize_kernel_enter ThreadX entry function */
-;/* */
-;/* RELEASE HISTORY */
-;/* */
-;/* DATE NAME DESCRIPTION */
-;/* */
-;/* 09-30-2020 William E. Lamie Initial Version 6.1 */
-;/* */
-;/**************************************************************************/
+;/**************************************************************************/
+;/* */
+;/* FUNCTION RELEASE */
+;/* */
+;/* _tx_initialize_low_level ARM11/IAR */
+;/* 6.1 */
+;/* AUTHOR */
+;/* */
+;/* William E. Lamie, Microsoft Corporation */
+;/* */
+;/* DESCRIPTION */
+;/* */
+;/* This function is responsible for any low-level processor */
+;/* initialization, including setting up interrupt vectors, setting */
+;/* up a periodic timer interrupt source, saving the system stack */
+;/* pointer for use in ISR processing later, and finding the first */
+;/* available RAM memory address for tx_application_define. */
+;/* */
+;/* INPUT */
+;/* */
+;/* None */
+;/* */
+;/* OUTPUT */
+;/* */
+;/* None */
+;/* */
+;/* CALLS */
+;/* */
+;/* None */
+;/* */
+;/* CALLED BY */
+;/* */
+;/* _tx_initialize_kernel_enter ThreadX entry function */
+;/* */
+;/**************************************************************************/
;VOID _tx_initialize_low_level(VOID)
;{
RSEG .text:CODE:NOROOT(2)
@@ -146,7 +140,7 @@ _tx_initialize_low_level
;
LDR r2, =_tx_initialize_unused_memory ; Pickup unused memory ptr address
STR r0, [r2, #0] ; Save first free memory address
-;
+;
; /* Setup Timer for periodic interrupts. */
;
; /* Done, return to caller. */
@@ -188,7 +182,7 @@ __tx_reserved_handler
RSEG .text:CODE:NOROOT(2)
PUBLIC __tx_irq_handler
RSEG .text:CODE:NOROOT(2)
- PUBLIC __tx_irq_processing_return
+ PUBLIC __tx_irq_processing_return
__tx_irq_handler
;
; /* Jump to context save to save system context. */
@@ -196,17 +190,17 @@ __tx_irq_handler
__tx_irq_processing_return
;
; /* At this point execution is still in the IRQ mode. The CPSR, point of
-; interrupt, and all C scratch registers are available for use. In
+; interrupt, and all C scratch registers are available for use. In
; addition, IRQ interrupts may be re-enabled - with certain restrictions -
; if nested IRQ interrupts are desired. Interrupts may be re-enabled over
-; small code sequences where lr is saved before enabling interrupts and
+; small code sequences where lr is saved before enabling interrupts and
; restored after interrupts are again disabled. */
;
-; /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start
+; /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start
; from IRQ mode with interrupts disabled. This routine switches to the
-; system mode and returns with IRQ interrupts enabled.
-;
-; NOTE: It is very important to ensure all IRQ interrupts are cleared
+; system mode and returns with IRQ interrupts enabled.
+;
+; NOTE: It is very important to ensure all IRQ interrupts are cleared
; prior to enabling nested IRQ interrupts. */
#ifdef TX_ENABLE_IRQ_NESTING
BL _tx_thread_irq_nesting_start
@@ -221,7 +215,7 @@ __tx_irq_processing_return
; /* Application IRQ handlers can be called here! */
;
; /* If interrupt nesting was started earlier, the end of interrupt nesting
-; service must be called before returning to _tx_thread_context_restore.
+; service must be called before returning to _tx_thread_context_restore.
; This routine returns in processing in IRQ mode with interrupts disabled. */
#ifdef TX_ENABLE_IRQ_NESTING
BL _tx_thread_irq_nesting_end
@@ -240,22 +234,22 @@ __tx_irq_processing_return
; /* Jump to context save to save system context. */
; STMDB sp!, {r0-r3} ; Save some scratch registers
; MRS r0, SPSR ; Pickup saved SPSR
-; SUB lr, lr, #4 ; Adjust point of interrupt
+; SUB lr, lr, #4 ; Adjust point of interrupt
; STMDB sp!, {r0, r10, r12, lr} ; Store other registers
; BL _tx_thread_vectored_context_save
;
; /* At this point execution is still in the IRQ mode. The CPSR, point of
-; interrupt, and all C scratch registers are available for use. In
+; interrupt, and all C scratch registers are available for use. In
; addition, IRQ interrupts may be re-enabled - with certain restrictions -
; if nested IRQ interrupts are desired. Interrupts may be re-enabled over
-; small code sequences where lr is saved before enabling interrupts and
+; small code sequences where lr is saved before enabling interrupts and
; restored after interrupts are again disabled. */
;
-; /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start
+; /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start
; from IRQ mode with interrupts disabled. This routine switches to the
-; system mode and returns with IRQ interrupts enabled.
-;
-; NOTE: It is very important to ensure all IRQ interrupts are cleared
+; system mode and returns with IRQ interrupts enabled.
+;
+; NOTE: It is very important to ensure all IRQ interrupts are cleared
; prior to enabling nested IRQ interrupts. */
;#ifdef TX_ENABLE_IRQ_NESTING
; BL _tx_thread_irq_nesting_start
@@ -264,7 +258,7 @@ __tx_irq_processing_return
; /* Application IRQ handler is called here! */
;
; /* If interrupt nesting was started earlier, the end of interrupt nesting
-; service must be called before returning to _tx_thread_context_restore.
+; service must be called before returning to _tx_thread_context_restore.
; This routine returns in processing in IRQ mode with interrupts disabled. */
;#ifdef TX_ENABLE_IRQ_NESTING
; BL _tx_thread_irq_nesting_end
@@ -288,11 +282,11 @@ __tx_fiq_processing_return
; /* At this point execution is still in the FIQ mode. The CPSR, point of
; interrupt, and all C scratch registers are available for use. */
;
-; /* Interrupt nesting is allowed after calling _tx_thread_fiq_nesting_start
+; /* Interrupt nesting is allowed after calling _tx_thread_fiq_nesting_start
; from FIQ mode with interrupts disabled. This routine switches to the
-; system mode and returns with FIQ interrupts enabled.
+; system mode and returns with FIQ interrupts enabled.
;
-; NOTE: It is very important to ensure all FIQ interrupts are cleared
+; NOTE: It is very important to ensure all FIQ interrupts are cleared
; prior to enabling nested FIQ interrupts. */
#ifdef TX_ENABLE_FIQ_NESTING
BL _tx_thread_fiq_nesting_start
generated by cgit v1.3.1 (git 2.54.0) at 2026-08-13 06:47:48 +0000