diff options
Diffstat (limited to 'ports/cortex_m0/ac5')
| -rw-r--r-- | ports/cortex_m0/ac5/example_build/tx_initialize_low_level.s | 24 | ||||
| -rw-r--r-- | ports/cortex_m0/ac5/inc/tx_port.h | 2 |
2 files changed, 3 insertions, 23 deletions
diff --git a/ports/cortex_m0/ac5/example_build/tx_initialize_low_level.s b/ports/cortex_m0/ac5/example_build/tx_initialize_low_level.s index 3a585477..8f2cbaf1 100644 --- a/ports/cortex_m0/ac5/example_build/tx_initialize_low_level.s +++ b/ports/cortex_m0/ac5/example_build/tx_initialize_low_level.s @@ -1,5 +1,6 @@ ;/*************************************************************************** ; * Copyright (c) 2024 Microsoft Corporation +; * Copyright (c) 2026-present Eclipse ThreadX contributors ; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at @@ -7,6 +8,7 @@ ; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ +; Portions of this file were generated with AI assistance. ; ; ;/**************************************************************************/ @@ -20,7 +22,6 @@ ;/**************************************************************************/ ; ; - IMPORT _tx_thread_system_stack_ptr IMPORT _tx_initialize_unused_memory IMPORT _tx_timer_interrupt IMPORT __main @@ -137,12 +138,6 @@ _tx_initialize_low_level ADDS r1, r1, #4 ; STR r1, [r0] ; Setup first unused memory pointer ; -; /* Setup Vector Table Offset Register. */ -; - LDR r0, =0xE000ED08 ; Build address of NVIC registers - LDR r1, =__tx_vectors ; Pickup address of vector table - STR r1, [r0] ; Set vector table address -; ; /* Enable the cycle count register. */ ; ; LDR r0, =0xE0001000 ; Build address of DWT register @@ -151,21 +146,6 @@ _tx_initialize_low_level ; ORRS r1, r1, r2 ; Set the CYCCNTENA bit ; STR r1, [r0] ; Enable the cycle count register ; -; /* Setup Vector Table Offset Register. */ -; - LDR r0, =0xE000E000 ; Build address of NVIC registers - LDR r2, =0xD08 ; Offset to vector base register - ADD r0, r0, r2 ; Build vector base register - LDR r1, =__tx_vectors ; Pickup address of vector table - STR r1, [r0] ; Set vector table address -; -; /* Set system stack pointer from vector value. */ -; - LDR r0, =_tx_thread_system_stack_ptr ; Build address of system stack pointer - LDR r1, =__tx_vectors ; Pickup address of vector table - LDR r1, [r1] ; Pickup reset stack pointer - STR r1, [r0] ; Save system stack pointer -; ; /* Configure SysTick. */ ; LDR r0, =0xE000E000 ; Build address of NVIC registers diff --git a/ports/cortex_m0/ac5/inc/tx_port.h b/ports/cortex_m0/ac5/inc/tx_port.h index 5ddf74bb..53018a6f 100644 --- a/ports/cortex_m0/ac5/inc/tx_port.h +++ b/ports/cortex_m0/ac5/inc/tx_port.h @@ -312,7 +312,7 @@ unsigned int was_masked; #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M0/AC5 Version 6.5.1.202602a *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M0/AC5 Version 6.5.2.202603 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; |