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-rw-r--r--ports/cortex_m0/ac6/src/tx_thread_system_return.S3
1 files changed, 3 insertions, 0 deletions
diff --git a/ports/cortex_m0/ac6/src/tx_thread_system_return.S b/ports/cortex_m0/ac6/src/tx_thread_system_return.S
index fc62c0c6..bd7a23f3 100644
--- a/ports/cortex_m0/ac6/src/tx_thread_system_return.S
+++ b/ports/cortex_m0/ac6/src/tx_thread_system_return.S
@@ -72,12 +72,15 @@ _tx_thread_system_return:
LDR r0, =0x10000000 @ Load PENDSVSET bit
LDR r1, =0xE000ED04 @ Load NVIC base
STR r0, [r1] @ Set PENDSVBIT in ICSR
+ DSB #0xF @ Ensure memory access is complete
+ ISB #0xF @ Flush pipeline
MRS r0, IPSR @ Pickup IPSR
CMP r0, #0 @ Is it a thread returning?
BNE _isr_context @ If ISR, skip interrupt enable
MRS r1, PRIMASK @ Thread context returning, pickup PRIMASK
CPSIE i @ Enable interrupts
MSR PRIMASK, r1 @ Restore original interrupt posture
+ ISB #0xF @ Flush pipeline
_isr_context:
BX lr @ Return to caller
@/* } */