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-rw-r--r--ports/cortex_m0/ac5/src/tx_thread_schedule.s25
-rw-r--r--ports/cortex_m0/ac6/src/tx_thread_schedule.S25
-rwxr-xr-x[-rw-r--r--]ports/cortex_m0/gnu/CMakeLists.txt0
-rw-r--r--[-rwxr-xr-x]ports/cortex_m0/gnu/src/tx_thread_context_restore.S0
-rw-r--r--[-rwxr-xr-x]ports/cortex_m0/gnu/src/tx_thread_context_save.S0
-rw-r--r--[-rwxr-xr-x]ports/cortex_m0/gnu/src/tx_thread_interrupt_control.S0
-rw-r--r--[-rwxr-xr-x]ports/cortex_m0/gnu/src/tx_thread_interrupt_disable.S0
-rw-r--r--[-rwxr-xr-x]ports/cortex_m0/gnu/src/tx_thread_interrupt_restore.S0
-rw-r--r--[-rwxr-xr-x]ports/cortex_m0/gnu/src/tx_thread_schedule.S27
-rw-r--r--[-rwxr-xr-x]ports/cortex_m0/gnu/src/tx_thread_stack_build.S0
-rw-r--r--[-rwxr-xr-x]ports/cortex_m0/gnu/src/tx_thread_system_return.S0
-rw-r--r--[-rwxr-xr-x]ports/cortex_m0/gnu/src/tx_timer_interrupt.S0
-rw-r--r--ports/cortex_m0/iar/src/tx_thread_schedule.s25
-rw-r--r--ports/cortex_m0/keil/src/tx_thread_schedule.s27
14 files changed, 116 insertions, 13 deletions
diff --git a/ports/cortex_m0/ac5/src/tx_thread_schedule.s b/ports/cortex_m0/ac5/src/tx_thread_schedule.s
index d30a2fb6..18b8d6ab 100644
--- a/ports/cortex_m0/ac5/src/tx_thread_schedule.s
+++ b/ports/cortex_m0/ac5/src/tx_thread_schedule.s
@@ -30,6 +30,10 @@
IMPORT _tx_execution_thread_enter
IMPORT _tx_execution_thread_exit
ENDIF
+ IF :DEF:TX_LOW_POWER
+ IMPORT tx_low_power_enter
+ IMPORT tx_low_power_exit
+ ENDIF
;
;
AREA ||.text||, CODE, READONLY
@@ -39,7 +43,7 @@
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_schedule Cortex-M0/AC5 */
-;/* 6.1 */
+;/* 6.1.5 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
@@ -72,7 +76,10 @@
;/* */
;/* DATE NAME DESCRIPTION */
;/* */
-;/* 09-30-2020 William E. Lamie Initial Version 6.1 */
+;/* 09-30-2020 William E. Lamie Initial Version 6.1 */
+;/* 03-02-2021 Scott Larson Modified comment(s), add */
+;/* low power code, */
+;/* resulting in version 6.1.5 */
;/* */
;/**************************************************************************/
;VOID _tx_thread_schedule(VOID)
@@ -240,11 +247,23 @@ __tx_ts_wait
STR r1, [r0] ; Store it in the current pointer
CMP r1, #0 ; If non-NULL, a new thread is ready!
BNE __tx_ts_ready ;
- IF :DEF:TX_ENABLE_WFI
+ IF:DEF:TX_LOW_POWER
+ PUSH {r0-r3}
+ BL tx_low_power_enter ; Possibly enter low power mode
+ POP {r0-r3}
+ ENDIF
+
+ IF:DEF:TX_ENABLE_WFI
DSB ; Ensure no outstanding memory transactions
WFI ; Wait for interrupt
ISB ; Ensure pipeline is flushed
ENDIF
+
+ IF:DEF:TX_LOW_POWER
+ PUSH {r0-r3}
+ BL tx_low_power_exit ; Exit low power mode
+ POP {r0-r3}
+ ENDIF
__tx_ts_ISB
CPSIE i ; Enable interrupts
B __tx_ts_wait ; Loop to continue waiting
diff --git a/ports/cortex_m0/ac6/src/tx_thread_schedule.S b/ports/cortex_m0/ac6/src/tx_thread_schedule.S
index 8563a92f..f1ee3a94 100644
--- a/ports/cortex_m0/ac6/src/tx_thread_schedule.S
+++ b/ports/cortex_m0/ac6/src/tx_thread_schedule.S
@@ -25,6 +25,10 @@
.global _tx_thread_execute_ptr
.global _tx_timer_time_slice
.global _tx_thread_system_stack_ptr
+#ifdef TX_LOW_POWER
+ .global tx_low_power_enter
+ .global tx_low_power_exit
+#endif
@
@
.text
@@ -35,7 +39,7 @@
@/* FUNCTION RELEASE */
@/* */
@/* _tx_thread_schedule Cortex-M0/AC6 */
-@/* 6.1 */
+@/* 6.1.5 */
@/* AUTHOR */
@/* */
@/* William E. Lamie, Microsoft Corporation */
@@ -68,7 +72,10 @@
@/* */
@/* DATE NAME DESCRIPTION */
@/* */
-@/* 09-30-2020 William E. Lamie Initial Version 6.1 */
+@/* 09-30-2020 William E. Lamie Initial Version 6.1 */
+@/* 03-02-2021 Scott Larson Modified comment(s), add */
+@/* low power code, */
+@/* resulting in version 6.1.5 */
@/* */
@/**************************************************************************/
@VOID _tx_thread_schedule(VOID)
@@ -244,11 +251,25 @@ __tx_ts_wait:
STR r1, [r0] @ Store it in the current pointer
CMP r1, #0 @ If non-NULL, a new thread is ready!
BNE __tx_ts_ready @
+
+#ifdef TX_LOW_POWER
+ PUSH {r0-r3}
+ BL tx_low_power_enter @ Possibly enter low power mode
+ POP {r0-r3}
+#endif
+
#ifdef TX_ENABLE_WFI
DSB @ Ensure no outstanding memory transactions
WFI @ Wait for interrupt
ISB @ Ensure pipeline is flushed
#endif
+
+#ifdef TX_LOW_POWER
+ PUSH {r0-r3}
+ BL tx_low_power_exit @ Exit low power mode
+ POP {r0-r3}
+#endif
+
CPSIE i @ Enable interrupts
B __tx_ts_wait @ Loop to continue waiting
@
diff --git a/ports/cortex_m0/gnu/CMakeLists.txt b/ports/cortex_m0/gnu/CMakeLists.txt
index 0e3cc8ec..0e3cc8ec 100644..100755
--- a/ports/cortex_m0/gnu/CMakeLists.txt
+++ b/ports/cortex_m0/gnu/CMakeLists.txt
diff --git a/ports/cortex_m0/gnu/src/tx_thread_context_restore.S b/ports/cortex_m0/gnu/src/tx_thread_context_restore.S
index fc453b61..fc453b61 100755..100644
--- a/ports/cortex_m0/gnu/src/tx_thread_context_restore.S
+++ b/ports/cortex_m0/gnu/src/tx_thread_context_restore.S
diff --git a/ports/cortex_m0/gnu/src/tx_thread_context_save.S b/ports/cortex_m0/gnu/src/tx_thread_context_save.S
index 710f5e26..710f5e26 100755..100644
--- a/ports/cortex_m0/gnu/src/tx_thread_context_save.S
+++ b/ports/cortex_m0/gnu/src/tx_thread_context_save.S
diff --git a/ports/cortex_m0/gnu/src/tx_thread_interrupt_control.S b/ports/cortex_m0/gnu/src/tx_thread_interrupt_control.S
index 4854108c..4854108c 100755..100644
--- a/ports/cortex_m0/gnu/src/tx_thread_interrupt_control.S
+++ b/ports/cortex_m0/gnu/src/tx_thread_interrupt_control.S
diff --git a/ports/cortex_m0/gnu/src/tx_thread_interrupt_disable.S b/ports/cortex_m0/gnu/src/tx_thread_interrupt_disable.S
index 96c9f60c..96c9f60c 100755..100644
--- a/ports/cortex_m0/gnu/src/tx_thread_interrupt_disable.S
+++ b/ports/cortex_m0/gnu/src/tx_thread_interrupt_disable.S
diff --git a/ports/cortex_m0/gnu/src/tx_thread_interrupt_restore.S b/ports/cortex_m0/gnu/src/tx_thread_interrupt_restore.S
index 9591c805..9591c805 100755..100644
--- a/ports/cortex_m0/gnu/src/tx_thread_interrupt_restore.S
+++ b/ports/cortex_m0/gnu/src/tx_thread_interrupt_restore.S
diff --git a/ports/cortex_m0/gnu/src/tx_thread_schedule.S b/ports/cortex_m0/gnu/src/tx_thread_schedule.S
index 788eddde..e110259b 100755..100644
--- a/ports/cortex_m0/gnu/src/tx_thread_schedule.S
+++ b/ports/cortex_m0/gnu/src/tx_thread_schedule.S
@@ -27,6 +27,10 @@
.global _tx_thread_system_stack_ptr
.global _tx_execution_thread_enter
.global _tx_execution_thread_exit
+#ifdef TX_LOW_POWER
+ .global tx_low_power_enter
+ .global tx_low_power_exit
+#endif
@
@
.text
@@ -37,7 +41,7 @@
@/* FUNCTION RELEASE */
@/* */
@/* _tx_thread_schedule Cortex-M0/GNU */
-@/* 6.1 */
+@/* 6.1.5 */
@/* AUTHOR */
@/* */
@/* William E. Lamie, Microsoft Corporation */
@@ -70,9 +74,12 @@
@/* */
@/* DATE NAME DESCRIPTION */
@/* */
-@/* 05-19-2020 William E. Lamie Initial Version 6.0 */
-@/* 09-30-2020 William E. Lamie Modified comment(s), */
+@/* 05-19-2020 William E. Lamie Initial Version 6.0 */
+@/* 09-30-2020 William E. Lamie Modified comment(s), */
@/* resulting in version 6.1 */
+@/* 03-02-2021 Scott Larson Modified comment(s), add */
+@/* low power code, */
+@/* resulting in version 6.1.5 */
@/* */
@/**************************************************************************/
@VOID _tx_thread_schedule(VOID)
@@ -248,11 +255,25 @@ __tx_ts_wait:
STR r1, [r0] @ Store it in the current pointer
CMP r1, #0 @ If non-NULL, a new thread is ready!
BNE __tx_ts_ready @
+
+#ifdef TX_LOW_POWER
+ PUSH {r0-r3}
+ BL tx_low_power_enter @ Possibly enter low power mode
+ POP {r0-r3}
+#endif
+
#ifdef TX_ENABLE_WFI
DSB @ Ensure no outstanding memory transactions
WFI @ Wait for interrupt
ISB @ Ensure pipeline is flushed
#endif
+
+#ifdef TX_LOW_POWER
+ PUSH {r0-r3}
+ BL tx_low_power_exit @ Exit low power mode
+ POP {r0-r3}
+#endif
+
CPSIE i @ Enable interrupts
B __tx_ts_wait @ Loop to continue waiting
@
diff --git a/ports/cortex_m0/gnu/src/tx_thread_stack_build.S b/ports/cortex_m0/gnu/src/tx_thread_stack_build.S
index 352739b1..352739b1 100755..100644
--- a/ports/cortex_m0/gnu/src/tx_thread_stack_build.S
+++ b/ports/cortex_m0/gnu/src/tx_thread_stack_build.S
diff --git a/ports/cortex_m0/gnu/src/tx_thread_system_return.S b/ports/cortex_m0/gnu/src/tx_thread_system_return.S
index a6a9109e..a6a9109e 100755..100644
--- a/ports/cortex_m0/gnu/src/tx_thread_system_return.S
+++ b/ports/cortex_m0/gnu/src/tx_thread_system_return.S
diff --git a/ports/cortex_m0/gnu/src/tx_timer_interrupt.S b/ports/cortex_m0/gnu/src/tx_timer_interrupt.S
index 9a61b0d3..9a61b0d3 100755..100644
--- a/ports/cortex_m0/gnu/src/tx_timer_interrupt.S
+++ b/ports/cortex_m0/gnu/src/tx_timer_interrupt.S
diff --git a/ports/cortex_m0/iar/src/tx_thread_schedule.s b/ports/cortex_m0/iar/src/tx_thread_schedule.s
index 02c60b6e..e4bac172 100644
--- a/ports/cortex_m0/iar/src/tx_thread_schedule.s
+++ b/ports/cortex_m0/iar/src/tx_thread_schedule.s
@@ -28,6 +28,10 @@
EXTERN _tx_thread_preempt_disable
EXTERN _tx_execution_thread_enter
EXTERN _tx_execution_thread_exit
+#ifdef TX_LOW_POWER
+ EXTERN tx_low_power_enter
+ EXTERN tx_low_power_exit
+#endif
;
;
SECTION `.text`:CODE:NOROOT(2)
@@ -37,7 +41,7 @@
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_schedule Cortex-M0/IAR */
-;/* 6.1 */
+;/* 6.1.5 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
@@ -70,7 +74,10 @@
;/* */
;/* DATE NAME DESCRIPTION */
;/* */
-;/* 09-30-2020 William E. Lamie Initial Version 6.1 */
+;/* 09-30-2020 William E. Lamie Initial Version 6.1 */
+;/* 03-02-2021 Scott Larson Modified comment(s), add */
+;/* low power code, */
+;/* resulting in version 6.1.5 */
;/* */
;/**************************************************************************/
;VOID _tx_thread_schedule(VOID)
@@ -238,11 +245,25 @@ __tx_ts_wait:
STR r1, [r0] ; Store it in the current pointer
CMP r1, #0 ; If non-NULL, a new thread is ready!
BNE __tx_ts_ready ;
+
+#ifdef TX_LOW_POWER
+ PUSH {r0-r3}
+ BL tx_low_power_enter ; Possibly enter low power mode
+ POP {r0-r3}
+#endif
+
#ifdef TX_ENABLE_WFI
DSB ; Ensure no outstanding memory transactions
WFI ; Wait for interrupt
ISB ; Ensure pipeline is flushed
#endif
+
+#ifdef TX_LOW_POWER
+ PUSH {r0-r3}
+ BL tx_low_power_exit ; Exit low power mode
+ POP {r0-r3}
+#endif
+
CPSIE i ; Enable interrupts
B __tx_ts_wait ; Loop to continue waiting
;
diff --git a/ports/cortex_m0/keil/src/tx_thread_schedule.s b/ports/cortex_m0/keil/src/tx_thread_schedule.s
index c1699d87..7eb7451e 100644
--- a/ports/cortex_m0/keil/src/tx_thread_schedule.s
+++ b/ports/cortex_m0/keil/src/tx_thread_schedule.s
@@ -30,6 +30,10 @@
IMPORT _tx_execution_thread_enter
IMPORT _tx_execution_thread_exit
ENDIF
+ IF :DEF:TX_LOW_POWER
+ IMPORT tx_low_power_enter
+ IMPORT tx_low_power_exit
+ ENDIF
;
;
AREA ||.text||, CODE, READONLY
@@ -39,7 +43,7 @@
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_schedule Cortex-M0/AC5 */
-;/* 6.1 */
+;/* 6.1.5 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
@@ -72,7 +76,10 @@
;/* */
;/* DATE NAME DESCRIPTION */
;/* */
-;/* 09-30-2020 William E. Lamie Initial Version 6.1 */
+;/* 09-30-2020 William E. Lamie Initial Version 6.1 */
+;/* 03-02-2021 Scott Larson Modified comment(s), add */
+;/* low power code, */
+;/* resulting in version 6.1.5 */
;/* */
;/**************************************************************************/
;VOID _tx_thread_schedule(VOID)
@@ -241,11 +248,25 @@ __tx_ts_wait
STR r1, [r0] ; Store it in the current pointer
CMP r1, #0 ; If non-NULL, a new thread is ready!
BNE __tx_ts_ready ;
- IF :DEF:TX_ENABLE_WFI
+
+ IF:DEF:TX_LOW_POWER
+ PUSH {r0-r3}
+ BL tx_low_power_enter ; Possibly enter low power mode
+ POP {r0-r3}
+ ENDIF
+
+ IF:DEF:TX_ENABLE_WFI
DSB ; Ensure no outstanding memory transactions
WFI ; Wait for interrupt
ISB ; Ensure pipeline is flushed
ENDIF
+
+ IF:DEF:TX_LOW_POWER
+ PUSH {r0-r3}
+ BL tx_low_power_exit ; Exit low power mode
+ POP {r0-r3}
+ ENDIF
+
__tx_ts_ISB
CPSIE i ; Enable interrupts
B __tx_ts_wait ; Loop to continue waiting
generated by cgit v1.3.1 (git 2.54.0) at 2026-08-31 03:53:59 +0000