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-rw-r--r--ports/cortex_m3/ac5/src/tx_thread_schedule.s27
-rw-r--r--ports/cortex_m3/ac6/src/tx_thread_schedule.S26
-rw-r--r--ports/cortex_m3/ghs/src/tx_thread_schedule.arm21
-rwxr-xr-x[-rw-r--r--]ports/cortex_m3/gnu/CMakeLists.txt0
-rw-r--r--ports/cortex_m3/gnu/src/tx_thread_schedule.S29
-rw-r--r--ports/cortex_m3/iar/src/tx_thread_schedule.s25
-rw-r--r--ports/cortex_m3/keil/src/tx_thread_schedule.s27
7 files changed, 139 insertions, 16 deletions
diff --git a/ports/cortex_m3/ac5/src/tx_thread_schedule.s b/ports/cortex_m3/ac5/src/tx_thread_schedule.s
index c0753dfe..82158967 100644
--- a/ports/cortex_m3/ac5/src/tx_thread_schedule.s
+++ b/ports/cortex_m3/ac5/src/tx_thread_schedule.s
@@ -30,6 +30,10 @@
IMPORT _tx_execution_thread_enter
IMPORT _tx_execution_thread_exit
ENDIF
+ IF :DEF:TX_LOW_POWER
+ IMPORT tx_low_power_enter
+ IMPORT tx_low_power_exit
+ ENDIF
;
;
AREA ||.text||, CODE, READONLY
@@ -39,7 +43,7 @@
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_schedule Cortex-M3/AC5 */
-;/* 6.1 */
+;/* 6.1.5 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
@@ -72,7 +76,10 @@
;/* */
;/* DATE NAME DESCRIPTION */
;/* */
-;/* 09-30-2020 William E. Lamie Initial Version 6.1 */
+;/* 09-30-2020 William E. Lamie Initial Version 6.1 */
+;/* 03-02-2021 Scott Larson Modified comment(s), add */
+;/* low power code, */
+;/* resulting in version 6.1.5 */
;/* */
;/**************************************************************************/
;VOID _tx_thread_schedule(VOID)
@@ -217,11 +224,25 @@ __tx_ts_wait
LDR r1, [r2] ; Pickup the next thread to execute pointer
STR r1, [r0] ; Store it in the current pointer
CBNZ r1, __tx_ts_ready ; If non-NULL, a new thread is ready!
- IF :DEF:TX_ENABLE_WFI
+
+ IF:DEF:TX_LOW_POWER
+ PUSH {r0-r3}
+ BL tx_low_power_enter ; Possibly enter low power mode
+ POP {r0-r3}
+ ENDIF
+
+ IF:DEF:TX_ENABLE_WFI
DSB ; Ensure no outstanding memory transactions
WFI ; Wait for interrupt
ISB ; Ensure pipeline is flushed
ENDIF
+
+ IF:DEF:TX_LOW_POWER
+ PUSH {r0-r3}
+ BL tx_low_power_exit ; Exit low power mode
+ POP {r0-r3}
+ ENDIF
+
CPSIE i ; Enable interrupts
B __tx_ts_wait ; Loop to continue waiting
;
diff --git a/ports/cortex_m3/ac6/src/tx_thread_schedule.S b/ports/cortex_m3/ac6/src/tx_thread_schedule.S
index 526bfd35..1998d02a 100644
--- a/ports/cortex_m3/ac6/src/tx_thread_schedule.S
+++ b/ports/cortex_m3/ac6/src/tx_thread_schedule.S
@@ -25,6 +25,11 @@
.global _tx_thread_execute_ptr
.global _tx_timer_time_slice
.global _tx_thread_system_stack_ptr
+#ifdef TX_LOW_POWER
+ .global tx_low_power_enter
+ .global tx_low_power_exit
+#endif
+
@
@
.text
@@ -35,7 +40,7 @@
@/* FUNCTION RELEASE */
@/* */
@/* _tx_thread_schedule Cortex-M3/AC6 */
-@/* 6.1 */
+@/* 6.1.5 */
@/* AUTHOR */
@/* */
@/* William E. Lamie, Microsoft Corporation */
@@ -68,7 +73,10 @@
@/* */
@/* DATE NAME DESCRIPTION */
@/* */
-@/* 09-30-2020 William E. Lamie Initial Version 6.1 */
+@/* 09-30-2020 William E. Lamie Initial Version 6.1 */
+@/* 03-02-2021 Scott Larson Modified comment(s), add */
+@/* low power code, */
+@/* resulting in version 6.1.5 */
@/* */
@/**************************************************************************/
@VOID _tx_thread_schedule(VOID)
@@ -218,11 +226,25 @@ __tx_ts_wait:
LDR r1, [r2] @ Pickup the next thread to execute pointer
STR r1, [r0] @ Store it in the current pointer
CBNZ r1, __tx_ts_ready @ If non-NULL, a new thread is ready!
+
+#ifdef TX_LOW_POWER
+ PUSH {r0-r3}
+ BL tx_low_power_enter @ Possibly enter low power mode
+ POP {r0-r3}
+#endif
+
#ifdef TX_ENABLE_WFI
DSB @ Ensure no outstanding memory transactions
WFI @ Wait for interrupt
ISB @ Ensure pipeline is flushed
#endif
+
+#ifdef TX_LOW_POWER
+ PUSH {r0-r3}
+ BL tx_low_power_exit @ Exit low power mode
+ POP {r0-r3}
+#endif
+
CPSIE i @ Enable interrupts
B __tx_ts_wait @ Loop to continue waiting
@
diff --git a/ports/cortex_m3/ghs/src/tx_thread_schedule.arm b/ports/cortex_m3/ghs/src/tx_thread_schedule.arm
index 61546f63..81e1e8e0 100644
--- a/ports/cortex_m3/ghs/src/tx_thread_schedule.arm
+++ b/ports/cortex_m3/ghs/src/tx_thread_schedule.arm
@@ -28,7 +28,7 @@
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_schedule Cortex-M3/GHS */
-;/* 6.1 */
+;/* 6.1.5 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
@@ -61,7 +61,10 @@
;/* */
;/* DATE NAME DESCRIPTION */
;/* */
-;/* 09-30-2020 William E. Lamie Initial Version 6.1 */
+;/* 09-30-2020 William E. Lamie Initial Version 6.1 */
+;/* 03-02-2021 Scott Larson Modified comment(s), add */
+;/* low power code, */
+;/* resulting in version 6.1.5 */
;/* */
;/**************************************************************************/
;VOID _tx_thread_schedule(VOID)
@@ -210,11 +213,25 @@ __tx_ts_wait:
LDR r1, [r2] ; Pickup the next thread to execute pointer
STR r1, [r0] ; Store it in the current pointer
CBNZ r1, __tx_ts_ready ; If non-NULL, a new thread is ready!
+
+#ifdef TX_LOW_POWER
+ PUSH {r0-r3}
+ BL tx_low_power_enter ; Possibly enter low power mode
+ POP {r0-r3}
+#endif
+
#ifdef TX_ENABLE_WFI
DSB ; Ensure no outstanding memory transactions
WFI ; Wait for interrupt
ISB ; Ensure pipeline is flushed
#endif
+
+#ifdef TX_LOW_POWER
+ PUSH {r0-r3}
+ BL tx_low_power_exit ; Exit low power mode
+ POP {r0-r3}
+#endif
+
CPSIE i ; Enable interrupts
B __tx_ts_wait ; Loop to continue waiting
;
diff --git a/ports/cortex_m3/gnu/CMakeLists.txt b/ports/cortex_m3/gnu/CMakeLists.txt
index 71e2d4f2..71e2d4f2 100644..100755
--- a/ports/cortex_m3/gnu/CMakeLists.txt
+++ b/ports/cortex_m3/gnu/CMakeLists.txt
diff --git a/ports/cortex_m3/gnu/src/tx_thread_schedule.S b/ports/cortex_m3/gnu/src/tx_thread_schedule.S
index b2689609..b9227c28 100644
--- a/ports/cortex_m3/gnu/src/tx_thread_schedule.S
+++ b/ports/cortex_m3/gnu/src/tx_thread_schedule.S
@@ -27,6 +27,10 @@
.global _tx_thread_system_stack_ptr
.global _tx_execution_thread_enter
.global _tx_execution_thread_exit
+#ifdef TX_LOW_POWER
+ .global tx_low_power_enter
+ .global tx_low_power_exit
+#endif
@
@
.text
@@ -37,7 +41,7 @@
@/* FUNCTION RELEASE */
@/* */
@/* _tx_thread_schedule Cortex-M3/GNU */
-@/* 6.1 */
+@/* 6.1.5 */
@/* AUTHOR */
@/* */
@/* William E. Lamie, Microsoft Corporation */
@@ -70,9 +74,12 @@
@/* */
@/* DATE NAME DESCRIPTION */
@/* */
-@/* 05-19-2020 William E. Lamie Initial Version 6.0 */
-@/* 09-30-2020 William E. Lamie Modified comment(s), */
-@/* resulting in version 6.1 */
+@/* 05-19-2020 William E. Lamie Initial Version 6.0 */
+@/* 09-30-2020 William E. Lamie Modified comment(s), */
+@/* resulting in version 6.1 */
+@/* 03-02-2021 Scott Larson Modified comment(s), add */
+@/* low power code, */
+@/* resulting in version 6.1.5 */
@/* */
@/**************************************************************************/
@VOID _tx_thread_schedule(VOID)
@@ -222,11 +229,25 @@ __tx_ts_wait:
LDR r1, [r2] @ Pickup the next thread to execute pointer
STR r1, [r0] @ Store it in the current pointer
CBNZ r1, __tx_ts_ready @ If non-NULL, a new thread is ready!
+
+#ifdef TX_LOW_POWER
+ PUSH {r0-r3}
+ BL tx_low_power_enter @ Possibly enter low power mode
+ POP {r0-r3}
+#endif
+
#ifdef TX_ENABLE_WFI
DSB @ Ensure no outstanding memory transactions
WFI @ Wait for interrupt
ISB @ Ensure pipeline is flushed
#endif
+
+#ifdef TX_LOW_POWER
+ PUSH {r0-r3}
+ BL tx_low_power_exit @ Exit low power mode
+ POP {r0-r3}
+#endif
+
CPSIE i @ Enable interrupts
B __tx_ts_wait @ Loop to continue waiting
@
diff --git a/ports/cortex_m3/iar/src/tx_thread_schedule.s b/ports/cortex_m3/iar/src/tx_thread_schedule.s
index e8a3c13d..4d109e86 100644
--- a/ports/cortex_m3/iar/src/tx_thread_schedule.s
+++ b/ports/cortex_m3/iar/src/tx_thread_schedule.s
@@ -28,6 +28,10 @@
EXTERN _tx_execution_thread_enter
EXTERN _tx_execution_thread_exit
EXTERN _tx_thread_preempt_disable
+#ifdef TX_LOW_POWER
+ EXTERN tx_low_power_enter
+ EXTERN tx_low_power_exit
+#endif
;
;
SECTION `.text`:CODE:NOROOT(2)
@@ -37,7 +41,7 @@
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_schedule Cortex-M3/IAR */
-;/* 6.1 */
+;/* 6.1.5 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
@@ -70,7 +74,10 @@
;/* */
;/* DATE NAME DESCRIPTION */
;/* */
-;/* 09-30-2020 William E. Lamie Initial Version 6.1 */
+;/* 09-30-2020 William E. Lamie Initial Version 6.1 */
+;/* 03-02-2021 Scott Larson Modified comment(s), add */
+;/* low power code, */
+;/* resulting in version 6.1.5 */
;/* */
;/**************************************************************************/
;VOID _tx_thread_schedule(VOID)
@@ -216,11 +223,25 @@ __tx_ts_wait:
LDR r1, [r2] ; Pickup the next thread to execute pointer
STR r1, [r0] ; Store it in the current pointer
CBNZ r1, __tx_ts_ready ; If non-NULL, a new thread is ready!
+
+#ifdef TX_LOW_POWER
+ PUSH {r0-r3}
+ BL tx_low_power_enter ; Possibly enter low power mode
+ POP {r0-r3}
+#endif
+
#ifdef TX_ENABLE_WFI
DSB ; Ensure no outstanding memory transactions
WFI ; Wait for interrupt
ISB ; Ensure pipeline is flushed
#endif
+
+#ifdef TX_LOW_POWER
+ PUSH {r0-r3}
+ BL tx_low_power_exit ; Exit low power mode
+ POP {r0-r3}
+#endif
+
CPSIE i ; Enable interrupts
B __tx_ts_wait ; Loop to continue waiting
;
diff --git a/ports/cortex_m3/keil/src/tx_thread_schedule.s b/ports/cortex_m3/keil/src/tx_thread_schedule.s
index beae1e0f..405f28f9 100644
--- a/ports/cortex_m3/keil/src/tx_thread_schedule.s
+++ b/ports/cortex_m3/keil/src/tx_thread_schedule.s
@@ -30,6 +30,10 @@
IMPORT _tx_execution_thread_enter
IMPORT _tx_execution_thread_exit
ENDIF
+ IF :DEF:TX_LOW_POWER
+ IMPORT tx_low_power_enter
+ IMPORT tx_low_power_exit
+ ENDIF
;
;
AREA ||.text||, CODE, READONLY
@@ -39,7 +43,7 @@
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_schedule Cortex-M3/AC5 */
-;/* 6.1 */
+;/* 6.1.5 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
@@ -72,7 +76,10 @@
;/* */
;/* DATE NAME DESCRIPTION */
;/* */
-;/* 09-30-2020 William E. Lamie Initial Version 6.1 */
+;/* 09-30-2020 William E. Lamie Initial Version 6.1 */
+;/* 03-02-2021 Scott Larson Modified comment(s), add */
+;/* low power code, */
+;/* resulting in version 6.1.5 */
;/* */
;/**************************************************************************/
;VOID _tx_thread_schedule(VOID)
@@ -217,11 +224,25 @@ __tx_ts_wait
LDR r1, [r2] ; Pickup the next thread to execute pointer
STR r1, [r0] ; Store it in the current pointer
CBNZ r1, __tx_ts_ready ; If non-NULL, a new thread is ready!
- IF :DEF:TX_ENABLE_WFI
+
+ IF:DEF:TX_LOW_POWER
+ PUSH {r0-r3}
+ BL tx_low_power_enter ; Possibly enter low power mode
+ POP {r0-r3}
+ ENDIF
+
+ IF:DEF:TX_ENABLE_WFI
DSB ; Ensure no outstanding memory transactions
WFI ; Wait for interrupt
ISB ; Ensure pipeline is flushed
ENDIF
+
+ IF:DEF:TX_LOW_POWER
+ PUSH {r0-r3}
+ BL tx_low_power_exit ; Exit low power mode
+ POP {r0-r3}
+ ENDIF
+
CPSIE i ; Enable interrupts
B __tx_ts_wait ; Loop to continue waiting
;
generated by cgit v1.3.1 (git 2.54.0) at 2026-08-31 07:08:31 +0000