diff options
Diffstat (limited to 'ports_module/cortex_m33/iar')
25 files changed, 341 insertions, 329 deletions
diff --git a/ports_module/cortex_m33/iar/example_build/tx_initialize_low_level.s b/ports_module/cortex_m33/iar/example_build/tx_initialize_low_level.s index e58c20a1..1ba0a002 100644 --- a/ports_module/cortex_m33/iar/example_build/tx_initialize_low_level.s +++ b/ports_module/cortex_m33/iar/example_build/tx_initialize_low_level.s @@ -1,26 +1,25 @@ -;/**************************************************************************/ -;/* */ -;/* Copyright (c) Microsoft Corporation. All rights reserved. */ -;/* */ -;/* This software is licensed under the Microsoft Software License */ -;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ -;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ -;/* and in the root directory of this software. */ -;/* */ -;/**************************************************************************/ -; -; -;/**************************************************************************/ -;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ -;/** */ -;/** Initialize */ -;/** */ -;/**************************************************************************/ -;/**************************************************************************/ -; -; +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Initialize */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + EXTERN _tx_thread_system_stack_ptr EXTERN _tx_initialize_unused_memory EXTERN _tx_timer_interrupt @@ -28,126 +27,112 @@ EXTERN __vector_table EXTERN _tx_thread_current_ptr EXTERN _tx_thread_stack_error_handler -; -; + SYSTEM_CLOCK EQU 96000000 SYSTICK_CYCLES EQU ((SYSTEM_CLOCK / 100) -1) -; -; + RSEG FREE_MEM:DATA PUBLIC __tx_free_memory_start __tx_free_memory_start DS32 4 -; -; + SECTION `.text`:CODE:NOROOT(2) THUMB - -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_initialize_low_level Cortex-M33/IAR */ -;/* 6.0.1 */ -;/* AUTHOR */ -;/* */ -;/* Scott Larson, Microsoft Corporation */ -;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function is responsible for any low-level processor */ -;/* initialization, including setting up interrupt vectors, setting */ -;/* up a periodic timer interrupt source, saving the system stack */ -;/* pointer for use in ISR processing later, and finding the first */ -;/* available RAM memory address for tx_application_define. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* _tx_initialize_kernel_enter ThreadX entry function */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ -;/* */ -;/**************************************************************************/ -;VOID _tx_initialize_low_level(VOID) -;{ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_initialize_low_level Cortex-M33/IAR */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is responsible for any low-level processor */ +/* initialization, including setting up interrupt vectors, setting */ +/* up a periodic timer interrupt source, saving the system stack */ +/* pointer for use in ISR processing later, and finding the first */ +/* available RAM memory address for tx_application_define. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_initialize_kernel_enter ThreadX entry function */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +// VOID _tx_initialize_low_level(VOID) +// { PUBLIC _tx_initialize_low_level _tx_initialize_low_level: -; -; /* Disable interrupts during ThreadX initialization. */ -; + + /* Disable interrupts during ThreadX initialization. */ CPSID i -; -; /* Set base of available memory to end of non-initialised RAM area. */ -; - LDR r0, =_tx_initialize_unused_memory ; Build address of unused memory pointer - LDR r1, =__tx_free_memory_start ; Build first free address - STR r1, [r0] ; Setup first unused memory pointer -; -; /* Setup Vector Table Offset Register. */ -; - MOV r0, #0xE000E000 ; Build address of NVIC registers - LDR r1, =__vector_table ; Pickup address of vector table - STR r1, [r0, #0xD08] ; Set vector table address -; -; /* Enable the cycle count register. */ -; -; LDR r0, =0xE0001000 ; Build address of DWT register -; LDR r1, [r0] ; Pickup the current value -; ORR r1, r1, #1 ; Set the CYCCNTENA bit -; STR r1, [r0] ; Enable the cycle count register -; -; /* Set system stack pointer from vector value. */ -; - LDR r0, =_tx_thread_system_stack_ptr ; Build address of system stack pointer - LDR r1, =__vector_table ; Pickup address of vector table - LDR r1, [r1] ; Pickup reset stack pointer - STR r1, [r0] ; Save system stack pointer -; -; /* Configure SysTick. */ -; - MOV r0, #0xE000E000 ; Build address of NVIC registers + + /* Set base of available memory to end of non-initialised RAM area. */ + LDR r0, =_tx_initialize_unused_memory // Build address of unused memory pointer + LDR r1, =__tx_free_memory_start // Build first free address + STR r1, [r0] // Setup first unused memory pointer + + /* Setup Vector Table Offset Register. */ + MOV r0, #0xE000E000 // Build address of NVIC registers + LDR r1, =__vector_table // Pickup address of vector table + STR r1, [r0, #0xD08] // Set vector table address + + /* Enable the cycle count register. */ +// LDR r0, =0xE0001000 // Build address of DWT register +// LDR r1, [r0] // Pickup the current value +// ORR r1, r1, #1 // Set the CYCCNTENA bit +// STR r1, [r0] // Enable the cycle count register + + /* Set system stack pointer from vector value. */ + LDR r0, =_tx_thread_system_stack_ptr // Build address of system stack pointer + LDR r1, =__vector_table // Pickup address of vector table + LDR r1, [r1] // Pickup reset stack pointer + STR r1, [r0] // Save system stack pointer + + /* Configure SysTick. */ + MOV r0, #0xE000E000 // Build address of NVIC registers LDR r1, =SYSTICK_CYCLES - STR r1, [r0, #0x14] ; Setup SysTick Reload Value - MOV r1, #0x7 ; Build SysTick Control Enable Value - STR r1, [r0, #0x10] ; Setup SysTick Control -; -; /* Configure handler priorities. */ -; - LDR r1, =0x00000000 ; Rsrv, UsgF, BusF, MemM - STR r1, [r0, #0xD18] ; Setup System Handlers 4-7 Priority Registers + STR r1, [r0, #0x14] // Setup SysTick Reload Value + MOV r1, #0x7 // Build SysTick Control Enable Value + STR r1, [r0, #0x10] // Setup SysTick Control - LDR r1, =0xFF000000 ; SVCl, Rsrv, Rsrv, Rsrv - STR r1, [r0, #0xD1C] ; Setup System Handlers 8-11 Priority Registers - ; Note: SVC must be lowest priority, which is 0xFF + /* Configure handler priorities. */ + LDR r1, =0x00000000 // Rsrv, UsgF, BusF, MemM + STR r1, [r0, #0xD18] // Setup System Handlers 4-7 Priority Registers + LDR r1, =0xFF000000 // SVCl, Rsrv, Rsrv, Rsrv + STR r1, [r0, #0xD1C] // Setup System Handlers 8-11 Priority Registers + // Note: SVC must be lowest priority, which is 0xFF + LDR r1, =0x40FF0000 // SysT, PnSV, Rsrv, DbgM + STR r1, [r0, #0xD20] // Setup System Handlers 12-15 Priority Registers + // Note: PnSV must be lowest priority, which is 0xFF - LDR r1, =0x40FF0000 ; SysT, PnSV, Rsrv, DbgM - STR r1, [r0, #0xD20] ; Setup System Handlers 12-15 Priority Registers - ; Note: PnSV must be lowest priority, which is 0xFF -; -; /* Return to caller. */ -; + /* Return to caller. */ BX lr -;} -; -; -;/* Define shells for each of the unused vectors. */ -; +// } + + +/* Define shells for each of the unused vectors. */ + PUBLIC __tx_BadHandler __tx_BadHandler: B __tx_BadHandler @@ -155,30 +140,39 @@ __tx_BadHandler: PUBLIC __tx_IntHandler __tx_IntHandler: -; VOID InterruptHandler (VOID) -; { - PUSH {r0,lr} ; Save LR (and dummy r0 to maintain stack alignment) - -; /* Do interrupt handler work here */ -; /* .... */ - +// VOID InterruptHandler (VOID) +// { + PUSH {r0,lr} // Save LR (and dummy r0 to maintain stack alignment) +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) + BL _tx_execution_isr_enter // Call the ISR enter function +#endif + /* Do interrupt handler work here */ + /* .... */ +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) + BL _tx_execution_isr_exit // Call the ISR exit function +#endif POP {r0,lr} - BX LR -; } + BX lr +// } PUBLIC __tx_SysTickHandler PUBLIC SysTick_Handler SysTick_Handler: __tx_SysTickHandler: -; VOID TimerInterruptHandler (VOID) -; { -; - PUSH {r0,lr} ; Save LR (and dummy r0 to maintain stack alignment) +// VOID TimerInterruptHandler (VOID) +// { + PUSH {r0,lr} // Save LR (and dummy r0 to maintain stack alignment) +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) + BL _tx_execution_isr_enter // Call the ISR enter function +#endif BL _tx_timer_interrupt +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) + BL _tx_execution_isr_exit // Call the ISR exit function +#endif POP {r0,lr} - BX LR -; } + BX lr +// } PUBLIC HardFault_Handler HardFault_Handler: @@ -187,55 +181,55 @@ HardFault_Handler: PUBLIC UsageFault_Handler UsageFault_Handler: - CPSID i ; Disable interrupts - ; Check for stack limit fault - LDR r0, =0xE000ED28 ; CFSR address - LDR r1,[r0] ; Pick up CFSR - TST r1, #0x00100000 ; Check for Stack Overflow + CPSID i // Disable interrupts + // Check for stack limit fault + LDR r0, =0xE000ED28 // CFSR address + LDR r1,[r0] // Pick up CFSR + TST r1, #0x00100000 // Check for Stack Overflow _unhandled_usage_loop - BEQ _unhandled_usage_loop ; If not stack overflow then loop - - ; Handle stack overflow - STR r1, [r0] ; Clear CFSR flag(s) - + BEQ _unhandled_usage_loop // If not stack overflow then loop + + // Handle stack overflow + STR r1, [r0] // Clear CFSR flag(s) + #ifdef __ARMVFP__ - LDR r0, =0xE000EF34 ; Cleanup FPU context: Load FPCCR address - LDR r1, [r0] ; Load FPCCR - BIC r1, r1, #1 ; Clear the lazy preservation active bit - STR r1, [r0] ; Store the value + LDR r0, =0xE000EF34 // Cleanup FPU context: Load FPCCR address + LDR r1, [r0] // Load FPCCR + BIC r1, r1, #1 // Clear the lazy preservation active bit + STR r1, [r0] // Store the value #endif - - MOV32 r0, _tx_thread_current_ptr ; Build current thread pointer address - LDR r0,[r0] ; Pick up current thread pointer - PUSH {r0,lr} ; Save LR (and r0 to maintain stack alignment) - BL _tx_thread_stack_error_handler ; Call ThreadX/user handler - POP {r0,lr} ; Restore LR and dummy reg - -#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY - ; Call the thread exit function to indicate the thread is no longer executing. - PUSH {r0, lr} ; Save LR (and r0 just for alignment) - BL _tx_execution_thread_exit ; Call the thread exit function - POP {r0, lr} ; Recover LR + + LDR r0, =_tx_thread_current_ptr // Build current thread pointer address + LDR r0,[r0] // Pick up current thread pointer + PUSH {r0,lr} // Save LR (and r0 to maintain stack alignment) + BL _tx_thread_stack_error_handler // Call ThreadX/user handler + POP {r0,lr} // Restore LR and dummy reg + +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) + // Call the thread exit function to indicate the thread is no longer executing. + PUSH {r0, lr} // Save LR (and r0 just for alignment) + BL _tx_execution_thread_exit // Call the thread exit function + POP {r0, lr} // Recover LR #endif - - MOV r1, #0 ; Build NULL value - LDR r0, =_tx_thread_current_ptr ; Pickup address of current thread pointer - STR r1, [r0] ; Clear current thread pointer - - ; Return from UsageFault_Handler exception - LDR r0, =0xE000ED04 ; Load ICSR - LDR r1, =0x10000000 ; Set PENDSVSET bit - STR r1, [r0] ; Store ICSR - DSB ; Wait for memory access to complete - CPSIE i ; Enable interrupts - BX lr ; Return from exception + + MOV r1, #0 // Build NULL value + LDR r0, =_tx_thread_current_ptr // Pickup address of current thread pointer + STR r1, [r0] // Clear current thread pointer + + // Return from UsageFault_Handler exception + LDR r0, =0xE000ED04 // Load ICSR + LDR r1, =0x10000000 // Set PENDSVSET bit + STR r1, [r0] // Store ICSR + DSB // Wait for memory access to complete + CPSIE i // Enable interrupts + BX lr // Return from exception PUBLIC __tx_NMIHandler __tx_NMIHandler: B __tx_NMIHandler - - + + PUBLIC __tx_DBGHandler __tx_DBGHandler: B __tx_DBGHandler diff --git a/ports_module/cortex_m33/iar/inc/tx_secure_interface.h b/ports_module/cortex_m33/iar/inc/tx_secure_interface.h index c2779f40..0a2bdd67 100644 --- a/ports_module/cortex_m33/iar/inc/tx_secure_interface.h +++ b/ports_module/cortex_m33/iar/inc/tx_secure_interface.h @@ -42,7 +42,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ diff --git a/ports_module/cortex_m33/iar/module_manager/src/tx_thread_context_restore.s b/ports_module/cortex_m33/iar/module_manager/src/tx_thread_context_restore.s index e6b64c8b..19f225d6 100644 --- a/ports_module/cortex_m33/iar/module_manager/src/tx_thread_context_restore.s +++ b/ports_module/cortex_m33/iar/module_manager/src/tx_thread_context_restore.s @@ -27,16 +27,15 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_context_restore Cortex-M/IAR */ -/* 6.1.5 */ +/* _tx_thread_context_restore Cortex-M33/IAR */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ /* */ /* DESCRIPTION */ /* */ -/* This function is only needed for legacy applications and it should */ -/* not be called in any new development on a Cortex-M. */ +/* This function is not needed for Cortex-M. */ /* */ /* INPUT */ /* */ @@ -58,7 +57,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 03-02-2021 Scott Larson Initial Version 6.1.5 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) @@ -66,7 +65,7 @@ PUBLIC _tx_thread_context_restore _tx_thread_context_restore: -#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) /* Call the ISR exit function to indicate an ISR is complete. */ PUSH {r0, lr} // Save return address BL _tx_execution_isr_exit // Call the ISR exit function @@ -74,6 +73,5 @@ _tx_thread_context_restore: #endif BX lr - // } END diff --git a/ports_module/cortex_m33/iar/module_manager/src/tx_thread_context_save.s b/ports_module/cortex_m33/iar/module_manager/src/tx_thread_context_save.s index 7df6a4f2..1e725265 100644 --- a/ports_module/cortex_m33/iar/module_manager/src/tx_thread_context_save.s +++ b/ports_module/cortex_m33/iar/module_manager/src/tx_thread_context_save.s @@ -27,16 +27,15 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_context_save Cortex-M/IAR */ -/* 6.1.5 */ +/* _tx_thread_context_save Cortex-M33/IAR */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ /* */ /* DESCRIPTION */ /* */ -/* This function is only needed for legacy applications and it should */ -/* not be called in any new development on a Cortex-M. */ +/* This function is not needed for Cortex-M. */ /* */ /* INPUT */ /* */ @@ -48,7 +47,7 @@ /* */ /* CALLS */ /* */ -/* None */ +/* [_tx_execution_isr_enter] Execution profiling ISR enter */ /* */ /* CALLED BY */ /* */ @@ -58,7 +57,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 03-02-2021 Scott Larson Initial Version 6.1.5 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) @@ -66,15 +65,13 @@ PUBLIC _tx_thread_context_save _tx_thread_context_save: -#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) /* Call the ISR enter function to indicate an ISR is starting. */ PUSH {r0, lr} // Save return address BL _tx_execution_isr_enter // Call the ISR enter function POP {r0, lr} // Recover return address #endif - /* Context is already saved - just return. */ - BX lr // } END diff --git a/ports_module/cortex_m33/iar/module_manager/src/tx_thread_interrupt_control.s b/ports_module/cortex_m33/iar/module_manager/src/tx_thread_interrupt_control.s index 0086829d..45e5c5de 100644 --- a/ports_module/cortex_m33/iar/module_manager/src/tx_thread_interrupt_control.s +++ b/ports_module/cortex_m33/iar/module_manager/src/tx_thread_interrupt_control.s @@ -26,8 +26,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_interrupt_control Cortex-M/IAR */ -/* 6.1.5 */ +/* _tx_thread_interrupt_control Cortex-M33/IAR */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -57,17 +57,22 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 03-02-2021 Scott Larson Initial Version 6.1.5 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) // { PUBLIC _tx_thread_interrupt_control _tx_thread_interrupt_control: +#ifdef TX_PORT_USE_BASEPRI + MRS r1, BASEPRI // Pickup current interrupt posture + MSR BASEPRI, r0 // Apply the new interrupt posture + MOV r0, r1 // Transfer old to return register +#else MRS r1, PRIMASK // Pickup current interrupt lockout MSR PRIMASK, r0 // Apply the new interrupt lockout MOV r0, r1 // Transfer old to return register +#endif BX lr // Return to caller - // } END diff --git a/ports_module/cortex_m33/iar/module_manager/src/tx_thread_interrupt_disable.s b/ports_module/cortex_m33/iar/module_manager/src/tx_thread_interrupt_disable.s index c6853ed1..68421f0e 100644 --- a/ports_module/cortex_m33/iar/module_manager/src/tx_thread_interrupt_disable.s +++ b/ports_module/cortex_m33/iar/module_manager/src/tx_thread_interrupt_disable.s @@ -26,8 +26,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_interrupt_disable Cortex-M/IAR */ -/* 6.1.5 */ +/* _tx_thread_interrupt_disable Cortex-M33/IAR */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -57,19 +57,22 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 03-02-2021 Scott Larson Initial Version 6.1.5 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ // UINT _tx_thread_interrupt_disable(VOID) // { PUBLIC _tx_thread_interrupt_disable _tx_thread_interrupt_disable: - /* Return current interrupt lockout posture. */ - +#ifdef TX_PORT_USE_BASEPRI + MRS r0, BASEPRI + LDR r1, =TX_PORT_BASEPRI + MSR BASEPRI, r1 +#else MRS r0, PRIMASK CPSID i +#endif BX lr - // } END diff --git a/ports_module/cortex_m33/iar/module_manager/src/tx_thread_interrupt_restore.s b/ports_module/cortex_m33/iar/module_manager/src/tx_thread_interrupt_restore.s index f4e46f8b..c590eb13 100644 --- a/ports_module/cortex_m33/iar/module_manager/src/tx_thread_interrupt_restore.s +++ b/ports_module/cortex_m33/iar/module_manager/src/tx_thread_interrupt_restore.s @@ -26,8 +26,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_interrupt_restore Cortex-M/IAR */ -/* 6.1.5 */ +/* _tx_thread_interrupt_restore Cortex-M33/IAR */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -57,18 +57,19 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 03-02-2021 Scott Larson Initial Version 6.1.5 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_interrupt_restore(UINT previous_posture) // { PUBLIC _tx_thread_interrupt_restore _tx_thread_interrupt_restore: - /* Restore previous interrupt lockout posture. */ - +#ifdef TX_PORT_USE_BASEPRI + MSR BASEPRI, r0 +#else MSR PRIMASK, r0 +#endif BX lr - // } END diff --git a/ports_module/cortex_m33/iar/module_manager/src/tx_thread_schedule.s b/ports_module/cortex_m33/iar/module_manager/src/tx_thread_schedule.s index 861e2946..a584c2b7 100644 --- a/ports_module/cortex_m33/iar/module_manager/src/tx_thread_schedule.s +++ b/ports_module/cortex_m33/iar/module_manager/src/tx_thread_schedule.s @@ -41,8 +41,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_schedule Cortex-M33/MPU/IAR */ -/* 6.1.7 */ +/* _tx_thread_schedule Cortex-M33/IAR */ +/* 6.1.8 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -87,37 +87,31 @@ // { PUBLIC _tx_thread_schedule _tx_thread_schedule: - /* This function should only ever be called on Cortex-M from the first schedule request. Subsequent scheduling occurs from the PendSV handling routine below. */ /* Clear the preempt-disable flag to enable rescheduling after initialization on Cortex-M targets. */ - MOV r0, #0 // Build value for TX_FALSE LDR r2, =_tx_thread_preempt_disable // Build address of preempt disable flag STR r0, [r2, #0] // Clear preempt disable flag - /* Clear CONTROL.FPCA bit so VFP registers aren't unnecessarily stacked. */ - #ifdef __ARMVFP__ + /* Clear CONTROL.FPCA bit so VFP registers aren't unnecessarily stacked. */ MRS r0, CONTROL // Pickup current CONTROL register BIC r0, r0, #4 // Clear the FPCA bit MSR CONTROL, r0 // Setup new CONTROL register #endif /* Enable memory fault registers. */ - LDR r0, =0xE000ED24 // Build SHCSR address LDR r1, =0x70000 // Enable Usage, Bus, and MemManage faults STR r1, [r0] // /* Enable interrupts */ - CPSIE i /* Enter the scheduler for the first time. */ - MOV r0, #0x10000000 // Load PENDSVSET bit MOV r1, #0xE000E000 // Load NVIC base STR r0, [r1, #0xD04] // Set PENDSVBIT in ICSR @@ -234,12 +228,9 @@ BusFault_Handler: PUBLIC PendSV_Handler PendSV_Handler: - - /* Get current thread value and new thread pointer. */ - __tx_ts_handler: -#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) /* Call the thread exit function to indicate the thread is no longer executing. */ CPSID i // Disable interrupts PUSH {r0, lr} // Save LR (and r0 just for alignment) @@ -350,7 +341,7 @@ __tx_ts_restore: STR r5, [r4] // Setup global time-slice -#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) /* Call the thread entry function to indicate the thread is executing. */ PUSH {r0, r1} // Save r0 and r1 BL _tx_execution_thread_enter // Call the thread execution enter function @@ -413,8 +404,6 @@ _skip_vfp_restore: LDMIA r12!, {r4-r11} // Recover thread's registers MSR PSP, r12 // Setup the thread's stack pointer - /* Return to thread. */ - BX lr // Return to thread! @@ -435,7 +424,7 @@ SVC_Handler: CMP r2, #2 // Is it a secure stack free request? BEQ _tx_svc_secure_free // Yes, go there -#endif // End of ifndef TX_SINGLE_MODE_SECURE, TX_SINGLE_MODE_NON_SECURE +#endif // End of ifndef TX_SINGLE_MODE_SECURE, TX_SINGLE_MODE_NON_SECURE CMP r2, #3 // Is it the entry into ThreadX? @@ -444,7 +433,7 @@ SVC_Handler: /* At this point we have an SVC 3, which means we are entering the kernel from a module thread with user mode selected. */ - LDR r2, =_txm_module_priv // Load address of where we should have come from + LDR r2, =_txm_module_priv-1 // Load address of where we should have come from CMP r1, r2 // Did we come from user_mode_entry? IT NE // If no (not equal), then... BXNE lr // return from where we came. @@ -501,7 +490,7 @@ _tx_skip_kernel_stack_enter: _tx_thread_user_return: - LDR r2, =_txm_module_user_mode_exit // Load address of where we should have come from + LDR r2, =_txm_module_user_mode_exit-1 // Load address of where we should have come from CMP r1, r2 // Did we come from user_mode_exit? IT NE // If no (not equal), then... BXNE lr // return from where we came @@ -527,6 +516,27 @@ _tx_thread_user_return: STR r1, [r2, #16] // Set stack end STR r3, [r2, #20] // Set stack size #endif + + /* If lazy stacking is pending, check if it can be cleared. + if(LSPACT && tx_thread_module_stack_start < FPCAR && FPCAR < tx_thread_module_stack_end) + then clear LSPACT. */ + LDR r3, =0xE000EF34 // Address of FPCCR + LDR r3, [r3] // Load FPCCR + TST r3, #1 // Check if LSPACT is set + BEQ _tx_no_lazy_clear // if clear, move on + LDR r1, =0xE000EF38 // Address of FPCAR + LDR r1, [r1] // Load FPCAR + LDR r0, [r2, #0xA4] // Load kernel stack start + CMP r1, r0 // If FPCAR < start, move on + BLO _tx_no_lazy_clear + LDR r0, [r2, #0xA8] // Load kernel stack end + CMP r0, r1 // If end < FPCAR, move on + BLO _tx_no_lazy_clear + BIC r3, #1 // Clear LSPACT + LDR r1, =0xE000EF34 // Address of FPCCR + STR r3, [r1] // Save updated FPCCR +_tx_no_lazy_clear: + LDR r0, [r2, #0xB0] // Load the module thread stack pointer MRS r3, PSP // Pickup kernel stack pointer TST r0, #1 // Is module stack extended? @@ -536,14 +546,14 @@ _tx_thread_user_return: ORREQ lr, lr, #0x10 // Else set bit, return with standard frame /* Copy kernel hardware stack to module thread stack. */ - LDM r3!, {r1-r2} - STM r0!, {r1-r2} - LDM r3!, {r1-r2} - STM r0!, {r1-r2} - LDM r3!, {r1-r2} - STM r0!, {r1-r2} - LDM r3!, {r1-r2} - STM r0!, {r1-r2} + LDM r3!, {r1-r2} // Get r0, r1 from kernel stack + STM r0!, {r1-r2} // Insert r0, r1 into thread stack + LDM r3!, {r1-r2} // Get r2, r3 from kernel stack + STM r0!, {r1-r2} // Insert r2, r3 into thread stack + LDM r3!, {r1-r2} // Get r12, lr from kernel stack + STM r0!, {r1-r2} // Insert r12, lr into thread stack + LDM r3!, {r1-r2} // Get pc, xpsr from kernel stack + STM r0!, {r1-r2} // Insert pc, xpsr into thread stack SUB r0, r0, #32 // Subtract 32 to get back to top of stack MSR PSP, r0 // Set thread stack pointer @@ -560,7 +570,7 @@ _tx_skip_kernel_stack_exit: #if (!defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE)) _tx_svc_secure_alloc: - LDR r2, =_tx_alloc_return // Load address of where we should have come from + LDR r2, =_tx_alloc_return-1 // Load address of where we should have come from CMP r1, r2 // Did we come from _tx_thread_secure_stack_allocate? IT NE // If no (not equal), then... BXNE lr // return from where we came. @@ -573,7 +583,7 @@ _tx_svc_secure_alloc: BX lr _tx_svc_secure_free: - LDR r2, =_tx_free_return // Load address of where we should have come from + LDR r2, =_tx_free_return-1 // Load address of where we should have come from CMP r1, r2 // Did we come from _tx_thread_secure_stack_free? IT NE // If no (not equal), then... BXNE lr // return from where we came. @@ -584,11 +594,11 @@ _tx_svc_secure_free: POP {r12, lr} // Restore SP and EXC_RETURN STR r0, [r12] // Store function return value BX lr -#endif // End of ifndef TX_SINGLE_MODE_SECURE, TX_SINGLE_MODE_NON_SECURE +#endif // End of ifndef TX_SINGLE_MODE_SECURE, TX_SINGLE_MODE_NON_SECURE - /* Kernel entry function from user mode. */ + /* Kernel entry function from user mode. */ EXTERN _txm_module_manager_kernel_dispatch SECTION `.text`:CODE:NOROOT(5) @@ -623,5 +633,4 @@ _txm_module_user_mode_exit: _tx_vfp_access: VMOV.F32 s0, s0 // Simply access the VFP BX lr // Return to caller - END diff --git a/ports_module/cortex_m33/iar/module_manager/src/tx_thread_secure_stack.c b/ports_module/cortex_m33/iar/module_manager/src/tx_thread_secure_stack.c index 844f8175..64006f59 100644 --- a/ports_module/cortex_m33/iar/module_manager/src/tx_thread_secure_stack.c +++ b/ports_module/cortex_m33/iar/module_manager/src/tx_thread_secure_stack.c @@ -62,8 +62,8 @@ typedef struct TX_THREAD_SECURE_STACK_INFO_STRUCT /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_secure_stack_initialize Cortex-M33/IAR */ -/* 6.1.1 */ +/* _tx_thread_secure_mode_stack_initialize Cortex-M33/IAR */ +/* 6.1.8 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -78,7 +78,7 @@ typedef struct TX_THREAD_SECURE_STACK_INFO_STRUCT /* */ /* OUTPUT */ /* */ -/* None */ +/* status */ /* */ /* CALLS */ /* */ @@ -98,21 +98,34 @@ typedef struct TX_THREAD_SECURE_STACK_INFO_STRUCT /* 09-30-2020 Scott Larson Initial Version 6.1 */ /* 10-16-2020 Scott Larson Modified comment(s), */ /* resulting in version 6.1.1 */ +/* 08-02-2021 Scott Larson Change name, execute in */ +/* handler mode, */ +/* resulting in version 6.1.8 */ /* */ /**************************************************************************/ __attribute__((cmse_nonsecure_entry)) -void _tx_thread_secure_stack_initialize(void) +UINT _tx_thread_secure_mode_stack_initialize(void) { - - /* Set secure mode to use PSP. */ - __set_CONTROL(__get_CONTROL() | 2); - - /* Set process stack pointer and stack limit to 0 to throw exception when a thread - without a secure stack calls a secure function that tries to use secure stack. */ - __set_PSPLIM(0); - __set_PSP(0); - - return; +UINT status; + + /* Make sure function is called from interrupt (threads should not call). */ + if (__get_IPSR() == 0) + { + status = TX_CALLER_ERROR; + } + else + { + /* Set secure mode to use PSP. */ + __set_CONTROL(__get_CONTROL() | 2); + + /* Set process stack pointer and stack limit to 0 to throw exception when a thread + without a secure stack calls a secure function that tries to use secure stack. */ + __set_PSPLIM(0); + __set_PSP(0); + + status = TX_SUCCESS; + } + return status; } @@ -291,7 +304,7 @@ UINT _tx_thread_secure_mode_stack_free(TX_THREAD *thread_ptr) { UINT status; TX_THREAD_SECURE_STACK_INFO *info_ptr; - + status = TX_SUCCESS; /* Pickup stack info from thread. */ @@ -376,7 +389,7 @@ void _tx_thread_secure_stack_context_save(TX_THREAD *thread_ptr) { TX_THREAD_SECURE_STACK_INFO *info_ptr; ULONG sp; - + /* This function should be called from scheduler only. */ if (__get_IPSR() == 0) { diff --git a/ports_module/cortex_m33/iar/module_manager/src/tx_thread_secure_stack_allocate.s b/ports_module/cortex_m33/iar/module_manager/src/tx_thread_secure_stack_allocate.s index 560d8f03..c718d34a 100644 --- a/ports_module/cortex_m33/iar/module_manager/src/tx_thread_secure_stack_allocate.s +++ b/ports_module/cortex_m33/iar/module_manager/src/tx_thread_secure_stack_allocate.s @@ -20,7 +20,6 @@ /**************************************************************************/ /**************************************************************************/ - SECTION `.text`:CODE:NOROOT(2) THUMB /**************************************************************************/ @@ -82,5 +81,4 @@ _tx_alloc_return: #endif _alloc_return_interrupt_enabled BX lr - END diff --git a/ports_module/cortex_m33/iar/module_manager/src/tx_thread_secure_stack_free.s b/ports_module/cortex_m33/iar/module_manager/src/tx_thread_secure_stack_free.s index b962fc70..e1875b7c 100644 --- a/ports_module/cortex_m33/iar/module_manager/src/tx_thread_secure_stack_free.s +++ b/ports_module/cortex_m33/iar/module_manager/src/tx_thread_secure_stack_free.s @@ -20,7 +20,6 @@ /**************************************************************************/ /**************************************************************************/ - SECTION `.text`:CODE:NOROOT(2) THUMB /**************************************************************************/ diff --git a/ports_module/cortex_m33/iar/module_manager/src/tx_thread_stack_build.s b/ports_module/cortex_m33/iar/module_manager/src/tx_thread_stack_build.s index 5bf333d1..d4131978 100644 --- a/ports_module/cortex_m33/iar/module_manager/src/tx_thread_stack_build.s +++ b/ports_module/cortex_m33/iar/module_manager/src/tx_thread_stack_build.s @@ -26,8 +26,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_stack_build Cortex-M/IAR */ -/* 6.1.5 */ +/* _tx_thread_stack_build Cortex-M33/IAR */ +/* 6.1.8 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -59,14 +59,13 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 03-02-2021 Scott Larson Initial Version 6.1.5 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) // { PUBLIC _tx_thread_stack_build _tx_thread_stack_build: - /* Build a fake interrupt frame. The form of the fake interrupt stack on the Cortex-M should look like the following after it is built: @@ -94,7 +93,11 @@ _tx_thread_stack_build: LDR r2, [r0, #16] // Pickup end of stack area BIC r2, r2, #0x7 // Align frame for 8-byte alignment SUB r2, r2, #68 // Subtract frame size - LDR r3, =0xFFFFFFFD // Build initial LR value +#ifdef TX_SINGLE_MODE_SECURE + LDR r3, =0xFFFFFFFD // Build initial LR value for secure mode +#else + LDR r3, =0xFFFFFFBC // Build initial LR value to return to non-secure PSP +#endif STR r3, [r2, #0] // Save on the stack /* Actually build the stack frame. */ diff --git a/ports_module/cortex_m33/iar/module_manager/src/tx_thread_stack_error_handler.c b/ports_module/cortex_m33/iar/module_manager/src/tx_thread_stack_error_handler.c index 27ac5c42..4d3bbee7 100644 --- a/ports_module/cortex_m33/iar/module_manager/src/tx_thread_stack_error_handler.c +++ b/ports_module/cortex_m33/iar/module_manager/src/tx_thread_stack_error_handler.c @@ -28,8 +28,8 @@ #include "tx_api.h" #include "tx_thread.h" -/* Define the global function pointer for stack error handling. If a stack error is - detected and the application has registered a stack error handler, it will be +/* Define the global function pointer for stack error handling. If a stack error is + detected and the application has registered a stack error handler, it will be called via this function pointer. */ VOID (*_tx_thread_application_stack_error_handler)(TX_THREAD *thread_ptr); @@ -38,8 +38,8 @@ VOID (*_tx_thread_application_stack_error_handler)(TX_THREAD *thread_ptr); /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_stack_error_handler Cortex-M33/IAR */ -/* 6.1 */ +/* _tx_thread_stack_error_handler Cortex-M33 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -70,12 +70,11 @@ VOID (*_tx_thread_application_stack_error_handler)(TX_THREAD *thread_ptr); /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ VOID _tx_thread_stack_error_handler(TX_THREAD *thread_ptr) { - #ifndef TX_THREAD_NO_TERMINATE_STACK_ERROR /* Is there a thread? */ if (thread_ptr) @@ -88,10 +87,7 @@ VOID _tx_thread_stack_error_handler(TX_THREAD *thread_ptr) /* Determine if the application has registered an error handler. */ if (_tx_thread_application_stack_error_handler != TX_NULL) { - /* Yes, an error handler is present, simply call the application error handler. */ (_tx_thread_application_stack_error_handler)(thread_ptr); } - } - diff --git a/ports_module/cortex_m33/iar/module_manager/src/tx_thread_stack_error_notify.c b/ports_module/cortex_m33/iar/module_manager/src/tx_thread_stack_error_notify.c index 328103b2..d61a27b3 100644 --- a/ports_module/cortex_m33/iar/module_manager/src/tx_thread_stack_error_notify.c +++ b/ports_module/cortex_m33/iar/module_manager/src/tx_thread_stack_error_notify.c @@ -35,8 +35,8 @@ extern VOID (*_tx_thread_application_stack_error_handler)(TX_THREAD *thread_ptr) /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_stack_error_notify Cortex-M33/IAR */ -/* 6.1 */ +/* _tx_thread_stack_error_notify Cortex-M33 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -68,7 +68,7 @@ extern VOID (*_tx_thread_application_stack_error_handler)(TX_THREAD *thread_ptr) /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _tx_thread_stack_error_notify(VOID (*stack_error_handler)(TX_THREAD *thread_ptr)) @@ -76,7 +76,6 @@ UINT _tx_thread_stack_error_notify(VOID (*stack_error_handler)(TX_THREAD *threa TX_INTERRUPT_SAVE_AREA - /* Disable interrupts. */ TX_DISABLE @@ -95,4 +94,3 @@ TX_INTERRUPT_SAVE_AREA /* Return success to caller. */ return(TX_SUCCESS); } - diff --git a/ports_module/cortex_m33/iar/module_manager/src/tx_thread_system_return.s b/ports_module/cortex_m33/iar/module_manager/src/tx_thread_system_return.s index 3a180138..2b8aea89 100644 --- a/ports_module/cortex_m33/iar/module_manager/src/tx_thread_system_return.s +++ b/ports_module/cortex_m33/iar/module_manager/src/tx_thread_system_return.s @@ -26,8 +26,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_system_return Cortex-M/IAR */ -/* 6.1.5 */ +/* _tx_thread_system_return Cortex-M33/IAR */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -59,14 +59,13 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 03-02-2021 Scott Larson Initial Version 6.1.5 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) // { PUBLIC _tx_thread_system_return _tx_thread_system_return: - /* Return to real scheduler via PendSV. Note that this routine is often replaced with in-line assembly in tx_port.h to improved performance. */ @@ -76,11 +75,17 @@ _tx_thread_system_return: MRS r0, IPSR // Pickup IPSR CMP r0, #0 // Is it a thread returning? BNE _isr_context // If ISR, skip interrupt enable +#ifdef TX_PORT_USE_BASEPRI + MRS r1, BASEPRI // Thread context returning, pickup BASEPRI + MOV r0, #0 + MSR BASEPRI, r0 // Enable interrupts + MSR BASEPRI, r1 // Restore original interrupt posture +#else MRS r1, PRIMASK // Thread context returning, pickup PRIMASK CPSIE i // Enable interrupts MSR PRIMASK, r1 // Restore original interrupt posture +#endif _isr_context: BX lr // Return to caller - // } END diff --git a/ports_module/cortex_m33/iar/module_manager/src/tx_timer_interrupt.s b/ports_module/cortex_m33/iar/module_manager/src/tx_timer_interrupt.s index c2dfae5c..f13e9f0f 100644 --- a/ports_module/cortex_m33/iar/module_manager/src/tx_timer_interrupt.s +++ b/ports_module/cortex_m33/iar/module_manager/src/tx_timer_interrupt.s @@ -39,8 +39,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_timer_interrupt Cortex-M/IAR */ -/* 6.1.5 */ +/* _tx_timer_interrupt Cortex-M33/IAR */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -73,7 +73,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 03-02-2021 Scott Larson Initial Version 6.1.5 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) @@ -188,7 +188,7 @@ __tx_timer_done: __tx_something_expired: - STMDB sp!, {r0, lr} // Save the lr register on the stack + PUSH {r0, lr} // Save the lr register on the stack // and save r0 just to keep 8-byte alignment /* Did a timer expire? */ @@ -234,12 +234,11 @@ __tx_timer_dont_activate: BEQ __tx_timer_skip_time_slice // If the same, there was no time-slice performed STR r2, [r0] // Not the same, issue the PendSV for preemption __tx_timer_skip_time_slice: - // } __tx_timer_not_ts_expiration: - LDMIA sp!, {r0, lr} // Recover lr register (r0 is just there for + POP {r0, lr} // Recover lr register (r0 is just there for // the 8-byte stack alignment // } @@ -248,6 +247,5 @@ __tx_timer_nothing_expired: DSB // Complete all memory access BX lr // Return to caller - // } END diff --git a/ports_module/cortex_m33/iar/module_manager/src/txe_thread_secure_stack_allocate.c b/ports_module/cortex_m33/iar/module_manager/src/txe_thread_secure_stack_allocate.c index 3ff6fa68..aaddb639 100644 --- a/ports_module/cortex_m33/iar/module_manager/src/txe_thread_secure_stack_allocate.c +++ b/ports_module/cortex_m33/iar/module_manager/src/txe_thread_secure_stack_allocate.c @@ -33,8 +33,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_secure_stack_allocate PORTABLE C */ -/* 6.1 */ +/* _tx_thread_secure_stack_allocate Cortex-M33 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -68,7 +68,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txe_thread_secure_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size) @@ -84,7 +84,6 @@ UINT status; /* Check for an invalid thread pointer. */ if (thread_ptr == TX_NULL) { - /* Thread pointer is invalid, return appropriate error code. */ status = TX_THREAD_ERROR; } @@ -92,7 +91,6 @@ UINT status; /* Now check for invalid thread ID. */ else if (thread_ptr -> tx_thread_id != TX_THREAD_ID) { - /* Thread pointer is invalid, return appropriate error code. */ status = TX_THREAD_ERROR; } @@ -111,7 +109,6 @@ UINT status; /* Determine if everything is okay. */ if (status == TX_SUCCESS) { - /* Call actual secure stack allocate function. */ status = _tx_thread_secure_stack_allocate(thread_ptr, stack_size); } @@ -120,4 +117,3 @@ UINT status; return(status); #endif } - diff --git a/ports_module/cortex_m33/iar/module_manager/src/txe_thread_secure_stack_free.c b/ports_module/cortex_m33/iar/module_manager/src/txe_thread_secure_stack_free.c index f8207c68..2c73a8e6 100644 --- a/ports_module/cortex_m33/iar/module_manager/src/txe_thread_secure_stack_free.c +++ b/ports_module/cortex_m33/iar/module_manager/src/txe_thread_secure_stack_free.c @@ -33,8 +33,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _txe_thread_secure_stack_free PORTABLE C */ -/* 6.1 */ +/* _txe_thread_secure_stack_free Cortex-M33 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -66,7 +66,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txe_thread_secure_stack_free(TX_THREAD *thread_ptr) @@ -118,4 +118,3 @@ UINT status; return(status); #endif } - diff --git a/ports_module/cortex_m33/iar/module_manager/src/txm_module_manager_alignment_adjust.c b/ports_module/cortex_m33/iar/module_manager/src/txm_module_manager_alignment_adjust.c index 19f65bfc..8cb93534 100644 --- a/ports_module/cortex_m33/iar/module_manager/src/txm_module_manager_alignment_adjust.c +++ b/ports_module/cortex_m33/iar/module_manager/src/txm_module_manager_alignment_adjust.c @@ -30,8 +30,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _txm_module_manager_alignment_adjust Cortex-M33/MPU/IAR */ -/* 6.1.5 */ +/* _txm_module_manager_alignment_adjust Cortex-M33 */ +/* 6.1.8 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -65,7 +65,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 03-02-2021 Scott Larson Initial Version 6.1.5 */ +/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ /* */ /**************************************************************************/ VOID _txm_module_manager_alignment_adjust(TXM_MODULE_PREAMBLE *module_preamble, diff --git a/ports_module/cortex_m33/iar/module_manager/src/txm_module_manager_external_memory_enable.c b/ports_module/cortex_m33/iar/module_manager/src/txm_module_manager_external_memory_enable.c index dca26152..67bc7196 100644 --- a/ports_module/cortex_m33/iar/module_manager/src/txm_module_manager_external_memory_enable.c +++ b/ports_module/cortex_m33/iar/module_manager/src/txm_module_manager_external_memory_enable.c @@ -33,8 +33,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _txm_module_manager_external_memory_enable Cortex-M33/MPU/IAR */ -/* 6.1.5 */ +/* _txm_module_manager_external_memory_enable Cortex-M33 */ +/* 6.1.8 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -68,7 +68,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 03-02-2021 Scott Larson Initial Version 6.1.5 */ +/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ /* */ /**************************************************************************/ UINT _txm_module_manager_external_memory_enable(TXM_MODULE_INSTANCE *module_instance, diff --git a/ports_module/cortex_m33/iar/module_manager/src/txm_module_manager_memory_fault_handler.c b/ports_module/cortex_m33/iar/module_manager/src/txm_module_manager_memory_fault_handler.c index 0b974872..0ed0c212 100644 --- a/ports_module/cortex_m33/iar/module_manager/src/txm_module_manager_memory_fault_handler.c +++ b/ports_module/cortex_m33/iar/module_manager/src/txm_module_manager_memory_fault_handler.c @@ -45,8 +45,8 @@ TXM_MODULE_MANAGER_FAULT_INFO /* */ /* FUNCTION RELEASE */ /* */ -/* _txm_module_manager_memory_fault_handler Cortex-M33/MPU/IAR */ -/* 6.1.5 */ +/* _txm_module_manager_memory_fault_handler Cortex-M33 */ +/* 6.1.8 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -76,7 +76,7 @@ TXM_MODULE_MANAGER_FAULT_INFO /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 03-02-2021 Scott Larson Initial Version 6.1.5 */ +/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ /* */ /**************************************************************************/ VOID _txm_module_manager_memory_fault_handler(VOID) diff --git a/ports_module/cortex_m33/iar/module_manager/src/txm_module_manager_memory_fault_notify.c b/ports_module/cortex_m33/iar/module_manager/src/txm_module_manager_memory_fault_notify.c index 618a699e..88baa804 100644 --- a/ports_module/cortex_m33/iar/module_manager/src/txm_module_manager_memory_fault_notify.c +++ b/ports_module/cortex_m33/iar/module_manager/src/txm_module_manager_memory_fault_notify.c @@ -38,8 +38,8 @@ extern VOID (*_txm_module_manager_fault_notify)(TX_THREAD *, TXM_MODULE_INSTA /* */ /* FUNCTION RELEASE */ /* */ -/* _txm_module_manager_memory_fault_notify Cortex-M33/MPU/IAR */ -/* 6.1.5 */ +/* _txm_module_manager_memory_fault_notify Cortex-M33 */ +/* 6.1.8 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -71,7 +71,7 @@ extern VOID (*_txm_module_manager_fault_notify)(TX_THREAD *, TXM_MODULE_INSTA /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 03-02-2021 Scott Larson Initial Version 6.1.5 */ +/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ /* */ /**************************************************************************/ UINT _txm_module_manager_memory_fault_notify(VOID (*notify_function)(TX_THREAD *, TXM_MODULE_INSTANCE *)) diff --git a/ports_module/cortex_m33/iar/module_manager/src/txm_module_manager_mm_register_setup.c b/ports_module/cortex_m33/iar/module_manager/src/txm_module_manager_mm_register_setup.c index 4bd99c30..5ad546a3 100644 --- a/ports_module/cortex_m33/iar/module_manager/src/txm_module_manager_mm_register_setup.c +++ b/ports_module/cortex_m33/iar/module_manager/src/txm_module_manager_mm_register_setup.c @@ -29,7 +29,7 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _txm_module_manager_mm_register_setup Cortex-M33/Generic */ +/* _txm_module_manager_mm_register_setup Cortex-M33 */ /* 6.1.6 */ /* AUTHOR */ /* */ @@ -123,7 +123,7 @@ ULONG callback_stack_size; /* */ /* FUNCTION RELEASE */ /* */ -/* _txm_module_manager_inside_data_check Cortex-M33/Generic */ +/* _txm_module_manager_inside_data_check Cortex-M33 */ /* 6.1.6 */ /* AUTHOR */ /* */ diff --git a/ports_module/cortex_m33/iar/module_manager/src/txm_module_manager_port_dispatch.c b/ports_module/cortex_m33/iar/module_manager/src/txm_module_manager_port_dispatch.c index 7c7e01ea..977107d1 100644 --- a/ports_module/cortex_m33/iar/module_manager/src/txm_module_manager_port_dispatch.c +++ b/ports_module/cortex_m33/iar/module_manager/src/txm_module_manager_port_dispatch.c @@ -30,8 +30,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _txm_module_manager_port_dispatch Cortex-M33/IAR */ -/* 6.1.5 */ +/* _txm_module_manager_port_dispatch Cortex-M33 */ +/* 6.1.8 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -65,7 +65,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 03-02-2021 Scott Larson Initial Version 6.1.5 */ +/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ /* */ /**************************************************************************/ ALIGN_TYPE _txm_module_manager_port_dispatch(TXM_MODULE_INSTANCE *module_instance, ULONG kernel_request, ALIGN_TYPE param_0, ALIGN_TYPE param_1, ALIGN_TYPE param_2) diff --git a/ports_module/cortex_m33/iar/module_manager/src/txm_module_manager_thread_stack_build.s b/ports_module/cortex_m33/iar/module_manager/src/txm_module_manager_thread_stack_build.s index b10b9c97..d2d5e91b 100644 --- a/ports_module/cortex_m33/iar/module_manager/src/txm_module_manager_thread_stack_build.s +++ b/ports_module/cortex_m33/iar/module_manager/src/txm_module_manager_thread_stack_build.s @@ -26,8 +26,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _txm_module_manager_thread_stack_build Cortex-M33/MPU/IAR */ -/* 6.1.5 */ +/* _txm_module_manager_thread_stack_build Cortex-M33/IAR */ +/* 6.1.8 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -59,7 +59,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 03-02-2021 Scott Larson Initial Version 6.1.5 */ +/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ /* */ /**************************************************************************/ // VOID _txm_module_manager_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(TX_THREAD *, TXM_MODULE_INSTANCE *)) |