diff options
Diffstat (limited to 'ports_module/cortex_m4/ac5')
20 files changed, 176 insertions, 137 deletions
diff --git a/ports_module/cortex_m4/ac5/example_build/tx_initialize_low_level.S b/ports_module/cortex_m4/ac5/example_build/tx_initialize_low_level.S index c06f4b07..15238789 100644 --- a/ports_module/cortex_m4/ac5/example_build/tx_initialize_low_level.S +++ b/ports_module/cortex_m4/ac5/example_build/tx_initialize_low_level.S @@ -135,8 +135,8 @@ Reset_Handler /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 11-09-2020 Scott Larson Modified comment(s), */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 11-09-2020 Scott Larson Modified comment(s), */ /* resulting in version 6.1.2 */ /* */ /**************************************************************************/ diff --git a/ports_module/cortex_m4/ac5/inc/txm_module_port.h b/ports_module/cortex_m4/ac5/inc/txm_module_port.h index b9d2ea5b..443935e7 100644 --- a/ports_module/cortex_m4/ac5/inc/txm_module_port.h +++ b/ports_module/cortex_m4/ac5/inc/txm_module_port.h @@ -40,11 +40,11 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 11-09-2020 Scott Larson Modified comment(s), */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 11-09-2020 Scott Larson Modified comment(s), */ /* increase kernel stack size, */ /* resulting in version 6.1.2 */ -/* 04-02-2021 Scott Larson Modified comment(s), */ +/* 04-02-2021 Scott Larson Modified comment(s), */ /* added check for overflow, */ /* resulting in version 6.1.6 */ /* */ @@ -107,6 +107,21 @@ The following extensions must also be defined in tx_port.h: #define TXM_MODULE_KERNEL_STACK_SIZE 768 #endif +/* For the following 3 access control settings, change TEX and C, B, S (bits 21 through 16 of MPU_RASR) + * to reflect your system memory attributes (cache, shareable, memory type). */ +/* Code region access control: privileged read-only, outer & inner write-back, normal memory, shareable. */ +#ifndef TXM_MODULE_MPU_CODE_ACCESS_CONTROL +#define TXM_MODULE_MPU_CODE_ACCESS_CONTROL 0x06070000 +#endif +/* Data region access control: execute never, read/write, outer & inner write-back, normal memory, shareable. */ +#ifndef TXM_MODULE_MPU_DATA_ACCESS_CONTROL +#define TXM_MODULE_MPU_DATA_ACCESS_CONTROL 0x13070000 +#endif +/* Shared region access control: execute never, read-only, outer & inner write-back, normal memory, shareable. */ +#ifndef TXM_MODULE_MPU_SHARED_ACCESS_CONTROL +#define TXM_MODULE_MPU_SHARED_ACCESS_CONTROL 0x12070000 +#endif + /* Define constants specific to the tools the module can be built with for this particular modules port. */ #define TXM_MODULE_IAR_COMPILER 0x00000000 diff --git a/ports_module/cortex_m4/ac5/module_lib/src/txm_module_initialize.S b/ports_module/cortex_m4/ac5/module_lib/src/txm_module_initialize.S index e965b809..f3952da6 100644 --- a/ports_module/cortex_m4/ac5/module_lib/src/txm_module_initialize.S +++ b/ports_module/cortex_m4/ac5/module_lib/src/txm_module_initialize.S @@ -59,8 +59,8 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 11-09-2020 Scott Larson Modified comment(s), */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 11-09-2020 Scott Larson Modified comment(s), */ /* resulting in version 6.1.2 */ /* */ /**************************************************************************/ diff --git a/ports_module/cortex_m4/ac5/module_lib/src/txm_module_thread_shell_entry.c b/ports_module/cortex_m4/ac5/module_lib/src/txm_module_thread_shell_entry.c index 490b35db..33b1e5a5 100644 --- a/ports_module/cortex_m4/ac5/module_lib/src/txm_module_thread_shell_entry.c +++ b/ports_module/cortex_m4/ac5/module_lib/src/txm_module_thread_shell_entry.c @@ -90,7 +90,7 @@ __align(8) UCHAR txm_heap[TXM_MODULE_HEAP_SIZE]; /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_ENTRY_INFO *thread_info) @@ -107,14 +107,14 @@ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_EN { /* Initialize the ARM C environment. */ _txm_module_initialize(); - + /* Save the entry info pointer, for later use. */ _txm_module_entry_info = thread_info; - + /* Save the kernel function dispatch address. This is used to make all resident calls from the module. */ _txm_module_kernel_call_dispatcher = thread_info -> txm_module_thread_entry_info_kernel_call_dispatcher; - + /* Ensure that we have a valid pointer. */ while (!_txm_module_kernel_call_dispatcher) { diff --git a/ports_module/cortex_m4/ac5/module_manager/src/tx_thread_context_restore.S b/ports_module/cortex_m4/ac5/module_manager/src/tx_thread_context_restore.S index 65f7d711..1159ea66 100644 --- a/ports_module/cortex_m4/ac5/module_manager/src/tx_thread_context_restore.S +++ b/ports_module/cortex_m4/ac5/module_manager/src/tx_thread_context_restore.S @@ -20,9 +20,9 @@ /**************************************************************************/ /**************************************************************************/ - IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) IMPORT _tx_execution_isr_exit - ENDIF +#endif AREA ||.text||, CODE, READONLY PRESERVE8 @@ -30,11 +30,11 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_context_restore Cortex-M4/AC5 */ -/* 6.1.2 */ +/* _tx_thread_context_restore Cortex-Mx/AC5 */ +/* 6.1.8 */ /* AUTHOR */ /* */ -/* William E. Lamie, Microsoft Corporation */ +/* Scott Larson, Microsoft Corporation */ /* */ /* DESCRIPTION */ /* */ @@ -51,7 +51,7 @@ /* */ /* CALLS */ /* */ -/* None */ +/* [_tx_execution_isr_exit] Execution profiling ISR exit */ /* */ /* CALLED BY */ /* */ @@ -61,9 +61,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 11-09-2020 Scott Larson Modified comment(s), */ -/* resulting in version 6.1.2 */ +/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ /* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) @@ -71,14 +69,13 @@ EXPORT _tx_thread_context_restore _tx_thread_context_restore - IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) /* Call the ISR exit function to indicate an ISR is complete. */ - PUSH {r0,lr} // Save ISR lr + PUSH {r0, lr} // Save return address BL _tx_execution_isr_exit // Call the ISR exit function - POP {r0,lr} // Restore ISR lr - ENDIF + POP {r0, lr} // Recover return address +#endif - POP {lr} BX lr // } ALIGN diff --git a/ports_module/cortex_m4/ac5/module_manager/src/tx_thread_context_save.S b/ports_module/cortex_m4/ac5/module_manager/src/tx_thread_context_save.S index c05300fe..d8ee75a4 100644 --- a/ports_module/cortex_m4/ac5/module_manager/src/tx_thread_context_save.S +++ b/ports_module/cortex_m4/ac5/module_manager/src/tx_thread_context_save.S @@ -20,9 +20,9 @@ /**************************************************************************/ /**************************************************************************/ - IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) IMPORT _tx_execution_isr_enter - ENDIF +#endif AREA ||.text||, CODE, READONLY PRESERVE8 @@ -30,11 +30,11 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_context_save Cortex-M4/AC5 */ -/* 6.1.2 */ +/* _tx_thread_context_save Cortex-Mx/AC5 */ +/* 6.1.8 */ /* AUTHOR */ /* */ -/* William E. Lamie, Microsoft Corporation */ +/* Scott Larson, Microsoft Corporation */ /* */ /* DESCRIPTION */ /* */ @@ -51,7 +51,7 @@ /* */ /* CALLS */ /* */ -/* None */ +/* [_tx_execution_isr_enter] Execution profiling ISR enter */ /* */ /* CALLED BY */ /* */ @@ -61,9 +61,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 11-09-2020 Scott Larson Modified comment(s), */ -/* resulting in version 6.1.2 */ +/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ /* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) @@ -71,16 +69,16 @@ EXPORT _tx_thread_context_save _tx_thread_context_save - IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY - /* Call the ISR enter function to indicate an ISR is executing. */ - PUSH {r0, lr} // Save ISR lr +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) + /* Call the ISR enter function to indicate an ISR is starting. */ + PUSH {r0, lr} // Save return address BL _tx_execution_isr_enter // Call the ISR enter function - POP {r0, lr} // Recover ISR lr - ENDIF + POP {r0, lr} // Recover return address +#endif - /* Return to interrupt processing. */ + /* Context is already saved - just return. */ - BX lr // Return to interrupt processing caller + BX lr // } ALIGN LTORG diff --git a/ports_module/cortex_m4/ac5/module_manager/src/tx_thread_interrupt_control.S b/ports_module/cortex_m4/ac5/module_manager/src/tx_thread_interrupt_control.S index 3c574171..4c5e1c33 100644 --- a/ports_module/cortex_m4/ac5/module_manager/src/tx_thread_interrupt_control.S +++ b/ports_module/cortex_m4/ac5/module_manager/src/tx_thread_interrupt_control.S @@ -25,11 +25,11 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_interrupt_control Cortex-M4/AC5 */ -/* 6.1.2 */ +/* _tx_thread_interrupt_control Cortex-Mx/AC5 */ +/* 6.1.8 */ /* AUTHOR */ /* */ -/* William E. Lamie, Microsoft Corporation */ +/* Scott Larson, Microsoft Corporation */ /* */ /* DESCRIPTION */ /* */ @@ -56,19 +56,22 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 11-09-2020 Scott Larson Modified comment(s), */ -/* resulting in version 6.1.2 */ +/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ /* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) // { EXPORT _tx_thread_interrupt_control _tx_thread_interrupt_control +#ifdef TX_PORT_USE_BASEPRI + MRS r1, BASEPRI // Pickup current interrupt posture + MSR BASEPRI, r0 // Apply the new interrupt posture + MOV r0, r1 // Transfer old to return register +#else MRS r1, PRIMASK // Pickup current interrupt lockout MSR PRIMASK, r0 // Apply the new interrupt lockout MOV r0, r1 // Transfer old to return register +#endif BX lr // Return to caller - // } END diff --git a/ports_module/cortex_m4/ac5/module_manager/src/tx_thread_interrupt_disable.S b/ports_module/cortex_m4/ac5/module_manager/src/tx_thread_interrupt_disable.S index cee8330d..88e6a864 100644 --- a/ports_module/cortex_m4/ac5/module_manager/src/tx_thread_interrupt_disable.S +++ b/ports_module/cortex_m4/ac5/module_manager/src/tx_thread_interrupt_disable.S @@ -25,11 +25,11 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_interrupt_disable Cortex-M4/AC5 */ -/* 6.1.2 */ +/* _tx_thread_interrupt_disable Cortex-Mx/AC5 */ +/* 6.1.8 */ /* AUTHOR */ /* */ -/* William E. Lamie, Microsoft Corporation */ +/* Scott Larson, Microsoft Corporation */ /* */ /* DESCRIPTION */ /* */ @@ -38,11 +38,11 @@ /* */ /* INPUT */ /* */ -/* old_posture Old interrupt lockout posture */ +/* None */ /* */ /* OUTPUT */ /* */ -/* None */ +/* old_posture Old interrupt lockout posture */ /* */ /* CALLS */ /* */ @@ -56,21 +56,22 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 11-09-2020 Scott Larson Modified comment(s), */ -/* resulting in version 6.1.2 */ +/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ /* */ /**************************************************************************/ -// UINT _tx_thread_interrupt_disable(UINT new_posture) +// UINT _tx_thread_interrupt_disable(VOID) // { EXPORT _tx_thread_interrupt_disable _tx_thread_interrupt_disable - /* Return current interrupt lockout posture. */ - +#ifdef TX_PORT_USE_BASEPRI + MRS r0, BASEPRI + LDR r1, =TX_PORT_BASEPRI + MSR BASEPRI, r1 +#else MRS r0, PRIMASK CPSID i +#endif BX lr - // } END diff --git a/ports_module/cortex_m4/ac5/module_manager/src/tx_thread_interrupt_restore.S b/ports_module/cortex_m4/ac5/module_manager/src/tx_thread_interrupt_restore.S index 9287a2e8..22340c21 100644 --- a/ports_module/cortex_m4/ac5/module_manager/src/tx_thread_interrupt_restore.S +++ b/ports_module/cortex_m4/ac5/module_manager/src/tx_thread_interrupt_restore.S @@ -25,11 +25,11 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_interrupt_restore Cortex-M4/AC5 */ -/* 6.1.2 */ +/* _tx_thread_interrupt_restore Cortex-Mx/AC5 */ +/* 6.1.8 */ /* AUTHOR */ /* */ -/* William E. Lamie, Microsoft Corporation */ +/* Scott Larson, Microsoft Corporation */ /* */ /* DESCRIPTION */ /* */ @@ -38,11 +38,11 @@ /* */ /* INPUT */ /* */ -/* None */ +/* previous_posture Previous interrupt posture */ /* */ /* OUTPUT */ /* */ -/* previous_posture Previous interrupt posture */ +/* None */ /* */ /* CALLS */ /* */ @@ -56,20 +56,20 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 11-09-2020 Scott Larson Modified comment(s), */ -/* resulting in version 6.1.2 */ +/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ /* */ /**************************************************************************/ -// VOID _tx_thread_interrupt_restore(UINT new_posture) +// VOID _tx_thread_interrupt_restore(UINT previous_posture) // { EXPORT _tx_thread_interrupt_restore _tx_thread_interrupt_restore /* Restore previous interrupt lockout posture. */ - +#ifdef TX_PORT_USE_BASEPRI + MSR BASEPRI, r0 +#else MSR PRIMASK, r0 +#endif BX lr - // } END diff --git a/ports_module/cortex_m4/ac5/module_manager/src/tx_thread_schedule.S b/ports_module/cortex_m4/ac5/module_manager/src/tx_thread_schedule.S index 04b90b44..71275358 100644 --- a/ports_module/cortex_m4/ac5/module_manager/src/tx_thread_schedule.S +++ b/ports_module/cortex_m4/ac5/module_manager/src/tx_thread_schedule.S @@ -23,15 +23,15 @@ IMPORT _tx_thread_current_ptr IMPORT _tx_thread_execute_ptr IMPORT _tx_timer_time_slice - IF :DEF: TX_ENABLE_EXECUTION_CHANGE_NOTIFY +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) IMPORT _tx_execution_thread_enter IMPORT _tx_execution_thread_exit - ENDIF +#endif IMPORT _tx_thread_preempt_disable IMPORT _txm_module_manager_memory_fault_handler IMPORT _txm_module_manager_memory_fault_info - IMPORT _txm_module_priv - IMPORT _txm_module_user_mode_exit + IMPORT _txm_module_priv + IMPORT _txm_module_user_mode_exit AREA ||.text||, CODE, READONLY THUMB @@ -90,7 +90,7 @@ _tx_thread_schedule /* This function should only ever be called on Cortex-M from the first schedule request. Subsequent scheduling occurs - from the PendSV handling routines below. */ + from the PendSV handling routine below. */ /* Clear the preempt-disable flag to enable rescheduling after initialization on Cortex-M targets. */ @@ -98,22 +98,19 @@ _tx_thread_schedule LDR r2, =_tx_thread_preempt_disable // Build address of preempt disable flag STR r0, [r2, #0] // Clear preempt disable flag - /* Clear CONTROL.FPCA bit so FPU registers aren't unnecessarily stacked. */ - - IF {TARGET_FPU_VFP} = {TRUE} +#ifdef __TARGET_FPU_VFP + /* Clear CONTROL.FPCA bit so VFP registers aren't unnecessarily stacked. */ MRS r0, CONTROL // Pickup current CONTROL register BIC r0, r0, #4 // Clear the FPCA bit MSR CONTROL, r0 // Setup new CONTROL register - ENDIF +#endif /* Enable memory fault registers. */ - LDR r0, =0xE000ED24 // Build SHCSR address LDR r1, =0x70000 // Enable Usage, Bus, and MemManage faults STR r1, [r0] // /* Enable interrupts */ - CPSIE i /* Enter the scheduler for the first time. */ @@ -135,7 +132,6 @@ __tx_wait_here EXPORT MemManage_Handler MemManage_Handler - CPSID i // Disable interrupts /* Now pickup and store all the fault related information. */ @@ -194,21 +190,21 @@ MemManage_Handler // Bit 7 = 1 -> MMFAR is valid STRB r1, [r0] // Clear the MMFSR - IF {TARGET_FPU_VFP} = {TRUE} +#ifdef __TARGET_FPU_VFP LDR r0, =0xE000EF34 // Cleanup FPU context: Load FPCCR address LDR r1, [r0] // Load FPCCR BIC r1, r1, #1 // Clear the lazy preservation active bit - STR r1, [r0] // Store the value - ENDIF + STR r1, [r0] // Save FPCCR +#endif BL _txm_module_manager_memory_fault_handler // Call memory manager fault handler - IF :DEF: TX_ENABLE_EXECUTION_CHANGE_NOTIFY +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) /* Call the thread exit function to indicate the thread is no longer executing. */ CPSID i // Disable interrupts BL _tx_execution_thread_exit // Call the thread exit function CPSIE i // Enable interrupts - ENDIF +#endif MOV r1, #0 // Build NULL value LDR r0, =_tx_thread_current_ptr // Pickup address of current thread pointer @@ -235,14 +231,14 @@ __tx_PendSVHandler __tx_ts_handler - IF :DEF: TX_ENABLE_EXECUTION_CHANGE_NOTIFY +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) /* Call the thread exit function to indicate the thread is no longer executing. */ CPSID i // Disable interrupts PUSH {r0, lr} // Save LR (and r0 just for alignment) BL _tx_execution_thread_exit // Call the thread exit function POP {r0, lr} // Recover LR CPSIE i // Enable interrupts - ENDIF +#endif LDR r0, =_tx_thread_current_ptr // Build current thread pointer address LDR r2, =_tx_thread_execute_ptr // Build execute thread pointer address @@ -258,12 +254,12 @@ __tx_ts_handler STR r3, [r0] // Set _tx_thread_current_ptr to NULL MRS r12, PSP // Pickup PSP pointer (thread's stack pointer) STMDB r12!, {r4-r11} // Save its remaining registers - IF {TARGET_FPU_VFP} = {TRUE} +#ifdef __TARGET_FPU_VFP TST LR, #0x10 // Determine if the VFP extended frame is present BNE _skip_vfp_save VSTMDB r12!,{s16-s31} // Yes, save additional VFP registers _skip_vfp_save - ENDIF +#endif LDR r4, =_tx_timer_time_slice // Build address of time-slice variable STMDB r12!, {LR} // Save LR on the stack @@ -335,12 +331,12 @@ __tx_ts_restore STR r5, [r4] // Setup global time-slice - IF :DEF: TX_ENABLE_EXECUTION_CHANGE_NOTIFY +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) /* Call the thread entry function to indicate the thread is executing. */ PUSH {r0, r1} // Save r0 and r1 BL _tx_execution_thread_enter // Call the thread execution enter function POP {r0, r1} // Recover r0 and r1 - ENDIF +#endif /* Restore the thread context and PSP. */ @@ -372,12 +368,12 @@ __tx_ts_restore STR r1, [r0] // Enable MPU skip_mpu_setup LDMIA r12!, {LR} // Pickup LR - IF {TARGET_FPU_VFP} = {TRUE} +#ifdef __TARGET_FPU_VFP TST LR, #0x10 // Determine if the VFP extended frame is present BNE _skip_vfp_restore // If not, skip VFP restore VLDMIA r12!, {s16-s31} // Yes, restore additional VFP registers _skip_vfp_restore - ENDIF +#endif LDMIA r12!, {r4-r11} // Recover thread's registers MSR PSP, r12 // Setup the thread's stack pointer @@ -425,22 +421,26 @@ __tx_SVCallHandler /* Switch to the module thread's kernel stack */ LDR r0, [r2, #0xA8] // Load the module kernel stack end - IF :LNOT: :DEF: TXM_MODULE_KERNEL_STACK_MAINTENANCE_DISABLE +#ifndef TXM_MODULE_KERNEL_STACK_MAINTENANCE_DISABLE LDR r1, [r2, #0xA4] // Load the module kernel stack start LDR r3, [r2, #0xAC] // Load the module kernel stack size STR r1, [r2, #12] // Set stack start STR r0, [r2, #16] // Set stack end STR r3, [r2, #20] // Set stack size - ENDIF +#endif MRS r3, PSP // Pickup thread stack pointer +#ifdef __TARGET_FPU_VFP TST lr, #0x10 // Test for extended module stack ITT EQ ORREQ r3, r3, #1 // If so, set LSB in thread stack pointer to indicate extended frame ORREQ lr, lr, #0x10 // Set bit, return with standard frame +#endif STR r3, [r2, #0xB0] // Save thread stack pointer +#ifdef __TARGET_FPU_VFP BIC r3, #1 // Clear possibly OR'd bit - +#endif + /* Build kernel stack by copying thread stack two registers at a time */ ADD r3, r3, #32 // Start at bottom of hardware stack LDMDB r3!, {r1-r2} @@ -478,21 +478,46 @@ _tx_thread_user_return TST r0, #2 // Check if memory protected BEQ _tx_skip_kernel_stack_exit - IF :LNOT: :DEF: TXM_MODULE_KERNEL_STACK_MAINTENANCE_DISABLE +#ifndef TXM_MODULE_KERNEL_STACK_MAINTENANCE_DISABLE LDR r0, [r2, #0xB4] // Load the module thread stack start LDR r1, [r2, #0xB8] // Load the module thread stack end LDR r3, [r2, #0xBC] // Load the module thread stack size STR r0, [r2, #12] // Set stack start STR r1, [r2, #16] // Set stack end STR r3, [r2, #20] // Set stack size - ENDIF +#endif + +#ifdef __TARGET_FPU_VFP + /* If lazy stacking is pending, check if it can be cleared. + if(LSPACT && tx_thread_module_stack_start < FPCAR && FPCAR < tx_thread_module_stack_end) + then clear LSPACT. */ + LDR r3, =0xE000EF34 // Address of FPCCR + LDR r3, [r3] // Load FPCCR + TST r3, #1 // Check if LSPACT is set + BEQ _tx_no_lazy_clear // if clear, move on + LDR r1, =0xE000EF38 // Address of FPCAR + LDR r1, [r1] // Load FPCAR + LDR r0, [r2, #0xA4] // Load kernel stack start + CMP r1, r0 // If FPCAR < start, move on + BLO _tx_no_lazy_clear + LDR r0, [r2, #0xA8] // Load kernel stack end + CMP r0, r1 // If end < FPCAR, move on + BLO _tx_no_lazy_clear + BIC r3, #1 // Clear LSPACT + LDR r1, =0xE000EF34 // Address of FPCCR + STR r3, [r1] // Save updated FPCCR +_tx_no_lazy_clear: +#endif + LDR r0, [r2, #0xB0] // Load the module thread stack pointer MRS r3, PSP // Pickup kernel stack pointer +#ifdef __TARGET_FPU_VFP TST r0, #1 // Is module stack extended? ITTE NE // If so... BICNE lr, #0x10 // Clear bit, return with extended frame BICNE r0, #1 // Clear bit that indicates extended module frame ORREQ lr, lr, #0x10 // Else set bit, return with standard frame +#endif /* Copy kernel hardware stack to module thread stack. */ LDM r3!, {r1-r2} @@ -516,7 +541,7 @@ _tx_skip_kernel_stack_exit MSR CONTROL, r0 // Setup new CONTROL register BX lr // Return to thread - IF {TARGET_FPU_VFP} = {TRUE} +#ifdef __TARGET_FPU_VFP EXPORT tx_thread_fpu_enable tx_thread_fpu_enable EXPORT tx_thread_fpu_disable @@ -526,13 +551,13 @@ tx_thread_fpu_disable backward compatibility purposes and therefore simply returns. */ BX LR // Return to caller - + EXPORT _tx_vfp_access _tx_vfp_access VMOV.F32 s0, s0 // Simply access the VFP BX lr // Return to caller - - ENDIF + +#endif ALIGN 4 END diff --git a/ports_module/cortex_m4/ac5/module_manager/src/tx_thread_stack_build.S b/ports_module/cortex_m4/ac5/module_manager/src/tx_thread_stack_build.S index 0ccd8d6f..11effa55 100644 --- a/ports_module/cortex_m4/ac5/module_manager/src/tx_thread_stack_build.S +++ b/ports_module/cortex_m4/ac5/module_manager/src/tx_thread_stack_build.S @@ -25,11 +25,11 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_stack_build Cortex-M4/AC5 */ -/* 6.1.2 */ +/* _tx_thread_stack_build Cortex-Mx/AC5 */ +/* 6.1.8 */ /* AUTHOR */ /* */ -/* William E. Lamie, Microsoft Corporation */ +/* Scott Larson, Microsoft Corporation */ /* */ /* DESCRIPTION */ /* */ @@ -58,9 +58,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 11-09-2020 Scott Larson Modified comment(s), */ -/* resulting in version 6.1.2 */ +/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ /* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) diff --git a/ports_module/cortex_m4/ac5/module_manager/src/tx_thread_system_return.S b/ports_module/cortex_m4/ac5/module_manager/src/tx_thread_system_return.S index fd7eec6b..0ab4ae36 100644 --- a/ports_module/cortex_m4/ac5/module_manager/src/tx_thread_system_return.S +++ b/ports_module/cortex_m4/ac5/module_manager/src/tx_thread_system_return.S @@ -25,11 +25,11 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_system_return Cortex-M4/AC5 */ -/* 6.1.2 */ +/* _tx_thread_system_return Cortex-Mx/AC5 */ +/* 6.1.8 */ /* AUTHOR */ /* */ -/* William E. Lamie, Microsoft Corporation */ +/* Scott Larson, Microsoft Corporation */ /* */ /* DESCRIPTION */ /* */ @@ -58,9 +58,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 11-09-2020 Scott Larson Modified comment(s), */ -/* resulting in version 6.1.2 */ +/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ /* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) @@ -77,11 +75,17 @@ _tx_thread_system_return MRS r0, IPSR // Pickup IPSR CMP r0, #0 // Is it a thread returning? BNE _isr_context // If ISR, skip interrupt enable +#ifdef TX_PORT_USE_BASEPRI + MRS r1, BASEPRI // Thread context returning, pickup BASEPRI + MOV r0, #0 + MSR BASEPRI, r0 // Enable interrupts + MSR BASEPRI, r1 // Restore original interrupt posture +#else MRS r1, PRIMASK // Thread context returning, pickup PRIMASK CPSIE i // Enable interrupts MSR PRIMASK, r1 // Restore original interrupt posture +#endif _isr_context BX lr // Return to caller - // } END diff --git a/ports_module/cortex_m4/ac5/module_manager/src/tx_timer_interrupt.S b/ports_module/cortex_m4/ac5/module_manager/src/tx_timer_interrupt.S index b1a58dd9..12fef571 100644 --- a/ports_module/cortex_m4/ac5/module_manager/src/tx_timer_interrupt.S +++ b/ports_module/cortex_m4/ac5/module_manager/src/tx_timer_interrupt.S @@ -39,11 +39,11 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_timer_interrupt Cortex-M4/AC5 */ -/* 6.1.2 */ +/* _tx_timer_interrupt Cortex-Mx/AC5 */ +/* 6.1.8 */ /* AUTHOR */ /* */ -/* William E. Lamie, Microsoft Corporation */ +/* Scott Larson, Microsoft Corporation */ /* */ /* DESCRIPTION */ /* */ @@ -73,9 +73,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 11-09-2020 Scott Larson Modified comment(s), */ -/* resulting in version 6.1.2 */ +/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ /* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) @@ -113,6 +111,7 @@ _tx_timer_interrupt // if (__tx_timer_time_slice == 0) CBNZ r2, __tx_timer_no_time_slice // Has it expired? + // No, skip expiration processing /* Set the time-slice expired flag. */ // _tx_timer_expired_time_slice = TX_TRUE; @@ -249,7 +248,6 @@ __tx_timer_nothing_expired DSB // Complete all memory access BX lr // Return to caller - // } ALIGN LTORG diff --git a/ports_module/cortex_m4/ac5/module_manager/src/txm_module_manager_alignment_adjust.c b/ports_module/cortex_m4/ac5/module_manager/src/txm_module_manager_alignment_adjust.c index 2f945552..f91a8fae 100644 --- a/ports_module/cortex_m4/ac5/module_manager/src/txm_module_manager_alignment_adjust.c +++ b/ports_module/cortex_m4/ac5/module_manager/src/txm_module_manager_alignment_adjust.c @@ -61,7 +61,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ ULONG _txm_power_of_two_block_size(ULONG size) @@ -128,7 +128,7 @@ ULONG _txm_power_of_two_block_size(ULONG size) /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ VOID _txm_module_manager_alignment_adjust(TXM_MODULE_PREAMBLE *module_preamble, diff --git a/ports_module/cortex_m4/ac5/module_manager/src/txm_module_manager_external_memory_enable.c b/ports_module/cortex_m4/ac5/module_manager/src/txm_module_manager_external_memory_enable.c index 3eed0481..df025827 100644 --- a/ports_module/cortex_m4/ac5/module_manager/src/txm_module_manager_external_memory_enable.c +++ b/ports_module/cortex_m4/ac5/module_manager/src/txm_module_manager_external_memory_enable.c @@ -70,7 +70,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txm_module_manager_external_memory_enable(TXM_MODULE_INSTANCE *module_instance, diff --git a/ports_module/cortex_m4/ac5/module_manager/src/txm_module_manager_memory_fault_handler.c b/ports_module/cortex_m4/ac5/module_manager/src/txm_module_manager_memory_fault_handler.c index 9efd8bdc..44c01f1e 100644 --- a/ports_module/cortex_m4/ac5/module_manager/src/txm_module_manager_memory_fault_handler.c +++ b/ports_module/cortex_m4/ac5/module_manager/src/txm_module_manager_memory_fault_handler.c @@ -76,7 +76,7 @@ TXM_MODULE_MANAGER_FAULT_INFO /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ VOID _txm_module_manager_memory_fault_handler(VOID) diff --git a/ports_module/cortex_m4/ac5/module_manager/src/txm_module_manager_memory_fault_notify.c b/ports_module/cortex_m4/ac5/module_manager/src/txm_module_manager_memory_fault_notify.c index 43a782f1..e4d38642 100644 --- a/ports_module/cortex_m4/ac5/module_manager/src/txm_module_manager_memory_fault_notify.c +++ b/ports_module/cortex_m4/ac5/module_manager/src/txm_module_manager_memory_fault_notify.c @@ -71,7 +71,7 @@ extern VOID (*_txm_module_manager_fault_notify)(TX_THREAD *, TXM_MODULE_INSTA /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txm_module_manager_memory_fault_notify(VOID (*notify_function)(TX_THREAD *, TXM_MODULE_INSTANCE *)) diff --git a/ports_module/cortex_m4/ac5/module_manager/src/txm_module_manager_mm_register_setup.c b/ports_module/cortex_m4/ac5/module_manager/src/txm_module_manager_mm_register_setup.c index b48dada5..6fa28af7 100644 --- a/ports_module/cortex_m4/ac5/module_manager/src/txm_module_manager_mm_register_setup.c +++ b/ports_module/cortex_m4/ac5/module_manager/src/txm_module_manager_mm_register_setup.c @@ -61,7 +61,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ ULONG _txm_module_manager_region_size_get(ULONG block_size) @@ -184,7 +184,7 @@ ULONG return_value; /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ ULONG _txm_module_manager_calculate_srd_bits(ULONG block_size, ULONG length) @@ -261,7 +261,7 @@ UINT srd_bit_index; /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ VOID _txm_module_manager_mm_register_setup(TXM_MODULE_INSTANCE *module_instance) diff --git a/ports_module/cortex_m4/ac5/module_manager/src/txm_module_manager_thread_stack_build.S b/ports_module/cortex_m4/ac5/module_manager/src/txm_module_manager_thread_stack_build.S index 032975e2..62e944a1 100644 --- a/ports_module/cortex_m4/ac5/module_manager/src/txm_module_manager_thread_stack_build.S +++ b/ports_module/cortex_m4/ac5/module_manager/src/txm_module_manager_thread_stack_build.S @@ -59,8 +59,8 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 11-09-2020 Scott Larson Modified comment(s), */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 11-09-2020 Scott Larson Modified comment(s), */ /* resulting in version 6.1.2 */ /* */ /**************************************************************************/ diff --git a/ports_module/cortex_m4/ac5/module_manager/src/txm_module_manager_user_mode_entry.S b/ports_module/cortex_m4/ac5/module_manager/src/txm_module_manager_user_mode_entry.S index 83d6f960..f9b136a2 100644 --- a/ports_module/cortex_m4/ac5/module_manager/src/txm_module_manager_user_mode_entry.S +++ b/ports_module/cortex_m4/ac5/module_manager/src/txm_module_manager_user_mode_entry.S @@ -60,8 +60,8 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 11-09-2020 Scott Larson Modified comment(s), */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 11-09-2020 Scott Larson Modified comment(s), */ /* resulting in version 6.1.2 */ /* */ /**************************************************************************/ |