| Age | Commit message (Expand) | Author |
|---|---|---|
| 2026-09-15 | Normalized the AI disclosure comment to one fixed line per file (#740) | Frédéric Desbiens |
| 2026-09-09 | riscv32: spec compliance and regression test fix (#691) | Akif Ejaz |
| 2026-09-03 | Fixed the clobbered return address in the RISC-V context save (#696) | Frédéric Desbiens |
| 2026-05-27 | Refactored, consolidated, and cleaned up RV32/RV64 ports (#536) | Frédéric Desbiens |
| 2026-05-25 | Implemented lazy FPU, GP relaxation, and QEMU automation for GNU port in arch... | Wei-Chen Lai |
| 2026-05-25 | Added port for the OpenHW CORE-V MCU platform (#535) | Frédéric Desbiens |
| 2026-05-19 | Add QEMU based CI regression test infra for RV32 and RV64 (#526) | Akif Ejaz |
| 2026-03-05 | Updated copyright headers and version number constants (#509) | Frédéric Desbiens |
| 2026-02-16 | Add RISC-V32 arch. port layer | Akif Ejaz |
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