diff options
| author | William D. Jones <[email protected]> | 2019-01-10 09:58:06 -0500 |
|---|---|---|
| committer | William D. Jones <[email protected]> | 2019-01-10 09:58:06 -0500 |
| commit | b367baeaf1d64930654f136a2409f1322fc73ab2 (patch) | |
| tree | 710698145d52c72b807971d05512330fde2cc9b1 /examples/device | |
| parent | e4d6f336f0d5004fd9ee3074305b7980ba777dfd (diff) | |
| parent | 5804e56e3c2ab4480bf72d94d997f769a645af47 (diff) | |
Merge branch 'master' of https://github.com/hathach/tinyusb into stm32f4
Diffstat (limited to 'examples/device')
78 files changed, 64915 insertions, 6373 deletions
diff --git a/examples/device/cdc_msc_hid/Makefile b/examples/device/cdc_msc_hid/Makefile index 0c1afc53e..d3f592b99 100644 --- a/examples/device/cdc_msc_hid/Makefile +++ b/examples/device/cdc_msc_hid/Makefile @@ -81,8 +81,7 @@ LIB_SOURCE += \ src/class/cdc/cdc_device.c \ src/class/hid/hid_device.c \ src/tusb.c \ - src/portable/$(VENDOR)/$(CHIP_FAMILY)/dcd_$(CHIP_FAMILY).c \ - src/portable/$(VENDOR)/$(CHIP_FAMILY)/hal_$(CHIP_FAMILY).c + src/portable/$(VENDOR)/$(CHIP_FAMILY)/dcd_$(CHIP_FAMILY).c SRC_C += $(LIB_SOURCE) diff --git a/examples/device/cdc_msc_hid/ses/cdc_msc_hid.emProject b/examples/device/cdc_msc_hid/ses/cdc_msc_hid.emProject index ebf758cd3..9d0672b8c 100644 --- a/examples/device/cdc_msc_hid/ses/cdc_msc_hid.emProject +++ b/examples/device/cdc_msc_hid/ses/cdc_msc_hid.emProject @@ -3,4 +3,10 @@ <import file_name="nrf5x/nrf5x.emProject" /> <import file_name="samd21/samd21.emProject" /> <import file_name="samd51/samd51.emProject" /> + <import file_name="lpc43xx/lpc43xx.emProject" /> + <import file_name="lpc175x_6x/lpc175x_6x.emProject" /> + <import file_name="lpc13xx/lpc13xx.emProject" /> + <import file_name="lpc11u6x/lpc11u6x.emProject" /> + <import file_name="lpc18xx/lpc18xx.emProject" /> + <import file_name="lpc40xx/lpc40xx.emProject" /> </solution> diff --git a/examples/device/cdc_msc_hid/ses/lpc11u6x/LPC1100_Startup.s b/examples/device/cdc_msc_hid/ses/lpc11u6x/LPC1100_Startup.s new file mode 100644 index 000000000..56918e1b7 --- /dev/null +++ b/examples/device/cdc_msc_hid/ses/lpc11u6x/LPC1100_Startup.s @@ -0,0 +1,145 @@ +/********************************************************************* +* SEGGER Microcontroller GmbH * +* The Embedded Experts * +********************************************************************** +* * +* (c) 2014 - 2018 SEGGER Microcontroller GmbH * +* * +* www.segger.com Support: [email protected] * +* * +********************************************************************** +* * +* All rights reserved. * +* * +* Redistribution and use in source and binary forms, with or * +* without modification, are permitted provided that the following * +* conditions are met: * +* * +* - Redistributions of source code must retain the above copyright * +* notice, this list of conditions and the following disclaimer. * +* * +* - Neither the name of SEGGER Microcontroller GmbH * +* nor the names of its contributors may be used to endorse or * +* promote products derived from this software without specific * +* prior written permission. * +* * +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND * +* CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, * +* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * +* DISCLAIMED. * +* IN NO EVENT SHALL SEGGER Microcontroller GmbH BE LIABLE FOR * +* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT * +* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * +* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF * +* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE * +* USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH * +* DAMAGE. * +* * +*********************************************************************/ + +/***************************************************************************** + * Preprocessor Definitions * + * ------------------------ * + * NO_STACK_INIT * + * * + * If defined, the stack pointer will not be initialised. * + * * + * NO_SYSTEM_INIT * + * * + * If defined, the SystemInit() function will not be called. By default * + * SystemInit() is called after reset to enable the clocks and memories to * + * be initialised prior to any C startup initialisation. * + * * + * NO_VTOR_CONFIG * + * * + * If defined, the vector table offset register will not be configured. * + * * + * MEMORY_INIT * + * * + * If defined, the MemoryInit() function will be called. By default * + * MemoryInit() is called after SystemInit() to enable an external memory * + * controller. * + * * + * STACK_INIT_VAL * + * * + * If defined, specifies the initial stack pointer value. If undefined, * + * the stack pointer will be initialised to point to the end of the * + * RAM segment. * + * * + * VECTORS_IN_RAM * + * * + * If defined, the exception vectors will be copied from Flash to RAM. * + * * + *****************************************************************************/ + + .syntax unified + + .global Reset_Handler + .extern _vectors + + .section .init, "ax" + .thumb_func + + .equ VTOR_REG, 0xE000ED08 + +#ifndef STACK_INIT_VAL +#define STACK_INIT_VAL __RAM_segment_end__ +#endif + +Reset_Handler: +#ifndef NO_STACK_INIT + /* Initialize main stack */ + ldr r0, =STACK_INIT_VAL + ldr r1, =0x7 + bics r0, r1 + mov sp, r0 +#endif + +#ifndef NO_SYSTEM_INIT + /* Initialize system */ + ldr r0, =SystemInit + blx r0 + .pushsection .init_array, "aw", %init_array + .word SystemCoreClockUpdate + .popsection +#endif + +#ifdef MEMORY_INIT + ldr r0, =MemoryInit + blx r0 +#endif + +#ifdef VECTORS_IN_RAM + /* Copy exception vectors into RAM */ + ldr r0, =__vectors_start__ + ldr r1, =__vectors_end__ + ldr r2, =__vectors_ram_start__ +1: + cmp r0, r1 + beq 2f + ldr r3, [r0] + str r3, [r2] + adds r0, r0, #4 + adds r2, r2, #4 + b 1b +2: +#endif + +#ifndef NO_VTOR_CONFIG + /* Configure vector table offset register */ + ldr r0, =VTOR_REG +#ifdef VECTORS_IN_RAM + ldr r1, =_vectors_ram +#else + ldr r1, =_vectors +#endif + str r1, [r0] +#endif + + /* Jump to program start */ + b _start + + diff --git a/examples/device/cdc_msc_hid/ses/lpc11u6x/LPC1100_Target.js b/examples/device/cdc_msc_hid/ses/lpc11u6x/LPC1100_Target.js new file mode 100644 index 000000000..e0ee57767 --- /dev/null +++ b/examples/device/cdc_msc_hid/ses/lpc11u6x/LPC1100_Target.js @@ -0,0 +1,50 @@ +/********************************************************************* +* SEGGER Microcontroller GmbH * +* The Embedded Experts * +********************************************************************** +* * +* (c) 2014 - 2018 SEGGER Microcontroller GmbH * +* * +* www.segger.com Support: [email protected] * +* * +********************************************************************** +* * +* All rights reserved. * +* * +* Redistribution and use in source and binary forms, with or * +* without modification, are permitted provided that the following * +* conditions are met: * +* * +* - Redistributions of source code must retain the above copyright * +* notice, this list of conditions and the following disclaimer. * +* * +* - Neither the name of SEGGER Microcontroller GmbH * +* nor the names of its contributors may be used to endorse or * +* promote products derived from this software without specific * +* prior written permission. * +* * +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND * +* CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, * +* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * +* DISCLAIMED. * +* IN NO EVENT SHALL SEGGER Microcontroller GmbH BE LIABLE FOR * +* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT * +* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * +* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF * +* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE * +* USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH * +* DAMAGE. * +* * +*********************************************************************/ + +function Reset() { + TargetInterface.resetAndStop(); +} + +function EnableTrace(traceInterfaceType) { + // TODO: Enable trace +} + diff --git a/examples/device/cdc_msc_hid/ses/lpc11u6x/LPC11U68_MemoryMap.xml b/examples/device/cdc_msc_hid/ses/lpc11u6x/LPC11U68_MemoryMap.xml new file mode 100644 index 000000000..2913af3a0 --- /dev/null +++ b/examples/device/cdc_msc_hid/ses/lpc11u6x/LPC11U68_MemoryMap.xml @@ -0,0 +1,7 @@ +<!DOCTYPE Board_Memory_Definition_File> +<root name="LPC11U68"> + <MemorySegment name="FLASH" start="0x00000000" size="0x00040000" access="ReadOnly" /> + <MemorySegment name="RAM" start="0x10000000" size="0x00008000" access="Read/Write" /> + <MemorySegment name="RAM2" start="0x20000000" size="0x00000800" access="Read/Write" /> + <MemorySegment name="RAM3" start="0x20004000" size="0x00000800" access="Read/Write" /> +</root> diff --git a/examples/device/cdc_msc_hid/ses/lpc11u6x/LPC11U6x_Registers.xml b/examples/device/cdc_msc_hid/ses/lpc11u6x/LPC11U6x_Registers.xml new file mode 100644 index 000000000..f1f465eae --- /dev/null +++ b/examples/device/cdc_msc_hid/ses/lpc11u6x/LPC11U6x_Registers.xml @@ -0,0 +1,11919 @@ +<!DOCTYPE Register_Definition_File> +<Processor name="LPC11U6x" description="LPC11U6x ARM cortex-m0+"> + <RegisterGroup name="I2C0" start="0x40000000" description="I2C-bus controller"> + <Register start="+0x000" size="4" name="CONSET" access="Read/Write" description="I2C Control Set Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is set. Writing a zero has no effect on the corresponding bit in the I2C control register." reset_value="0x00" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + <BitField start="2" size="1" name="AA" description="Assert acknowledge flag." /> + <BitField start="3" size="1" name="SI" description="I2C interrupt flag." /> + <BitField start="4" size="1" name="STO" description="STOP flag." /> + <BitField start="5" size="1" name="STA" description="START flag." /> + <BitField start="6" size="1" name="I2EN" description="I2C interface enable." /> + <BitField start="7" size="25" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x004" size="4" name="STAT" access="ReadOnly" description="I2C Status Register. During I2C operation, this register provides detailed status codes that allow software to determine the next action needed." reset_value="0xF8" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="RESERVED" description="These bits are unused and are always 0." /> + <BitField start="3" size="5" name="STATUS" description="These bits give the actual status information about the I2C interface." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x008" size="4" name="DAT" access="Read/Write" description="I2C Data Register. During master or slave transmit mode, data to be transmitted is written to this register. During master or slave receive mode, data that has been received may be read from this register." reset_value="0x00" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="Data" description="This register holds data values that have been received or are to be transmitted." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x00C" size="4" name="ADR0" access="Read/Write" description="I2C Slave Address Register 0. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="GC" description="General Call enable bit." /> + <BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x010" size="4" name="SCLH" access="Read/Write" description="SCH Duty Cycle Register High Half Word. Determines the high time of the I2C clock." reset_value="0x04" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="16" name="SCLH" description="Count for SCL HIGH time period selection." /> + <BitField start="16" size="16" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x014" size="4" name="SCLL" access="Read/Write" description="SCL Duty Cycle Register Low Half Word. Determines the low time of the I2C clock. I2nSCLL and I2nSCLH together determine the clock frequency generated by an I2C master and certain times used in slave mode." reset_value="0x04" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="16" name="SCLL" description="Count for SCL low time period selection." /> + <BitField start="16" size="16" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x018" size="4" name="CONCLR" access="WriteOnly" description="I2C Control Clear Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is cleared. Writing a zero has no effect on the corresponding bit in the I2C control register." reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="2" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + <BitField start="2" size="1" name="AAC" description="Assert acknowledge Clear bit." /> + <BitField start="3" size="1" name="SIC" description="I2C interrupt Clear bit." /> + <BitField start="4" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + <BitField start="5" size="1" name="STAC" description="START flag Clear bit." /> + <BitField start="6" size="1" name="I2ENC" description="I2C interface Disable bit." /> + <BitField start="7" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x01C" size="4" name="MMCTRL" access="Read/Write" description="Monitor mode control register." reset_value="0x00" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="MM_ENA" description="Monitor mode enable."> + <Enum name="MONITOR_MODE_DISABLE" start="0" description="Monitor mode disabled." /> + <Enum name="THE_I2C_MODULE_WILL_" start="1" description="The I2C module will enter monitor mode. In this mode the SDA output will be forced high. This will prevent the I2C module from outputting data of any kind (including ACK) onto the I 2C data bus. Depending on the state of the ENA_SCL bit, the output may be also forced high, preventing the module from having control over the I2C clock line." /> + </BitField> + <BitField start="1" size="1" name="ENA_SCL" description="SCL output enable."> + <Enum name="HIGH" start="0" description="When this bit is cleared to 0, the SCL output will be forced high when the module is in monitor mode. As described above, this will prevent the module from having any control over the I2C clock line." /> + <Enum name="NORMAL" start="1" description="When this bit is set, the I2C module may exercise the same control over the clock line that it would in normal operation. This means that, acting as a slave peripheral, the I2C module can stretch the clock line (hold it low) until it has had time to respond to an I2C interrupt.[1]" /> + </BitField> + <BitField start="2" size="1" name="MATCH_ALL" description="Select interrupt register match."> + <Enum name="MATCH" start="0" description="When this bit is cleared, an interrupt will only be generated when a match occurs to one of the (up-to) four address registers described above. That is, the module will respond as a normal slave as far as address-recognition is concerned." /> + <Enum name="ANYADDRESS" start="1" description="When this bit is set to 1 and the I2C is in monitor mode, an interrupt will be generated on ANY address received. This will enable the part to monitor all traffic on the bus." /> + </BitField> + <BitField start="3" size="29" name="RESERVED" description="Reserved. The value read from reserved bits is not defined." /> + </Register> + <Register start="+0x020+0" size="4" name="ADR1" access="Read/Write" description="I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="GC" description="General Call enable bit." /> + <BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x020+4" size="4" name="ADR2" access="Read/Write" description="I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="GC" description="General Call enable bit." /> + <BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x020+8" size="4" name="ADR3" access="Read/Write" description="I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="GC" description="General Call enable bit." /> + <BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x02C" size="4" name="DATA_BUFFER" access="ReadOnly" description="Data buffer register. The contents of the 8 MSBs of the I2DAT shift register will be transferred to the DATA_BUFFER automatically after every nine bits (8 bits of data plus ACK or NACK) has been received on the bus." reset_value="0x00" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="Data" description="This register holds contents of the 8 MSBs of the DAT shift register." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x030+0" size="4" name="MASK0" access="Read/Write" description="I2C Slave address mask register. This mask register is associated with I2ADR0 to determine an address match. The mask register has no effect when comparing to the General Call address (0000000)." reset_value="0x00" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." /> + <BitField start="1" size="7" name="MASK" description="Mask bits." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from reserved bits is undefined." /> + </Register> + <Register start="+0x030+4" size="4" name="MASK1" access="Read/Write" description="I2C Slave address mask register. This mask register is associated with I2ADR0 to determine an address match. The mask register has no effect when comparing to the General Call address (0000000)." reset_value="0x00" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." /> + <BitField start="1" size="7" name="MASK" description="Mask bits." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from reserved bits is undefined." /> + </Register> + <Register start="+0x030+8" size="4" name="MASK2" access="Read/Write" description="I2C Slave address mask register. This mask register is associated with I2ADR0 to determine an address match. The mask register has no effect when comparing to the General Call address (0000000)." reset_value="0x00" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." /> + <BitField start="1" size="7" name="MASK" description="Mask bits." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from reserved bits is undefined." /> + </Register> + <Register start="+0x030+12" size="4" name="MASK3" access="Read/Write" description="I2C Slave address mask register. This mask register is associated with I2ADR0 to determine an address match. The mask register has no effect when comparing to the General Call address (0000000)." reset_value="0x00" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." /> + <BitField start="1" size="7" name="MASK" description="Mask bits." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from reserved bits is undefined." /> + </Register> + </RegisterGroup> + <RegisterGroup name="WWDT" start="0x40004000" description="Windowed Watchdog Timer (WWDT)"> + <Register start="+0x000" size="4" name="MOD" access="Read/Write" description="Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="WDEN" description="Watchdog enable bit. Once this bit has been written with a 1 it cannot be rewritten with a 0."> + <Enum name="STOPPED" start="0" description="The watchdog timer is stopped." /> + <Enum name="RUNNING" start="1" description="The watchdog timer is running." /> + </BitField> + <BitField start="1" size="1" name="WDRESET" description="Watchdog reset enable bit. Once this bit has been written with a 1 it cannot be rewritten with a 0."> + <Enum name="INTERRUPT" start="0" description="A watchdog timeout will not cause a chip reset." /> + </BitField> + <BitField start="2" size="1" name="WDTOF" description="Watchdog time-out flag. Set when the watchdog timer times out, by a feed error, or by events associated with WDPROTECT. Cleared by software. Causes a chip reset if WDRESET = 1." /> + <BitField start="3" size="1" name="WDINT" description="Warning interrupt flag. Set when the timer reaches the value in WDWARNINT. Cleared by software." /> + <BitField start="4" size="1" name="WDPROTECT" description="Watchdog update mode. This bit can be set once by software and is only cleared by a reset."> + <Enum name="NOT_LOCKED" start="0" description="The watchdog time-out value (TC) can be changed at any time." /> + <Enum name="LOCKED" start="1" description="The watchdog time-out value (TC) can be changed only after the counter is below the value of WDWARNINT and WDWINDOW." /> + </BitField> + <BitField start="5" size="1" name="LOCK" description="A 1 in this bit prevents disabling or powering down the clock source selected by bit 0 of the WDCLKSRC register and also prevents switching to a clock source that is disabled or powered down. This bit can be set once by software and is only cleared by any reset. If this bit is one and the WWDT clock source is the IRC when Deep-sleep or Power-down modes are entered, the IRC remains running thereby increasing power consumption in Deep-sleep mode and potentially preventing the part of entering Power-down mode correctly (see Section 15.7)." /> + <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x004" size="4" name="TC" access="Read/Write" description="Watchdog timer constant register. This 24-bit register determines the time-out value." reset_value="0xFF" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="24" name="COUNT" description="Watchdog time-out value." /> + <BitField start="24" size="8" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x008" size="4" name="FEED" access="WriteOnly" description="Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in WDTC." reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="8" name="FEED" description="Feed value should be 0xAA followed by 0x55." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x00C" size="4" name="TV" access="ReadOnly" description="Watchdog timer value register. This 24-bit register reads out the current value of the Watchdog timer." reset_value="0xFF" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="24" name="COUNT" description="Counter timer value." /> + <BitField start="24" size="8" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x010" size="4" name="CLKSEL" access="Read/Write" description="Watchdog clock select register." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="CLKSEL" description="Selects source of WDT clock"> + <Enum name="IRC" start="0" description="IRC" /> + <Enum name="WATCHDOG_OSCILLATOR_" start="1" description="Watchdog oscillator (WDOSC)" /> + </BitField> + <BitField start="1" size="30" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + <BitField start="31" size="1" name="LOCK" description="If this bit is set to one writing to this register does not affect bit 0. The clock source can only be changed by first clearing this bit, then writing the new value of bit 0." /> + </Register> + <Register start="+0x014" size="4" name="WARNINT" access="Read/Write" description="Watchdog Warning Interrupt compare value." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="10" name="WARNINT" description="Watchdog warning interrupt compare value." /> + <BitField start="10" size="22" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x018" size="4" name="WINDOW" access="Read/Write" description="Watchdog Window compare value." reset_value="0xFFFFFF" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="24" name="WINDOW" description="Watchdog window value." /> + <BitField start="24" size="8" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + </RegisterGroup> + <RegisterGroup name="USART0" start="0x40008000" description="USART0"> + <Register start="+0x000" size="4" name="RBR" access="None" description="Receiver Buffer Register. Contains the next received character to be read. (DLAB=0)" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="8" name="RBR" description="The USART Receiver Buffer Register contains the oldest received byte in the USART RX FIFO." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x000" size="4" name="THR" access="None" description="Transmit Holding Register. The next character to be transmitted is written here. (DLAB=0)" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="8" name="THR" description="Writing to the USART Transmit Holding Register causes the data to be stored in the USART transmit FIFO. The byte will be sent when it is the oldest byte in the FIFO and the transmitter is available." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x000" size="4" name="DLL" access="Read/Write" description="Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. (DLAB=1)" reset_value="0x01" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="DLLSB" description="The USART Divisor Latch LSB Register, along with the DLM register, determines the baud rate of the USART." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x004" size="4" name="DLM" access="Read/Write" description="Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. (DLAB=1)" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="DLMSB" description="The USART Divisor Latch MSB Register, along with the DLL register, determines the baud rate of the USART." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x004" size="4" name="IER" access="Read/Write" description="Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential USART interrupts. (DLAB=0)" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RBRINTEN" description="RBR Interrupt Enable. Enables the Receive Data Available interrupt. It also controls the Character Receive Time-out interrupt."> + <Enum name="DISABLE_THE_RDA_INTE" start="0" description="Disable the RDA interrupt." /> + <Enum name="ENABLE_THE_RDA_INTER" start="1" description="Enable the RDA interrupt." /> + </BitField> + <BitField start="1" size="1" name="THREINTEN" description="THRE Interrupt Enable. Enables the THRE interrupt. The status of this interrupt can be read from LSR[5]."> + <Enum name="DISABLE_THE_THRE_INT" start="0" description="Disable the THRE interrupt." /> + <Enum name="ENABLE_THE_THRE_INTE" start="1" description="Enable the THRE interrupt." /> + </BitField> + <BitField start="2" size="1" name="RLSINTEN" description="Enables the Receive Line Status interrupt. The status of this interrupt can be read from LSR[4:1]."> + <Enum name="DISABLE_THE_RLS_INTE" start="0" description="Disable the RLS interrupt." /> + <Enum name="ENABLE_THE_RLS_INTER" start="1" description="Enable the RLS interrupt." /> + </BitField> + <BitField start="3" size="1" name="MSINTEN" description="Enables the Modem Status interrupt. The components of this interrupt can be read from the MSR."> + <Enum name="DISABLE_THE_MS_INTER" start="0" description="Disable the MS interrupt." /> + <Enum name="ENABLE_THE_MS_INTERR" start="1" description="Enable the MS interrupt." /> + </BitField> + <BitField start="4" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + <BitField start="8" size="1" name="ABEOINTEN" description="Enables the end of auto-baud interrupt."> + <Enum name="DISABLE_END_OF_AUTO_" start="0" description="Disable end of auto-baud Interrupt." /> + <Enum name="ENABLE_END_OF_AUTO_B" start="1" description="Enable end of auto-baud Interrupt." /> + </BitField> + <BitField start="9" size="1" name="ABTOINTEN" description="Enables the auto-baud time-out interrupt."> + <Enum name="DISABLE_AUTO_BAUD_TI" start="0" description="Disable auto-baud time-out Interrupt." /> + <Enum name="ENABLE_AUTO_BAUD_TIM" start="1" description="Enable auto-baud time-out Interrupt." /> + </BitField> + <BitField start="10" size="22" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x008" size="4" name="IIR" access="ReadOnly" description="Interrupt ID Register. Identifies which interrupt(s) are pending." reset_value="0x01" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="INTSTATUS" description="Interrupt status. Note that IIR[0] is active low. The pending interrupt can be determined by evaluating IIR[3:1]."> + <Enum name="AT_LEAST_ONE_INTERRU" start="0" description="At least one interrupt is pending." /> + <Enum name="NO_INTERRUPT_IS_PEND" start="1" description="No interrupt is pending." /> + </BitField> + <BitField start="1" size="3" name="INTID" description="Interrupt identification. IER[3:1] identifies an interrupt corresponding to the USART Rx FIFO. All other values of IER[3:1] not listed below are reserved."> + <Enum name="1_RECEIVE_LINE_S" start="0x3" description="1 - Receive Line Status (RLS)." /> + <Enum name="2A__RECEIVE_DATA_AV" start="0x2" description="2a - Receive Data Available (RDA)." /> + <Enum name="2B__CHARACTER_TIME_" start="0x6" description="2b - Character Time-out Indicator (CTI)." /> + <Enum name="3_THRE_INTERRUPT" start="0x1" description="3 - THRE Interrupt." /> + <Enum name="4_MODEM_STATUS" start="0x0" description="4 - Modem status" /> + </BitField> + <BitField start="4" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + <BitField start="6" size="2" name="FIFOEN" description="These bits are equivalent to FCR[0]." /> + <BitField start="8" size="1" name="ABEOINT" description="End of auto-baud interrupt. True if auto-baud has finished successfully and interrupt is enabled." /> + <BitField start="9" size="1" name="ABTOINT" description="Auto-baud time-out interrupt. True if auto-baud has timed out and interrupt is enabled." /> + <BitField start="10" size="22" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x008" size="4" name="FCR" access="WriteOnly" description="FIFO Control Register. Controls USART FIFO usage and modes." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="FIFOEN" description="FIFO enable"> + <Enum name="DISABLED" start="0" description="USART FIFOs are disabled. Must not be used in the application." /> + <Enum name="ENABLED" start="1" description="Active high enable for both USART Rx and TX FIFOs and FCR[7:1] access. This bit must be set for proper USART operation. Any transition on this bit will automatically clear the USART FIFOs." /> + </BitField> + <BitField start="1" size="1" name="RXFIFORES" description="RX FIFO Reset"> + <Enum name="NO_IMPACT" start="0" description="No impact on either of USART FIFOs." /> + <Enum name="CLEAR" start="1" description="Writing a logic 1 to FCR[1] will clear all bytes in USART Rx FIFO, reset the pointer logic. This bit is self-clearing." /> + </BitField> + <BitField start="2" size="1" name="TXFIFORES" description="TX FIFO Reset"> + <Enum name="NO_IMPACT" start="0" description="No impact on either of USART FIFOs." /> + <Enum name="CLEAR" start="1" description="Writing a logic 1 to FCR[2] will clear all bytes in USART TX FIFO, reset the pointer logic. This bit is self-clearing." /> + </BitField> + <BitField start="3" size="1" name="RESERVED" description="Reserved" /> + <BitField start="4" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + <BitField start="6" size="2" name="RXTL" description="RX Trigger Level. These two bits determine how many receiver USART FIFO characters must be written before an interrupt is activated."> + <Enum name="TRIGGER_LEVEL_0_1_C" start="0x0" description="Trigger level 0 (1 character or 0x01)." /> + <Enum name="TRIGGER_LEVEL_1_4_C" start="0x1" description="Trigger level 1 (4 characters or 0x04)." /> + <Enum name="TRIGGER_LEVEL_2_8_C" start="0x2" description="Trigger level 2 (8 characters or 0x08)." /> + <Enum name="TRIGGER_LEVEL_3_14_" start="0x3" description="Trigger level 3 (14 characters or 0x0E)." /> + </BitField> + <BitField start="8" size="24" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x00C" size="4" name="LCR" access="Read/Write" description="Line Control Register. Contains controls for frame formatting and break generation." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="WLS" description="Word Length Select"> + <Enum name="5_BIT_CHARACTER_LENG" start="0x0" description="5-bit character length." /> + <Enum name="6_BIT_CHARACTER_LENG" start="0x1" description="6-bit character length." /> + <Enum name="7_BIT_CHARACTER_LENG" start="0x2" description="7-bit character length." /> + <Enum name="8_BIT_CHARACTER_LENG" start="0x3" description="8-bit character length." /> + </BitField> + <BitField start="2" size="1" name="SBS" description="Stop Bit Select"> + <Enum name="1_STOP_BIT_" start="0" description="1 stop bit." /> + <Enum name="2_STOP_BITS_1_5_IF_" start="1" description="2 stop bits (1.5 if LCR[1:0]=00)." /> + </BitField> + <BitField start="3" size="1" name="PE" description="Parity Enable"> + <Enum name="DISABLE_PARITY_GENER" start="0" description="Disable parity generation and checking." /> + <Enum name="ENABLE_PARITY_GENERA" start="1" description="Enable parity generation and checking." /> + </BitField> + <BitField start="4" size="2" name="PS" description="Parity Select"> + <Enum name="ODD_PARITY_NUMBER_O" start="0x0" description="Odd parity. Number of 1s in the transmitted character and the attached parity bit will be odd." /> + <Enum name="EVEN_PARITY_NUMBER_" start="0x1" description="Even Parity. Number of 1s in the transmitted character and the attached parity bit will be even." /> + <Enum name="FORCED_1_STICK_PARIT" start="0x2" description="Forced 1 stick parity." /> + <Enum name="FORCED_0_STICK_PARIT" start="0x3" description="Forced 0 stick parity." /> + </BitField> + <BitField start="6" size="1" name="BC" description="Break Control"> + <Enum name="DISABLE_BREAK_TRANSM" start="0" description="Disable break transmission." /> + <Enum name="ENABLE_BREAK_TRANSMI" start="1" description="Enable break transmission. Output pin USART TXD is forced to logic 0 when LCR[6] is active high." /> + </BitField> + <BitField start="7" size="1" name="DLAB" description="Divisor Latch Access Bit"> + <Enum name="DISABLE_ACCESS_TO_DI" start="0" description="Disable access to Divisor Latches." /> + <Enum name="ENABLE_ACCESS_TO_DIV" start="1" description="Enable access to Divisor Latches." /> + </BitField> + <BitField start="8" size="24" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x010" size="4" name="MCR" access="Read/Write" description="Modem Control Register." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="DTRCTRL" description="Source for modem output pin DTR. This bit reads as 0 when modem loopback mode is active." /> + <BitField start="1" size="1" name="RTSCTRL" description="Source for modem output pin RTS. This bit reads as 0 when modem loopback mode is active." /> + <BitField start="2" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + <BitField start="4" size="1" name="LMS" description="Loopback Mode Select. The modem loopback mode provides a mechanism to perform diagnostic loopback testing. Serial data from the transmitter is connected internally to serial input of the receiver. Input pin, RXD, has no effect on loopback and output pin, TXD is held in marking state. The DSR, CTS, DCD, and RI pins are ignored. Externally, DTR and RTS are set inactive. Internally, the upper four bits of the MSR are driven by the lower four bits of the MCR. This permits modem status interrupts to be generated in loopback mode by writing the lower four bits of MCR."> + <Enum name="DISABLE_MODEM_LOOPBA" start="0" description="Disable modem loopback mode." /> + <Enum name="ENABLE_MODEM_LOOPBAC" start="1" description="Enable modem loopback mode." /> + </BitField> + <BitField start="5" size="1" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + <BitField start="6" size="1" name="RTSEN" description="RTS enable"> + <Enum name="DISABLE_AUTO_RTS_FLO" start="0" description="Disable auto-rts flow control." /> + <Enum name="ENABLE_AUTO_RTS_FLOW" start="1" description="Enable auto-rts flow control." /> + </BitField> + <BitField start="7" size="1" name="CTSEN" description="CTS enable"> + <Enum name="DISABLE_AUTO_CTS_FLO" start="0" description="Disable auto-cts flow control." /> + <Enum name="ENABLE_AUTO_CTS_FLOW" start="1" description="Enable auto-cts flow control." /> + </BitField> + <BitField start="8" size="24" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x014" size="4" name="LSR" access="None" description="Line Status Register. Contains flags for transmit and receive status, including line errors." reset_value="0x60" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RDR" description="Receiver Data Ready:LSR[0] is set when the RBR holds an unread character and is cleared when the USART RBR FIFO is empty."> + <Enum name="RBR_IS_EMPTY_" start="0" description="RBR is empty." /> + <Enum name="RBR_CONTAINS_VALID_D" start="1" description="RBR contains valid data." /> + </BitField> + <BitField start="1" size="1" name="OE" description="Overrun Error. The overrun error condition is set as soon as it occurs. A LSR read clears LSR[1]. LSR[1] is set when USART RSR has a new character assembled and the USART RBR FIFO is full. In this case, the USART RBR FIFO will not be overwritten and the character in the USART RSR will be lost."> + <Enum name="INACTIVE" start="0" description="Overrun error status is inactive." /> + <Enum name="ACTIVE" start="1" description="Overrun error status is active." /> + </BitField> + <BitField start="2" size="1" name="PE" description="Parity Error. When the parity bit of a received character is in the wrong state, a parity error occurs. A LSR read clears LSR[2]. Time of parity error detection is dependent on FCR[0]. Note: A parity error is associated with the character at the top of the USART RBR FIFO."> + <Enum name="INACTIVE" start="0" description="Parity error status is inactive." /> + <Enum name="ACTIVE" start="1" description="Parity error status is active." /> + </BitField> + <BitField start="3" size="1" name="FE" description="Framing Error. When the stop bit of a received character is a logic 0, a framing error occurs. A LSR read clears LSR[3]. The time of the framing error detection is dependent on FCR0. Upon detection of a framing error, the RX will attempt to re-synchronize to the data and assume that the bad stop bit is actually an early start bit. However, it cannot be assumed that the next received byte will be correct even if there is no Framing Error. Note: A framing error is associated with the character at the top of the USART RBR FIFO."> + <Enum name="INACTIVE" start="0" description="Framing error status is inactive." /> + <Enum name="ACTIVE" start="1" description="Framing error status is active." /> + </BitField> + <BitField start="4" size="1" name="BI" description="Break Interrupt. When RXD1 is held in the spacing state (all zeros) for one full character transmission (start, data, parity, stop), a break interrupt occurs. Once the break condition has been detected, the receiver goes idle until RXD1 goes to marking state (all ones). A LSR read clears this status bit. The time of break detection is dependent on FCR[0]. Note: The break interrupt is associated with the character at the top of the USART RBR FIFO."> + <Enum name="INACTIVE" start="0" description="Break interrupt status is inactive." /> + <Enum name="ACTIVE" start="1" description="Break interrupt status is active." /> + </BitField> + <BitField start="5" size="1" name="THRE" description="Transmitter Holding Register Empty. THRE is set immediately upon detection of an empty USART THR and is cleared on a THR write."> + <Enum name="THR_CONTAINS_VALID_D" start="0" description="THR contains valid data." /> + <Enum name="THR_IS_EMPTY_" start="1" description="THR is empty." /> + </BitField> + <BitField start="6" size="1" name="TEMT" description="Transmitter Empty. TEMT is set when both THR and TSR are empty; TEMT is cleared when either the TSR or the THR contain valid data."> + <Enum name="VALID_D" start="0" description="THR and/or the TSR contains valid data." /> + <Enum name="EMPTY" start="1" description="THR and the TSR are empty." /> + </BitField> + <BitField start="7" size="1" name="RXFE" description="Error in RX FIFO. LSR[7] is set when a character with a RX error such as framing error, parity error or break interrupt, is loaded into the RBR. This bit is cleared when the LSR register is read and there are no subsequent errors in the USART FIFO."> + <Enum name="NO_ERROR" start="0" description="RBR contains no USART RX errors or FCR[0]=0." /> + <Enum name="ERRO" start="1" description="USART RBR contains at least one USART RX error." /> + </BitField> + <BitField start="8" size="1" name="TXERR" description="Tx Error. In smart card T=0 operation, this bit is set when the smart card has NACKed a transmitted character, one more than the number of times indicated by the TXRETRY field." /> + <BitField start="9" size="23" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x018" size="4" name="MSR" access="None" description="Modem Status Register." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="DCTS" description="Delta CTS. Set upon state change of input CTS. Cleared on an MSR read."> + <Enum name="NO_CHANGE_DETECTED_O" start="0" description="No change detected on modem input, CTS." /> + <Enum name="STATE_CHANGE_DETECTE" start="1" description="State change detected on modem input, CTS." /> + </BitField> + <BitField start="1" size="1" name="DDSR" description="Delta DSR. Set upon state change of input DSR. Cleared on an MSR read."> + <Enum name="NO_CHANGE_DETECTED_O" start="0" description="No change detected on modem input, DSR." /> + <Enum name="STATE_CHANGE_DETECTE" start="1" description="State change detected on modem input, DSR." /> + </BitField> + <BitField start="2" size="1" name="TERI" description="Trailing Edge RI. Set upon low to high transition of input RI. Cleared on an MSR read."> + <Enum name="NO_CHANGE_DETECTED_O" start="0" description="No change detected on modem input, RI." /> + <Enum name="LOW_TO_HIGH_TRANSITI" start="1" description="Low-to-high transition detected on RI." /> + </BitField> + <BitField start="3" size="1" name="DDCD" description="Delta DCD. Set upon state change of input DCD. Cleared on an MSR read."> + <Enum name="NO_CHANGE_DETECTED_O" start="0" description="No change detected on modem input, DCD." /> + <Enum name="STATE_CHANGE_DETECTE" start="1" description="State change detected on modem input, DCD." /> + </BitField> + <BitField start="4" size="1" name="CTS" description="Clear To Send State. Complement of input signal CTS. This bit is connected to MCR[1] in modem loopback mode." /> + <BitField start="5" size="1" name="DSR" description="Data Set Ready State. Complement of input signal DSR. This bit is connected to MCR[0] in modem loopback mode." /> + <BitField start="6" size="1" name="RI" description="Ring Indicator State. Complement of input RI. This bit is connected to MCR[2] in modem loopback mode." /> + <BitField start="7" size="1" name="DCD" description="Data Carrier Detect State. Complement of input DCD. This bit is connected to MCR[3] in modem loopback mode." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x01C" size="4" name="SCR" access="Read/Write" description="Scratch Pad Register. Eight-bit temporary storage for software." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="PAD" description="A readable, writable byte." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x020" size="4" name="ACR" access="Read/Write" description="Auto-baud Control Register. Contains controls for the auto-baud feature." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="START" description="This bit is automatically cleared after auto-baud completion."> + <Enum name="AUTO_BAUD_STOP_AUTO" start="0" description="Auto-baud stop (auto-baud is not running)." /> + <Enum name="AUTO_BAUD_START_AUT" start="1" description="Auto-baud start (auto-baud is running). Auto-baud run bit. This bit is automatically cleared after auto-baud completion." /> + </BitField> + <BitField start="1" size="1" name="MODE" description="Auto-baud mode select bit."> + <Enum name="MODE_0_" start="0" description="Mode 0." /> + <Enum name="MODE_1_" start="1" description="Mode 1." /> + </BitField> + <BitField start="2" size="1" name="AUTORESTART" description="Start mode"> + <Enum name="NO_RESTART" start="0" description="No restart" /> + <Enum name="RESTART_IN_CASE_OF_T" start="1" description="Restart in case of time-out (counter restarts at next USART Rx falling edge)" /> + </BitField> + <BitField start="3" size="5" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + <BitField start="8" size="1" name="ABEOINTCLR" description="End of auto-baud interrupt clear bit (write only accessible)."> + <Enum name="NO_IMPACT" start="0" description="Writing a 0 has no impact." /> + <Enum name="CLEAR" start="1" description="Writing a 1 will clear the corresponding interrupt in the IIR." /> + </BitField> + <BitField start="9" size="1" name="ABTOINTCLR" description="Auto-baud time-out interrupt clear bit (write only accessible)."> + <Enum name="NO_IMPACT" start="0" description="Writing a 0 has no impact." /> + <Enum name="CLEAR" start="1" description="Writing a 1 will clear the corresponding interrupt in the IIR." /> + </BitField> + <BitField start="10" size="22" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x024" size="4" name="ICR" access="Read/Write" description="IrDA Control Register. Enables and configures the IrDA (remote control) mode." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="IRDAEN" description="IrDA mode enable"> + <Enum name="IRDA_MODE_IS_DISABLE" start="0" description="IrDA mode is disabled, USARTn acts as a standard USART." /> + <Enum name="IRDA_MODE_IS_ENABLED" start="1" description="IrDA mode is enabled." /> + </BitField> + <BitField start="1" size="1" name="IRDAINV" description="Serial input inverter"> + <Enum name="INVERTED" start="0" description="The serial input is not inverted." /> + <Enum name="NOT_INVERTED" start="1" description="The serial input is inverted. This has no effect on the serial output." /> + </BitField> + <BitField start="2" size="1" name="FIXPULSEEN" description="IrDA fixed pulse width mode."> + <Enum name="DISABLED" start="0" description="IrDA fixed pulse width mode disabled." /> + <Enum name="ENABLED" start="1" description="IrDA fixed pulse width mode enabled." /> + </BitField> + <BitField start="3" size="3" name="PULSEDIV" description="Configures the pulse width when FixPulseEn = 1."> + <Enum name="3_DIV_16_X_BAUD_RATE" start="0x0" description="3 / (16 x baud rate)" /> + <Enum name="2_X_TPCLK" start="0x1" description="2 x TPCLK" /> + <Enum name="4_X_TPCLK" start="0x2" description="4 x TPCLK" /> + <Enum name="8_X_TPCLK" start="0x3" description="8 x TPCLK" /> + <Enum name="16_X_TPCLK" start="0x4" description="16 x TPCLK" /> + <Enum name="32_X_TPCLK" start="0x5" description="32 x TPCLK" /> + <Enum name="64_X_TPCLK" start="0x6" description="64 x TPCLK" /> + <Enum name="128_X_TPCLK" start="0x7" description="128 x TPCLK" /> + </BitField> + <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x028" size="4" name="FDR" access="Read/Write" description="Fractional Divider Register. Generates a clock input for the baud rate divider." reset_value="0x10" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="4" name="DIVADDVAL" description="Baud rate generation pre-scaler divisor value. If this field is 0, fractional baud rate generator will not impact the USART baud rate." /> + <BitField start="4" size="4" name="MULVAL" description="Baud rate pre-scaler multiplier value. This field must be greater or equal 1 for USART to operate properly, regardless of whether the fractional baud rate generator is used or not." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x02C" size="4" name="OSR" access="Read/Write" description="Oversampling Register. Controls the degree of oversampling during each bit time." reset_value="0xF0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + <BitField start="1" size="3" name="OSFRAC" description="Fractional part of the oversampling ratio, in units of 1/8th of an input clock period. (001 = 0.125, ..., 111 = 0.875)" /> + <BitField start="4" size="4" name="OSINT" description="Integer part of the oversampling ratio, minus 1. The reset values equate to the normal operating mode of 16 input clocks per bit time." /> + <BitField start="8" size="7" name="FDINT" description="In Smart Card mode, these bits act as a more-significant extension of the OSint field, allowing an oversampling ratio up to 2048 as required by ISO7816-3. In Smart Card mode, bits 14:4 should initially be set to 371, yielding an oversampling ratio of 372." /> + <BitField start="15" size="17" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x030" size="4" name="TER" access="Read/Write" description="Transmit Enable Register. Turns off USART transmitter for use with software flow control." reset_value="0x80" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="7" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + <BitField start="7" size="1" name="TXEN" description="When this bit is 1, as it is after a Reset, data written to the THR is output on the TXD pin as soon as any preceding data has been sent. If this bit cleared to 0 while a character is being sent, the transmission of that character is completed, but no further characters are sent until this bit is set again. In other words, a 0 in this bit blocks the transfer of characters from the THR or TX FIFO into the transmit shift register. Software can clear this bit when it detects that the a hardware-handshaking TX-permit signal (CTS) has gone false, or with software handshaking, when it receives an XOFF character (DC3). Software can set this bit again when it detects that the TX-permit signal has gone true, or when it receives an XON (DC1) character." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x040" size="4" name="HDEN" access="Read/Write" description="Half duplex enable register." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="HDEN" description="Half-duplex mode enable"> + <Enum name="DISABLE_HALF_DUPLEX_" start="0" description="Disable half-duplex mode." /> + <Enum name="ENABLE_HALF_DUPLEX_M" start="1" description="Enable half-duplex mode." /> + </BitField> + <BitField start="1" size="31" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x048" size="4" name="SCICTRL" access="Read/Write" description="Smart Card Interface Control register. Enables and configures the Smart Card Interface feature." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="SCIEN" description="Smart Card Interface Enable."> + <Enum name="SMART_CARD_INTERFACE" start="0" description="Smart card interface disabled." /> + <Enum name="ASYNCHRONOUS_HALF_DU" start="1" description="Asynchronous half duplex smart card interface is enabled." /> + </BitField> + <BitField start="1" size="1" name="NACKDIS" description="NACK response disable. Only applicable in T=0."> + <Enum name="ENABLED" start="0" description="A NACK response is enabled." /> + <Enum name="DISABLED" start="1" description="A NACK response is inhibited." /> + </BitField> + <BitField start="2" size="1" name="PROTSEL" description="Protocol selection as defined in the ISO7816-3 standard."> + <Enum name="T_EQ_0" start="0" description="T = 0" /> + <Enum name="T_EQ_1" start="1" description="T = 1" /> + </BitField> + <BitField start="3" size="2" name="RESERVED" description="Reserved." /> + <BitField start="5" size="3" name="TXRETRY" description="When the protocol selection T bit (above) is 0, the field controls the maximum number of retransmissions that the USART will attempt if the remote device signals NACK. When NACK has occurred this number of times plus one, the Tx Error bit in the LSR is set, an interrupt is requested if enabled, and the USART is locked until the FIFO is cleared." /> + <BitField start="8" size="8" name="XTRAGUARD" description="When the protocol selection T bit (above) is 0, this field indicates the number of bit times (ETUs) by which the guard time after a character transmitted by the USART should exceed the nominal 2 bit times. 0xFF in this field may indicate that there is just a single bit after a character and 11 bit times/character" /> + <BitField start="16" size="16" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x04C" size="4" name="RS485CTRL" access="Read/Write" description="RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="NMMEN" description="NMM enable."> + <Enum name="DISABLED" start="0" description="RS-485/EIA-485 Normal Multidrop Mode (NMM) is disabled." /> + <Enum name="ENABLED" start="1" description="RS-485/EIA-485 Normal Multidrop Mode (NMM) is enabled. In this mode, an address is detected when a received byte causes the USART to set the parity error and generate an interrupt." /> + </BitField> + <BitField start="1" size="1" name="RXDIS" description="Receiver enable."> + <Enum name="THE_RECEIVER_IS_ENAB" start="0" description="The receiver is enabled." /> + <Enum name="THE_RECEIVER_IS_DISA" start="1" description="The receiver is disabled." /> + </BitField> + <BitField start="2" size="1" name="AADEN" description="AAD enable."> + <Enum name="AUTO_ADDRESS_DETECT_" start="0" description="Auto Address Detect (AAD) is disabled." /> + <Enum name="AUTO_ADDRESS_DETECT_" start="1" description="Auto Address Detect (AAD) is enabled." /> + </BitField> + <BitField start="3" size="1" name="SEL" description="Select direction control pin"> + <Enum name="RTS" start="0" description="If direction control is enabled (bit DCTRL = 1), pin RTS is used for direction control." /> + <Enum name="DTR" start="1" description="If direction control is enabled (bit DCTRL = 1), pin DTR is used for direction control." /> + </BitField> + <BitField start="4" size="1" name="DCTRL" description="Auto direction control enable."> + <Enum name="DISABLE_AUTO_DIRECTI" start="0" description="Disable Auto Direction Control." /> + <Enum name="ENABLE_AUTO_DIRECTIO" start="1" description="Enable Auto Direction Control." /> + </BitField> + <BitField start="5" size="1" name="OINV" description="Polarity control. This bit reverses the polarity of the direction control signal on the RTS (or DTR) pin."> + <Enum name="LOW" start="0" description="The direction control pin will be driven to logic 0 when the transmitter has data to be sent. It will be driven to logic 1 after the last bit of data has been transmitted." /> + <Enum name="HIGH" start="1" description="The direction control pin will be driven to logic 1 when the transmitter has data to be sent. It will be driven to logic 0 after the last bit of data has been transmitted." /> + </BitField> + <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x050" size="4" name="RS485ADRMATCH" access="Read/Write" description="RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="ADRMATCH" description="Contains the address match value." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x054" size="4" name="RS485DLY" access="Read/Write" description="RS-485/EIA-485 direction control delay." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="DLY" description="Contains the direction control (RTS or DTR) delay value. This register works in conjunction with an 8-bit counter." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x058" size="4" name="SYNCCTRL" access="Read/Write" description="Synchronous mode control register." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="SYNC" description="Enables synchronous mode."> + <Enum name="DISABLED" start="0" description="Disabled" /> + <Enum name="ENABLED" start="1" description="Enabled" /> + </BitField> + <BitField start="1" size="1" name="CSRC" description="Clock source select."> + <Enum name="SYNCHRONOUS_SLAVE_MO" start="0" description="Synchronous slave mode (SCLK in)" /> + <Enum name="SYNCHRONOUS_MASTER_M" start="1" description="Synchronous master mode (SCLK out)" /> + </BitField> + <BitField start="2" size="1" name="FES" description="Falling edge sampling."> + <Enum name="RISING" start="0" description="RxD is sampled on the rising edge of SCLK " /> + <Enum name="FALLING" start="1" description="RxD is sampled on the falling edge of SCLK" /> + </BitField> + <BitField start="3" size="1" name="TSBYPASS" description="Transmit synchronization bypass in synchronous slave mode."> + <Enum name="SYNC" start="0" description="The input clock is synchronized prior to being used in clock edge detection logic" /> + <Enum name="NOSYNC" start="1" description="The input clock is not synchronized prior to being used in clock edge detection logic. This allows for a high er input clock rate at the expense of potential metastability." /> + </BitField> + <BitField start="4" size="1" name="CSCEN" description="Continuous master clock enable (used only when CSRC is 1)"> + <Enum name="SCLK_CYCLES_ONLY_WHE" start="0" description="SCLK cycles only when characters are being sent on TxD" /> + <Enum name="SCLK_RUNS_CONTINUOUS" start="1" description="SCLK runs continuously (characters can be received on RxD independently from transmission on TxD)" /> + </BitField> + <BitField start="5" size="1" name="SSDIS" description="Start/stop bits"> + <Enum name="SEND_START_AND_STOP_" start="0" description="Send start and stop bits as in other modes." /> + <Enum name="DO_NOT_SEND_STARTSTOP" start="1" description="Do not send start/stop bits." /> + </BitField> + <BitField start="6" size="1" name="CCCLR" description="Continuous clock clear"> + <Enum name="CSCEN_IS_UNDER_SOFTW" start="0" description="CSCEN is under software control." /> + <Enum name="HARDWARE_CLEARS_CSCE" start="1" description="Hardware clears CSCEN after each character is received." /> + </BitField> + <BitField start="7" size="25" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + </RegisterGroup> + <RegisterGroup name="CT16B0" start="0x4000C000" description="16-bit counter/timers CT16B0"> + <Register start="+0x000" size="4" name="IR" access="Read/Write" description="Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="MR0INT" description="Interrupt flag for match channel 0." /> + <BitField start="1" size="1" name="MR1INT" description="Interrupt flag for match channel 1." /> + <BitField start="2" size="1" name="MR2INT" description="Interrupt flag for match channel 2." /> + <BitField start="3" size="1" name="MR3INT" description="Interrupt flag for match channel 3." /> + <BitField start="4" size="1" name="CR0INT" description="Interrupt flag for capture channel 0 event." /> + <BitField start="5" size="1" name="CR1INT" description="Interrupt flag for capture channel 1 event." /> + <BitField start="6" size="1" name="CR2INT" description="Interrupt flag for capture channel 2 event." /> + <BitField start="7" size="25" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x004" size="4" name="TCR" access="Read/Write" description="Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="CEN" description="Counter enable."> + <Enum name="DISABLED" start="0" description="The counters are disabled." /> + <Enum name="ENABLED" start="1" description="The Timer Counter and Prescale Counter are enabled for counting." /> + </BitField> + <BitField start="1" size="1" name="CRST" description="Counter reset."> + <Enum name="NOP" start="0" description="Do nothing." /> + <Enum name="RESET" start="1" description="The Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero." /> + </BitField> + <BitField start="2" size="30" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x008" size="4" name="TC" access="Read/Write" description="Timer Counter. The 16-bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="16" name="TCVAL" description="Timer counter value." /> + <BitField start="16" size="16" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x00C" size="4" name="PR" access="Read/Write" description="Prescale Register. When the Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="16" name="PCVAL" description="Prescale value." /> + <BitField start="16" size="16" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x010" size="4" name="PC" access="Read/Write" description="Prescale Counter. The 16-bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="16" name="PC" description="Prescale counter value." /> + <BitField start="16" size="16" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x014" size="4" name="MCR" access="Read/Write" description="Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="MR0I" description="Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC."> + <Enum name="ENABLED" start="1" description="Enabled" /> + <Enum name="DISABLED" start="0" description="Disabled" /> + </BitField> + <BitField start="1" size="1" name="MR0R" description="Reset on MR0: the TC will be reset if MR0 matches it."> + <Enum name="ENABLED" start="1" description="Enabled" /> + <Enum name="DISABLED" start="0" description="Disabled" /> + </BitField> + <BitField start="2" size="1" name="MR0S" description="Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC."> + <Enum name="ENABLED" start="1" description="Enabled" /> + <Enum name="DISABLED" start="0" description="Disabled" /> + </BitField> + <BitField start="3" size="1" name="MR1I" description="Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC."> + <Enum name="ENABLED" start="1" description="Enabled" /> + <Enum name="DISABLED" start="0" description="Disabled" /> + </BitField> + <BitField start="4" size="1" name="MR1R" description="Reset on MR1: the TC will be reset if MR1 matches it."> + <Enum name="ENABLED" start="1" description="Enabled" /> + <Enum name="DISABLED" start="0" description="Disabled" /> + </BitField> + <BitField start="5" size="1" name="MR1S" description="Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC."> + <Enum name="ENABLED" start="1" description="Enabled" /> + <Enum name="DISABLED" start="0" description="Disabled" /> + </BitField> + <BitField start="6" size="1" name="MR2I" description="Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC."> + <Enum name="ENABLED" start="1" description="Enabled" /> + <Enum name="DISABLED" start="0" description="Disabled" /> + </BitField> + <BitField start="7" size="1" name="MR2R" description="Reset on MR2: the TC will be reset if MR2 matches it."> + <Enum name="ENABLED" start="1" description="Enabled" /> + <Enum name="DISABLED" start="0" description="Disabled" /> + </BitField> + <BitField start="8" size="1" name="MR2S" description="Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC."> + <Enum name="ENABLED" start="1" description="Enabled" /> + <Enum name="DISABLED" start="0" description="Disabled" /> + </BitField> + <BitField start="9" size="1" name="MR3I" description="Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC."> + <Enum name="ENABLED" start="1" description="Enabled" /> + <Enum name="DISABLED" start="0" description="Disabled" /> + </BitField> + <BitField start="10" size="1" name="MR3R" description="Reset on MR3: the TC will be reset if MR3 matches it."> + <Enum name="ENABLED" start="1" description="Enabled" /> + <Enum name="DISABLED" start="0" description="Disabled" /> + </BitField> + <BitField start="11" size="1" name="MR3S" description="Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC."> + <Enum name="ENABLED" start="1" description="Enabled" /> + <Enum name="DISABLED" start="0" description="Disabled" /> + </BitField> + <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x018+0" size="4" name="MR0" access="Read/Write" description="Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="16" name="MATCH" description="Timer counter match value." /> + <BitField start="16" size="16" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x018+4" size="4" name="MR1" access="Read/Write" description="Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="16" name="MATCH" description="Timer counter match value." /> + <BitField start="16" size="16" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x018+8" size="4" name="MR2" access="Read/Write" description="Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="16" name="MATCH" description="Timer counter match value." /> + <BitField start="16" size="16" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x018+12" size="4" name="MR3" access="Read/Write" description="Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="16" name="MATCH" description="Timer counter match value." /> + <BitField start="16" size="16" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x028" size="4" name="CCR" access="Read/Write" description="Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="CAP0RE" description="Rising edge of capture channel 0: a sequence of 0 then 1 causes CR0 to be loaded with the contents of TC."> + <Enum name="ENABLED" start="1" description="Enabled." /> + <Enum name="DISABLED" start="0" description="Disabled." /> + </BitField> + <BitField start="1" size="1" name="CAP0FE" description="Falling edge of capture channel 0:: a sequence of 1 then 0 causes CR0 to be loaded with the contents of TC."> + <Enum name="ENABLED" start="1" description="Enabled." /> + <Enum name="DISABLED" start="0" description="Disabled." /> + </BitField> + <BitField start="2" size="1" name="CAP0I" description="Generate interrupt on channel 0 capture event: a CR0 load generates an interrupt."> + <Enum name="ENABLED" start="1" description="Enabled." /> + <Enum name="DISABLED" start="0" description="Disabled." /> + </BitField> + <BitField start="3" size="1" name="CAP1RE" description="Rising edge of capture channel 1: a sequence of 0 then 1 causes CR1 to be loaded with the contents of TC."> + <Enum name="ENABLED" start="1" description="Enabled." /> + <Enum name="DISABLED" start="0" description="Disabled." /> + </BitField> + <BitField start="4" size="1" name="CAP1FE" description="Falling edge of capture channel 1:: a sequence of 1 then 0 causes CR1 to be loaded with the contents of TC."> + <Enum name="ENABLED" start="1" description="Enabled." /> + <Enum name="DISABLED" start="0" description="Disabled." /> + </BitField> + <BitField start="5" size="1" name="CAP1I" description="Generate interrupt on channel 1 capture event: a CR1 load generates an interrupt."> + <Enum name="ENABLED" start="1" description="Enabled." /> + <Enum name="DISABLED" start="0" description="Disabled." /> + </BitField> + <BitField start="6" size="1" name="CAP2RE" description="Rising edge of capture channel 2: a sequence of 0 then 1 causes CR2 to be loaded with the contents of TC."> + <Enum name="ENABLED" start="1" description="Enabled." /> + <Enum name="DISABLED" start="0" description="Disabled." /> + </BitField> + <BitField start="7" size="1" name="CAP2FE" description="Falling edge of capture channel 2: a sequence of 1 then 0 causes CR2 to be loaded with the contents of TC."> + <Enum name="ENABLED" start="1" description="Enabled." /> + <Enum name="DISABLED" start="0" description="Disabled." /> + </BitField> + <BitField start="8" size="1" name="CAP2I" description="Generate interrupt on channel 2 capture event: a CR2 load generates an interrupt."> + <Enum name="ENABLED" start="1" description="Enabled." /> + <Enum name="DISABLED" start="0" description="Disabled." /> + </BitField> + <BitField start="9" size="23" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x02C+0" size="4" name="CR0" access="ReadOnly" description="Capture Register. CR is loaded with the value of TC when there is an event on the CAP input." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="16" name="CAP" description="Timer counter capture value." /> + <BitField start="16" size="16" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x02C+4" size="4" name="CR1" access="ReadOnly" description="Capture Register. CR is loaded with the value of TC when there is an event on the CAP input." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="16" name="CAP" description="Timer counter capture value." /> + <BitField start="16" size="16" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x02C+8" size="4" name="CR2" access="ReadOnly" description="Capture Register. CR is loaded with the value of TC when there is an event on the CAP input." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="16" name="CAP" description="Timer counter capture value." /> + <BitField start="16" size="16" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x03C" size="4" name="EMR" access="Read/Write" description="External Match Register. The EMR controls the match function and the external match pins CT16B0_MAT[1:0] and CT16B1_MAT[1:0]." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="EM0" description="External Match 0. This bit reflects the state of output CT16B0_MAT0/CT16B1_MAT0, whether or not this output is connected to its pin. When a match occurs between the TC and MR0, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[5:4] control the functionality of this output. This bit is driven to the CT16B0_MAT0/CT16B1_MAT0 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH)." /> + <BitField start="1" size="1" name="EM1" description="External Match 1. This bit reflects the state of output CT16B0_MAT1/CT16B1_MAT1, whether or not this output is connected to its pin. When a match occurs between the TC and MR1, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[7:6] control the functionality of this output. This bit is driven to the CT16B0_MAT0/CT16B1_MAT0 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH)." /> + <BitField start="2" size="1" name="EM2" description="External Match 2. This bit reflects the state of match channel 2. When a match occurs between the TC and MR2, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[9:8] control the functionality of this output." /> + <BitField start="3" size="1" name="EM3" description="External Match 3. This bit reflects the state of output of match channel 3. When a match occurs between the TC and MR3, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[11:10] control the functionality of this output." /> + <BitField start="4" size="2" name="EMC0" description="External Match Control 0. Determines the functionality of External Match 0. Table 267 shows the encoding of these bits."> + <Enum name="NOP" start="0x0" description="Do Nothing." /> + <Enum name="CLEAR" start="0x1" description="Clear. Clear the
corresponding External Match bit/output to 0 (CT16Bn_MAT0 pin is
LOW if pinned out)." /> + <Enum name="SET" start="0x2" description="Set. Set the corresponding External Match bit/output to 1
(CT16Bn_MAT0 pin is HIGH if pinned out)." /> + <Enum name="TOGGLE" start="0x3" description="Toggle. Toggle the corresponding
External Match bit/output." /> + </BitField> + <BitField start="6" size="2" name="EMC1" description="External Match Control 1. Determines the functionality of External Match 1."> + <Enum name="NOP" start="0x0" description="Do Nothing." /> + <Enum name="CLEAR" start="0x1" description="Clear. Clear the
corresponding External Match bit/output to 0 (CT16Bn_MAT0 pin is
LOW if pinned out)." /> + <Enum name="SET" start="0x2" description="Set. Set the corresponding External Match bit/output to 1
(CT16Bn_MAT0 pin is HIGH if pinned out)." /> + <Enum name="TOGGLE" start="0x3" description="Toggle. Toggle the corresponding
External Match bit/output." /> + </BitField> + <BitField start="8" size="2" name="EMC2" description="External Match Control 2. Determines the functionality of External Match 2."> + <Enum name="NOP" start="0x0" description="Do Nothing." /> + <Enum name="CLEAR" start="0x1" description="Clear. Clear the
corresponding External Match bit/output to 0 (CT16Bn_MAT0 pin is
LOW if pinned out)." /> + <Enum name="SET" start="0x2" description="Set. Set the corresponding External Match bit/output to 1
(CT16Bn_MAT0 pin is HIGH if pinned out)." /> + <Enum name="TOGGLE" start="0x3" description="Toggle. Toggle the corresponding
External Match bit/output." /> + </BitField> + <BitField start="10" size="2" name="EMC3" description="External Match Control 3. Determines the functionality of External Match 3."> + <Enum name="NOP" start="0x0" description="Do Nothing." /> + <Enum name="CLEAR" start="0x1" description="Clear. Clear the
corresponding External Match bit/output to 0 (CT16Bn_MAT0 pin is
LOW if pinned out)." /> + <Enum name="SET" start="0x2" description="Set. Set the corresponding External Match bit/output to 1
(CT16Bn_MAT0 pin is HIGH if pinned out)." /> + <Enum name="TOGGLE" start="0x3" description="Toggle. Toggle the corresponding
External Match bit/output." /> + </BitField> + <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x070" size="4" name="CTCR" access="Read/Write" description="Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="CTM" description="Counter/Timer Mode. This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). If Counter mode is selected in the CTCR, bits 2:0 in the Capture Control Register (CCR) must be programmed as 000."> + <Enum name="TIMER_MODE" start="0x0" description="Timer Mode. Increments every rising PCLK edge" /> + <Enum name="RISING" start="0x1" description="Counter Moderising edge. . TC is incremented on rising edges on the CAP input selected by bits 3:2." /> + <Enum name="FALLING" start="0x2" description="Counter Mode falling edge: TC is incremented on falling edges on the CAP input selected by bits 3:2." /> + <Enum name="DUAL" start="0x3" description="Counter Mode dual edge: TC is incremented on both edges on the CAP input selected by bits 3:2." /> + </BitField> + <BitField start="2" size="2" name="CIS" description="Count Input Select. In counter mode (when bits 1:0 in this register are not 00), these bits select which CAP pin is sampled for clocking. Value 0x3 isreserved."> + <Enum name="CAPTURE_CHANNEL_0" start="0x0" description="Capture channel 0." /> + <Enum name="CAPTURE_CHANNEL_1" start="0x1" description="Capture channel 1." /> + <Enum name="CAPTURE_CHANNEL_2" start="0x2" description="Capture channel 2." /> + </BitField> + <BitField start="4" size="1" name="ENCC" description="Setting this bit to 1 enables clearing of the timer and the prescaler when the capture-edge event specified in bits 7:5 occurs." /> + <BitField start="5" size="3" name="SELCC" description="Edge select. When bit 4 is 1, these bits select which capture input edge will cause the timer and prescaler to be cleared. These bits have no effect when bit 4 is low. Values 0x2 to 0x3 and 0x6 to 0x7 are reserved."> + <Enum name="CAP0RISING" start="0x0" description="Rising Edge of thesignal on capture channel 0 clears the timer (if bit 4 is set)." /> + <Enum name="CAP0FALLING" start="0x1" description="Falling Edge of thesignal on capture channel 0 clears the timer (if bit 4 is set)." /> + <Enum name="CAP1RISING" start="0x2" description="Rising Edge of thesignal on capture channel 1 clears the timer (if bit 4 is set)." /> + <Enum name="CAP1FALLING" start="0x3" description="Falling Edge of thesignal on capture channel 1 clears the timer (if bit 4 is set)." /> + <Enum name="CAP2RISING" start="0x4" description="Rising Edge of thesignal on capture channel 2 clears the timer (if bit 4 is set)." /> + <Enum name="CAP1FALLING" start="0x5" description="Falling Edge of thesignal on capture channel 2 clears the timer (if bit 4 is set)." /> + </BitField> + <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x074" size="4" name="PWMC" access="Read/Write" description="PWM Control Register. The PWMCON enables PWM mode for the external match pins CT16B0_MAT[1:0] and CT16B1_MAT[1:0]." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="PWMEN0" description="PWM mode enable for channel0."> + <Enum name="EM0" start="0" description="CT16Bn_MAT0 is controlled by EM0." /> + <Enum name="PWM" start="1" description="PWM mode is enabled for CT16Bn_MAT0." /> + </BitField> + <BitField start="1" size="1" name="PWMEN1" description="PWM mode enable for channel1."> + <Enum name="EM1" start="0" description="CT16Bn_MAT01 is controlled by EM1." /> + <Enum name="PWM" start="1" description="PWM mode is enabled for CT16Bn_MAT1." /> + </BitField> + <BitField start="2" size="1" name="PWMEN2" description="PWM mode enable for channel2."> + <Enum name="EM2" start="0" description="CT16Bn_MAT2 is controlled by EM2." /> + <Enum name="PWM" start="1" description="PWM mode is enabled for CT16Bn_MAT2." /> + </BitField> + <BitField start="3" size="1" name="PWMEN3" description="PWM mode enable for channel3."> + <Enum name="EM3" start="0" description="CT16Bn_MAT3 is controlled by EM3." /> + <Enum name="PWM" start="1" description="PWM mode is enabled for CT16Bn_MAT3." /> + </BitField> + <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + </RegisterGroup> + <RegisterGroup name="CT16B1" start="0x40010000" description="16-bit counter/timers CT16B1"> + <Register start="+0x000" size="4" name="IR" access="Read/Write" description="Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="MR0INT" description="Interrupt flag for match channel 0." /> + <BitField start="1" size="1" name="MR1INT" description="Interrupt flag for match channel 1." /> + <BitField start="2" size="1" name="MR2INT" description="Interrupt flag for match channel 2." /> + <BitField start="3" size="1" name="MR3INT" description="Interrupt flag for match channel 3." /> + <BitField start="4" size="1" name="CR0INT" description="Interrupt flag for capture channel 0 event." /> + <BitField start="5" size="1" name="CR1INT" description="Interrupt flag for capture channel 1 event." /> + <BitField start="6" size="1" name="CR2INT" description="Interrupt flag for capture channel 2 event." /> + <BitField start="7" size="25" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x004" size="4" name="TCR" access="Read/Write" description="Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="CEN" description="Counter enable."> + <Enum name="DISABLED" start="0" description="The counters are disabled." /> + <Enum name="ENABLED" start="1" description="The Timer Counter and Prescale Counter are enabled for counting." /> + </BitField> + <BitField start="1" size="1" name="CRST" description="Counter reset."> + <Enum name="NOP" start="0" description="Do nothing." /> + <Enum name="RESET" start="1" description="The Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero." /> + </BitField> + <BitField start="2" size="30" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x008" size="4" name="TC" access="Read/Write" description="Timer Counter. The 16-bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="16" name="TCVAL" description="Timer counter value." /> + <BitField start="16" size="16" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x00C" size="4" name="PR" access="Read/Write" description="Prescale Register. When the Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="16" name="PCVAL" description="Prescale value." /> + <BitField start="16" size="16" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x010" size="4" name="PC" access="Read/Write" description="Prescale Counter. The 16-bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="16" name="PC" description="Prescale counter value." /> + <BitField start="16" size="16" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x014" size="4" name="MCR" access="Read/Write" description="Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="MR0I" description="Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC."> + <Enum name="ENABLED" start="1" description="Enabled" /> + <Enum name="DISABLED" start="0" description="Disabled" /> + </BitField> + <BitField start="1" size="1" name="MR0R" description="Reset on MR0: the TC will be reset if MR0 matches it."> + <Enum name="ENABLED" start="1" description="Enabled" /> + <Enum name="DISABLED" start="0" description="Disabled" /> + </BitField> + <BitField start="2" size="1" name="MR0S" description="Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC."> + <Enum name="ENABLED" start="1" description="Enabled" /> + <Enum name="DISABLED" start="0" description="Disabled" /> + </BitField> + <BitField start="3" size="1" name="MR1I" description="Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC."> + <Enum name="ENABLED" start="1" description="Enabled" /> + <Enum name="DISABLED" start="0" description="Disabled" /> + </BitField> + <BitField start="4" size="1" name="MR1R" description="Reset on MR1: the TC will be reset if MR1 matches it."> + <Enum name="ENABLED" start="1" description="Enabled" /> + <Enum name="DISABLED" start="0" description="Disabled" /> + </BitField> + <BitField start="5" size="1" name="MR1S" description="Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC."> + <Enum name="ENABLED" start="1" description="Enabled" /> + <Enum name="DISABLED" start="0" description="Disabled" /> + </BitField> + <BitField start="6" size="1" name="MR2I" description="Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC."> + <Enum name="ENABLED" start="1" description="Enabled" /> + <Enum name="DISABLED" start="0" description="Disabled" /> + </BitField> + <BitField start="7" size="1" name="MR2R" description="Reset on MR2: the TC will be reset if MR2 matches it."> + <Enum name="ENABLED" start="1" description="Enabled" /> + <Enum name="DISABLED" start="0" description="Disabled" /> + </BitField> + <BitField start="8" size="1" name="MR2S" description="Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC."> + <Enum name="ENABLED" start="1" description="Enabled" /> + <Enum name="DISABLED" start="0" description="Disabled" /> + </BitField> + <BitField start="9" size="1" name="MR3I" description="Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC."> + <Enum name="ENABLED" start="1" description="Enabled" /> + <Enum name="DISABLED" start="0" description="Disabled" /> + </BitField> + <BitField start="10" size="1" name="MR3R" description="Reset on MR3: the TC will be reset if MR3 matches it."> + <Enum name="ENABLED" start="1" description="Enabled" /> + <Enum name="DISABLED" start="0" description="Disabled" /> + </BitField> + <BitField start="11" size="1" name="MR3S" description="Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC."> + <Enum name="ENABLED" start="1" description="Enabled" /> + <Enum name="DISABLED" start="0" description="Disabled" /> + </BitField> + <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x018+0" size="4" name="MR0" access="Read/Write" description="Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="16" name="MATCH" description="Timer counter match value." /> + <BitField start="16" size="16" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x018+4" size="4" name="MR1" access="Read/Write" description="Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="16" name="MATCH" description="Timer counter match value." /> + <BitField start="16" size="16" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x018+8" size="4" name="MR2" access="Read/Write" description="Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="16" name="MATCH" description="Timer counter match value." /> + <BitField start="16" size="16" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x018+12" size="4" name="MR3" access="Read/Write" description="Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="16" name="MATCH" description="Timer counter match value." /> + <BitField start="16" size="16" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x028" size="4" name="CCR" access="Read/Write" description="Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="CAP0RE" description="Rising edge of capture channel 0: a sequence of 0 then 1 causes CR0 to be loaded with the contents of TC."> + <Enum name="ENABLED" start="1" description="Enabled." /> + <Enum name="DISABLED" start="0" description="Disabled." /> + </BitField> + <BitField start="1" size="1" name="CAP0FE" description="Falling edge of capture channel 0:: a sequence of 1 then 0 causes CR0 to be loaded with the contents of TC."> + <Enum name="ENABLED" start="1" description="Enabled." /> + <Enum name="DISABLED" start="0" description="Disabled." /> + </BitField> + <BitField start="2" size="1" name="CAP0I" description="Generate interrupt on channel 0 capture event: a CR0 load generates an interrupt."> + <Enum name="ENABLED" start="1" description="Enabled." /> + <Enum name="DISABLED" start="0" description="Disabled." /> + </BitField> + <BitField start="3" size="1" name="CAP1RE" description="Rising edge of capture channel 1: a sequence of 0 then 1 causes CR1 to be loaded with the contents of TC."> + <Enum name="ENABLED" start="1" description="Enabled." /> + <Enum name="DISABLED" start="0" description="Disabled." /> + </BitField> + <BitField start="4" size="1" name="CAP1FE" description="Falling edge of capture channel 1:: a sequence of 1 then 0 causes CR1 to be loaded with the contents of TC."> + <Enum name="ENABLED" start="1" description="Enabled." /> + <Enum name="DISABLED" start="0" description="Disabled." /> + </BitField> + <BitField start="5" size="1" name="CAP1I" description="Generate interrupt on channel 1 capture event: a CR1 load generates an interrupt."> + <Enum name="ENABLED" start="1" description="Enabled." /> + <Enum name="DISABLED" start="0" description="Disabled." /> + </BitField> + <BitField start="6" size="1" name="CAP2RE" description="Rising edge of capture channel 2: a sequence of 0 then 1 causes CR2 to be loaded with the contents of TC."> + <Enum name="ENABLED" start="1" description="Enabled." /> + <Enum name="DISABLED" start="0" description="Disabled." /> + </BitField> + <BitField start="7" size="1" name="CAP2FE" description="Falling edge of capture channel 2: a sequence of 1 then 0 causes CR2 to be loaded with the contents of TC."> + <Enum name="ENABLED" start="1" description="Enabled." /> + <Enum name="DISABLED" start="0" description="Disabled." /> + </BitField> + <BitField start="8" size="1" name="CAP2I" description="Generate interrupt on channel 2 capture event: a CR2 load generates an interrupt."> + <Enum name="ENABLED" start="1" description="Enabled." /> + <Enum name="DISABLED" start="0" description="Disabled." /> + </BitField> + <BitField start="9" size="23" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x02C+0" size="4" name="CR0" access="ReadOnly" description="Capture Register. CR is loaded with the value of TC when there is an event on the CAP input." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="16" name="CAP" description="Timer counter capture value." /> + <BitField start="16" size="16" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x02C+4" size="4" name="CR1" access="ReadOnly" description="Capture Register. CR is loaded with the value of TC when there is an event on the CAP input." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="16" name="CAP" description="Timer counter capture value." /> + <BitField start="16" size="16" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x02C+8" size="4" name="CR2" access="ReadOnly" description="Capture Register. CR is loaded with the value of TC when there is an event on the CAP input." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="16" name="CAP" description="Timer counter capture value." /> + <BitField start="16" size="16" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x03C" size="4" name="EMR" access="Read/Write" description="External Match Register. The EMR controls the match function and the external match pins CT16B0_MAT[1:0] and CT16B1_MAT[1:0]." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="EM0" description="External Match 0. This bit reflects the state of output CT16B0_MAT0/CT16B1_MAT0, whether or not this output is connected to its pin. When a match occurs between the TC and MR0, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[5:4] control the functionality of this output. This bit is driven to the CT16B0_MAT0/CT16B1_MAT0 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH)." /> + <BitField start="1" size="1" name="EM1" description="External Match 1. This bit reflects the state of output CT16B0_MAT1/CT16B1_MAT1, whether or not this output is connected to its pin. When a match occurs between the TC and MR1, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[7:6] control the functionality of this output. This bit is driven to the CT16B0_MAT0/CT16B1_MAT0 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH)." /> + <BitField start="2" size="1" name="EM2" description="External Match 2. This bit reflects the state of match channel 2. When a match occurs between the TC and MR2, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[9:8] control the functionality of this output." /> + <BitField start="3" size="1" name="EM3" description="External Match 3. This bit reflects the state of output of match channel 3. When a match occurs between the TC and MR3, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[11:10] control the functionality of this output." /> + <BitField start="4" size="2" name="EMC0" description="External Match Control 0. Determines the functionality of External Match 0. Table 267 shows the encoding of these bits."> + <Enum name="NOP" start="0x0" description="Do Nothing." /> + <Enum name="CLEAR" start="0x1" description="Clear. Clear the
corresponding External Match bit/output to 0 (CT16Bn_MAT0 pin is
LOW if pinned out)." /> + <Enum name="SET" start="0x2" description="Set. Set the corresponding External Match bit/output to 1
(CT16Bn_MAT0 pin is HIGH if pinned out)." /> + <Enum name="TOGGLE" start="0x3" description="Toggle. Toggle the corresponding
External Match bit/output." /> + </BitField> + <BitField start="6" size="2" name="EMC1" description="External Match Control 1. Determines the functionality of External Match 1."> + <Enum name="NOP" start="0x0" description="Do Nothing." /> + <Enum name="CLEAR" start="0x1" description="Clear. Clear the
corresponding External Match bit/output to 0 (CT16Bn_MAT0 pin is
LOW if pinned out)." /> + <Enum name="SET" start="0x2" description="Set. Set the corresponding External Match bit/output to 1
(CT16Bn_MAT0 pin is HIGH if pinned out)." /> + <Enum name="TOGGLE" start="0x3" description="Toggle. Toggle the corresponding
External Match bit/output." /> + </BitField> + <BitField start="8" size="2" name="EMC2" description="External Match Control 2. Determines the functionality of External Match 2."> + <Enum name="NOP" start="0x0" description="Do Nothing." /> + <Enum name="CLEAR" start="0x1" description="Clear. Clear the
corresponding External Match bit/output to 0 (CT16Bn_MAT0 pin is
LOW if pinned out)." /> + <Enum name="SET" start="0x2" description="Set. Set the corresponding External Match bit/output to 1
(CT16Bn_MAT0 pin is HIGH if pinned out)." /> + <Enum name="TOGGLE" start="0x3" description="Toggle. Toggle the corresponding
External Match bit/output." /> + </BitField> + <BitField start="10" size="2" name="EMC3" description="External Match Control 3. Determines the functionality of External Match 3."> + <Enum name="NOP" start="0x0" description="Do Nothing." /> + <Enum name="CLEAR" start="0x1" description="Clear. Clear the
corresponding External Match bit/output to 0 (CT16Bn_MAT0 pin is
LOW if pinned out)." /> + <Enum name="SET" start="0x2" description="Set. Set the corresponding External Match bit/output to 1
(CT16Bn_MAT0 pin is HIGH if pinned out)." /> + <Enum name="TOGGLE" start="0x3" description="Toggle. Toggle the corresponding
External Match bit/output." /> + </BitField> + <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x070" size="4" name="CTCR" access="Read/Write" description="Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="CTM" description="Counter/Timer Mode. This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). If Counter mode is selected in the CTCR, bits 2:0 in the Capture Control Register (CCR) must be programmed as 000."> + <Enum name="TIMER_MODE" start="0x0" description="Timer Mode. Increments every rising PCLK edge" /> + <Enum name="RISING" start="0x1" description="Counter Moderising edge. . TC is incremented on rising edges on the CAP input selected by bits 3:2." /> + <Enum name="FALLING" start="0x2" description="Counter Mode falling edge: TC is incremented on falling edges on the CAP input selected by bits 3:2." /> + <Enum name="DUAL" start="0x3" description="Counter Mode dual edge: TC is incremented on both edges on the CAP input selected by bits 3:2." /> + </BitField> + <BitField start="2" size="2" name="CIS" description="Count Input Select. In counter mode (when bits 1:0 in this register are not 00), these bits select which CAP pin is sampled for clocking. Value 0x3 isreserved."> + <Enum name="CAPTURE_CHANNEL_0" start="0x0" description="Capture channel 0." /> + <Enum name="CAPTURE_CHANNEL_1" start="0x1" description="Capture channel 1." /> + <Enum name="CAPTURE_CHANNEL_2" start="0x2" description="Capture channel 2." /> + </BitField> + <BitField start="4" size="1" name="ENCC" description="Setting this bit to 1 enables clearing of the timer and the prescaler when the capture-edge event specified in bits 7:5 occurs." /> + <BitField start="5" size="3" name="SELCC" description="Edge select. When bit 4 is 1, these bits select which capture input edge will cause the timer and prescaler to be cleared. These bits have no effect when bit 4 is low. Values 0x2 to 0x3 and 0x6 to 0x7 are reserved."> + <Enum name="CAP0RISING" start="0x0" description="Rising Edge of thesignal on capture channel 0 clears the timer (if bit 4 is set)." /> + <Enum name="CAP0FALLING" start="0x1" description="Falling Edge of thesignal on capture channel 0 clears the timer (if bit 4 is set)." /> + <Enum name="CAP1RISING" start="0x2" description="Rising Edge of thesignal on capture channel 1 clears the timer (if bit 4 is set)." /> + <Enum name="CAP1FALLING" start="0x3" description="Falling Edge of thesignal on capture channel 1 clears the timer (if bit 4 is set)." /> + <Enum name="CAP2RISING" start="0x4" description="Rising Edge of thesignal on capture channel 2 clears the timer (if bit 4 is set)." /> + <Enum name="CAP1FALLING" start="0x5" description="Falling Edge of thesignal on capture channel 2 clears the timer (if bit 4 is set)." /> + </BitField> + <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x074" size="4" name="PWMC" access="Read/Write" description="PWM Control Register. The PWMCON enables PWM mode for the external match pins CT16B0_MAT[1:0] and CT16B1_MAT[1:0]." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="PWMEN0" description="PWM mode enable for channel0."> + <Enum name="EM0" start="0" description="CT16Bn_MAT0 is controlled by EM0." /> + <Enum name="PWM" start="1" description="PWM mode is enabled for CT16Bn_MAT0." /> + </BitField> + <BitField start="1" size="1" name="PWMEN1" description="PWM mode enable for channel1."> + <Enum name="EM1" start="0" description="CT16Bn_MAT01 is controlled by EM1." /> + <Enum name="PWM" start="1" description="PWM mode is enabled for CT16Bn_MAT1." /> + </BitField> + <BitField start="2" size="1" name="PWMEN2" description="PWM mode enable for channel2."> + <Enum name="EM2" start="0" description="CT16Bn_MAT2 is controlled by EM2." /> + <Enum name="PWM" start="1" description="PWM mode is enabled for CT16Bn_MAT2." /> + </BitField> + <BitField start="3" size="1" name="PWMEN3" description="PWM mode enable for channel3."> + <Enum name="EM3" start="0" description="CT16Bn_MAT3 is controlled by EM3." /> + <Enum name="PWM" start="1" description="PWM mode is enabled for CT16Bn_MAT3." /> + </BitField> + <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + </RegisterGroup> + <RegisterGroup name="CT32B0" start="0x40014000" description="32-bit counter/timers CT32B0"> + <Register start="+0x000" size="4" name="IR" access="Read/Write" description="Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="MR0INT" description="Interrupt flag for match channel 0." /> + <BitField start="1" size="1" name="MR1INT" description="Interrupt flag for match channel 1." /> + <BitField start="2" size="1" name="MR2INT" description="Interrupt flag for match channel 2." /> + <BitField start="3" size="1" name="MR3INT" description="Interrupt flag for match channel 3." /> + <BitField start="4" size="1" name="CR0INT" description="Interrupt flag for capture channel 0 event." /> + <BitField start="5" size="1" name="CR1INT" description="Interrupt flag for capture channel 1 event." /> + <BitField start="6" size="1" name="CR2INT" description="Interrupt flag for capture channel 2 event." /> + <BitField start="7" size="25" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x004" size="4" name="TCR" access="Read/Write" description="Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="CEN" description="Counter enable."> + <Enum name="DISABLED" start="0" description="The counters are disabled." /> + <Enum name="ENABLED" start="1" description="The Timer Counter and Prescale Counter are enabled for counting." /> + </BitField> + <BitField start="1" size="1" name="CRST" description="Counter reset."> + <Enum name="NOP" start="0" description="Do nothing." /> + <Enum name="RESET" start="1" description="The Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero." /> + </BitField> + <BitField start="2" size="30" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x008" size="4" name="TC" access="Read/Write" description="Timer Counter. The 32-bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="TCVAL" description="Timer counter value." /> + </Register> + <Register start="+0x00C" size="4" name="PR" access="Read/Write" description="Prescale Register. When the Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="PCVAL" description="Prescaler value." /> + </Register> + <Register start="+0x010" size="4" name="PC" access="Read/Write" description="Prescale Counter. The 32-bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="PC" description="Prescale counter value." /> + </Register> + <Register start="+0x014" size="4" name="MCR" access="Read/Write" description="Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="MR0I" description="Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC."> + <Enum name="ENABLED" start="1" description="Enabled" /> + <Enum name="DISABLED" start="0" description="Disabled" /> + </BitField> + <BitField start="1" size="1" name="MR0R" description="Reset on MR0: the TC will be reset if MR0 matches it."> + <Enum name="ENABLED" start="1" description="Enabled" /> + <Enum name="DISABLED" start="0" description="Disabled" /> + </BitField> + <BitField start="2" size="1" name="MR0S" description="Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC."> + <Enum name="ENABLED" start="1" description="Enabled" /> + <Enum name="DISABLED" start="0" description="Disabled" /> + </BitField> + <BitField start="3" size="1" name="MR1I" description="Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC."> + <Enum name="ENABLED" start="1" description="Enabled" /> + <Enum name="DISABLED" start="0" description="Disabled" /> + </BitField> + <BitField start="4" size="1" name="MR1R" description="Reset on MR1: the TC will be reset if MR1 matches it."> + <Enum name="ENABLED" start="1" description="Enabled" /> + <Enum name="DISABLED" start="0" description="Disabled" /> + </BitField> + <BitField start="5" size="1" name="MR1S" description="Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC."> + <Enum name="ENABLED" start="1" description="Enabled" /> + <Enum name="DISABLED" start="0" description="Disabled" /> + </BitField> + <BitField start="6" size="1" name="MR2I" description="Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC."> + <Enum name="ENABLED" start="1" description="Enabled" /> + <Enum name="DISABLED" start="0" description="Disabled" /> + </BitField> + <BitField start="7" size="1" name="MR2R" description="Reset on MR2: the TC will be reset if MR2 matches it."> + <Enum name="ENABLED" start="1" description="Enabled" /> + <Enum name="DISABLED" start="0" description="Disabled" /> + </BitField> + <BitField start="8" size="1" name="MR2S" description="Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC."> + <Enum name="ENABLED" start="1" description="Enabled" /> + <Enum name="DISABLED" start="0" description="Disabled" /> + </BitField> + <BitField start="9" size="1" name="MR3I" description="Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC."> + <Enum name="ENABLED" start="1" description="Enabled" /> + <Enum name="DISABLED" start="0" description="Disabled" /> + </BitField> + <BitField start="10" size="1" name="MR3R" description="Reset on MR3: the TC will be reset if MR3 matches it."> + <Enum name="ENABLED" start="1" description="Enabled" /> + <Enum name="DISABLED" start="0" description="Disabled" /> + </BitField> + <BitField start="11" size="1" name="MR3S" description="Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC."> + <Enum name="ENABLED" start="1" description="Enabled" /> + <Enum name="DISABLED" start="0" description="Disabled" /> + </BitField> + <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x018+0" size="4" name="MR0" access="Read/Write" description="Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="MATCH" description="Timer counter match value." /> + </Register> + <Register start="+0x018+4" size="4" name="MR1" access="Read/Write" description="Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="MATCH" description="Timer counter match value." /> + </Register> + <Register start="+0x018+8" size="4" name="MR2" access="Read/Write" description="Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="MATCH" description="Timer counter match value." /> + </Register> + <Register start="+0x018+12" size="4" name="MR3" access="Read/Write" description="Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="MATCH" description="Timer counter match value." /> + </Register> + <Register start="+0x028" size="4" name="CCR" access="Read/Write" description="Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="CAP0RE" description="Rising edge of capture channel 0: a sequence of 0 then 1 causes CR0 to be loaded with the contents of TC."> + <Enum name="ENABLED" start="1" description="Enabled." /> + <Enum name="DISABLED" start="0" description="Disabled." /> + </BitField> + <BitField start="1" size="1" name="CAP0FE" description="Falling edge of capture channel 0:: a sequence of 1 then 0 causes CR0 to be loaded with the contents of TC."> + <Enum name="ENABLED" start="1" description="Enabled." /> + <Enum name="DISABLED" start="0" description="Disabled." /> + </BitField> + <BitField start="2" size="1" name="CAP0I" description="Generate interrupt on channel 0 capture event: a CR0 load generates an interrupt."> + <Enum name="ENABLED" start="1" description="Enabled." /> + <Enum name="DISABLED" start="0" description="Disabled." /> + </BitField> + <BitField start="3" size="1" name="CAP1RE" description="Rising edge of capture channel 1: a sequence of 0 then 1 causes CR1 to be loaded with the contents of TC."> + <Enum name="ENABLED" start="1" description="Enabled." /> + <Enum name="DISABLED" start="0" description="Disabled." /> + </BitField> + <BitField start="4" size="1" name="CAP1FE" description="Falling edge of capture channel 1:: a sequence of 1 then 0 causes CR1 to be loaded with the contents of TC."> + <Enum name="ENABLED" start="1" description="Enabled." /> + <Enum name="DISABLED" start="0" description="Disabled." /> + </BitField> + <BitField start="5" size="1" name="CAP1I" description="Generate interrupt on channel 1 capture event: a CR1 load generates an interrupt."> + <Enum name="ENABLED" start="1" description="Enabled." /> + <Enum name="DISABLED" start="0" description="Disabled." /> + </BitField> + <BitField start="6" size="1" name="CAP2RE" description="Rising edge of capture channel 2: a sequence of 0 then 1 causes CR2 to be loaded with the contents of TC."> + <Enum name="ENABLED" start="1" description="Enabled." /> + <Enum name="DISABLED" start="0" description="Disabled." /> + </BitField> + <BitField start="7" size="1" name="CAP2FE" description="Falling edge of capture channel 2: a sequence of 1 then 0 causes CR2 to be loaded with the contents of TC."> + <Enum name="ENABLED" start="1" description="Enabled." /> + <Enum name="DISABLED" start="0" description="Disabled." /> + </BitField> + <BitField start="8" size="1" name="CAP2I" description="Generate interrupt on channel 2 capture event: a CR2 load generates an interrupt."> + <Enum name="ENABLED" start="1" description="Enabled." /> + <Enum name="DISABLED" start="0" description="Disabled." /> + </BitField> + <BitField start="9" size="23" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x02C+0" size="4" name="CR0" access="ReadOnly" description="Capture Register. CR is loaded with the value of TC when there is an event on the CAP input." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CAP" description="Timer counter capture value." /> + </Register> + <Register start="+0x02C+4" size="4" name="CR1" access="ReadOnly" description="Capture Register. CR is loaded with the value of TC when there is an event on the CAP input." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CAP" description="Timer counter capture value." /> + </Register> + <Register start="+0x02C+8" size="4" name="CR2" access="ReadOnly" description="Capture Register. CR is loaded with the value of TC when there is an event on the CAP input." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CAP" description="Timer counter capture value." /> + </Register> + <Register start="+0x03C" size="4" name="EMR" access="Read/Write" description="External Match Register. The EMR controls the match function and the external match pins CT32Bn_MAT[3:0]." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="EM0" description="External Match 0. This bit reflects the state of output CT32Bn_MAT0, whether or not this output is connected to its pin. When a match occurs between the TC and MR0, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[5:4] control the functionality of this output. This bit is driven to the CT32B0_MAT0/CT32B1_MAT0 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH)." /> + <BitField start="1" size="1" name="EM1" description="External Match 1. This bit reflects the state of output CT32Bn_MAT1, whether or not this output is connected to its pin. When a match occurs between the TC and MR1, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[7:6] control the functionality of this output. This bit is driven to the CT32B0_MAT1/CT32B1_MAT1 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH)." /> + <BitField start="2" size="1" name="EM2" description="External Match 2. This bit reflects the state of output CT32Bn_MAT2, whether or not this output is connected to its pin. When a match occurs between the TC and MR2, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[9:8] control the functionality of this output. This bit is driven to the CT32B0_MAT2/CT32B1_MAT2 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH)." /> + <BitField start="3" size="1" name="EM3" description="External Match 3. This bit reflects the state of output CT32Bn_MAT3, whether or not this output is connected to its pin. When a match occurs between the TC and MR3, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[11:10] control the functionality of this output. This bit is driven to the CT32B3_MAT0/CT32B1_MAT3 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH)." /> + <BitField start="4" size="2" name="EMC0" description="External Match Control 0. Determines the functionality of External Match 0."> + <Enum name="NOP" start="0x0" description="Do Nothing." /> + <Enum name="CLEAR" start="0x1" description="Clear the corresponding
External Match bit/output to 0 (CT32Bi_MAT0 pin is LOW if pinned
out)." /> + <Enum name="SET" start="0x2" description="Set
the corresponding External Match bit/output to 1 (CT32Bi_MAT0 pin
is HIGH if pinned out)." /> + <Enum name="TOGGLE" start="0x3" description="Toggle the corresponding External Match bit/output." /> + </BitField> + <BitField start="6" size="2" name="EMC1" description="External Match Control 1. Determines the functionality of External Match 1."> + <Enum name="NOP" start="0x0" description="Do Nothing." /> + <Enum name="CLEAR" start="0x1" description="Clear the corresponding
External Match bit/output to 0 (CT32Bi_MAT0 pin is LOW if pinned
out)." /> + <Enum name="SET" start="0x2" description="Set
the corresponding External Match bit/output to 1 (CT32Bi_MAT0 pin
is HIGH if pinned out)." /> + <Enum name="TOGGLE" start="0x3" description="Toggle the corresponding External Match bit/output." /> + </BitField> + <BitField start="8" size="2" name="EMC2" description="External Match Control 2. Determines the functionality of External Match 2."> + <Enum name="NOP" start="0x0" description="Do Nothing." /> + <Enum name="CLEAR" start="0x1" description="Clear the corresponding
External Match bit/output to 0 (CT32Bi_MAT0 pin is LOW if pinned
out)." /> + <Enum name="SET" start="0x2" description="Set
the corresponding External Match bit/output to 1 (CT32Bi_MAT0 pin
is HIGH if pinned out)." /> + <Enum name="TOGGLE" start="0x3" description="Toggle the corresponding External Match bit/output." /> + </BitField> + <BitField start="10" size="2" name="EMC3" description="External Match Control 3. Determines the functionality of External Match 3."> + <Enum name="NOP" start="0x0" description="Do Nothing." /> + <Enum name="CLEAR" start="0x1" description="Clear the corresponding
External Match bit/output to 0 (CT32Bi_MAT0 pin is LOW if pinned
out)." /> + <Enum name="SET" start="0x2" description="Set
the corresponding External Match bit/output to 1 (CT32Bi_MAT0 pin
is HIGH if pinned out)." /> + <Enum name="TOGGLE" start="0x3" description="Toggle the corresponding External Match bit/output." /> + </BitField> + <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x070" size="4" name="CTCR" access="Read/Write" description="Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="CTM" description="Counter/Timer Mode. This field selects which rising PCLK edges can increment the Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). If Counter mode is selected in the CTCR, bits 2:0 in the Capture Control Register (CCR) must be programmed as 000."> + <Enum name="TIMER_MODE" start="0x0" description="Timer Mode. Increments every rising PCLK edge" /> + <Enum name="COUNTER_MODE_RISING" start="0x1" description="Counter Mode rising edge. TC is incremented on rising edges on the CAP input selected by bits 3:2." /> + <Enum name="COUNTER_MODE_FALLING" start="0x2" description="Counter Mode falling edge. TC is incremented on falling edges on the CAP input selected by bits 3:2." /> + <Enum name="COUNTER_MODE_DUAL_ED" start="0x3" description="Counter Mode dual edge. TC is incremented on both edges on the CAP input selected by bits 3:2." /> + </BitField> + <BitField start="2" size="2" name="CIS" description="Count Input Select. In counter mode (when bits 1:0 in this register are not 00), these bits select which CAP pin is sampled for clocking. Value 0x3 is reserved."> + <Enum name="CAPTURE_CHANNEL_0" start="0x0" description="Capture channel 0." /> + <Enum name="CAPTURE_CHANNEL_1" start="0x1" description="Capture channel 1." /> + <Enum name="CAPTURE_CHANNEL_2" start="0x2" description="Capture channel 2." /> + </BitField> + <BitField start="4" size="1" name="ENCC" description="Setting this bit to 1 enables clearing of the timer and the prescaler when the capture-edge event specified in bits 7:5 occurs." /> + <BitField start="5" size="3" name="SELCC" description="Edge select. When bit 4 is 1, these bits select which capture input edge will cause the timer and prescaler to be cleared. These bits have no effect when bit 4 is low. Values 0x2 to 0x3 and 0x6 to 0x7 are reserved."> + <Enum name="CAP0RISING" start="0x0" description="Rising Edge of the signal on capture channel 0 clears the timer (if bit 4 is set)." /> + <Enum name="CAP0FALLING" start="0x1" description="Falling Edge of the signal on capture channel 0 clears the timer (if bit 4 is set)." /> + <Enum name="CAP1RISING" start="0x2" description="Rising Edge of the signal on capture channel 1 clears the timer (if bit 4 is set)." /> + <Enum name="CAP1FALLING" start="0x3" description="Falling Edge of the signal on capture channel 1 clears the timer (if bit 4 is set)." /> + <Enum name="CAP2RISING" start="0x4" description="Rising Edge of the signal on capture channel 2 clears the timer (if bit 4 is set)." /> + <Enum name="CAP2FALLING" start="0x5" description="Falling Edge of the signal on capture channel 2 clears the timer (if bit 4 is set)." /> + </BitField> + <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x074" size="4" name="PWMC" access="Read/Write" description="PWM Control Register. The PWMCON enables PWM mode for the external match pins CT32Bn_MAT[3:0]." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="PWMEN0" description="PWM mode enable for channel0."> + <Enum name="EM0" start="0" description="CT32Bn_MAT0 is controlled by EM0." /> + <Enum name="PWM" start="1" description="PWM mode is enabled for CT32Bn_MAT0." /> + </BitField> + <BitField start="1" size="1" name="PWMEN1" description="PWM mode enable for channel1."> + <Enum name="EM1" start="0" description="CT32Bn_MAT01 is controlled by EM1." /> + <Enum name="PWM" start="1" description="PWM mode is enabled for CT32Bn_MAT1." /> + </BitField> + <BitField start="2" size="1" name="PWMEN2" description="PWM mode enable for channel2."> + <Enum name="EM2" start="0" description="CT32Bn_MAT2 is controlled by EM2." /> + <Enum name="PWM" start="1" description="PWM mode is enabled for CT32Bn_MAT2." /> + </BitField> + <BitField start="3" size="1" name="PWMEN3" description="PWM mode enable for channel3. Note: It is recommended to use match channel 3 to set the PWM cycle."> + <Enum name="EM3" start="0" description="CT32Bn_MAT3 is controlled by EM3." /> + <Enum name="PWM" start="1" description="PWM mode is enabled for CT132Bn_MAT3." /> + </BitField> + <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + </RegisterGroup> + <RegisterGroup name="CT32B1" start="0x40018000" description="32-bit counter/timers CT32B1"> + <Register start="+0x000" size="4" name="IR" access="Read/Write" description="Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="MR0INT" description="Interrupt flag for match channel 0." /> + <BitField start="1" size="1" name="MR1INT" description="Interrupt flag for match channel 1." /> + <BitField start="2" size="1" name="MR2INT" description="Interrupt flag for match channel 2." /> + <BitField start="3" size="1" name="MR3INT" description="Interrupt flag for match channel 3." /> + <BitField start="4" size="1" name="CR0INT" description="Interrupt flag for capture channel 0 event." /> + <BitField start="5" size="1" name="CR1INT" description="Interrupt flag for capture channel 1 event." /> + <BitField start="6" size="1" name="CR2INT" description="Interrupt flag for capture channel 2 event." /> + <BitField start="7" size="25" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x004" size="4" name="TCR" access="Read/Write" description="Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="CEN" description="Counter enable."> + <Enum name="DISABLED" start="0" description="The counters are disabled." /> + <Enum name="ENABLED" start="1" description="The Timer Counter and Prescale Counter are enabled for counting." /> + </BitField> + <BitField start="1" size="1" name="CRST" description="Counter reset."> + <Enum name="NOP" start="0" description="Do nothing." /> + <Enum name="RESET" start="1" description="The Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero." /> + </BitField> + <BitField start="2" size="30" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x008" size="4" name="TC" access="Read/Write" description="Timer Counter. The 32-bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="TCVAL" description="Timer counter value." /> + </Register> + <Register start="+0x00C" size="4" name="PR" access="Read/Write" description="Prescale Register. When the Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="PCVAL" description="Prescaler value." /> + </Register> + <Register start="+0x010" size="4" name="PC" access="Read/Write" description="Prescale Counter. The 32-bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="PC" description="Prescale counter value." /> + </Register> + <Register start="+0x014" size="4" name="MCR" access="Read/Write" description="Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="MR0I" description="Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC."> + <Enum name="ENABLED" start="1" description="Enabled" /> + <Enum name="DISABLED" start="0" description="Disabled" /> + </BitField> + <BitField start="1" size="1" name="MR0R" description="Reset on MR0: the TC will be reset if MR0 matches it."> + <Enum name="ENABLED" start="1" description="Enabled" /> + <Enum name="DISABLED" start="0" description="Disabled" /> + </BitField> + <BitField start="2" size="1" name="MR0S" description="Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC."> + <Enum name="ENABLED" start="1" description="Enabled" /> + <Enum name="DISABLED" start="0" description="Disabled" /> + </BitField> + <BitField start="3" size="1" name="MR1I" description="Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC."> + <Enum name="ENABLED" start="1" description="Enabled" /> + <Enum name="DISABLED" start="0" description="Disabled" /> + </BitField> + <BitField start="4" size="1" name="MR1R" description="Reset on MR1: the TC will be reset if MR1 matches it."> + <Enum name="ENABLED" start="1" description="Enabled" /> + <Enum name="DISABLED" start="0" description="Disabled" /> + </BitField> + <BitField start="5" size="1" name="MR1S" description="Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC."> + <Enum name="ENABLED" start="1" description="Enabled" /> + <Enum name="DISABLED" start="0" description="Disabled" /> + </BitField> + <BitField start="6" size="1" name="MR2I" description="Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC."> + <Enum name="ENABLED" start="1" description="Enabled" /> + <Enum name="DISABLED" start="0" description="Disabled" /> + </BitField> + <BitField start="7" size="1" name="MR2R" description="Reset on MR2: the TC will be reset if MR2 matches it."> + <Enum name="ENABLED" start="1" description="Enabled" /> + <Enum name="DISABLED" start="0" description="Disabled" /> + </BitField> + <BitField start="8" size="1" name="MR2S" description="Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC."> + <Enum name="ENABLED" start="1" description="Enabled" /> + <Enum name="DISABLED" start="0" description="Disabled" /> + </BitField> + <BitField start="9" size="1" name="MR3I" description="Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC."> + <Enum name="ENABLED" start="1" description="Enabled" /> + <Enum name="DISABLED" start="0" description="Disabled" /> + </BitField> + <BitField start="10" size="1" name="MR3R" description="Reset on MR3: the TC will be reset if MR3 matches it."> + <Enum name="ENABLED" start="1" description="Enabled" /> + <Enum name="DISABLED" start="0" description="Disabled" /> + </BitField> + <BitField start="11" size="1" name="MR3S" description="Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC."> + <Enum name="ENABLED" start="1" description="Enabled" /> + <Enum name="DISABLED" start="0" description="Disabled" /> + </BitField> + <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x018+0" size="4" name="MR0" access="Read/Write" description="Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="MATCH" description="Timer counter match value." /> + </Register> + <Register start="+0x018+4" size="4" name="MR1" access="Read/Write" description="Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="MATCH" description="Timer counter match value." /> + </Register> + <Register start="+0x018+8" size="4" name="MR2" access="Read/Write" description="Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="MATCH" description="Timer counter match value." /> + </Register> + <Register start="+0x018+12" size="4" name="MR3" access="Read/Write" description="Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="MATCH" description="Timer counter match value." /> + </Register> + <Register start="+0x028" size="4" name="CCR" access="Read/Write" description="Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="CAP0RE" description="Rising edge of capture channel 0: a sequence of 0 then 1 causes CR0 to be loaded with the contents of TC."> + <Enum name="ENABLED" start="1" description="Enabled." /> + <Enum name="DISABLED" start="0" description="Disabled." /> + </BitField> + <BitField start="1" size="1" name="CAP0FE" description="Falling edge of capture channel 0:: a sequence of 1 then 0 causes CR0 to be loaded with the contents of TC."> + <Enum name="ENABLED" start="1" description="Enabled." /> + <Enum name="DISABLED" start="0" description="Disabled." /> + </BitField> + <BitField start="2" size="1" name="CAP0I" description="Generate interrupt on channel 0 capture event: a CR0 load generates an interrupt."> + <Enum name="ENABLED" start="1" description="Enabled." /> + <Enum name="DISABLED" start="0" description="Disabled." /> + </BitField> + <BitField start="3" size="1" name="CAP1RE" description="Rising edge of capture channel 1: a sequence of 0 then 1 causes CR1 to be loaded with the contents of TC."> + <Enum name="ENABLED" start="1" description="Enabled." /> + <Enum name="DISABLED" start="0" description="Disabled." /> + </BitField> + <BitField start="4" size="1" name="CAP1FE" description="Falling edge of capture channel 1:: a sequence of 1 then 0 causes CR1 to be loaded with the contents of TC."> + <Enum name="ENABLED" start="1" description="Enabled." /> + <Enum name="DISABLED" start="0" description="Disabled." /> + </BitField> + <BitField start="5" size="1" name="CAP1I" description="Generate interrupt on channel 1 capture event: a CR1 load generates an interrupt."> + <Enum name="ENABLED" start="1" description="Enabled." /> + <Enum name="DISABLED" start="0" description="Disabled." /> + </BitField> + <BitField start="6" size="1" name="CAP2RE" description="Rising edge of capture channel 2: a sequence of 0 then 1 causes CR2 to be loaded with the contents of TC."> + <Enum name="ENABLED" start="1" description="Enabled." /> + <Enum name="DISABLED" start="0" description="Disabled." /> + </BitField> + <BitField start="7" size="1" name="CAP2FE" description="Falling edge of capture channel 2: a sequence of 1 then 0 causes CR2 to be loaded with the contents of TC."> + <Enum name="ENABLED" start="1" description="Enabled." /> + <Enum name="DISABLED" start="0" description="Disabled." /> + </BitField> + <BitField start="8" size="1" name="CAP2I" description="Generate interrupt on channel 2 capture event: a CR2 load generates an interrupt."> + <Enum name="ENABLED" start="1" description="Enabled." /> + <Enum name="DISABLED" start="0" description="Disabled." /> + </BitField> + <BitField start="9" size="23" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x02C+0" size="4" name="CR0" access="ReadOnly" description="Capture Register. CR is loaded with the value of TC when there is an event on the CAP input." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CAP" description="Timer counter capture value." /> + </Register> + <Register start="+0x02C+4" size="4" name="CR1" access="ReadOnly" description="Capture Register. CR is loaded with the value of TC when there is an event on the CAP input." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CAP" description="Timer counter capture value." /> + </Register> + <Register start="+0x02C+8" size="4" name="CR2" access="ReadOnly" description="Capture Register. CR is loaded with the value of TC when there is an event on the CAP input." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CAP" description="Timer counter capture value." /> + </Register> + <Register start="+0x03C" size="4" name="EMR" access="Read/Write" description="External Match Register. The EMR controls the match function and the external match pins CT32Bn_MAT[3:0]." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="EM0" description="External Match 0. This bit reflects the state of output CT32Bn_MAT0, whether or not this output is connected to its pin. When a match occurs between the TC and MR0, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[5:4] control the functionality of this output. This bit is driven to the CT32B0_MAT0/CT32B1_MAT0 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH)." /> + <BitField start="1" size="1" name="EM1" description="External Match 1. This bit reflects the state of output CT32Bn_MAT1, whether or not this output is connected to its pin. When a match occurs between the TC and MR1, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[7:6] control the functionality of this output. This bit is driven to the CT32B0_MAT1/CT32B1_MAT1 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH)." /> + <BitField start="2" size="1" name="EM2" description="External Match 2. This bit reflects the state of output CT32Bn_MAT2, whether or not this output is connected to its pin. When a match occurs between the TC and MR2, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[9:8] control the functionality of this output. This bit is driven to the CT32B0_MAT2/CT32B1_MAT2 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH)." /> + <BitField start="3" size="1" name="EM3" description="External Match 3. This bit reflects the state of output CT32Bn_MAT3, whether or not this output is connected to its pin. When a match occurs between the TC and MR3, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[11:10] control the functionality of this output. This bit is driven to the CT32B3_MAT0/CT32B1_MAT3 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH)." /> + <BitField start="4" size="2" name="EMC0" description="External Match Control 0. Determines the functionality of External Match 0."> + <Enum name="NOP" start="0x0" description="Do Nothing." /> + <Enum name="CLEAR" start="0x1" description="Clear the corresponding
External Match bit/output to 0 (CT32Bi_MAT0 pin is LOW if pinned
out)." /> + <Enum name="SET" start="0x2" description="Set
the corresponding External Match bit/output to 1 (CT32Bi_MAT0 pin
is HIGH if pinned out)." /> + <Enum name="TOGGLE" start="0x3" description="Toggle the corresponding External Match bit/output." /> + </BitField> + <BitField start="6" size="2" name="EMC1" description="External Match Control 1. Determines the functionality of External Match 1."> + <Enum name="NOP" start="0x0" description="Do Nothing." /> + <Enum name="CLEAR" start="0x1" description="Clear the corresponding
External Match bit/output to 0 (CT32Bi_MAT0 pin is LOW if pinned
out)." /> + <Enum name="SET" start="0x2" description="Set
the corresponding External Match bit/output to 1 (CT32Bi_MAT0 pin
is HIGH if pinned out)." /> + <Enum name="TOGGLE" start="0x3" description="Toggle the corresponding External Match bit/output." /> + </BitField> + <BitField start="8" size="2" name="EMC2" description="External Match Control 2. Determines the functionality of External Match 2."> + <Enum name="NOP" start="0x0" description="Do Nothing." /> + <Enum name="CLEAR" start="0x1" description="Clear the corresponding
External Match bit/output to 0 (CT32Bi_MAT0 pin is LOW if pinned
out)." /> + <Enum name="SET" start="0x2" description="Set
the corresponding External Match bit/output to 1 (CT32Bi_MAT0 pin
is HIGH if pinned out)." /> + <Enum name="TOGGLE" start="0x3" description="Toggle the corresponding External Match bit/output." /> + </BitField> + <BitField start="10" size="2" name="EMC3" description="External Match Control 3. Determines the functionality of External Match 3."> + <Enum name="NOP" start="0x0" description="Do Nothing." /> + <Enum name="CLEAR" start="0x1" description="Clear the corresponding
External Match bit/output to 0 (CT32Bi_MAT0 pin is LOW if pinned
out)." /> + <Enum name="SET" start="0x2" description="Set
the corresponding External Match bit/output to 1 (CT32Bi_MAT0 pin
is HIGH if pinned out)." /> + <Enum name="TOGGLE" start="0x3" description="Toggle the corresponding External Match bit/output." /> + </BitField> + <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x070" size="4" name="CTCR" access="Read/Write" description="Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="CTM" description="Counter/Timer Mode. This field selects which rising PCLK edges can increment the Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). If Counter mode is selected in the CTCR, bits 2:0 in the Capture Control Register (CCR) must be programmed as 000."> + <Enum name="TIMER_MODE" start="0x0" description="Timer Mode. Increments every rising PCLK edge" /> + <Enum name="COUNTER_MODE_RISING" start="0x1" description="Counter Mode rising edge. TC is incremented on rising edges on the CAP input selected by bits 3:2." /> + <Enum name="COUNTER_MODE_FALLING" start="0x2" description="Counter Mode falling edge. TC is incremented on falling edges on the CAP input selected by bits 3:2." /> + <Enum name="COUNTER_MODE_DUAL_ED" start="0x3" description="Counter Mode dual edge. TC is incremented on both edges on the CAP input selected by bits 3:2." /> + </BitField> + <BitField start="2" size="2" name="CIS" description="Count Input Select. In counter mode (when bits 1:0 in this register are not 00), these bits select which CAP pin is sampled for clocking. Value 0x3 is reserved."> + <Enum name="CAPTURE_CHANNEL_0" start="0x0" description="Capture channel 0." /> + <Enum name="CAPTURE_CHANNEL_1" start="0x1" description="Capture channel 1." /> + <Enum name="CAPTURE_CHANNEL_2" start="0x2" description="Capture channel 2." /> + </BitField> + <BitField start="4" size="1" name="ENCC" description="Setting this bit to 1 enables clearing of the timer and the prescaler when the capture-edge event specified in bits 7:5 occurs." /> + <BitField start="5" size="3" name="SELCC" description="Edge select. When bit 4 is 1, these bits select which capture input edge will cause the timer and prescaler to be cleared. These bits have no effect when bit 4 is low. Values 0x2 to 0x3 and 0x6 to 0x7 are reserved."> + <Enum name="CAP0RISING" start="0x0" description="Rising Edge of the signal on capture channel 0 clears the timer (if bit 4 is set)." /> + <Enum name="CAP0FALLING" start="0x1" description="Falling Edge of the signal on capture channel 0 clears the timer (if bit 4 is set)." /> + <Enum name="CAP1RISING" start="0x2" description="Rising Edge of the signal on capture channel 1 clears the timer (if bit 4 is set)." /> + <Enum name="CAP1FALLING" start="0x3" description="Falling Edge of the signal on capture channel 1 clears the timer (if bit 4 is set)." /> + <Enum name="CAP2RISING" start="0x4" description="Rising Edge of the signal on capture channel 2 clears the timer (if bit 4 is set)." /> + <Enum name="CAP2FALLING" start="0x5" description="Falling Edge of the signal on capture channel 2 clears the timer (if bit 4 is set)." /> + </BitField> + <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x074" size="4" name="PWMC" access="Read/Write" description="PWM Control Register. The PWMCON enables PWM mode for the external match pins CT32Bn_MAT[3:0]." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="PWMEN0" description="PWM mode enable for channel0."> + <Enum name="EM0" start="0" description="CT32Bn_MAT0 is controlled by EM0." /> + <Enum name="PWM" start="1" description="PWM mode is enabled for CT32Bn_MAT0." /> + </BitField> + <BitField start="1" size="1" name="PWMEN1" description="PWM mode enable for channel1."> + <Enum name="EM1" start="0" description="CT32Bn_MAT01 is controlled by EM1." /> + <Enum name="PWM" start="1" description="PWM mode is enabled for CT32Bn_MAT1." /> + </BitField> + <BitField start="2" size="1" name="PWMEN2" description="PWM mode enable for channel2."> + <Enum name="EM2" start="0" description="CT32Bn_MAT2 is controlled by EM2." /> + <Enum name="PWM" start="1" description="PWM mode is enabled for CT32Bn_MAT2." /> + </BitField> + <BitField start="3" size="1" name="PWMEN3" description="PWM mode enable for channel3. Note: It is recommended to use match channel 3 to set the PWM cycle."> + <Enum name="EM3" start="0" description="CT32Bn_MAT3 is controlled by EM3." /> + <Enum name="PWM" start="1" description="PWM mode is enabled for CT132Bn_MAT3." /> + </BitField> + <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + </RegisterGroup> + <RegisterGroup name="ADC" start="0x4001C000" description="12-bit Analog-to-Digital Converter (ADC)"> + <Register start="+0x000" size="4" name="CTRL" access="Read/Write" description="A/D Control Register. Contains the clock divide value, enable bits for each sequence and the A/D power-down bit." reset_value="0x0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="CLKDIV" description="The system clock is divided by this value plus one to produce the clock for the A/D converter, which should be less than or equal to 50 MHz (up to 100 MHz in 10-bit mode). Typically, software should program the smallest value in this field that yields this maximum clock rate or slightly less, but in certain cases (such as a high-impedance analog source) a slower clock may be desirable." /> + <BitField start="8" size="2" name="RESERVED" description="Reserved." /> + <BitField start="10" size="1" name="LPWRMODE" description="Select low-power ADC mode. The analog circuitry is automatically powered-down when no conversions are taking place. When any (hardware or software) triggering event is detected, the analog circuitry is enabled. After the required start-up time, the requested conversion will be launched. Once the conversion completes, the analog-circuitry will again be powered-down provided no further conversions are pending. Using this mode can save an appreciable amount of current (approximately 2.5 mA) when conversions are required relatively infrequently. The penalty for using this mode is an approximately 15 ADC clock delay (30 clocks in 10-bit mode), based on the frequency specified in the CLKDIV field, from the time the trigger event occurs until sampling of the A/D input commences. This mode will NOT power-up the A/D if the ADC_ENA bit is low."> + <Enum name="DISABLED" start="0" description="Disabled. The low-power ADC mode is disabled. The analog circuitry remains activated even when no conversions are requested." /> + <Enum name="ENABLED" start="1" description="Enabled. The low-power ADC mode is enabled." /> + </BitField> + <BitField start="30" size="1" name="CAL_MODE" description="Writing a 1 to this bit initiates a self-calibration cycle. This bit will be automatically cleared by hardware after the calibration cycle is complete. Other bits of this register may be written to concurrently with setting this bit, however once this bit has been set no further writes to this register are permitted until the full calibration cycle has ended." /> + <BitField start="31" size="1" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x008" size="4" name="SEQA_CTRL" access="Read/Write" description="A/D Conversion Sequence-A control Register: Controls triggering and channel selection for conversion sequence-A. Also specifies interrupt mode for sequence-A." reset_value="0x0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="12" name="CHANNELS" description="Selects which one or more of the twelve channels will be sampled and converted when this sequence is launched. A 1 in any bit of this field will cause the corresponding channel to be included in the conversion sequence, where bit 0 corresponds to channel 0, bit 1 to channel 1 and so forth. When this conversion sequence is triggered, either by a hardware trigger or via software command, A/D conversions will be performed on each enabled channel, in sequence, beginning with the lowest-ordered channel. This field can ONLY be changed while the SEQA_ENA bit (bit 31) is LOW. It is allowed to change this field and set bit 31 in the same write." /> + <BitField start="12" size="3" name="TRIGGER" description="Selects which of the available hardware trigger sources will cause this conversion sequence to be initiated. Program the trigger input number in this field." /> + <BitField start="15" size="3" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + <BitField start="18" size="1" name="TRIGPOL" description="Select the polarity of the selected input trigger for this conversion sequence."> + <Enum name="NEGATIVE_EDGE" start="0" description="Negative edge. A negative edge launches the conversion sequence on the selected trigger input." /> + <Enum name="POSITIVE_EDGE" start="1" description="Positive edge. A positive edge launches the conversion sequence on the selected trigger input." /> + </BitField> + <BitField start="19" size="1" name="SYNCBYPASS" description="Setting this bit allows the hardware trigger input to bypass synchronization flip-flops stages and therefore shorten the time between the trigger input signal and the start of a conversion. There are slightly different criteria for whether or not this bit can be set depending on the clock operating mode: Synchronous mode: Synchronization may be bypassed (this bit may be set) if the selected trigger source is already synchronous with the main system clock (eg. coming from an on-chip, system-clock-based timer). Whether this bit is set or not, a trigger pulse must be maintained for at least one system clock period. Asynchronous mode: Synchronization may be bypassed (this bit may be set) if it is certain that the duration of a trigger input pulse will be at least one cycle of the ADC clock (regardless of whether the trigger comes from and on-chip or off-chip source). If this bit is NOT set, the trigger pulse must at least be maintained for one system clock period."> + <Enum name="ENABLE_SYNCHRONIZATI" start="0" description="Enable synchronization. The hardware trigger bypass is not enabled." /> + <Enum name="BYPASS_SYNCHRONIZATI" start="1" description="Bypass synchronization. The hardware trigger bypass is enabled." /> + </BitField> + <BitField start="20" size="6" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + <BitField start="26" size="1" name="START" description="Writing a 1 to this field will launch one pass through this conversion sequence. The behavior will be identical to a sequence triggered by a hardware trigger. Do not write 1 to this bit if the BURST bit is set. This bit is only set to a 1 momentarily when written-to to launch a conversion sequence. It will consequently always read-back as a zero." /> + <BitField start="27" size="1" name="BURST" description="Writing a 1 to this bit will cause this conversion sequence to be continuously cycled through. Other sequence A triggers will be ignored while this bit is set. Repeated conversions can be halted by clearing this bit. The sequence currently in progress will be completed before conversions are terminated." /> + <BitField start="28" size="1" name="SINGLESTEP" description="When this bit is set, a hardware trigger or a write to the START bit will launch a single conversion on the next channel in the sequence instead of the default response of launching an entire sequence of conversions. Once all of the channels comprising a sequence have been converted, a subsequent trigger will repeat the sequence beginning with the first enabled channel. Interrupt generation will still occur either after each individual conversion or at the end of the entire sequence, depending on the state of the MODE bit." /> + <BitField start="29" size="1" name="LOWPRIO" description="Set priority for sequence A."> + <Enum name="LOW_PRIORITY" start="0" description="Low priority. Any B trigger which occurs while an A conversion sequence is active will be ignored and lost." /> + <Enum name="HIGH_PRIORITY" start="1" description="High priority. Setting this bit to a 1 will permit any enabled B sequence trigger (including a B sequence software start) to immediately interrupt this sequence and launch a B sequence in it's place. The conversion currently in progress will be terminated. The A sequence that was interrupted will automatically resume after the B sequence completes. The channel whose conversion was terminated will be re-sampled and the conversion sequence will resume from that point." /> + </BitField> + <BitField start="30" size="1" name="MODE" description="Indicates whether the primary method for retrieving conversion results for this sequence will be accomplished via reading the global data register (SEQA_GDAT) at the end of each conversion, or the individual channel result registers at the end of the entire sequence. Impacts when conversion-complete interrupt/DMA requests for sequence-A will be generated and which overrun conditions contribute to an overrun interrupt as described below:"> + <Enum name="END_OF_CONVERSION" start="0" description="End of conversion. The sequence A interrupt/DMA flag will be set at the end of each individual A/D conversion performed under sequence A. This flag will mirror the DATAVALID bit in the SEQA_GDAT register. The OVERRUN bit in the SEQA_GDAT register will contribute to generation of an overrun interrupt/DMA request if enabled." /> + <Enum name="END_OF_SEQUENCE" start="1" description="End of sequence. The sequence A interrupt/DMA flag will be set when the entire set of sequence-A conversions completes. This flag will need to be explicitly cleared by software or by the DMA-clear signal in this mode. The OVERRUN bit in the SEQA_GDAT register will NOT contribute to generation of an overrun interrupt/DMA request since it is assumed this register may not be utilized in this mode." /> + </BitField> + <BitField start="31" size="1" name="SEQA_ENA" description="Sequence Enable"> + <Enum name="DISABLED" start="0" description="Disabled. Sequence A is disabled. Sequence A triggers are ignored. If this bit is cleared while sequence A is in progress, the sequence will be halted at the end of the current conversion. After the sequence is re-enabled, a new trigger will be required to restart the sequence beginning with the next enabled channel." /> + <Enum name="ENABLED" start="1" description="Enabled. Sequence A is enabled." /> + </BitField> + </Register> + <Register start="+0x00C" size="4" name="SEQB_CTRL" access="Read/Write" description="A/D Conversion Sequence-B Control Register: Controls triggering and channel selection for conversion sequence-B. Also specifies interrupt mode for sequence-B." reset_value="0x0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="12" name="CHANNELS" description="Selects which one or more of the twelve channels will be sampled and converted when this sequence is launched. A 1 in any bit of this field will cause the corresponding channel to be included in the conversion sequence, where bit 0 corresponds to channel 0, bit 1 to channel 1 and so forth. When this conversion sequence is triggered, either by a hardware trigger or via software command, A/D conversions will be performed on each enabled channel, in sequence, beginning with the lowest-ordered channel. This field can ONLY be changed while the SEQB_ENA bit (bit 31) is LOW. It is permissible to change this field and set bit 31 in the same write." /> + <BitField start="12" size="3" name="TRIGGER" description="Selects which of the available hardware trigger sources will cause this conversion sequence to be initiated. Program the trigger input number in this field." /> + <BitField start="15" size="3" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + <BitField start="18" size="1" name="TRIGPOL" description="Select the polarity of the selected input trigger for this conversion sequence."> + <Enum name="NEGATIVE_EDGE" start="0" description="Negative edge. A negative edge launches the conversion sequence on the selected trigger input." /> + <Enum name="POSITIVE_EDGE" start="1" description="Positive edge. A positive edge launches the conversion sequence on the selected trigger input." /> + </BitField> + <BitField start="19" size="1" name="SYNCBYPASS" description="Setting this bit allows the hardware trigger input to bypass synchronization flip-flops stages and therefore shorten the time between the trigger input signal and the start of a conversion. There are slightly different criteria for whether or not this bit can be set depending on the clock operating mode: Synchronous mode: Synchronization may be bypassed (this bit may be set) if the selected trigger source is already synchronous with the main system clock (eg. coming from an on-chip, system-clock-based timer). Whether this bit is set or not, a trigger pulse must be maintained for at least one system clock period. Asynchronous mode: Synchronization may be bypassed (this bit may be set) if it is certain that the duration of a trigger input pulse will be at least one cycle of the ADC clock (regardless of whether the trigger comes from and on-chip or off-chip source). If this bit is NOT set, the trigger pulse must at least be maintained for one system clock period."> + <Enum name="ENABLE_SYNCHRONIZATI" start="0" description="Enable synchronization. The hardware trigger bypass is not enabled." /> + <Enum name="BYPASS_SYNCHRONIZATI" start="1" description="Bypass synchronization. The hardware trigger bypass is enabled." /> + </BitField> + <BitField start="20" size="6" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + <BitField start="26" size="1" name="START" description="Writing a 1 to this field will launch one pass through this conversion sequence. The behavior will be identical to a sequence triggered by a hardware trigger. Do not write a 1 to this bit if the BURST bit is set. This bit is only set to a 1 momentarily when written-to to launch a conversion sequence. It will consequently always read-back as a zero." /> + <BitField start="27" size="1" name="BURST" description="Writing a 1 to this bit will cause this conversion sequence to be continuously cycled through. Other B triggers will be ignored while this bit is set. Repeated conversions can be halted by clearing this bit. The sequence currently in progress will be completed before conversions are terminated." /> + <BitField start="28" size="1" name="SINGLESTEP" description="When this bit is set, a hardware trigger or a write to the START bit will launch a single conversion on the next channel in the sequence instead of the default response of launching an entire sequence of conversions. Once all of the channels comprising a sequence have been converted, a subsequent trigger will repeat the sequence beginning with the first enabled channel. Interrupt generation will still occur either after each individual conversion or at the end of the entire sequence, depending on the state of the MODE bit." /> + <BitField start="29" size="1" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + <BitField start="30" size="1" name="MODE" description="Indicates whether the primary method for retrieving conversion results for this sequence will be accomplished via reading the global data register (SEQB_GDAT) at the end of each conversion, or the individual channel result registers at the end of the entire sequence. Impacts when conversion-complete interrupt/DMA requests for sequence-B will be generated and which overrun conditions contribute to an overrun interrupt as described below:"> + <Enum name="END_OF_CONVERSION" start="0" description="End of conversion. The sequence B interrupt/DMA flag will be set at the end of each individual A/D conversion performed under sequence B. This flag will mirror the DATAVALID bit in the SEQB_GDAT register. The OVERRUN bit in the SEQB_GDAT register will contribute to generation of an overrun interrupt/DMA request if enabled." /> + <Enum name="END_OF_SEQUENCE" start="1" description="End of sequence. The sequence B interrupt/DMA flag will be set when the entire set of sequence B conversions completes. This flag will need to be explicitly cleared by software or by the DMA-clear signal in this mode. The OVERRUN bit in the SEQB_GDAT register will NOT contribute to generation of an overrun interrupt/DMA request since it is assumed this register will not be utilized in this mode." /> + </BitField> + <BitField start="31" size="1" name="SEQB_ENA" description="Sequence Enable"> + <Enum name="DISABLED" start="0" description="Disabled. Sequence B is disabled. Sequence B triggers are ignored. If this bit is cleared while sequence B is in progress, the sequence will be halted at the end of the current conversion. After the sequence is re-enabled, a new trigger will be required to restart the sequence beginning with the next enabled channel." /> + <Enum name="ENABLED" start="1" description="Enabled. Sequence B is enabled." /> + </BitField> + </Register> + <Register start="+0x010" size="4" name="SEQA_GDAT" access="Read/Write" description="A/D Sequence-A Global Data Register. This register contains the result of the most recent A/D conversion performed under sequence-A" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + <BitField start="4" size="12" name="RESULT" description="This field contains the 12-bit A/D conversion result from the most recent conversion performed under conversion sequence associated with this register. The result is the a binary fraction representing the voltage on the currently-selected input channel as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VREFN, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP. DATAVALID = 1 indicates that this result has not yet been read." /> + <BitField start="16" size="2" name="THCMPRANGE" description="Indicates whether the result of the last conversion performed was above, below or within the range established by the designated threshold comparison registers (THRn_LOW and THRn_HIGH)." /> + <BitField start="18" size="2" name="THCMPCROSS" description="Indicates whether the result of the last conversion performed represented a crossing of the threshold level established by the designated LOW threshold comparison register (THRn_LOW) and, if so, in what direction the crossing occurred." /> + <BitField start="20" size="6" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + <BitField start="26" size="4" name="CHN" description="These bits contain the channel from which the RESULT bits were converted (e.g. 0000 identifies channel 0, 0001 channel 1...)." /> + <BitField start="30" size="1" name="OVERRUN" description="This bit is set if a new conversion result is loaded into the RESULT field before a previous result has been read - i.e. while the DATAVALID bit is set. This bit is cleared, along with the DATAVALID bit, whenever this register is read. This bit will contribute to an overrun interrupt request if the MODE bit (in SEQA_CTRL) for the corresponding sequence is set to '0' (and if the overrun interrupt is enabled)." /> + <BitField start="31" size="1" name="DATAVALID" description="This bit is set to '1' at the end of each conversion when a new result is loaded into the RESULT field. It is cleared whenever this register is read. This bit will cause a conversion-complete interrupt for the corresponding sequence if the MODE bit (in SEQA_CTRL) for that sequence is set to 0 (and if the interrupt is enabled)." /> + </Register> + <Register start="+0x014" size="4" name="SEQB_GDAT" access="Read/Write" description="A/D Sequence-B Global Data Register. This register contains the result of the most recent A/D conversion performed under sequence-B" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + <BitField start="4" size="12" name="RESULT" description="This field contains the 12-bit A/D conversion result from the most recent conversion performed under conversion sequence associated with this register. This will be a binary fraction representing the voltage on the currently-selected input channel as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VREFN, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on V REFP. DATAVALID = 1 indicates that this result has not yet been read." /> + <BitField start="16" size="2" name="THCMPRANGE" description="Indicates whether the result of the last conversion performed was above, below or within the range established by the designated threshold comparison registers (THRn_LOW and THRn_HIGH). Threshold Range Comparison result. 0x0 = In Range: The last completed conversion was greater than or equal to the value programmed into the designated LOW threshold register (THRn_LOW) but less than or equal to the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x1 = Below Range: The last completed conversion on was less than the value programmed into the designated LOW threshold register (THRn_LOW). 0x2 = Above Range: The last completed conversion was greater than the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x3 = Reserved." /> + <BitField start="18" size="2" name="THCMPCROSS" description="Indicates whether the result of the last conversion performed represented a crossing of the threshold level established by the designated LOW threshold comparison register (THRn_LOW) and, if so, in what direction the crossing occurred. 0x0 = No threshold Crossing detected: The most recent completed conversion on this channel had the same relationship (above or below) to the threshold value established by the designated LOW threshold register (THRn_LOW) as did the previous conversion on this channel. 0x1 = Reserved. 0x2 = Downward Threshold Crossing Detected. Indicates that a threshold crossing in the downward direction has occurred - i.e. the previous sample on this channel was above the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is below that threshold. 0x3 = Upward Threshold Crossing Detected. Indicates that a threshold crossing in the upward direction has occurred - i.e. the previous sample on this channel was below the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is above that threshold." /> + <BitField start="20" size="6" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + <BitField start="26" size="4" name="CHN" description="These bits contain the channel from which the RESULT bits were converted (e.g. 0b0000 identifies channel 0, 0b0001 channel 1...)." /> + <BitField start="30" size="1" name="OVERRUN" description="This bit is set if a new conversion result is loaded into the RESULT field before a previous result has been read - i.e. while the DATAVALID bit is set. This bit is cleared, along with the DATAVALID bit, whenever this register is read. This bit will contribute to an overrun interrupt request if the MODE bit (in SEQB_CTRL) for the corresponding sequence is set to 0 (and if the overrun interrupt is enabled)." /> + <BitField start="31" size="1" name="DATAVALID" description="This bit is set to 1 at the end of each conversion when a new result is loaded into the RESULT field. It is cleared whenever this register is read. This bit will cause a conversion-complete interrupt for the corresponding sequence if the MODE bit (in SEQB_CTRL) for that sequence is set to 0 (and if the interrupt is enabled)." /> + </Register> + <Register start="+0x020+0" size="4" name="DAT[0]" access="ReadOnly" description="A/D Channel 0 Data Register. This register contains the result of the most recent conversion completed on channel 0." reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + <BitField start="4" size="12" name="RESULT" description="This field contains the 12-bit A/D conversion result from the last conversion performed on this channel. This will be a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VREFN, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP." /> + <BitField start="16" size="2" name="THCMPRANGE" description="Threshold Range Comparison result. 0x0 = In Range: The last completed conversion was greater than or equal to the value programmed into the designated LOW threshold register (THRn_LOW) but less than or equal to the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x1 = Below Range: The last completed conversion on was less than the value programmed into the designated LOW threshold register (THRn_LOW). 0x2 = Above Range: The last completed conversion was greater than the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x3 = Reserved." /> + <BitField start="18" size="2" name="THCMPCROSS" description="Threshold Crossing Comparison result. 0x0 = No threshold Crossing detected: The most recent completed conversion on this channel had the same relationship (above or below) to the threshold value established by the designated LOW threshold register (THRn_LOW) as did the previous conversion on this channel. 0x1 = Reserved. 0x2 = Downward Threshold Crossing Detected. Indicates that a threshold crossing in the downward direction has occurred - i.e. the previous sample on this channel was above the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is below that threshold. 0x3 = Upward Threshold Crossing Detected. Indicates that a threshold crossing in the upward direction has occurred - i.e. the previous sample on this channel was below the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is above that threshold." /> + <BitField start="20" size="6" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + <BitField start="26" size="4" name="CHANNEL" description="This field is hard-coded to contain the channel number that this particular register relates to (i.e. this field will contain 0b0000 for the DAT0 register, 0b0001 for the DAT1 register, etc)" /> + <BitField start="30" size="1" name="OVERRUN" description="This bit will be set to a 1 if a new conversion on this channel completes and overwrites the previous contents of the RESULT field before it has been read - i.e. while the DONE bit is set. This bit is cleared, along with the DONE bit, whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. This bit (in any of the 12 registers) will cause an overrun interrupt request to be asserted if the overrun interrupt is enabled. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled." /> + <BitField start="31" size="1" name="DATAVALID" description="This bit is set to 1 when an A/D conversion on this channel completes. This bit is cleared whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled." /> + </Register> + <Register start="+0x020+4" size="4" name="DAT[1]" access="ReadOnly" description="A/D Channel 0 Data Register. This register contains the result of the most recent conversion completed on channel 0." reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + <BitField start="4" size="12" name="RESULT" description="This field contains the 12-bit A/D conversion result from the last conversion performed on this channel. This will be a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VREFN, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP." /> + <BitField start="16" size="2" name="THCMPRANGE" description="Threshold Range Comparison result. 0x0 = In Range: The last completed conversion was greater than or equal to the value programmed into the designated LOW threshold register (THRn_LOW) but less than or equal to the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x1 = Below Range: The last completed conversion on was less than the value programmed into the designated LOW threshold register (THRn_LOW). 0x2 = Above Range: The last completed conversion was greater than the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x3 = Reserved." /> + <BitField start="18" size="2" name="THCMPCROSS" description="Threshold Crossing Comparison result. 0x0 = No threshold Crossing detected: The most recent completed conversion on this channel had the same relationship (above or below) to the threshold value established by the designated LOW threshold register (THRn_LOW) as did the previous conversion on this channel. 0x1 = Reserved. 0x2 = Downward Threshold Crossing Detected. Indicates that a threshold crossing in the downward direction has occurred - i.e. the previous sample on this channel was above the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is below that threshold. 0x3 = Upward Threshold Crossing Detected. Indicates that a threshold crossing in the upward direction has occurred - i.e. the previous sample on this channel was below the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is above that threshold." /> + <BitField start="20" size="6" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + <BitField start="26" size="4" name="CHANNEL" description="This field is hard-coded to contain the channel number that this particular register relates to (i.e. this field will contain 0b0000 for the DAT0 register, 0b0001 for the DAT1 register, etc)" /> + <BitField start="30" size="1" name="OVERRUN" description="This bit will be set to a 1 if a new conversion on this channel completes and overwrites the previous contents of the RESULT field before it has been read - i.e. while the DONE bit is set. This bit is cleared, along with the DONE bit, whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. This bit (in any of the 12 registers) will cause an overrun interrupt request to be asserted if the overrun interrupt is enabled. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled." /> + <BitField start="31" size="1" name="DATAVALID" description="This bit is set to 1 when an A/D conversion on this channel completes. This bit is cleared whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled." /> + </Register> + <Register start="+0x020+8" size="4" name="DAT[2]" access="ReadOnly" description="A/D Channel 0 Data Register. This register contains the result of the most recent conversion completed on channel 0." reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + <BitField start="4" size="12" name="RESULT" description="This field contains the 12-bit A/D conversion result from the last conversion performed on this channel. This will be a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VREFN, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP." /> + <BitField start="16" size="2" name="THCMPRANGE" description="Threshold Range Comparison result. 0x0 = In Range: The last completed conversion was greater than or equal to the value programmed into the designated LOW threshold register (THRn_LOW) but less than or equal to the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x1 = Below Range: The last completed conversion on was less than the value programmed into the designated LOW threshold register (THRn_LOW). 0x2 = Above Range: The last completed conversion was greater than the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x3 = Reserved." /> + <BitField start="18" size="2" name="THCMPCROSS" description="Threshold Crossing Comparison result. 0x0 = No threshold Crossing detected: The most recent completed conversion on this channel had the same relationship (above or below) to the threshold value established by the designated LOW threshold register (THRn_LOW) as did the previous conversion on this channel. 0x1 = Reserved. 0x2 = Downward Threshold Crossing Detected. Indicates that a threshold crossing in the downward direction has occurred - i.e. the previous sample on this channel was above the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is below that threshold. 0x3 = Upward Threshold Crossing Detected. Indicates that a threshold crossing in the upward direction has occurred - i.e. the previous sample on this channel was below the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is above that threshold." /> + <BitField start="20" size="6" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + <BitField start="26" size="4" name="CHANNEL" description="This field is hard-coded to contain the channel number that this particular register relates to (i.e. this field will contain 0b0000 for the DAT0 register, 0b0001 for the DAT1 register, etc)" /> + <BitField start="30" size="1" name="OVERRUN" description="This bit will be set to a 1 if a new conversion on this channel completes and overwrites the previous contents of the RESULT field before it has been read - i.e. while the DONE bit is set. This bit is cleared, along with the DONE bit, whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. This bit (in any of the 12 registers) will cause an overrun interrupt request to be asserted if the overrun interrupt is enabled. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled." /> + <BitField start="31" size="1" name="DATAVALID" description="This bit is set to 1 when an A/D conversion on this channel completes. This bit is cleared whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled." /> + </Register> + <Register start="+0x020+12" size="4" name="DAT[3]" access="ReadOnly" description="A/D Channel 0 Data Register. This register contains the result of the most recent conversion completed on channel 0." reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + <BitField start="4" size="12" name="RESULT" description="This field contains the 12-bit A/D conversion result from the last conversion performed on this channel. This will be a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VREFN, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP." /> + <BitField start="16" size="2" name="THCMPRANGE" description="Threshold Range Comparison result. 0x0 = In Range: The last completed conversion was greater than or equal to the value programmed into the designated LOW threshold register (THRn_LOW) but less than or equal to the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x1 = Below Range: The last completed conversion on was less than the value programmed into the designated LOW threshold register (THRn_LOW). 0x2 = Above Range: The last completed conversion was greater than the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x3 = Reserved." /> + <BitField start="18" size="2" name="THCMPCROSS" description="Threshold Crossing Comparison result. 0x0 = No threshold Crossing detected: The most recent completed conversion on this channel had the same relationship (above or below) to the threshold value established by the designated LOW threshold register (THRn_LOW) as did the previous conversion on this channel. 0x1 = Reserved. 0x2 = Downward Threshold Crossing Detected. Indicates that a threshold crossing in the downward direction has occurred - i.e. the previous sample on this channel was above the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is below that threshold. 0x3 = Upward Threshold Crossing Detected. Indicates that a threshold crossing in the upward direction has occurred - i.e. the previous sample on this channel was below the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is above that threshold." /> + <BitField start="20" size="6" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + <BitField start="26" size="4" name="CHANNEL" description="This field is hard-coded to contain the channel number that this particular register relates to (i.e. this field will contain 0b0000 for the DAT0 register, 0b0001 for the DAT1 register, etc)" /> + <BitField start="30" size="1" name="OVERRUN" description="This bit will be set to a 1 if a new conversion on this channel completes and overwrites the previous contents of the RESULT field before it has been read - i.e. while the DONE bit is set. This bit is cleared, along with the DONE bit, whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. This bit (in any of the 12 registers) will cause an overrun interrupt request to be asserted if the overrun interrupt is enabled. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled." /> + <BitField start="31" size="1" name="DATAVALID" description="This bit is set to 1 when an A/D conversion on this channel completes. This bit is cleared whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled." /> + </Register> + <Register start="+0x020+16" size="4" name="DAT[4]" access="ReadOnly" description="A/D Channel 0 Data Register. This register contains the result of the most recent conversion completed on channel 0." reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + <BitField start="4" size="12" name="RESULT" description="This field contains the 12-bit A/D conversion result from the last conversion performed on this channel. This will be a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VREFN, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP." /> + <BitField start="16" size="2" name="THCMPRANGE" description="Threshold Range Comparison result. 0x0 = In Range: The last completed conversion was greater than or equal to the value programmed into the designated LOW threshold register (THRn_LOW) but less than or equal to the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x1 = Below Range: The last completed conversion on was less than the value programmed into the designated LOW threshold register (THRn_LOW). 0x2 = Above Range: The last completed conversion was greater than the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x3 = Reserved." /> + <BitField start="18" size="2" name="THCMPCROSS" description="Threshold Crossing Comparison result. 0x0 = No threshold Crossing detected: The most recent completed conversion on this channel had the same relationship (above or below) to the threshold value established by the designated LOW threshold register (THRn_LOW) as did the previous conversion on this channel. 0x1 = Reserved. 0x2 = Downward Threshold Crossing Detected. Indicates that a threshold crossing in the downward direction has occurred - i.e. the previous sample on this channel was above the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is below that threshold. 0x3 = Upward Threshold Crossing Detected. Indicates that a threshold crossing in the upward direction has occurred - i.e. the previous sample on this channel was below the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is above that threshold." /> + <BitField start="20" size="6" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + <BitField start="26" size="4" name="CHANNEL" description="This field is hard-coded to contain the channel number that this particular register relates to (i.e. this field will contain 0b0000 for the DAT0 register, 0b0001 for the DAT1 register, etc)" /> + <BitField start="30" size="1" name="OVERRUN" description="This bit will be set to a 1 if a new conversion on this channel completes and overwrites the previous contents of the RESULT field before it has been read - i.e. while the DONE bit is set. This bit is cleared, along with the DONE bit, whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. This bit (in any of the 12 registers) will cause an overrun interrupt request to be asserted if the overrun interrupt is enabled. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled." /> + <BitField start="31" size="1" name="DATAVALID" description="This bit is set to 1 when an A/D conversion on this channel completes. This bit is cleared whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled." /> + </Register> + <Register start="+0x020+20" size="4" name="DAT[5]" access="ReadOnly" description="A/D Channel 0 Data Register. This register contains the result of the most recent conversion completed on channel 0." reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + <BitField start="4" size="12" name="RESULT" description="This field contains the 12-bit A/D conversion result from the last conversion performed on this channel. This will be a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VREFN, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP." /> + <BitField start="16" size="2" name="THCMPRANGE" description="Threshold Range Comparison result. 0x0 = In Range: The last completed conversion was greater than or equal to the value programmed into the designated LOW threshold register (THRn_LOW) but less than or equal to the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x1 = Below Range: The last completed conversion on was less than the value programmed into the designated LOW threshold register (THRn_LOW). 0x2 = Above Range: The last completed conversion was greater than the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x3 = Reserved." /> + <BitField start="18" size="2" name="THCMPCROSS" description="Threshold Crossing Comparison result. 0x0 = No threshold Crossing detected: The most recent completed conversion on this channel had the same relationship (above or below) to the threshold value established by the designated LOW threshold register (THRn_LOW) as did the previous conversion on this channel. 0x1 = Reserved. 0x2 = Downward Threshold Crossing Detected. Indicates that a threshold crossing in the downward direction has occurred - i.e. the previous sample on this channel was above the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is below that threshold. 0x3 = Upward Threshold Crossing Detected. Indicates that a threshold crossing in the upward direction has occurred - i.e. the previous sample on this channel was below the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is above that threshold." /> + <BitField start="20" size="6" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + <BitField start="26" size="4" name="CHANNEL" description="This field is hard-coded to contain the channel number that this particular register relates to (i.e. this field will contain 0b0000 for the DAT0 register, 0b0001 for the DAT1 register, etc)" /> + <BitField start="30" size="1" name="OVERRUN" description="This bit will be set to a 1 if a new conversion on this channel completes and overwrites the previous contents of the RESULT field before it has been read - i.e. while the DONE bit is set. This bit is cleared, along with the DONE bit, whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. This bit (in any of the 12 registers) will cause an overrun interrupt request to be asserted if the overrun interrupt is enabled. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled." /> + <BitField start="31" size="1" name="DATAVALID" description="This bit is set to 1 when an A/D conversion on this channel completes. This bit is cleared whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled." /> + </Register> + <Register start="+0x020+24" size="4" name="DAT[6]" access="ReadOnly" description="A/D Channel 0 Data Register. This register contains the result of the most recent conversion completed on channel 0." reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + <BitField start="4" size="12" name="RESULT" description="This field contains the 12-bit A/D conversion result from the last conversion performed on this channel. This will be a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VREFN, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP." /> + <BitField start="16" size="2" name="THCMPRANGE" description="Threshold Range Comparison result. 0x0 = In Range: The last completed conversion was greater than or equal to the value programmed into the designated LOW threshold register (THRn_LOW) but less than or equal to the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x1 = Below Range: The last completed conversion on was less than the value programmed into the designated LOW threshold register (THRn_LOW). 0x2 = Above Range: The last completed conversion was greater than the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x3 = Reserved." /> + <BitField start="18" size="2" name="THCMPCROSS" description="Threshold Crossing Comparison result. 0x0 = No threshold Crossing detected: The most recent completed conversion on this channel had the same relationship (above or below) to the threshold value established by the designated LOW threshold register (THRn_LOW) as did the previous conversion on this channel. 0x1 = Reserved. 0x2 = Downward Threshold Crossing Detected. Indicates that a threshold crossing in the downward direction has occurred - i.e. the previous sample on this channel was above the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is below that threshold. 0x3 = Upward Threshold Crossing Detected. Indicates that a threshold crossing in the upward direction has occurred - i.e. the previous sample on this channel was below the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is above that threshold." /> + <BitField start="20" size="6" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + <BitField start="26" size="4" name="CHANNEL" description="This field is hard-coded to contain the channel number that this particular register relates to (i.e. this field will contain 0b0000 for the DAT0 register, 0b0001 for the DAT1 register, etc)" /> + <BitField start="30" size="1" name="OVERRUN" description="This bit will be set to a 1 if a new conversion on this channel completes and overwrites the previous contents of the RESULT field before it has been read - i.e. while the DONE bit is set. This bit is cleared, along with the DONE bit, whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. This bit (in any of the 12 registers) will cause an overrun interrupt request to be asserted if the overrun interrupt is enabled. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled." /> + <BitField start="31" size="1" name="DATAVALID" description="This bit is set to 1 when an A/D conversion on this channel completes. This bit is cleared whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled." /> + </Register> + <Register start="+0x020+28" size="4" name="DAT[7]" access="ReadOnly" description="A/D Channel 0 Data Register. This register contains the result of the most recent conversion completed on channel 0." reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + <BitField start="4" size="12" name="RESULT" description="This field contains the 12-bit A/D conversion result from the last conversion performed on this channel. This will be a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VREFN, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP." /> + <BitField start="16" size="2" name="THCMPRANGE" description="Threshold Range Comparison result. 0x0 = In Range: The last completed conversion was greater than or equal to the value programmed into the designated LOW threshold register (THRn_LOW) but less than or equal to the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x1 = Below Range: The last completed conversion on was less than the value programmed into the designated LOW threshold register (THRn_LOW). 0x2 = Above Range: The last completed conversion was greater than the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x3 = Reserved." /> + <BitField start="18" size="2" name="THCMPCROSS" description="Threshold Crossing Comparison result. 0x0 = No threshold Crossing detected: The most recent completed conversion on this channel had the same relationship (above or below) to the threshold value established by the designated LOW threshold register (THRn_LOW) as did the previous conversion on this channel. 0x1 = Reserved. 0x2 = Downward Threshold Crossing Detected. Indicates that a threshold crossing in the downward direction has occurred - i.e. the previous sample on this channel was above the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is below that threshold. 0x3 = Upward Threshold Crossing Detected. Indicates that a threshold crossing in the upward direction has occurred - i.e. the previous sample on this channel was below the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is above that threshold." /> + <BitField start="20" size="6" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + <BitField start="26" size="4" name="CHANNEL" description="This field is hard-coded to contain the channel number that this particular register relates to (i.e. this field will contain 0b0000 for the DAT0 register, 0b0001 for the DAT1 register, etc)" /> + <BitField start="30" size="1" name="OVERRUN" description="This bit will be set to a 1 if a new conversion on this channel completes and overwrites the previous contents of the RESULT field before it has been read - i.e. while the DONE bit is set. This bit is cleared, along with the DONE bit, whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. This bit (in any of the 12 registers) will cause an overrun interrupt request to be asserted if the overrun interrupt is enabled. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled." /> + <BitField start="31" size="1" name="DATAVALID" description="This bit is set to 1 when an A/D conversion on this channel completes. This bit is cleared whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled." /> + </Register> + <Register start="+0x020+32" size="4" name="DAT[8]" access="ReadOnly" description="A/D Channel 0 Data Register. This register contains the result of the most recent conversion completed on channel 0." reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + <BitField start="4" size="12" name="RESULT" description="This field contains the 12-bit A/D conversion result from the last conversion performed on this channel. This will be a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VREFN, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP." /> + <BitField start="16" size="2" name="THCMPRANGE" description="Threshold Range Comparison result. 0x0 = In Range: The last completed conversion was greater than or equal to the value programmed into the designated LOW threshold register (THRn_LOW) but less than or equal to the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x1 = Below Range: The last completed conversion on was less than the value programmed into the designated LOW threshold register (THRn_LOW). 0x2 = Above Range: The last completed conversion was greater than the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x3 = Reserved." /> + <BitField start="18" size="2" name="THCMPCROSS" description="Threshold Crossing Comparison result. 0x0 = No threshold Crossing detected: The most recent completed conversion on this channel had the same relationship (above or below) to the threshold value established by the designated LOW threshold register (THRn_LOW) as did the previous conversion on this channel. 0x1 = Reserved. 0x2 = Downward Threshold Crossing Detected. Indicates that a threshold crossing in the downward direction has occurred - i.e. the previous sample on this channel was above the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is below that threshold. 0x3 = Upward Threshold Crossing Detected. Indicates that a threshold crossing in the upward direction has occurred - i.e. the previous sample on this channel was below the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is above that threshold." /> + <BitField start="20" size="6" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + <BitField start="26" size="4" name="CHANNEL" description="This field is hard-coded to contain the channel number that this particular register relates to (i.e. this field will contain 0b0000 for the DAT0 register, 0b0001 for the DAT1 register, etc)" /> + <BitField start="30" size="1" name="OVERRUN" description="This bit will be set to a 1 if a new conversion on this channel completes and overwrites the previous contents of the RESULT field before it has been read - i.e. while the DONE bit is set. This bit is cleared, along with the DONE bit, whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. This bit (in any of the 12 registers) will cause an overrun interrupt request to be asserted if the overrun interrupt is enabled. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled." /> + <BitField start="31" size="1" name="DATAVALID" description="This bit is set to 1 when an A/D conversion on this channel completes. This bit is cleared whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled." /> + </Register> + <Register start="+0x020+36" size="4" name="DAT[9]" access="ReadOnly" description="A/D Channel 0 Data Register. This register contains the result of the most recent conversion completed on channel 0." reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + <BitField start="4" size="12" name="RESULT" description="This field contains the 12-bit A/D conversion result from the last conversion performed on this channel. This will be a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VREFN, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP." /> + <BitField start="16" size="2" name="THCMPRANGE" description="Threshold Range Comparison result. 0x0 = In Range: The last completed conversion was greater than or equal to the value programmed into the designated LOW threshold register (THRn_LOW) but less than or equal to the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x1 = Below Range: The last completed conversion on was less than the value programmed into the designated LOW threshold register (THRn_LOW). 0x2 = Above Range: The last completed conversion was greater than the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x3 = Reserved." /> + <BitField start="18" size="2" name="THCMPCROSS" description="Threshold Crossing Comparison result. 0x0 = No threshold Crossing detected: The most recent completed conversion on this channel had the same relationship (above or below) to the threshold value established by the designated LOW threshold register (THRn_LOW) as did the previous conversion on this channel. 0x1 = Reserved. 0x2 = Downward Threshold Crossing Detected. Indicates that a threshold crossing in the downward direction has occurred - i.e. the previous sample on this channel was above the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is below that threshold. 0x3 = Upward Threshold Crossing Detected. Indicates that a threshold crossing in the upward direction has occurred - i.e. the previous sample on this channel was below the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is above that threshold." /> + <BitField start="20" size="6" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + <BitField start="26" size="4" name="CHANNEL" description="This field is hard-coded to contain the channel number that this particular register relates to (i.e. this field will contain 0b0000 for the DAT0 register, 0b0001 for the DAT1 register, etc)" /> + <BitField start="30" size="1" name="OVERRUN" description="This bit will be set to a 1 if a new conversion on this channel completes and overwrites the previous contents of the RESULT field before it has been read - i.e. while the DONE bit is set. This bit is cleared, along with the DONE bit, whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. This bit (in any of the 12 registers) will cause an overrun interrupt request to be asserted if the overrun interrupt is enabled. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled." /> + <BitField start="31" size="1" name="DATAVALID" description="This bit is set to 1 when an A/D conversion on this channel completes. This bit is cleared whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled." /> + </Register> + <Register start="+0x020+40" size="4" name="DAT[10]" access="ReadOnly" description="A/D Channel 0 Data Register. This register contains the result of the most recent conversion completed on channel 0." reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + <BitField start="4" size="12" name="RESULT" description="This field contains the 12-bit A/D conversion result from the last conversion performed on this channel. This will be a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VREFN, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP." /> + <BitField start="16" size="2" name="THCMPRANGE" description="Threshold Range Comparison result. 0x0 = In Range: The last completed conversion was greater than or equal to the value programmed into the designated LOW threshold register (THRn_LOW) but less than or equal to the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x1 = Below Range: The last completed conversion on was less than the value programmed into the designated LOW threshold register (THRn_LOW). 0x2 = Above Range: The last completed conversion was greater than the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x3 = Reserved." /> + <BitField start="18" size="2" name="THCMPCROSS" description="Threshold Crossing Comparison result. 0x0 = No threshold Crossing detected: The most recent completed conversion on this channel had the same relationship (above or below) to the threshold value established by the designated LOW threshold register (THRn_LOW) as did the previous conversion on this channel. 0x1 = Reserved. 0x2 = Downward Threshold Crossing Detected. Indicates that a threshold crossing in the downward direction has occurred - i.e. the previous sample on this channel was above the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is below that threshold. 0x3 = Upward Threshold Crossing Detected. Indicates that a threshold crossing in the upward direction has occurred - i.e. the previous sample on this channel was below the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is above that threshold." /> + <BitField start="20" size="6" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + <BitField start="26" size="4" name="CHANNEL" description="This field is hard-coded to contain the channel number that this particular register relates to (i.e. this field will contain 0b0000 for the DAT0 register, 0b0001 for the DAT1 register, etc)" /> + <BitField start="30" size="1" name="OVERRUN" description="This bit will be set to a 1 if a new conversion on this channel completes and overwrites the previous contents of the RESULT field before it has been read - i.e. while the DONE bit is set. This bit is cleared, along with the DONE bit, whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. This bit (in any of the 12 registers) will cause an overrun interrupt request to be asserted if the overrun interrupt is enabled. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled." /> + <BitField start="31" size="1" name="DATAVALID" description="This bit is set to 1 when an A/D conversion on this channel completes. This bit is cleared whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled." /> + </Register> + <Register start="+0x020+44" size="4" name="DAT[11]" access="ReadOnly" description="A/D Channel 0 Data Register. This register contains the result of the most recent conversion completed on channel 0." reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + <BitField start="4" size="12" name="RESULT" description="This field contains the 12-bit A/D conversion result from the last conversion performed on this channel. This will be a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VREFN, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP." /> + <BitField start="16" size="2" name="THCMPRANGE" description="Threshold Range Comparison result. 0x0 = In Range: The last completed conversion was greater than or equal to the value programmed into the designated LOW threshold register (THRn_LOW) but less than or equal to the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x1 = Below Range: The last completed conversion on was less than the value programmed into the designated LOW threshold register (THRn_LOW). 0x2 = Above Range: The last completed conversion was greater than the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x3 = Reserved." /> + <BitField start="18" size="2" name="THCMPCROSS" description="Threshold Crossing Comparison result. 0x0 = No threshold Crossing detected: The most recent completed conversion on this channel had the same relationship (above or below) to the threshold value established by the designated LOW threshold register (THRn_LOW) as did the previous conversion on this channel. 0x1 = Reserved. 0x2 = Downward Threshold Crossing Detected. Indicates that a threshold crossing in the downward direction has occurred - i.e. the previous sample on this channel was above the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is below that threshold. 0x3 = Upward Threshold Crossing Detected. Indicates that a threshold crossing in the upward direction has occurred - i.e. the previous sample on this channel was below the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is above that threshold." /> + <BitField start="20" size="6" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + <BitField start="26" size="4" name="CHANNEL" description="This field is hard-coded to contain the channel number that this particular register relates to (i.e. this field will contain 0b0000 for the DAT0 register, 0b0001 for the DAT1 register, etc)" /> + <BitField start="30" size="1" name="OVERRUN" description="This bit will be set to a 1 if a new conversion on this channel completes and overwrites the previous contents of the RESULT field before it has been read - i.e. while the DONE bit is set. This bit is cleared, along with the DONE bit, whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. This bit (in any of the 12 registers) will cause an overrun interrupt request to be asserted if the overrun interrupt is enabled. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled." /> + <BitField start="31" size="1" name="DATAVALID" description="This bit is set to 1 when an A/D conversion on this channel completes. This bit is cleared whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled." /> + </Register> + <Register start="+0x050" size="4" name="THR0_LOW" access="Read/Write" description="A/D Low Compare Threshold Register 0 : Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 0." reset_value="0x0" reset_mask="0xFFFFFFFF"> + <BitField start="4" size="12" name="THRLOW" description="Low threshold value against which A/D results will be compared" /> + <BitField start="16" size="16" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x054" size="4" name="THR1_LOW" access="Read/Write" description="A/D Low Compare Threshold Register 1: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 1." reset_value="0x0" reset_mask="0xFFFFFFFF"> + <BitField start="4" size="12" name="THRLOW" description="Low threshold value against which A/D results will be compared" /> + <BitField start="16" size="16" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x058" size="4" name="THR0_HIGH" access="Read/Write" description="A/D High Compare Threshold Register 0: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 0." reset_value="0x0" reset_mask="0xFFFFFFFF"> + <BitField start="4" size="12" name="THRHIGH" description="High threshold value against which A/D results will be compared" /> + <BitField start="16" size="16" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x05C" size="4" name="THR1_HIGH" access="Read/Write" description="A/D High Compare Threshold Register 1: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 1." reset_value="0x0" reset_mask="0xFFFFFFFF"> + <BitField start="4" size="12" name="THRHIGH" description="High threshold value against which A/D results will be compared" /> + <BitField start="16" size="16" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x060" size="4" name="CHAN_THRSEL" access="ReadOnly" description="A/D Channel-Threshold Select Register. Specifies which set of threshold compare registers are to be used for each channel" reset_value="0x0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="CH0_THRSEL" description="Threshold select by channel."> + <Enum name="THRESHOLD_0" start="0" description="Threshold 0. Channel 0 results will be compared against the threshold levels indicated in the THR0_LOW and THR0_HIGH registers" /> + <Enum name="THRESHOLD_1" start="1" description="Threshold 1. Channel 0 results will be compared against the threshold levels indicated in the THR1_LOW and THR1_HIGH registers" /> + </BitField> + <BitField start="1" size="1" name="CH1_THRSEL" description="Threshold select by channel."> + <Enum name="THRESHOLD_0" start="0" description="Threshold 0. Channel 1 results will be compared against the threshold levels indicated in the THR0_LOW and THR0_HIGH registers" /> + <Enum name="THRESHOLD_1" start="1" description="Threshold 1. Channel 1 results will be compared against the threshold levels indicated in the THR1_LOW and THR1_HIGH registers" /> + </BitField> + <BitField start="2" size="1" name="CH2_THRSEL" description="Threshold select by channel."> + <Enum name="THRESHOLD_0" start="0" description="Threshold 0. Channel 2 results will be compared against the threshold levels indicated in the THR0_LOW and THR0_HIGH registers" /> + <Enum name="THRESHOLD_1" start="1" description="Threshold 1. Channel 2 results will be compared against the threshold levels indicated in the THR1_LOW and THR1_HIGH registers" /> + </BitField> + <BitField start="3" size="1" name="CH3_THRSEL" description="Threshold select by channel."> + <Enum name="THRESHOLD_0" start="0" description="Threshold 0. Channel 3 results will be compared against the threshold levels indicated in the THR0_LOW and THR0_HIGH registers" /> + <Enum name="THRESHOLD_1" start="1" description="Threshold 1. Channel 3 results will be compared against the threshold levels indicated in the THR1_LOW and THR1_HIGH registers" /> + </BitField> + <BitField start="4" size="1" name="CH4_THRSEL" description="Threshold select by channel."> + <Enum name="THRESHOLD_0" start="0" description="Threshold 0. Channel 4 results will be compared against the threshold levels indicated in the THR0_LOW and THR0_HIGH registers" /> + <Enum name="THRESHOLD_1" start="1" description="Threshold 1. Channel 4 results will be compared against the threshold levels indicated in the THR1_LOW and THR1_HIGH registers" /> + </BitField> + <BitField start="5" size="1" name="CH5_THRSEL" description="Threshold select by channel."> + <Enum name="THRESHOLD_0" start="0" description="Threshold 0. Channel 5 results will be compared against the threshold levels indicated in the THR0_LOW and THR0_HIGH registers" /> + <Enum name="THRESHOLD_1" start="1" description="Threshold 1. Channel 5 results will be compared against the threshold levels indicated in the THR1_LOW and THR1_HIGH registers" /> + </BitField> + <BitField start="6" size="1" name="CH6_THRSEL" description="Threshold select by channel."> + <Enum name="THRESHOLD_0" start="0" description="Threshold 0. Channel 6 results will be compared against the threshold levels indicated in the THR0_LOW and THR0_HIGH registers" /> + <Enum name="THRESHOLD_1" start="1" description="Threshold 1. Channel 6 results will be compared against the threshold levels indicated in the THR1_LOW and THR1_HIGH registers" /> + </BitField> + <BitField start="7" size="1" name="CH7_THRSEL" description="Threshold select by channel."> + <Enum name="THRESHOLD_0" start="0" description="Threshold 0. Channel 7 results will be compared against the threshold levels indicated in the THR0_LOW and THR0_HIGH registers" /> + <Enum name="THRESHOLD_1" start="1" description="Threshold 1. Channel 7 results will be compared against the threshold levels indicated in the THR1_LOW and THR1_HIGH registers" /> + </BitField> + <BitField start="8" size="1" name="CH8_THRSEL" description="Threshold select by channel."> + <Enum name="THRESHOLD_0" start="0" description="Threshold 0. Channel 8 results will be compared against the threshold levels indicated in the THR0_LOW and THR0_HIGH registers" /> + <Enum name="THRESHOLD_1" start="1" description="Threshold 1. Channel 8 results will be compared against the threshold levels indicated in the THR1_LOW and THR1_HIGH registers" /> + </BitField> + <BitField start="9" size="1" name="CH9_THRSEL" description="Threshold select by channel."> + <Enum name="THRESHOLD_0" start="0" description="Threshold 0. Channel 9 results will be compared against the threshold levels indicated in the THR0_LOW and THR0_HIGH registers" /> + <Enum name="THRESHOLD_1" start="1" description="Threshold 1. Channel 9 results will be compared against the threshold levels indicated in the THR1_LOW and THR1_HIGH registers" /> + </BitField> + <BitField start="10" size="1" name="CH10_THRSEL" description="Threshold select by channel."> + <Enum name="THRESHOLD_0" start="0" description="Threshold 0. Channel 10 results will be compared against the threshold levels indicated in the THR0_LOW and THR0_HIGH registers" /> + <Enum name="THRESHOLD_1" start="1" description="Threshold 1. Channel 10 results will be compared against the threshold levels indicated in the THR1_LOW and THR1_HIGH registers" /> + </BitField> + <BitField start="11" size="1" name="CH11_THRSEL" description="Threshold select by channel."> + <Enum name="THRESHOLD_0" start="0" description="Threshold 0. Channel 11 results will be compared against the threshold levels indicated in the THR0_LOW and THR0_HIGH registers" /> + <Enum name="THRESHOLD_1" start="1" description="Threshold 1. Channel 11 results will be compared against the threshold levels indicated in the THR1_LOW and THR1_HIGH registers" /> + </BitField> + </Register> + <Register start="+0x064" size="4" name="INTEN" access="Read/Write" description="A/D Interrupt Enable Register. This register contains enable bits that enable the sequence-A, sequence-B, threshold compare and data overrun interrupts to be generated." reset_value="0x0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="SEQA_INTEN" description="Sequence A interrupt enable."> + <Enum name="DISABLED" start="0" description="Disabled. The sequence A interrupt/DMA request is disabled." /> + <Enum name="ENABLED" start="1" description="Enabled. The sequence A interrupt/DMA request is enabled and will be asserted either upon completion of each individual conversion performed as part of sequence A, or upon completion of the entire A sequence of conversions, depending on the MODE bit in the SEQA_CTRL register." /> + </BitField> + <BitField start="1" size="1" name="SEQB_INTEN" description="Sequence B interrupt enable."> + <Enum name="DISABLED" start="0" description="Disabled. The sequence B interrupt/DMA request is disabled." /> + <Enum name="ENABLED" start="1" description="Enabled. The sequence B interrupt/DMA request is enabled and will be asserted either upon completion of each individual conversion performed as part of sequence B, or upon completion of the entire B sequence of conversions, depending on the MODE bit in the SEQB_CTRL register." /> + </BitField> + <BitField start="2" size="1" name="OVR_INTEN" description="Overrun interrupt enable."> + <Enum name="DISABLED" start="0" description="Disabled. The overrun interrupt is disabled." /> + <Enum name="ENABLED" start="1" description="Enabled. The overrun interrupt is enabled. Detection of an overrun condition on any of the 12 channel data registers will cause an overrun interrupt request. In addition, if the MODE bit for a particular sequence is 0, then an overrun in the global data register for that sequence will also cause this interrupt request to be asserted." /> + </BitField> + <BitField start="3" size="2" name="ADCMPINTEN0" description="Threshold comparison interrupt enable."> + <Enum name="DISABLED" start="0x0" description="Disabled." /> + <Enum name="OUTSIDE_THRESHOLD" start="0x1" description="Outside threshold." /> + <Enum name="CROSSING_THRESHOLD" start="0x2" description="Crossing threshold." /> + <Enum name="RESERVED" start="0x3" description="Reserved" /> + </BitField> + <BitField start="5" size="2" name="ADCMPINTEN1" description="Threshold comparison interrupt enable."> + <Enum name="DISABLED" start="0x0" description="Disabled." /> + <Enum name="OUTSIDE_THRESHOLD" start="0x1" description="Outside threshold." /> + <Enum name="CROSSING_THRESHOLD" start="0x2" description="Crossing threshold." /> + <Enum name="RESERVED" start="0x3" description="Reserved." /> + </BitField> + <BitField start="7" size="2" name="ADCMPINTEN2" description="Threshold comparison interrupt enable."> + <Enum name="DISABLED" start="0x0" description="Disabled." /> + <Enum name="OUTSIDE_THRESHOLD" start="0x1" description="Outside threshold." /> + <Enum name="CROSSING_THRESHOLD" start="0x2" description="Crossing threshold." /> + <Enum name="RESERVED" start="0x3" description="Reserved" /> + </BitField> + <BitField start="9" size="2" name="ADCMPINTEN3" description="Threshold comparison interrupt enable."> + <Enum name="DISABLED" start="0x0" description="Disabled." /> + <Enum name="OUTSIDE_THRESHOLD" start="0x1" description="Outside threshold." /> + <Enum name="CROSSING_THRESHOLD" start="0x2" description="Crossing threshold." /> + <Enum name="RESERVED" start="0x3" description="Reserved" /> + </BitField> + <BitField start="11" size="2" name="ADCMPINTEN4" description="Threshold comparison interrupt enable."> + <Enum name="DISABLED" start="0x0" description="Disabled." /> + <Enum name="OUTSIDE_THRESHOLD" start="0x1" description="Outside threshold." /> + <Enum name="CROSSING_THRESHOLD" start="0x2" description="Crossing threshold." /> + <Enum name="RESERVED" start="0x3" description="Reserved" /> + </BitField> + <BitField start="13" size="2" name="ADCMPINTEN5" description="Threshold comparison interrupt enable."> + <Enum name="DISABLED" start="0x0" description="Disabled." /> + <Enum name="OUTSIDE_THRESHOLD" start="0x1" description="Outside threshold." /> + <Enum name="CROSSING_THRESHOLD" start="0x2" description="Crossing threshold." /> + <Enum name="RESERVED" start="0x3" description="Reserved" /> + </BitField> + <BitField start="15" size="2" name="ADCMPINTEN6" description="Threshold comparison interrupt enable."> + <Enum name="DISABLED" start="0x0" description="Disabled." /> + <Enum name="OUTSIDE_THRESHOLD" start="0x1" description="Outside threshold." /> + <Enum name="CROSSING_THRESHOLD" start="0x2" description="Crossing threshold." /> + <Enum name="RESERVED" start="0x3" description="Reserved." /> + </BitField> + <BitField start="17" size="2" name="ADCMPINTEN7" description="Threshold comparison interrupt enable."> + <Enum name="DISABLED" start="0x0" description="Disabled." /> + <Enum name="OUTSIDE_THRESHOLD" start="0x1" description="Outside threshold." /> + <Enum name="CROSSING_THRESHOLD" start="0x2" description="Crossing threshold." /> + <Enum name="RESERVED" start="0x3" description="Reserved" /> + </BitField> + <BitField start="19" size="2" name="ADCMPINTEN8" description="Threshold comparison interrupt enable."> + <Enum name="DISABLED" start="0x0" description="Disabled." /> + <Enum name="OUTSIDE_THRESHOLD" start="0x1" description="Outside threshold." /> + <Enum name="CROSSING_THRESHOLD" start="0x2" description="Crossing threshold." /> + <Enum name="RESERVED" start="0x3" description="Reserved" /> + </BitField> + <BitField start="21" size="2" name="ADCMPINTEN9" description="Threshold comparison interrupt enable."> + <Enum name="DISABLED" start="0x0" description="Disabled." /> + <Enum name="OUTSIDE_THRESHOLD" start="0x1" description="Outside threshold." /> + <Enum name="CROSSING_THRESHOLD" start="0x2" description="Crossing threshold." /> + <Enum name="RESERVED" start="0x3" description="Reserved" /> + </BitField> + <BitField start="23" size="2" name="ADCMPINTEN10" description="Threshold comparison interrupt enable."> + <Enum name="DISABLED" start="0x0" description="Disabled." /> + <Enum name="OUTSIDE_THRESHOLD" start="0x1" description="Outside threshold." /> + <Enum name="CROSSING_THRESHOLD" start="0x2" description="Crossing threshold." /> + <Enum name="RESERVED" start="0x3" description="Reserved" /> + </BitField> + <BitField start="25" size="2" name="ADCMPINTEN11" description="Threshold comparison interrupt enable."> + <Enum name="DISABLED" start="0x0" description="Disabled." /> + <Enum name="OUTSIDE_THRESHOLD" start="0x1" description="Outside threshold." /> + <Enum name="CROSSING_THRESHOLD" start="0x2" description="Crossing threshold." /> + <Enum name="RESERVED" start="0x3" description="Reserved" /> + </BitField> + <BitField start="27" size="5" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x068" size="4" name="FLAGS" access="ReadOnly" description="A/D Flags Register. Contains the four interrupt request flags and the individual component overrun and threshold-compare flags. (The overrun bits replicate information stored in the result registers)." reset_value="0x0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="THCMP0" description="Threshold comparison event on Channel 0. Set to 1 upon either an out-of-range result or a threshold-crossing result if enabled to do so in the INTEN register. This bit is cleared by writing a 1." /> + <BitField start="1" size="1" name="THCMP1" description="Threshold comparison event on Channel 1. Set to 1 upon either an out-of-range result or a threshold-crossing result if enabled to do so in the INTEN register. This bit is cleared by writing a 1." /> + <BitField start="2" size="1" name="THCMP2" description="Threshold comparison event on Channel 2. Set to 1 upon either an out-of-range result or a threshold-crossing result if enabled to do so in the INTEN register. This bit is cleared by writing a 1." /> + <BitField start="3" size="1" name="THCMP3" description="Threshold comparison event on Channel 3. Set to 1 upon either an out-of-range result or a threshold-crossing result if enabled to do so in the INTEN register. This bit is cleared by writing a 1." /> + <BitField start="4" size="1" name="THCMP4" description="Threshold comparison event on Channel 4. Set to 1 upon either an out-of-range result or a threshold-crossing result if enabled to do so in the INTEN register. This bit is cleared by writing a 1." /> + <BitField start="5" size="1" name="THCMP5" description="Threshold comparison event on Channel 5. Set to 1 upon either an out-of-range result or a threshold-crossing result if enabled to do so in the INTEN register. This bit is cleared by writing a 1." /> + <BitField start="6" size="1" name="THCMP6" description="Threshold comparison event on Channel 6. Set to 1 upon either an out-of-range result or a threshold-crossing result if enabled to do so in the INTEN register. This bit is cleared by writing a 1." /> + <BitField start="7" size="1" name="THCMP7" description="Threshold comparison event on Channel 7. Set to 1 upon either an out-of-range result or a threshold-crossing result if enabled to do so in the INTEN register. This bit is cleared by writing a 1." /> + <BitField start="8" size="1" name="THCMP8" description="Threshold comparison event on Channel 8. Set to 1 upon either an out-of-range result or a threshold-crossing result if enabled to do so in the INTEN register. This bit is cleared by writing a 1." /> + <BitField start="9" size="1" name="THCMP9" description="Threshold comparison event on Channel 9. Set to 1 upon either an out-of-range result or a threshold-crossing result if enabled to do so in the INTEN register. This bit is cleared by writing a 1." /> + <BitField start="10" size="1" name="THCMP10" description="Threshold comparison event on Channel 10. Set to 1 upon either an out-of-range result or a threshold-crossing result if enabled to do so in the INTEN register. This bit is cleared by writing a 1." /> + <BitField start="11" size="1" name="THCMP11" description="Threshold comparison event on Channel 11. Set to 1 upon either an out-of-range result or a threshold-crossing result if enabled to do so in the INTEN register. This bit is cleared by writing a 1." /> + <BitField start="12" size="1" name="OVERRUN0" description="Mirrors the OVERRRUN status flag from the result register for A/D channel 0" /> + <BitField start="13" size="1" name="OVERRUN1" description="Mirrors the OVERRRUN status flag from the result register for A/D channel 1" /> + <BitField start="14" size="1" name="OVERRUN2" description="Mirrors the OVERRRUN status flag from the result register for A/D channel 2" /> + <BitField start="15" size="1" name="OVERRUN3" description="Mirrors the OVERRRUN status flag from the result register for A/D channel 3" /> + <BitField start="16" size="1" name="OVERRUN4" description="Mirrors the OVERRRUN status flag from the result register for A/D channel 4" /> + <BitField start="17" size="1" name="OVERRUN5" description="Mirrors the OVERRRUN status flag from the result register for A/D channel 5" /> + <BitField start="18" size="1" name="OVERRUN6" description="Mirrors the OVERRRUN status flag from the result register for A/D channel 6" /> + <BitField start="19" size="1" name="OVERRUN7" description="Mirrors the OVERRRUN status flag from the result register for A/D channel 7" /> + <BitField start="20" size="1" name="OVERRUN8" description="Mirrors the OVERRRUN status flag from the result register for A/D channel 8" /> + <BitField start="21" size="1" name="OVERRUN9" description="Mirrors the OVERRRUN status flag from the result register for A/D channel 9" /> + <BitField start="22" size="1" name="OVERRUN10" description="Mirrors the OVERRRUN status flag from the result register for A/D channel 10" /> + <BitField start="23" size="1" name="OVERRUN11" description="Mirrors the OVERRRUN status flag from the result register for A/D channel 11" /> + <BitField start="24" size="1" name="SEQA_OVR" description="Mirrors the global OVERRUN status flag in the SEQA_GDAT register" /> + <BitField start="25" size="1" name="SEQB_OVR" description="Mirrors the global OVERRUN status flag in the SEQB_GDAT register" /> + <BitField start="26" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + <BitField start="28" size="1" name="SEQA_INT" description="Sequence A interrupt/DMA flag. If the MODE bit in the SEQA_CTRL register is 0, this flag will mirror the DATAVALID bit in the sequence A global data register (SEQA_GDAT), which is set at the end of every A/D conversion performed as part of sequence A. It will be cleared automatically when the SEQA_GDAT register is read. If the MODE bit in the SEQA_CTRL register is 1, this flag will be set upon completion of an entire A sequence. In this case it must be cleared by writing a 1 to this SEQA_INT bit. This interrupt must be enabled in the INTEN register." /> + <BitField start="29" size="1" name="SEQB_INT" description="Sequence A interrupt/DMA flag. If the MODE bit in the SEQB_CTRL register is 0, this flag will mirror the DATAVALID bit in the sequence A global data register (SEQB_GDAT), which is set at the end of every A/D conversion performed as part of sequence B. It will be cleared automatically when the SEQB_GDAT register is read. If the MODE bit in the SEQB_CTRL register is 1, this flag will be set upon completion of an entire B sequence. In this case it must be cleared by writing a 1 to this SEQB_INT bit. This interrupt must be enabled in the INTEN register." /> + <BitField start="30" size="1" name="THCMP_INT" description="Threshold Comparison Interrupt/DMA flag. This bit will be set if any of the 12 THCMP flags in the lower bits of this register are set to 1 (due to an enabled out-of-range or threshold-crossing event on any channel). Each type of threshold comparison interrupt on each channel must be individually enabled in the INTEN register to cause this interrupt. This bit will be cleared when all of the component flags in bits 11:0 are cleared via writing 1s to those bits." /> + <BitField start="31" size="1" name="OVR_INT" description="Overrun Interrupt flag. Any overrun bit in any of the individual channel data registers will cause this interrupt. In addition, if the MODE bit in either of the SEQn_CTRL registers is 0 then the OVERRUN bit in the corresponding SEQn_GDAT register will also cause this interrupt. This interrupt must be enabled in the INTEN register. This bit will be cleared when all of the individual overrun bits have been cleared via reading the corresponding data registers." /> + </Register> + <Register start="+0x06C" size="4" name="TRM" access="Read/Write" description="ADC trim register." reset_value="0x00000F00" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="RESERVED" description="Reserved." /> + <BitField start="5" size="1" name="VRANGE" description="Reserved."> + <Enum name="HIGH_VOLTAGE" start="0" description="High voltage. VDDA = 2.7 V to 3.6 V." /> + <Enum name="LOW_VOLTAGE" start="1" description="Low voltage. VDDA = 1.8 V to 2.7 V." /> + </BitField> + <BitField start="6" size="26" name="RESERVED" description="Reserved." /> + </Register> + </RegisterGroup> + <RegisterGroup name="I2C1" start="0x40020000" description="I2C1"> + <Register start="+0x000" size="4" name="CONSET" access="Read/Write" description="I2C Control Set Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is set. Writing a zero has no effect on the corresponding bit in the I2C control register." reset_value="0x00" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + <BitField start="2" size="1" name="AA" description="Assert acknowledge flag." /> + <BitField start="3" size="1" name="SI" description="I2C interrupt flag." /> + <BitField start="4" size="1" name="STO" description="STOP flag." /> + <BitField start="5" size="1" name="STA" description="START flag." /> + <BitField start="6" size="1" name="I2EN" description="I2C interface enable." /> + <BitField start="7" size="25" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x004" size="4" name="STAT" access="ReadOnly" description="I2C Status Register. During I2C operation, this register provides detailed status codes that allow software to determine the next action needed." reset_value="0xF8" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="RESERVED" description="These bits are unused and are always 0." /> + <BitField start="3" size="5" name="STATUS" description="These bits give the actual status information about the I2C interface." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x008" size="4" name="DAT" access="Read/Write" description="I2C Data Register. During master or slave transmit mode, data to be transmitted is written to this register. During master or slave receive mode, data that has been received may be read from this register." reset_value="0x00" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="Data" description="This register holds data values that have been received or are to be transmitted." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x00C" size="4" name="ADR0" access="Read/Write" description="I2C Slave Address Register 0. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="GC" description="General Call enable bit." /> + <BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x010" size="4" name="SCLH" access="Read/Write" description="SCH Duty Cycle Register High Half Word. Determines the high time of the I2C clock." reset_value="0x04" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="16" name="SCLH" description="Count for SCL HIGH time period selection." /> + <BitField start="16" size="16" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x014" size="4" name="SCLL" access="Read/Write" description="SCL Duty Cycle Register Low Half Word. Determines the low time of the I2C clock. I2nSCLL and I2nSCLH together determine the clock frequency generated by an I2C master and certain times used in slave mode." reset_value="0x04" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="16" name="SCLL" description="Count for SCL low time period selection." /> + <BitField start="16" size="16" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x018" size="4" name="CONCLR" access="WriteOnly" description="I2C Control Clear Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is cleared. Writing a zero has no effect on the corresponding bit in the I2C control register." reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="2" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + <BitField start="2" size="1" name="AAC" description="Assert acknowledge Clear bit." /> + <BitField start="3" size="1" name="SIC" description="I2C interrupt Clear bit." /> + <BitField start="4" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + <BitField start="5" size="1" name="STAC" description="START flag Clear bit." /> + <BitField start="6" size="1" name="I2ENC" description="I2C interface Disable bit." /> + <BitField start="7" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x01C" size="4" name="MMCTRL" access="Read/Write" description="Monitor mode control register." reset_value="0x00" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="MM_ENA" description="Monitor mode enable."> + <Enum name="MONITOR_MODE_DISABLE" start="0" description="Monitor mode disabled." /> + <Enum name="THE_I2C_MODULE_WILL_" start="1" description="The I2C module will enter monitor mode. In this mode the SDA output will be forced high. This will prevent the I2C module from outputting data of any kind (including ACK) onto the I 2C data bus. Depending on the state of the ENA_SCL bit, the output may be also forced high, preventing the module from having control over the I2C clock line." /> + </BitField> + <BitField start="1" size="1" name="ENA_SCL" description="SCL output enable."> + <Enum name="HIGH" start="0" description="When this bit is cleared to 0, the SCL output will be forced high when the module is in monitor mode. As described above, this will prevent the module from having any control over the I2C clock line." /> + <Enum name="NORMAL" start="1" description="When this bit is set, the I2C module may exercise the same control over the clock line that it would in normal operation. This means that, acting as a slave peripheral, the I2C module can stretch the clock line (hold it low) until it has had time to respond to an I2C interrupt.[1]" /> + </BitField> + <BitField start="2" size="1" name="MATCH_ALL" description="Select interrupt register match."> + <Enum name="MATCH" start="0" description="When this bit is cleared, an interrupt will only be generated when a match occurs to one of the (up-to) four address registers described above. That is, the module will respond as a normal slave as far as address-recognition is concerned." /> + <Enum name="ANYADDRESS" start="1" description="When this bit is set to 1 and the I2C is in monitor mode, an interrupt will be generated on ANY address received. This will enable the part to monitor all traffic on the bus." /> + </BitField> + <BitField start="3" size="29" name="RESERVED" description="Reserved. The value read from reserved bits is not defined." /> + </Register> + <Register start="+0x020+0" size="4" name="ADR1" access="Read/Write" description="I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="GC" description="General Call enable bit." /> + <BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x020+4" size="4" name="ADR2" access="Read/Write" description="I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="GC" description="General Call enable bit." /> + <BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x020+8" size="4" name="ADR3" access="Read/Write" description="I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="GC" description="General Call enable bit." /> + <BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x02C" size="4" name="DATA_BUFFER" access="ReadOnly" description="Data buffer register. The contents of the 8 MSBs of the I2DAT shift register will be transferred to the DATA_BUFFER automatically after every nine bits (8 bits of data plus ACK or NACK) has been received on the bus." reset_value="0x00" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="Data" description="This register holds contents of the 8 MSBs of the DAT shift register." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x030+0" size="4" name="MASK0" access="Read/Write" description="I2C Slave address mask register. This mask register is associated with I2ADR0 to determine an address match. The mask register has no effect when comparing to the General Call address (0000000)." reset_value="0x00" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." /> + <BitField start="1" size="7" name="MASK" description="Mask bits." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from reserved bits is undefined." /> + </Register> + <Register start="+0x030+4" size="4" name="MASK1" access="Read/Write" description="I2C Slave address mask register. This mask register is associated with I2ADR0 to determine an address match. The mask register has no effect when comparing to the General Call address (0000000)." reset_value="0x00" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." /> + <BitField start="1" size="7" name="MASK" description="Mask bits." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from reserved bits is undefined." /> + </Register> + <Register start="+0x030+8" size="4" name="MASK2" access="Read/Write" description="I2C Slave address mask register. This mask register is associated with I2ADR0 to determine an address match. The mask register has no effect when comparing to the General Call address (0000000)." reset_value="0x00" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." /> + <BitField start="1" size="7" name="MASK" description="Mask bits." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from reserved bits is undefined." /> + </Register> + <Register start="+0x030+12" size="4" name="MASK3" access="Read/Write" description="I2C Slave address mask register. This mask register is associated with I2ADR0 to determine an address match. The mask register has no effect when comparing to the General Call address (0000000)." reset_value="0x00" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." /> + <BitField start="1" size="7" name="MASK" description="Mask bits." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from reserved bits is undefined." /> + </Register> + </RegisterGroup> + <RegisterGroup name="RTC" start="0x40024000" description="Real-Time Clock (RTC)"> + <Register start="+0x000" size="4" name="CTRL" access="Read/Write" description="RTC control register" reset_value="0xF" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="SWRESET" description="Software reset control"> + <Enum name="NOT_IN_RESET" start="0" description="Not in reset. The RTC is not held in reset. This bit must be cleared prior to configuring or initiating any operation of the RTC." /> + <Enum name="IN_RESET" start="1" description="In reset. The RTC is held in reset. All register bits within the RTC will be forced to their reset value except the OFD bit. This bit must be cleared before writing to any register in the RTC - including writes to set any of the other bits within this register. Do not attempt to write to any bits of this register at the same time that the reset bit is being cleared. This bit may also serve as a Power Fail Detect flag for the always-on voltage domain." /> + </BitField> + <BitField start="1" size="1" name="OFD" description="Oscillator fail detect status."> + <Enum name="RUN" start="0" description="Run. The RTC oscillator is running properly. Writing a 0 has no effect." /> + <Enum name="FAIL" start="1" description="Fail. RTC oscillator fail detected. Clear this flag after the following power-up. Writing a 1 clears this bit." /> + </BitField> + <BitField start="2" size="1" name="ALARM1HZ" description="RTC 1 Hz timer alarm flag status."> + <Enum name="NO_MATCH" start="0" description="No match. No match has occurred on the 1 Hz RTC timer. Writing a 0 has no effect." /> + <Enum name="MATCH" start="1" description="Match. A match condition has occurred on the 1 Hz RTC timer. This flag generates an RTC alarm interrupt request RTC_ALARM which can also wake up the part from any low power mode. Writing a 1 clears this bit." /> + </BitField> + <BitField start="3" size="1" name="WAKE1KHZ" description="RTC 1 kHz timer wake-up flag status."> + <Enum name="RUN" start="0" description="Run. The RTC 1 kHz timer is running. Writing a 0 has no effect." /> + <Enum name="TIME_OUT" start="1" description="Time-out. The 1 kHz high-resolution/wake-up timer has timed out. This flag generates an RTC wake-up interrupt request RTC-WAKE which can also wake up the part from any low power mode. Writing a 1 clears this bit." /> + </BitField> + <BitField start="4" size="1" name="ALARMDPD_EN" description="RTC 1 Hz timer alarm enable for Deep power-down."> + <Enum name="DISABLE" start="0" description="Disable. A match on the 1 Hz RTC timer will not bring the part out of Deep power-down mode." /> + <Enum name="ENABLE" start="1" description="Enable. A match on the 1 Hz RTC timer bring the part out of Deep power-down mode." /> + </BitField> + <BitField start="5" size="1" name="WAKEDPD_EN" description="RTC 1 kHz timer wake-up enable for Deep power-down."> + <Enum name="DISABLE" start="0" description="Disable. A match on the 1 kHz RTC timer will not bring the part out of Deep power-down mode." /> + <Enum name="ENABLE" start="1" description="Enable. A match on the 1 kHz RTC timer bring the part out of Deep power-down mode." /> + </BitField> + <BitField start="6" size="1" name="RTC1KHZ_EN" description="RTC 1 kHz clock enable. This bit can be set to 0 to conserve power if the 1 kHz timer is not used. This bit has no effect when the RTC is disabled (bit 7 of this register is 0)."> + <Enum name="DISABLE" start="0" description="Disable. A match on the 1 kHz RTC timer will not bring the part out of Deep power-down mode." /> + <Enum name="ENABLE" start="1" description="Enable. The 1 kHz RTC timer is enabled." /> + </BitField> + <BitField start="7" size="1" name="RTC_EN" description="RTC enable."> + <Enum name="DISABLE" start="0" description="Disable. The RTC 1 Hz and 1 kHz clocks are shut down and the RTC operation is disabled. This bit should be 0 when writing to load a value in the RTC counter register." /> + <Enum name="ENABLE" start="1" description="Enable. The 1 Hz RTC clock is running and RTC operation is enabled. You must set this bit to initiate operation of the RTC. The first clock to the RTC counter occurs 1 s after this bit is set. To also enable the high-resolution, 1 kHz clock, set bit 6 in this register." /> + </BitField> + <BitField start="8" size="24" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x004" size="4" name="MATCH" access="Read/Write" description="RTC match register" reset_value="0xFFFF" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="MATVAL" description="Contains the match value against which the 1 Hz RTC timer will be compared to generate set the alarm flag RTC_ALARM and generate an alarm interrupt/wake-up if enabled." /> + </Register> + <Register start="+0x008" size="4" name="COUNT" access="Read/Write" description="RTC counter register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="VAL" description="A read reflects the current value of the main, 1 Hz RTC timer. A write loads a new initial value into the timer. The RTC counter will count up continuously at a 1 Hz rate once the RTC Software Reset is removed (by clearing bit 0 of the CTRL register). Only write to this register when the RTC1HZ_EN bit in the RTC CTRL Register is 0. The counter increments one second after the RTC1HZ_EN bit is set." /> + </Register> + <Register start="+0x00C" size="4" name="WAKE" access="Read/Write" description="RTC high-resolution/wake-up timer control register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="16" name="VAL" description="A read reflects the current value of the high-resolution/wake-up timer. A write pre-loads a start count value into the wake-up timer and initializes a count-down sequence. Do not write to this register while counting is in progress." /> + <BitField start="16" size="16" name="RESERVED" description="Reserved." /> + </Register> + </RegisterGroup> + <RegisterGroup name="DMATRIGMUX" start="0x40028000" description="DMA controller"> + <Register start="+0x000+0" size="4" name="DMA_ITRIG_PINMUX[0]" access="Read/Write" description="Trigger input select register for DMA channel 0." reset_value="0x1F" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="INP_N" description="Trigger input number (decimal value) to DMA channel n. All other values are reserved. 0	 = ADC0_SEQA_IRQ 1 = 	ADC0_SEQB_IRQ 2	 = CT16B0_MAT0 3 = 	CT16B1_MAT0 4	 = CT32B0_MAT0 5	 = CT16B1_MAT0 6	 = PINT0 ( pin interrupt 0) 7 = 	PINT1 (pin interrupt1 ) 8 = 	SCT0_DMA0 9 = 	SCT0_DMA1 10	 = SCT1_DMA0 11	 = SCT1_DMA1" /> + <BitField start="5" size="27" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x000+4" size="4" name="DMA_ITRIG_PINMUX[1]" access="Read/Write" description="Trigger input select register for DMA channel 0." reset_value="0x1F" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="INP_N" description="Trigger input number (decimal value) to DMA channel n. All other values are reserved. 0	 = ADC0_SEQA_IRQ 1 = 	ADC0_SEQB_IRQ 2	 = CT16B0_MAT0 3 = 	CT16B1_MAT0 4	 = CT32B0_MAT0 5	 = CT16B1_MAT0 6	 = PINT0 ( pin interrupt 0) 7 = 	PINT1 (pin interrupt1 ) 8 = 	SCT0_DMA0 9 = 	SCT0_DMA1 10	 = SCT1_DMA0 11	 = SCT1_DMA1" /> + <BitField start="5" size="27" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x000+8" size="4" name="DMA_ITRIG_PINMUX[2]" access="Read/Write" description="Trigger input select register for DMA channel 0." reset_value="0x1F" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="INP_N" description="Trigger input number (decimal value) to DMA channel n. All other values are reserved. 0	 = ADC0_SEQA_IRQ 1 = 	ADC0_SEQB_IRQ 2	 = CT16B0_MAT0 3 = 	CT16B1_MAT0 4	 = CT32B0_MAT0 5	 = CT16B1_MAT0 6	 = PINT0 ( pin interrupt 0) 7 = 	PINT1 (pin interrupt1 ) 8 = 	SCT0_DMA0 9 = 	SCT0_DMA1 10	 = SCT1_DMA0 11	 = SCT1_DMA1" /> + <BitField start="5" size="27" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x000+12" size="4" name="DMA_ITRIG_PINMUX[3]" access="Read/Write" description="Trigger input select register for DMA channel 0." reset_value="0x1F" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="INP_N" description="Trigger input number (decimal value) to DMA channel n. All other values are reserved. 0	 = ADC0_SEQA_IRQ 1 = 	ADC0_SEQB_IRQ 2	 = CT16B0_MAT0 3 = 	CT16B1_MAT0 4	 = CT32B0_MAT0 5	 = CT16B1_MAT0 6	 = PINT0 ( pin interrupt 0) 7 = 	PINT1 (pin interrupt1 ) 8 = 	SCT0_DMA0 9 = 	SCT0_DMA1 10	 = SCT1_DMA0 11	 = SCT1_DMA1" /> + <BitField start="5" size="27" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x000+16" size="4" name="DMA_ITRIG_PINMUX[4]" access="Read/Write" description="Trigger input select register for DMA channel 0." reset_value="0x1F" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="INP_N" description="Trigger input number (decimal value) to DMA channel n. All other values are reserved. 0	 = ADC0_SEQA_IRQ 1 = 	ADC0_SEQB_IRQ 2	 = CT16B0_MAT0 3 = 	CT16B1_MAT0 4	 = CT32B0_MAT0 5	 = CT16B1_MAT0 6	 = PINT0 ( pin interrupt 0) 7 = 	PINT1 (pin interrupt1 ) 8 = 	SCT0_DMA0 9 = 	SCT0_DMA1 10	 = SCT1_DMA0 11	 = SCT1_DMA1" /> + <BitField start="5" size="27" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x000+20" size="4" name="DMA_ITRIG_PINMUX[5]" access="Read/Write" description="Trigger input select register for DMA channel 0." reset_value="0x1F" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="INP_N" description="Trigger input number (decimal value) to DMA channel n. All other values are reserved. 0	 = ADC0_SEQA_IRQ 1 = 	ADC0_SEQB_IRQ 2	 = CT16B0_MAT0 3 = 	CT16B1_MAT0 4	 = CT32B0_MAT0 5	 = CT16B1_MAT0 6	 = PINT0 ( pin interrupt 0) 7 = 	PINT1 (pin interrupt1 ) 8 = 	SCT0_DMA0 9 = 	SCT0_DMA1 10	 = SCT1_DMA0 11	 = SCT1_DMA1" /> + <BitField start="5" size="27" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x000+24" size="4" name="DMA_ITRIG_PINMUX[6]" access="Read/Write" description="Trigger input select register for DMA channel 0." reset_value="0x1F" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="INP_N" description="Trigger input number (decimal value) to DMA channel n. All other values are reserved. 0	 = ADC0_SEQA_IRQ 1 = 	ADC0_SEQB_IRQ 2	 = CT16B0_MAT0 3 = 	CT16B1_MAT0 4	 = CT32B0_MAT0 5	 = CT16B1_MAT0 6	 = PINT0 ( pin interrupt 0) 7 = 	PINT1 (pin interrupt1 ) 8 = 	SCT0_DMA0 9 = 	SCT0_DMA1 10	 = SCT1_DMA0 11	 = SCT1_DMA1" /> + <BitField start="5" size="27" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x000+28" size="4" name="DMA_ITRIG_PINMUX[7]" access="Read/Write" description="Trigger input select register for DMA channel 0." reset_value="0x1F" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="INP_N" description="Trigger input number (decimal value) to DMA channel n. All other values are reserved. 0	 = ADC0_SEQA_IRQ 1 = 	ADC0_SEQB_IRQ 2	 = CT16B0_MAT0 3 = 	CT16B1_MAT0 4	 = CT32B0_MAT0 5	 = CT16B1_MAT0 6	 = PINT0 ( pin interrupt 0) 7 = 	PINT1 (pin interrupt1 ) 8 = 	SCT0_DMA0 9 = 	SCT0_DMA1 10	 = SCT1_DMA0 11	 = SCT1_DMA1" /> + <BitField start="5" size="27" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x000+32" size="4" name="DMA_ITRIG_PINMUX[8]" access="Read/Write" description="Trigger input select register for DMA channel 0." reset_value="0x1F" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="INP_N" description="Trigger input number (decimal value) to DMA channel n. All other values are reserved. 0	 = ADC0_SEQA_IRQ 1 = 	ADC0_SEQB_IRQ 2	 = CT16B0_MAT0 3 = 	CT16B1_MAT0 4	 = CT32B0_MAT0 5	 = CT16B1_MAT0 6	 = PINT0 ( pin interrupt 0) 7 = 	PINT1 (pin interrupt1 ) 8 = 	SCT0_DMA0 9 = 	SCT0_DMA1 10	 = SCT1_DMA0 11	 = SCT1_DMA1" /> + <BitField start="5" size="27" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x000+36" size="4" name="DMA_ITRIG_PINMUX[9]" access="Read/Write" description="Trigger input select register for DMA channel 0." reset_value="0x1F" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="INP_N" description="Trigger input number (decimal value) to DMA channel n. All other values are reserved. 0	 = ADC0_SEQA_IRQ 1 = 	ADC0_SEQB_IRQ 2	 = CT16B0_MAT0 3 = 	CT16B1_MAT0 4	 = CT32B0_MAT0 5	 = CT16B1_MAT0 6	 = PINT0 ( pin interrupt 0) 7 = 	PINT1 (pin interrupt1 ) 8 = 	SCT0_DMA0 9 = 	SCT0_DMA1 10	 = SCT1_DMA0 11	 = SCT1_DMA1" /> + <BitField start="5" size="27" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x000+40" size="4" name="DMA_ITRIG_PINMUX[10]" access="Read/Write" description="Trigger input select register for DMA channel 0." reset_value="0x1F" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="INP_N" description="Trigger input number (decimal value) to DMA channel n. All other values are reserved. 0	 = ADC0_SEQA_IRQ 1 = 	ADC0_SEQB_IRQ 2	 = CT16B0_MAT0 3 = 	CT16B1_MAT0 4	 = CT32B0_MAT0 5	 = CT16B1_MAT0 6	 = PINT0 ( pin interrupt 0) 7 = 	PINT1 (pin interrupt1 ) 8 = 	SCT0_DMA0 9 = 	SCT0_DMA1 10	 = SCT1_DMA0 11	 = SCT1_DMA1" /> + <BitField start="5" size="27" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x000+44" size="4" name="DMA_ITRIG_PINMUX[11]" access="Read/Write" description="Trigger input select register for DMA channel 0." reset_value="0x1F" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="INP_N" description="Trigger input number (decimal value) to DMA channel n. All other values are reserved. 0	 = ADC0_SEQA_IRQ 1 = 	ADC0_SEQB_IRQ 2	 = CT16B0_MAT0 3 = 	CT16B1_MAT0 4	 = CT32B0_MAT0 5	 = CT16B1_MAT0 6	 = PINT0 ( pin interrupt 0) 7 = 	PINT1 (pin interrupt1 ) 8 = 	SCT0_DMA0 9 = 	SCT0_DMA1 10	 = SCT1_DMA0 11	 = SCT1_DMA1" /> + <BitField start="5" size="27" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x000+48" size="4" name="DMA_ITRIG_PINMUX[12]" access="Read/Write" description="Trigger input select register for DMA channel 0." reset_value="0x1F" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="INP_N" description="Trigger input number (decimal value) to DMA channel n. All other values are reserved. 0	 = ADC0_SEQA_IRQ 1 = 	ADC0_SEQB_IRQ 2	 = CT16B0_MAT0 3 = 	CT16B1_MAT0 4	 = CT32B0_MAT0 5	 = CT16B1_MAT0 6	 = PINT0 ( pin interrupt 0) 7 = 	PINT1 (pin interrupt1 ) 8 = 	SCT0_DMA0 9 = 	SCT0_DMA1 10	 = SCT1_DMA0 11	 = SCT1_DMA1" /> + <BitField start="5" size="27" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x000+52" size="4" name="DMA_ITRIG_PINMUX[13]" access="Read/Write" description="Trigger input select register for DMA channel 0." reset_value="0x1F" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="INP_N" description="Trigger input number (decimal value) to DMA channel n. All other values are reserved. 0	 = ADC0_SEQA_IRQ 1 = 	ADC0_SEQB_IRQ 2	 = CT16B0_MAT0 3 = 	CT16B1_MAT0 4	 = CT32B0_MAT0 5	 = CT16B1_MAT0 6	 = PINT0 ( pin interrupt 0) 7 = 	PINT1 (pin interrupt1 ) 8 = 	SCT0_DMA0 9 = 	SCT0_DMA1 10	 = SCT1_DMA0 11	 = SCT1_DMA1" /> + <BitField start="5" size="27" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x000+56" size="4" name="DMA_ITRIG_PINMUX[14]" access="Read/Write" description="Trigger input select register for DMA channel 0." reset_value="0x1F" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="INP_N" description="Trigger input number (decimal value) to DMA channel n. All other values are reserved. 0	 = ADC0_SEQA_IRQ 1 = 	ADC0_SEQB_IRQ 2	 = CT16B0_MAT0 3 = 	CT16B1_MAT0 4	 = CT32B0_MAT0 5	 = CT16B1_MAT0 6	 = PINT0 ( pin interrupt 0) 7 = 	PINT1 (pin interrupt1 ) 8 = 	SCT0_DMA0 9 = 	SCT0_DMA1 10	 = SCT1_DMA0 11	 = SCT1_DMA1" /> + <BitField start="5" size="27" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x000+60" size="4" name="DMA_ITRIG_PINMUX[15]" access="Read/Write" description="Trigger input select register for DMA channel 0." reset_value="0x1F" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="INP_N" description="Trigger input number (decimal value) to DMA channel n. All other values are reserved. 0	 = ADC0_SEQA_IRQ 1 = 	ADC0_SEQB_IRQ 2	 = CT16B0_MAT0 3 = 	CT16B1_MAT0 4	 = CT32B0_MAT0 5	 = CT16B1_MAT0 6	 = PINT0 ( pin interrupt 0) 7 = 	PINT1 (pin interrupt1 ) 8 = 	SCT0_DMA0 9 = 	SCT0_DMA1 10	 = SCT1_DMA0 11	 = SCT1_DMA1" /> + <BitField start="5" size="27" name="RESERVED" description="Reserved." /> + </Register> + </RegisterGroup> + <RegisterGroup name="PMU" start="0x40038000" description="Power Management Unit (PMU)"> + <Register start="+0x000" size="4" name="PCON" access="Read/Write" description="Power control register" reset_value="0x0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="PM" description="Power mode"> + <Enum name="DEFAULT" start="0x0" description="Default. The part is in active or sleep mode." /> + <Enum name="DEEP_SLEEP" start="0x1" description="Deep-sleep. ARM WFI will enter Deep-sleep mode." /> + <Enum name="POWER_DOWN" start="0x2" description="Power-down. ARM WFI will enter Power-down mode." /> + <Enum name="DEEP_POWER_DOWN" start="0x3" description="Deep power-down. ARM WFI will enter Deep-power down mode (ARM Cortex-M0+ core powered-down)." /> + </BitField> + <BitField start="3" size="1" name="NODPD" description="A 1 in this bit prevents entry to Deep power-down mode when 0x3 is written to the PM field above, the SLEEPDEEP bit is set, and a WFI is executed. This bit is cleared only by power-on reset, so writing a one to this bit locks the part in a mode in which Deep power-down mode is blocked." /> + <BitField start="4" size="4" name="RESERVED" description="Reserved. Do not write ones to this bit." /> + <BitField start="8" size="1" name="SLEEPFLAG" description="Sleep mode flag"> + <Enum name="ACTIVE_MODE" start="0" description="Active mode. Read: No power-down mode entered. Part is in Active mode. Write: No effect." /> + <Enum name="LOW_POWER_MODE" start="1" description="Low power mode. Read: Sleep/Deep-sleep or Deep power-down mode entered. Write: Writing a 1 clears the SLEEPFLAG bit to 0." /> + </BitField> + <BitField start="9" size="2" name="RESERVED" description="Reserved. Do not write ones to this bit." /> + <BitField start="11" size="1" name="DPDFLAG" description="Deep power-down flag"> + <Enum name="NOT_DEEP_POWER_DOWN" start="0" description="Not Deep power-down. Read: Deep power-down mode not entered. Write: No effect." /> + <Enum name="DEEP_POWER_DOWN" start="1" description="Deep power-down. Read: Deep power-down mode entered. Write: Clear the Deep power-down flag." /> + </BitField> + <BitField start="12" size="20" name="RESERVED" description="Reserved. Do not write ones to this bit." /> + </Register> + <Register start="+0x004+0" size="4" name="GPREG0" access="Read/Write" description="General purpose register 0" reset_value="0x0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="GPDATA" description="Data retained during Deep power-down mode." /> + </Register> + <Register start="+0x004+4" size="4" name="GPREG1" access="Read/Write" description="General purpose register 0" reset_value="0x0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="GPDATA" description="Data retained during Deep power-down mode." /> + </Register> + <Register start="+0x004+8" size="4" name="GPREG2" access="Read/Write" description="General purpose register 0" reset_value="0x0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="GPDATA" description="Data retained during Deep power-down mode." /> + </Register> + <Register start="+0x004+12" size="4" name="GPREG3" access="Read/Write" description="General purpose register 0" reset_value="0x0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="GPDATA" description="Data retained during Deep power-down mode." /> + </Register> + <Register start="+0x014" size="4" name="GPREG4" access="Read/Write" description="Deep power down control register" reset_value="0x0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="10" name="RESERVED" description="Reserved. Do not write ones to this bit." /> + <BitField start="10" size="1" name="WAKEUPHYS" description="WAKEUP pin hysteresis enable"> + <Enum name="DISABLE_HYSTERESIS_F" start="0" description="Disable Hysteresis for WAKUP pin disabled." /> + <Enum name="ENABLE" start="1" description="Enable. Hysteresis for WAKEUP pin enabled." /> + </BitField> + <BitField start="11" size="1" name="WAKEPAD_DISABLE" description="WAKEUP pin disable. Setting this bit disables the wake-up pin, so it can be used for other purposes. Never set this bit if you intend to use a pin to wake up the part from Deep power-down mode. You can only disable the wake-up pin if the RTC wake-up timer is enabled and configured. Setting this bit is not necessary if Deep power-down mode is not used."> + <Enum name="ENABLE" start="0" description="Enable. The wake-up function is enabled on pin PIO0_16." /> + <Enum name="DISABLE" start="1" description="Disable. Setting this bit disables the wake-up function on pin PIO0_16." /> + </BitField> + <BitField start="12" size="20" name="GPDATA" description="Data retained during Deep power-down mode." /> + </Register> + </RegisterGroup> + <RegisterGroup name="FLASHCTRL" start="0x4003C000" description=" Flash controller "> + <Register start="+0x010" size="4" name="FLASHCFG" access="Read/Write" description="Flash configuration register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="2" name="FLASHTIM" description="Flash memory access time. FLASHTIM +1 is equal to the number of system clocks used for flash access."> + <Enum name="1_SYSTEM_CLOCK_FLASH" start="0x0" description="1 system clock flash access time (for system clock frequencies of up to 20 MHz)." /> + <Enum name="2_SYSTEM_CLOCKS_FLAS" start="0x1" description="2 system clocks flash access time (for system clock frequencies of up to 30 MHz)." /> + <Enum name="RESERVED_" start="0x2" description="Reserved." /> + <Enum name="RESERVED_" start="0x3" description="Reserved." /> + </BitField> + <BitField start="2" size="30" name="RESERVED" description="Reserved. User software must not change the value of these bits. Bits 31:2 must be written back exactly as read." /> + </Register> + <Register start="+0x020" size="4" name="FMSSTART" access="Read/Write" description="Signature start address register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="17" name="START" description="Signature generation start address (corresponds to AHB byte address bits[20:4])." /> + <BitField start="17" size="15" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x024" size="4" name="FMSSTOP" access="Read/Write" description="Signature stop-address register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="17" name="STOPA" description="Stop address for signature generation (the word specified by STOPA is included in the address range). The address is in units of memory words, not bytes. If the option bistprotection=1, bits 2:0 cannot be written and are forced to 111." /> + <BitField start="17" size="1" name="STRTBIST" description="When this bit is written to 1, signature generation starts. At the end of signature generation, this bit is automatically cleared." /> + <BitField start="18" size="14" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x02C" size="4" name="FMSW0" access="ReadOnly" description="Signature Word " reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="SIG" description="32-bit signature." /> + </Register> + </RegisterGroup> + <RegisterGroup name="SSP0" start="0x40040000" description="SSP/SPI "> + <Register start="+0x000" size="4" name="CR0" access="Read/Write" description="Control Register 0. Selects the serial clock rate, bus type, and data size." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="4" name="DSS" description="Data Size Select. This field controls the number of bits transferred in each frame. Values 0000-0010 are not supported and should not be used."> + <Enum name="4_BIT_TRANSFER" start="0x3" description="4-bit transfer" /> + <Enum name="5_BIT_TRANSFER" start="0x4" description="5-bit transfer" /> + <Enum name="6_BIT_TRANSFER" start="0x5" description="6-bit transfer" /> + <Enum name="7_BIT_TRANSFER" start="0x6" description="7-bit transfer" /> + <Enum name="8_BIT_TRANSFER" start="0x7" description="8-bit transfer" /> + <Enum name="9_BIT_TRANSFER" start="0x8" description="9-bit transfer" /> + <Enum name="10_BIT_TRANSFER" start="0x9" description="10-bit transfer" /> + <Enum name="11_BIT_TRANSFER" start="0xA" description="11-bit transfer" /> + <Enum name="12_BIT_TRANSFER" start="0xB" description="12-bit transfer" /> + <Enum name="13_BIT_TRANSFER" start="0xC" description="13-bit transfer" /> + <Enum name="14_BIT_TRANSFER" start="0xD" description="14-bit transfer" /> + <Enum name="15_BIT_TRANSFER" start="0xE" description="15-bit transfer" /> + <Enum name="16_BIT_TRANSFER" start="0xF" description="16-bit transfer" /> + </BitField> + <BitField start="4" size="2" name="FRF" description="Frame Format."> + <Enum name="SPI" start="0x0" description="SPI" /> + <Enum name="TI" start="0x1" description="TI" /> + <Enum name="MICROWIRE" start="0x2" description="Microwire" /> + <Enum name="RESERVED" start="0x3" description="This combination is not supported and should not be used." /> + </BitField> + <BitField start="6" size="1" name="CPOL" description="Clock Out Polarity. This bit is only used in SPI mode."> + <Enum name="LOW" start="0" description="SPI controller maintains the bus clock low between frames." /> + <Enum name="HIGH" start="1" description="SPI controller maintains the bus clock high between frames." /> + </BitField> + <BitField start="7" size="1" name="CPHA" description="Clock Out Phase. This bit is only used in SPI mode."> + <Enum name="FIRSTCLOCK" start="0" description="SPI controller captures serial data on the first clock transition of the frame, that is, the transition away from the inter-frame state of the clock line." /> + <Enum name="SECONDCLOCK" start="1" description="SPI controller captures serial data on the second clock transition of the frame, that is, the transition back to the inter-frame state of the clock line." /> + </BitField> + <BitField start="8" size="8" name="SCR" description="Serial Clock Rate. The number of prescaler output clocks per bit on the bus, minus one. Given that CPSDVSR is the prescale divider, and the APB clock PCLK clocks the prescaler, the bit frequency is PCLK / (CPSDVSR X [SCR+1])." /> + <BitField start="16" size="16" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x004" size="4" name="CR1" access="Read/Write" description="Control Register 1. Selects master/slave and other modes." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="LBM" description="Loop Back Mode."> + <Enum name="DURING_NORMAL_OPERAT" start="0" description="During normal operation." /> + <Enum name="SERIAL_INPUT_IS_TAKE" start="1" description="Serial input is taken from the serial output (MOSI or MISO) rather than the serial input pin (MISO or MOSI respectively)." /> + </BitField> + <BitField start="1" size="1" name="SSE" description="SPI Enable."> + <Enum name="DISABLED" start="0" description="The SPI controller is disabled." /> + <Enum name="ENABLED" start="1" description="The SPI controller will interact with other devices on the serial bus. Software should write the appropriate control information to the other SSP/SPI registers and interrupt controller registers, before setting this bit." /> + </BitField> + <BitField start="2" size="1" name="MS" description="Master/Slave Mode.This bit can only be written when the SSE bit is 0."> + <Enum name="MASTER" start="0" description="The SPI controller acts as a master on the bus, driving the SCLK, MOSI, and SSEL lines and receiving the MISO line." /> + <Enum name="SLAVE" start="1" description="The SPI controller acts as a slave on the bus, driving MISO line and receiving SCLK, MOSI, and SSEL lines." /> + </BitField> + <BitField start="3" size="1" name="SOD" description="Slave Output Disable. This bit is relevant only in slave mode (MS = 1). If it is 1, this blocks this SPI controller from driving the transmit data line (MISO)." /> + <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x008" size="4" name="DR" access="None" description="Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="16" name="DATA" description="Write: software can write data to be sent in a future frame to this register whenever the TNF bit in the Status register is 1, indicating that the Tx FIFO is not full. If the Tx FIFO was previously empty and the SPI controller is not busy on the bus, transmission of the data will begin immediately. Otherwise the data written to this register will be sent as soon as all previous data has been sent (and received). If the data length is less than 16 bit, software must right-justify the data written to this register. Read: software can read data from this register whenever the RNE bit in the Status register is 1, indicating that the Rx FIFO is not empty. When software reads this register, the SPI controller returns data from the least recent frame in the Rx FIFO. If the data length is less than 16 bit, the data is right-justified in this field with higher order bits filled with 0s." /> + <BitField start="16" size="16" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x00C" size="4" name="SR" access="ReadOnly" description="Status Register" reset_value="0x00000003" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="TFE" description="Transmit FIFO Empty. This bit is 1 is the Transmit FIFO is empty, 0 if not." /> + <BitField start="1" size="1" name="TNF" description="Transmit FIFO Not Full. This bit is 0 if the Tx FIFO is full, 1 if not." /> + <BitField start="2" size="1" name="RNE" description="Receive FIFO Not Empty. This bit is 0 if the Receive FIFO is empty, 1 if not." /> + <BitField start="3" size="1" name="RFF" description="Receive FIFO Full. This bit is 1 if the Receive FIFO is full, 0 if not." /> + <BitField start="4" size="1" name="BSY" description="Busy. This bit is 0 if the SPI controller is idle, 1 if it is currently sending/receiving a frame and/or the Tx FIFO is not empty." /> + <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x010" size="4" name="CPSR" access="Read/Write" description="Clock Prescale Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="CPSDVSR" description="This even value between 2 and 254, by which SPI_PCLK is divided to yield the prescaler output clock. Bit 0 always reads as 0." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x014" size="4" name="IMSC" access="Read/Write" description="Interrupt Mask Set and Clear Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RORIM" description="Software should set this bit to enable interrupt when a Receive Overrun occurs, that is, when the Rx FIFO is full and another frame is completely received. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs." /> + <BitField start="1" size="1" name="RTIM" description="Software should set this bit to enable interrupt when a Receive Time-out condition occurs. A Receive Time-out occurs when the Rx FIFO is not empty, and no has not been read for a time-out period. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1])." /> + <BitField start="2" size="1" name="RXIM" description="Software should set this bit to enable interrupt when the Rx FIFO is at least half full." /> + <BitField start="3" size="1" name="TXIM" description="Software should set this bit to enable interrupt when the Tx FIFO is at least half empty." /> + <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x018" size="4" name="RIS" access="ReadOnly" description="Raw Interrupt Status Register" reset_value="0x00000008" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RORRIS" description="This bit is 1 if another frame was completely received while the RxFIFO was full. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs." /> + <BitField start="1" size="1" name="RTRIS" description="This bit is 1 if the Rx FIFO is not empty, and has not been read for a time-out period. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1])." /> + <BitField start="2" size="1" name="RXRIS" description="This bit is 1 if the Rx FIFO is at least half full." /> + <BitField start="3" size="1" name="TXRIS" description="This bit is 1 if the Tx FIFO is at least half empty." /> + <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x01C" size="4" name="MIS" access="ReadOnly" description="Masked Interrupt Status Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RORMIS" description="This bit is 1 if another frame was completely received while the RxFIFO was full, and this interrupt is enabled." /> + <BitField start="1" size="1" name="RTMIS" description="This bit is 1 if the Rx FIFO is not empty, has not been read for a time-out period, and this interrupt is enabled. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1])." /> + <BitField start="2" size="1" name="RXMIS" description="This bit is 1 if the Rx FIFO is at least half full, and this interrupt is enabled." /> + <BitField start="3" size="1" name="TXMIS" description="This bit is 1 if the Tx FIFO is at least half empty, and this interrupt is enabled." /> + <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x020" size="4" name="ICR" access="WriteOnly" description="SSPICR Interrupt Clear Register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="RORIC" description="Writing a 1 to this bit clears the frame was received when RxFIFO was full interrupt." /> + <BitField start="1" size="1" name="RTIC" description="Writing a 1 to this bit clears the Rx FIFO was not empty and has not been read for a timeout period interrupt. The timeout period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1])." /> + <BitField start="2" size="30" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + </RegisterGroup> + <RegisterGroup name="IOCON" start="0x40044000" description="I/O control (IOCON) "> + <Register start="+0x000+0" size="4" name="PIO0_0" access="Read/Write" description="I/O configuration for port PIO0" reset_value="0x00000090" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function." /> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE" start="0" description="Disable." /> + <Enum name="ENABLE" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." /> + </BitField> + <BitField start="7" size="3" name="RESERVED" description="Reserved." /> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE" start="0" description="Disable." /> + <Enum name="ENABLE" start="1" description="Enable. Open-drain mode enabled. This is not a true open-drain mode." /> + </BitField> + <BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode."> + <Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." /> + <Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." /> + <Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." /> + <Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." /> + </BitField> + <BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved."> + <Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." /> + <Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." /> + <Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." /> + <Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." /> + <Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." /> + <Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." /> + <Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." /> + </BitField> + <BitField start="16" size="16" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x000+4" size="4" name="PIO0_1" access="Read/Write" description="I/O configuration for port PIO0" reset_value="0x00000090" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function." /> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE" start="0" description="Disable." /> + <Enum name="ENABLE" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." /> + </BitField> + <BitField start="7" size="3" name="RESERVED" description="Reserved." /> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE" start="0" description="Disable." /> + <Enum name="ENABLE" start="1" description="Enable. Open-drain mode enabled. This is not a true open-drain mode." /> + </BitField> + <BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode."> + <Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." /> + <Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." /> + <Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." /> + <Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." /> + </BitField> + <BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved."> + <Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." /> + <Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." /> + <Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." /> + <Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." /> + <Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." /> + <Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." /> + <Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." /> + </BitField> + <BitField start="16" size="16" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x000+8" size="4" name="PIO0_2" access="Read/Write" description="I/O configuration for port PIO0" reset_value="0x00000090" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function." /> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE" start="0" description="Disable." /> + <Enum name="ENABLE" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." /> + </BitField> + <BitField start="7" size="3" name="RESERVED" description="Reserved." /> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE" start="0" description="Disable." /> + <Enum name="ENABLE" start="1" description="Enable. Open-drain mode enabled. This is not a true open-drain mode." /> + </BitField> + <BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode."> + <Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." /> + <Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." /> + <Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." /> + <Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." /> + </BitField> + <BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved."> + <Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." /> + <Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." /> + <Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." /> + <Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." /> + <Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." /> + <Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." /> + <Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." /> + </BitField> + <BitField start="16" size="16" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x000+12" size="4" name="PIO0_3" access="Read/Write" description="I/O configuration for port PIO0" reset_value="0x00000090" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function." /> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE" start="0" description="Disable." /> + <Enum name="ENABLE" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." /> + </BitField> + <BitField start="7" size="3" name="RESERVED" description="Reserved." /> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE" start="0" description="Disable." /> + <Enum name="ENABLE" start="1" description="Enable. Open-drain mode enabled. This is not a true open-drain mode." /> + </BitField> + <BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode."> + <Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." /> + <Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." /> + <Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." /> + <Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." /> + </BitField> + <BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved."> + <Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." /> + <Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." /> + <Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." /> + <Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." /> + <Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." /> + <Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." /> + <Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." /> + </BitField> + <BitField start="16" size="16" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x010" size="4" name="PIO0_4" access="Read/Write" description="I/O configuration for open-drain pin PIO0_4" reset_value="0x00000080" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function. " /> + <BitField start="3" size="5" name="RESERVED" description="Reserved." /> + <BitField start="8" size="2" name="I2CMODE" description="Selects I2C mode (see Section 7.3.8). Select Standard mode (I2CMODE = 00, default) or Standard I/O functionality (I2CMODE = 01) if the pin function is GPIO (FUNC = 000)."> + <Enum name="STANDARD_MODE_FAST" start="0x0" description="Standard mode/ Fast-mode I2C." /> + <Enum name="STANDARD_IO_FUNCTIO" start="0x1" description="Standard I/O functionality" /> + <Enum name="FAST_MODE_PLUS_I2C" start="0x2" description="Fast-mode Plus I2C" /> + <Enum name="RESERVED" start="0x3" description="Reserved." /> + </BitField> + <BitField start="10" size="22" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x014" size="4" name="PIO0_5" access="Read/Write" description="I/O configuration for open-drain pin PIO0_5" reset_value="0x00000080" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function. " /> + <BitField start="3" size="5" name="RESERVED" description="Reserved." /> + <BitField start="8" size="2" name="I2CMODE" description="Selects I2C mode (see Section 7.3.8). Select Standard mode (I2CMODE = 00, default) or Standard I/O functionality (I2CMODE = 01) if the pin function is GPIO (FUNC = 000)."> + <Enum name="STANDARD_MODE_FAST" start="0x0" description="Standard mode/ Fast-mode I2C." /> + <Enum name="STANDARD_IO_FUNCTIO" start="0x1" description="Standard I/O functionality" /> + <Enum name="FAST_MODE_PLUS_I2C" start="0x2" description="Fast-mode Plus I2C" /> + <Enum name="RESERVED" start="0x3" description="Reserved." /> + </BitField> + <BitField start="10" size="22" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x018+0" size="4" name="PIO0_6" access="Read/Write" description="I/O configuration for port PIO0" reset_value="0x00000090" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function." /> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE" start="0" description="Disable." /> + <Enum name="ENABLE" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." /> + </BitField> + <BitField start="7" size="3" name="RESERVED" description="Reserved." /> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE" start="0" description="Disable." /> + <Enum name="ENABLE" start="1" description="Enable. Open-drain mode enabled. This is not a true open-drain mode." /> + </BitField> + <BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode."> + <Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." /> + <Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." /> + <Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." /> + <Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." /> + </BitField> + <BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved."> + <Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." /> + <Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." /> + <Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." /> + <Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." /> + <Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." /> + <Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." /> + <Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." /> + </BitField> + <BitField start="16" size="16" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x018+4" size="4" name="PIO0_7" access="Read/Write" description="I/O configuration for port PIO0" reset_value="0x00000090" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function." /> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE" start="0" description="Disable." /> + <Enum name="ENABLE" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." /> + </BitField> + <BitField start="7" size="3" name="RESERVED" description="Reserved." /> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE" start="0" description="Disable." /> + <Enum name="ENABLE" start="1" description="Enable. Open-drain mode enabled. This is not a true open-drain mode." /> + </BitField> + <BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode."> + <Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." /> + <Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." /> + <Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." /> + <Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." /> + </BitField> + <BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved."> + <Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." /> + <Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." /> + <Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." /> + <Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." /> + <Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." /> + <Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." /> + <Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." /> + </BitField> + <BitField start="16" size="16" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x018+8" size="4" name="PIO0_8" access="Read/Write" description="I/O configuration for port PIO0" reset_value="0x00000090" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function." /> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE" start="0" description="Disable." /> + <Enum name="ENABLE" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." /> + </BitField> + <BitField start="7" size="3" name="RESERVED" description="Reserved." /> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE" start="0" description="Disable." /> + <Enum name="ENABLE" start="1" description="Enable. Open-drain mode enabled. This is not a true open-drain mode." /> + </BitField> + <BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode."> + <Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." /> + <Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." /> + <Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." /> + <Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." /> + </BitField> + <BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved."> + <Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." /> + <Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." /> + <Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." /> + <Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." /> + <Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." /> + <Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." /> + <Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." /> + </BitField> + <BitField start="16" size="16" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x018+12" size="4" name="PIO0_9" access="Read/Write" description="I/O configuration for port PIO0" reset_value="0x00000090" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function." /> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE" start="0" description="Disable." /> + <Enum name="ENABLE" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." /> + </BitField> + <BitField start="7" size="3" name="RESERVED" description="Reserved." /> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE" start="0" description="Disable." /> + <Enum name="ENABLE" start="1" description="Enable. Open-drain mode enabled. This is not a true open-drain mode." /> + </BitField> + <BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode."> + <Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." /> + <Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." /> + <Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." /> + <Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." /> + </BitField> + <BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved."> + <Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." /> + <Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." /> + <Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." /> + <Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." /> + <Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." /> + <Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." /> + <Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." /> + </BitField> + <BitField start="16" size="16" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x018+16" size="4" name="PIO0_10" access="Read/Write" description="I/O configuration for port PIO0" reset_value="0x00000090" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function." /> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE" start="0" description="Disable." /> + <Enum name="ENABLE" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." /> + </BitField> + <BitField start="7" size="3" name="RESERVED" description="Reserved." /> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE" start="0" description="Disable." /> + <Enum name="ENABLE" start="1" description="Enable. Open-drain mode enabled. This is not a true open-drain mode." /> + </BitField> + <BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode."> + <Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." /> + <Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." /> + <Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." /> + <Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." /> + </BitField> + <BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved."> + <Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." /> + <Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." /> + <Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." /> + <Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." /> + <Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." /> + <Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." /> + <Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." /> + </BitField> + <BitField start="16" size="16" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x018+20" size="4" name="PIO0_11" access="Read/Write" description="I/O configuration for port PIO0" reset_value="0x00000090" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function." /> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE" start="0" description="Disable." /> + <Enum name="ENABLE" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." /> + </BitField> + <BitField start="7" size="3" name="RESERVED" description="Reserved." /> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE" start="0" description="Disable." /> + <Enum name="ENABLE" start="1" description="Enable. Open-drain mode enabled. This is not a true open-drain mode." /> + </BitField> + <BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode."> + <Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." /> + <Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." /> + <Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." /> + <Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." /> + </BitField> + <BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved."> + <Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." /> + <Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." /> + <Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." /> + <Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." /> + <Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." /> + <Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." /> + <Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." /> + </BitField> + <BitField start="16" size="16" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x018+24" size="4" name="PIO0_12" access="Read/Write" description="I/O configuration for port PIO0" reset_value="0x00000090" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function." /> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE" start="0" description="Disable." /> + <Enum name="ENABLE" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." /> + </BitField> + <BitField start="7" size="3" name="RESERVED" description="Reserved." /> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE" start="0" description="Disable." /> + <Enum name="ENABLE" start="1" description="Enable. Open-drain mode enabled. This is not a true open-drain mode." /> + </BitField> + <BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode."> + <Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." /> + <Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." /> + <Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." /> + <Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." /> + </BitField> + <BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved."> + <Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." /> + <Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." /> + <Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." /> + <Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." /> + <Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." /> + <Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." /> + <Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." /> + </BitField> + <BitField start="16" size="16" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x018+28" size="4" name="PIO0_13" access="Read/Write" description="I/O configuration for port PIO0" reset_value="0x00000090" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function." /> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE" start="0" description="Disable." /> + <Enum name="ENABLE" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." /> + </BitField> + <BitField start="7" size="3" name="RESERVED" description="Reserved." /> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE" start="0" description="Disable." /> + <Enum name="ENABLE" start="1" description="Enable. Open-drain mode enabled. This is not a true open-drain mode." /> + </BitField> + <BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode."> + <Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." /> + <Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." /> + <Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." /> + <Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." /> + </BitField> + <BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved."> + <Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." /> + <Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." /> + <Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." /> + <Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." /> + <Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." /> + <Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." /> + <Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." /> + </BitField> + <BitField start="16" size="16" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x018+32" size="4" name="PIO0_14" access="Read/Write" description="I/O configuration for port PIO0" reset_value="0x00000090" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function." /> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE" start="0" description="Disable." /> + <Enum name="ENABLE" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." /> + </BitField> + <BitField start="7" size="3" name="RESERVED" description="Reserved." /> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE" start="0" description="Disable." /> + <Enum name="ENABLE" start="1" description="Enable. Open-drain mode enabled. This is not a true open-drain mode." /> + </BitField> + <BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode."> + <Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." /> + <Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." /> + <Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." /> + <Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." /> + </BitField> + <BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved."> + <Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." /> + <Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." /> + <Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." /> + <Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." /> + <Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." /> + <Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." /> + <Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." /> + </BitField> + <BitField start="16" size="16" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x018+36" size="4" name="PIO0_15" access="Read/Write" description="I/O configuration for port PIO0" reset_value="0x00000090" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function." /> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE" start="0" description="Disable." /> + <Enum name="ENABLE" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." /> + </BitField> + <BitField start="7" size="3" name="RESERVED" description="Reserved." /> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE" start="0" description="Disable." /> + <Enum name="ENABLE" start="1" description="Enable. Open-drain mode enabled. This is not a true open-drain mode." /> + </BitField> + <BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode."> + <Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." /> + <Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." /> + <Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." /> + <Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." /> + </BitField> + <BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved."> + <Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." /> + <Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." /> + <Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." /> + <Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." /> + <Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." /> + <Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." /> + <Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." /> + </BitField> + <BitField start="16" size="16" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x018+40" size="4" name="PIO0_16" access="Read/Write" description="I/O configuration for port PIO0" reset_value="0x00000090" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function." /> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE" start="0" description="Disable." /> + <Enum name="ENABLE" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." /> + </BitField> + <BitField start="7" size="3" name="RESERVED" description="Reserved." /> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE" start="0" description="Disable." /> + <Enum name="ENABLE" start="1" description="Enable. Open-drain mode enabled. This is not a true open-drain mode." /> + </BitField> + <BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode."> + <Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." /> + <Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." /> + <Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." /> + <Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." /> + </BitField> + <BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved."> + <Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." /> + <Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." /> + <Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." /> + <Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." /> + <Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." /> + <Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." /> + <Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." /> + </BitField> + <BitField start="16" size="16" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x018+44" size="4" name="PIO0_17" access="Read/Write" description="I/O configuration for port PIO0" reset_value="0x00000090" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function." /> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE" start="0" description="Disable." /> + <Enum name="ENABLE" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." /> + </BitField> + <BitField start="7" size="3" name="RESERVED" description="Reserved." /> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE" start="0" description="Disable." /> + <Enum name="ENABLE" start="1" description="Enable. Open-drain mode enabled. This is not a true open-drain mode." /> + </BitField> + <BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode."> + <Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." /> + <Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." /> + <Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." /> + <Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." /> + </BitField> + <BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved."> + <Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." /> + <Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." /> + <Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." /> + <Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." /> + <Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." /> + <Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." /> + <Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." /> + </BitField> + <BitField start="16" size="16" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x018+48" size="4" name="PIO0_18" access="Read/Write" description="I/O configuration for port PIO0" reset_value="0x00000090" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function." /> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE" start="0" description="Disable." /> + <Enum name="ENABLE" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." /> + </BitField> + <BitField start="7" size="3" name="RESERVED" description="Reserved." /> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE" start="0" description="Disable." /> + <Enum name="ENABLE" start="1" description="Enable. Open-drain mode enabled. This is not a true open-drain mode." /> + </BitField> + <BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode."> + <Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." /> + <Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." /> + <Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." /> + <Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." /> + </BitField> + <BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved."> + <Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." /> + <Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." /> + <Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." /> + <Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." /> + <Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." /> + <Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." /> + <Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." /> + </BitField> + <BitField start="16" size="16" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x018+52" size="4" name="PIO0_19" access="Read/Write" description="I/O configuration for port PIO0" reset_value="0x00000090" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function." /> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE" start="0" description="Disable." /> + <Enum name="ENABLE" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." /> + </BitField> + <BitField start="7" size="3" name="RESERVED" description="Reserved." /> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE" start="0" description="Disable." /> + <Enum name="ENABLE" start="1" description="Enable. Open-drain mode enabled. This is not a true open-drain mode." /> + </BitField> + <BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode."> + <Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." /> + <Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." /> + <Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." /> + <Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." /> + </BitField> + <BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved."> + <Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." /> + <Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." /> + <Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." /> + <Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." /> + <Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." /> + <Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." /> + <Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." /> + </BitField> + <BitField start="16" size="16" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x018+56" size="4" name="PIO0_20" access="Read/Write" description="I/O configuration for port PIO0" reset_value="0x00000090" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function." /> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE" start="0" description="Disable." /> + <Enum name="ENABLE" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." /> + </BitField> + <BitField start="7" size="3" name="RESERVED" description="Reserved." /> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE" start="0" description="Disable." /> + <Enum name="ENABLE" start="1" description="Enable. Open-drain mode enabled. This is not a true open-drain mode." /> + </BitField> + <BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode."> + <Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." /> + <Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." /> + <Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." /> + <Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." /> + </BitField> + <BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved."> + <Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." /> + <Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." /> + <Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." /> + <Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." /> + <Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." /> + <Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." /> + <Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." /> + </BitField> + <BitField start="16" size="16" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x018+60" size="4" name="PIO0_21" access="Read/Write" description="I/O configuration for port PIO0" reset_value="0x00000090" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function." /> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE" start="0" description="Disable." /> + <Enum name="ENABLE" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." /> + </BitField> + <BitField start="7" size="3" name="RESERVED" description="Reserved." /> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE" start="0" description="Disable." /> + <Enum name="ENABLE" start="1" description="Enable. Open-drain mode enabled. This is not a true open-drain mode." /> + </BitField> + <BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode."> + <Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." /> + <Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." /> + <Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." /> + <Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." /> + </BitField> + <BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved."> + <Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." /> + <Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." /> + <Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." /> + <Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." /> + <Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." /> + <Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." /> + <Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." /> + </BitField> + <BitField start="16" size="16" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x018+64" size="4" name="PIO0_22" access="Read/Write" description="I/O configuration for port PIO0" reset_value="0x00000090" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function." /> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE" start="0" description="Disable." /> + <Enum name="ENABLE" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." /> + </BitField> + <BitField start="7" size="3" name="RESERVED" description="Reserved." /> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE" start="0" description="Disable." /> + <Enum name="ENABLE" start="1" description="Enable. Open-drain mode enabled. This is not a true open-drain mode." /> + </BitField> + <BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode."> + <Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." /> + <Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." /> + <Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." /> + <Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." /> + </BitField> + <BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved."> + <Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." /> + <Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." /> + <Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." /> + <Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." /> + <Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." /> + <Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." /> + <Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." /> + </BitField> + <BitField start="16" size="16" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x018+68" size="4" name="PIO0_23" access="Read/Write" description="I/O configuration for port PIO0" reset_value="0x00000090" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function." /> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE" start="0" description="Disable." /> + <Enum name="ENABLE" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." /> + </BitField> + <BitField start="7" size="3" name="RESERVED" description="Reserved." /> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE" start="0" description="Disable." /> + <Enum name="ENABLE" start="1" description="Enable. Open-drain mode enabled. This is not a true open-drain mode." /> + </BitField> + <BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode."> + <Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." /> + <Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." /> + <Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." /> + <Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." /> + </BitField> + <BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved."> + <Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." /> + <Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." /> + <Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." /> + <Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." /> + <Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." /> + <Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." /> + <Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." /> + </BitField> + <BitField start="16" size="16" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x060+0" size="4" name="PIO1_0" access="Read/Write" description="I/O configuration for port PIO1" reset_value="0x00000090" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function." /> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE" start="0" description="Disable." /> + <Enum name="ENABLE" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." /> + </BitField> + <BitField start="7" size="3" name="RESERVED" description="Reserved." /> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE" start="0" description="Disable." /> + <Enum name="ENABLED" start="1" description="Enabled. Open-drain mode enabled. This is not a true open-drain mode." /> + </BitField> + <BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode."> + <Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." /> + <Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." /> + <Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." /> + <Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." /> + </BitField> + <BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved."> + <Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." /> + <Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." /> + <Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." /> + <Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." /> + <Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." /> + <Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." /> + <Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." /> + </BitField> + <BitField start="16" size="16" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x060+4" size="4" name="PIO1_1" access="Read/Write" description="I/O configuration for port PIO1" reset_value="0x00000090" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function." /> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE" start="0" description="Disable." /> + <Enum name="ENABLE" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." /> + </BitField> + <BitField start="7" size="3" name="RESERVED" description="Reserved." /> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE" start="0" description="Disable." /> + <Enum name="ENABLED" start="1" description="Enabled. Open-drain mode enabled. This is not a true open-drain mode." /> + </BitField> + <BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode."> + <Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." /> + <Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." /> + <Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." /> + <Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." /> + </BitField> + <BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved."> + <Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." /> + <Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." /> + <Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." /> + <Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." /> + <Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." /> + <Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." /> + <Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." /> + </BitField> + <BitField start="16" size="16" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x060+8" size="4" name="PIO1_2" access="Read/Write" description="I/O configuration for port PIO1" reset_value="0x00000090" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function." /> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE" start="0" description="Disable." /> + <Enum name="ENABLE" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." /> + </BitField> + <BitField start="7" size="3" name="RESERVED" description="Reserved." /> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE" start="0" description="Disable." /> + <Enum name="ENABLED" start="1" description="Enabled. Open-drain mode enabled. This is not a true open-drain mode." /> + </BitField> + <BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode."> + <Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." /> + <Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." /> + <Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." /> + <Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." /> + </BitField> + <BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved."> + <Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." /> + <Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." /> + <Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." /> + <Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." /> + <Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." /> + <Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." /> + <Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." /> + </BitField> + <BitField start="16" size="16" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x060+12" size="4" name="PIO1_3" access="Read/Write" description="I/O configuration for port PIO1" reset_value="0x00000090" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function." /> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE" start="0" description="Disable." /> + <Enum name="ENABLE" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." /> + </BitField> + <BitField start="7" size="3" name="RESERVED" description="Reserved." /> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE" start="0" description="Disable." /> + <Enum name="ENABLED" start="1" description="Enabled. Open-drain mode enabled. This is not a true open-drain mode." /> + </BitField> + <BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode."> + <Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." /> + <Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." /> + <Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." /> + <Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." /> + </BitField> + <BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved."> + <Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." /> + <Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." /> + <Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." /> + <Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." /> + <Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." /> + <Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." /> + <Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." /> + </BitField> + <BitField start="16" size="16" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x060+16" size="4" name="PIO1_4" access="Read/Write" description="I/O configuration for port PIO1" reset_value="0x00000090" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function." /> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE" start="0" description="Disable." /> + <Enum name="ENABLE" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." /> + </BitField> + <BitField start="7" size="3" name="RESERVED" description="Reserved." /> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE" start="0" description="Disable." /> + <Enum name="ENABLED" start="1" description="Enabled. Open-drain mode enabled. This is not a true open-drain mode." /> + </BitField> + <BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode."> + <Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." /> + <Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." /> + <Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." /> + <Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." /> + </BitField> + <BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved."> + <Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." /> + <Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." /> + <Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." /> + <Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." /> + <Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." /> + <Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." /> + <Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." /> + </BitField> + <BitField start="16" size="16" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x060+20" size="4" name="PIO1_5" access="Read/Write" description="I/O configuration for port PIO1" reset_value="0x00000090" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function." /> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE" start="0" description="Disable." /> + <Enum name="ENABLE" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." /> + </BitField> + <BitField start="7" size="3" name="RESERVED" description="Reserved." /> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE" start="0" description="Disable." /> + <Enum name="ENABLED" start="1" description="Enabled. Open-drain mode enabled. This is not a true open-drain mode." /> + </BitField> + <BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode."> + <Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." /> + <Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." /> + <Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." /> + <Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." /> + </BitField> + <BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved."> + <Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." /> + <Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." /> + <Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." /> + <Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." /> + <Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." /> + <Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." /> + <Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." /> + </BitField> + <BitField start="16" size="16" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x060+24" size="4" name="PIO1_6" access="Read/Write" description="I/O configuration for port PIO1" reset_value="0x00000090" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function." /> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE" start="0" description="Disable." /> + <Enum name="ENABLE" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." /> + </BitField> + <BitField start="7" size="3" name="RESERVED" description="Reserved." /> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE" start="0" description="Disable." /> + <Enum name="ENABLED" start="1" description="Enabled. Open-drain mode enabled. This is not a true open-drain mode." /> + </BitField> + <BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode."> + <Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." /> + <Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." /> + <Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." /> + <Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." /> + </BitField> + <BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved."> + <Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." /> + <Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." /> + <Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." /> + <Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." /> + <Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." /> + <Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." /> + <Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." /> + </BitField> + <BitField start="16" size="16" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x060+28" size="4" name="PIO1_7" access="Read/Write" description="I/O configuration for port PIO1" reset_value="0x00000090" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function." /> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE" start="0" description="Disable." /> + <Enum name="ENABLE" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." /> + </BitField> + <BitField start="7" size="3" name="RESERVED" description="Reserved." /> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE" start="0" description="Disable." /> + <Enum name="ENABLED" start="1" description="Enabled. Open-drain mode enabled. This is not a true open-drain mode." /> + </BitField> + <BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode."> + <Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." /> + <Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." /> + <Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." /> + <Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." /> + </BitField> + <BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved."> + <Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." /> + <Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." /> + <Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." /> + <Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." /> + <Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." /> + <Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." /> + <Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." /> + </BitField> + <BitField start="16" size="16" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x060+32" size="4" name="PIO1_8" access="Read/Write" description="I/O configuration for port PIO1" reset_value="0x00000090" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function." /> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE" start="0" description="Disable." /> + <Enum name="ENABLE" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." /> + </BitField> + <BitField start="7" size="3" name="RESERVED" description="Reserved." /> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE" start="0" description="Disable." /> + <Enum name="ENABLED" start="1" description="Enabled. Open-drain mode enabled. This is not a true open-drain mode." /> + </BitField> + <BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode."> + <Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." /> + <Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." /> + <Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." /> + <Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." /> + </BitField> + <BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved."> + <Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." /> + <Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." /> + <Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." /> + <Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." /> + <Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." /> + <Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." /> + <Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." /> + </BitField> + <BitField start="16" size="16" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x060+36" size="4" name="PIO1_9" access="Read/Write" description="I/O configuration for port PIO1" reset_value="0x00000090" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function." /> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE" start="0" description="Disable." /> + <Enum name="ENABLE" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." /> + </BitField> + <BitField start="7" size="3" name="RESERVED" description="Reserved." /> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE" start="0" description="Disable." /> + <Enum name="ENABLED" start="1" description="Enabled. Open-drain mode enabled. This is not a true open-drain mode." /> + </BitField> + <BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode."> + <Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." /> + <Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." /> + <Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." /> + <Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." /> + </BitField> + <BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved."> + <Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." /> + <Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." /> + <Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." /> + <Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." /> + <Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." /> + <Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." /> + <Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." /> + </BitField> + <BitField start="16" size="16" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x060+40" size="4" name="PIO1_10" access="Read/Write" description="I/O configuration for port PIO1" reset_value="0x00000090" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function." /> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE" start="0" description="Disable." /> + <Enum name="ENABLE" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." /> + </BitField> + <BitField start="7" size="3" name="RESERVED" description="Reserved." /> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE" start="0" description="Disable." /> + <Enum name="ENABLED" start="1" description="Enabled. Open-drain mode enabled. This is not a true open-drain mode." /> + </BitField> + <BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode."> + <Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." /> + <Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." /> + <Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." /> + <Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." /> + </BitField> + <BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved."> + <Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." /> + <Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." /> + <Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." /> + <Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." /> + <Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." /> + <Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." /> + <Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." /> + </BitField> + <BitField start="16" size="16" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x060+44" size="4" name="PIO1_11" access="Read/Write" description="I/O configuration for port PIO1" reset_value="0x00000090" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function." /> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE" start="0" description="Disable." /> + <Enum name="ENABLE" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." /> + </BitField> + <BitField start="7" size="3" name="RESERVED" description="Reserved." /> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE" start="0" description="Disable." /> + <Enum name="ENABLED" start="1" description="Enabled. Open-drain mode enabled. This is not a true open-drain mode." /> + </BitField> + <BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode."> + <Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." /> + <Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." /> + <Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." /> + <Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." /> + </BitField> + <BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved."> + <Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." /> + <Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." /> + <Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." /> + <Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." /> + <Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." /> + <Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." /> + <Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." /> + </BitField> + <BitField start="16" size="16" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x060+48" size="4" name="PIO1_12" access="Read/Write" description="I/O configuration for port PIO1" reset_value="0x00000090" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function." /> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE" start="0" description="Disable." /> + <Enum name="ENABLE" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." /> + </BitField> + <BitField start="7" size="3" name="RESERVED" description="Reserved." /> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE" start="0" description="Disable." /> + <Enum name="ENABLED" start="1" description="Enabled. Open-drain mode enabled. This is not a true open-drain mode." /> + </BitField> + <BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode."> + <Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." /> + <Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." /> + <Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." /> + <Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." /> + </BitField> + <BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved."> + <Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." /> + <Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." /> + <Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." /> + <Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." /> + <Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." /> + <Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." /> + <Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." /> + </BitField> + <BitField start="16" size="16" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x060+52" size="4" name="PIO1_13" access="Read/Write" description="I/O configuration for port PIO1" reset_value="0x00000090" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function." /> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE" start="0" description="Disable." /> + <Enum name="ENABLE" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." /> + </BitField> + <BitField start="7" size="3" name="RESERVED" description="Reserved." /> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE" start="0" description="Disable." /> + <Enum name="ENABLED" start="1" description="Enabled. Open-drain mode enabled. This is not a true open-drain mode." /> + </BitField> + <BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode."> + <Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." /> + <Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." /> + <Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." /> + <Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." /> + </BitField> + <BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved."> + <Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." /> + <Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." /> + <Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." /> + <Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." /> + <Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." /> + <Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." /> + <Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." /> + </BitField> + <BitField start="16" size="16" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x060+56" size="4" name="PIO1_14" access="Read/Write" description="I/O configuration for port PIO1" reset_value="0x00000090" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function." /> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE" start="0" description="Disable." /> + <Enum name="ENABLE" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." /> + </BitField> + <BitField start="7" size="3" name="RESERVED" description="Reserved." /> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE" start="0" description="Disable." /> + <Enum name="ENABLED" start="1" description="Enabled. Open-drain mode enabled. This is not a true open-drain mode." /> + </BitField> + <BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode."> + <Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." /> + <Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." /> + <Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." /> + <Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." /> + </BitField> + <BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved."> + <Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." /> + <Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." /> + <Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." /> + <Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." /> + <Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." /> + <Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." /> + <Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." /> + </BitField> + <BitField start="16" size="16" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x060+60" size="4" name="PIO1_15" access="Read/Write" description="I/O configuration for port PIO1" reset_value="0x00000090" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function." /> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE" start="0" description="Disable." /> + <Enum name="ENABLE" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." /> + </BitField> + <BitField start="7" size="3" name="RESERVED" description="Reserved." /> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE" start="0" description="Disable." /> + <Enum name="ENABLED" start="1" description="Enabled. Open-drain mode enabled. This is not a true open-drain mode." /> + </BitField> + <BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode."> + <Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." /> + <Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." /> + <Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." /> + <Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." /> + </BitField> + <BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved."> + <Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." /> + <Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." /> + <Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." /> + <Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." /> + <Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." /> + <Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." /> + <Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." /> + </BitField> + <BitField start="16" size="16" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x060+64" size="4" name="PIO1_16" access="Read/Write" description="I/O configuration for port PIO1" reset_value="0x00000090" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function." /> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE" start="0" description="Disable." /> + <Enum name="ENABLE" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." /> + </BitField> + <BitField start="7" size="3" name="RESERVED" description="Reserved." /> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE" start="0" description="Disable." /> + <Enum name="ENABLED" start="1" description="Enabled. Open-drain mode enabled. This is not a true open-drain mode." /> + </BitField> + <BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode."> + <Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." /> + <Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." /> + <Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." /> + <Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." /> + </BitField> + <BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved."> + <Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." /> + <Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." /> + <Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." /> + <Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." /> + <Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." /> + <Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." /> + <Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." /> + </BitField> + <BitField start="16" size="16" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x060+68" size="4" name="PIO1_17" access="Read/Write" description="I/O configuration for port PIO1" reset_value="0x00000090" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function." /> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE" start="0" description="Disable." /> + <Enum name="ENABLE" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." /> + </BitField> + <BitField start="7" size="3" name="RESERVED" description="Reserved." /> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE" start="0" description="Disable." /> + <Enum name="ENABLED" start="1" description="Enabled. Open-drain mode enabled. This is not a true open-drain mode." /> + </BitField> + <BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode."> + <Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." /> + <Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." /> + <Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." /> + <Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." /> + </BitField> + <BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved."> + <Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." /> + <Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." /> + <Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." /> + <Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." /> + <Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." /> + <Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." /> + <Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." /> + </BitField> + <BitField start="16" size="16" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x060+72" size="4" name="PIO1_18" access="Read/Write" description="I/O configuration for port PIO1" reset_value="0x00000090" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function." /> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE" start="0" description="Disable." /> + <Enum name="ENABLE" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." /> + </BitField> + <BitField start="7" size="3" name="RESERVED" description="Reserved." /> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE" start="0" description="Disable." /> + <Enum name="ENABLED" start="1" description="Enabled. Open-drain mode enabled. This is not a true open-drain mode." /> + </BitField> + <BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode."> + <Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." /> + <Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." /> + <Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." /> + <Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." /> + </BitField> + <BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved."> + <Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." /> + <Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." /> + <Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." /> + <Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." /> + <Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." /> + <Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." /> + <Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." /> + </BitField> + <BitField start="16" size="16" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x060+76" size="4" name="PIO1_19" access="Read/Write" description="I/O configuration for port PIO1" reset_value="0x00000090" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function." /> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE" start="0" description="Disable." /> + <Enum name="ENABLE" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." /> + </BitField> + <BitField start="7" size="3" name="RESERVED" description="Reserved." /> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE" start="0" description="Disable." /> + <Enum name="ENABLED" start="1" description="Enabled. Open-drain mode enabled. This is not a true open-drain mode." /> + </BitField> + <BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode."> + <Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." /> + <Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." /> + <Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." /> + <Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." /> + </BitField> + <BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved."> + <Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." /> + <Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." /> + <Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." /> + <Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." /> + <Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." /> + <Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." /> + <Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." /> + </BitField> + <BitField start="16" size="16" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x060+80" size="4" name="PIO1_20" access="Read/Write" description="I/O configuration for port PIO1" reset_value="0x00000090" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function." /> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE" start="0" description="Disable." /> + <Enum name="ENABLE" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." /> + </BitField> + <BitField start="7" size="3" name="RESERVED" description="Reserved." /> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE" start="0" description="Disable." /> + <Enum name="ENABLED" start="1" description="Enabled. Open-drain mode enabled. This is not a true open-drain mode." /> + </BitField> + <BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode."> + <Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." /> + <Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." /> + <Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." /> + <Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." /> + </BitField> + <BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved."> + <Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." /> + <Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." /> + <Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." /> + <Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." /> + <Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." /> + <Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." /> + <Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." /> + </BitField> + <BitField start="16" size="16" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x060+84" size="4" name="PIO1_21" access="Read/Write" description="I/O configuration for port PIO1" reset_value="0x00000090" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function." /> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE" start="0" description="Disable." /> + <Enum name="ENABLE" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." /> + </BitField> + <BitField start="7" size="3" name="RESERVED" description="Reserved." /> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE" start="0" description="Disable." /> + <Enum name="ENABLED" start="1" description="Enabled. Open-drain mode enabled. This is not a true open-drain mode." /> + </BitField> + <BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode."> + <Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." /> + <Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." /> + <Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." /> + <Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." /> + </BitField> + <BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved."> + <Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." /> + <Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." /> + <Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." /> + <Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." /> + <Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." /> + <Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." /> + <Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." /> + </BitField> + <BitField start="16" size="16" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x060+88" size="4" name="PIO1_22" access="Read/Write" description="I/O configuration for port PIO1" reset_value="0x00000090" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function." /> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE" start="0" description="Disable." /> + <Enum name="ENABLE" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." /> + </BitField> + <BitField start="7" size="3" name="RESERVED" description="Reserved." /> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE" start="0" description="Disable." /> + <Enum name="ENABLED" start="1" description="Enabled. Open-drain mode enabled. This is not a true open-drain mode." /> + </BitField> + <BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode."> + <Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." /> + <Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." /> + <Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." /> + <Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." /> + </BitField> + <BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved."> + <Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." /> + <Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." /> + <Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." /> + <Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." /> + <Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." /> + <Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." /> + <Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." /> + </BitField> + <BitField start="16" size="16" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x060+92" size="4" name="PIO1_23" access="Read/Write" description="I/O configuration for port PIO1" reset_value="0x00000090" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function." /> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE" start="0" description="Disable." /> + <Enum name="ENABLE" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." /> + </BitField> + <BitField start="7" size="3" name="RESERVED" description="Reserved." /> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE" start="0" description="Disable." /> + <Enum name="ENABLED" start="1" description="Enabled. Open-drain mode enabled. This is not a true open-drain mode." /> + </BitField> + <BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode."> + <Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." /> + <Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." /> + <Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." /> + <Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." /> + </BitField> + <BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved."> + <Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." /> + <Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." /> + <Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." /> + <Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." /> + <Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." /> + <Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." /> + <Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." /> + </BitField> + <BitField start="16" size="16" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x060+96" size="4" name="PIO1_24" access="Read/Write" description="I/O configuration for port PIO1" reset_value="0x00000090" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function." /> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE" start="0" description="Disable." /> + <Enum name="ENABLE" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." /> + </BitField> + <BitField start="7" size="3" name="RESERVED" description="Reserved." /> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE" start="0" description="Disable." /> + <Enum name="ENABLED" start="1" description="Enabled. Open-drain mode enabled. This is not a true open-drain mode." /> + </BitField> + <BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode."> + <Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." /> + <Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." /> + <Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." /> + <Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." /> + </BitField> + <BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved."> + <Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." /> + <Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." /> + <Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." /> + <Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." /> + <Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." /> + <Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." /> + <Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." /> + </BitField> + <BitField start="16" size="16" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x060+100" size="4" name="PIO1_25" access="Read/Write" description="I/O configuration for port PIO1" reset_value="0x00000090" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function." /> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE" start="0" description="Disable." /> + <Enum name="ENABLE" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." /> + </BitField> + <BitField start="7" size="3" name="RESERVED" description="Reserved." /> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE" start="0" description="Disable." /> + <Enum name="ENABLED" start="1" description="Enabled. Open-drain mode enabled. This is not a true open-drain mode." /> + </BitField> + <BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode."> + <Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." /> + <Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." /> + <Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." /> + <Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." /> + </BitField> + <BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved."> + <Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." /> + <Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." /> + <Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." /> + <Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." /> + <Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." /> + <Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." /> + <Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." /> + </BitField> + <BitField start="16" size="16" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x060+104" size="4" name="PIO1_26" access="Read/Write" description="I/O configuration for port PIO1" reset_value="0x00000090" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function." /> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE" start="0" description="Disable." /> + <Enum name="ENABLE" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." /> + </BitField> + <BitField start="7" size="3" name="RESERVED" description="Reserved." /> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE" start="0" description="Disable." /> + <Enum name="ENABLED" start="1" description="Enabled. Open-drain mode enabled. This is not a true open-drain mode." /> + </BitField> + <BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode."> + <Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." /> + <Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." /> + <Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." /> + <Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." /> + </BitField> + <BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved."> + <Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." /> + <Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." /> + <Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." /> + <Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." /> + <Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." /> + <Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." /> + <Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." /> + </BitField> + <BitField start="16" size="16" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x060+108" size="4" name="PIO1_27" access="Read/Write" description="I/O configuration for port PIO1" reset_value="0x00000090" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function." /> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE" start="0" description="Disable." /> + <Enum name="ENABLE" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." /> + </BitField> + <BitField start="7" size="3" name="RESERVED" description="Reserved." /> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE" start="0" description="Disable." /> + <Enum name="ENABLED" start="1" description="Enabled. Open-drain mode enabled. This is not a true open-drain mode." /> + </BitField> + <BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode."> + <Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." /> + <Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." /> + <Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." /> + <Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." /> + </BitField> + <BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved."> + <Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." /> + <Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." /> + <Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." /> + <Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." /> + <Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." /> + <Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." /> + <Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." /> + </BitField> + <BitField start="16" size="16" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x060+112" size="4" name="PIO1_28" access="Read/Write" description="I/O configuration for port PIO1" reset_value="0x00000090" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function." /> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE" start="0" description="Disable." /> + <Enum name="ENABLE" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." /> + </BitField> + <BitField start="7" size="3" name="RESERVED" description="Reserved." /> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE" start="0" description="Disable." /> + <Enum name="ENABLED" start="1" description="Enabled. Open-drain mode enabled. This is not a true open-drain mode." /> + </BitField> + <BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode."> + <Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." /> + <Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." /> + <Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." /> + <Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." /> + </BitField> + <BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved."> + <Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." /> + <Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." /> + <Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." /> + <Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." /> + <Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." /> + <Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." /> + <Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." /> + </BitField> + <BitField start="16" size="16" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x060+116" size="4" name="PIO1_29" access="Read/Write" description="I/O configuration for port PIO1" reset_value="0x00000090" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function." /> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE" start="0" description="Disable." /> + <Enum name="ENABLE" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." /> + </BitField> + <BitField start="7" size="3" name="RESERVED" description="Reserved." /> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE" start="0" description="Disable." /> + <Enum name="ENABLED" start="1" description="Enabled. Open-drain mode enabled. This is not a true open-drain mode." /> + </BitField> + <BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode."> + <Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." /> + <Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." /> + <Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." /> + <Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." /> + </BitField> + <BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved."> + <Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." /> + <Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." /> + <Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." /> + <Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." /> + <Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." /> + <Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." /> + <Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." /> + </BitField> + <BitField start="16" size="16" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x060+120" size="4" name="PIO1_30" access="Read/Write" description="I/O configuration for port PIO1" reset_value="0x00000090" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function." /> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE" start="0" description="Disable." /> + <Enum name="ENABLE" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." /> + </BitField> + <BitField start="7" size="3" name="RESERVED" description="Reserved." /> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE" start="0" description="Disable." /> + <Enum name="ENABLED" start="1" description="Enabled. Open-drain mode enabled. This is not a true open-drain mode." /> + </BitField> + <BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode."> + <Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." /> + <Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." /> + <Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." /> + <Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." /> + </BitField> + <BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved."> + <Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." /> + <Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." /> + <Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." /> + <Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." /> + <Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." /> + <Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." /> + <Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." /> + </BitField> + <BitField start="16" size="16" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x060+124" size="4" name="PIO1_31" access="Read/Write" description="I/O configuration for port PIO1" reset_value="0x00000090" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function." /> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE" start="0" description="Disable." /> + <Enum name="ENABLE" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." /> + </BitField> + <BitField start="7" size="3" name="RESERVED" description="Reserved." /> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE" start="0" description="Disable." /> + <Enum name="ENABLED" start="1" description="Enabled. Open-drain mode enabled. This is not a true open-drain mode." /> + </BitField> + <BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode."> + <Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." /> + <Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." /> + <Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." /> + <Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." /> + </BitField> + <BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved."> + <Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." /> + <Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." /> + <Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." /> + <Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." /> + <Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." /> + <Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." /> + <Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." /> + </BitField> + <BitField start="16" size="16" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x0F0+0" size="4" name="PIO2_0" access="Read/Write" description="I/O configuration for port PIO2" reset_value="0x00000090" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function." /> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE" start="0" description="Disable." /> + <Enum name="ENABLE" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." /> + </BitField> + <BitField start="7" size="3" name="RESERVED" description="Reserved." /> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE" start="0" description="Disable." /> + <Enum name="ENABLED" start="1" description="Enabled. Open-drain mode enabled. This is not a true open-drain mode." /> + </BitField> + <BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode."> + <Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." /> + <Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." /> + <Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." /> + <Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." /> + </BitField> + <BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved."> + <Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." /> + <Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." /> + <Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." /> + <Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." /> + <Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." /> + <Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." /> + <Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." /> + </BitField> + <BitField start="16" size="16" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x0F0+4" size="4" name="PIO2_1" access="Read/Write" description="I/O configuration for port PIO2" reset_value="0x00000090" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function." /> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE" start="0" description="Disable." /> + <Enum name="ENABLE" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." /> + </BitField> + <BitField start="7" size="3" name="RESERVED" description="Reserved." /> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE" start="0" description="Disable." /> + <Enum name="ENABLED" start="1" description="Enabled. Open-drain mode enabled. This is not a true open-drain mode." /> + </BitField> + <BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode."> + <Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." /> + <Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." /> + <Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." /> + <Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." /> + </BitField> + <BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved."> + <Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." /> + <Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." /> + <Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." /> + <Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." /> + <Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." /> + <Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." /> + <Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." /> + </BitField> + <BitField start="16" size="16" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x0FC+0" size="4" name="PIO2_2" access="Read/Write" description="I/O configuration for port PIO2" reset_value="0x00000090" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function." /> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE" start="0" description="Disable." /> + <Enum name="ENABLE" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." /> + </BitField> + <BitField start="7" size="3" name="RESERVED" description="Reserved." /> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE" start="0" description="Disable." /> + <Enum name="ENABLED" start="1" description="Enabled. Open-drain mode enabled. This is not a true open-drain mode." /> + </BitField> + <BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode."> + <Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." /> + <Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." /> + <Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." /> + <Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." /> + </BitField> + <BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved."> + <Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." /> + <Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." /> + <Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." /> + <Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." /> + <Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." /> + <Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." /> + <Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." /> + </BitField> + <BitField start="16" size="16" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x0FC+4" size="4" name="PIO2_3" access="Read/Write" description="I/O configuration for port PIO2" reset_value="0x00000090" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function." /> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE" start="0" description="Disable." /> + <Enum name="ENABLE" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." /> + </BitField> + <BitField start="7" size="3" name="RESERVED" description="Reserved." /> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE" start="0" description="Disable." /> + <Enum name="ENABLED" start="1" description="Enabled. Open-drain mode enabled. This is not a true open-drain mode." /> + </BitField> + <BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode."> + <Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." /> + <Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." /> + <Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." /> + <Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." /> + </BitField> + <BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved."> + <Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." /> + <Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." /> + <Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." /> + <Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." /> + <Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." /> + <Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." /> + <Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." /> + </BitField> + <BitField start="16" size="16" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x0FC+8" size="4" name="PIO2_4" access="Read/Write" description="I/O configuration for port PIO2" reset_value="0x00000090" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function." /> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE" start="0" description="Disable." /> + <Enum name="ENABLE" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." /> + </BitField> + <BitField start="7" size="3" name="RESERVED" description="Reserved." /> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE" start="0" description="Disable." /> + <Enum name="ENABLED" start="1" description="Enabled. Open-drain mode enabled. This is not a true open-drain mode." /> + </BitField> + <BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode."> + <Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." /> + <Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." /> + <Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." /> + <Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." /> + </BitField> + <BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved."> + <Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." /> + <Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." /> + <Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." /> + <Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." /> + <Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." /> + <Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." /> + <Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." /> + </BitField> + <BitField start="16" size="16" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x0FC+12" size="4" name="PIO2_5" access="Read/Write" description="I/O configuration for port PIO2" reset_value="0x00000090" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function." /> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE" start="0" description="Disable." /> + <Enum name="ENABLE" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." /> + </BitField> + <BitField start="7" size="3" name="RESERVED" description="Reserved." /> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE" start="0" description="Disable." /> + <Enum name="ENABLED" start="1" description="Enabled. Open-drain mode enabled. This is not a true open-drain mode." /> + </BitField> + <BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode."> + <Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." /> + <Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." /> + <Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." /> + <Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." /> + </BitField> + <BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved."> + <Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." /> + <Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." /> + <Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." /> + <Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." /> + <Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." /> + <Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." /> + <Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." /> + </BitField> + <BitField start="16" size="16" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x0FC+16" size="4" name="PIO2_6" access="Read/Write" description="I/O configuration for port PIO2" reset_value="0x00000090" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function." /> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE" start="0" description="Disable." /> + <Enum name="ENABLE" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." /> + </BitField> + <BitField start="7" size="3" name="RESERVED" description="Reserved." /> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE" start="0" description="Disable." /> + <Enum name="ENABLED" start="1" description="Enabled. Open-drain mode enabled. This is not a true open-drain mode." /> + </BitField> + <BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode."> + <Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." /> + <Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." /> + <Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." /> + <Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." /> + </BitField> + <BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved."> + <Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." /> + <Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." /> + <Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." /> + <Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." /> + <Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." /> + <Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." /> + <Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." /> + </BitField> + <BitField start="16" size="16" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x0FC+20" size="4" name="PIO2_7" access="Read/Write" description="I/O configuration for port PIO2" reset_value="0x00000090" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function." /> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE" start="0" description="Disable." /> + <Enum name="ENABLE" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." /> + </BitField> + <BitField start="7" size="3" name="RESERVED" description="Reserved." /> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE" start="0" description="Disable." /> + <Enum name="ENABLED" start="1" description="Enabled. Open-drain mode enabled. This is not a true open-drain mode." /> + </BitField> + <BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode."> + <Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." /> + <Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." /> + <Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." /> + <Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." /> + </BitField> + <BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved."> + <Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." /> + <Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." /> + <Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." /> + <Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." /> + <Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." /> + <Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." /> + <Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." /> + </BitField> + <BitField start="16" size="16" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x0FC+24" size="4" name="PIO2_8" access="Read/Write" description="I/O configuration for port PIO2" reset_value="0x00000090" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function." /> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE" start="0" description="Disable." /> + <Enum name="ENABLE" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." /> + </BitField> + <BitField start="7" size="3" name="RESERVED" description="Reserved." /> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE" start="0" description="Disable." /> + <Enum name="ENABLED" start="1" description="Enabled. Open-drain mode enabled. This is not a true open-drain mode." /> + </BitField> + <BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode."> + <Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." /> + <Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." /> + <Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." /> + <Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." /> + </BitField> + <BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved."> + <Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." /> + <Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." /> + <Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." /> + <Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." /> + <Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." /> + <Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." /> + <Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." /> + </BitField> + <BitField start="16" size="16" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x0FC+28" size="4" name="PIO2_9" access="Read/Write" description="I/O configuration for port PIO2" reset_value="0x00000090" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function." /> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE" start="0" description="Disable." /> + <Enum name="ENABLE" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." /> + </BitField> + <BitField start="7" size="3" name="RESERVED" description="Reserved." /> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE" start="0" description="Disable." /> + <Enum name="ENABLED" start="1" description="Enabled. Open-drain mode enabled. This is not a true open-drain mode." /> + </BitField> + <BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode."> + <Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." /> + <Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." /> + <Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." /> + <Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." /> + </BitField> + <BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved."> + <Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." /> + <Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." /> + <Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." /> + <Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." /> + <Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." /> + <Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." /> + <Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." /> + </BitField> + <BitField start="16" size="16" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x0FC+32" size="4" name="PIO2_10" access="Read/Write" description="I/O configuration for port PIO2" reset_value="0x00000090" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function." /> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE" start="0" description="Disable." /> + <Enum name="ENABLE" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." /> + </BitField> + <BitField start="7" size="3" name="RESERVED" description="Reserved." /> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE" start="0" description="Disable." /> + <Enum name="ENABLED" start="1" description="Enabled. Open-drain mode enabled. This is not a true open-drain mode." /> + </BitField> + <BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode."> + <Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." /> + <Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." /> + <Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." /> + <Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." /> + </BitField> + <BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved."> + <Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." /> + <Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." /> + <Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." /> + <Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." /> + <Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." /> + <Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." /> + <Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." /> + </BitField> + <BitField start="16" size="16" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x0FC+36" size="4" name="PIO2_11" access="Read/Write" description="I/O configuration for port PIO2" reset_value="0x00000090" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function." /> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE" start="0" description="Disable." /> + <Enum name="ENABLE" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." /> + </BitField> + <BitField start="7" size="3" name="RESERVED" description="Reserved." /> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE" start="0" description="Disable." /> + <Enum name="ENABLED" start="1" description="Enabled. Open-drain mode enabled. This is not a true open-drain mode." /> + </BitField> + <BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode."> + <Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." /> + <Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." /> + <Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." /> + <Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." /> + </BitField> + <BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved."> + <Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." /> + <Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." /> + <Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." /> + <Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." /> + <Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." /> + <Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." /> + <Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." /> + </BitField> + <BitField start="16" size="16" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x0FC+40" size="4" name="PIO2_12" access="Read/Write" description="I/O configuration for port PIO2" reset_value="0x00000090" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function." /> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE" start="0" description="Disable." /> + <Enum name="ENABLE" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." /> + </BitField> + <BitField start="7" size="3" name="RESERVED" description="Reserved." /> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE" start="0" description="Disable." /> + <Enum name="ENABLED" start="1" description="Enabled. Open-drain mode enabled. This is not a true open-drain mode." /> + </BitField> + <BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode."> + <Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." /> + <Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." /> + <Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." /> + <Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." /> + </BitField> + <BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved."> + <Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." /> + <Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." /> + <Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." /> + <Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." /> + <Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." /> + <Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." /> + <Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." /> + </BitField> + <BitField start="16" size="16" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x0FC+44" size="4" name="PIO2_13" access="Read/Write" description="I/O configuration for port PIO2" reset_value="0x00000090" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function." /> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE" start="0" description="Disable." /> + <Enum name="ENABLE" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." /> + </BitField> + <BitField start="7" size="3" name="RESERVED" description="Reserved." /> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE" start="0" description="Disable." /> + <Enum name="ENABLED" start="1" description="Enabled. Open-drain mode enabled. This is not a true open-drain mode." /> + </BitField> + <BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode."> + <Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." /> + <Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." /> + <Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." /> + <Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." /> + </BitField> + <BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved."> + <Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." /> + <Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." /> + <Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." /> + <Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." /> + <Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." /> + <Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." /> + <Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." /> + </BitField> + <BitField start="16" size="16" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x0FC+48" size="4" name="PIO2_14" access="Read/Write" description="I/O configuration for port PIO2" reset_value="0x00000090" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function." /> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE" start="0" description="Disable." /> + <Enum name="ENABLE" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." /> + </BitField> + <BitField start="7" size="3" name="RESERVED" description="Reserved." /> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE" start="0" description="Disable." /> + <Enum name="ENABLED" start="1" description="Enabled. Open-drain mode enabled. This is not a true open-drain mode." /> + </BitField> + <BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode."> + <Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." /> + <Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." /> + <Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." /> + <Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." /> + </BitField> + <BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved."> + <Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." /> + <Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." /> + <Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." /> + <Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." /> + <Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." /> + <Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." /> + <Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." /> + </BitField> + <BitField start="16" size="16" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x0FC+52" size="4" name="PIO2_15" access="Read/Write" description="I/O configuration for port PIO2" reset_value="0x00000090" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function." /> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE" start="0" description="Disable." /> + <Enum name="ENABLE" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." /> + </BitField> + <BitField start="7" size="3" name="RESERVED" description="Reserved." /> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE" start="0" description="Disable." /> + <Enum name="ENABLED" start="1" description="Enabled. Open-drain mode enabled. This is not a true open-drain mode." /> + </BitField> + <BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode."> + <Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." /> + <Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." /> + <Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." /> + <Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." /> + </BitField> + <BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved."> + <Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." /> + <Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." /> + <Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." /> + <Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." /> + <Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." /> + <Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." /> + <Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." /> + </BitField> + <BitField start="16" size="16" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x0FC+56" size="4" name="PIO2_16" access="Read/Write" description="I/O configuration for port PIO2" reset_value="0x00000090" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function." /> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE" start="0" description="Disable." /> + <Enum name="ENABLE" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." /> + </BitField> + <BitField start="7" size="3" name="RESERVED" description="Reserved." /> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE" start="0" description="Disable." /> + <Enum name="ENABLED" start="1" description="Enabled. Open-drain mode enabled. This is not a true open-drain mode." /> + </BitField> + <BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode."> + <Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." /> + <Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." /> + <Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." /> + <Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." /> + </BitField> + <BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved."> + <Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." /> + <Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." /> + <Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." /> + <Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." /> + <Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." /> + <Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." /> + <Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." /> + </BitField> + <BitField start="16" size="16" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x0FC+60" size="4" name="PIO2_17" access="Read/Write" description="I/O configuration for port PIO2" reset_value="0x00000090" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function." /> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE" start="0" description="Disable." /> + <Enum name="ENABLE" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." /> + </BitField> + <BitField start="7" size="3" name="RESERVED" description="Reserved." /> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE" start="0" description="Disable." /> + <Enum name="ENABLED" start="1" description="Enabled. Open-drain mode enabled. This is not a true open-drain mode." /> + </BitField> + <BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode."> + <Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." /> + <Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." /> + <Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." /> + <Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." /> + </BitField> + <BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved."> + <Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." /> + <Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." /> + <Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." /> + <Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." /> + <Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." /> + <Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." /> + <Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." /> + </BitField> + <BitField start="16" size="16" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x0FC+64" size="4" name="PIO2_18" access="Read/Write" description="I/O configuration for port PIO2" reset_value="0x00000090" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function." /> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE" start="0" description="Disable." /> + <Enum name="ENABLE" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." /> + </BitField> + <BitField start="7" size="3" name="RESERVED" description="Reserved." /> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE" start="0" description="Disable." /> + <Enum name="ENABLED" start="1" description="Enabled. Open-drain mode enabled. This is not a true open-drain mode." /> + </BitField> + <BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode."> + <Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." /> + <Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." /> + <Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." /> + <Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." /> + </BitField> + <BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved."> + <Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." /> + <Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." /> + <Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." /> + <Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." /> + <Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." /> + <Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." /> + <Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." /> + </BitField> + <BitField start="16" size="16" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x0FC+68" size="4" name="PIO2_19" access="Read/Write" description="I/O configuration for port PIO2" reset_value="0x00000090" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function." /> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE" start="0" description="Disable." /> + <Enum name="ENABLE" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." /> + </BitField> + <BitField start="7" size="3" name="RESERVED" description="Reserved." /> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE" start="0" description="Disable." /> + <Enum name="ENABLED" start="1" description="Enabled. Open-drain mode enabled. This is not a true open-drain mode." /> + </BitField> + <BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode."> + <Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." /> + <Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." /> + <Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." /> + <Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." /> + </BitField> + <BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved."> + <Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." /> + <Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." /> + <Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." /> + <Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." /> + <Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." /> + <Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." /> + <Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." /> + </BitField> + <BitField start="16" size="16" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x0FC+72" size="4" name="PIO2_20" access="Read/Write" description="I/O configuration for port PIO2" reset_value="0x00000090" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function." /> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE" start="0" description="Disable." /> + <Enum name="ENABLE" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." /> + </BitField> + <BitField start="7" size="3" name="RESERVED" description="Reserved." /> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE" start="0" description="Disable." /> + <Enum name="ENABLED" start="1" description="Enabled. Open-drain mode enabled. This is not a true open-drain mode." /> + </BitField> + <BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode."> + <Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." /> + <Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." /> + <Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." /> + <Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." /> + </BitField> + <BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved."> + <Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." /> + <Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." /> + <Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." /> + <Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." /> + <Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." /> + <Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." /> + <Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." /> + </BitField> + <BitField start="16" size="16" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x0FC+76" size="4" name="PIO2_21" access="Read/Write" description="I/O configuration for port PIO2" reset_value="0x00000090" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function." /> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE" start="0" description="Disable." /> + <Enum name="ENABLE" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." /> + </BitField> + <BitField start="7" size="3" name="RESERVED" description="Reserved." /> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE" start="0" description="Disable." /> + <Enum name="ENABLED" start="1" description="Enabled. Open-drain mode enabled. This is not a true open-drain mode." /> + </BitField> + <BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode."> + <Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." /> + <Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." /> + <Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." /> + <Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." /> + </BitField> + <BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved."> + <Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." /> + <Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." /> + <Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." /> + <Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." /> + <Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." /> + <Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." /> + <Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." /> + </BitField> + <BitField start="16" size="16" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x0FC+80" size="4" name="PIO2_22" access="Read/Write" description="I/O configuration for port PIO2" reset_value="0x00000090" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function." /> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE" start="0" description="Disable." /> + <Enum name="ENABLE" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." /> + </BitField> + <BitField start="7" size="3" name="RESERVED" description="Reserved." /> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE" start="0" description="Disable." /> + <Enum name="ENABLED" start="1" description="Enabled. Open-drain mode enabled. This is not a true open-drain mode." /> + </BitField> + <BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode."> + <Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." /> + <Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." /> + <Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." /> + <Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." /> + </BitField> + <BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved."> + <Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." /> + <Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." /> + <Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." /> + <Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." /> + <Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." /> + <Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." /> + <Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." /> + </BitField> + <BitField start="16" size="16" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x0FC+84" size="4" name="PIO2_23" access="Read/Write" description="I/O configuration for port PIO2" reset_value="0x00000090" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function." /> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE" start="0" description="Disable." /> + <Enum name="ENABLE" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." /> + </BitField> + <BitField start="7" size="3" name="RESERVED" description="Reserved." /> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE" start="0" description="Disable." /> + <Enum name="ENABLED" start="1" description="Enabled. Open-drain mode enabled. This is not a true open-drain mode." /> + </BitField> + <BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode."> + <Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." /> + <Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." /> + <Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." /> + <Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." /> + </BitField> + <BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved."> + <Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." /> + <Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." /> + <Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." /> + <Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." /> + <Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." /> + <Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." /> + <Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." /> + </BitField> + <BitField start="16" size="16" name="RESERVED" description="Reserved." /> + </Register> + </RegisterGroup> + <RegisterGroup name="SYSCON" start="0x40048000" description="System configuration (SYSCON)"> + <Register start="+0x000" size="4" name="SYSMEMREMAP" access="Read/Write" description="System memory remap" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="MAP" description="System memory remap. Value 0x3 is reserved."> + <Enum name="BOOT_LOADER_MODE" start="0x0" description="Boot Loader Mode. Interrupt vectors are re-mapped to Boot ROM." /> + <Enum name="USER_RAM_MODE" start="0x1" description="User RAM Mode. Interrupt vectors are re-mapped to Static RAM." /> + <Enum name="USER_FLASH_MODE" start="0x2" description="User Flash Mode. Interrupt vectors are not re-mapped and reside in Flash." /> + </BitField> + <BitField start="2" size="30" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x004" size="4" name="PRESETCTRL" access="Read/Write" description="Peripheral reset control" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="SSP0_RST_N" description="SSP0 reset control"> + <Enum name="RESET" start="0" description="Reset. Resets the SSP0 peripheral." /> + <Enum name="CLEAR_RESET" start="1" description="Clear reset. SSP0 reset de-asserted." /> + </BitField> + <BitField start="1" size="1" name="I2C0_RST_N" description="I2C0 reset control"> + <Enum name="RESET" start="0" description="Reset. Resets the I2C0 peripheral." /> + <Enum name="CLEAR_RESET" start="1" description="Clear reset. I2C0 reset de-asserted." /> + </BitField> + <BitField start="2" size="1" name="SSP1_RST_N" description="SSP1 reset control"> + <Enum name="RESET" start="0" description="Reset. Resets the SSP1 peripheral." /> + <Enum name="CLEAR_RESET" start="1" description="Clear reset. SSP1 reset de-asserted." /> + </BitField> + <BitField start="3" size="1" name="I2C1_RST_N" description="I2C1 reset control"> + <Enum name="RESET" start="0" description="Reset. Resets the I2C1 peripheral." /> + <Enum name="CLEAR_RESET" start="1" description="Clear reset. I2C1 reset de-asserted." /> + </BitField> + <BitField start="4" size="1" name="FRG_RST_N" description="FRG reset control"> + <Enum name="RESET" start="0" description="Reset. Resets the FRG peripheral." /> + <Enum name="CLEAR_RESET" start="1" description="Clear reset. FRG reset de-asserted." /> + </BitField> + <BitField start="5" size="1" name="USART1_RST_N" description="USART1 reset control"> + <Enum name="RESET" start="0" description="Reset. Resets the USART1 peripheral." /> + <Enum name="CLEAR_RESET" start="1" description="Clear reset. USART1 reset de-asserted." /> + </BitField> + <BitField start="6" size="1" name="USART2_RST_N" description="USART2 reset control"> + <Enum name="RESET" start="0" description="Reset. Resets the USART2 peripheral." /> + <Enum name="CLEAR_RESET" start="1" description="Clear reset. USART2 reset de-asserted." /> + </BitField> + <BitField start="7" size="1" name="USART3_RST_N" description="USART3 reset control"> + <Enum name="RESET" start="0" description="Reset. Resets the USART3 peripheral." /> + <Enum name="CLEAR_RESET" start="1" description="Clear reset. USART3 reset de-asserted." /> + </BitField> + <BitField start="8" size="1" name="USART4_RST_N" description="USART4 reset control"> + <Enum name="RESET" start="0" description="Reset. Resets the USART4 peripheral." /> + <Enum name="CLEAR_RESET" start="1" description="Clear reset. USART4 reset de-asserted." /> + </BitField> + <BitField start="9" size="1" name="SCT0_RST_N" description="SCT0 reset control"> + <Enum name="RESET" start="0" description="Reset. Resets the SCT0 peripheral." /> + <Enum name="CLEAR_RESET" start="1" description="Clear reset. SCT0 reset de-asserted." /> + </BitField> + <BitField start="10" size="1" name="SCT1_RST_N" description="SCT1 reset control"> + <Enum name="RESET" start="0" description="Reset. Resets the SCT1 peripheral." /> + <Enum name="CLEAR_RESET" start="1" description="Clear reset. SCT1 reset de-asserted." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x008" size="4" name="SYSPLLCTRL" access="Read/Write" description="System PLL control" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="MSEL" description="Feedback divider value. The division value M is the programmed MSEL value + 1. 00000: Division ratio M = 1 to 11111: Division ratio M = 32" /> + <BitField start="5" size="2" name="PSEL" description="Post divider ratio P. The division ratio is 2 x P."> + <Enum name="P_EQ_1" start="0x0" description="P = 1" /> + <Enum name="P_EQ_2" start="0x1" description="P = 2" /> + <Enum name="P_EQ_4" start="0x2" description="P = 4" /> + <Enum name="P_EQ_8" start="0x3" description="P = 8" /> + </BitField> + <BitField start="7" size="25" name="RESERVED" description="Reserved. Do not write ones to reserved bits." /> + </Register> + <Register start="+0x00C" size="4" name="SYSPLLSTAT" access="ReadOnly" description="System PLL status" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="LOCK" description="PLL lock status"> + <Enum name="NO_LOCK" start="0" description="No lock. PLL not locked" /> + <Enum name="LOCK" start="1" description="Lock. PLL locked" /> + </BitField> + <BitField start="1" size="31" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x010" size="4" name="USBPLLCTRL" access="Read/Write" description="USB PLL control" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="MSEL" description="Feedback divider value. The division value M is the programmed MSEL value + 1. 00000: Division ratio M = 1 to 11111: Division ratio M = 32" /> + <BitField start="5" size="2" name="PSEL" description="Post divider ratio P. The division ratio is 2 x P."> + <Enum name="P_EQ_1" start="0x0" description="P = 1" /> + <Enum name="P_EQ_2" start="0x1" description="P = 2" /> + <Enum name="P_EQ_4" start="0x2" description="P = 4" /> + <Enum name="P_EQ_8" start="0x3" description="P = 8" /> + </BitField> + <BitField start="7" size="25" name="RESERVED" description="Reserved. Do not write ones to reserved bits." /> + </Register> + <Register start="+0x014" size="4" name="USBPLLSTAT" access="ReadOnly" description="USB PLL status" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="LOCK" description="PLL lock status"> + <Enum name="NO_LOCK" start="0" description="No lock. PLL not locked" /> + <Enum name="LOCK" start="1" description="Lock. PLL locked" /> + </BitField> + <BitField start="1" size="31" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x01C" size="4" name="RTCOSCCTRL" access="Read/Write" description="RTC oscillator 32 kHz output control" reset_value="0x1" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RTCOSCEN" description="Enable the RTC 32 kHz output."> + <Enum name="DISABLED" start="0" description="Disabled. 32 kHz output disabled." /> + <Enum name="ENABLED" start="1" description="Enabled. 32 kHz output enabled." /> + </BitField> + <BitField start="1" size="31" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x020" size="4" name="SYSOSCCTRL" access="Read/Write" description="System oscillator control" reset_value="0x000" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="BYPASS" description="Bypass system oscillator"> + <Enum name="OSCILLATOR_IS_NOT_BY" start="0" description="Oscillator is not bypassed." /> + <Enum name="BYPASS_ENABLED" start="1" description="Bypass enabled. PLL input (sys_osc_clk) is fed directly from the XTALIN pin bypassing the oscillator. Use this mode when using an external clock source instead of the crystal oscillator." /> + </BitField> + <BitField start="1" size="1" name="FREQRANGE" description="Determines frequency range for Low-power oscillator."> + <Enum name="LOW" start="0" description="Low. 1 - 20 MHz frequency range." /> + <Enum name="HIGH" start="1" description="High. 15 - 25 MHz frequency range." /> + </BitField> + <BitField start="2" size="30" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x024" size="4" name="WDTOSCCTRL" access="Read/Write" description="Watchdog oscillator control" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="DIVSEL" description="Select divider for Fclkana. wdt_osc_clk = Fclkana/ (2 x (1 + DIVSEL)) 00000: 2 x (1 + DIVSEL) = 2 00001: 2 x (1 + DIVSEL) = 4 to 11111: 2 x (1 + DIVSEL) = 64" /> + <BitField start="5" size="4" name="FREQSEL" description="Select watchdog oscillator analog output frequency (Fclkana)."> + <Enum name="0" start="0x1" description="0.6 MHz" /> + <Enum name="1" start="0x2" description="1.05 MHz" /> + <Enum name="1" start="0x3" description="1.4 MHz" /> + <Enum name="1" start="0x4" description="1.75 MHz" /> + <Enum name="2" start="0x5" description="2.1 MHz" /> + <Enum name="2" start="0x6" description="2.4 MHz" /> + <Enum name="2" start="0x7" description="2.7 MHz" /> + <Enum name="3" start="0x8" description="3.0 MHz" /> + <Enum name="3" start="0x9" description="3.25 MHz" /> + <Enum name="3" start="0xA" description="3.5 MHz" /> + <Enum name="3" start="0xB" description="3.75 MHz" /> + <Enum name="4" start="0xC" description="4.0 MHz" /> + <Enum name="4" start="0xD" description="4.2 MHz" /> + <Enum name="4" start="0xE" description="4.4 MHz" /> + <Enum name="4" start="0xF" description="4.6 MHz" /> + </BitField> + <BitField start="9" size="23" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x028" size="4" name="IRCCTRL" access="Read/Write" description="IRC control" reset_value="0x080" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="TRIM" description="Trim value" /> + <BitField start="8" size="24" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x030" size="4" name="SYSRSTSTAT" access="Read/Write" description="System reset status register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="POR" description="POR reset status"> + <Enum name="NO_POR_DETECTED" start="0" description="No POR detected" /> + <Enum name="POR_DETECTED" start="1" description="POR detected" /> + </BitField> + <BitField start="1" size="1" name="EXTRST" description="Status of the external RESET pin"> + <Enum name="NO_RESET_EVENT_DETEC" start="0" description="No reset event detected" /> + <Enum name="RESET_DETECTED" start="1" description="Reset detected" /> + </BitField> + <BitField start="2" size="1" name="WDT" description="Status of the Watchdog reset"> + <Enum name="NO_WDT_RESET_DETECTE" start="0" description="No WDT reset detected" /> + <Enum name="WDT_RESET_DETECTED" start="1" description="WDT reset detected" /> + </BitField> + <BitField start="3" size="1" name="BOD" description="Status of the Brown-out detect reset"> + <Enum name="NO_BOD_RESET_DETECTE" start="0" description="No BOD reset detected" /> + <Enum name="BOD_RESET_DETECTED" start="1" description="BOD reset detected" /> + </BitField> + <BitField start="4" size="1" name="SYSRST" description="Status of the software system reset"> + <Enum name="NO_SYSTEM_RESET_DETE" start="0" description="No System reset detected" /> + <Enum name="SYSTEM_RESET_DETECTE" start="1" description="System reset detected" /> + </BitField> + <BitField start="5" size="27" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x040" size="4" name="SYSPLLCLKSEL" access="Read/Write" description="System PLL clock source select" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="SEL" description="System PLL clock source"> + <Enum name="IRC" start="0x0" description="IRC" /> + <Enum name="SYSTEM_OSCILLATOR" start="0x1" description="System oscillator. Crystal Oscillator (SYSOSC)" /> + <Enum name="RESERVED" start="0x2" description="Reserved" /> + <Enum name="32_KHZ_CLOCK" start="0x3" description="32 kHz clock.Select this option when the 32 kHz clock is the clock source for the main clock and select the pll input in the MAINCLKSEL register. Do not use the 32 kHz clock with the PLL." /> + </BitField> + <BitField start="2" size="30" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x044" size="4" name="SYSPLLCLKUEN" access="Read/Write" description="System PLL clock source update enable" reset_value="0x1" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="ENA" description="Enable system PLL clock source update"> + <Enum name="NO_CHANGE" start="0" description="No change" /> + <Enum name="UPDATE_CLOCK_SOURCE" start="1" description="Update clock source" /> + </BitField> + <BitField start="1" size="31" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x048" size="4" name="USBPLLCLKSEL" access="Read/Write" description="USB PLL clock source select" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="SEL" description="USB PLL clock source"> + <Enum name="IRC" start="0x0" description="IRC. For full-speed USB, switch the USB PLL clock source to the system oscillator for correct USB operation. The IRC is suitable for low-speed USB operation only." /> + <Enum name="SYSTEM_OSCILLATOR" start="0x1" description="System oscillator" /> + <Enum name="RESERVED" start="0x2" description="Reserved" /> + <Enum name="RESERVED" start="0x3" description="Reserved" /> + </BitField> + <BitField start="2" size="30" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x04C" size="4" name="USBPLLCLKUEN" access="Read/Write" description="USB PLL clock source update enable" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="ENA" description="Enable USB PLL clock source update"> + <Enum name="NO_CHANGE" start="0" description="No change" /> + <Enum name="UPDATE_CLOCK_SOURCE" start="1" description="Update clock source" /> + </BitField> + <BitField start="1" size="31" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x070" size="4" name="MAINCLKSEL" access="Read/Write" description="Main clock source select" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="SEL" description="Clock source for main clock"> + <Enum name="IRC_OSCILLATOR" start="0x0" description="IRC Oscillator" /> + <Enum name="PLL_INPUT" start="0x1" description="PLL input" /> + <Enum name="WATCHDOG_OSCILLATOR" start="0x2" description="Watchdog oscillator" /> + <Enum name="PLL_OUTPUT" start="0x3" description="PLL output" /> + </BitField> + <BitField start="2" size="30" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x074" size="4" name="MAINCLKUEN" access="Read/Write" description="Main clock source update enable" reset_value="0x1" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="ENA" description="Enable main clock source update"> + <Enum name="NO_CHANGE" start="0" description="No change" /> + <Enum name="UPDATE_CLOCK_SOURCE" start="1" description="Update clock source" /> + </BitField> + <BitField start="1" size="31" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x078" size="4" name="SYSAHBCLKDIV" access="Read/Write" description="System clock divider" reset_value="0x001" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="DIV" description="System AHB clock divider values 0: System clock disabled. 1: Divide by 1. to 255: Divide by 255." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x080" size="4" name="SYSAHBCLKCTRL" access="Read/Write" description="System clock control" reset_value="0x3F" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="SYS" description="This bit is read-only and always reads as 1. It configures the always-on clock for the AHB, the APB bridges, the Cortex-M0 core clocks, SYSCON, reset control, SRAM0, and the PMU. Writes to this bit are ignored." /> + <BitField start="1" size="1" name="ROM" description="Enables clock for ROM."> + <Enum name="DISABLE" start="0" description="Disable" /> + <Enum name="ENABLE" start="1" description="Enable" /> + </BitField> + <BitField start="2" size="1" name="RAM0" description="Enables clock for Main SRAM0."> + <Enum name="DISABLE" start="0" description="Disable" /> + <Enum name="ENABLE" start="1" description="Enable" /> + </BitField> + <BitField start="3" size="1" name="FLASHREG" description="Enables clock for flash register interface."> + <Enum name="DISABLED" start="0" description="Disabled" /> + <Enum name="ENABLED" start="1" description="Enabled" /> + </BitField> + <BitField start="4" size="1" name="FLASHARRAY" description="Enables clock for flash access."> + <Enum name="DISABLED" start="0" description="Disabled" /> + <Enum name="ENABLED" start="1" description="Enabled" /> + </BitField> + <BitField start="5" size="1" name="I2C0" description="Enables clock for I2C."> + <Enum name="DISABLE" start="0" description="Disable" /> + <Enum name="ENABLE" start="1" description="Enable" /> + </BitField> + <BitField start="6" size="1" name="GPIO" description="Enables clock for GPIO port registers."> + <Enum name="DISABLE" start="0" description="Disable" /> + <Enum name="ENABLE" start="1" description="Enable" /> + </BitField> + <BitField start="7" size="1" name="CT16B0" description="Enables clock for 16-bit counter/timer 0."> + <Enum name="DISABLE" start="0" description="Disable" /> + <Enum name="ENABLE" start="1" description="Enable" /> + </BitField> + <BitField start="8" size="1" name="CT16B1" description="Enables clock for 16-bit counter/timer 1."> + <Enum name="DISABLE" start="0" description="Disable" /> + <Enum name="ENABLE" start="1" description="Enable" /> + </BitField> + <BitField start="9" size="1" name="CT32B0" description="Enables clock for 32-bit counter/timer 0."> + <Enum name="DISABLE" start="0" description="Disable" /> + <Enum name="ENABLE" start="1" description="Enable" /> + </BitField> + <BitField start="10" size="1" name="CT32B1" description="Enables clock for 32-bit counter/timer 1."> + <Enum name="DISABLE" start="0" description="Disable" /> + <Enum name="ENABLE" start="1" description="Enable" /> + </BitField> + <BitField start="11" size="1" name="SSP0" description="Enables clock for SSP0."> + <Enum name="DISABLE" start="0" description="Disable" /> + <Enum name="ENABLE" start="1" description="Enable" /> + </BitField> + <BitField start="12" size="1" name="USART0" description="Enables clock for USART0."> + <Enum name="DISABLE" start="0" description="Disable" /> + <Enum name="ENABLE" start="1" description="Enable" /> + </BitField> + <BitField start="13" size="1" name="ADC" description="Enables clock for ADC."> + <Enum name="DISABLE" start="0" description="Disable" /> + <Enum name="ENABLE" start="1" description="Enable" /> + </BitField> + <BitField start="14" size="1" name="USB" description="Enables clock to the USB register interface."> + <Enum name="DISABLE" start="0" description="Disable" /> + <Enum name="ENABLE" start="1" description="Enable" /> + </BitField> + <BitField start="15" size="1" name="WWDT" description="Enables clock for WWDT."> + <Enum name="DISABLE" start="0" description="Disable" /> + <Enum name="ENABLE" start="1" description="Enable" /> + </BitField> + <BitField start="16" size="1" name="IOCON" description="Enables clock for I/O configuration block."> + <Enum name="DISABLE" start="0" description="Disable" /> + <Enum name="ENABLE" start="1" description="Enable" /> + </BitField> + <BitField start="17" size="1" name="RESERVED" description="Reserved" /> + <BitField start="18" size="1" name="SSP1" description="Enables clock for SSP1."> + <Enum name="DISABLE" start="0" description="Disable" /> + <Enum name="ENABLE" start="1" description="Enable" /> + </BitField> + <BitField start="19" size="1" name="PINT" description="Enables clock to GPIO Pin interrupt register interface."> + <Enum name="DISABLE" start="0" description="Disable" /> + <Enum name="ENABLE" start="1" description="Enable" /> + </BitField> + <BitField start="20" size="1" name="USART1" description="Enables clock to USART1 register interface."> + <Enum name="DISABLE" start="0" description="Disable" /> + <Enum name="ENABLE" start="1" description="Enable" /> + </BitField> + <BitField start="21" size="1" name="USART2" description="Enables clock to USART2 register interface."> + <Enum name="DISABLE" start="0" description="Disable" /> + <Enum name="ENABLE" start="1" description="Enable" /> + </BitField> + <BitField start="22" size="1" name="USART3_4" description="Enables clock to USART3 and USART4 register interfaces."> + <Enum name="DISABLE" start="0" description="Disable" /> + <Enum name="ENABLE" start="1" description="Enable" /> + </BitField> + <BitField start="23" size="1" name="GROUP0INT" description="Enables clock to GPIO GROUP0 interrupt register interface."> + <Enum name="DISABLE" start="0" description="Disable" /> + <Enum name="ENABLE" start="1" description="Enable" /> + </BitField> + <BitField start="24" size="1" name="GROUP1INT" description="Enables clock to GPIO GROUP1 interrupt register interface."> + <Enum name="DISABLE" start="0" description="Disable" /> + <Enum name="ENABLE" start="1" description="Enable" /> + </BitField> + <BitField start="25" size="1" name="I2C1" description="Enables clock for I2C1."> + <Enum name="DISABLE" start="0" description="Disable" /> + <Enum name="ENABLE" start="1" description="Enable" /> + </BitField> + <BitField start="26" size="1" name="RAM1" description="Enables clock for SRAM1 located at 0x2000 0000 to 0x2000 0800."> + <Enum name="DISABLE" start="0" description="Disable" /> + <Enum name="ENABLE" start="1" description="Enable" /> + </BitField> + <BitField start="27" size="1" name="USBSRAM" description="Enables USB SRAM/SRAM2 block located at 0x2000 4000 to 0x2000 4800."> + <Enum name="DISABLE" start="0" description="Disable" /> + <Enum name="ENABLE" start="1" description="Enable" /> + </BitField> + <BitField start="28" size="1" name="CRC" description="Enables clock for CRC."> + <Enum name="DISABLE" start="0" description="Disable" /> + <Enum name="ENABLE" start="1" description="Enable" /> + </BitField> + <BitField start="29" size="1" name="DMA" description="Enables clock for DMA."> + <Enum name="DISABLE" start="0" description="Disable" /> + <Enum name="ENABLE" start="1" description="Enable" /> + </BitField> + <BitField start="30" size="1" name="RTC" description="Enables clock for RTC register interface."> + <Enum name="DISABLE" start="0" description="Disable" /> + <Enum name="ENABLE" start="1" description="Enable" /> + </BitField> + <BitField start="31" size="1" name="SCT0_1" description="Enables clock for SCT0 and SCT1."> + <Enum name="DISABLE" start="0" description="Disable" /> + <Enum name="ENABLE" start="1" description="Enable" /> + </BitField> + </Register> + <Register start="+0x094" size="4" name="SSP0CLKDIV" access="Read/Write" description="SSP0 clock divider" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="DIV" description="SPI0_PCLK clock divider values. 0: System clock disabled. 1: Divide by 1. to 255: Divide by 255." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x098" size="4" name="USART0CLKDIV" access="Read/Write" description="USART0 clock divider" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="DIV" description="UART_PCLK clock divider values 0: Disable UART_PCLK. 1: Divide by 1. to 255: Divide by 255." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x09C" size="4" name="SSP1CLKDIV" access="Read/Write" description="SSP1 clock divider" reset_value="0x0000" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="DIV" description="SSP1_PCLK clock divider values 0: Disable SSP1_PCLK. 1: Divide by 1. to 255: Divide by 255." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x0A0" size="4" name="FRGCLKDIV" access="Read/Write" description="Clock divider for the common fractional baud rate generator of USART1, USART2, USART3, USART4" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="DIV" description="USART fractional baud rate generator clock divider values. 0: Clock disabled. 1: Divide by 1. to 255: Divide by 255." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x0C0" size="4" name="USBCLKSEL" access="Read/Write" description="USB clock source select" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="SEL" description="USB clock source. Values 0x2 and 0x3 are reserved."> + <Enum name="USB_PLL_OUT" start="0x0" description="USB PLL out" /> + <Enum name="MAIN_CLOCK" start="0x1" description="Main clock" /> + </BitField> + <BitField start="2" size="30" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x0C4" size="4" name="USBCLKUEN" access="Read/Write" description="USB clock source update enable" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="ENA" description="Enable USB clock source update"> + <Enum name="NO_CHANGE" start="0" description="No change" /> + <Enum name="UPDATE_CLOCK_SOURCE" start="1" description="Update clock source" /> + </BitField> + <BitField start="1" size="31" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x0C8" size="4" name="USBCLKDIV" access="Read/Write" description="USB clock source divider" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="DIV" description="USB clock divider values 0: Disable USB clock. 1: Divide by 1. to 255: Divide by 255." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x0E0" size="4" name="CLKOUTSEL" access="Read/Write" description="CLKOUT clock source select" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="SEL" description="CLKOUT clock source"> + <Enum name="IRC_OSCILLATOR" start="0x0" description="IRC oscillator" /> + <Enum name="CRYSTAL_OSCILLATOR" start="0x1" description="Crystal oscillator (SYSOSC)" /> + <Enum name="WATCHDOG_OSCILLATOR" start="0x2" description="Watchdog oscillator" /> + <Enum name="MAIN_CLOCK" start="0x3" description="Main clock" /> + </BitField> + <BitField start="2" size="30" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x0E4" size="4" name="CLKOUTUEN" access="Read/Write" description="CLKOUT clock source update enable" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="ENA" description="Enable CLKOUT clock source update"> + <Enum name="NO_CHANGE" start="0" description="No change" /> + <Enum name="UPDATE_CLOCK_SOURCE" start="1" description="Update clock source" /> + </BitField> + <BitField start="1" size="31" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x0E8" size="4" name="CLKOUTDIV" access="Read/Write" description="CLKOUT clock divider" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="DIV" description="CLKOUT clock divider values 0: Disable CLKOUT clock divider. 1: Divide by 1. to 255: Divide by 255." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x0F0" size="4" name="UARTFRGDIV" access="Read/Write" description="USART fractional generator divider value" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="DIV" description="Denominator of the fractional divider. DIV is equal to the programmed value +1. Always set to 0xFF to use with the fractional baud rate generator." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x0F4" size="4" name="UARTFRGMULT" access="Read/Write" description="USART fractional generator multiplier value" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="MULT" description="Numerator of the fractional divider. MULT is equal to the programmed value." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x0FC" size="4" name="EXTTRACECMD" access="Read/Write" description="External trace buffer command register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="START" description="Trace start command. Writing a one to this bit sets the TSTART signal to the MTB to HIGH and starts tracing if the TSTARTEN bit in the MTB master register is set to one as well." /> + <BitField start="1" size="1" name="STOP" description="Trace stop command. Writing a one to this bit sets the TSTOP signal in the MTB to HIGH and stops tracing if the TSTOPEN bit in the MTB master register is set to one as well." /> + <BitField start="2" size="30" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x100" size="4" name="PIOPORCAP0" access="ReadOnly" description="POR captured PIO status 0" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="24" name="PIOSTAT" description="State of PIO0_23 through PIO0_0 at power-on reset" /> + <BitField start="24" size="8" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x104" size="4" name="PIOPORCAP1" access="ReadOnly" description="POR captured PIO status 1" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="PIOSTAT" description="State of PIO1_31 through PIO1_0 at power-on reset" /> + </Register> + <Register start="+0x108" size="4" name="PIOPORCAP2" access="ReadOnly" description="POR captured PIO status 1" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="24" name="PIOSTAT" description="State of PIO2_23 through PIO2_0 at power-on reset" /> + </Register> + <Register start="+0x134" size="4" name="IOCONCLKDIV6" access="Read/Write" description="Peripheral clock to the IOCON block for programmable glitch filter" reset_value="0x00000000" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="DIV" description="IOCON glitch filter clock divider values 0: Disable IOCONFILTR_PCLK. 1: Divide by 1. to 255: Divide by 255." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x138" size="4" name="IOCONCLKDIV5" access="Read/Write" description="Peripheral clock to the IOCON block for programmable glitch filter" reset_value="0x00000000" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="DIV" description="IOCON glitch filter clock divider values 0: Disable IOCONFILTR_PCLK. 1: Divide by 1. to 255: Divide by 255." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x13C" size="4" name="IOCONCLKDIV4" access="Read/Write" description="Peripheral clock to the IOCON block for programmable glitch filter" reset_value="0x00000000" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="DIV" description="IOCON glitch filter clock divider values 0: Disable IOCONFILTR_PCLK. 1: Divide by 1. to 255: Divide by 255." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x140" size="4" name="IOCONCLKDIV3" access="Read/Write" description="Peripheral clock to the IOCON block for programmable glitch filter" reset_value="0x00000000" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="DIV" description="IOCON glitch filter clock divider values 0: Disable IOCONFILTR_PCLK. 1: Divide by 1. to 255: Divide by 255." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x144" size="4" name="IOCONCLKDIV2" access="Read/Write" description="Peripheral clock to the IOCON block for programmable glitch filter" reset_value="0x00000000" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="DIV" description="IOCON glitch filter clock divider values 0: Disable IOCONFILTR_PCLK. 1: Divide by 1. to 255: Divide by 255." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x148" size="4" name="IOCONCLKDIV1" access="Read/Write" description="Peripheral clock to the IOCON block for programmable glitch filter" reset_value="0x00000000" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="DIV" description="IOCON glitch filter clock divider values 0: Disable IOCONFILTR_PCLK. 1: Divide by 1. to 255: Divide by 255." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x14C" size="4" name="IOCONCLKDIV0" access="Read/Write" description="Peripheral clock to the IOCON block for programmable glitch filter" reset_value="0x00000000" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="DIV" description="IOCON glitch filter clock divider values 0: Disable IOCONFILTR_PCLK. 1: Divide by 1. to 255: Divide by 255." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x150" size="4" name="BODCTRL" access="Read/Write" description="Brown-Out Detect" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="BODRSTLEV" description="BOD reset level"> + <Enum name="LEVEL_0" start="0x0" description="Level 0." /> + <Enum name="LEVEL_1" start="0x1" description="Level 1." /> + <Enum name="LEVEL_2" start="0x2" description="Level 2." /> + <Enum name="LEVEL_3" start="0x3" description="Level 3." /> + </BitField> + <BitField start="2" size="2" name="BODINTVAL" description="BOD interrupt level"> + <Enum name="RESERVED" start="0x0" description="Reserved." /> + <Enum name="RESERVED" start="0x1" description="Reserved" /> + <Enum name="LEVEL_2" start="0x2" description="Level 2." /> + <Enum name="LEVEL_3" start="0x3" description="Level 3." /> + </BitField> + <BitField start="4" size="1" name="BODRSTENA" description="BOD reset enable"> + <Enum name="DISABLE_RESET_FUNCTI" start="0" description="Disable reset function." /> + <Enum name="ENABLE_RESET_FUNCTIO" start="1" description="Enable reset function." /> + </BitField> + <BitField start="5" size="27" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x154" size="4" name="SYSTCKCAL" access="Read/Write" description="System tick counter calibration" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="26" name="CAL" description="System tick timer calibration value" /> + <BitField start="26" size="6" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x170" size="4" name="IRQLATENCY" access="Read/Write" description="IRQ delay. Allows trade-off between interrupt latency and determinism." reset_value="0x00000010" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="LATENCY" description="8-bit latency value" /> + <BitField start="8" size="24" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x174" size="4" name="NMISRC" access="Read/Write" description="NMI Source Control" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="IRQN" description="The IRQ number of the interrupt that acts as the Non-Maskable Interrupt (NMI) if bit 31 is 1. See Table 6 for the list of interrupt sources and their IRQ numbers." /> + <BitField start="5" size="26" name="RESERVED" description="Reserved" /> + <BitField start="31" size="1" name="NMIEN" description="Write a 1 to this bit to enable the Non-Maskable Interrupt (NMI) source selected by bits 4:0." /> + </Register> + <Register start="+0x178+0" size="4" name="PINTSEL0" access="Read/Write" description="GPIO Pin Interrupt Select register 0" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="6" name="INTPIN" description="Pin number. PIO0_0 = 0, ..., PIO0_23 = 23, PIO1_0 = 24, ..., PIO1_31 = 55, PIO2_0 = 56, ..., PIO2_7 = 63." /> + <BitField start="6" size="26" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x178+4" size="4" name="PINTSEL1" access="Read/Write" description="GPIO Pin Interrupt Select register 0" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="6" name="INTPIN" description="Pin number. PIO0_0 = 0, ..., PIO0_23 = 23, PIO1_0 = 24, ..., PIO1_31 = 55, PIO2_0 = 56, ..., PIO2_7 = 63." /> + <BitField start="6" size="26" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x178+8" size="4" name="PINTSEL2" access="Read/Write" description="GPIO Pin Interrupt Select register 0" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="6" name="INTPIN" description="Pin number. PIO0_0 = 0, ..., PIO0_23 = 23, PIO1_0 = 24, ..., PIO1_31 = 55, PIO2_0 = 56, ..., PIO2_7 = 63." /> + <BitField start="6" size="26" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x178+12" size="4" name="PINTSEL3" access="Read/Write" description="GPIO Pin Interrupt Select register 0" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="6" name="INTPIN" description="Pin number. PIO0_0 = 0, ..., PIO0_23 = 23, PIO1_0 = 24, ..., PIO1_31 = 55, PIO2_0 = 56, ..., PIO2_7 = 63." /> + <BitField start="6" size="26" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x178+16" size="4" name="PINTSEL4" access="Read/Write" description="GPIO Pin Interrupt Select register 0" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="6" name="INTPIN" description="Pin number. PIO0_0 = 0, ..., PIO0_23 = 23, PIO1_0 = 24, ..., PIO1_31 = 55, PIO2_0 = 56, ..., PIO2_7 = 63." /> + <BitField start="6" size="26" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x178+20" size="4" name="PINTSEL5" access="Read/Write" description="GPIO Pin Interrupt Select register 0" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="6" name="INTPIN" description="Pin number. PIO0_0 = 0, ..., PIO0_23 = 23, PIO1_0 = 24, ..., PIO1_31 = 55, PIO2_0 = 56, ..., PIO2_7 = 63." /> + <BitField start="6" size="26" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x178+24" size="4" name="PINTSEL6" access="Read/Write" description="GPIO Pin Interrupt Select register 0" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="6" name="INTPIN" description="Pin number. PIO0_0 = 0, ..., PIO0_23 = 23, PIO1_0 = 24, ..., PIO1_31 = 55, PIO2_0 = 56, ..., PIO2_7 = 63." /> + <BitField start="6" size="26" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x178+28" size="4" name="PINTSEL7" access="Read/Write" description="GPIO Pin Interrupt Select register 0" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="6" name="INTPIN" description="Pin number. PIO0_0 = 0, ..., PIO0_23 = 23, PIO1_0 = 24, ..., PIO1_31 = 55, PIO2_0 = 56, ..., PIO2_7 = 63." /> + <BitField start="6" size="26" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x198" size="4" name="USBCLKCTRL" access="Read/Write" description="USB clock control" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="AP_CLK" description="USB need_clock signal control"> + <Enum name="HARDWARE" start="0" description="Hardware. Under hardware control." /> + <Enum name="FORCED" start="1" description="Forced. Forced HIGH." /> + </BitField> + <BitField start="1" size="1" name="POL_CLK" description="USB need_clock polarity for triggering the USB wake-up interrupt"> + <Enum name="FALLING_EDGE" start="0" description="Falling edge. Falling edge of the USB need_clock triggers the USB wake-up (default)." /> + <Enum name="RISING_EDGE" start="1" description="Rising edge. Rising edge of the USB need_clock triggers the USB wake-up." /> + </BitField> + <BitField start="2" size="1" name="RESERVED" description="Reserved. Only write 0 to this bit." /> + <BitField start="3" size="29" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x19C" size="4" name="USBCLKST" access="ReadOnly" description="USB clock status" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="NEED_CLKST" description="USB need_clock signal status"> + <Enum name="LOW" start="0" description="LOW" /> + <Enum name="HIGH" start="1" description="HIGH" /> + </BitField> + <BitField start="1" size="31" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x204" size="4" name="STARTERP0" access="Read/Write" description="Start logic 0 interrupt wake-up enable register 0" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="PINT0" description="Pin interrupt 0 wake-up"> + <Enum name="DISABLED" start="0" description="Disabled" /> + <Enum name="ENABLED" start="1" description="Enabled" /> + </BitField> + <BitField start="1" size="1" name="PINT1" description="Pin interrupt 1 wake-up"> + <Enum name="DISABLED" start="0" description="Disabled" /> + <Enum name="ENABLED" start="1" description="Enabled" /> + </BitField> + <BitField start="2" size="1" name="PINT2" description="Pin interrupt 2 wake-up"> + <Enum name="DISABLED" start="0" description="Disabled" /> + <Enum name="ENABLED" start="1" description="Enabled" /> + </BitField> + <BitField start="3" size="1" name="PINT3" description="Pin interrupt 3 wake-up"> + <Enum name="DISABLED" start="0" description="Disabled" /> + <Enum name="ENABLED" start="1" description="Enabled" /> + </BitField> + <BitField start="4" size="1" name="PINT4" description="Pin interrupt 4 wake-up"> + <Enum name="DISABLED" start="0" description="Disabled" /> + <Enum name="ENABLED" start="1" description="Enabled" /> + </BitField> + <BitField start="5" size="1" name="PINT5" description="Pin interrupt 5 wake-up"> + <Enum name="DISABLED" start="0" description="Disabled" /> + <Enum name="ENABLED" start="1" description="Enabled" /> + </BitField> + <BitField start="6" size="1" name="PINT6" description="Pin interrupt 6 wake-up"> + <Enum name="DISABLED" start="0" description="Disabled" /> + <Enum name="ENABLED" start="1" description="Enabled" /> + </BitField> + <BitField start="7" size="1" name="PINT7" description="Pin interrupt 7 wake-up"> + <Enum name="DISABLED" start="0" description="Disabled" /> + <Enum name="ENABLED" start="1" description="Enabled" /> + </BitField> + <BitField start="8" size="24" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x214" size="4" name="STARTERP1" access="Read/Write" description="Start logic 1 interrupt wake-up enable register 1" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="12" size="1" name="RTCINT" description="RTC interrupt wake-up"> + <Enum name="DISABLED" start="0" description="Disabled" /> + <Enum name="ENABLED" start="1" description="Enabled" /> + </BitField> + <BitField start="13" size="1" name="WWDT_BODINT" description="Combined WWDT interrupt or Brown Out Detect (BOD) interrupt wake-up"> + <Enum name="DISABLED" start="0" description="Disabled" /> + <Enum name="ENABLED" start="1" description="Enabled" /> + </BitField> + <BitField start="14" size="5" name="RESERVED" description="Reserved" /> + <BitField start="19" size="1" name="USB_WAKEUP" description="USB need_clock signal wake-up"> + <Enum name="DISABLED" start="0" description="Disabled" /> + <Enum name="ENABLED" start="1" description="Enabled" /> + </BitField> + <BitField start="20" size="1" name="GROUP0INT" description="GPIO GROUP0 interrupt wake-up"> + <Enum name="DISABLED" start="0" description="Disabled" /> + <Enum name="ENABLED" start="1" description="Enabled" /> + </BitField> + <BitField start="21" size="1" name="GROUP1INT" description="GPIO GROUP1 interrupt wake-up"> + <Enum name="DISABLED" start="0" description="Disabled" /> + <Enum name="ENABLED" start="1" description="Enabled" /> + </BitField> + <BitField start="22" size="1" name="RESERVED" description="Reserved." /> + <BitField start="23" size="1" name="USART1_4" description="Combined USART1 and USART4 interrupt wake-up"> + <Enum name="DISABLED" start="0" description="Disabled" /> + <Enum name="ENABLED" start="1" description="Enabled" /> + </BitField> + <BitField start="24" size="1" name="USART2_3" description="Combined USART2 and USART3 interrupt wake-up"> + <Enum name="DISABLED" start="0" description="Disabled" /> + <Enum name="ENABLED" start="1" description="Enabled" /> + </BitField> + </Register> + <Register start="+0x230" size="4" name="PDSLEEPCFG" access="Read/Write" description="Power-down states in deep-sleep mode" reset_value="0" reset_mask="0x00000000"> + <BitField start="3" size="1" name="BOD_PD" description="BOD power-down control for Deep-sleep and Power-down mode"> + <Enum name="POWERED_DOWN" start="1" description="Powered down" /> + <Enum name="POWERED" start="0" description="Powered" /> + </BitField> + <BitField start="4" size="2" name="RESERVED" description="Reserved." /> + <BitField start="6" size="1" name="WDTOSC_PD" description="Watchdog oscillator power-down control for Deep-sleep and Power-down mode"> + <Enum name="POWERED_DOWN" start="1" description="Powered down" /> + <Enum name="POWERED" start="0" description="Powered" /> + </BitField> + <BitField start="7" size="25" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x234" size="4" name="PDAWAKECFG" access="Read/Write" description="Power-down states for wake-up from deep-sleep" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="IRCOUT_PD" description="IRC oscillator output wake-up configuration"> + <Enum name="POWERED_DOWN" start="1" description="Powered down" /> + <Enum name="POWERED" start="0" description="Powered" /> + </BitField> + <BitField start="1" size="1" name="IRC_PD" description="IRC oscillator power-down wake-up configuration"> + <Enum name="POWERED_DOWN" start="1" description="Powered down" /> + <Enum name="POWERED" start="0" description="Powered" /> + </BitField> + <BitField start="2" size="1" name="FLASH_PD" description="Flash wake-up configuration"> + <Enum name="POWERED_DOWN" start="1" description="Powered down" /> + <Enum name="POWERED" start="0" description="Powered" /> + </BitField> + <BitField start="3" size="1" name="BOD_PD" description="BOD wake-up configuration"> + <Enum name="POWERED_DOWN" start="1" description="Powered down" /> + <Enum name="POWERED" start="0" description="Powered" /> + </BitField> + <BitField start="4" size="1" name="ADC_PD" description="ADC wake-up configuration"> + <Enum name="POWERED_DOWN" start="1" description="Powered down" /> + <Enum name="POWERED" start="0" description="Powered" /> + </BitField> + <BitField start="5" size="1" name="SYSOSC_PD" description="Crystal oscillator wake-up configuration"> + <Enum name="POWERED_DOWN" start="1" description="Powered down" /> + <Enum name="POWERED" start="0" description="Powered" /> + </BitField> + <BitField start="6" size="1" name="WDTOSC_PD" description="Watchdog oscillator wake-up configuration"> + <Enum name="POWERED_DOWN" start="1" description="Powered down" /> + <Enum name="POWERED" start="0" description="Powered" /> + </BitField> + <BitField start="7" size="1" name="SYSPLL_PD" description="System PLL wake-up configuration"> + <Enum name="POWERED_DOWN" start="1" description="Powered down" /> + <Enum name="POWERED" start="0" description="Powered" /> + </BitField> + <BitField start="8" size="1" name="USBPLL_PD" description="USB PLL wake-up configuration"> + <Enum name="POWERED" start="0" description="Powered" /> + <Enum name="POWERED_DOWN" start="1" description="Powered down" /> + </BitField> + <BitField start="9" size="1" name="RESERVED" description="Reserved. Always write this bit as 0." /> + <BitField start="10" size="1" name="USBPAD_PD" description="USB transceiver wake-up configuration"> + <Enum name="POWERED" start="0" description="Powered" /> + <Enum name="POWERED_DOWN" start="1" description="Powered down" /> + </BitField> + <BitField start="11" size="1" name="RESERVED" description="Reserved. This bit must be set to one in Run mode." /> + <BitField start="12" size="1" name="RESERVED" description="Reserved." /> + <BitField start="13" size="1" name="TEMPSENSE_PD" description="Temperature sensor wake-up configuration"> + <Enum name="POWERED" start="0" description="Powered" /> + <Enum name="POWERED_DOWN" start="1" description="Powered down" /> + </BitField> + <BitField start="14" size="18" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x238" size="4" name="PDRUNCFG" access="Read/Write" description="Power configuration register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="IRCOUT_PD" description="IRC oscillator output power-down"> + <Enum name="POWERED" start="0" description="Powered" /> + <Enum name="POWERED_DOWN" start="1" description="Powered down" /> + </BitField> + <BitField start="1" size="1" name="IRC_PD" description="IRC oscillator power-down"> + <Enum name="POWERED" start="0" description="Powered" /> + <Enum name="POWERED_DOWN" start="1" description="Powered down" /> + </BitField> + <BitField start="2" size="1" name="FLASH_PD" description="Flash power-down"> + <Enum name="POWERED" start="0" description="Powered" /> + <Enum name="POWERED_DOWN" start="1" description="Powered down" /> + </BitField> + <BitField start="3" size="1" name="BOD_PD" description="BOD power-down"> + <Enum name="POWERED" start="0" description="Powered" /> + <Enum name="POWERED_DOWN" start="1" description="Powered down" /> + </BitField> + <BitField start="4" size="1" name="ADC_PD" description="ADC power-down"> + <Enum name="POWERED" start="0" description="Powered" /> + <Enum name="POWERED_DOWN" start="1" description="Powered down" /> + </BitField> + <BitField start="5" size="1" name="SYSOSC_PD" description="Crystal oscillator power-down. After power-up, add a software delay of approximately 500 us before using."> + <Enum name="POWERED" start="0" description="Powered" /> + <Enum name="POWERED_DOWN" start="1" description="Powered down" /> + </BitField> + <BitField start="6" size="1" name="WDTOSC_PD" description="Watchdog oscillator power-down"> + <Enum name="POWERED" start="0" description="Powered" /> + <Enum name="POWERED_DOWN" start="1" description="Powered down" /> + </BitField> + <BitField start="7" size="1" name="SYSPLL_PD" description="System PLL power-down"> + <Enum name="POWERED" start="0" description="Powered" /> + <Enum name="POWERED_DOWN" start="1" description="Powered down" /> + </BitField> + <BitField start="8" size="1" name="USBPLL_PD" description="USB PLL power-down"> + <Enum name="POWERED" start="0" description="Powered" /> + <Enum name="POWERED_DOWN" start="1" description="Powered down" /> + </BitField> + <BitField start="9" size="1" name="RESERVED" description="Reserved. Always write this bit as 0." /> + <BitField start="10" size="1" name="USBPAD_PD" description="USB transceiver power-down configuration"> + <Enum name="POWERED" start="0" description="Powered" /> + <Enum name="POWERED_DOWN" start="1" description="Powered down" /> + </BitField> + <BitField start="11" size="1" name="RESERVED" description="Reserved. This bit must be set to one in Run mode." /> + <BitField start="12" size="1" name="RESERVED" description="Reserved." /> + <BitField start="13" size="1" name="TEMPSENSE_PD" description="Temperature sensor wake-up configuration"> + <Enum name="POWERED" start="0" description="Powered" /> + <Enum name="POWERED_DOWN" start="1" description="Powered down" /> + </BitField> + <BitField start="14" size="2" name="RESERVED" description="Reserved. Always write these bits as 0b11." /> + <BitField start="16" size="16" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x3F4" size="4" name="DEVICE_ID" access="ReadOnly" description="Device ID" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="DEVICEID" description="PARTID" /> + </Register> + </RegisterGroup> + <RegisterGroup name="USART4" start="0x4004C000" description="USART4 "> + <Register start="+0x000" size="4" name="CFG" access="Read/Write" description="USART Configuration register. Basic USART configuration settings that typically are not changed during operation." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="ENABLE" description="USART Enable."> + <Enum name="DISABLED" start="0" description="Disabled. The USART is disabled and the internal state machine and counters are reset. While Enable = 0, all USART interrupts and DMA transfers are disabled. When Enable is set again, CFG and most other control bits remain unchanged. For instance, when re-enabled, the USART will immediately generate a TxRdy interrupt (if enabled in the INTENSET register) or a DMA transfer request because the transmitter has been reset and is therefore available." /> + <Enum name="ENABLED" start="1" description="Enabled. The USART is enabled for operation." /> + </BitField> + <BitField start="1" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="2" size="2" name="DATALEN" description="Selects the data size for the USART."> + <Enum name="7_BIT_DATA_LENGTH" start="0x0" description="7 bit Data length." /> + <Enum name="8_BIT_DATA_LENGTH" start="0x1" description="8 bit Data length." /> + <Enum name="9_BIT_DATA_LENGTH" start="0x2" description="9 bit data length. The 9th bit is commonly used for addressing in multidrop mode. See the ADDRDET bit in the CTL register." /> + <Enum name="RESERVED" start="0x3" description="Reserved." /> + </BitField> + <BitField start="4" size="2" name="PARITYSEL" description="Selects what type of parity is used by the USART."> + <Enum name="NO_PARITY" start="0x0" description="No parity." /> + <Enum name="RESERVED" start="0x1" description="Reserved." /> + <Enum name="EVEN_PARITY" start="0x2" description="Even parity. Adds a bit to each character such that the number of 1s in a transmitted character is even, and the number of 1s in a received character is expected to be even." /> + <Enum name="ODD_PARITY" start="0x3" description="Odd parity. Adds a bit to each character such that the number of 1s in a transmitted character is odd, and the number of 1s in a received character is expected to be odd." /> + </BitField> + <BitField start="6" size="1" name="STOPLEN" description="Number of stop bits appended to transmitted data. Only a single stop bit is required for received data."> + <Enum name="1_STOP_BIT" start="0" description="1 stop bit." /> + <Enum name="2_STOP_BITS" start="1" description="2 stop bits. This setting should only be used for asynchronous communication." /> + </BitField> + <BitField start="7" size="1" name="MODE32K" description="Selects standard or 32 kHz clocking mode."> + <Enum name="STANDARD" start="0" description="UART uses standard clocking." /> + <Enum name="32KHZ" start="1" description="UART uses the 32 kHz clock from the RTC oscillator as the clock source to the BRG, and uses a special bit clocking scheme." /> + </BitField> + <BitField start="8" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="9" size="1" name="CTSEN" description="CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin, or from the USART's own RTS if loopback mode is enabled. See Section 11.8.4 for more information."> + <Enum name="NO_FLOW_CONTROL" start="0" description="No flow control. The transmitter does not receive any automatic flow control signal." /> + <Enum name="FLOW_CONTROL_ENABLED" start="1" description="Flow control enabled. The transmitter uses the CTS input (or RTS output in loopback mode) for flow control purposes." /> + </BitField> + <BitField start="10" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="11" size="1" name="SYNCEN" description="Selects synchronous or asynchronous operation."> + <Enum name="ASYNCHRONOUS" start="0" description="Asynchronous mode is selected." /> + <Enum name="SYNCHRONOUS" start="1" description="Synchronous mode is selected." /> + </BitField> + <BitField start="12" size="1" name="CLKPOL" description="Selects the clock polarity and sampling edge of received data in synchronous mode."> + <Enum name="FALLING_EDGE" start="0" description="Falling edge. Un_RXD is sampled on the falling edge of SCLK." /> + <Enum name="RISING_EDGE" start="1" description="Rising edge. Un_RXD is sampled on the rising edge of SCLK." /> + </BitField> + <BitField start="13" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="14" size="1" name="SYNCMST" description="Synchronous mode Master select."> + <Enum name="SLAVE" start="0" description="Slave. When synchronous mode is enabled, the USART is a slave." /> + <Enum name="MASTER" start="1" description="Master. When synchronous mode is enabled, the USART is a master." /> + </BitField> + <BitField start="15" size="1" name="LOOP" description="Selects data loopback mode."> + <Enum name="NORMAL_OPERATION" start="0" description="Normal operation." /> + <Enum name="LOOPBACK_MODE" start="1" description="Loopback mode. This provides a mechanism to perform diagnostic loopback testing for USART data. Serial data from the transmitter (Un_TXD) is connected internally to serial input of the receive (Un_RXD). Un_TXD and Un_RTS activity will also appear on external pins if these functions are configured to appear on device pins. The receiver RTS signal is also looped back to CTS and performs flow control if enabled by CTSEN." /> + </BitField> + <BitField start="16" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="18" size="1" name="OETA" description="Output Enable Turnaround time enable for RS-485 operation."> + <Enum name="DEASSERTED" start="0" description="Deasserted. If selected by OESEL, the Output Enable signal deasserted at the end of the last stop bit of a transmission." /> + <Enum name="ASSERTED" start="1" description="Asserted. If selected by OESEL, the Output Enable signal remains asserted for 1 character time after then end the last stop bit of a transmission. OE will also remain asserted if another transmit begins before it is deasserted." /> + </BitField> + <BitField start="19" size="1" name="AUTOADDR" description="Automatic Address matching enable."> + <Enum name="DISABLED" start="0" description="Disabled. When addressing is enabled by ADDRDET, address matching is done by software. This provides the possibility of versatile addressing (e.g. respond to more than one address)." /> + <Enum name="ENABLED" start="1" description="Enabled. When addressing is enabled by ADDRDET, address matching is done by hardware, using the value in the ADDR register as the address to match." /> + </BitField> + <BitField start="20" size="1" name="OESEL" description="Output Enable Select."> + <Enum name="FLOW_CONTROL" start="0" description="Flow control. The RTS signal is used as the standard flow control function." /> + <Enum name="OUTPUT_ENABLE" start="1" description="Output enable. The RTS signal is taken over in order to provide an output enable signal to control an RS-485 transceiver." /> + </BitField> + <BitField start="21" size="1" name="OEPOL" description="Output Enable Polarity."> + <Enum name="LOW" start="0" description="Low. If selected by OESEL, the output enable is active low." /> + <Enum name="HIGH" start="1" description="High. If selected by OESEL, the output enable is active high." /> + </BitField> + <BitField start="22" size="1" name="RXPOL" description="Receive data polarity."> + <Enum name="NOT_CHANGED" start="0" description="Not changed. The RX signal is used as it arrives from the pin. This means that the RX rest value is 1, start bit is 0, data is not inverted, and the stop bit is 1." /> + <Enum name="INVERTED" start="1" description="Inverted. The RX signal is inverted before being used by the UART. This means that the RX rest value is 0, start bit is 1, data is inverted, and the stop bit is 0." /> + </BitField> + <BitField start="23" size="1" name="TXPOL" description="Transmit data polarity."> + <Enum name="NOT_CHANGED" start="0" description="Not changed. The TX signal is sent out without change. This means that the TX rest value is 1, start bit is 0, data is not inverted, and the stop bit is 1." /> + <Enum name="INVERTED" start="1" description="Inverted. The TX signal is inverted by the UART before being sent out. This means that the TX rest value is 0, start bit is 1, data is inverted, and the stop bit is 0." /> + </BitField> + <BitField start="24" size="8" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x004" size="4" name="CTL" access="Read/Write" description="USART Control register. USART control settings that are more likely to change during operation." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="1" size="1" name="TXBRKEN" description="Break Enable."> + <Enum name="NORMAL_OPERATION" start="0" description="Normal operation." /> + <Enum name="CONTINUOUS_BREAK_IS" start="1" description="Continuous break is sent immediately when this bit is set, and remains until this bit is cleared. A break may be sent without danger of corrupting any currently transmitting character if the transmitter is first disabled (TXDIS in CTL is set) and then waiting for the transmitter to be disabled (TXDISINT in STAT = 1) before writing 1 to TXBRKEN." /> + </BitField> + <BitField start="2" size="1" name="ADDRDET" description="Enable address detect mode."> + <Enum name="DISABLED" start="0" description="Disabled. The USART presents all incoming data." /> + <Enum name="ENABLED" start="1" description="Enabled. The USART receiver ignores incoming data that does not have the most significant bit of the data (typically the 9th bit) = 1. When the data MSB bit = 1, the receiver treats the incoming data normally, generating a received data interrupt. Software can then check the data to see if this is an address that should be handled. If it is, the ADDRDET bit is cleared by software and further incoming data is handled normally." /> + </BitField> + <BitField start="3" size="3" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="6" size="1" name="TXDIS" description="Transmit Disable."> + <Enum name="NOT_DISABLED" start="0" description="Not disabled. USART transmitter is not disabled." /> + <Enum name="DISABLED" start="1" description="Disabled. USART transmitter is disabled after any character currently being transmitted is complete. This feature can be used to facilitate software flow control." /> + </BitField> + <BitField start="7" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="8" size="1" name="CC" description="Continuous Clock generation. By default, SCLK is only output while data is being transmitted in synchronous mode."> + <Enum name="CLOCK_ON_CHARACTER" start="0" description="Clock on character. In synchronous mode, SCLK cycles only when characters are being sent on Un_TXD or to complete a character that is being received." /> + <Enum name="CONTINUOUS_CLOCK" start="1" description="Continuous clock. SCLK runs continuously in synchronous mode, allowing characters to be received on Un_RxD independently from transmission on Un_TXD)." /> + </BitField> + <BitField start="9" size="1" name="CLRCCONRX" description="Clear Continuous Clock."> + <Enum name="NO_EFFECT" start="0" description="No effect on the CC bit." /> + <Enum name="AUTO_CLEAR" start="1" description="Auto-clear. The CC bit is automatically cleared when a complete character has been received. This bit is cleared at the same time." /> + </BitField> + <BitField start="10" size="6" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="16" size="1" name="AUTOBAUD" description="Autobaud enable."> + <Enum name="DISABLED" start="0" description="Disabled. UART is in normal operating mode." /> + <Enum name="ENABLED" start="1" description="Enabled. UART is in autobaud mode. This bit should only be set when the UART receiver is idle. The first start bit of RX is measured and used the update the BRG register to match the received data rate. AUTOBAUD is cleared once this process is complete, or if there is an AERR. This bit can be cleared by software when set, but only when the UART receiver is idle." /> + </BitField> + <BitField start="17" size="15" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x008" size="4" name="STAT" access="Read/Write" description="USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them." reset_value="0x000E" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RXRDY" description="Receiver Ready flag. When 1, indicates that data is available to be read from the receiver buffer. Cleared after a read of the RXDAT or RXDATSTAT registers." /> + <BitField start="1" size="1" name="RXIDLE" description="Receiver Idle. When 0, indicates that the receiver is currently in the process of receiving data. When 1, indicates that the receiver is not currently in the process of receiving data." /> + <BitField start="2" size="1" name="TXRDY" description="Transmitter Ready flag. When 1, this bit indicates that data may be written to the transmit buffer. Previous data may still be in the process of being transmitted. Cleared when data is written to TXDAT. Set when the data is moved from the transmit buffer to the transmit shift register." /> + <BitField start="3" size="1" name="TXIDLE" description="Transmitter Idle. When 0, indicates that the transmitter is currently in the process of sending data.When 1, indicate that the transmitter is not currently in the process of sending data." /> + <BitField start="4" size="1" name="CTS" description="This bit reflects the current state of the CTS signal, regardless of the setting of the CTSEN bit in the CFG register. This will be the value of the CTS input pin unless loopback mode is enabled." /> + <BitField start="5" size="1" name="DELTACTS" description="This bit is set when a change in the state is detected for the CTS flag above. This bit is cleared by software." /> + <BitField start="6" size="1" name="TXDISSTAT" description="Transmitter Disabled Interrupt flag. When 1, this bit indicates that the USART transmitter is fully idle after being disabled via the TXDIS in the CFG register (TXDIS = 1)." /> + <BitField start="7" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="8" size="1" name="OVERRUNINT" description="Overrun Error interrupt flag. This flag is set when a new character is received while the receiver buffer is still in use. If this occurs, the newly received character in the shift register is lost." /> + <BitField start="9" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="10" size="1" name="RXBRK" description="Received Break. This bit reflects the current state of the receiver break detection logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also be set when this condition occurs because the stop bit(s) for the character would be missing. RXBRK is cleared when the Un_RXD pin goes high." /> + <BitField start="11" size="1" name="DELTARXBRK" description="This bit is set when a change in the state of receiver break detection occurs. Cleared by software." /> + <BitField start="12" size="1" name="START" description="This bit is set when a start is detected on the receiver input. Its purpose is primarily to allow wake-up from Deep-sleep or Power-down mode immediately when a start is detected. Cleared by software." /> + <BitField start="13" size="1" name="FRAMERRINT" description="Framing Error interrupt flag. This flag is set when a character is received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source." /> + <BitField start="14" size="1" name="PARITYERRINT" description="Parity Error interrupt flag. This flag is set when a parity error is detected in a received character.." /> + <BitField start="15" size="1" name="RXNOISEINT" description="Received Noise interrupt flag. Three samples of received data are taken in order to determine the value of each received data bit, except in synchronous mode. This acts as a noise filter if one sample disagrees. This flag is set when a received data bit contains one disagreeing sample. This could indicate line noise, a baud rate or character format mismatch, or loss of synchronization during data reception." /> + <BitField start="16" size="1" name="ABERR" description="Auto-baud Error. An auto-baud error can occur if the BRG counts to its limit before the end of the start bit that is being measured, essentially an auto-baud time-out." /> + <BitField start="17" size="15" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x00C" size="4" name="INTENSET" access="Read/Write" description="Interrupt Enable read and Set register. Contains an individual interrupt enable bit for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RXRDYEN" description="When 1, enables an interrupt when there is a received character available to be read from the RXDAT register." /> + <BitField start="1" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="2" size="1" name="TXRDYEN" description="When 1, enables an interrupt when the TXDAT register is available to take another character to transmit." /> + <BitField start="3" size="1" name="TXIDLEEN" description="When 1, enables an interrupt when the transmitter becomes idle (TXIDLE = 1)." /> + <BitField start="4" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="5" size="1" name="DELTACTSEN" description="When 1, enables an interrupt when there is a change in the state of the CTS input." /> + <BitField start="6" size="1" name="TXDISEN" description="When 1, enables an interrupt when the transmitter is fully disabled as indicated by the TXDISINT flag in STAT. See description of the TXDISINT bit for details." /> + <BitField start="7" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="8" size="1" name="OVERRUNEN" description="When 1, enables an interrupt when an overrun error occurred." /> + <BitField start="9" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="11" size="1" name="DELTARXBRKEN" description="When 1, enables an interrupt when a change of state has occurred in the detection of a received break condition (break condition asserted or deasserted)." /> + <BitField start="12" size="1" name="STARTEN" description="When 1, enables an interrupt when a received start bit has been detected." /> + <BitField start="13" size="1" name="FRAMERREN" description="When 1, enables an interrupt when a framing error has been detected." /> + <BitField start="14" size="1" name="PARITYERREN" description="When 1, enables an interrupt when a parity error has been detected." /> + <BitField start="15" size="1" name="RXNOISEEN" description="When 1, enables an interrupt when noise is detected." /> + <BitField start="16" size="1" name="ABERREN" description="When 1, enables an interrupt when an auto-baud error occurs." /> + <BitField start="17" size="15" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x010" size="4" name="INTENCLR" access="WriteOnly" description="Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared." reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="RXRDYCLR" description="Writing 1 clears the corresponding bit in the INTENSET register." /> + <BitField start="1" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="2" size="1" name="TXRDYCLR" description="Writing 1 clears the corresponding bit in the INTENSET register." /> + <BitField start="3" size="1" name="TXIDLECLR" description="Writing 1 clears the corresponding bit in the INTENSET register." /> + <BitField start="4" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="5" size="1" name="DELTACTSCLR" description="Writing 1 clears the corresponding bit in the INTENSET register." /> + <BitField start="6" size="1" name="TXDISINTCLR" description="Writing 1 clears the corresponding bit in the INTENSET register." /> + <BitField start="7" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="8" size="1" name="OVERRUNCLR" description="Writing 1 clears the corresponding bit in the INTENSET register." /> + <BitField start="9" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="11" size="1" name="DELTARXBRKCLR" description="Writing 1 clears the corresponding bit in the INTENSET register." /> + <BitField start="12" size="1" name="STARTCLR" description="Writing 1 clears the corresponding bit in the INTENSET register." /> + <BitField start="13" size="1" name="FRAMERRCLR" description="Writing 1 clears the corresponding bit in the INTENSET register." /> + <BitField start="14" size="1" name="PARITYERRCLR" description="Writing 1 clears the corresponding bit in the INTENSET register." /> + <BitField start="15" size="1" name="RXNOISECLR" description="Writing 1 clears the corresponding bit in the INTENSET register." /> + <BitField start="16" size="1" name="ABERRCLR" description="Writing 1 clears the corresponding bit in the INTENSET register." /> + <BitField start="17" size="15" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x014" size="4" name="RXDAT" access="None" description="Receiver Data register. Contains the last character received." reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="9" name="RXDAT" description="The USART Receiver Data register contains the next received character. The number of bits that are relevant depends on the USART configuration settings." /> + <BitField start="9" size="23" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x018" size="4" name="RXDATSTAT" access="None" description="Receiver Data with Status register. Combines the last character received with the current USART receive status. Allows DMA or software to recover incoming data and status together." reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="9" name="RXDAT" description="The USART Receiver Data register contains the next received character. The number of bits that are relevant depends on the USART configuration settings." /> + <BitField start="9" size="4" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." /> + <BitField start="13" size="1" name="FRAMERR" description="Framing Error status flag. This bit is valid when there is a character to be read in the RXDAT register and reflects the status of that character. This bit will set when the character in RXDAT was received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source." /> + <BitField start="14" size="1" name="PARITYERR" description="Parity Error status flag. This bit is valid when there is a character to be read in the RXDAT register and reflects the status of that character. This bit will be set when a parity error is detected in a received character." /> + <BitField start="15" size="1" name="RXNOISE" description="Received Noise flag. See description of the RXNOISEINT bit in Table 133." /> + <BitField start="16" size="16" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x01C" size="4" name="TXDAT" access="Read/Write" description="Transmit Data register. Data to be transmitted is written here." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="9" name="TXDAT" description="Writing to the USART Transmit Data Register causes the data to be transmitted as soon as the transmit shift register is available and any conditions for transmitting data are met: CTS low (if CTSEN bit = 1), TXDIS bit = 0." /> + <BitField start="9" size="23" name="RESERVED" description="Reserved. Only zero should be written." /> + </Register> + <Register start="+0x020" size="4" name="BRG" access="Read/Write" description="Baud Rate Generator register. 16-bit integer baud rate divisor value." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="16" name="BRGVAL" description="This value is used to divide the USART input clock to determine the baud rate, based on the input clock from the FRG. 0 = The FRG clock is used directly by the USART function. 1 = The FRG clock is divided by 2 before use by the USART function. 2 = The FRG clock is divided by 3 before use by the USART function. ... 0xFFFF = The FRG clock is divided by 65,536 before use by the USART function." /> + <BitField start="16" size="16" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x024" size="4" name="INTSTAT" access="ReadOnly" description="Interrupt status register. Reflects interrupts that are currently enabled." reset_value="0x0005" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RXRDY" description="Receiver Ready flag." /> + <BitField start="1" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="2" size="1" name="TXRDY" description="Transmitter Ready flag." /> + <BitField start="3" size="1" name="TXIDLE" description="Transmitter idle status." /> + <BitField start="4" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="5" size="1" name="DELTACTS" description="This bit is set when a change in the state of the CTS input is detected." /> + <BitField start="6" size="1" name="TXDISINT" description="Transmitter Disabled Interrupt flag." /> + <BitField start="7" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="8" size="1" name="OVERRUNINT" description="Overrun Error interrupt flag." /> + <BitField start="9" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="11" size="1" name="DELTARXBRK" description="This bit is set when a change in the state of receiver break detection occurs." /> + <BitField start="12" size="1" name="START" description="This bit is set when a start is detected on the receiver input." /> + <BitField start="13" size="1" name="FRAMERRINT" description="Framing Error interrupt flag." /> + <BitField start="14" size="1" name="PARITYERRINT" description="Parity Error interrupt flag." /> + <BitField start="15" size="1" name="RXNOISEINT" description="Received Noise interrupt flag." /> + <BitField start="16" size="1" name="ABERR" description="Auto-baud Error flag." /> + <BitField start="17" size="15" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x028" size="4" name="OSR" access="Read/Write" description="Oversample selection register for asynchronous communication." reset_value="0xF" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="4" name="OSRVAL" description="Oversample Selection Value. 0 to 3 = not supported 0x4 = 5 peripheral clocks are used to transmit and receive each data bit. 0x5 = 6 peripheral clocks are used to transmit and receive each data bit. ... 0xF= 16 peripheral clocks are used to transmit and receive each data bit." /> + <BitField start="4" size="28" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x02C" size="4" name="ADDR" access="Read/Write" description="Address register for automatic address matching." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="ADDRESS" description="8-bit address used with automatic address matching. Used when address detection is enabled (ADDRDET in CTL = 1) and automatic address matching is enabled (AUTOADDR in CFG = 1)." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." /> + </Register> + </RegisterGroup> + <RegisterGroup name="SSP1" start="0x40058000" description="SSP1"> + <Register start="+0x000" size="4" name="CR0" access="Read/Write" description="Control Register 0. Selects the serial clock rate, bus type, and data size." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="4" name="DSS" description="Data Size Select. This field controls the number of bits transferred in each frame. Values 0000-0010 are not supported and should not be used."> + <Enum name="4_BIT_TRANSFER" start="0x3" description="4-bit transfer" /> + <Enum name="5_BIT_TRANSFER" start="0x4" description="5-bit transfer" /> + <Enum name="6_BIT_TRANSFER" start="0x5" description="6-bit transfer" /> + <Enum name="7_BIT_TRANSFER" start="0x6" description="7-bit transfer" /> + <Enum name="8_BIT_TRANSFER" start="0x7" description="8-bit transfer" /> + <Enum name="9_BIT_TRANSFER" start="0x8" description="9-bit transfer" /> + <Enum name="10_BIT_TRANSFER" start="0x9" description="10-bit transfer" /> + <Enum name="11_BIT_TRANSFER" start="0xA" description="11-bit transfer" /> + <Enum name="12_BIT_TRANSFER" start="0xB" description="12-bit transfer" /> + <Enum name="13_BIT_TRANSFER" start="0xC" description="13-bit transfer" /> + <Enum name="14_BIT_TRANSFER" start="0xD" description="14-bit transfer" /> + <Enum name="15_BIT_TRANSFER" start="0xE" description="15-bit transfer" /> + <Enum name="16_BIT_TRANSFER" start="0xF" description="16-bit transfer" /> + </BitField> + <BitField start="4" size="2" name="FRF" description="Frame Format."> + <Enum name="SPI" start="0x0" description="SPI" /> + <Enum name="TI" start="0x1" description="TI" /> + <Enum name="MICROWIRE" start="0x2" description="Microwire" /> + <Enum name="RESERVED" start="0x3" description="This combination is not supported and should not be used." /> + </BitField> + <BitField start="6" size="1" name="CPOL" description="Clock Out Polarity. This bit is only used in SPI mode."> + <Enum name="LOW" start="0" description="SPI controller maintains the bus clock low between frames." /> + <Enum name="HIGH" start="1" description="SPI controller maintains the bus clock high between frames." /> + </BitField> + <BitField start="7" size="1" name="CPHA" description="Clock Out Phase. This bit is only used in SPI mode."> + <Enum name="FIRSTCLOCK" start="0" description="SPI controller captures serial data on the first clock transition of the frame, that is, the transition away from the inter-frame state of the clock line." /> + <Enum name="SECONDCLOCK" start="1" description="SPI controller captures serial data on the second clock transition of the frame, that is, the transition back to the inter-frame state of the clock line." /> + </BitField> + <BitField start="8" size="8" name="SCR" description="Serial Clock Rate. The number of prescaler output clocks per bit on the bus, minus one. Given that CPSDVSR is the prescale divider, and the APB clock PCLK clocks the prescaler, the bit frequency is PCLK / (CPSDVSR X [SCR+1])." /> + <BitField start="16" size="16" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x004" size="4" name="CR1" access="Read/Write" description="Control Register 1. Selects master/slave and other modes." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="LBM" description="Loop Back Mode."> + <Enum name="DURING_NORMAL_OPERAT" start="0" description="During normal operation." /> + <Enum name="SERIAL_INPUT_IS_TAKE" start="1" description="Serial input is taken from the serial output (MOSI or MISO) rather than the serial input pin (MISO or MOSI respectively)." /> + </BitField> + <BitField start="1" size="1" name="SSE" description="SPI Enable."> + <Enum name="DISABLED" start="0" description="The SPI controller is disabled." /> + <Enum name="ENABLED" start="1" description="The SPI controller will interact with other devices on the serial bus. Software should write the appropriate control information to the other SSP/SPI registers and interrupt controller registers, before setting this bit." /> + </BitField> + <BitField start="2" size="1" name="MS" description="Master/Slave Mode.This bit can only be written when the SSE bit is 0."> + <Enum name="MASTER" start="0" description="The SPI controller acts as a master on the bus, driving the SCLK, MOSI, and SSEL lines and receiving the MISO line." /> + <Enum name="SLAVE" start="1" description="The SPI controller acts as a slave on the bus, driving MISO line and receiving SCLK, MOSI, and SSEL lines." /> + </BitField> + <BitField start="3" size="1" name="SOD" description="Slave Output Disable. This bit is relevant only in slave mode (MS = 1). If it is 1, this blocks this SPI controller from driving the transmit data line (MISO)." /> + <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x008" size="4" name="DR" access="None" description="Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="16" name="DATA" description="Write: software can write data to be sent in a future frame to this register whenever the TNF bit in the Status register is 1, indicating that the Tx FIFO is not full. If the Tx FIFO was previously empty and the SPI controller is not busy on the bus, transmission of the data will begin immediately. Otherwise the data written to this register will be sent as soon as all previous data has been sent (and received). If the data length is less than 16 bit, software must right-justify the data written to this register. Read: software can read data from this register whenever the RNE bit in the Status register is 1, indicating that the Rx FIFO is not empty. When software reads this register, the SPI controller returns data from the least recent frame in the Rx FIFO. If the data length is less than 16 bit, the data is right-justified in this field with higher order bits filled with 0s." /> + <BitField start="16" size="16" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x00C" size="4" name="SR" access="ReadOnly" description="Status Register" reset_value="0x00000003" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="TFE" description="Transmit FIFO Empty. This bit is 1 is the Transmit FIFO is empty, 0 if not." /> + <BitField start="1" size="1" name="TNF" description="Transmit FIFO Not Full. This bit is 0 if the Tx FIFO is full, 1 if not." /> + <BitField start="2" size="1" name="RNE" description="Receive FIFO Not Empty. This bit is 0 if the Receive FIFO is empty, 1 if not." /> + <BitField start="3" size="1" name="RFF" description="Receive FIFO Full. This bit is 1 if the Receive FIFO is full, 0 if not." /> + <BitField start="4" size="1" name="BSY" description="Busy. This bit is 0 if the SPI controller is idle, 1 if it is currently sending/receiving a frame and/or the Tx FIFO is not empty." /> + <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x010" size="4" name="CPSR" access="Read/Write" description="Clock Prescale Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="CPSDVSR" description="This even value between 2 and 254, by which SPI_PCLK is divided to yield the prescaler output clock. Bit 0 always reads as 0." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x014" size="4" name="IMSC" access="Read/Write" description="Interrupt Mask Set and Clear Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RORIM" description="Software should set this bit to enable interrupt when a Receive Overrun occurs, that is, when the Rx FIFO is full and another frame is completely received. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs." /> + <BitField start="1" size="1" name="RTIM" description="Software should set this bit to enable interrupt when a Receive Time-out condition occurs. A Receive Time-out occurs when the Rx FIFO is not empty, and no has not been read for a time-out period. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1])." /> + <BitField start="2" size="1" name="RXIM" description="Software should set this bit to enable interrupt when the Rx FIFO is at least half full." /> + <BitField start="3" size="1" name="TXIM" description="Software should set this bit to enable interrupt when the Tx FIFO is at least half empty." /> + <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x018" size="4" name="RIS" access="ReadOnly" description="Raw Interrupt Status Register" reset_value="0x00000008" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RORRIS" description="This bit is 1 if another frame was completely received while the RxFIFO was full. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs." /> + <BitField start="1" size="1" name="RTRIS" description="This bit is 1 if the Rx FIFO is not empty, and has not been read for a time-out period. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1])." /> + <BitField start="2" size="1" name="RXRIS" description="This bit is 1 if the Rx FIFO is at least half full." /> + <BitField start="3" size="1" name="TXRIS" description="This bit is 1 if the Tx FIFO is at least half empty." /> + <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x01C" size="4" name="MIS" access="ReadOnly" description="Masked Interrupt Status Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RORMIS" description="This bit is 1 if another frame was completely received while the RxFIFO was full, and this interrupt is enabled." /> + <BitField start="1" size="1" name="RTMIS" description="This bit is 1 if the Rx FIFO is not empty, has not been read for a time-out period, and this interrupt is enabled. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1])." /> + <BitField start="2" size="1" name="RXMIS" description="This bit is 1 if the Rx FIFO is at least half full, and this interrupt is enabled." /> + <BitField start="3" size="1" name="TXMIS" description="This bit is 1 if the Tx FIFO is at least half empty, and this interrupt is enabled." /> + <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x020" size="4" name="ICR" access="WriteOnly" description="SSPICR Interrupt Clear Register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="RORIC" description="Writing a 1 to this bit clears the frame was received when RxFIFO was full interrupt." /> + <BitField start="1" size="1" name="RTIC" description="Writing a 1 to this bit clears the Rx FIFO was not empty and has not been read for a timeout period interrupt. The timeout period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1])." /> + <BitField start="2" size="30" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + </RegisterGroup> + <RegisterGroup name="GINT0" start="0x4005C000" description="GPIO group interrupt 0"> + <Register start="+0x000" size="4" name="CTRL" access="Read/Write" description="GPIO grouped interrupt control register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="INT" description="Group interrupt status. This bit is cleared by writing a one to it. Writing zero has no effect."> + <Enum name="NO_INTERRUPT_REQUEST" start="0" description="No interrupt request is pending." /> + <Enum name="INTERRUPT_REQUEST_IS" start="1" description="Interrupt request is active." /> + </BitField> + <BitField start="1" size="1" name="COMB" description="Combine enabled inputs for group interrupt"> + <Enum name="OR_FUNCTIONALITY_A_" start="0" description="OR functionality: A grouped interrupt is generated when any one of the enabled inputs is active (based on its programmed polarity)." /> + <Enum name="AND_FUNCTIONALITY_A" start="1" description="AND functionality: An interrupt is generated when all enabled bits are active (based on their programmed polarity)." /> + </BitField> + <BitField start="2" size="1" name="TRIG" description="Group interrupt trigger"> + <Enum name="EDGE_TRIGGERED" start="0" description="Edge-triggered" /> + <Enum name="LEVEL_TRIGGERED" start="1" description="Level-triggered" /> + </BitField> + <BitField start="3" size="29" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x020+0" size="4" name="PORT_POL[0]" access="Read/Write" description="GPIO grouped interrupt port 0 polarity register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="POL0" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="1" size="1" name="POL1" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="2" size="1" name="POL2" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="3" size="1" name="POL3" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="4" size="1" name="POL4" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="5" size="1" name="POL5" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="6" size="1" name="POL6" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="7" size="1" name="POL7" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="8" size="1" name="POL8" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="9" size="1" name="POL9" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="10" size="1" name="POL10" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="11" size="1" name="POL11" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="12" size="1" name="POL12" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="13" size="1" name="POL13" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="14" size="1" name="POL14" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="15" size="1" name="POL15" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="16" size="1" name="POL16" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="17" size="1" name="POL17" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="18" size="1" name="POL18" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="19" size="1" name="POL19" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="20" size="1" name="POL20" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="21" size="1" name="POL21" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="22" size="1" name="POL22" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="23" size="1" name="POL23" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="24" size="1" name="POL24" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="25" size="1" name="POL25" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="26" size="1" name="POL26" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="27" size="1" name="POL27" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="28" size="1" name="POL28" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="29" size="1" name="POL29" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="30" size="1" name="POL30" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="31" size="1" name="POL31" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + </Register> + <Register start="+0x020+4" size="4" name="PORT_POL[1]" access="Read/Write" description="GPIO grouped interrupt port 0 polarity register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="POL0" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="1" size="1" name="POL1" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="2" size="1" name="POL2" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="3" size="1" name="POL3" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="4" size="1" name="POL4" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="5" size="1" name="POL5" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="6" size="1" name="POL6" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="7" size="1" name="POL7" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="8" size="1" name="POL8" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="9" size="1" name="POL9" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="10" size="1" name="POL10" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="11" size="1" name="POL11" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="12" size="1" name="POL12" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="13" size="1" name="POL13" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="14" size="1" name="POL14" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="15" size="1" name="POL15" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="16" size="1" name="POL16" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="17" size="1" name="POL17" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="18" size="1" name="POL18" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="19" size="1" name="POL19" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="20" size="1" name="POL20" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="21" size="1" name="POL21" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="22" size="1" name="POL22" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="23" size="1" name="POL23" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="24" size="1" name="POL24" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="25" size="1" name="POL25" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="26" size="1" name="POL26" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="27" size="1" name="POL27" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="28" size="1" name="POL28" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="29" size="1" name="POL29" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="30" size="1" name="POL30" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="31" size="1" name="POL31" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + </Register> + <Register start="+0x020+8" size="4" name="PORT_POL[2]" access="Read/Write" description="GPIO grouped interrupt port 0 polarity register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="POL0" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="1" size="1" name="POL1" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="2" size="1" name="POL2" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="3" size="1" name="POL3" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="4" size="1" name="POL4" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="5" size="1" name="POL5" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="6" size="1" name="POL6" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="7" size="1" name="POL7" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="8" size="1" name="POL8" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="9" size="1" name="POL9" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="10" size="1" name="POL10" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="11" size="1" name="POL11" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="12" size="1" name="POL12" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="13" size="1" name="POL13" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="14" size="1" name="POL14" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="15" size="1" name="POL15" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="16" size="1" name="POL16" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="17" size="1" name="POL17" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="18" size="1" name="POL18" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="19" size="1" name="POL19" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="20" size="1" name="POL20" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="21" size="1" name="POL21" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="22" size="1" name="POL22" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="23" size="1" name="POL23" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="24" size="1" name="POL24" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="25" size="1" name="POL25" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="26" size="1" name="POL26" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="27" size="1" name="POL27" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="28" size="1" name="POL28" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="29" size="1" name="POL29" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="30" size="1" name="POL30" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="31" size="1" name="POL31" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + </Register> + <Register start="+0x040+0" size="4" name="PORT_ENA[0]" access="Read/Write" description="GPIO grouped interrupt port enable register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="ENA0" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="1" size="1" name="ENA1" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="2" size="1" name="ENA2" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="3" size="1" name="ENA3" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="4" size="1" name="ENA4" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="5" size="1" name="ENA5" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="6" size="1" name="ENA6" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="7" size="1" name="ENA7" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="8" size="1" name="ENA8" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="9" size="1" name="ENA9" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="10" size="1" name="ENA10" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="11" size="1" name="ENA11" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="12" size="1" name="ENA12" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="13" size="1" name="ENA13" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="14" size="1" name="ENA14" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="15" size="1" name="ENA15" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="16" size="1" name="ENA16" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="17" size="1" name="ENA17" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="18" size="1" name="ENA18" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="19" size="1" name="ENA19" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="20" size="1" name="ENA20" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="21" size="1" name="ENA21" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="22" size="1" name="ENA22" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="23" size="1" name="ENA23" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="24" size="1" name="ENA24" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="25" size="1" name="ENA25" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="26" size="1" name="ENA26" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="27" size="1" name="ENA27" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="28" size="1" name="ENA28" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="29" size="1" name="ENA29" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="30" size="1" name="ENA30" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="31" size="1" name="ENA31" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." /> + </Register> + <Register start="+0x040+4" size="4" name="PORT_ENA[1]" access="Read/Write" description="GPIO grouped interrupt port enable register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="ENA0" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="1" size="1" name="ENA1" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="2" size="1" name="ENA2" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="3" size="1" name="ENA3" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="4" size="1" name="ENA4" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="5" size="1" name="ENA5" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="6" size="1" name="ENA6" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="7" size="1" name="ENA7" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="8" size="1" name="ENA8" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="9" size="1" name="ENA9" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="10" size="1" name="ENA10" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="11" size="1" name="ENA11" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="12" size="1" name="ENA12" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="13" size="1" name="ENA13" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="14" size="1" name="ENA14" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="15" size="1" name="ENA15" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="16" size="1" name="ENA16" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="17" size="1" name="ENA17" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="18" size="1" name="ENA18" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="19" size="1" name="ENA19" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="20" size="1" name="ENA20" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="21" size="1" name="ENA21" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="22" size="1" name="ENA22" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="23" size="1" name="ENA23" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="24" size="1" name="ENA24" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="25" size="1" name="ENA25" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="26" size="1" name="ENA26" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="27" size="1" name="ENA27" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="28" size="1" name="ENA28" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="29" size="1" name="ENA29" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="30" size="1" name="ENA30" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="31" size="1" name="ENA31" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." /> + </Register> + <Register start="+0x040+8" size="4" name="PORT_ENA[2]" access="Read/Write" description="GPIO grouped interrupt port enable register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="ENA0" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="1" size="1" name="ENA1" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="2" size="1" name="ENA2" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="3" size="1" name="ENA3" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="4" size="1" name="ENA4" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="5" size="1" name="ENA5" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="6" size="1" name="ENA6" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="7" size="1" name="ENA7" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="8" size="1" name="ENA8" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="9" size="1" name="ENA9" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="10" size="1" name="ENA10" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="11" size="1" name="ENA11" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="12" size="1" name="ENA12" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="13" size="1" name="ENA13" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="14" size="1" name="ENA14" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="15" size="1" name="ENA15" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="16" size="1" name="ENA16" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="17" size="1" name="ENA17" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="18" size="1" name="ENA18" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="19" size="1" name="ENA19" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="20" size="1" name="ENA20" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="21" size="1" name="ENA21" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="22" size="1" name="ENA22" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="23" size="1" name="ENA23" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="24" size="1" name="ENA24" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="25" size="1" name="ENA25" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="26" size="1" name="ENA26" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="27" size="1" name="ENA27" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="28" size="1" name="ENA28" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="29" size="1" name="ENA29" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="30" size="1" name="ENA30" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="31" size="1" name="ENA31" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." /> + </Register> + </RegisterGroup> + <RegisterGroup name="GINT1" start="0x40060000" description="GINT1"> + <Register start="+0x000" size="4" name="CTRL" access="Read/Write" description="GPIO grouped interrupt control register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="INT" description="Group interrupt status. This bit is cleared by writing a one to it. Writing zero has no effect."> + <Enum name="NO_INTERRUPT_REQUEST" start="0" description="No interrupt request is pending." /> + <Enum name="INTERRUPT_REQUEST_IS" start="1" description="Interrupt request is active." /> + </BitField> + <BitField start="1" size="1" name="COMB" description="Combine enabled inputs for group interrupt"> + <Enum name="OR_FUNCTIONALITY_A_" start="0" description="OR functionality: A grouped interrupt is generated when any one of the enabled inputs is active (based on its programmed polarity)." /> + <Enum name="AND_FUNCTIONALITY_A" start="1" description="AND functionality: An interrupt is generated when all enabled bits are active (based on their programmed polarity)." /> + </BitField> + <BitField start="2" size="1" name="TRIG" description="Group interrupt trigger"> + <Enum name="EDGE_TRIGGERED" start="0" description="Edge-triggered" /> + <Enum name="LEVEL_TRIGGERED" start="1" description="Level-triggered" /> + </BitField> + <BitField start="3" size="29" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x020+0" size="4" name="PORT_POL[0]" access="Read/Write" description="GPIO grouped interrupt port 0 polarity register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="POL0" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="1" size="1" name="POL1" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="2" size="1" name="POL2" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="3" size="1" name="POL3" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="4" size="1" name="POL4" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="5" size="1" name="POL5" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="6" size="1" name="POL6" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="7" size="1" name="POL7" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="8" size="1" name="POL8" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="9" size="1" name="POL9" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="10" size="1" name="POL10" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="11" size="1" name="POL11" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="12" size="1" name="POL12" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="13" size="1" name="POL13" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="14" size="1" name="POL14" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="15" size="1" name="POL15" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="16" size="1" name="POL16" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="17" size="1" name="POL17" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="18" size="1" name="POL18" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="19" size="1" name="POL19" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="20" size="1" name="POL20" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="21" size="1" name="POL21" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="22" size="1" name="POL22" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="23" size="1" name="POL23" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="24" size="1" name="POL24" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="25" size="1" name="POL25" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="26" size="1" name="POL26" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="27" size="1" name="POL27" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="28" size="1" name="POL28" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="29" size="1" name="POL29" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="30" size="1" name="POL30" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="31" size="1" name="POL31" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + </Register> + <Register start="+0x020+4" size="4" name="PORT_POL[1]" access="Read/Write" description="GPIO grouped interrupt port 0 polarity register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="POL0" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="1" size="1" name="POL1" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="2" size="1" name="POL2" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="3" size="1" name="POL3" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="4" size="1" name="POL4" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="5" size="1" name="POL5" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="6" size="1" name="POL6" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="7" size="1" name="POL7" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="8" size="1" name="POL8" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="9" size="1" name="POL9" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="10" size="1" name="POL10" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="11" size="1" name="POL11" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="12" size="1" name="POL12" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="13" size="1" name="POL13" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="14" size="1" name="POL14" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="15" size="1" name="POL15" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="16" size="1" name="POL16" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="17" size="1" name="POL17" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="18" size="1" name="POL18" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="19" size="1" name="POL19" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="20" size="1" name="POL20" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="21" size="1" name="POL21" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="22" size="1" name="POL22" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="23" size="1" name="POL23" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="24" size="1" name="POL24" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="25" size="1" name="POL25" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="26" size="1" name="POL26" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="27" size="1" name="POL27" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="28" size="1" name="POL28" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="29" size="1" name="POL29" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="30" size="1" name="POL30" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="31" size="1" name="POL31" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + </Register> + <Register start="+0x020+8" size="4" name="PORT_POL[2]" access="Read/Write" description="GPIO grouped interrupt port 0 polarity register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="POL0" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="1" size="1" name="POL1" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="2" size="1" name="POL2" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="3" size="1" name="POL3" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="4" size="1" name="POL4" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="5" size="1" name="POL5" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="6" size="1" name="POL6" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="7" size="1" name="POL7" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="8" size="1" name="POL8" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="9" size="1" name="POL9" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="10" size="1" name="POL10" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="11" size="1" name="POL11" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="12" size="1" name="POL12" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="13" size="1" name="POL13" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="14" size="1" name="POL14" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="15" size="1" name="POL15" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="16" size="1" name="POL16" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="17" size="1" name="POL17" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="18" size="1" name="POL18" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="19" size="1" name="POL19" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="20" size="1" name="POL20" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="21" size="1" name="POL21" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="22" size="1" name="POL22" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="23" size="1" name="POL23" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="24" size="1" name="POL24" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="25" size="1" name="POL25" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="26" size="1" name="POL26" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="27" size="1" name="POL27" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="28" size="1" name="POL28" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="29" size="1" name="POL29" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="30" size="1" name="POL30" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="31" size="1" name="POL31" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + </Register> + <Register start="+0x040+0" size="4" name="PORT_ENA[0]" access="Read/Write" description="GPIO grouped interrupt port enable register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="ENA0" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="1" size="1" name="ENA1" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="2" size="1" name="ENA2" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="3" size="1" name="ENA3" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="4" size="1" name="ENA4" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="5" size="1" name="ENA5" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="6" size="1" name="ENA6" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="7" size="1" name="ENA7" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="8" size="1" name="ENA8" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="9" size="1" name="ENA9" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="10" size="1" name="ENA10" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="11" size="1" name="ENA11" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="12" size="1" name="ENA12" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="13" size="1" name="ENA13" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="14" size="1" name="ENA14" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="15" size="1" name="ENA15" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="16" size="1" name="ENA16" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="17" size="1" name="ENA17" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="18" size="1" name="ENA18" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="19" size="1" name="ENA19" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="20" size="1" name="ENA20" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="21" size="1" name="ENA21" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="22" size="1" name="ENA22" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="23" size="1" name="ENA23" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="24" size="1" name="ENA24" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="25" size="1" name="ENA25" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="26" size="1" name="ENA26" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="27" size="1" name="ENA27" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="28" size="1" name="ENA28" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="29" size="1" name="ENA29" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="30" size="1" name="ENA30" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="31" size="1" name="ENA31" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." /> + </Register> + <Register start="+0x040+4" size="4" name="PORT_ENA[1]" access="Read/Write" description="GPIO grouped interrupt port enable register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="ENA0" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="1" size="1" name="ENA1" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="2" size="1" name="ENA2" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="3" size="1" name="ENA3" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="4" size="1" name="ENA4" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="5" size="1" name="ENA5" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="6" size="1" name="ENA6" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="7" size="1" name="ENA7" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="8" size="1" name="ENA8" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="9" size="1" name="ENA9" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="10" size="1" name="ENA10" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="11" size="1" name="ENA11" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="12" size="1" name="ENA12" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="13" size="1" name="ENA13" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="14" size="1" name="ENA14" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="15" size="1" name="ENA15" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="16" size="1" name="ENA16" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="17" size="1" name="ENA17" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="18" size="1" name="ENA18" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="19" size="1" name="ENA19" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="20" size="1" name="ENA20" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="21" size="1" name="ENA21" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="22" size="1" name="ENA22" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="23" size="1" name="ENA23" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="24" size="1" name="ENA24" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="25" size="1" name="ENA25" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="26" size="1" name="ENA26" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="27" size="1" name="ENA27" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="28" size="1" name="ENA28" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="29" size="1" name="ENA29" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="30" size="1" name="ENA30" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="31" size="1" name="ENA31" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." /> + </Register> + <Register start="+0x040+8" size="4" name="PORT_ENA[2]" access="Read/Write" description="GPIO grouped interrupt port enable register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="ENA0" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="1" size="1" name="ENA1" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="2" size="1" name="ENA2" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="3" size="1" name="ENA3" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="4" size="1" name="ENA4" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="5" size="1" name="ENA5" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="6" size="1" name="ENA6" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="7" size="1" name="ENA7" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="8" size="1" name="ENA8" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="9" size="1" name="ENA9" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="10" size="1" name="ENA10" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="11" size="1" name="ENA11" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="12" size="1" name="ENA12" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="13" size="1" name="ENA13" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="14" size="1" name="ENA14" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="15" size="1" name="ENA15" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="16" size="1" name="ENA16" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="17" size="1" name="ENA17" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="18" size="1" name="ENA18" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="19" size="1" name="ENA19" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="20" size="1" name="ENA20" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="21" size="1" name="ENA21" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="22" size="1" name="ENA22" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="23" size="1" name="ENA23" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="24" size="1" name="ENA24" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="25" size="1" name="ENA25" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="26" size="1" name="ENA26" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="27" size="1" name="ENA27" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="28" size="1" name="ENA28" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="29" size="1" name="ENA29" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="30" size="1" name="ENA30" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="31" size="1" name="ENA31" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." /> + </Register> + </RegisterGroup> + <RegisterGroup name="USART1" start="0x4006C000" description="USART1"> + <Register start="+0x000" size="4" name="CFG" access="Read/Write" description="USART Configuration register. Basic USART configuration settings that typically are not changed during operation." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="ENABLE" description="USART Enable."> + <Enum name="DISABLED" start="0" description="Disabled. The USART is disabled and the internal state machine and counters are reset. While Enable = 0, all USART interrupts and DMA transfers are disabled. When Enable is set again, CFG and most other control bits remain unchanged. For instance, when re-enabled, the USART will immediately generate a TxRdy interrupt (if enabled in the INTENSET register) or a DMA transfer request because the transmitter has been reset and is therefore available." /> + <Enum name="ENABLED" start="1" description="Enabled. The USART is enabled for operation." /> + </BitField> + <BitField start="1" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="2" size="2" name="DATALEN" description="Selects the data size for the USART."> + <Enum name="7_BIT_DATA_LENGTH" start="0x0" description="7 bit Data length." /> + <Enum name="8_BIT_DATA_LENGTH" start="0x1" description="8 bit Data length." /> + <Enum name="9_BIT_DATA_LENGTH" start="0x2" description="9 bit data length. The 9th bit is commonly used for addressing in multidrop mode. See the ADDRDET bit in the CTL register." /> + <Enum name="RESERVED" start="0x3" description="Reserved." /> + </BitField> + <BitField start="4" size="2" name="PARITYSEL" description="Selects what type of parity is used by the USART."> + <Enum name="NO_PARITY" start="0x0" description="No parity." /> + <Enum name="RESERVED" start="0x1" description="Reserved." /> + <Enum name="EVEN_PARITY" start="0x2" description="Even parity. Adds a bit to each character such that the number of 1s in a transmitted character is even, and the number of 1s in a received character is expected to be even." /> + <Enum name="ODD_PARITY" start="0x3" description="Odd parity. Adds a bit to each character such that the number of 1s in a transmitted character is odd, and the number of 1s in a received character is expected to be odd." /> + </BitField> + <BitField start="6" size="1" name="STOPLEN" description="Number of stop bits appended to transmitted data. Only a single stop bit is required for received data."> + <Enum name="1_STOP_BIT" start="0" description="1 stop bit." /> + <Enum name="2_STOP_BITS" start="1" description="2 stop bits. This setting should only be used for asynchronous communication." /> + </BitField> + <BitField start="7" size="1" name="MODE32K" description="Selects standard or 32 kHz clocking mode."> + <Enum name="STANDARD" start="0" description="UART uses standard clocking." /> + <Enum name="32KHZ" start="1" description="UART uses the 32 kHz clock from the RTC oscillator as the clock source to the BRG, and uses a special bit clocking scheme." /> + </BitField> + <BitField start="8" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="9" size="1" name="CTSEN" description="CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin, or from the USART's own RTS if loopback mode is enabled. See Section 11.8.4 for more information."> + <Enum name="NO_FLOW_CONTROL" start="0" description="No flow control. The transmitter does not receive any automatic flow control signal." /> + <Enum name="FLOW_CONTROL_ENABLED" start="1" description="Flow control enabled. The transmitter uses the CTS input (or RTS output in loopback mode) for flow control purposes." /> + </BitField> + <BitField start="10" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="11" size="1" name="SYNCEN" description="Selects synchronous or asynchronous operation."> + <Enum name="ASYNCHRONOUS" start="0" description="Asynchronous mode is selected." /> + <Enum name="SYNCHRONOUS" start="1" description="Synchronous mode is selected." /> + </BitField> + <BitField start="12" size="1" name="CLKPOL" description="Selects the clock polarity and sampling edge of received data in synchronous mode."> + <Enum name="FALLING_EDGE" start="0" description="Falling edge. Un_RXD is sampled on the falling edge of SCLK." /> + <Enum name="RISING_EDGE" start="1" description="Rising edge. Un_RXD is sampled on the rising edge of SCLK." /> + </BitField> + <BitField start="13" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="14" size="1" name="SYNCMST" description="Synchronous mode Master select."> + <Enum name="SLAVE" start="0" description="Slave. When synchronous mode is enabled, the USART is a slave." /> + <Enum name="MASTER" start="1" description="Master. When synchronous mode is enabled, the USART is a master." /> + </BitField> + <BitField start="15" size="1" name="LOOP" description="Selects data loopback mode."> + <Enum name="NORMAL_OPERATION" start="0" description="Normal operation." /> + <Enum name="LOOPBACK_MODE" start="1" description="Loopback mode. This provides a mechanism to perform diagnostic loopback testing for USART data. Serial data from the transmitter (Un_TXD) is connected internally to serial input of the receive (Un_RXD). Un_TXD and Un_RTS activity will also appear on external pins if these functions are configured to appear on device pins. The receiver RTS signal is also looped back to CTS and performs flow control if enabled by CTSEN." /> + </BitField> + <BitField start="16" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="18" size="1" name="OETA" description="Output Enable Turnaround time enable for RS-485 operation."> + <Enum name="DEASSERTED" start="0" description="Deasserted. If selected by OESEL, the Output Enable signal deasserted at the end of the last stop bit of a transmission." /> + <Enum name="ASSERTED" start="1" description="Asserted. If selected by OESEL, the Output Enable signal remains asserted for 1 character time after then end the last stop bit of a transmission. OE will also remain asserted if another transmit begins before it is deasserted." /> + </BitField> + <BitField start="19" size="1" name="AUTOADDR" description="Automatic Address matching enable."> + <Enum name="DISABLED" start="0" description="Disabled. When addressing is enabled by ADDRDET, address matching is done by software. This provides the possibility of versatile addressing (e.g. respond to more than one address)." /> + <Enum name="ENABLED" start="1" description="Enabled. When addressing is enabled by ADDRDET, address matching is done by hardware, using the value in the ADDR register as the address to match." /> + </BitField> + <BitField start="20" size="1" name="OESEL" description="Output Enable Select."> + <Enum name="FLOW_CONTROL" start="0" description="Flow control. The RTS signal is used as the standard flow control function." /> + <Enum name="OUTPUT_ENABLE" start="1" description="Output enable. The RTS signal is taken over in order to provide an output enable signal to control an RS-485 transceiver." /> + </BitField> + <BitField start="21" size="1" name="OEPOL" description="Output Enable Polarity."> + <Enum name="LOW" start="0" description="Low. If selected by OESEL, the output enable is active low." /> + <Enum name="HIGH" start="1" description="High. If selected by OESEL, the output enable is active high." /> + </BitField> + <BitField start="22" size="1" name="RXPOL" description="Receive data polarity."> + <Enum name="NOT_CHANGED" start="0" description="Not changed. The RX signal is used as it arrives from the pin. This means that the RX rest value is 1, start bit is 0, data is not inverted, and the stop bit is 1." /> + <Enum name="INVERTED" start="1" description="Inverted. The RX signal is inverted before being used by the UART. This means that the RX rest value is 0, start bit is 1, data is inverted, and the stop bit is 0." /> + </BitField> + <BitField start="23" size="1" name="TXPOL" description="Transmit data polarity."> + <Enum name="NOT_CHANGED" start="0" description="Not changed. The TX signal is sent out without change. This means that the TX rest value is 1, start bit is 0, data is not inverted, and the stop bit is 1." /> + <Enum name="INVERTED" start="1" description="Inverted. The TX signal is inverted by the UART before being sent out. This means that the TX rest value is 0, start bit is 1, data is inverted, and the stop bit is 0." /> + </BitField> + <BitField start="24" size="8" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x004" size="4" name="CTL" access="Read/Write" description="USART Control register. USART control settings that are more likely to change during operation." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="1" size="1" name="TXBRKEN" description="Break Enable."> + <Enum name="NORMAL_OPERATION" start="0" description="Normal operation." /> + <Enum name="CONTINUOUS_BREAK_IS" start="1" description="Continuous break is sent immediately when this bit is set, and remains until this bit is cleared. A break may be sent without danger of corrupting any currently transmitting character if the transmitter is first disabled (TXDIS in CTL is set) and then waiting for the transmitter to be disabled (TXDISINT in STAT = 1) before writing 1 to TXBRKEN." /> + </BitField> + <BitField start="2" size="1" name="ADDRDET" description="Enable address detect mode."> + <Enum name="DISABLED" start="0" description="Disabled. The USART presents all incoming data." /> + <Enum name="ENABLED" start="1" description="Enabled. The USART receiver ignores incoming data that does not have the most significant bit of the data (typically the 9th bit) = 1. When the data MSB bit = 1, the receiver treats the incoming data normally, generating a received data interrupt. Software can then check the data to see if this is an address that should be handled. If it is, the ADDRDET bit is cleared by software and further incoming data is handled normally." /> + </BitField> + <BitField start="3" size="3" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="6" size="1" name="TXDIS" description="Transmit Disable."> + <Enum name="NOT_DISABLED" start="0" description="Not disabled. USART transmitter is not disabled." /> + <Enum name="DISABLED" start="1" description="Disabled. USART transmitter is disabled after any character currently being transmitted is complete. This feature can be used to facilitate software flow control." /> + </BitField> + <BitField start="7" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="8" size="1" name="CC" description="Continuous Clock generation. By default, SCLK is only output while data is being transmitted in synchronous mode."> + <Enum name="CLOCK_ON_CHARACTER" start="0" description="Clock on character. In synchronous mode, SCLK cycles only when characters are being sent on Un_TXD or to complete a character that is being received." /> + <Enum name="CONTINUOUS_CLOCK" start="1" description="Continuous clock. SCLK runs continuously in synchronous mode, allowing characters to be received on Un_RxD independently from transmission on Un_TXD)." /> + </BitField> + <BitField start="9" size="1" name="CLRCCONRX" description="Clear Continuous Clock."> + <Enum name="NO_EFFECT" start="0" description="No effect on the CC bit." /> + <Enum name="AUTO_CLEAR" start="1" description="Auto-clear. The CC bit is automatically cleared when a complete character has been received. This bit is cleared at the same time." /> + </BitField> + <BitField start="10" size="6" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="16" size="1" name="AUTOBAUD" description="Autobaud enable."> + <Enum name="DISABLED" start="0" description="Disabled. UART is in normal operating mode." /> + <Enum name="ENABLED" start="1" description="Enabled. UART is in autobaud mode. This bit should only be set when the UART receiver is idle. The first start bit of RX is measured and used the update the BRG register to match the received data rate. AUTOBAUD is cleared once this process is complete, or if there is an AERR. This bit can be cleared by software when set, but only when the UART receiver is idle." /> + </BitField> + <BitField start="17" size="15" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x008" size="4" name="STAT" access="Read/Write" description="USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them." reset_value="0x000E" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RXRDY" description="Receiver Ready flag. When 1, indicates that data is available to be read from the receiver buffer. Cleared after a read of the RXDAT or RXDATSTAT registers." /> + <BitField start="1" size="1" name="RXIDLE" description="Receiver Idle. When 0, indicates that the receiver is currently in the process of receiving data. When 1, indicates that the receiver is not currently in the process of receiving data." /> + <BitField start="2" size="1" name="TXRDY" description="Transmitter Ready flag. When 1, this bit indicates that data may be written to the transmit buffer. Previous data may still be in the process of being transmitted. Cleared when data is written to TXDAT. Set when the data is moved from the transmit buffer to the transmit shift register." /> + <BitField start="3" size="1" name="TXIDLE" description="Transmitter Idle. When 0, indicates that the transmitter is currently in the process of sending data.When 1, indicate that the transmitter is not currently in the process of sending data." /> + <BitField start="4" size="1" name="CTS" description="This bit reflects the current state of the CTS signal, regardless of the setting of the CTSEN bit in the CFG register. This will be the value of the CTS input pin unless loopback mode is enabled." /> + <BitField start="5" size="1" name="DELTACTS" description="This bit is set when a change in the state is detected for the CTS flag above. This bit is cleared by software." /> + <BitField start="6" size="1" name="TXDISSTAT" description="Transmitter Disabled Interrupt flag. When 1, this bit indicates that the USART transmitter is fully idle after being disabled via the TXDIS in the CFG register (TXDIS = 1)." /> + <BitField start="7" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="8" size="1" name="OVERRUNINT" description="Overrun Error interrupt flag. This flag is set when a new character is received while the receiver buffer is still in use. If this occurs, the newly received character in the shift register is lost." /> + <BitField start="9" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="10" size="1" name="RXBRK" description="Received Break. This bit reflects the current state of the receiver break detection logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also be set when this condition occurs because the stop bit(s) for the character would be missing. RXBRK is cleared when the Un_RXD pin goes high." /> + <BitField start="11" size="1" name="DELTARXBRK" description="This bit is set when a change in the state of receiver break detection occurs. Cleared by software." /> + <BitField start="12" size="1" name="START" description="This bit is set when a start is detected on the receiver input. Its purpose is primarily to allow wake-up from Deep-sleep or Power-down mode immediately when a start is detected. Cleared by software." /> + <BitField start="13" size="1" name="FRAMERRINT" description="Framing Error interrupt flag. This flag is set when a character is received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source." /> + <BitField start="14" size="1" name="PARITYERRINT" description="Parity Error interrupt flag. This flag is set when a parity error is detected in a received character.." /> + <BitField start="15" size="1" name="RXNOISEINT" description="Received Noise interrupt flag. Three samples of received data are taken in order to determine the value of each received data bit, except in synchronous mode. This acts as a noise filter if one sample disagrees. This flag is set when a received data bit contains one disagreeing sample. This could indicate line noise, a baud rate or character format mismatch, or loss of synchronization during data reception." /> + <BitField start="16" size="1" name="ABERR" description="Auto-baud Error. An auto-baud error can occur if the BRG counts to its limit before the end of the start bit that is being measured, essentially an auto-baud time-out." /> + <BitField start="17" size="15" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x00C" size="4" name="INTENSET" access="Read/Write" description="Interrupt Enable read and Set register. Contains an individual interrupt enable bit for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RXRDYEN" description="When 1, enables an interrupt when there is a received character available to be read from the RXDAT register." /> + <BitField start="1" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="2" size="1" name="TXRDYEN" description="When 1, enables an interrupt when the TXDAT register is available to take another character to transmit." /> + <BitField start="3" size="1" name="TXIDLEEN" description="When 1, enables an interrupt when the transmitter becomes idle (TXIDLE = 1)." /> + <BitField start="4" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="5" size="1" name="DELTACTSEN" description="When 1, enables an interrupt when there is a change in the state of the CTS input." /> + <BitField start="6" size="1" name="TXDISEN" description="When 1, enables an interrupt when the transmitter is fully disabled as indicated by the TXDISINT flag in STAT. See description of the TXDISINT bit for details." /> + <BitField start="7" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="8" size="1" name="OVERRUNEN" description="When 1, enables an interrupt when an overrun error occurred." /> + <BitField start="9" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="11" size="1" name="DELTARXBRKEN" description="When 1, enables an interrupt when a change of state has occurred in the detection of a received break condition (break condition asserted or deasserted)." /> + <BitField start="12" size="1" name="STARTEN" description="When 1, enables an interrupt when a received start bit has been detected." /> + <BitField start="13" size="1" name="FRAMERREN" description="When 1, enables an interrupt when a framing error has been detected." /> + <BitField start="14" size="1" name="PARITYERREN" description="When 1, enables an interrupt when a parity error has been detected." /> + <BitField start="15" size="1" name="RXNOISEEN" description="When 1, enables an interrupt when noise is detected." /> + <BitField start="16" size="1" name="ABERREN" description="When 1, enables an interrupt when an auto-baud error occurs." /> + <BitField start="17" size="15" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x010" size="4" name="INTENCLR" access="WriteOnly" description="Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared." reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="RXRDYCLR" description="Writing 1 clears the corresponding bit in the INTENSET register." /> + <BitField start="1" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="2" size="1" name="TXRDYCLR" description="Writing 1 clears the corresponding bit in the INTENSET register." /> + <BitField start="3" size="1" name="TXIDLECLR" description="Writing 1 clears the corresponding bit in the INTENSET register." /> + <BitField start="4" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="5" size="1" name="DELTACTSCLR" description="Writing 1 clears the corresponding bit in the INTENSET register." /> + <BitField start="6" size="1" name="TXDISINTCLR" description="Writing 1 clears the corresponding bit in the INTENSET register." /> + <BitField start="7" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="8" size="1" name="OVERRUNCLR" description="Writing 1 clears the corresponding bit in the INTENSET register." /> + <BitField start="9" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="11" size="1" name="DELTARXBRKCLR" description="Writing 1 clears the corresponding bit in the INTENSET register." /> + <BitField start="12" size="1" name="STARTCLR" description="Writing 1 clears the corresponding bit in the INTENSET register." /> + <BitField start="13" size="1" name="FRAMERRCLR" description="Writing 1 clears the corresponding bit in the INTENSET register." /> + <BitField start="14" size="1" name="PARITYERRCLR" description="Writing 1 clears the corresponding bit in the INTENSET register." /> + <BitField start="15" size="1" name="RXNOISECLR" description="Writing 1 clears the corresponding bit in the INTENSET register." /> + <BitField start="16" size="1" name="ABERRCLR" description="Writing 1 clears the corresponding bit in the INTENSET register." /> + <BitField start="17" size="15" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x014" size="4" name="RXDAT" access="None" description="Receiver Data register. Contains the last character received." reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="9" name="RXDAT" description="The USART Receiver Data register contains the next received character. The number of bits that are relevant depends on the USART configuration settings." /> + <BitField start="9" size="23" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x018" size="4" name="RXDATSTAT" access="None" description="Receiver Data with Status register. Combines the last character received with the current USART receive status. Allows DMA or software to recover incoming data and status together." reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="9" name="RXDAT" description="The USART Receiver Data register contains the next received character. The number of bits that are relevant depends on the USART configuration settings." /> + <BitField start="9" size="4" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." /> + <BitField start="13" size="1" name="FRAMERR" description="Framing Error status flag. This bit is valid when there is a character to be read in the RXDAT register and reflects the status of that character. This bit will set when the character in RXDAT was received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source." /> + <BitField start="14" size="1" name="PARITYERR" description="Parity Error status flag. This bit is valid when there is a character to be read in the RXDAT register and reflects the status of that character. This bit will be set when a parity error is detected in a received character." /> + <BitField start="15" size="1" name="RXNOISE" description="Received Noise flag. See description of the RXNOISEINT bit in Table 133." /> + <BitField start="16" size="16" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x01C" size="4" name="TXDAT" access="Read/Write" description="Transmit Data register. Data to be transmitted is written here." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="9" name="TXDAT" description="Writing to the USART Transmit Data Register causes the data to be transmitted as soon as the transmit shift register is available and any conditions for transmitting data are met: CTS low (if CTSEN bit = 1), TXDIS bit = 0." /> + <BitField start="9" size="23" name="RESERVED" description="Reserved. Only zero should be written." /> + </Register> + <Register start="+0x020" size="4" name="BRG" access="Read/Write" description="Baud Rate Generator register. 16-bit integer baud rate divisor value." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="16" name="BRGVAL" description="This value is used to divide the USART input clock to determine the baud rate, based on the input clock from the FRG. 0 = The FRG clock is used directly by the USART function. 1 = The FRG clock is divided by 2 before use by the USART function. 2 = The FRG clock is divided by 3 before use by the USART function. ... 0xFFFF = The FRG clock is divided by 65,536 before use by the USART function." /> + <BitField start="16" size="16" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x024" size="4" name="INTSTAT" access="ReadOnly" description="Interrupt status register. Reflects interrupts that are currently enabled." reset_value="0x0005" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RXRDY" description="Receiver Ready flag." /> + <BitField start="1" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="2" size="1" name="TXRDY" description="Transmitter Ready flag." /> + <BitField start="3" size="1" name="TXIDLE" description="Transmitter idle status." /> + <BitField start="4" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="5" size="1" name="DELTACTS" description="This bit is set when a change in the state of the CTS input is detected." /> + <BitField start="6" size="1" name="TXDISINT" description="Transmitter Disabled Interrupt flag." /> + <BitField start="7" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="8" size="1" name="OVERRUNINT" description="Overrun Error interrupt flag." /> + <BitField start="9" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="11" size="1" name="DELTARXBRK" description="This bit is set when a change in the state of receiver break detection occurs." /> + <BitField start="12" size="1" name="START" description="This bit is set when a start is detected on the receiver input." /> + <BitField start="13" size="1" name="FRAMERRINT" description="Framing Error interrupt flag." /> + <BitField start="14" size="1" name="PARITYERRINT" description="Parity Error interrupt flag." /> + <BitField start="15" size="1" name="RXNOISEINT" description="Received Noise interrupt flag." /> + <BitField start="16" size="1" name="ABERR" description="Auto-baud Error flag." /> + <BitField start="17" size="15" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x028" size="4" name="OSR" access="Read/Write" description="Oversample selection register for asynchronous communication." reset_value="0xF" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="4" name="OSRVAL" description="Oversample Selection Value. 0 to 3 = not supported 0x4 = 5 peripheral clocks are used to transmit and receive each data bit. 0x5 = 6 peripheral clocks are used to transmit and receive each data bit. ... 0xF= 16 peripheral clocks are used to transmit and receive each data bit." /> + <BitField start="4" size="28" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x02C" size="4" name="ADDR" access="Read/Write" description="Address register for automatic address matching." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="ADDRESS" description="8-bit address used with automatic address matching. Used when address detection is enabled (ADDRDET in CTL = 1) and automatic address matching is enabled (AUTOADDR in CFG = 1)." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." /> + </Register> + </RegisterGroup> + <RegisterGroup name="USART2" start="0x40070000" description="USART2"> + <Register start="+0x000" size="4" name="CFG" access="Read/Write" description="USART Configuration register. Basic USART configuration settings that typically are not changed during operation." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="ENABLE" description="USART Enable."> + <Enum name="DISABLED" start="0" description="Disabled. The USART is disabled and the internal state machine and counters are reset. While Enable = 0, all USART interrupts and DMA transfers are disabled. When Enable is set again, CFG and most other control bits remain unchanged. For instance, when re-enabled, the USART will immediately generate a TxRdy interrupt (if enabled in the INTENSET register) or a DMA transfer request because the transmitter has been reset and is therefore available." /> + <Enum name="ENABLED" start="1" description="Enabled. The USART is enabled for operation." /> + </BitField> + <BitField start="1" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="2" size="2" name="DATALEN" description="Selects the data size for the USART."> + <Enum name="7_BIT_DATA_LENGTH" start="0x0" description="7 bit Data length." /> + <Enum name="8_BIT_DATA_LENGTH" start="0x1" description="8 bit Data length." /> + <Enum name="9_BIT_DATA_LENGTH" start="0x2" description="9 bit data length. The 9th bit is commonly used for addressing in multidrop mode. See the ADDRDET bit in the CTL register." /> + <Enum name="RESERVED" start="0x3" description="Reserved." /> + </BitField> + <BitField start="4" size="2" name="PARITYSEL" description="Selects what type of parity is used by the USART."> + <Enum name="NO_PARITY" start="0x0" description="No parity." /> + <Enum name="RESERVED" start="0x1" description="Reserved." /> + <Enum name="EVEN_PARITY" start="0x2" description="Even parity. Adds a bit to each character such that the number of 1s in a transmitted character is even, and the number of 1s in a received character is expected to be even." /> + <Enum name="ODD_PARITY" start="0x3" description="Odd parity. Adds a bit to each character such that the number of 1s in a transmitted character is odd, and the number of 1s in a received character is expected to be odd." /> + </BitField> + <BitField start="6" size="1" name="STOPLEN" description="Number of stop bits appended to transmitted data. Only a single stop bit is required for received data."> + <Enum name="1_STOP_BIT" start="0" description="1 stop bit." /> + <Enum name="2_STOP_BITS" start="1" description="2 stop bits. This setting should only be used for asynchronous communication." /> + </BitField> + <BitField start="7" size="1" name="MODE32K" description="Selects standard or 32 kHz clocking mode."> + <Enum name="STANDARD" start="0" description="UART uses standard clocking." /> + <Enum name="32KHZ" start="1" description="UART uses the 32 kHz clock from the RTC oscillator as the clock source to the BRG, and uses a special bit clocking scheme." /> + </BitField> + <BitField start="8" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="9" size="1" name="CTSEN" description="CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin, or from the USART's own RTS if loopback mode is enabled. See Section 11.8.4 for more information."> + <Enum name="NO_FLOW_CONTROL" start="0" description="No flow control. The transmitter does not receive any automatic flow control signal." /> + <Enum name="FLOW_CONTROL_ENABLED" start="1" description="Flow control enabled. The transmitter uses the CTS input (or RTS output in loopback mode) for flow control purposes." /> + </BitField> + <BitField start="10" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="11" size="1" name="SYNCEN" description="Selects synchronous or asynchronous operation."> + <Enum name="ASYNCHRONOUS" start="0" description="Asynchronous mode is selected." /> + <Enum name="SYNCHRONOUS" start="1" description="Synchronous mode is selected." /> + </BitField> + <BitField start="12" size="1" name="CLKPOL" description="Selects the clock polarity and sampling edge of received data in synchronous mode."> + <Enum name="FALLING_EDGE" start="0" description="Falling edge. Un_RXD is sampled on the falling edge of SCLK." /> + <Enum name="RISING_EDGE" start="1" description="Rising edge. Un_RXD is sampled on the rising edge of SCLK." /> + </BitField> + <BitField start="13" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="14" size="1" name="SYNCMST" description="Synchronous mode Master select."> + <Enum name="SLAVE" start="0" description="Slave. When synchronous mode is enabled, the USART is a slave." /> + <Enum name="MASTER" start="1" description="Master. When synchronous mode is enabled, the USART is a master." /> + </BitField> + <BitField start="15" size="1" name="LOOP" description="Selects data loopback mode."> + <Enum name="NORMAL_OPERATION" start="0" description="Normal operation." /> + <Enum name="LOOPBACK_MODE" start="1" description="Loopback mode. This provides a mechanism to perform diagnostic loopback testing for USART data. Serial data from the transmitter (Un_TXD) is connected internally to serial input of the receive (Un_RXD). Un_TXD and Un_RTS activity will also appear on external pins if these functions are configured to appear on device pins. The receiver RTS signal is also looped back to CTS and performs flow control if enabled by CTSEN." /> + </BitField> + <BitField start="16" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="18" size="1" name="OETA" description="Output Enable Turnaround time enable for RS-485 operation."> + <Enum name="DEASSERTED" start="0" description="Deasserted. If selected by OESEL, the Output Enable signal deasserted at the end of the last stop bit of a transmission." /> + <Enum name="ASSERTED" start="1" description="Asserted. If selected by OESEL, the Output Enable signal remains asserted for 1 character time after then end the last stop bit of a transmission. OE will also remain asserted if another transmit begins before it is deasserted." /> + </BitField> + <BitField start="19" size="1" name="AUTOADDR" description="Automatic Address matching enable."> + <Enum name="DISABLED" start="0" description="Disabled. When addressing is enabled by ADDRDET, address matching is done by software. This provides the possibility of versatile addressing (e.g. respond to more than one address)." /> + <Enum name="ENABLED" start="1" description="Enabled. When addressing is enabled by ADDRDET, address matching is done by hardware, using the value in the ADDR register as the address to match." /> + </BitField> + <BitField start="20" size="1" name="OESEL" description="Output Enable Select."> + <Enum name="FLOW_CONTROL" start="0" description="Flow control. The RTS signal is used as the standard flow control function." /> + <Enum name="OUTPUT_ENABLE" start="1" description="Output enable. The RTS signal is taken over in order to provide an output enable signal to control an RS-485 transceiver." /> + </BitField> + <BitField start="21" size="1" name="OEPOL" description="Output Enable Polarity."> + <Enum name="LOW" start="0" description="Low. If selected by OESEL, the output enable is active low." /> + <Enum name="HIGH" start="1" description="High. If selected by OESEL, the output enable is active high." /> + </BitField> + <BitField start="22" size="1" name="RXPOL" description="Receive data polarity."> + <Enum name="NOT_CHANGED" start="0" description="Not changed. The RX signal is used as it arrives from the pin. This means that the RX rest value is 1, start bit is 0, data is not inverted, and the stop bit is 1." /> + <Enum name="INVERTED" start="1" description="Inverted. The RX signal is inverted before being used by the UART. This means that the RX rest value is 0, start bit is 1, data is inverted, and the stop bit is 0." /> + </BitField> + <BitField start="23" size="1" name="TXPOL" description="Transmit data polarity."> + <Enum name="NOT_CHANGED" start="0" description="Not changed. The TX signal is sent out without change. This means that the TX rest value is 1, start bit is 0, data is not inverted, and the stop bit is 1." /> + <Enum name="INVERTED" start="1" description="Inverted. The TX signal is inverted by the UART before being sent out. This means that the TX rest value is 0, start bit is 1, data is inverted, and the stop bit is 0." /> + </BitField> + <BitField start="24" size="8" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x004" size="4" name="CTL" access="Read/Write" description="USART Control register. USART control settings that are more likely to change during operation." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="1" size="1" name="TXBRKEN" description="Break Enable."> + <Enum name="NORMAL_OPERATION" start="0" description="Normal operation." /> + <Enum name="CONTINUOUS_BREAK_IS" start="1" description="Continuous break is sent immediately when this bit is set, and remains until this bit is cleared. A break may be sent without danger of corrupting any currently transmitting character if the transmitter is first disabled (TXDIS in CTL is set) and then waiting for the transmitter to be disabled (TXDISINT in STAT = 1) before writing 1 to TXBRKEN." /> + </BitField> + <BitField start="2" size="1" name="ADDRDET" description="Enable address detect mode."> + <Enum name="DISABLED" start="0" description="Disabled. The USART presents all incoming data." /> + <Enum name="ENABLED" start="1" description="Enabled. The USART receiver ignores incoming data that does not have the most significant bit of the data (typically the 9th bit) = 1. When the data MSB bit = 1, the receiver treats the incoming data normally, generating a received data interrupt. Software can then check the data to see if this is an address that should be handled. If it is, the ADDRDET bit is cleared by software and further incoming data is handled normally." /> + </BitField> + <BitField start="3" size="3" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="6" size="1" name="TXDIS" description="Transmit Disable."> + <Enum name="NOT_DISABLED" start="0" description="Not disabled. USART transmitter is not disabled." /> + <Enum name="DISABLED" start="1" description="Disabled. USART transmitter is disabled after any character currently being transmitted is complete. This feature can be used to facilitate software flow control." /> + </BitField> + <BitField start="7" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="8" size="1" name="CC" description="Continuous Clock generation. By default, SCLK is only output while data is being transmitted in synchronous mode."> + <Enum name="CLOCK_ON_CHARACTER" start="0" description="Clock on character. In synchronous mode, SCLK cycles only when characters are being sent on Un_TXD or to complete a character that is being received." /> + <Enum name="CONTINUOUS_CLOCK" start="1" description="Continuous clock. SCLK runs continuously in synchronous mode, allowing characters to be received on Un_RxD independently from transmission on Un_TXD)." /> + </BitField> + <BitField start="9" size="1" name="CLRCCONRX" description="Clear Continuous Clock."> + <Enum name="NO_EFFECT" start="0" description="No effect on the CC bit." /> + <Enum name="AUTO_CLEAR" start="1" description="Auto-clear. The CC bit is automatically cleared when a complete character has been received. This bit is cleared at the same time." /> + </BitField> + <BitField start="10" size="6" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="16" size="1" name="AUTOBAUD" description="Autobaud enable."> + <Enum name="DISABLED" start="0" description="Disabled. UART is in normal operating mode." /> + <Enum name="ENABLED" start="1" description="Enabled. UART is in autobaud mode. This bit should only be set when the UART receiver is idle. The first start bit of RX is measured and used the update the BRG register to match the received data rate. AUTOBAUD is cleared once this process is complete, or if there is an AERR. This bit can be cleared by software when set, but only when the UART receiver is idle." /> + </BitField> + <BitField start="17" size="15" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x008" size="4" name="STAT" access="Read/Write" description="USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them." reset_value="0x000E" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RXRDY" description="Receiver Ready flag. When 1, indicates that data is available to be read from the receiver buffer. Cleared after a read of the RXDAT or RXDATSTAT registers." /> + <BitField start="1" size="1" name="RXIDLE" description="Receiver Idle. When 0, indicates that the receiver is currently in the process of receiving data. When 1, indicates that the receiver is not currently in the process of receiving data." /> + <BitField start="2" size="1" name="TXRDY" description="Transmitter Ready flag. When 1, this bit indicates that data may be written to the transmit buffer. Previous data may still be in the process of being transmitted. Cleared when data is written to TXDAT. Set when the data is moved from the transmit buffer to the transmit shift register." /> + <BitField start="3" size="1" name="TXIDLE" description="Transmitter Idle. When 0, indicates that the transmitter is currently in the process of sending data.When 1, indicate that the transmitter is not currently in the process of sending data." /> + <BitField start="4" size="1" name="CTS" description="This bit reflects the current state of the CTS signal, regardless of the setting of the CTSEN bit in the CFG register. This will be the value of the CTS input pin unless loopback mode is enabled." /> + <BitField start="5" size="1" name="DELTACTS" description="This bit is set when a change in the state is detected for the CTS flag above. This bit is cleared by software." /> + <BitField start="6" size="1" name="TXDISSTAT" description="Transmitter Disabled Interrupt flag. When 1, this bit indicates that the USART transmitter is fully idle after being disabled via the TXDIS in the CFG register (TXDIS = 1)." /> + <BitField start="7" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="8" size="1" name="OVERRUNINT" description="Overrun Error interrupt flag. This flag is set when a new character is received while the receiver buffer is still in use. If this occurs, the newly received character in the shift register is lost." /> + <BitField start="9" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="10" size="1" name="RXBRK" description="Received Break. This bit reflects the current state of the receiver break detection logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also be set when this condition occurs because the stop bit(s) for the character would be missing. RXBRK is cleared when the Un_RXD pin goes high." /> + <BitField start="11" size="1" name="DELTARXBRK" description="This bit is set when a change in the state of receiver break detection occurs. Cleared by software." /> + <BitField start="12" size="1" name="START" description="This bit is set when a start is detected on the receiver input. Its purpose is primarily to allow wake-up from Deep-sleep or Power-down mode immediately when a start is detected. Cleared by software." /> + <BitField start="13" size="1" name="FRAMERRINT" description="Framing Error interrupt flag. This flag is set when a character is received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source." /> + <BitField start="14" size="1" name="PARITYERRINT" description="Parity Error interrupt flag. This flag is set when a parity error is detected in a received character.." /> + <BitField start="15" size="1" name="RXNOISEINT" description="Received Noise interrupt flag. Three samples of received data are taken in order to determine the value of each received data bit, except in synchronous mode. This acts as a noise filter if one sample disagrees. This flag is set when a received data bit contains one disagreeing sample. This could indicate line noise, a baud rate or character format mismatch, or loss of synchronization during data reception." /> + <BitField start="16" size="1" name="ABERR" description="Auto-baud Error. An auto-baud error can occur if the BRG counts to its limit before the end of the start bit that is being measured, essentially an auto-baud time-out." /> + <BitField start="17" size="15" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x00C" size="4" name="INTENSET" access="Read/Write" description="Interrupt Enable read and Set register. Contains an individual interrupt enable bit for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RXRDYEN" description="When 1, enables an interrupt when there is a received character available to be read from the RXDAT register." /> + <BitField start="1" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="2" size="1" name="TXRDYEN" description="When 1, enables an interrupt when the TXDAT register is available to take another character to transmit." /> + <BitField start="3" size="1" name="TXIDLEEN" description="When 1, enables an interrupt when the transmitter becomes idle (TXIDLE = 1)." /> + <BitField start="4" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="5" size="1" name="DELTACTSEN" description="When 1, enables an interrupt when there is a change in the state of the CTS input." /> + <BitField start="6" size="1" name="TXDISEN" description="When 1, enables an interrupt when the transmitter is fully disabled as indicated by the TXDISINT flag in STAT. See description of the TXDISINT bit for details." /> + <BitField start="7" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="8" size="1" name="OVERRUNEN" description="When 1, enables an interrupt when an overrun error occurred." /> + <BitField start="9" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="11" size="1" name="DELTARXBRKEN" description="When 1, enables an interrupt when a change of state has occurred in the detection of a received break condition (break condition asserted or deasserted)." /> + <BitField start="12" size="1" name="STARTEN" description="When 1, enables an interrupt when a received start bit has been detected." /> + <BitField start="13" size="1" name="FRAMERREN" description="When 1, enables an interrupt when a framing error has been detected." /> + <BitField start="14" size="1" name="PARITYERREN" description="When 1, enables an interrupt when a parity error has been detected." /> + <BitField start="15" size="1" name="RXNOISEEN" description="When 1, enables an interrupt when noise is detected." /> + <BitField start="16" size="1" name="ABERREN" description="When 1, enables an interrupt when an auto-baud error occurs." /> + <BitField start="17" size="15" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x010" size="4" name="INTENCLR" access="WriteOnly" description="Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared." reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="RXRDYCLR" description="Writing 1 clears the corresponding bit in the INTENSET register." /> + <BitField start="1" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="2" size="1" name="TXRDYCLR" description="Writing 1 clears the corresponding bit in the INTENSET register." /> + <BitField start="3" size="1" name="TXIDLECLR" description="Writing 1 clears the corresponding bit in the INTENSET register." /> + <BitField start="4" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="5" size="1" name="DELTACTSCLR" description="Writing 1 clears the corresponding bit in the INTENSET register." /> + <BitField start="6" size="1" name="TXDISINTCLR" description="Writing 1 clears the corresponding bit in the INTENSET register." /> + <BitField start="7" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="8" size="1" name="OVERRUNCLR" description="Writing 1 clears the corresponding bit in the INTENSET register." /> + <BitField start="9" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="11" size="1" name="DELTARXBRKCLR" description="Writing 1 clears the corresponding bit in the INTENSET register." /> + <BitField start="12" size="1" name="STARTCLR" description="Writing 1 clears the corresponding bit in the INTENSET register." /> + <BitField start="13" size="1" name="FRAMERRCLR" description="Writing 1 clears the corresponding bit in the INTENSET register." /> + <BitField start="14" size="1" name="PARITYERRCLR" description="Writing 1 clears the corresponding bit in the INTENSET register." /> + <BitField start="15" size="1" name="RXNOISECLR" description="Writing 1 clears the corresponding bit in the INTENSET register." /> + <BitField start="16" size="1" name="ABERRCLR" description="Writing 1 clears the corresponding bit in the INTENSET register." /> + <BitField start="17" size="15" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x014" size="4" name="RXDAT" access="None" description="Receiver Data register. Contains the last character received." reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="9" name="RXDAT" description="The USART Receiver Data register contains the next received character. The number of bits that are relevant depends on the USART configuration settings." /> + <BitField start="9" size="23" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x018" size="4" name="RXDATSTAT" access="None" description="Receiver Data with Status register. Combines the last character received with the current USART receive status. Allows DMA or software to recover incoming data and status together." reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="9" name="RXDAT" description="The USART Receiver Data register contains the next received character. The number of bits that are relevant depends on the USART configuration settings." /> + <BitField start="9" size="4" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." /> + <BitField start="13" size="1" name="FRAMERR" description="Framing Error status flag. This bit is valid when there is a character to be read in the RXDAT register and reflects the status of that character. This bit will set when the character in RXDAT was received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source." /> + <BitField start="14" size="1" name="PARITYERR" description="Parity Error status flag. This bit is valid when there is a character to be read in the RXDAT register and reflects the status of that character. This bit will be set when a parity error is detected in a received character." /> + <BitField start="15" size="1" name="RXNOISE" description="Received Noise flag. See description of the RXNOISEINT bit in Table 133." /> + <BitField start="16" size="16" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x01C" size="4" name="TXDAT" access="Read/Write" description="Transmit Data register. Data to be transmitted is written here." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="9" name="TXDAT" description="Writing to the USART Transmit Data Register causes the data to be transmitted as soon as the transmit shift register is available and any conditions for transmitting data are met: CTS low (if CTSEN bit = 1), TXDIS bit = 0." /> + <BitField start="9" size="23" name="RESERVED" description="Reserved. Only zero should be written." /> + </Register> + <Register start="+0x020" size="4" name="BRG" access="Read/Write" description="Baud Rate Generator register. 16-bit integer baud rate divisor value." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="16" name="BRGVAL" description="This value is used to divide the USART input clock to determine the baud rate, based on the input clock from the FRG. 0 = The FRG clock is used directly by the USART function. 1 = The FRG clock is divided by 2 before use by the USART function. 2 = The FRG clock is divided by 3 before use by the USART function. ... 0xFFFF = The FRG clock is divided by 65,536 before use by the USART function." /> + <BitField start="16" size="16" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x024" size="4" name="INTSTAT" access="ReadOnly" description="Interrupt status register. Reflects interrupts that are currently enabled." reset_value="0x0005" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RXRDY" description="Receiver Ready flag." /> + <BitField start="1" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="2" size="1" name="TXRDY" description="Transmitter Ready flag." /> + <BitField start="3" size="1" name="TXIDLE" description="Transmitter idle status." /> + <BitField start="4" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="5" size="1" name="DELTACTS" description="This bit is set when a change in the state of the CTS input is detected." /> + <BitField start="6" size="1" name="TXDISINT" description="Transmitter Disabled Interrupt flag." /> + <BitField start="7" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="8" size="1" name="OVERRUNINT" description="Overrun Error interrupt flag." /> + <BitField start="9" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="11" size="1" name="DELTARXBRK" description="This bit is set when a change in the state of receiver break detection occurs." /> + <BitField start="12" size="1" name="START" description="This bit is set when a start is detected on the receiver input." /> + <BitField start="13" size="1" name="FRAMERRINT" description="Framing Error interrupt flag." /> + <BitField start="14" size="1" name="PARITYERRINT" description="Parity Error interrupt flag." /> + <BitField start="15" size="1" name="RXNOISEINT" description="Received Noise interrupt flag." /> + <BitField start="16" size="1" name="ABERR" description="Auto-baud Error flag." /> + <BitField start="17" size="15" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x028" size="4" name="OSR" access="Read/Write" description="Oversample selection register for asynchronous communication." reset_value="0xF" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="4" name="OSRVAL" description="Oversample Selection Value. 0 to 3 = not supported 0x4 = 5 peripheral clocks are used to transmit and receive each data bit. 0x5 = 6 peripheral clocks are used to transmit and receive each data bit. ... 0xF= 16 peripheral clocks are used to transmit and receive each data bit." /> + <BitField start="4" size="28" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x02C" size="4" name="ADDR" access="Read/Write" description="Address register for automatic address matching." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="ADDRESS" description="8-bit address used with automatic address matching. Used when address detection is enabled (ADDRDET in CTL = 1) and automatic address matching is enabled (AUTOADDR in CFG = 1)." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." /> + </Register> + </RegisterGroup> + <RegisterGroup name="USART3" start="0x40074000" description="USART3"> + <Register start="+0x000" size="4" name="CFG" access="Read/Write" description="USART Configuration register. Basic USART configuration settings that typically are not changed during operation." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="ENABLE" description="USART Enable."> + <Enum name="DISABLED" start="0" description="Disabled. The USART is disabled and the internal state machine and counters are reset. While Enable = 0, all USART interrupts and DMA transfers are disabled. When Enable is set again, CFG and most other control bits remain unchanged. For instance, when re-enabled, the USART will immediately generate a TxRdy interrupt (if enabled in the INTENSET register) or a DMA transfer request because the transmitter has been reset and is therefore available." /> + <Enum name="ENABLED" start="1" description="Enabled. The USART is enabled for operation." /> + </BitField> + <BitField start="1" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="2" size="2" name="DATALEN" description="Selects the data size for the USART."> + <Enum name="7_BIT_DATA_LENGTH" start="0x0" description="7 bit Data length." /> + <Enum name="8_BIT_DATA_LENGTH" start="0x1" description="8 bit Data length." /> + <Enum name="9_BIT_DATA_LENGTH" start="0x2" description="9 bit data length. The 9th bit is commonly used for addressing in multidrop mode. See the ADDRDET bit in the CTL register." /> + <Enum name="RESERVED" start="0x3" description="Reserved." /> + </BitField> + <BitField start="4" size="2" name="PARITYSEL" description="Selects what type of parity is used by the USART."> + <Enum name="NO_PARITY" start="0x0" description="No parity." /> + <Enum name="RESERVED" start="0x1" description="Reserved." /> + <Enum name="EVEN_PARITY" start="0x2" description="Even parity. Adds a bit to each character such that the number of 1s in a transmitted character is even, and the number of 1s in a received character is expected to be even." /> + <Enum name="ODD_PARITY" start="0x3" description="Odd parity. Adds a bit to each character such that the number of 1s in a transmitted character is odd, and the number of 1s in a received character is expected to be odd." /> + </BitField> + <BitField start="6" size="1" name="STOPLEN" description="Number of stop bits appended to transmitted data. Only a single stop bit is required for received data."> + <Enum name="1_STOP_BIT" start="0" description="1 stop bit." /> + <Enum name="2_STOP_BITS" start="1" description="2 stop bits. This setting should only be used for asynchronous communication." /> + </BitField> + <BitField start="7" size="1" name="MODE32K" description="Selects standard or 32 kHz clocking mode."> + <Enum name="STANDARD" start="0" description="UART uses standard clocking." /> + <Enum name="32KHZ" start="1" description="UART uses the 32 kHz clock from the RTC oscillator as the clock source to the BRG, and uses a special bit clocking scheme." /> + </BitField> + <BitField start="8" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="9" size="1" name="CTSEN" description="CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin, or from the USART's own RTS if loopback mode is enabled. See Section 11.8.4 for more information."> + <Enum name="NO_FLOW_CONTROL" start="0" description="No flow control. The transmitter does not receive any automatic flow control signal." /> + <Enum name="FLOW_CONTROL_ENABLED" start="1" description="Flow control enabled. The transmitter uses the CTS input (or RTS output in loopback mode) for flow control purposes." /> + </BitField> + <BitField start="10" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="11" size="1" name="SYNCEN" description="Selects synchronous or asynchronous operation."> + <Enum name="ASYNCHRONOUS" start="0" description="Asynchronous mode is selected." /> + <Enum name="SYNCHRONOUS" start="1" description="Synchronous mode is selected." /> + </BitField> + <BitField start="12" size="1" name="CLKPOL" description="Selects the clock polarity and sampling edge of received data in synchronous mode."> + <Enum name="FALLING_EDGE" start="0" description="Falling edge. Un_RXD is sampled on the falling edge of SCLK." /> + <Enum name="RISING_EDGE" start="1" description="Rising edge. Un_RXD is sampled on the rising edge of SCLK." /> + </BitField> + <BitField start="13" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="14" size="1" name="SYNCMST" description="Synchronous mode Master select."> + <Enum name="SLAVE" start="0" description="Slave. When synchronous mode is enabled, the USART is a slave." /> + <Enum name="MASTER" start="1" description="Master. When synchronous mode is enabled, the USART is a master." /> + </BitField> + <BitField start="15" size="1" name="LOOP" description="Selects data loopback mode."> + <Enum name="NORMAL_OPERATION" start="0" description="Normal operation." /> + <Enum name="LOOPBACK_MODE" start="1" description="Loopback mode. This provides a mechanism to perform diagnostic loopback testing for USART data. Serial data from the transmitter (Un_TXD) is connected internally to serial input of the receive (Un_RXD). Un_TXD and Un_RTS activity will also appear on external pins if these functions are configured to appear on device pins. The receiver RTS signal is also looped back to CTS and performs flow control if enabled by CTSEN." /> + </BitField> + <BitField start="16" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="18" size="1" name="OETA" description="Output Enable Turnaround time enable for RS-485 operation."> + <Enum name="DEASSERTED" start="0" description="Deasserted. If selected by OESEL, the Output Enable signal deasserted at the end of the last stop bit of a transmission." /> + <Enum name="ASSERTED" start="1" description="Asserted. If selected by OESEL, the Output Enable signal remains asserted for 1 character time after then end the last stop bit of a transmission. OE will also remain asserted if another transmit begins before it is deasserted." /> + </BitField> + <BitField start="19" size="1" name="AUTOADDR" description="Automatic Address matching enable."> + <Enum name="DISABLED" start="0" description="Disabled. When addressing is enabled by ADDRDET, address matching is done by software. This provides the possibility of versatile addressing (e.g. respond to more than one address)." /> + <Enum name="ENABLED" start="1" description="Enabled. When addressing is enabled by ADDRDET, address matching is done by hardware, using the value in the ADDR register as the address to match." /> + </BitField> + <BitField start="20" size="1" name="OESEL" description="Output Enable Select."> + <Enum name="FLOW_CONTROL" start="0" description="Flow control. The RTS signal is used as the standard flow control function." /> + <Enum name="OUTPUT_ENABLE" start="1" description="Output enable. The RTS signal is taken over in order to provide an output enable signal to control an RS-485 transceiver." /> + </BitField> + <BitField start="21" size="1" name="OEPOL" description="Output Enable Polarity."> + <Enum name="LOW" start="0" description="Low. If selected by OESEL, the output enable is active low." /> + <Enum name="HIGH" start="1" description="High. If selected by OESEL, the output enable is active high." /> + </BitField> + <BitField start="22" size="1" name="RXPOL" description="Receive data polarity."> + <Enum name="NOT_CHANGED" start="0" description="Not changed. The RX signal is used as it arrives from the pin. This means that the RX rest value is 1, start bit is 0, data is not inverted, and the stop bit is 1." /> + <Enum name="INVERTED" start="1" description="Inverted. The RX signal is inverted before being used by the UART. This means that the RX rest value is 0, start bit is 1, data is inverted, and the stop bit is 0." /> + </BitField> + <BitField start="23" size="1" name="TXPOL" description="Transmit data polarity."> + <Enum name="NOT_CHANGED" start="0" description="Not changed. The TX signal is sent out without change. This means that the TX rest value is 1, start bit is 0, data is not inverted, and the stop bit is 1." /> + <Enum name="INVERTED" start="1" description="Inverted. The TX signal is inverted by the UART before being sent out. This means that the TX rest value is 0, start bit is 1, data is inverted, and the stop bit is 0." /> + </BitField> + <BitField start="24" size="8" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x004" size="4" name="CTL" access="Read/Write" description="USART Control register. USART control settings that are more likely to change during operation." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="1" size="1" name="TXBRKEN" description="Break Enable."> + <Enum name="NORMAL_OPERATION" start="0" description="Normal operation." /> + <Enum name="CONTINUOUS_BREAK_IS" start="1" description="Continuous break is sent immediately when this bit is set, and remains until this bit is cleared. A break may be sent without danger of corrupting any currently transmitting character if the transmitter is first disabled (TXDIS in CTL is set) and then waiting for the transmitter to be disabled (TXDISINT in STAT = 1) before writing 1 to TXBRKEN." /> + </BitField> + <BitField start="2" size="1" name="ADDRDET" description="Enable address detect mode."> + <Enum name="DISABLED" start="0" description="Disabled. The USART presents all incoming data." /> + <Enum name="ENABLED" start="1" description="Enabled. The USART receiver ignores incoming data that does not have the most significant bit of the data (typically the 9th bit) = 1. When the data MSB bit = 1, the receiver treats the incoming data normally, generating a received data interrupt. Software can then check the data to see if this is an address that should be handled. If it is, the ADDRDET bit is cleared by software and further incoming data is handled normally." /> + </BitField> + <BitField start="3" size="3" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="6" size="1" name="TXDIS" description="Transmit Disable."> + <Enum name="NOT_DISABLED" start="0" description="Not disabled. USART transmitter is not disabled." /> + <Enum name="DISABLED" start="1" description="Disabled. USART transmitter is disabled after any character currently being transmitted is complete. This feature can be used to facilitate software flow control." /> + </BitField> + <BitField start="7" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="8" size="1" name="CC" description="Continuous Clock generation. By default, SCLK is only output while data is being transmitted in synchronous mode."> + <Enum name="CLOCK_ON_CHARACTER" start="0" description="Clock on character. In synchronous mode, SCLK cycles only when characters are being sent on Un_TXD or to complete a character that is being received." /> + <Enum name="CONTINUOUS_CLOCK" start="1" description="Continuous clock. SCLK runs continuously in synchronous mode, allowing characters to be received on Un_RxD independently from transmission on Un_TXD)." /> + </BitField> + <BitField start="9" size="1" name="CLRCCONRX" description="Clear Continuous Clock."> + <Enum name="NO_EFFECT" start="0" description="No effect on the CC bit." /> + <Enum name="AUTO_CLEAR" start="1" description="Auto-clear. The CC bit is automatically cleared when a complete character has been received. This bit is cleared at the same time." /> + </BitField> + <BitField start="10" size="6" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="16" size="1" name="AUTOBAUD" description="Autobaud enable."> + <Enum name="DISABLED" start="0" description="Disabled. UART is in normal operating mode." /> + <Enum name="ENABLED" start="1" description="Enabled. UART is in autobaud mode. This bit should only be set when the UART receiver is idle. The first start bit of RX is measured and used the update the BRG register to match the received data rate. AUTOBAUD is cleared once this process is complete, or if there is an AERR. This bit can be cleared by software when set, but only when the UART receiver is idle." /> + </BitField> + <BitField start="17" size="15" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x008" size="4" name="STAT" access="Read/Write" description="USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them." reset_value="0x000E" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RXRDY" description="Receiver Ready flag. When 1, indicates that data is available to be read from the receiver buffer. Cleared after a read of the RXDAT or RXDATSTAT registers." /> + <BitField start="1" size="1" name="RXIDLE" description="Receiver Idle. When 0, indicates that the receiver is currently in the process of receiving data. When 1, indicates that the receiver is not currently in the process of receiving data." /> + <BitField start="2" size="1" name="TXRDY" description="Transmitter Ready flag. When 1, this bit indicates that data may be written to the transmit buffer. Previous data may still be in the process of being transmitted. Cleared when data is written to TXDAT. Set when the data is moved from the transmit buffer to the transmit shift register." /> + <BitField start="3" size="1" name="TXIDLE" description="Transmitter Idle. When 0, indicates that the transmitter is currently in the process of sending data.When 1, indicate that the transmitter is not currently in the process of sending data." /> + <BitField start="4" size="1" name="CTS" description="This bit reflects the current state of the CTS signal, regardless of the setting of the CTSEN bit in the CFG register. This will be the value of the CTS input pin unless loopback mode is enabled." /> + <BitField start="5" size="1" name="DELTACTS" description="This bit is set when a change in the state is detected for the CTS flag above. This bit is cleared by software." /> + <BitField start="6" size="1" name="TXDISSTAT" description="Transmitter Disabled Interrupt flag. When 1, this bit indicates that the USART transmitter is fully idle after being disabled via the TXDIS in the CFG register (TXDIS = 1)." /> + <BitField start="7" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="8" size="1" name="OVERRUNINT" description="Overrun Error interrupt flag. This flag is set when a new character is received while the receiver buffer is still in use. If this occurs, the newly received character in the shift register is lost." /> + <BitField start="9" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="10" size="1" name="RXBRK" description="Received Break. This bit reflects the current state of the receiver break detection logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also be set when this condition occurs because the stop bit(s) for the character would be missing. RXBRK is cleared when the Un_RXD pin goes high." /> + <BitField start="11" size="1" name="DELTARXBRK" description="This bit is set when a change in the state of receiver break detection occurs. Cleared by software." /> + <BitField start="12" size="1" name="START" description="This bit is set when a start is detected on the receiver input. Its purpose is primarily to allow wake-up from Deep-sleep or Power-down mode immediately when a start is detected. Cleared by software." /> + <BitField start="13" size="1" name="FRAMERRINT" description="Framing Error interrupt flag. This flag is set when a character is received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source." /> + <BitField start="14" size="1" name="PARITYERRINT" description="Parity Error interrupt flag. This flag is set when a parity error is detected in a received character.." /> + <BitField start="15" size="1" name="RXNOISEINT" description="Received Noise interrupt flag. Three samples of received data are taken in order to determine the value of each received data bit, except in synchronous mode. This acts as a noise filter if one sample disagrees. This flag is set when a received data bit contains one disagreeing sample. This could indicate line noise, a baud rate or character format mismatch, or loss of synchronization during data reception." /> + <BitField start="16" size="1" name="ABERR" description="Auto-baud Error. An auto-baud error can occur if the BRG counts to its limit before the end of the start bit that is being measured, essentially an auto-baud time-out." /> + <BitField start="17" size="15" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x00C" size="4" name="INTENSET" access="Read/Write" description="Interrupt Enable read and Set register. Contains an individual interrupt enable bit for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RXRDYEN" description="When 1, enables an interrupt when there is a received character available to be read from the RXDAT register." /> + <BitField start="1" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="2" size="1" name="TXRDYEN" description="When 1, enables an interrupt when the TXDAT register is available to take another character to transmit." /> + <BitField start="3" size="1" name="TXIDLEEN" description="When 1, enables an interrupt when the transmitter becomes idle (TXIDLE = 1)." /> + <BitField start="4" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="5" size="1" name="DELTACTSEN" description="When 1, enables an interrupt when there is a change in the state of the CTS input." /> + <BitField start="6" size="1" name="TXDISEN" description="When 1, enables an interrupt when the transmitter is fully disabled as indicated by the TXDISINT flag in STAT. See description of the TXDISINT bit for details." /> + <BitField start="7" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="8" size="1" name="OVERRUNEN" description="When 1, enables an interrupt when an overrun error occurred." /> + <BitField start="9" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="11" size="1" name="DELTARXBRKEN" description="When 1, enables an interrupt when a change of state has occurred in the detection of a received break condition (break condition asserted or deasserted)." /> + <BitField start="12" size="1" name="STARTEN" description="When 1, enables an interrupt when a received start bit has been detected." /> + <BitField start="13" size="1" name="FRAMERREN" description="When 1, enables an interrupt when a framing error has been detected." /> + <BitField start="14" size="1" name="PARITYERREN" description="When 1, enables an interrupt when a parity error has been detected." /> + <BitField start="15" size="1" name="RXNOISEEN" description="When 1, enables an interrupt when noise is detected." /> + <BitField start="16" size="1" name="ABERREN" description="When 1, enables an interrupt when an auto-baud error occurs." /> + <BitField start="17" size="15" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x010" size="4" name="INTENCLR" access="WriteOnly" description="Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared." reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="RXRDYCLR" description="Writing 1 clears the corresponding bit in the INTENSET register." /> + <BitField start="1" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="2" size="1" name="TXRDYCLR" description="Writing 1 clears the corresponding bit in the INTENSET register." /> + <BitField start="3" size="1" name="TXIDLECLR" description="Writing 1 clears the corresponding bit in the INTENSET register." /> + <BitField start="4" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="5" size="1" name="DELTACTSCLR" description="Writing 1 clears the corresponding bit in the INTENSET register." /> + <BitField start="6" size="1" name="TXDISINTCLR" description="Writing 1 clears the corresponding bit in the INTENSET register." /> + <BitField start="7" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="8" size="1" name="OVERRUNCLR" description="Writing 1 clears the corresponding bit in the INTENSET register." /> + <BitField start="9" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="11" size="1" name="DELTARXBRKCLR" description="Writing 1 clears the corresponding bit in the INTENSET register." /> + <BitField start="12" size="1" name="STARTCLR" description="Writing 1 clears the corresponding bit in the INTENSET register." /> + <BitField start="13" size="1" name="FRAMERRCLR" description="Writing 1 clears the corresponding bit in the INTENSET register." /> + <BitField start="14" size="1" name="PARITYERRCLR" description="Writing 1 clears the corresponding bit in the INTENSET register." /> + <BitField start="15" size="1" name="RXNOISECLR" description="Writing 1 clears the corresponding bit in the INTENSET register." /> + <BitField start="16" size="1" name="ABERRCLR" description="Writing 1 clears the corresponding bit in the INTENSET register." /> + <BitField start="17" size="15" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x014" size="4" name="RXDAT" access="None" description="Receiver Data register. Contains the last character received." reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="9" name="RXDAT" description="The USART Receiver Data register contains the next received character. The number of bits that are relevant depends on the USART configuration settings." /> + <BitField start="9" size="23" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x018" size="4" name="RXDATSTAT" access="None" description="Receiver Data with Status register. Combines the last character received with the current USART receive status. Allows DMA or software to recover incoming data and status together." reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="9" name="RXDAT" description="The USART Receiver Data register contains the next received character. The number of bits that are relevant depends on the USART configuration settings." /> + <BitField start="9" size="4" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." /> + <BitField start="13" size="1" name="FRAMERR" description="Framing Error status flag. This bit is valid when there is a character to be read in the RXDAT register and reflects the status of that character. This bit will set when the character in RXDAT was received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source." /> + <BitField start="14" size="1" name="PARITYERR" description="Parity Error status flag. This bit is valid when there is a character to be read in the RXDAT register and reflects the status of that character. This bit will be set when a parity error is detected in a received character." /> + <BitField start="15" size="1" name="RXNOISE" description="Received Noise flag. See description of the RXNOISEINT bit in Table 133." /> + <BitField start="16" size="16" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x01C" size="4" name="TXDAT" access="Read/Write" description="Transmit Data register. Data to be transmitted is written here." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="9" name="TXDAT" description="Writing to the USART Transmit Data Register causes the data to be transmitted as soon as the transmit shift register is available and any conditions for transmitting data are met: CTS low (if CTSEN bit = 1), TXDIS bit = 0." /> + <BitField start="9" size="23" name="RESERVED" description="Reserved. Only zero should be written." /> + </Register> + <Register start="+0x020" size="4" name="BRG" access="Read/Write" description="Baud Rate Generator register. 16-bit integer baud rate divisor value." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="16" name="BRGVAL" description="This value is used to divide the USART input clock to determine the baud rate, based on the input clock from the FRG. 0 = The FRG clock is used directly by the USART function. 1 = The FRG clock is divided by 2 before use by the USART function. 2 = The FRG clock is divided by 3 before use by the USART function. ... 0xFFFF = The FRG clock is divided by 65,536 before use by the USART function." /> + <BitField start="16" size="16" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x024" size="4" name="INTSTAT" access="ReadOnly" description="Interrupt status register. Reflects interrupts that are currently enabled." reset_value="0x0005" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RXRDY" description="Receiver Ready flag." /> + <BitField start="1" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="2" size="1" name="TXRDY" description="Transmitter Ready flag." /> + <BitField start="3" size="1" name="TXIDLE" description="Transmitter idle status." /> + <BitField start="4" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="5" size="1" name="DELTACTS" description="This bit is set when a change in the state of the CTS input is detected." /> + <BitField start="6" size="1" name="TXDISINT" description="Transmitter Disabled Interrupt flag." /> + <BitField start="7" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="8" size="1" name="OVERRUNINT" description="Overrun Error interrupt flag." /> + <BitField start="9" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="11" size="1" name="DELTARXBRK" description="This bit is set when a change in the state of receiver break detection occurs." /> + <BitField start="12" size="1" name="START" description="This bit is set when a start is detected on the receiver input." /> + <BitField start="13" size="1" name="FRAMERRINT" description="Framing Error interrupt flag." /> + <BitField start="14" size="1" name="PARITYERRINT" description="Parity Error interrupt flag." /> + <BitField start="15" size="1" name="RXNOISEINT" description="Received Noise interrupt flag." /> + <BitField start="16" size="1" name="ABERR" description="Auto-baud Error flag." /> + <BitField start="17" size="15" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x028" size="4" name="OSR" access="Read/Write" description="Oversample selection register for asynchronous communication." reset_value="0xF" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="4" name="OSRVAL" description="Oversample Selection Value. 0 to 3 = not supported 0x4 = 5 peripheral clocks are used to transmit and receive each data bit. 0x5 = 6 peripheral clocks are used to transmit and receive each data bit. ... 0xF= 16 peripheral clocks are used to transmit and receive each data bit." /> + <BitField start="4" size="28" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x02C" size="4" name="ADDR" access="Read/Write" description="Address register for automatic address matching." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="ADDRESS" description="8-bit address used with automatic address matching. Used when address detection is enabled (ADDRDET in CTL = 1) and automatic address matching is enabled (AUTOADDR in CFG = 1)." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." /> + </Register> + </RegisterGroup> + <RegisterGroup name="USB" start="0x40080000" description="USB device controller"> + <Register start="+0x000" size="4" name="DEVCMDSTAT" access="Read/Write" description="USB Device Command/Status register" reset_value="0x00000800" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="7" name="DEV_ADDR" description="USB device address. After bus reset, the address is reset to 0x00. If the enable bit is set, the device will respond on packets for function address DEV_ADDR. When receiving a SetAddress Control Request from the USB host, software must program the new address before completing the status phase of the SetAddress Control Request." /> + <BitField start="7" size="1" name="DEV_EN" description="USB device enable. If this bit is set, the HW will start responding on packets for function address DEV_ADDR." /> + <BitField start="8" size="1" name="SETUP" description="SETUP token received. If a SETUP token is received and acknowledged by the device, this bit is set. As long as this bit is set all received IN and OUT tokens will be NAKed by HW. SW must clear this bit by writing a one. If this bit is zero, HW will handle the tokens to the CTRL EP0 as indicated by the CTRL EP0 IN and OUT data information programmed by SW." /> + <BitField start="9" size="1" name="PLL_ON" description="USB Clock/PLL control."> + <Enum name="USB_NEEDCLK_FUNCTION" start="0" description="USB_NeedClk functional" /> + <Enum name="USB_NEEDCLK_ALWAYS_1" start="1" description="USB_NeedClk always 1. Clock will not be stopped in case of suspend." /> + </BitField> + <BitField start="10" size="1" name="RESERVED" description="Reserved." /> + <BitField start="11" size="1" name="LPM_SUP" description="LPM Support."> + <Enum name="LPM_NOT_SUPPORTED" start="0" description="LPM not supported." /> + <Enum name="LPM_SUPPORTED" start="1" description="LPM supported." /> + </BitField> + <BitField start="12" size="1" name="INTONNAK_AO" description="Interrupt on NAK for interrupt and bulk OUT EP"> + <Enum name="ONLY_ACKNOWLEDGED_PA" start="0" description="Only acknowledged packets generate an interrupt" /> + <Enum name="BOTH_ACKNOWLEDGED_AN" start="1" description="Both acknowledged and NAKed packets generate interrupts." /> + </BitField> + <BitField start="13" size="1" name="INTONNAK_AI" description="Interrupt on NAK for interrupt and bulk IN EP"> + <Enum name="ONLY_ACKNOWLEDGED_PA" start="0" description="Only acknowledged packets generate an interrupt" /> + <Enum name="BOTH_ACKNOWLEDGED_AN" start="1" description="Both acknowledged and NAKed packets generate interrupts." /> + </BitField> + <BitField start="14" size="1" name="INTONNAK_CO" description="Interrupt on NAK for control OUT EP"> + <Enum name="ONLY_ACKNOWLEDGED_PA" start="0" description="Only acknowledged packets generate an interrupt" /> + <Enum name="BOTH_ACKNOWLEDGED_AN" start="1" description="Both acknowledged and NAKed packets generate interrupts." /> + </BitField> + <BitField start="15" size="1" name="INTONNAK_CI" description="Interrupt on NAK for control IN EP"> + <Enum name="ONLY_ACKNOWLEDGED_PA" start="0" description="Only acknowledged packets generate an interrupt" /> + <Enum name="BOTH_ACKNOWLEDGED_AN" start="1" description="Both acknowledged and NAKed packets generate interrupts." /> + </BitField> + <BitField start="16" size="1" name="DCON" description="Device status - connect. The connect bit must be set by SW to indicate that the device must signal a connect. The pull-up resistor on USB_DP will be enabled when this bit is set and the VbusDebounced bit is one." /> + <BitField start="17" size="1" name="DSUS" description="Device status - suspend. The suspend bit indicates the current suspend state. It is set to 1 when the device hasn't seen any activity on its upstream port for more than 3 milliseconds. It is reset to 0 on any activity. When the device is suspended (Suspend bit DSUS = 1) and the software writes a 0 to it, the device will generate a remote wake-up. This will only happen when the device is connected (Connect bit = 1). When the device is not connected or not suspended, a writing a 0 has no effect. Writing a 1 never has an effect." /> + <BitField start="18" size="1" name="RESERVED" description="Reserved." /> + <BitField start="19" size="1" name="LPM_SUS" description="Device status - LPM Suspend. This bit represents the current LPM suspend state. It is set to 1 by HW when the device has acknowledged the LPM request from the USB host and the Token Retry Time of 10us has elapsed. When the device is in the LPM suspended state (LPM suspend bit = 1) and the software writes a zero to this bit, the device will generate a remote walk-up. Software can only write a zero to this bit when the LPM_REWP bit is set to 1. HW resets this bit when it receives a host initiated resume. HW only updates the LPM_SUS bit when the LPM_SUPP bit is equal to one." /> + <BitField start="20" size="1" name="LPM_REWP" description="LPM Remote Wake-up Enabled by USB host. HW sets this bit to one when the bRemoteWake bit in the LPM extended token is set to 1. HW will reset this bit to 0 when it receives the host initiated LPM resume, when a remote wake-up is sent by the device or when a USB bus reset is received. Software can use this bit to check if the remote wake-up feature is enabled by the host for the LPM transaction." /> + <BitField start="21" size="3" name="RESERVED" description="Reserved." /> + <BitField start="24" size="1" name="DCON_C" description="Device status - connect change. The Connect Change bit is set when the device's pull-up resistor is disconnected because VBus disappeared. The bit is reset by writing a one to it." /> + <BitField start="25" size="1" name="DSUS_C" description="Device status - suspend change. The suspend change bit is set to 1 when the suspend bit toggles. The suspend bit can toggle because: - The device goes in the suspended state - The device is disconnected - The device receives resume signaling on its upstream port. The bit is reset by writing a one to it." /> + <BitField start="26" size="1" name="DRES_C" description="Device status - reset change. This bit is set when the device received a bus reset. On a bus reset the device will automatically go to the default state (unconfigured and responding to address 0). The bit is reset by writing a one to it." /> + <BitField start="27" size="1" name="RESERVED" description="Reserved." /> + <BitField start="28" size="1" name="VBUSDEBOUNCED" description="This bit indicates if Vbus is detected or not. The bit raises immediately when Vbus becomes high. It drops to zero if Vbus is low for at least 3 ms. If this bit is high and the DCon bit is set, the HW will enable the pull-up resistor to signal a connect." /> + <BitField start="29" size="3" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x004" size="4" name="INFO" access="Read/Write" description="USB Info register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="11" name="FRAME_NR" description="Frame number. This contains the frame number of the last successfully received SOF. In case no SOF was received by the device at the beginning of a frame, the frame number returned is that of the last successfully received SOF. In case the SOF frame number contained a CRC error, the frame number returned will be the corrupted frame number as received by the device." /> + <BitField start="11" size="4" name="ERR_CODE" description="The error code which last occurred:"> + <Enum name="NO_ERROR" start="0x0" description="No error" /> + <Enum name="PID_ENCODING_ERROR" start="0x1" description="PID encoding error" /> + <Enum name="PID_UNKNOWN" start="0x2" description="PID unknown" /> + <Enum name="PACKET_UNEXPECTED" start="0x3" description="Packet unexpected" /> + <Enum name="TOKEN_CRC_ERROR" start="0x4" description="Token CRC error" /> + <Enum name="DATA_CRC_ERROR" start="0x5" description="Data CRC error" /> + <Enum name="TIME_OUT" start="0x6" description="Time out" /> + <Enum name="BABBLE" start="0x7" description="Babble" /> + <Enum name="TRUNCATED_EOP" start="0x8" description="Truncated EOP" /> + <Enum name="SENT_RECEIVED_NAK" start="0x9" description="Sent/Received NAK" /> + <Enum name="SENT_STALL" start="0xA" description="Sent Stall" /> + <Enum name="OVERRUN" start="0xB" description="Overrun" /> + <Enum name="SENT_EMPTY_PACKET" start="0xC" description="Sent empty packet" /> + <Enum name="BITSTUFF_ERROR" start="0xD" description="Bitstuff error" /> + <Enum name="SYNC_ERROR" start="0xE" description="Sync error" /> + <Enum name="WRONG_DATA_TOGGLE" start="0xF" description="Wrong data toggle" /> + </BitField> + <BitField start="15" size="1" name="RESERVED" description="Reserved." /> + <BitField start="16" size="16" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x008" size="4" name="EPLISTSTART" access="Read/Write" description="USB EP Command/Status List start address" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="RESERVED" description="Reserved" /> + <BitField start="8" size="24" name="EP_LIST" description="Start address of the USB EP Command/Status List." /> + </Register> + <Register start="+0x00C" size="4" name="DATABUFSTART" access="Read/Write" description="USB Data buffer start address" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="22" name="RESERVED" description="Reserved" /> + <BitField start="22" size="10" name="DA_BUF" description="Start address of the buffer pointer page where all endpoint data buffers are located." /> + </Register> + <Register start="+0x010" size="4" name="LPM" access="Read/Write" description="Link Power Management register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="4" name="HIRD_HW" description="Host Initiated Resume Duration - HW. This is the HIRD value from the last received LPM token" /> + <BitField start="4" size="4" name="HIRD_SW" description="Host Initiated Resume Duration - SW. This is the time duration required by the USB device system to come out of LPM initiated suspend after receiving the host initiated LPM resume." /> + <BitField start="8" size="1" name="DATA_PENDING" description="As long as this bit is set to one and LPM supported bit is set to one, HW will return a NYET handshake on every LPM token it receives. If LPM supported bit is set to one and this bit is zero, HW will return an ACK handshake on every LPM token it receives. If SW has still data pending and LPM is supported, it must set this bit to 1." /> + <BitField start="9" size="23" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x014" size="4" name="EPSKIP" access="Read/Write" description="USB Endpoint skip" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="30" name="SKIP" description="Endpoint skip: Writing 1 to one of these bits, will indicate to HW that it must deactivate the buffer assigned to this endpoint and return control back to software. When HW has deactivated the endpoint, it will clear this bit, but it will not modify the EPINUSE bit. An interrupt will be generated when the Active bit goes from 1 to 0. Note: In case of double-buffering, HW will only clear the Active bit of the buffer indicated by the EPINUSE bit." /> + <BitField start="30" size="2" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x018" size="4" name="EPINUSE" access="Read/Write" description="USB Endpoint Buffer in use" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="RESERVED" description="Reserved. Fixed to zero because the control endpoint zero is fixed to single-buffering for each physical endpoint." /> + <BitField start="2" size="8" name="BUF" description="Buffer in use: This register has one bit per physical endpoint. 0: HW is accessing buffer 0. 1: HW is accessing buffer 1." /> + <BitField start="10" size="22" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x01C" size="4" name="EPBUFCFG" access="Read/Write" description="USB Endpoint Buffer Configuration register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="RESERVED" description="Reserved. Fixed to zero because the control endpoint zero is fixed to single-buffering for each physical endpoint." /> + <BitField start="2" size="8" name="BUF_SB" description="Buffer usage: This register has one bit per physical endpoint. 0: Single-buffer. 1: Double-buffer. If the bit is set to single-buffer (0), it will not toggle the corresponding EPINUSE bit when it clears the active bit. If the bit is set to double-buffer (1), HW will toggle the EPINUSE bit when it clears the Active bit for the buffer." /> + <BitField start="10" size="22" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x020" size="4" name="INTSTAT" access="Read/Write" description="USB interrupt status register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="EP0OUT" description="Interrupt status register bit for the Control EP0 OUT direction. This bit will be set if NBytes transitions to zero or the skip bit is set by software or a SETUP packet is successfully received for the control EP0. If the IntOnNAK_CO is set, this bit will also be set when a NAK is transmitted for the Control EP0 OUT direction. Software can clear this bit by writing a one to it." /> + <BitField start="1" size="1" name="EP0IN" description="Interrupt status register bit for the Control EP0 IN direction. This bit will be set if NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_CI is set, this bit will also be set when a NAK is transmitted for the Control EP0 IN direction. Software can clear this bit by writing a one to it." /> + <BitField start="2" size="1" name="EP1OUT" description="Interrupt status register bit for the EP1 OUT direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AO is set, this bit will also be set when a NAK is transmitted for the EP1 OUT direction. Software can clear this bit by writing a one to it." /> + <BitField start="3" size="1" name="EP1IN" description="Interrupt status register bit for the EP1 IN direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AI is set, this bit will also be set when a NAK is transmitted for the EP1 IN direction. Software can clear this bit by writing a one to it." /> + <BitField start="4" size="1" name="EP2OUT" description="Interrupt status register bit for the EP2 OUT direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AO is set, this bit will also be set when a NAK is transmitted for the EP2 OUT direction. Software can clear this bit by writing a one to it." /> + <BitField start="5" size="1" name="EP2IN" description="Interrupt status register bit for the EP2 IN direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AI is set, this bit will also be set when a NAK is transmitted for the EP2 IN direction. Software can clear this bit by writing a one to it." /> + <BitField start="6" size="1" name="EP3OUT" description="Interrupt status register bit for the EP3 OUT direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AO is set, this bit will also be set when a NAK is transmitted for the EP3 OUT direction. Software can clear this bit by writing a one to it." /> + <BitField start="7" size="1" name="EP3IN" description="Interrupt status register bit for the EP3 IN direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AI is set, this bit will also be set when a NAK is transmitted for the EP3 IN direction. Software can clear this bit by writing a one to it." /> + <BitField start="8" size="1" name="EP4OUT" description="Interrupt status register bit for the EP4 OUT direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AO is set, this bit will also be set when a NAK is transmitted for the EP4 OUT direction. Software can clear this bit by writing a one to it." /> + <BitField start="9" size="1" name="EP4IN" description="Interrupt status register bit for the EP4 IN direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AI is set, this bit will also be set when a NAK is transmitted for the EP4 IN direction. Software can clear this bit by writing a one to it." /> + <BitField start="10" size="20" name="RESERVED" description="Reserved" /> + <BitField start="30" size="1" name="FRAME_INT" description="Frame interrupt. This bit is set to one every millisecond when the VbusDebounced bit and the DCON bit are set. This bit can be used by software when handling isochronous endpoints. Software can clear this bit by writing a one to it." /> + <BitField start="31" size="1" name="DEV_INT" description="Device status interrupt. This bit is set by HW when one of the bits in the Device Status Change register are set. Software can clear this bit by writing a one to it." /> + </Register> + <Register start="+0x024" size="4" name="INTEN" access="Read/Write" description="USB interrupt enable register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="10" name="EP_INT_EN" description="If this bit is set and the corresponding USB interrupt status bit is set, a HW interrupt is generated on the interrupt line indicated by the corresponding USB interrupt routing bit." /> + <BitField start="10" size="20" name="RESERVED" description="Reserved" /> + <BitField start="30" size="1" name="FRAME_INT_EN" description="If this bit is set and the corresponding USB interrupt status bit is set, a HW interrupt is generated on the interrupt line indicated by the corresponding USB interrupt routing bit." /> + <BitField start="31" size="1" name="DEV_INT_EN" description="If this bit is set and the corresponding USB interrupt status bit is set, a HW interrupt is generated on the interrupt line indicated by the corresponding USB interrupt routing bit." /> + </Register> + <Register start="+0x028" size="4" name="INTSETSTAT" access="Read/Write" description="USB set interrupt status register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="10" name="EP_SET_INT" description="If software writes a one to one of these bits, the corresponding USB interrupt status bit is set. When this register is read, the same value as the USB interrupt status register is returned." /> + <BitField start="10" size="20" name="RESERVED" description="Reserved" /> + <BitField start="30" size="1" name="FRAME_SET_INT" description="If software writes a one to one of these bits, the corresponding USB interrupt status bit is set. When this register is read, the same value as the USB interrupt status register is returned." /> + <BitField start="31" size="1" name="DEV_SET_INT" description="If software writes a one to one of these bits, the corresponding USB interrupt status bit is set. When this register is read, the same value as the USB interrupt status register is returned." /> + </Register> + <Register start="+0x02C" size="4" name="INTROUTING" access="Read/Write" description="USB interrupt routing register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="10" name="ROUTE_INT9_0" description="This bit can control on which hardware interrupt line the interrupt will be generated: 0: IRQ interrupt line is selected for this interrupt bit 1: FIQ interrupt line is selected for this interrupt bit" /> + <BitField start="10" size="20" name="RESERVED" description="Reserved" /> + <BitField start="30" size="1" name="ROUTE_INT30" description="This bit can control on which hardware interrupt line the interrupt will be generated: 0: IRQ interrupt line is selected for this interrupt bit 1: FIQ interrupt line is selected for this interrupt bit" /> + <BitField start="31" size="1" name="ROUTE_INT31" description="This bit can control on which hardware interrupt line the interrupt will be generated: 0: IRQ interrupt line is selected for this interrupt bit 1: FIQ interrupt line is selected for this interrupt bit" /> + </Register> + <Register start="+0x034" size="4" name="EPTOGGLE" access="ReadOnly" description="USB Endpoint toggle register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="10" name="TOGGLE" description="Endpoint data toggle: This field indicates the current value of the data toggle for the corresponding endpoint." /> + <BitField start="10" size="22" name="RESERVED" description="Reserved" /> + </Register> + </RegisterGroup> + <RegisterGroup name="CRC" start="0x50000000" description="Cyclic Redundancy Check (CRC) engine"> + <Register start="+0x00" size="4" name="MODE" access="Read/Write" description="CRC mode register" reset_value="0x00000000" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="CRC_POLY" description="CRC polynom: 1X= CRC-32 polynomial 01= CRC-16 polynomial 00= CRC-CCITT polynomial" /> + <BitField start="2" size="1" name="BIT_RVS_WR" description="Data bit order: 1= Bit order reverse for CRC_WR_DATA (per byte) 0= No bit order reverse for CRC_WR_DATA (per byte)" /> + <BitField start="3" size="1" name="CMPL_WR" description="Data complement: 1= 1's complement for CRC_WR_DATA 0= No 1's complement for CRC_WR_DATA" /> + <BitField start="4" size="1" name="BIT_RVS_SUM" description="CRC sum bit order: 1= Bit order reverse for CRC_SUM 0= No bit order reverse for CRC_SUM" /> + <BitField start="5" size="1" name="CMPL_SUM" description="CRC sum complement: 1= 1's complement for CRC_SUM 0=No 1's complement for CRC_SUM" /> + <BitField start="6" size="26" name="Reserved" description="Always 0 when read" /> + </Register> + <Register start="+0x04" size="4" name="SEED" access="Read/Write" description="CRC seed register" reset_value="0x0000FFFF" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRC_SEED" description="A write access to this register will load CRC seed value to CRC_SUM register with selected bit order and 1's complement pre-processes. A write access to this register will overrule the CRC calculation in progresses." /> + </Register> + <Register start="+0x08" size="4" name="SUM" access="ReadOnly" description="CRC checksum register" reset_value="0x0000FFFF" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRC_SUM" description="The most recent CRC sum can be read through this register with selected bit order and 1's complement post-processes." /> + </Register> + <Register start="+0x08" size="4" name="WR_DATA" access="WriteOnly" description="CRC data register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="CRC_WR_DATA" description="Data written to this register will be taken to perform CRC calculation with selected bit order and 1's complement pre-process. Any write size 8, 16 or 32-bit are allowed and accept back-to-back transactions." /> + </Register> + </RegisterGroup> + <RegisterGroup name="DMA" start="0x50004000" description="DMA controller"> + <Register start="+0x000" size="4" name="CTRL" access="Read/Write" description="DMA control." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="ENABLE" description="DMA controller master enable."> + <Enum name="DISABLED" start="0" description="Disabled. The DMA controller is disabled. This clears any triggers that were asserted at the point when disabled, but does not prevent re-triggering when the DMA controller is re-enabled." /> + <Enum name="ENABLED" start="1" description="Enabled. The DMA controller is enabled." /> + </BitField> + <BitField start="1" size="31" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x004" size="4" name="INTSTAT" access="ReadOnly" description="Interrupt status." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="1" size="1" name="ACTIVEINT" description="Summarizes whether any enabled interrupts are pending."> + <Enum name="NOT_PENDING" start="0" description="Not pending. No enabled interrupts are pending." /> + <Enum name="PENDING" start="1" description="Pending. At least one enabled interrupt is pending." /> + </BitField> + <BitField start="2" size="1" name="ACTIVEERRINT" description="Summarizes whether any error interrupts are pending."> + <Enum name="NOT_PENDING" start="0" description="Not pending. No error interrupts are pending." /> + <Enum name="PENDING" start="1" description="Pending. At least one error interrupt is pending." /> + </BitField> + <BitField start="3" size="29" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x008" size="4" name="SRAMBASE" access="Read/Write" description="SRAM address of the channel configuration table." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="10" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="10" size="22" name="OFFSET" description="Address of the beginning of the DMA descriptor table. The table must begin on a 1 kB boundary. Boundary needed for 18 channel DMA configuration: 512 bytes (bottom 9 bits = 0)" /> + </Register> + <Register start="+0x020" size="4" name="ENABLESET0" access="Read/Write" description="Channel Enable read and Set for all DMA channels." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="16" name="ENA" description="Enable for DMA channels 15:0. Bit n enables or disables DMA channel n. 0 = disabled. 1 = enabled." /> + <BitField start="16" size="16" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x028" size="4" name="ENABLECLR0" access="WriteOnly" description="Channel Enable Clear for all DMA channels." reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="16" name="CLR" description="Writing ones to this register clears the corresponding bits in ENABLESET0. Bit n clears the channel enable bit n." /> + </Register> + <Register start="+0x030" size="4" name="ACTIVE0" access="ReadOnly" description="Channel Active status for all DMA channels." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="16" name="ACT" description="Active flag for DMA channel n. Bit n corresponds to DMA channel n. 0 = not active. 1 = active." /> + <BitField start="16" size="16" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x038" size="4" name="BUSY0" access="ReadOnly" description="Channel Busy status for all DMA channels." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="16" name="BSY" description="Busy flag for DMA channel n. Bit n corresponds to DMA channel n. 0 = not busy. 1 = busy." /> + <BitField start="16" size="16" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x040" size="4" name="ERRINT0" access="Read/Write" description="Error Interrupt status for all DMA channels." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="16" name="ERR" description="Error Interrupt flag for DMA channel n. Bit n corresponds to DMA channel n. 0 = error interrupt is not active. 1 = error interrupt is active." /> + <BitField start="18" size="14" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x048" size="4" name="INTENSET0" access="Read/Write" description="Interrupt Enable read and Set for all DMA channels." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="16" name="INTEN" description="Interrupt Enable read and set for DMA channel n. Bit n corresponds to DMA channel n. 0 = interrupt for DMA channel is disabled. 1 = interrupt for DMA channel is enabled." /> + <BitField start="16" size="16" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x050" size="4" name="INTENCLR0" access="WriteOnly" description="Interrupt Enable Clear for all DMA channels." reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="16" name="CLR" description="Writing ones to this register clears corresponding bits in the INTENSET0. Bit n corresponds to DMA channel n." /> + <BitField start="16" size="16" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x058" size="4" name="INTA0" access="Read/Write" description="Interrupt A status for all DMA channels." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="16" name="IA" description="Interrupt A status for DMA channel n. Bit n corresponds to DMA channel n. 0 = the DMA channel interrupt A is not active. 1 = the DMA channel interrupt A is active." /> + <BitField start="16" size="16" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x060" size="4" name="INTB0" access="Read/Write" description="Interrupt B status for all DMA channels." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="16" name="IB" description="Interrupt B status for DMA channel n. Bit n corresponds to DMA channel n. 0 = the DMA channel interrupt B is not active. 1 = the DMA channel interrupt B is active." /> + <BitField start="16" size="16" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x068" size="4" name="SETVALID0" access="WriteOnly" description="Set ValidPending control bits for all DMA channels." reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="16" name="SV" description="SETVALID control for DMA channel n. Bit n corresponds to DMA channel n. 0 = no effect. 1 = sets the VALIDPENDING control bit for DMA channel n." /> + <BitField start="16" size="16" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x070" size="4" name="SETTRIG0" access="WriteOnly" description="Set Trigger control bits for all DMA channels." reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="16" name="TRIG" description="Set Trigger control bit for DMA channel 0. Bit n corresponds to DMA channel n. 0 = no effect. 1 = sets the TRIG bit for DMA channel n." /> + <BitField start="16" size="16" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x078" size="4" name="ABORT0" access="WriteOnly" description="Channel Abort control for all DMA channels." reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="16" name="AORTCTRL" description="Abort control for DMA channel 0. Bit n corresponds to DMA channel n. 0 = no effect. 1 = aborts DMA operations on channel n." /> + <BitField start="16" size="16" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x400+0" size="4" name="CFG0" access="Read/Write" description="Configuration register for DMA channel 0." reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="PERIPHREQEN" description="Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move, any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller."> + <Enum name="DISABLED" start="0" description="Disabled. Peripheral DMA requests are disabled." /> + <Enum name="ENABLED" start="1" description="Enabled. Peripheral DMA requests are enabled." /> + </BitField> + <BitField start="1" size="1" name="HWTRIGEN" description="Hardware Triggering Enable for this channel."> + <Enum name="DISABLED" start="0" description="Disabled. Hardware triggering is not used." /> + <Enum name="ENABLED" start="1" description="Enabled. Use hardware triggering." /> + </BitField> + <BitField start="2" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="4" size="1" name="TRIGPOL" description="Trigger Polarity. Selects the polarity of a hardware trigger for this channel."> + <Enum name="ACTIVE_LOW__FALLING" start="0" description="Active low - falling edge. Hardware trigger is active low or falling edge triggered, based on TRIGTYPE." /> + <Enum name="ACTIVE_HIGH__RISING" start="1" description="Active high - rising edge. Hardware trigger is active high or rising edge triggered, based on TRIGTYPE." /> + </BitField> + <BitField start="5" size="1" name="TRIGTYPE" description="Trigger Type. Selects hardware trigger as edge triggered or level triggered."> + <Enum name="EDGE" start="0" description="Edge. Hardware trigger is edge triggered." /> + <Enum name="LEVEL" start="1" description="Level. Hardware trigger is level triggered. Note that when level triggering without burst (BURSTPOWER = 0) is selected, only hardware triggers should be used on that channel." /> + </BitField> + <BitField start="6" size="1" name="TRIGBURST" description="Trigger Burst. Selects whether hardware triggers cause a single or burst transfer."> + <Enum name="SINGLE_TRANSFER" start="0" description="Single transfer. Hardware trigger causes a single transfer." /> + <Enum name="BURST_TRANSFER" start="1" description="Burst transfer. When the trigger for this channel is set to edge triggered, a hardware trigger causes a burst transfer, as defined by BURSTPOWER. When the trigger for this channel is set to level triggered, a hardware trigger causes transfers to continue as long as the trigger is asserted, unless the transfer is complete." /> + </BitField> + <BitField start="7" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="8" size="4" name="BURSTPOWER" description="Burst Power is used in two ways. It always selects the address wrap size when SrcBurstWrap and/or DstBurstWrap is modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many transfers are performed for each DMA trigger. This can be used, for example, with peripherals that contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). ... 1010: Burst size = 1024 (210). This corresponds to the maximum supported transfer count. others: not supported." /> + <BitField start="12" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="14" size="1" name="SRCBURSTWRAP" description="Source Burst Wrap. When enabled, the source data address for the DMA is wrapped, meaning that the source address range for each burst will be the same. As an example, this could be used to read several sequential registers from a peripheral for each DMA burst, reading the same registers again for each burst."> + <Enum name="DISABLED" start="0" description="Disabled. Source burst wrapping is not enabled for this DMA channel." /> + <Enum name="ENABLED" start="1" description="Enabled. Source burst wrapping is enabled for this DMA channel." /> + </BitField> + <BitField start="15" size="1" name="DSTBURSTWRAP" description="Destination Burst Wrap. When enabled, the destination data address for the DMA is wrapped, meaning that the destination address range for each burst will be the same. As an example, this could be used to write several sequential registers to a peripheral for each DMA burst, writing the same registers again for each burst."> + <Enum name="DISABLED" start="0" description="Disabled. Destination burst wrapping is not enabled for this DMA channel." /> + <Enum name="ENABLED" start="1" description="Enabled. Destination burst wrapping is enabled for this DMA channel." /> + </BitField> + <BitField start="16" size="2" name="CHPRIORITY" description="Priority of this channel when multiple DMA requests are pending. This description reflects a 2-bit priority field providing 4 priority levels. 0x0 = highest priority. 0x3 = lowest priority." /> + <BitField start="18" size="14" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x400+16" size="4" name="CFG1" access="Read/Write" description="Configuration register for DMA channel 0." reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="PERIPHREQEN" description="Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move, any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller."> + <Enum name="DISABLED" start="0" description="Disabled. Peripheral DMA requests are disabled." /> + <Enum name="ENABLED" start="1" description="Enabled. Peripheral DMA requests are enabled." /> + </BitField> + <BitField start="1" size="1" name="HWTRIGEN" description="Hardware Triggering Enable for this channel."> + <Enum name="DISABLED" start="0" description="Disabled. Hardware triggering is not used." /> + <Enum name="ENABLED" start="1" description="Enabled. Use hardware triggering." /> + </BitField> + <BitField start="2" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="4" size="1" name="TRIGPOL" description="Trigger Polarity. Selects the polarity of a hardware trigger for this channel."> + <Enum name="ACTIVE_LOW__FALLING" start="0" description="Active low - falling edge. Hardware trigger is active low or falling edge triggered, based on TRIGTYPE." /> + <Enum name="ACTIVE_HIGH__RISING" start="1" description="Active high - rising edge. Hardware trigger is active high or rising edge triggered, based on TRIGTYPE." /> + </BitField> + <BitField start="5" size="1" name="TRIGTYPE" description="Trigger Type. Selects hardware trigger as edge triggered or level triggered."> + <Enum name="EDGE" start="0" description="Edge. Hardware trigger is edge triggered." /> + <Enum name="LEVEL" start="1" description="Level. Hardware trigger is level triggered. Note that when level triggering without burst (BURSTPOWER = 0) is selected, only hardware triggers should be used on that channel." /> + </BitField> + <BitField start="6" size="1" name="TRIGBURST" description="Trigger Burst. Selects whether hardware triggers cause a single or burst transfer."> + <Enum name="SINGLE_TRANSFER" start="0" description="Single transfer. Hardware trigger causes a single transfer." /> + <Enum name="BURST_TRANSFER" start="1" description="Burst transfer. When the trigger for this channel is set to edge triggered, a hardware trigger causes a burst transfer, as defined by BURSTPOWER. When the trigger for this channel is set to level triggered, a hardware trigger causes transfers to continue as long as the trigger is asserted, unless the transfer is complete." /> + </BitField> + <BitField start="7" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="8" size="4" name="BURSTPOWER" description="Burst Power is used in two ways. It always selects the address wrap size when SrcBurstWrap and/or DstBurstWrap is modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many transfers are performed for each DMA trigger. This can be used, for example, with peripherals that contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). ... 1010: Burst size = 1024 (210). This corresponds to the maximum supported transfer count. others: not supported." /> + <BitField start="12" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="14" size="1" name="SRCBURSTWRAP" description="Source Burst Wrap. When enabled, the source data address for the DMA is wrapped, meaning that the source address range for each burst will be the same. As an example, this could be used to read several sequential registers from a peripheral for each DMA burst, reading the same registers again for each burst."> + <Enum name="DISABLED" start="0" description="Disabled. Source burst wrapping is not enabled for this DMA channel." /> + <Enum name="ENABLED" start="1" description="Enabled. Source burst wrapping is enabled for this DMA channel." /> + </BitField> + <BitField start="15" size="1" name="DSTBURSTWRAP" description="Destination Burst Wrap. When enabled, the destination data address for the DMA is wrapped, meaning that the destination address range for each burst will be the same. As an example, this could be used to write several sequential registers to a peripheral for each DMA burst, writing the same registers again for each burst."> + <Enum name="DISABLED" start="0" description="Disabled. Destination burst wrapping is not enabled for this DMA channel." /> + <Enum name="ENABLED" start="1" description="Enabled. Destination burst wrapping is enabled for this DMA channel." /> + </BitField> + <BitField start="16" size="2" name="CHPRIORITY" description="Priority of this channel when multiple DMA requests are pending. This description reflects a 2-bit priority field providing 4 priority levels. 0x0 = highest priority. 0x3 = lowest priority." /> + <BitField start="18" size="14" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x400+32" size="4" name="CFG2" access="Read/Write" description="Configuration register for DMA channel 0." reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="PERIPHREQEN" description="Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move, any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller."> + <Enum name="DISABLED" start="0" description="Disabled. Peripheral DMA requests are disabled." /> + <Enum name="ENABLED" start="1" description="Enabled. Peripheral DMA requests are enabled." /> + </BitField> + <BitField start="1" size="1" name="HWTRIGEN" description="Hardware Triggering Enable for this channel."> + <Enum name="DISABLED" start="0" description="Disabled. Hardware triggering is not used." /> + <Enum name="ENABLED" start="1" description="Enabled. Use hardware triggering." /> + </BitField> + <BitField start="2" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="4" size="1" name="TRIGPOL" description="Trigger Polarity. Selects the polarity of a hardware trigger for this channel."> + <Enum name="ACTIVE_LOW__FALLING" start="0" description="Active low - falling edge. Hardware trigger is active low or falling edge triggered, based on TRIGTYPE." /> + <Enum name="ACTIVE_HIGH__RISING" start="1" description="Active high - rising edge. Hardware trigger is active high or rising edge triggered, based on TRIGTYPE." /> + </BitField> + <BitField start="5" size="1" name="TRIGTYPE" description="Trigger Type. Selects hardware trigger as edge triggered or level triggered."> + <Enum name="EDGE" start="0" description="Edge. Hardware trigger is edge triggered." /> + <Enum name="LEVEL" start="1" description="Level. Hardware trigger is level triggered. Note that when level triggering without burst (BURSTPOWER = 0) is selected, only hardware triggers should be used on that channel." /> + </BitField> + <BitField start="6" size="1" name="TRIGBURST" description="Trigger Burst. Selects whether hardware triggers cause a single or burst transfer."> + <Enum name="SINGLE_TRANSFER" start="0" description="Single transfer. Hardware trigger causes a single transfer." /> + <Enum name="BURST_TRANSFER" start="1" description="Burst transfer. When the trigger for this channel is set to edge triggered, a hardware trigger causes a burst transfer, as defined by BURSTPOWER. When the trigger for this channel is set to level triggered, a hardware trigger causes transfers to continue as long as the trigger is asserted, unless the transfer is complete." /> + </BitField> + <BitField start="7" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="8" size="4" name="BURSTPOWER" description="Burst Power is used in two ways. It always selects the address wrap size when SrcBurstWrap and/or DstBurstWrap is modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many transfers are performed for each DMA trigger. This can be used, for example, with peripherals that contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). ... 1010: Burst size = 1024 (210). This corresponds to the maximum supported transfer count. others: not supported." /> + <BitField start="12" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="14" size="1" name="SRCBURSTWRAP" description="Source Burst Wrap. When enabled, the source data address for the DMA is wrapped, meaning that the source address range for each burst will be the same. As an example, this could be used to read several sequential registers from a peripheral for each DMA burst, reading the same registers again for each burst."> + <Enum name="DISABLED" start="0" description="Disabled. Source burst wrapping is not enabled for this DMA channel." /> + <Enum name="ENABLED" start="1" description="Enabled. Source burst wrapping is enabled for this DMA channel." /> + </BitField> + <BitField start="15" size="1" name="DSTBURSTWRAP" description="Destination Burst Wrap. When enabled, the destination data address for the DMA is wrapped, meaning that the destination address range for each burst will be the same. As an example, this could be used to write several sequential registers to a peripheral for each DMA burst, writing the same registers again for each burst."> + <Enum name="DISABLED" start="0" description="Disabled. Destination burst wrapping is not enabled for this DMA channel." /> + <Enum name="ENABLED" start="1" description="Enabled. Destination burst wrapping is enabled for this DMA channel." /> + </BitField> + <BitField start="16" size="2" name="CHPRIORITY" description="Priority of this channel when multiple DMA requests are pending. This description reflects a 2-bit priority field providing 4 priority levels. 0x0 = highest priority. 0x3 = lowest priority." /> + <BitField start="18" size="14" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x400+48" size="4" name="CFG3" access="Read/Write" description="Configuration register for DMA channel 0." reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="PERIPHREQEN" description="Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move, any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller."> + <Enum name="DISABLED" start="0" description="Disabled. Peripheral DMA requests are disabled." /> + <Enum name="ENABLED" start="1" description="Enabled. Peripheral DMA requests are enabled." /> + </BitField> + <BitField start="1" size="1" name="HWTRIGEN" description="Hardware Triggering Enable for this channel."> + <Enum name="DISABLED" start="0" description="Disabled. Hardware triggering is not used." /> + <Enum name="ENABLED" start="1" description="Enabled. Use hardware triggering." /> + </BitField> + <BitField start="2" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="4" size="1" name="TRIGPOL" description="Trigger Polarity. Selects the polarity of a hardware trigger for this channel."> + <Enum name="ACTIVE_LOW__FALLING" start="0" description="Active low - falling edge. Hardware trigger is active low or falling edge triggered, based on TRIGTYPE." /> + <Enum name="ACTIVE_HIGH__RISING" start="1" description="Active high - rising edge. Hardware trigger is active high or rising edge triggered, based on TRIGTYPE." /> + </BitField> + <BitField start="5" size="1" name="TRIGTYPE" description="Trigger Type. Selects hardware trigger as edge triggered or level triggered."> + <Enum name="EDGE" start="0" description="Edge. Hardware trigger is edge triggered." /> + <Enum name="LEVEL" start="1" description="Level. Hardware trigger is level triggered. Note that when level triggering without burst (BURSTPOWER = 0) is selected, only hardware triggers should be used on that channel." /> + </BitField> + <BitField start="6" size="1" name="TRIGBURST" description="Trigger Burst. Selects whether hardware triggers cause a single or burst transfer."> + <Enum name="SINGLE_TRANSFER" start="0" description="Single transfer. Hardware trigger causes a single transfer." /> + <Enum name="BURST_TRANSFER" start="1" description="Burst transfer. When the trigger for this channel is set to edge triggered, a hardware trigger causes a burst transfer, as defined by BURSTPOWER. When the trigger for this channel is set to level triggered, a hardware trigger causes transfers to continue as long as the trigger is asserted, unless the transfer is complete." /> + </BitField> + <BitField start="7" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="8" size="4" name="BURSTPOWER" description="Burst Power is used in two ways. It always selects the address wrap size when SrcBurstWrap and/or DstBurstWrap is modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many transfers are performed for each DMA trigger. This can be used, for example, with peripherals that contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). ... 1010: Burst size = 1024 (210). This corresponds to the maximum supported transfer count. others: not supported." /> + <BitField start="12" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="14" size="1" name="SRCBURSTWRAP" description="Source Burst Wrap. When enabled, the source data address for the DMA is wrapped, meaning that the source address range for each burst will be the same. As an example, this could be used to read several sequential registers from a peripheral for each DMA burst, reading the same registers again for each burst."> + <Enum name="DISABLED" start="0" description="Disabled. Source burst wrapping is not enabled for this DMA channel." /> + <Enum name="ENABLED" start="1" description="Enabled. Source burst wrapping is enabled for this DMA channel." /> + </BitField> + <BitField start="15" size="1" name="DSTBURSTWRAP" description="Destination Burst Wrap. When enabled, the destination data address for the DMA is wrapped, meaning that the destination address range for each burst will be the same. As an example, this could be used to write several sequential registers to a peripheral for each DMA burst, writing the same registers again for each burst."> + <Enum name="DISABLED" start="0" description="Disabled. Destination burst wrapping is not enabled for this DMA channel." /> + <Enum name="ENABLED" start="1" description="Enabled. Destination burst wrapping is enabled for this DMA channel." /> + </BitField> + <BitField start="16" size="2" name="CHPRIORITY" description="Priority of this channel when multiple DMA requests are pending. This description reflects a 2-bit priority field providing 4 priority levels. 0x0 = highest priority. 0x3 = lowest priority." /> + <BitField start="18" size="14" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x400+64" size="4" name="CFG4" access="Read/Write" description="Configuration register for DMA channel 0." reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="PERIPHREQEN" description="Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move, any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller."> + <Enum name="DISABLED" start="0" description="Disabled. Peripheral DMA requests are disabled." /> + <Enum name="ENABLED" start="1" description="Enabled. Peripheral DMA requests are enabled." /> + </BitField> + <BitField start="1" size="1" name="HWTRIGEN" description="Hardware Triggering Enable for this channel."> + <Enum name="DISABLED" start="0" description="Disabled. Hardware triggering is not used." /> + <Enum name="ENABLED" start="1" description="Enabled. Use hardware triggering." /> + </BitField> + <BitField start="2" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="4" size="1" name="TRIGPOL" description="Trigger Polarity. Selects the polarity of a hardware trigger for this channel."> + <Enum name="ACTIVE_LOW__FALLING" start="0" description="Active low - falling edge. Hardware trigger is active low or falling edge triggered, based on TRIGTYPE." /> + <Enum name="ACTIVE_HIGH__RISING" start="1" description="Active high - rising edge. Hardware trigger is active high or rising edge triggered, based on TRIGTYPE." /> + </BitField> + <BitField start="5" size="1" name="TRIGTYPE" description="Trigger Type. Selects hardware trigger as edge triggered or level triggered."> + <Enum name="EDGE" start="0" description="Edge. Hardware trigger is edge triggered." /> + <Enum name="LEVEL" start="1" description="Level. Hardware trigger is level triggered. Note that when level triggering without burst (BURSTPOWER = 0) is selected, only hardware triggers should be used on that channel." /> + </BitField> + <BitField start="6" size="1" name="TRIGBURST" description="Trigger Burst. Selects whether hardware triggers cause a single or burst transfer."> + <Enum name="SINGLE_TRANSFER" start="0" description="Single transfer. Hardware trigger causes a single transfer." /> + <Enum name="BURST_TRANSFER" start="1" description="Burst transfer. When the trigger for this channel is set to edge triggered, a hardware trigger causes a burst transfer, as defined by BURSTPOWER. When the trigger for this channel is set to level triggered, a hardware trigger causes transfers to continue as long as the trigger is asserted, unless the transfer is complete." /> + </BitField> + <BitField start="7" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="8" size="4" name="BURSTPOWER" description="Burst Power is used in two ways. It always selects the address wrap size when SrcBurstWrap and/or DstBurstWrap is modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many transfers are performed for each DMA trigger. This can be used, for example, with peripherals that contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). ... 1010: Burst size = 1024 (210). This corresponds to the maximum supported transfer count. others: not supported." /> + <BitField start="12" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="14" size="1" name="SRCBURSTWRAP" description="Source Burst Wrap. When enabled, the source data address for the DMA is wrapped, meaning that the source address range for each burst will be the same. As an example, this could be used to read several sequential registers from a peripheral for each DMA burst, reading the same registers again for each burst."> + <Enum name="DISABLED" start="0" description="Disabled. Source burst wrapping is not enabled for this DMA channel." /> + <Enum name="ENABLED" start="1" description="Enabled. Source burst wrapping is enabled for this DMA channel." /> + </BitField> + <BitField start="15" size="1" name="DSTBURSTWRAP" description="Destination Burst Wrap. When enabled, the destination data address for the DMA is wrapped, meaning that the destination address range for each burst will be the same. As an example, this could be used to write several sequential registers to a peripheral for each DMA burst, writing the same registers again for each burst."> + <Enum name="DISABLED" start="0" description="Disabled. Destination burst wrapping is not enabled for this DMA channel." /> + <Enum name="ENABLED" start="1" description="Enabled. Destination burst wrapping is enabled for this DMA channel." /> + </BitField> + <BitField start="16" size="2" name="CHPRIORITY" description="Priority of this channel when multiple DMA requests are pending. This description reflects a 2-bit priority field providing 4 priority levels. 0x0 = highest priority. 0x3 = lowest priority." /> + <BitField start="18" size="14" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x400+80" size="4" name="CFG5" access="Read/Write" description="Configuration register for DMA channel 0." reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="PERIPHREQEN" description="Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move, any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller."> + <Enum name="DISABLED" start="0" description="Disabled. Peripheral DMA requests are disabled." /> + <Enum name="ENABLED" start="1" description="Enabled. Peripheral DMA requests are enabled." /> + </BitField> + <BitField start="1" size="1" name="HWTRIGEN" description="Hardware Triggering Enable for this channel."> + <Enum name="DISABLED" start="0" description="Disabled. Hardware triggering is not used." /> + <Enum name="ENABLED" start="1" description="Enabled. Use hardware triggering." /> + </BitField> + <BitField start="2" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="4" size="1" name="TRIGPOL" description="Trigger Polarity. Selects the polarity of a hardware trigger for this channel."> + <Enum name="ACTIVE_LOW__FALLING" start="0" description="Active low - falling edge. Hardware trigger is active low or falling edge triggered, based on TRIGTYPE." /> + <Enum name="ACTIVE_HIGH__RISING" start="1" description="Active high - rising edge. Hardware trigger is active high or rising edge triggered, based on TRIGTYPE." /> + </BitField> + <BitField start="5" size="1" name="TRIGTYPE" description="Trigger Type. Selects hardware trigger as edge triggered or level triggered."> + <Enum name="EDGE" start="0" description="Edge. Hardware trigger is edge triggered." /> + <Enum name="LEVEL" start="1" description="Level. Hardware trigger is level triggered. Note that when level triggering without burst (BURSTPOWER = 0) is selected, only hardware triggers should be used on that channel." /> + </BitField> + <BitField start="6" size="1" name="TRIGBURST" description="Trigger Burst. Selects whether hardware triggers cause a single or burst transfer."> + <Enum name="SINGLE_TRANSFER" start="0" description="Single transfer. Hardware trigger causes a single transfer." /> + <Enum name="BURST_TRANSFER" start="1" description="Burst transfer. When the trigger for this channel is set to edge triggered, a hardware trigger causes a burst transfer, as defined by BURSTPOWER. When the trigger for this channel is set to level triggered, a hardware trigger causes transfers to continue as long as the trigger is asserted, unless the transfer is complete." /> + </BitField> + <BitField start="7" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="8" size="4" name="BURSTPOWER" description="Burst Power is used in two ways. It always selects the address wrap size when SrcBurstWrap and/or DstBurstWrap is modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many transfers are performed for each DMA trigger. This can be used, for example, with peripherals that contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). ... 1010: Burst size = 1024 (210). This corresponds to the maximum supported transfer count. others: not supported." /> + <BitField start="12" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="14" size="1" name="SRCBURSTWRAP" description="Source Burst Wrap. When enabled, the source data address for the DMA is wrapped, meaning that the source address range for each burst will be the same. As an example, this could be used to read several sequential registers from a peripheral for each DMA burst, reading the same registers again for each burst."> + <Enum name="DISABLED" start="0" description="Disabled. Source burst wrapping is not enabled for this DMA channel." /> + <Enum name="ENABLED" start="1" description="Enabled. Source burst wrapping is enabled for this DMA channel." /> + </BitField> + <BitField start="15" size="1" name="DSTBURSTWRAP" description="Destination Burst Wrap. When enabled, the destination data address for the DMA is wrapped, meaning that the destination address range for each burst will be the same. As an example, this could be used to write several sequential registers to a peripheral for each DMA burst, writing the same registers again for each burst."> + <Enum name="DISABLED" start="0" description="Disabled. Destination burst wrapping is not enabled for this DMA channel." /> + <Enum name="ENABLED" start="1" description="Enabled. Destination burst wrapping is enabled for this DMA channel." /> + </BitField> + <BitField start="16" size="2" name="CHPRIORITY" description="Priority of this channel when multiple DMA requests are pending. This description reflects a 2-bit priority field providing 4 priority levels. 0x0 = highest priority. 0x3 = lowest priority." /> + <BitField start="18" size="14" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x400+96" size="4" name="CFG6" access="Read/Write" description="Configuration register for DMA channel 0." reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="PERIPHREQEN" description="Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move, any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller."> + <Enum name="DISABLED" start="0" description="Disabled. Peripheral DMA requests are disabled." /> + <Enum name="ENABLED" start="1" description="Enabled. Peripheral DMA requests are enabled." /> + </BitField> + <BitField start="1" size="1" name="HWTRIGEN" description="Hardware Triggering Enable for this channel."> + <Enum name="DISABLED" start="0" description="Disabled. Hardware triggering is not used." /> + <Enum name="ENABLED" start="1" description="Enabled. Use hardware triggering." /> + </BitField> + <BitField start="2" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="4" size="1" name="TRIGPOL" description="Trigger Polarity. Selects the polarity of a hardware trigger for this channel."> + <Enum name="ACTIVE_LOW__FALLING" start="0" description="Active low - falling edge. Hardware trigger is active low or falling edge triggered, based on TRIGTYPE." /> + <Enum name="ACTIVE_HIGH__RISING" start="1" description="Active high - rising edge. Hardware trigger is active high or rising edge triggered, based on TRIGTYPE." /> + </BitField> + <BitField start="5" size="1" name="TRIGTYPE" description="Trigger Type. Selects hardware trigger as edge triggered or level triggered."> + <Enum name="EDGE" start="0" description="Edge. Hardware trigger is edge triggered." /> + <Enum name="LEVEL" start="1" description="Level. Hardware trigger is level triggered. Note that when level triggering without burst (BURSTPOWER = 0) is selected, only hardware triggers should be used on that channel." /> + </BitField> + <BitField start="6" size="1" name="TRIGBURST" description="Trigger Burst. Selects whether hardware triggers cause a single or burst transfer."> + <Enum name="SINGLE_TRANSFER" start="0" description="Single transfer. Hardware trigger causes a single transfer." /> + <Enum name="BURST_TRANSFER" start="1" description="Burst transfer. When the trigger for this channel is set to edge triggered, a hardware trigger causes a burst transfer, as defined by BURSTPOWER. When the trigger for this channel is set to level triggered, a hardware trigger causes transfers to continue as long as the trigger is asserted, unless the transfer is complete." /> + </BitField> + <BitField start="7" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="8" size="4" name="BURSTPOWER" description="Burst Power is used in two ways. It always selects the address wrap size when SrcBurstWrap and/or DstBurstWrap is modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many transfers are performed for each DMA trigger. This can be used, for example, with peripherals that contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). ... 1010: Burst size = 1024 (210). This corresponds to the maximum supported transfer count. others: not supported." /> + <BitField start="12" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="14" size="1" name="SRCBURSTWRAP" description="Source Burst Wrap. When enabled, the source data address for the DMA is wrapped, meaning that the source address range for each burst will be the same. As an example, this could be used to read several sequential registers from a peripheral for each DMA burst, reading the same registers again for each burst."> + <Enum name="DISABLED" start="0" description="Disabled. Source burst wrapping is not enabled for this DMA channel." /> + <Enum name="ENABLED" start="1" description="Enabled. Source burst wrapping is enabled for this DMA channel." /> + </BitField> + <BitField start="15" size="1" name="DSTBURSTWRAP" description="Destination Burst Wrap. When enabled, the destination data address for the DMA is wrapped, meaning that the destination address range for each burst will be the same. As an example, this could be used to write several sequential registers to a peripheral for each DMA burst, writing the same registers again for each burst."> + <Enum name="DISABLED" start="0" description="Disabled. Destination burst wrapping is not enabled for this DMA channel." /> + <Enum name="ENABLED" start="1" description="Enabled. Destination burst wrapping is enabled for this DMA channel." /> + </BitField> + <BitField start="16" size="2" name="CHPRIORITY" description="Priority of this channel when multiple DMA requests are pending. This description reflects a 2-bit priority field providing 4 priority levels. 0x0 = highest priority. 0x3 = lowest priority." /> + <BitField start="18" size="14" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x400+112" size="4" name="CFG7" access="Read/Write" description="Configuration register for DMA channel 0." reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="PERIPHREQEN" description="Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move, any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller."> + <Enum name="DISABLED" start="0" description="Disabled. Peripheral DMA requests are disabled." /> + <Enum name="ENABLED" start="1" description="Enabled. Peripheral DMA requests are enabled." /> + </BitField> + <BitField start="1" size="1" name="HWTRIGEN" description="Hardware Triggering Enable for this channel."> + <Enum name="DISABLED" start="0" description="Disabled. Hardware triggering is not used." /> + <Enum name="ENABLED" start="1" description="Enabled. Use hardware triggering." /> + </BitField> + <BitField start="2" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="4" size="1" name="TRIGPOL" description="Trigger Polarity. Selects the polarity of a hardware trigger for this channel."> + <Enum name="ACTIVE_LOW__FALLING" start="0" description="Active low - falling edge. Hardware trigger is active low or falling edge triggered, based on TRIGTYPE." /> + <Enum name="ACTIVE_HIGH__RISING" start="1" description="Active high - rising edge. Hardware trigger is active high or rising edge triggered, based on TRIGTYPE." /> + </BitField> + <BitField start="5" size="1" name="TRIGTYPE" description="Trigger Type. Selects hardware trigger as edge triggered or level triggered."> + <Enum name="EDGE" start="0" description="Edge. Hardware trigger is edge triggered." /> + <Enum name="LEVEL" start="1" description="Level. Hardware trigger is level triggered. Note that when level triggering without burst (BURSTPOWER = 0) is selected, only hardware triggers should be used on that channel." /> + </BitField> + <BitField start="6" size="1" name="TRIGBURST" description="Trigger Burst. Selects whether hardware triggers cause a single or burst transfer."> + <Enum name="SINGLE_TRANSFER" start="0" description="Single transfer. Hardware trigger causes a single transfer." /> + <Enum name="BURST_TRANSFER" start="1" description="Burst transfer. When the trigger for this channel is set to edge triggered, a hardware trigger causes a burst transfer, as defined by BURSTPOWER. When the trigger for this channel is set to level triggered, a hardware trigger causes transfers to continue as long as the trigger is asserted, unless the transfer is complete." /> + </BitField> + <BitField start="7" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="8" size="4" name="BURSTPOWER" description="Burst Power is used in two ways. It always selects the address wrap size when SrcBurstWrap and/or DstBurstWrap is modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many transfers are performed for each DMA trigger. This can be used, for example, with peripherals that contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). ... 1010: Burst size = 1024 (210). This corresponds to the maximum supported transfer count. others: not supported." /> + <BitField start="12" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="14" size="1" name="SRCBURSTWRAP" description="Source Burst Wrap. When enabled, the source data address for the DMA is wrapped, meaning that the source address range for each burst will be the same. As an example, this could be used to read several sequential registers from a peripheral for each DMA burst, reading the same registers again for each burst."> + <Enum name="DISABLED" start="0" description="Disabled. Source burst wrapping is not enabled for this DMA channel." /> + <Enum name="ENABLED" start="1" description="Enabled. Source burst wrapping is enabled for this DMA channel." /> + </BitField> + <BitField start="15" size="1" name="DSTBURSTWRAP" description="Destination Burst Wrap. When enabled, the destination data address for the DMA is wrapped, meaning that the destination address range for each burst will be the same. As an example, this could be used to write several sequential registers to a peripheral for each DMA burst, writing the same registers again for each burst."> + <Enum name="DISABLED" start="0" description="Disabled. Destination burst wrapping is not enabled for this DMA channel." /> + <Enum name="ENABLED" start="1" description="Enabled. Destination burst wrapping is enabled for this DMA channel." /> + </BitField> + <BitField start="16" size="2" name="CHPRIORITY" description="Priority of this channel when multiple DMA requests are pending. This description reflects a 2-bit priority field providing 4 priority levels. 0x0 = highest priority. 0x3 = lowest priority." /> + <BitField start="18" size="14" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x400+128" size="4" name="CFG8" access="Read/Write" description="Configuration register for DMA channel 0." reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="PERIPHREQEN" description="Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move, any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller."> + <Enum name="DISABLED" start="0" description="Disabled. Peripheral DMA requests are disabled." /> + <Enum name="ENABLED" start="1" description="Enabled. Peripheral DMA requests are enabled." /> + </BitField> + <BitField start="1" size="1" name="HWTRIGEN" description="Hardware Triggering Enable for this channel."> + <Enum name="DISABLED" start="0" description="Disabled. Hardware triggering is not used." /> + <Enum name="ENABLED" start="1" description="Enabled. Use hardware triggering." /> + </BitField> + <BitField start="2" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="4" size="1" name="TRIGPOL" description="Trigger Polarity. Selects the polarity of a hardware trigger for this channel."> + <Enum name="ACTIVE_LOW__FALLING" start="0" description="Active low - falling edge. Hardware trigger is active low or falling edge triggered, based on TRIGTYPE." /> + <Enum name="ACTIVE_HIGH__RISING" start="1" description="Active high - rising edge. Hardware trigger is active high or rising edge triggered, based on TRIGTYPE." /> + </BitField> + <BitField start="5" size="1" name="TRIGTYPE" description="Trigger Type. Selects hardware trigger as edge triggered or level triggered."> + <Enum name="EDGE" start="0" description="Edge. Hardware trigger is edge triggered." /> + <Enum name="LEVEL" start="1" description="Level. Hardware trigger is level triggered. Note that when level triggering without burst (BURSTPOWER = 0) is selected, only hardware triggers should be used on that channel." /> + </BitField> + <BitField start="6" size="1" name="TRIGBURST" description="Trigger Burst. Selects whether hardware triggers cause a single or burst transfer."> + <Enum name="SINGLE_TRANSFER" start="0" description="Single transfer. Hardware trigger causes a single transfer." /> + <Enum name="BURST_TRANSFER" start="1" description="Burst transfer. When the trigger for this channel is set to edge triggered, a hardware trigger causes a burst transfer, as defined by BURSTPOWER. When the trigger for this channel is set to level triggered, a hardware trigger causes transfers to continue as long as the trigger is asserted, unless the transfer is complete." /> + </BitField> + <BitField start="7" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="8" size="4" name="BURSTPOWER" description="Burst Power is used in two ways. It always selects the address wrap size when SrcBurstWrap and/or DstBurstWrap is modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many transfers are performed for each DMA trigger. This can be used, for example, with peripherals that contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). ... 1010: Burst size = 1024 (210). This corresponds to the maximum supported transfer count. others: not supported." /> + <BitField start="12" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="14" size="1" name="SRCBURSTWRAP" description="Source Burst Wrap. When enabled, the source data address for the DMA is wrapped, meaning that the source address range for each burst will be the same. As an example, this could be used to read several sequential registers from a peripheral for each DMA burst, reading the same registers again for each burst."> + <Enum name="DISABLED" start="0" description="Disabled. Source burst wrapping is not enabled for this DMA channel." /> + <Enum name="ENABLED" start="1" description="Enabled. Source burst wrapping is enabled for this DMA channel." /> + </BitField> + <BitField start="15" size="1" name="DSTBURSTWRAP" description="Destination Burst Wrap. When enabled, the destination data address for the DMA is wrapped, meaning that the destination address range for each burst will be the same. As an example, this could be used to write several sequential registers to a peripheral for each DMA burst, writing the same registers again for each burst."> + <Enum name="DISABLED" start="0" description="Disabled. Destination burst wrapping is not enabled for this DMA channel." /> + <Enum name="ENABLED" start="1" description="Enabled. Destination burst wrapping is enabled for this DMA channel." /> + </BitField> + <BitField start="16" size="2" name="CHPRIORITY" description="Priority of this channel when multiple DMA requests are pending. This description reflects a 2-bit priority field providing 4 priority levels. 0x0 = highest priority. 0x3 = lowest priority." /> + <BitField start="18" size="14" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x400+144" size="4" name="CFG9" access="Read/Write" description="Configuration register for DMA channel 0." reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="PERIPHREQEN" description="Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move, any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller."> + <Enum name="DISABLED" start="0" description="Disabled. Peripheral DMA requests are disabled." /> + <Enum name="ENABLED" start="1" description="Enabled. Peripheral DMA requests are enabled." /> + </BitField> + <BitField start="1" size="1" name="HWTRIGEN" description="Hardware Triggering Enable for this channel."> + <Enum name="DISABLED" start="0" description="Disabled. Hardware triggering is not used." /> + <Enum name="ENABLED" start="1" description="Enabled. Use hardware triggering." /> + </BitField> + <BitField start="2" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="4" size="1" name="TRIGPOL" description="Trigger Polarity. Selects the polarity of a hardware trigger for this channel."> + <Enum name="ACTIVE_LOW__FALLING" start="0" description="Active low - falling edge. Hardware trigger is active low or falling edge triggered, based on TRIGTYPE." /> + <Enum name="ACTIVE_HIGH__RISING" start="1" description="Active high - rising edge. Hardware trigger is active high or rising edge triggered, based on TRIGTYPE." /> + </BitField> + <BitField start="5" size="1" name="TRIGTYPE" description="Trigger Type. Selects hardware trigger as edge triggered or level triggered."> + <Enum name="EDGE" start="0" description="Edge. Hardware trigger is edge triggered." /> + <Enum name="LEVEL" start="1" description="Level. Hardware trigger is level triggered. Note that when level triggering without burst (BURSTPOWER = 0) is selected, only hardware triggers should be used on that channel." /> + </BitField> + <BitField start="6" size="1" name="TRIGBURST" description="Trigger Burst. Selects whether hardware triggers cause a single or burst transfer."> + <Enum name="SINGLE_TRANSFER" start="0" description="Single transfer. Hardware trigger causes a single transfer." /> + <Enum name="BURST_TRANSFER" start="1" description="Burst transfer. When the trigger for this channel is set to edge triggered, a hardware trigger causes a burst transfer, as defined by BURSTPOWER. When the trigger for this channel is set to level triggered, a hardware trigger causes transfers to continue as long as the trigger is asserted, unless the transfer is complete." /> + </BitField> + <BitField start="7" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="8" size="4" name="BURSTPOWER" description="Burst Power is used in two ways. It always selects the address wrap size when SrcBurstWrap and/or DstBurstWrap is modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many transfers are performed for each DMA trigger. This can be used, for example, with peripherals that contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). ... 1010: Burst size = 1024 (210). This corresponds to the maximum supported transfer count. others: not supported." /> + <BitField start="12" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="14" size="1" name="SRCBURSTWRAP" description="Source Burst Wrap. When enabled, the source data address for the DMA is wrapped, meaning that the source address range for each burst will be the same. As an example, this could be used to read several sequential registers from a peripheral for each DMA burst, reading the same registers again for each burst."> + <Enum name="DISABLED" start="0" description="Disabled. Source burst wrapping is not enabled for this DMA channel." /> + <Enum name="ENABLED" start="1" description="Enabled. Source burst wrapping is enabled for this DMA channel." /> + </BitField> + <BitField start="15" size="1" name="DSTBURSTWRAP" description="Destination Burst Wrap. When enabled, the destination data address for the DMA is wrapped, meaning that the destination address range for each burst will be the same. As an example, this could be used to write several sequential registers to a peripheral for each DMA burst, writing the same registers again for each burst."> + <Enum name="DISABLED" start="0" description="Disabled. Destination burst wrapping is not enabled for this DMA channel." /> + <Enum name="ENABLED" start="1" description="Enabled. Destination burst wrapping is enabled for this DMA channel." /> + </BitField> + <BitField start="16" size="2" name="CHPRIORITY" description="Priority of this channel when multiple DMA requests are pending. This description reflects a 2-bit priority field providing 4 priority levels. 0x0 = highest priority. 0x3 = lowest priority." /> + <BitField start="18" size="14" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x400+160" size="4" name="CFG10" access="Read/Write" description="Configuration register for DMA channel 0." reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="PERIPHREQEN" description="Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move, any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller."> + <Enum name="DISABLED" start="0" description="Disabled. Peripheral DMA requests are disabled." /> + <Enum name="ENABLED" start="1" description="Enabled. Peripheral DMA requests are enabled." /> + </BitField> + <BitField start="1" size="1" name="HWTRIGEN" description="Hardware Triggering Enable for this channel."> + <Enum name="DISABLED" start="0" description="Disabled. Hardware triggering is not used." /> + <Enum name="ENABLED" start="1" description="Enabled. Use hardware triggering." /> + </BitField> + <BitField start="2" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="4" size="1" name="TRIGPOL" description="Trigger Polarity. Selects the polarity of a hardware trigger for this channel."> + <Enum name="ACTIVE_LOW__FALLING" start="0" description="Active low - falling edge. Hardware trigger is active low or falling edge triggered, based on TRIGTYPE." /> + <Enum name="ACTIVE_HIGH__RISING" start="1" description="Active high - rising edge. Hardware trigger is active high or rising edge triggered, based on TRIGTYPE." /> + </BitField> + <BitField start="5" size="1" name="TRIGTYPE" description="Trigger Type. Selects hardware trigger as edge triggered or level triggered."> + <Enum name="EDGE" start="0" description="Edge. Hardware trigger is edge triggered." /> + <Enum name="LEVEL" start="1" description="Level. Hardware trigger is level triggered. Note that when level triggering without burst (BURSTPOWER = 0) is selected, only hardware triggers should be used on that channel." /> + </BitField> + <BitField start="6" size="1" name="TRIGBURST" description="Trigger Burst. Selects whether hardware triggers cause a single or burst transfer."> + <Enum name="SINGLE_TRANSFER" start="0" description="Single transfer. Hardware trigger causes a single transfer." /> + <Enum name="BURST_TRANSFER" start="1" description="Burst transfer. When the trigger for this channel is set to edge triggered, a hardware trigger causes a burst transfer, as defined by BURSTPOWER. When the trigger for this channel is set to level triggered, a hardware trigger causes transfers to continue as long as the trigger is asserted, unless the transfer is complete." /> + </BitField> + <BitField start="7" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="8" size="4" name="BURSTPOWER" description="Burst Power is used in two ways. It always selects the address wrap size when SrcBurstWrap and/or DstBurstWrap is modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many transfers are performed for each DMA trigger. This can be used, for example, with peripherals that contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). ... 1010: Burst size = 1024 (210). This corresponds to the maximum supported transfer count. others: not supported." /> + <BitField start="12" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="14" size="1" name="SRCBURSTWRAP" description="Source Burst Wrap. When enabled, the source data address for the DMA is wrapped, meaning that the source address range for each burst will be the same. As an example, this could be used to read several sequential registers from a peripheral for each DMA burst, reading the same registers again for each burst."> + <Enum name="DISABLED" start="0" description="Disabled. Source burst wrapping is not enabled for this DMA channel." /> + <Enum name="ENABLED" start="1" description="Enabled. Source burst wrapping is enabled for this DMA channel." /> + </BitField> + <BitField start="15" size="1" name="DSTBURSTWRAP" description="Destination Burst Wrap. When enabled, the destination data address for the DMA is wrapped, meaning that the destination address range for each burst will be the same. As an example, this could be used to write several sequential registers to a peripheral for each DMA burst, writing the same registers again for each burst."> + <Enum name="DISABLED" start="0" description="Disabled. Destination burst wrapping is not enabled for this DMA channel." /> + <Enum name="ENABLED" start="1" description="Enabled. Destination burst wrapping is enabled for this DMA channel." /> + </BitField> + <BitField start="16" size="2" name="CHPRIORITY" description="Priority of this channel when multiple DMA requests are pending. This description reflects a 2-bit priority field providing 4 priority levels. 0x0 = highest priority. 0x3 = lowest priority." /> + <BitField start="18" size="14" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x400+176" size="4" name="CFG11" access="Read/Write" description="Configuration register for DMA channel 0." reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="PERIPHREQEN" description="Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move, any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller."> + <Enum name="DISABLED" start="0" description="Disabled. Peripheral DMA requests are disabled." /> + <Enum name="ENABLED" start="1" description="Enabled. Peripheral DMA requests are enabled." /> + </BitField> + <BitField start="1" size="1" name="HWTRIGEN" description="Hardware Triggering Enable for this channel."> + <Enum name="DISABLED" start="0" description="Disabled. Hardware triggering is not used." /> + <Enum name="ENABLED" start="1" description="Enabled. Use hardware triggering." /> + </BitField> + <BitField start="2" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="4" size="1" name="TRIGPOL" description="Trigger Polarity. Selects the polarity of a hardware trigger for this channel."> + <Enum name="ACTIVE_LOW__FALLING" start="0" description="Active low - falling edge. Hardware trigger is active low or falling edge triggered, based on TRIGTYPE." /> + <Enum name="ACTIVE_HIGH__RISING" start="1" description="Active high - rising edge. Hardware trigger is active high or rising edge triggered, based on TRIGTYPE." /> + </BitField> + <BitField start="5" size="1" name="TRIGTYPE" description="Trigger Type. Selects hardware trigger as edge triggered or level triggered."> + <Enum name="EDGE" start="0" description="Edge. Hardware trigger is edge triggered." /> + <Enum name="LEVEL" start="1" description="Level. Hardware trigger is level triggered. Note that when level triggering without burst (BURSTPOWER = 0) is selected, only hardware triggers should be used on that channel." /> + </BitField> + <BitField start="6" size="1" name="TRIGBURST" description="Trigger Burst. Selects whether hardware triggers cause a single or burst transfer."> + <Enum name="SINGLE_TRANSFER" start="0" description="Single transfer. Hardware trigger causes a single transfer." /> + <Enum name="BURST_TRANSFER" start="1" description="Burst transfer. When the trigger for this channel is set to edge triggered, a hardware trigger causes a burst transfer, as defined by BURSTPOWER. When the trigger for this channel is set to level triggered, a hardware trigger causes transfers to continue as long as the trigger is asserted, unless the transfer is complete." /> + </BitField> + <BitField start="7" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="8" size="4" name="BURSTPOWER" description="Burst Power is used in two ways. It always selects the address wrap size when SrcBurstWrap and/or DstBurstWrap is modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many transfers are performed for each DMA trigger. This can be used, for example, with peripherals that contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). ... 1010: Burst size = 1024 (210). This corresponds to the maximum supported transfer count. others: not supported." /> + <BitField start="12" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="14" size="1" name="SRCBURSTWRAP" description="Source Burst Wrap. When enabled, the source data address for the DMA is wrapped, meaning that the source address range for each burst will be the same. As an example, this could be used to read several sequential registers from a peripheral for each DMA burst, reading the same registers again for each burst."> + <Enum name="DISABLED" start="0" description="Disabled. Source burst wrapping is not enabled for this DMA channel." /> + <Enum name="ENABLED" start="1" description="Enabled. Source burst wrapping is enabled for this DMA channel." /> + </BitField> + <BitField start="15" size="1" name="DSTBURSTWRAP" description="Destination Burst Wrap. When enabled, the destination data address for the DMA is wrapped, meaning that the destination address range for each burst will be the same. As an example, this could be used to write several sequential registers to a peripheral for each DMA burst, writing the same registers again for each burst."> + <Enum name="DISABLED" start="0" description="Disabled. Destination burst wrapping is not enabled for this DMA channel." /> + <Enum name="ENABLED" start="1" description="Enabled. Destination burst wrapping is enabled for this DMA channel." /> + </BitField> + <BitField start="16" size="2" name="CHPRIORITY" description="Priority of this channel when multiple DMA requests are pending. This description reflects a 2-bit priority field providing 4 priority levels. 0x0 = highest priority. 0x3 = lowest priority." /> + <BitField start="18" size="14" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x400+192" size="4" name="CFG12" access="Read/Write" description="Configuration register for DMA channel 0." reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="PERIPHREQEN" description="Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move, any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller."> + <Enum name="DISABLED" start="0" description="Disabled. Peripheral DMA requests are disabled." /> + <Enum name="ENABLED" start="1" description="Enabled. Peripheral DMA requests are enabled." /> + </BitField> + <BitField start="1" size="1" name="HWTRIGEN" description="Hardware Triggering Enable for this channel."> + <Enum name="DISABLED" start="0" description="Disabled. Hardware triggering is not used." /> + <Enum name="ENABLED" start="1" description="Enabled. Use hardware triggering." /> + </BitField> + <BitField start="2" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="4" size="1" name="TRIGPOL" description="Trigger Polarity. Selects the polarity of a hardware trigger for this channel."> + <Enum name="ACTIVE_LOW__FALLING" start="0" description="Active low - falling edge. Hardware trigger is active low or falling edge triggered, based on TRIGTYPE." /> + <Enum name="ACTIVE_HIGH__RISING" start="1" description="Active high - rising edge. Hardware trigger is active high or rising edge triggered, based on TRIGTYPE." /> + </BitField> + <BitField start="5" size="1" name="TRIGTYPE" description="Trigger Type. Selects hardware trigger as edge triggered or level triggered."> + <Enum name="EDGE" start="0" description="Edge. Hardware trigger is edge triggered." /> + <Enum name="LEVEL" start="1" description="Level. Hardware trigger is level triggered. Note that when level triggering without burst (BURSTPOWER = 0) is selected, only hardware triggers should be used on that channel." /> + </BitField> + <BitField start="6" size="1" name="TRIGBURST" description="Trigger Burst. Selects whether hardware triggers cause a single or burst transfer."> + <Enum name="SINGLE_TRANSFER" start="0" description="Single transfer. Hardware trigger causes a single transfer." /> + <Enum name="BURST_TRANSFER" start="1" description="Burst transfer. When the trigger for this channel is set to edge triggered, a hardware trigger causes a burst transfer, as defined by BURSTPOWER. When the trigger for this channel is set to level triggered, a hardware trigger causes transfers to continue as long as the trigger is asserted, unless the transfer is complete." /> + </BitField> + <BitField start="7" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="8" size="4" name="BURSTPOWER" description="Burst Power is used in two ways. It always selects the address wrap size when SrcBurstWrap and/or DstBurstWrap is modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many transfers are performed for each DMA trigger. This can be used, for example, with peripherals that contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). ... 1010: Burst size = 1024 (210). This corresponds to the maximum supported transfer count. others: not supported." /> + <BitField start="12" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="14" size="1" name="SRCBURSTWRAP" description="Source Burst Wrap. When enabled, the source data address for the DMA is wrapped, meaning that the source address range for each burst will be the same. As an example, this could be used to read several sequential registers from a peripheral for each DMA burst, reading the same registers again for each burst."> + <Enum name="DISABLED" start="0" description="Disabled. Source burst wrapping is not enabled for this DMA channel." /> + <Enum name="ENABLED" start="1" description="Enabled. Source burst wrapping is enabled for this DMA channel." /> + </BitField> + <BitField start="15" size="1" name="DSTBURSTWRAP" description="Destination Burst Wrap. When enabled, the destination data address for the DMA is wrapped, meaning that the destination address range for each burst will be the same. As an example, this could be used to write several sequential registers to a peripheral for each DMA burst, writing the same registers again for each burst."> + <Enum name="DISABLED" start="0" description="Disabled. Destination burst wrapping is not enabled for this DMA channel." /> + <Enum name="ENABLED" start="1" description="Enabled. Destination burst wrapping is enabled for this DMA channel." /> + </BitField> + <BitField start="16" size="2" name="CHPRIORITY" description="Priority of this channel when multiple DMA requests are pending. This description reflects a 2-bit priority field providing 4 priority levels. 0x0 = highest priority. 0x3 = lowest priority." /> + <BitField start="18" size="14" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x400+208" size="4" name="CFG13" access="Read/Write" description="Configuration register for DMA channel 0." reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="PERIPHREQEN" description="Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move, any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller."> + <Enum name="DISABLED" start="0" description="Disabled. Peripheral DMA requests are disabled." /> + <Enum name="ENABLED" start="1" description="Enabled. Peripheral DMA requests are enabled." /> + </BitField> + <BitField start="1" size="1" name="HWTRIGEN" description="Hardware Triggering Enable for this channel."> + <Enum name="DISABLED" start="0" description="Disabled. Hardware triggering is not used." /> + <Enum name="ENABLED" start="1" description="Enabled. Use hardware triggering." /> + </BitField> + <BitField start="2" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="4" size="1" name="TRIGPOL" description="Trigger Polarity. Selects the polarity of a hardware trigger for this channel."> + <Enum name="ACTIVE_LOW__FALLING" start="0" description="Active low - falling edge. Hardware trigger is active low or falling edge triggered, based on TRIGTYPE." /> + <Enum name="ACTIVE_HIGH__RISING" start="1" description="Active high - rising edge. Hardware trigger is active high or rising edge triggered, based on TRIGTYPE." /> + </BitField> + <BitField start="5" size="1" name="TRIGTYPE" description="Trigger Type. Selects hardware trigger as edge triggered or level triggered."> + <Enum name="EDGE" start="0" description="Edge. Hardware trigger is edge triggered." /> + <Enum name="LEVEL" start="1" description="Level. Hardware trigger is level triggered. Note that when level triggering without burst (BURSTPOWER = 0) is selected, only hardware triggers should be used on that channel." /> + </BitField> + <BitField start="6" size="1" name="TRIGBURST" description="Trigger Burst. Selects whether hardware triggers cause a single or burst transfer."> + <Enum name="SINGLE_TRANSFER" start="0" description="Single transfer. Hardware trigger causes a single transfer." /> + <Enum name="BURST_TRANSFER" start="1" description="Burst transfer. When the trigger for this channel is set to edge triggered, a hardware trigger causes a burst transfer, as defined by BURSTPOWER. When the trigger for this channel is set to level triggered, a hardware trigger causes transfers to continue as long as the trigger is asserted, unless the transfer is complete." /> + </BitField> + <BitField start="7" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="8" size="4" name="BURSTPOWER" description="Burst Power is used in two ways. It always selects the address wrap size when SrcBurstWrap and/or DstBurstWrap is modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many transfers are performed for each DMA trigger. This can be used, for example, with peripherals that contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). ... 1010: Burst size = 1024 (210). This corresponds to the maximum supported transfer count. others: not supported." /> + <BitField start="12" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="14" size="1" name="SRCBURSTWRAP" description="Source Burst Wrap. When enabled, the source data address for the DMA is wrapped, meaning that the source address range for each burst will be the same. As an example, this could be used to read several sequential registers from a peripheral for each DMA burst, reading the same registers again for each burst."> + <Enum name="DISABLED" start="0" description="Disabled. Source burst wrapping is not enabled for this DMA channel." /> + <Enum name="ENABLED" start="1" description="Enabled. Source burst wrapping is enabled for this DMA channel." /> + </BitField> + <BitField start="15" size="1" name="DSTBURSTWRAP" description="Destination Burst Wrap. When enabled, the destination data address for the DMA is wrapped, meaning that the destination address range for each burst will be the same. As an example, this could be used to write several sequential registers to a peripheral for each DMA burst, writing the same registers again for each burst."> + <Enum name="DISABLED" start="0" description="Disabled. Destination burst wrapping is not enabled for this DMA channel." /> + <Enum name="ENABLED" start="1" description="Enabled. Destination burst wrapping is enabled for this DMA channel." /> + </BitField> + <BitField start="16" size="2" name="CHPRIORITY" description="Priority of this channel when multiple DMA requests are pending. This description reflects a 2-bit priority field providing 4 priority levels. 0x0 = highest priority. 0x3 = lowest priority." /> + <BitField start="18" size="14" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x400+224" size="4" name="CFG14" access="Read/Write" description="Configuration register for DMA channel 0." reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="PERIPHREQEN" description="Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move, any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller."> + <Enum name="DISABLED" start="0" description="Disabled. Peripheral DMA requests are disabled." /> + <Enum name="ENABLED" start="1" description="Enabled. Peripheral DMA requests are enabled." /> + </BitField> + <BitField start="1" size="1" name="HWTRIGEN" description="Hardware Triggering Enable for this channel."> + <Enum name="DISABLED" start="0" description="Disabled. Hardware triggering is not used." /> + <Enum name="ENABLED" start="1" description="Enabled. Use hardware triggering." /> + </BitField> + <BitField start="2" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="4" size="1" name="TRIGPOL" description="Trigger Polarity. Selects the polarity of a hardware trigger for this channel."> + <Enum name="ACTIVE_LOW__FALLING" start="0" description="Active low - falling edge. Hardware trigger is active low or falling edge triggered, based on TRIGTYPE." /> + <Enum name="ACTIVE_HIGH__RISING" start="1" description="Active high - rising edge. Hardware trigger is active high or rising edge triggered, based on TRIGTYPE." /> + </BitField> + <BitField start="5" size="1" name="TRIGTYPE" description="Trigger Type. Selects hardware trigger as edge triggered or level triggered."> + <Enum name="EDGE" start="0" description="Edge. Hardware trigger is edge triggered." /> + <Enum name="LEVEL" start="1" description="Level. Hardware trigger is level triggered. Note that when level triggering without burst (BURSTPOWER = 0) is selected, only hardware triggers should be used on that channel." /> + </BitField> + <BitField start="6" size="1" name="TRIGBURST" description="Trigger Burst. Selects whether hardware triggers cause a single or burst transfer."> + <Enum name="SINGLE_TRANSFER" start="0" description="Single transfer. Hardware trigger causes a single transfer." /> + <Enum name="BURST_TRANSFER" start="1" description="Burst transfer. When the trigger for this channel is set to edge triggered, a hardware trigger causes a burst transfer, as defined by BURSTPOWER. When the trigger for this channel is set to level triggered, a hardware trigger causes transfers to continue as long as the trigger is asserted, unless the transfer is complete." /> + </BitField> + <BitField start="7" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="8" size="4" name="BURSTPOWER" description="Burst Power is used in two ways. It always selects the address wrap size when SrcBurstWrap and/or DstBurstWrap is modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many transfers are performed for each DMA trigger. This can be used, for example, with peripherals that contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). ... 1010: Burst size = 1024 (210). This corresponds to the maximum supported transfer count. others: not supported." /> + <BitField start="12" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="14" size="1" name="SRCBURSTWRAP" description="Source Burst Wrap. When enabled, the source data address for the DMA is wrapped, meaning that the source address range for each burst will be the same. As an example, this could be used to read several sequential registers from a peripheral for each DMA burst, reading the same registers again for each burst."> + <Enum name="DISABLED" start="0" description="Disabled. Source burst wrapping is not enabled for this DMA channel." /> + <Enum name="ENABLED" start="1" description="Enabled. Source burst wrapping is enabled for this DMA channel." /> + </BitField> + <BitField start="15" size="1" name="DSTBURSTWRAP" description="Destination Burst Wrap. When enabled, the destination data address for the DMA is wrapped, meaning that the destination address range for each burst will be the same. As an example, this could be used to write several sequential registers to a peripheral for each DMA burst, writing the same registers again for each burst."> + <Enum name="DISABLED" start="0" description="Disabled. Destination burst wrapping is not enabled for this DMA channel." /> + <Enum name="ENABLED" start="1" description="Enabled. Destination burst wrapping is enabled for this DMA channel." /> + </BitField> + <BitField start="16" size="2" name="CHPRIORITY" description="Priority of this channel when multiple DMA requests are pending. This description reflects a 2-bit priority field providing 4 priority levels. 0x0 = highest priority. 0x3 = lowest priority." /> + <BitField start="18" size="14" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x400+240" size="4" name="CFG15" access="Read/Write" description="Configuration register for DMA channel 0." reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="PERIPHREQEN" description="Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move, any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller."> + <Enum name="DISABLED" start="0" description="Disabled. Peripheral DMA requests are disabled." /> + <Enum name="ENABLED" start="1" description="Enabled. Peripheral DMA requests are enabled." /> + </BitField> + <BitField start="1" size="1" name="HWTRIGEN" description="Hardware Triggering Enable for this channel."> + <Enum name="DISABLED" start="0" description="Disabled. Hardware triggering is not used." /> + <Enum name="ENABLED" start="1" description="Enabled. Use hardware triggering." /> + </BitField> + <BitField start="2" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="4" size="1" name="TRIGPOL" description="Trigger Polarity. Selects the polarity of a hardware trigger for this channel."> + <Enum name="ACTIVE_LOW__FALLING" start="0" description="Active low - falling edge. Hardware trigger is active low or falling edge triggered, based on TRIGTYPE." /> + <Enum name="ACTIVE_HIGH__RISING" start="1" description="Active high - rising edge. Hardware trigger is active high or rising edge triggered, based on TRIGTYPE." /> + </BitField> + <BitField start="5" size="1" name="TRIGTYPE" description="Trigger Type. Selects hardware trigger as edge triggered or level triggered."> + <Enum name="EDGE" start="0" description="Edge. Hardware trigger is edge triggered." /> + <Enum name="LEVEL" start="1" description="Level. Hardware trigger is level triggered. Note that when level triggering without burst (BURSTPOWER = 0) is selected, only hardware triggers should be used on that channel." /> + </BitField> + <BitField start="6" size="1" name="TRIGBURST" description="Trigger Burst. Selects whether hardware triggers cause a single or burst transfer."> + <Enum name="SINGLE_TRANSFER" start="0" description="Single transfer. Hardware trigger causes a single transfer." /> + <Enum name="BURST_TRANSFER" start="1" description="Burst transfer. When the trigger for this channel is set to edge triggered, a hardware trigger causes a burst transfer, as defined by BURSTPOWER. When the trigger for this channel is set to level triggered, a hardware trigger causes transfers to continue as long as the trigger is asserted, unless the transfer is complete." /> + </BitField> + <BitField start="7" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="8" size="4" name="BURSTPOWER" description="Burst Power is used in two ways. It always selects the address wrap size when SrcBurstWrap and/or DstBurstWrap is modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many transfers are performed for each DMA trigger. This can be used, for example, with peripherals that contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). ... 1010: Burst size = 1024 (210). This corresponds to the maximum supported transfer count. others: not supported." /> + <BitField start="12" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="14" size="1" name="SRCBURSTWRAP" description="Source Burst Wrap. When enabled, the source data address for the DMA is wrapped, meaning that the source address range for each burst will be the same. As an example, this could be used to read several sequential registers from a peripheral for each DMA burst, reading the same registers again for each burst."> + <Enum name="DISABLED" start="0" description="Disabled. Source burst wrapping is not enabled for this DMA channel." /> + <Enum name="ENABLED" start="1" description="Enabled. Source burst wrapping is enabled for this DMA channel." /> + </BitField> + <BitField start="15" size="1" name="DSTBURSTWRAP" description="Destination Burst Wrap. When enabled, the destination data address for the DMA is wrapped, meaning that the destination address range for each burst will be the same. As an example, this could be used to write several sequential registers to a peripheral for each DMA burst, writing the same registers again for each burst."> + <Enum name="DISABLED" start="0" description="Disabled. Destination burst wrapping is not enabled for this DMA channel." /> + <Enum name="ENABLED" start="1" description="Enabled. Destination burst wrapping is enabled for this DMA channel." /> + </BitField> + <BitField start="16" size="2" name="CHPRIORITY" description="Priority of this channel when multiple DMA requests are pending. This description reflects a 2-bit priority field providing 4 priority levels. 0x0 = highest priority. 0x3 = lowest priority." /> + <BitField start="18" size="14" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x404+0" size="4" name="CTLSTAT0" access="ReadOnly" description="Control and status register for DMA channel 0." reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="VALIDPENDING" description="Valid pending flag for this channel. This bit is set when a 1 is written to the corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel."> + <Enum name="NO_EFFECT_ON_DMA_OPE" start="0" description="No effect on DMA operation." /> + <Enum name="VALID_PENDING" start="1" description="Valid pending." /> + </BitField> + <BitField start="1" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="2" size="1" name="TRIG" description="Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1."> + <Enum name="NOT_TRIGGERED" start="0" description="Not triggered. The trigger for this DMA channel is not set. DMA operations will not be carried out." /> + <Enum name="TRIGGERED" start="1" description="Triggered. The trigger for this DMA channel is set. DMA operations will be carried out." /> + </BitField> + <BitField start="3" size="29" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x404+16" size="4" name="CTLSTAT1" access="ReadOnly" description="Control and status register for DMA channel 0." reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="VALIDPENDING" description="Valid pending flag for this channel. This bit is set when a 1 is written to the corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel."> + <Enum name="NO_EFFECT_ON_DMA_OPE" start="0" description="No effect on DMA operation." /> + <Enum name="VALID_PENDING" start="1" description="Valid pending." /> + </BitField> + <BitField start="1" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="2" size="1" name="TRIG" description="Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1."> + <Enum name="NOT_TRIGGERED" start="0" description="Not triggered. The trigger for this DMA channel is not set. DMA operations will not be carried out." /> + <Enum name="TRIGGERED" start="1" description="Triggered. The trigger for this DMA channel is set. DMA operations will be carried out." /> + </BitField> + <BitField start="3" size="29" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x404+32" size="4" name="CTLSTAT2" access="ReadOnly" description="Control and status register for DMA channel 0." reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="VALIDPENDING" description="Valid pending flag for this channel. This bit is set when a 1 is written to the corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel."> + <Enum name="NO_EFFECT_ON_DMA_OPE" start="0" description="No effect on DMA operation." /> + <Enum name="VALID_PENDING" start="1" description="Valid pending." /> + </BitField> + <BitField start="1" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="2" size="1" name="TRIG" description="Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1."> + <Enum name="NOT_TRIGGERED" start="0" description="Not triggered. The trigger for this DMA channel is not set. DMA operations will not be carried out." /> + <Enum name="TRIGGERED" start="1" description="Triggered. The trigger for this DMA channel is set. DMA operations will be carried out." /> + </BitField> + <BitField start="3" size="29" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x404+48" size="4" name="CTLSTAT3" access="ReadOnly" description="Control and status register for DMA channel 0." reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="VALIDPENDING" description="Valid pending flag for this channel. This bit is set when a 1 is written to the corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel."> + <Enum name="NO_EFFECT_ON_DMA_OPE" start="0" description="No effect on DMA operation." /> + <Enum name="VALID_PENDING" start="1" description="Valid pending." /> + </BitField> + <BitField start="1" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="2" size="1" name="TRIG" description="Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1."> + <Enum name="NOT_TRIGGERED" start="0" description="Not triggered. The trigger for this DMA channel is not set. DMA operations will not be carried out." /> + <Enum name="TRIGGERED" start="1" description="Triggered. The trigger for this DMA channel is set. DMA operations will be carried out." /> + </BitField> + <BitField start="3" size="29" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x404+64" size="4" name="CTLSTAT4" access="ReadOnly" description="Control and status register for DMA channel 0." reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="VALIDPENDING" description="Valid pending flag for this channel. This bit is set when a 1 is written to the corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel."> + <Enum name="NO_EFFECT_ON_DMA_OPE" start="0" description="No effect on DMA operation." /> + <Enum name="VALID_PENDING" start="1" description="Valid pending." /> + </BitField> + <BitField start="1" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="2" size="1" name="TRIG" description="Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1."> + <Enum name="NOT_TRIGGERED" start="0" description="Not triggered. The trigger for this DMA channel is not set. DMA operations will not be carried out." /> + <Enum name="TRIGGERED" start="1" description="Triggered. The trigger for this DMA channel is set. DMA operations will be carried out." /> + </BitField> + <BitField start="3" size="29" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x404+80" size="4" name="CTLSTAT5" access="ReadOnly" description="Control and status register for DMA channel 0." reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="VALIDPENDING" description="Valid pending flag for this channel. This bit is set when a 1 is written to the corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel."> + <Enum name="NO_EFFECT_ON_DMA_OPE" start="0" description="No effect on DMA operation." /> + <Enum name="VALID_PENDING" start="1" description="Valid pending." /> + </BitField> + <BitField start="1" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="2" size="1" name="TRIG" description="Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1."> + <Enum name="NOT_TRIGGERED" start="0" description="Not triggered. The trigger for this DMA channel is not set. DMA operations will not be carried out." /> + <Enum name="TRIGGERED" start="1" description="Triggered. The trigger for this DMA channel is set. DMA operations will be carried out." /> + </BitField> + <BitField start="3" size="29" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x404+96" size="4" name="CTLSTAT6" access="ReadOnly" description="Control and status register for DMA channel 0." reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="VALIDPENDING" description="Valid pending flag for this channel. This bit is set when a 1 is written to the corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel."> + <Enum name="NO_EFFECT_ON_DMA_OPE" start="0" description="No effect on DMA operation." /> + <Enum name="VALID_PENDING" start="1" description="Valid pending." /> + </BitField> + <BitField start="1" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="2" size="1" name="TRIG" description="Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1."> + <Enum name="NOT_TRIGGERED" start="0" description="Not triggered. The trigger for this DMA channel is not set. DMA operations will not be carried out." /> + <Enum name="TRIGGERED" start="1" description="Triggered. The trigger for this DMA channel is set. DMA operations will be carried out." /> + </BitField> + <BitField start="3" size="29" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x404+112" size="4" name="CTLSTAT7" access="ReadOnly" description="Control and status register for DMA channel 0." reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="VALIDPENDING" description="Valid pending flag for this channel. This bit is set when a 1 is written to the corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel."> + <Enum name="NO_EFFECT_ON_DMA_OPE" start="0" description="No effect on DMA operation." /> + <Enum name="VALID_PENDING" start="1" description="Valid pending." /> + </BitField> + <BitField start="1" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="2" size="1" name="TRIG" description="Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1."> + <Enum name="NOT_TRIGGERED" start="0" description="Not triggered. The trigger for this DMA channel is not set. DMA operations will not be carried out." /> + <Enum name="TRIGGERED" start="1" description="Triggered. The trigger for this DMA channel is set. DMA operations will be carried out." /> + </BitField> + <BitField start="3" size="29" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x404+128" size="4" name="CTLSTAT8" access="ReadOnly" description="Control and status register for DMA channel 0." reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="VALIDPENDING" description="Valid pending flag for this channel. This bit is set when a 1 is written to the corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel."> + <Enum name="NO_EFFECT_ON_DMA_OPE" start="0" description="No effect on DMA operation." /> + <Enum name="VALID_PENDING" start="1" description="Valid pending." /> + </BitField> + <BitField start="1" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="2" size="1" name="TRIG" description="Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1."> + <Enum name="NOT_TRIGGERED" start="0" description="Not triggered. The trigger for this DMA channel is not set. DMA operations will not be carried out." /> + <Enum name="TRIGGERED" start="1" description="Triggered. The trigger for this DMA channel is set. DMA operations will be carried out." /> + </BitField> + <BitField start="3" size="29" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x404+144" size="4" name="CTLSTAT9" access="ReadOnly" description="Control and status register for DMA channel 0." reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="VALIDPENDING" description="Valid pending flag for this channel. This bit is set when a 1 is written to the corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel."> + <Enum name="NO_EFFECT_ON_DMA_OPE" start="0" description="No effect on DMA operation." /> + <Enum name="VALID_PENDING" start="1" description="Valid pending." /> + </BitField> + <BitField start="1" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="2" size="1" name="TRIG" description="Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1."> + <Enum name="NOT_TRIGGERED" start="0" description="Not triggered. The trigger for this DMA channel is not set. DMA operations will not be carried out." /> + <Enum name="TRIGGERED" start="1" description="Triggered. The trigger for this DMA channel is set. DMA operations will be carried out." /> + </BitField> + <BitField start="3" size="29" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x404+160" size="4" name="CTLSTAT10" access="ReadOnly" description="Control and status register for DMA channel 0." reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="VALIDPENDING" description="Valid pending flag for this channel. This bit is set when a 1 is written to the corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel."> + <Enum name="NO_EFFECT_ON_DMA_OPE" start="0" description="No effect on DMA operation." /> + <Enum name="VALID_PENDING" start="1" description="Valid pending." /> + </BitField> + <BitField start="1" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="2" size="1" name="TRIG" description="Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1."> + <Enum name="NOT_TRIGGERED" start="0" description="Not triggered. The trigger for this DMA channel is not set. DMA operations will not be carried out." /> + <Enum name="TRIGGERED" start="1" description="Triggered. The trigger for this DMA channel is set. DMA operations will be carried out." /> + </BitField> + <BitField start="3" size="29" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x404+176" size="4" name="CTLSTAT11" access="ReadOnly" description="Control and status register for DMA channel 0." reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="VALIDPENDING" description="Valid pending flag for this channel. This bit is set when a 1 is written to the corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel."> + <Enum name="NO_EFFECT_ON_DMA_OPE" start="0" description="No effect on DMA operation." /> + <Enum name="VALID_PENDING" start="1" description="Valid pending." /> + </BitField> + <BitField start="1" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="2" size="1" name="TRIG" description="Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1."> + <Enum name="NOT_TRIGGERED" start="0" description="Not triggered. The trigger for this DMA channel is not set. DMA operations will not be carried out." /> + <Enum name="TRIGGERED" start="1" description="Triggered. The trigger for this DMA channel is set. DMA operations will be carried out." /> + </BitField> + <BitField start="3" size="29" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x404+192" size="4" name="CTLSTAT12" access="ReadOnly" description="Control and status register for DMA channel 0." reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="VALIDPENDING" description="Valid pending flag for this channel. This bit is set when a 1 is written to the corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel."> + <Enum name="NO_EFFECT_ON_DMA_OPE" start="0" description="No effect on DMA operation." /> + <Enum name="VALID_PENDING" start="1" description="Valid pending." /> + </BitField> + <BitField start="1" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="2" size="1" name="TRIG" description="Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1."> + <Enum name="NOT_TRIGGERED" start="0" description="Not triggered. The trigger for this DMA channel is not set. DMA operations will not be carried out." /> + <Enum name="TRIGGERED" start="1" description="Triggered. The trigger for this DMA channel is set. DMA operations will be carried out." /> + </BitField> + <BitField start="3" size="29" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x404+208" size="4" name="CTLSTAT13" access="ReadOnly" description="Control and status register for DMA channel 0." reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="VALIDPENDING" description="Valid pending flag for this channel. This bit is set when a 1 is written to the corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel."> + <Enum name="NO_EFFECT_ON_DMA_OPE" start="0" description="No effect on DMA operation." /> + <Enum name="VALID_PENDING" start="1" description="Valid pending." /> + </BitField> + <BitField start="1" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="2" size="1" name="TRIG" description="Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1."> + <Enum name="NOT_TRIGGERED" start="0" description="Not triggered. The trigger for this DMA channel is not set. DMA operations will not be carried out." /> + <Enum name="TRIGGERED" start="1" description="Triggered. The trigger for this DMA channel is set. DMA operations will be carried out." /> + </BitField> + <BitField start="3" size="29" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x404+224" size="4" name="CTLSTAT14" access="ReadOnly" description="Control and status register for DMA channel 0." reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="VALIDPENDING" description="Valid pending flag for this channel. This bit is set when a 1 is written to the corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel."> + <Enum name="NO_EFFECT_ON_DMA_OPE" start="0" description="No effect on DMA operation." /> + <Enum name="VALID_PENDING" start="1" description="Valid pending." /> + </BitField> + <BitField start="1" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="2" size="1" name="TRIG" description="Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1."> + <Enum name="NOT_TRIGGERED" start="0" description="Not triggered. The trigger for this DMA channel is not set. DMA operations will not be carried out." /> + <Enum name="TRIGGERED" start="1" description="Triggered. The trigger for this DMA channel is set. DMA operations will be carried out." /> + </BitField> + <BitField start="3" size="29" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x404+240" size="4" name="CTLSTAT15" access="ReadOnly" description="Control and status register for DMA channel 0." reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="VALIDPENDING" description="Valid pending flag for this channel. This bit is set when a 1 is written to the corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel."> + <Enum name="NO_EFFECT_ON_DMA_OPE" start="0" description="No effect on DMA operation." /> + <Enum name="VALID_PENDING" start="1" description="Valid pending." /> + </BitField> + <BitField start="1" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="2" size="1" name="TRIG" description="Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1."> + <Enum name="NOT_TRIGGERED" start="0" description="Not triggered. The trigger for this DMA channel is not set. DMA operations will not be carried out." /> + <Enum name="TRIGGERED" start="1" description="Triggered. The trigger for this DMA channel is set. DMA operations will be carried out." /> + </BitField> + <BitField start="3" size="29" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x408+0" size="4" name="XFERCFG0" access="Read/Write" description="Transfer configuration register for DMA channel 0." reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="CFGVALID" description="Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon, if all other activation criteria are fulfilled."> + <Enum name="NOT_VALID" start="0" description="Not valid. The current channel descriptor is not considered valid." /> + <Enum name="VALID" start="1" description="Valid. The current channel descriptor is considered valid." /> + </BitField> + <BitField start="1" size="1" name="RELOAD" description="Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers."> + <Enum name="DISABLED" start="0" description="Disabled. Do not reload the channels' control structure when the current descriptor is exhausted." /> + <Enum name="ENABLED" start="1" description="Enabled. Reload the channels' control structure when the current descriptor is exhausted." /> + </BitField> + <BitField start="2" size="1" name="SWTRIG" description="Software Trigger."> + <Enum name="WHEN_WRITTEN_BY_SOFT" start="0" description="When written by software, the trigger for this channel is not set. A new trigger, as defined by the HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the channel." /> + <Enum name="WHEN_WRITTEN_BY_SOFT" start="1" description="When written by software, the trigger for this channel is set immediately. This feature should not be used with level triggering when TRIGBURST = 0." /> + </BitField> + <BitField start="3" size="1" name="CLRTRIG" description="Clear Trigger."> + <Enum name="NOT_CLEARED" start="0" description="Not cleared. The trigger is not cleared when this descriptor is exhausted. If there is a reload, the next descriptor will be started." /> + <Enum name="CLEARED" start="1" description="Cleared. The trigger is cleared when this descriptor is exhausted." /> + </BitField> + <BitField start="4" size="1" name="SETINTA" description="Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed."> + <Enum name="NO_EFFECT" start="0" description="No effect." /> + <Enum name="SET" start="1" description="Set. The INTA flag for this channel will be set when the current descriptor is exhausted." /> + </BitField> + <BitField start="5" size="1" name="SETINTB" description="Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed."> + <Enum name="NO_EFFECT" start="0" description="No effect." /> + <Enum name="SET" start="1" description="Set. The INTB flag for this channel will be set when the current descriptor is exhausted." /> + </BitField> + <BitField start="6" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="8" size="2" name="WIDTH" description="Transfer width used for this DMA channel."> + <Enum name="8_BIT_TRANSFERS" start="0x0" description="8-bit transfers are performed (8-bit source reads and destination writes)." /> + <Enum name="16_BIT_TRANSFERS" start="0x1" description="16-bit transfers are performed (16-bit source reads and destination writes)." /> + <Enum name="32_BIT_TRANSFERS" start="0x2" description="32-bit transfers are performed (32-bit source reads and destination writes)." /> + <Enum name="RESERVED" start="0x3" description="Reserved setting, do not use." /> + </BitField> + <BitField start="10" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="12" size="2" name="SRCINC" description="Determines whether the source address is incremented for each DMA transfer."> + <Enum name="NO_INCREMENT" start="0x0" description="No increment. The source address is not incremented for each transfer. This is the usual case when the source is a peripheral device." /> + <Enum name="1_X_WIDTH" start="0x1" description="1 x width. The source address is incremented by the amount specified by Width for each transfer. This is the usual case when the source is memory." /> + <Enum name="2_X_WIDTH" start="0x2" description="2 x width. The source address is incremented by 2 times the amount specified by Width for each transfer." /> + <Enum name="4_X_WIDTH" start="0x3" description="4 x width. The source address is incremented by 4 times the amount specified by Width for each transfer." /> + </BitField> + <BitField start="14" size="2" name="DSTINC" description="Determines whether the destination address is incremented for each DMA transfer."> + <Enum name="NO_INCREMENT" start="0x0" description="No increment. The destination address is not incremented for each transfer. This is the usual case when the destination is a peripheral device." /> + <Enum name="1_X_WIDTH" start="0x1" description="1 x width. The destination address is incremented by the amount specified by Width for each transfer. This is the usual case when the destination is memory." /> + <Enum name="2_X_WIDTH" start="0x2" description="2 x width. The destination address is incremented by 2 times the amount specified by Width for each transfer." /> + <Enum name="4_X_WIDTH" start="0x3" description="4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer." /> + </BitField> + <BitField start="16" size="10" name="XFERCOUNT" description="Total number of transfers to be performed, minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence, it cannot be used by software to read back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 transfer will be performed. 0x1 = a total of 2 transfers will be performed. ... 0x3FF = a total of 1,024 transfers will be performed." /> + <BitField start="26" size="6" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x408+16" size="4" name="XFERCFG1" access="Read/Write" description="Transfer configuration register for DMA channel 0." reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="CFGVALID" description="Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon, if all other activation criteria are fulfilled."> + <Enum name="NOT_VALID" start="0" description="Not valid. The current channel descriptor is not considered valid." /> + <Enum name="VALID" start="1" description="Valid. The current channel descriptor is considered valid." /> + </BitField> + <BitField start="1" size="1" name="RELOAD" description="Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers."> + <Enum name="DISABLED" start="0" description="Disabled. Do not reload the channels' control structure when the current descriptor is exhausted." /> + <Enum name="ENABLED" start="1" description="Enabled. Reload the channels' control structure when the current descriptor is exhausted." /> + </BitField> + <BitField start="2" size="1" name="SWTRIG" description="Software Trigger."> + <Enum name="WHEN_WRITTEN_BY_SOFT" start="0" description="When written by software, the trigger for this channel is not set. A new trigger, as defined by the HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the channel." /> + <Enum name="WHEN_WRITTEN_BY_SOFT" start="1" description="When written by software, the trigger for this channel is set immediately. This feature should not be used with level triggering when TRIGBURST = 0." /> + </BitField> + <BitField start="3" size="1" name="CLRTRIG" description="Clear Trigger."> + <Enum name="NOT_CLEARED" start="0" description="Not cleared. The trigger is not cleared when this descriptor is exhausted. If there is a reload, the next descriptor will be started." /> + <Enum name="CLEARED" start="1" description="Cleared. The trigger is cleared when this descriptor is exhausted." /> + </BitField> + <BitField start="4" size="1" name="SETINTA" description="Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed."> + <Enum name="NO_EFFECT" start="0" description="No effect." /> + <Enum name="SET" start="1" description="Set. The INTA flag for this channel will be set when the current descriptor is exhausted." /> + </BitField> + <BitField start="5" size="1" name="SETINTB" description="Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed."> + <Enum name="NO_EFFECT" start="0" description="No effect." /> + <Enum name="SET" start="1" description="Set. The INTB flag for this channel will be set when the current descriptor is exhausted." /> + </BitField> + <BitField start="6" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="8" size="2" name="WIDTH" description="Transfer width used for this DMA channel."> + <Enum name="8_BIT_TRANSFERS" start="0x0" description="8-bit transfers are performed (8-bit source reads and destination writes)." /> + <Enum name="16_BIT_TRANSFERS" start="0x1" description="16-bit transfers are performed (16-bit source reads and destination writes)." /> + <Enum name="32_BIT_TRANSFERS" start="0x2" description="32-bit transfers are performed (32-bit source reads and destination writes)." /> + <Enum name="RESERVED" start="0x3" description="Reserved setting, do not use." /> + </BitField> + <BitField start="10" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="12" size="2" name="SRCINC" description="Determines whether the source address is incremented for each DMA transfer."> + <Enum name="NO_INCREMENT" start="0x0" description="No increment. The source address is not incremented for each transfer. This is the usual case when the source is a peripheral device." /> + <Enum name="1_X_WIDTH" start="0x1" description="1 x width. The source address is incremented by the amount specified by Width for each transfer. This is the usual case when the source is memory." /> + <Enum name="2_X_WIDTH" start="0x2" description="2 x width. The source address is incremented by 2 times the amount specified by Width for each transfer." /> + <Enum name="4_X_WIDTH" start="0x3" description="4 x width. The source address is incremented by 4 times the amount specified by Width for each transfer." /> + </BitField> + <BitField start="14" size="2" name="DSTINC" description="Determines whether the destination address is incremented for each DMA transfer."> + <Enum name="NO_INCREMENT" start="0x0" description="No increment. The destination address is not incremented for each transfer. This is the usual case when the destination is a peripheral device." /> + <Enum name="1_X_WIDTH" start="0x1" description="1 x width. The destination address is incremented by the amount specified by Width for each transfer. This is the usual case when the destination is memory." /> + <Enum name="2_X_WIDTH" start="0x2" description="2 x width. The destination address is incremented by 2 times the amount specified by Width for each transfer." /> + <Enum name="4_X_WIDTH" start="0x3" description="4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer." /> + </BitField> + <BitField start="16" size="10" name="XFERCOUNT" description="Total number of transfers to be performed, minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence, it cannot be used by software to read back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 transfer will be performed. 0x1 = a total of 2 transfers will be performed. ... 0x3FF = a total of 1,024 transfers will be performed." /> + <BitField start="26" size="6" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x408+32" size="4" name="XFERCFG2" access="Read/Write" description="Transfer configuration register for DMA channel 0." reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="CFGVALID" description="Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon, if all other activation criteria are fulfilled."> + <Enum name="NOT_VALID" start="0" description="Not valid. The current channel descriptor is not considered valid." /> + <Enum name="VALID" start="1" description="Valid. The current channel descriptor is considered valid." /> + </BitField> + <BitField start="1" size="1" name="RELOAD" description="Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers."> + <Enum name="DISABLED" start="0" description="Disabled. Do not reload the channels' control structure when the current descriptor is exhausted." /> + <Enum name="ENABLED" start="1" description="Enabled. Reload the channels' control structure when the current descriptor is exhausted." /> + </BitField> + <BitField start="2" size="1" name="SWTRIG" description="Software Trigger."> + <Enum name="WHEN_WRITTEN_BY_SOFT" start="0" description="When written by software, the trigger for this channel is not set. A new trigger, as defined by the HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the channel." /> + <Enum name="WHEN_WRITTEN_BY_SOFT" start="1" description="When written by software, the trigger for this channel is set immediately. This feature should not be used with level triggering when TRIGBURST = 0." /> + </BitField> + <BitField start="3" size="1" name="CLRTRIG" description="Clear Trigger."> + <Enum name="NOT_CLEARED" start="0" description="Not cleared. The trigger is not cleared when this descriptor is exhausted. If there is a reload, the next descriptor will be started." /> + <Enum name="CLEARED" start="1" description="Cleared. The trigger is cleared when this descriptor is exhausted." /> + </BitField> + <BitField start="4" size="1" name="SETINTA" description="Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed."> + <Enum name="NO_EFFECT" start="0" description="No effect." /> + <Enum name="SET" start="1" description="Set. The INTA flag for this channel will be set when the current descriptor is exhausted." /> + </BitField> + <BitField start="5" size="1" name="SETINTB" description="Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed."> + <Enum name="NO_EFFECT" start="0" description="No effect." /> + <Enum name="SET" start="1" description="Set. The INTB flag for this channel will be set when the current descriptor is exhausted." /> + </BitField> + <BitField start="6" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="8" size="2" name="WIDTH" description="Transfer width used for this DMA channel."> + <Enum name="8_BIT_TRANSFERS" start="0x0" description="8-bit transfers are performed (8-bit source reads and destination writes)." /> + <Enum name="16_BIT_TRANSFERS" start="0x1" description="16-bit transfers are performed (16-bit source reads and destination writes)." /> + <Enum name="32_BIT_TRANSFERS" start="0x2" description="32-bit transfers are performed (32-bit source reads and destination writes)." /> + <Enum name="RESERVED" start="0x3" description="Reserved setting, do not use." /> + </BitField> + <BitField start="10" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="12" size="2" name="SRCINC" description="Determines whether the source address is incremented for each DMA transfer."> + <Enum name="NO_INCREMENT" start="0x0" description="No increment. The source address is not incremented for each transfer. This is the usual case when the source is a peripheral device." /> + <Enum name="1_X_WIDTH" start="0x1" description="1 x width. The source address is incremented by the amount specified by Width for each transfer. This is the usual case when the source is memory." /> + <Enum name="2_X_WIDTH" start="0x2" description="2 x width. The source address is incremented by 2 times the amount specified by Width for each transfer." /> + <Enum name="4_X_WIDTH" start="0x3" description="4 x width. The source address is incremented by 4 times the amount specified by Width for each transfer." /> + </BitField> + <BitField start="14" size="2" name="DSTINC" description="Determines whether the destination address is incremented for each DMA transfer."> + <Enum name="NO_INCREMENT" start="0x0" description="No increment. The destination address is not incremented for each transfer. This is the usual case when the destination is a peripheral device." /> + <Enum name="1_X_WIDTH" start="0x1" description="1 x width. The destination address is incremented by the amount specified by Width for each transfer. This is the usual case when the destination is memory." /> + <Enum name="2_X_WIDTH" start="0x2" description="2 x width. The destination address is incremented by 2 times the amount specified by Width for each transfer." /> + <Enum name="4_X_WIDTH" start="0x3" description="4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer." /> + </BitField> + <BitField start="16" size="10" name="XFERCOUNT" description="Total number of transfers to be performed, minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence, it cannot be used by software to read back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 transfer will be performed. 0x1 = a total of 2 transfers will be performed. ... 0x3FF = a total of 1,024 transfers will be performed." /> + <BitField start="26" size="6" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x408+48" size="4" name="XFERCFG3" access="Read/Write" description="Transfer configuration register for DMA channel 0." reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="CFGVALID" description="Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon, if all other activation criteria are fulfilled."> + <Enum name="NOT_VALID" start="0" description="Not valid. The current channel descriptor is not considered valid." /> + <Enum name="VALID" start="1" description="Valid. The current channel descriptor is considered valid." /> + </BitField> + <BitField start="1" size="1" name="RELOAD" description="Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers."> + <Enum name="DISABLED" start="0" description="Disabled. Do not reload the channels' control structure when the current descriptor is exhausted." /> + <Enum name="ENABLED" start="1" description="Enabled. Reload the channels' control structure when the current descriptor is exhausted." /> + </BitField> + <BitField start="2" size="1" name="SWTRIG" description="Software Trigger."> + <Enum name="WHEN_WRITTEN_BY_SOFT" start="0" description="When written by software, the trigger for this channel is not set. A new trigger, as defined by the HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the channel." /> + <Enum name="WHEN_WRITTEN_BY_SOFT" start="1" description="When written by software, the trigger for this channel is set immediately. This feature should not be used with level triggering when TRIGBURST = 0." /> + </BitField> + <BitField start="3" size="1" name="CLRTRIG" description="Clear Trigger."> + <Enum name="NOT_CLEARED" start="0" description="Not cleared. The trigger is not cleared when this descriptor is exhausted. If there is a reload, the next descriptor will be started." /> + <Enum name="CLEARED" start="1" description="Cleared. The trigger is cleared when this descriptor is exhausted." /> + </BitField> + <BitField start="4" size="1" name="SETINTA" description="Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed."> + <Enum name="NO_EFFECT" start="0" description="No effect." /> + <Enum name="SET" start="1" description="Set. The INTA flag for this channel will be set when the current descriptor is exhausted." /> + </BitField> + <BitField start="5" size="1" name="SETINTB" description="Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed."> + <Enum name="NO_EFFECT" start="0" description="No effect." /> + <Enum name="SET" start="1" description="Set. The INTB flag for this channel will be set when the current descriptor is exhausted." /> + </BitField> + <BitField start="6" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="8" size="2" name="WIDTH" description="Transfer width used for this DMA channel."> + <Enum name="8_BIT_TRANSFERS" start="0x0" description="8-bit transfers are performed (8-bit source reads and destination writes)." /> + <Enum name="16_BIT_TRANSFERS" start="0x1" description="16-bit transfers are performed (16-bit source reads and destination writes)." /> + <Enum name="32_BIT_TRANSFERS" start="0x2" description="32-bit transfers are performed (32-bit source reads and destination writes)." /> + <Enum name="RESERVED" start="0x3" description="Reserved setting, do not use." /> + </BitField> + <BitField start="10" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="12" size="2" name="SRCINC" description="Determines whether the source address is incremented for each DMA transfer."> + <Enum name="NO_INCREMENT" start="0x0" description="No increment. The source address is not incremented for each transfer. This is the usual case when the source is a peripheral device." /> + <Enum name="1_X_WIDTH" start="0x1" description="1 x width. The source address is incremented by the amount specified by Width for each transfer. This is the usual case when the source is memory." /> + <Enum name="2_X_WIDTH" start="0x2" description="2 x width. The source address is incremented by 2 times the amount specified by Width for each transfer." /> + <Enum name="4_X_WIDTH" start="0x3" description="4 x width. The source address is incremented by 4 times the amount specified by Width for each transfer." /> + </BitField> + <BitField start="14" size="2" name="DSTINC" description="Determines whether the destination address is incremented for each DMA transfer."> + <Enum name="NO_INCREMENT" start="0x0" description="No increment. The destination address is not incremented for each transfer. This is the usual case when the destination is a peripheral device." /> + <Enum name="1_X_WIDTH" start="0x1" description="1 x width. The destination address is incremented by the amount specified by Width for each transfer. This is the usual case when the destination is memory." /> + <Enum name="2_X_WIDTH" start="0x2" description="2 x width. The destination address is incremented by 2 times the amount specified by Width for each transfer." /> + <Enum name="4_X_WIDTH" start="0x3" description="4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer." /> + </BitField> + <BitField start="16" size="10" name="XFERCOUNT" description="Total number of transfers to be performed, minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence, it cannot be used by software to read back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 transfer will be performed. 0x1 = a total of 2 transfers will be performed. ... 0x3FF = a total of 1,024 transfers will be performed." /> + <BitField start="26" size="6" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x408+64" size="4" name="XFERCFG4" access="Read/Write" description="Transfer configuration register for DMA channel 0." reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="CFGVALID" description="Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon, if all other activation criteria are fulfilled."> + <Enum name="NOT_VALID" start="0" description="Not valid. The current channel descriptor is not considered valid." /> + <Enum name="VALID" start="1" description="Valid. The current channel descriptor is considered valid." /> + </BitField> + <BitField start="1" size="1" name="RELOAD" description="Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers."> + <Enum name="DISABLED" start="0" description="Disabled. Do not reload the channels' control structure when the current descriptor is exhausted." /> + <Enum name="ENABLED" start="1" description="Enabled. Reload the channels' control structure when the current descriptor is exhausted." /> + </BitField> + <BitField start="2" size="1" name="SWTRIG" description="Software Trigger."> + <Enum name="WHEN_WRITTEN_BY_SOFT" start="0" description="When written by software, the trigger for this channel is not set. A new trigger, as defined by the HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the channel." /> + <Enum name="WHEN_WRITTEN_BY_SOFT" start="1" description="When written by software, the trigger for this channel is set immediately. This feature should not be used with level triggering when TRIGBURST = 0." /> + </BitField> + <BitField start="3" size="1" name="CLRTRIG" description="Clear Trigger."> + <Enum name="NOT_CLEARED" start="0" description="Not cleared. The trigger is not cleared when this descriptor is exhausted. If there is a reload, the next descriptor will be started." /> + <Enum name="CLEARED" start="1" description="Cleared. The trigger is cleared when this descriptor is exhausted." /> + </BitField> + <BitField start="4" size="1" name="SETINTA" description="Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed."> + <Enum name="NO_EFFECT" start="0" description="No effect." /> + <Enum name="SET" start="1" description="Set. The INTA flag for this channel will be set when the current descriptor is exhausted." /> + </BitField> + <BitField start="5" size="1" name="SETINTB" description="Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed."> + <Enum name="NO_EFFECT" start="0" description="No effect." /> + <Enum name="SET" start="1" description="Set. The INTB flag for this channel will be set when the current descriptor is exhausted." /> + </BitField> + <BitField start="6" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="8" size="2" name="WIDTH" description="Transfer width used for this DMA channel."> + <Enum name="8_BIT_TRANSFERS" start="0x0" description="8-bit transfers are performed (8-bit source reads and destination writes)." /> + <Enum name="16_BIT_TRANSFERS" start="0x1" description="16-bit transfers are performed (16-bit source reads and destination writes)." /> + <Enum name="32_BIT_TRANSFERS" start="0x2" description="32-bit transfers are performed (32-bit source reads and destination writes)." /> + <Enum name="RESERVED" start="0x3" description="Reserved setting, do not use." /> + </BitField> + <BitField start="10" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="12" size="2" name="SRCINC" description="Determines whether the source address is incremented for each DMA transfer."> + <Enum name="NO_INCREMENT" start="0x0" description="No increment. The source address is not incremented for each transfer. This is the usual case when the source is a peripheral device." /> + <Enum name="1_X_WIDTH" start="0x1" description="1 x width. The source address is incremented by the amount specified by Width for each transfer. This is the usual case when the source is memory." /> + <Enum name="2_X_WIDTH" start="0x2" description="2 x width. The source address is incremented by 2 times the amount specified by Width for each transfer." /> + <Enum name="4_X_WIDTH" start="0x3" description="4 x width. The source address is incremented by 4 times the amount specified by Width for each transfer." /> + </BitField> + <BitField start="14" size="2" name="DSTINC" description="Determines whether the destination address is incremented for each DMA transfer."> + <Enum name="NO_INCREMENT" start="0x0" description="No increment. The destination address is not incremented for each transfer. This is the usual case when the destination is a peripheral device." /> + <Enum name="1_X_WIDTH" start="0x1" description="1 x width. The destination address is incremented by the amount specified by Width for each transfer. This is the usual case when the destination is memory." /> + <Enum name="2_X_WIDTH" start="0x2" description="2 x width. The destination address is incremented by 2 times the amount specified by Width for each transfer." /> + <Enum name="4_X_WIDTH" start="0x3" description="4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer." /> + </BitField> + <BitField start="16" size="10" name="XFERCOUNT" description="Total number of transfers to be performed, minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence, it cannot be used by software to read back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 transfer will be performed. 0x1 = a total of 2 transfers will be performed. ... 0x3FF = a total of 1,024 transfers will be performed." /> + <BitField start="26" size="6" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x408+80" size="4" name="XFERCFG5" access="Read/Write" description="Transfer configuration register for DMA channel 0." reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="CFGVALID" description="Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon, if all other activation criteria are fulfilled."> + <Enum name="NOT_VALID" start="0" description="Not valid. The current channel descriptor is not considered valid." /> + <Enum name="VALID" start="1" description="Valid. The current channel descriptor is considered valid." /> + </BitField> + <BitField start="1" size="1" name="RELOAD" description="Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers."> + <Enum name="DISABLED" start="0" description="Disabled. Do not reload the channels' control structure when the current descriptor is exhausted." /> + <Enum name="ENABLED" start="1" description="Enabled. Reload the channels' control structure when the current descriptor is exhausted." /> + </BitField> + <BitField start="2" size="1" name="SWTRIG" description="Software Trigger."> + <Enum name="WHEN_WRITTEN_BY_SOFT" start="0" description="When written by software, the trigger for this channel is not set. A new trigger, as defined by the HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the channel." /> + <Enum name="WHEN_WRITTEN_BY_SOFT" start="1" description="When written by software, the trigger for this channel is set immediately. This feature should not be used with level triggering when TRIGBURST = 0." /> + </BitField> + <BitField start="3" size="1" name="CLRTRIG" description="Clear Trigger."> + <Enum name="NOT_CLEARED" start="0" description="Not cleared. The trigger is not cleared when this descriptor is exhausted. If there is a reload, the next descriptor will be started." /> + <Enum name="CLEARED" start="1" description="Cleared. The trigger is cleared when this descriptor is exhausted." /> + </BitField> + <BitField start="4" size="1" name="SETINTA" description="Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed."> + <Enum name="NO_EFFECT" start="0" description="No effect." /> + <Enum name="SET" start="1" description="Set. The INTA flag for this channel will be set when the current descriptor is exhausted." /> + </BitField> + <BitField start="5" size="1" name="SETINTB" description="Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed."> + <Enum name="NO_EFFECT" start="0" description="No effect." /> + <Enum name="SET" start="1" description="Set. The INTB flag for this channel will be set when the current descriptor is exhausted." /> + </BitField> + <BitField start="6" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="8" size="2" name="WIDTH" description="Transfer width used for this DMA channel."> + <Enum name="8_BIT_TRANSFERS" start="0x0" description="8-bit transfers are performed (8-bit source reads and destination writes)." /> + <Enum name="16_BIT_TRANSFERS" start="0x1" description="16-bit transfers are performed (16-bit source reads and destination writes)." /> + <Enum name="32_BIT_TRANSFERS" start="0x2" description="32-bit transfers are performed (32-bit source reads and destination writes)." /> + <Enum name="RESERVED" start="0x3" description="Reserved setting, do not use." /> + </BitField> + <BitField start="10" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="12" size="2" name="SRCINC" description="Determines whether the source address is incremented for each DMA transfer."> + <Enum name="NO_INCREMENT" start="0x0" description="No increment. The source address is not incremented for each transfer. This is the usual case when the source is a peripheral device." /> + <Enum name="1_X_WIDTH" start="0x1" description="1 x width. The source address is incremented by the amount specified by Width for each transfer. This is the usual case when the source is memory." /> + <Enum name="2_X_WIDTH" start="0x2" description="2 x width. The source address is incremented by 2 times the amount specified by Width for each transfer." /> + <Enum name="4_X_WIDTH" start="0x3" description="4 x width. The source address is incremented by 4 times the amount specified by Width for each transfer." /> + </BitField> + <BitField start="14" size="2" name="DSTINC" description="Determines whether the destination address is incremented for each DMA transfer."> + <Enum name="NO_INCREMENT" start="0x0" description="No increment. The destination address is not incremented for each transfer. This is the usual case when the destination is a peripheral device." /> + <Enum name="1_X_WIDTH" start="0x1" description="1 x width. The destination address is incremented by the amount specified by Width for each transfer. This is the usual case when the destination is memory." /> + <Enum name="2_X_WIDTH" start="0x2" description="2 x width. The destination address is incremented by 2 times the amount specified by Width for each transfer." /> + <Enum name="4_X_WIDTH" start="0x3" description="4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer." /> + </BitField> + <BitField start="16" size="10" name="XFERCOUNT" description="Total number of transfers to be performed, minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence, it cannot be used by software to read back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 transfer will be performed. 0x1 = a total of 2 transfers will be performed. ... 0x3FF = a total of 1,024 transfers will be performed." /> + <BitField start="26" size="6" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x408+96" size="4" name="XFERCFG6" access="Read/Write" description="Transfer configuration register for DMA channel 0." reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="CFGVALID" description="Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon, if all other activation criteria are fulfilled."> + <Enum name="NOT_VALID" start="0" description="Not valid. The current channel descriptor is not considered valid." /> + <Enum name="VALID" start="1" description="Valid. The current channel descriptor is considered valid." /> + </BitField> + <BitField start="1" size="1" name="RELOAD" description="Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers."> + <Enum name="DISABLED" start="0" description="Disabled. Do not reload the channels' control structure when the current descriptor is exhausted." /> + <Enum name="ENABLED" start="1" description="Enabled. Reload the channels' control structure when the current descriptor is exhausted." /> + </BitField> + <BitField start="2" size="1" name="SWTRIG" description="Software Trigger."> + <Enum name="WHEN_WRITTEN_BY_SOFT" start="0" description="When written by software, the trigger for this channel is not set. A new trigger, as defined by the HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the channel." /> + <Enum name="WHEN_WRITTEN_BY_SOFT" start="1" description="When written by software, the trigger for this channel is set immediately. This feature should not be used with level triggering when TRIGBURST = 0." /> + </BitField> + <BitField start="3" size="1" name="CLRTRIG" description="Clear Trigger."> + <Enum name="NOT_CLEARED" start="0" description="Not cleared. The trigger is not cleared when this descriptor is exhausted. If there is a reload, the next descriptor will be started." /> + <Enum name="CLEARED" start="1" description="Cleared. The trigger is cleared when this descriptor is exhausted." /> + </BitField> + <BitField start="4" size="1" name="SETINTA" description="Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed."> + <Enum name="NO_EFFECT" start="0" description="No effect." /> + <Enum name="SET" start="1" description="Set. The INTA flag for this channel will be set when the current descriptor is exhausted." /> + </BitField> + <BitField start="5" size="1" name="SETINTB" description="Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed."> + <Enum name="NO_EFFECT" start="0" description="No effect." /> + <Enum name="SET" start="1" description="Set. The INTB flag for this channel will be set when the current descriptor is exhausted." /> + </BitField> + <BitField start="6" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="8" size="2" name="WIDTH" description="Transfer width used for this DMA channel."> + <Enum name="8_BIT_TRANSFERS" start="0x0" description="8-bit transfers are performed (8-bit source reads and destination writes)." /> + <Enum name="16_BIT_TRANSFERS" start="0x1" description="16-bit transfers are performed (16-bit source reads and destination writes)." /> + <Enum name="32_BIT_TRANSFERS" start="0x2" description="32-bit transfers are performed (32-bit source reads and destination writes)." /> + <Enum name="RESERVED" start="0x3" description="Reserved setting, do not use." /> + </BitField> + <BitField start="10" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="12" size="2" name="SRCINC" description="Determines whether the source address is incremented for each DMA transfer."> + <Enum name="NO_INCREMENT" start="0x0" description="No increment. The source address is not incremented for each transfer. This is the usual case when the source is a peripheral device." /> + <Enum name="1_X_WIDTH" start="0x1" description="1 x width. The source address is incremented by the amount specified by Width for each transfer. This is the usual case when the source is memory." /> + <Enum name="2_X_WIDTH" start="0x2" description="2 x width. The source address is incremented by 2 times the amount specified by Width for each transfer." /> + <Enum name="4_X_WIDTH" start="0x3" description="4 x width. The source address is incremented by 4 times the amount specified by Width for each transfer." /> + </BitField> + <BitField start="14" size="2" name="DSTINC" description="Determines whether the destination address is incremented for each DMA transfer."> + <Enum name="NO_INCREMENT" start="0x0" description="No increment. The destination address is not incremented for each transfer. This is the usual case when the destination is a peripheral device." /> + <Enum name="1_X_WIDTH" start="0x1" description="1 x width. The destination address is incremented by the amount specified by Width for each transfer. This is the usual case when the destination is memory." /> + <Enum name="2_X_WIDTH" start="0x2" description="2 x width. The destination address is incremented by 2 times the amount specified by Width for each transfer." /> + <Enum name="4_X_WIDTH" start="0x3" description="4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer." /> + </BitField> + <BitField start="16" size="10" name="XFERCOUNT" description="Total number of transfers to be performed, minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence, it cannot be used by software to read back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 transfer will be performed. 0x1 = a total of 2 transfers will be performed. ... 0x3FF = a total of 1,024 transfers will be performed." /> + <BitField start="26" size="6" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x408+112" size="4" name="XFERCFG7" access="Read/Write" description="Transfer configuration register for DMA channel 0." reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="CFGVALID" description="Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon, if all other activation criteria are fulfilled."> + <Enum name="NOT_VALID" start="0" description="Not valid. The current channel descriptor is not considered valid." /> + <Enum name="VALID" start="1" description="Valid. The current channel descriptor is considered valid." /> + </BitField> + <BitField start="1" size="1" name="RELOAD" description="Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers."> + <Enum name="DISABLED" start="0" description="Disabled. Do not reload the channels' control structure when the current descriptor is exhausted." /> + <Enum name="ENABLED" start="1" description="Enabled. Reload the channels' control structure when the current descriptor is exhausted." /> + </BitField> + <BitField start="2" size="1" name="SWTRIG" description="Software Trigger."> + <Enum name="WHEN_WRITTEN_BY_SOFT" start="0" description="When written by software, the trigger for this channel is not set. A new trigger, as defined by the HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the channel." /> + <Enum name="WHEN_WRITTEN_BY_SOFT" start="1" description="When written by software, the trigger for this channel is set immediately. This feature should not be used with level triggering when TRIGBURST = 0." /> + </BitField> + <BitField start="3" size="1" name="CLRTRIG" description="Clear Trigger."> + <Enum name="NOT_CLEARED" start="0" description="Not cleared. The trigger is not cleared when this descriptor is exhausted. If there is a reload, the next descriptor will be started." /> + <Enum name="CLEARED" start="1" description="Cleared. The trigger is cleared when this descriptor is exhausted." /> + </BitField> + <BitField start="4" size="1" name="SETINTA" description="Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed."> + <Enum name="NO_EFFECT" start="0" description="No effect." /> + <Enum name="SET" start="1" description="Set. The INTA flag for this channel will be set when the current descriptor is exhausted." /> + </BitField> + <BitField start="5" size="1" name="SETINTB" description="Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed."> + <Enum name="NO_EFFECT" start="0" description="No effect." /> + <Enum name="SET" start="1" description="Set. The INTB flag for this channel will be set when the current descriptor is exhausted." /> + </BitField> + <BitField start="6" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="8" size="2" name="WIDTH" description="Transfer width used for this DMA channel."> + <Enum name="8_BIT_TRANSFERS" start="0x0" description="8-bit transfers are performed (8-bit source reads and destination writes)." /> + <Enum name="16_BIT_TRANSFERS" start="0x1" description="16-bit transfers are performed (16-bit source reads and destination writes)." /> + <Enum name="32_BIT_TRANSFERS" start="0x2" description="32-bit transfers are performed (32-bit source reads and destination writes)." /> + <Enum name="RESERVED" start="0x3" description="Reserved setting, do not use." /> + </BitField> + <BitField start="10" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="12" size="2" name="SRCINC" description="Determines whether the source address is incremented for each DMA transfer."> + <Enum name="NO_INCREMENT" start="0x0" description="No increment. The source address is not incremented for each transfer. This is the usual case when the source is a peripheral device." /> + <Enum name="1_X_WIDTH" start="0x1" description="1 x width. The source address is incremented by the amount specified by Width for each transfer. This is the usual case when the source is memory." /> + <Enum name="2_X_WIDTH" start="0x2" description="2 x width. The source address is incremented by 2 times the amount specified by Width for each transfer." /> + <Enum name="4_X_WIDTH" start="0x3" description="4 x width. The source address is incremented by 4 times the amount specified by Width for each transfer." /> + </BitField> + <BitField start="14" size="2" name="DSTINC" description="Determines whether the destination address is incremented for each DMA transfer."> + <Enum name="NO_INCREMENT" start="0x0" description="No increment. The destination address is not incremented for each transfer. This is the usual case when the destination is a peripheral device." /> + <Enum name="1_X_WIDTH" start="0x1" description="1 x width. The destination address is incremented by the amount specified by Width for each transfer. This is the usual case when the destination is memory." /> + <Enum name="2_X_WIDTH" start="0x2" description="2 x width. The destination address is incremented by 2 times the amount specified by Width for each transfer." /> + <Enum name="4_X_WIDTH" start="0x3" description="4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer." /> + </BitField> + <BitField start="16" size="10" name="XFERCOUNT" description="Total number of transfers to be performed, minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence, it cannot be used by software to read back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 transfer will be performed. 0x1 = a total of 2 transfers will be performed. ... 0x3FF = a total of 1,024 transfers will be performed." /> + <BitField start="26" size="6" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x408+128" size="4" name="XFERCFG8" access="Read/Write" description="Transfer configuration register for DMA channel 0." reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="CFGVALID" description="Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon, if all other activation criteria are fulfilled."> + <Enum name="NOT_VALID" start="0" description="Not valid. The current channel descriptor is not considered valid." /> + <Enum name="VALID" start="1" description="Valid. The current channel descriptor is considered valid." /> + </BitField> + <BitField start="1" size="1" name="RELOAD" description="Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers."> + <Enum name="DISABLED" start="0" description="Disabled. Do not reload the channels' control structure when the current descriptor is exhausted." /> + <Enum name="ENABLED" start="1" description="Enabled. Reload the channels' control structure when the current descriptor is exhausted." /> + </BitField> + <BitField start="2" size="1" name="SWTRIG" description="Software Trigger."> + <Enum name="WHEN_WRITTEN_BY_SOFT" start="0" description="When written by software, the trigger for this channel is not set. A new trigger, as defined by the HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the channel." /> + <Enum name="WHEN_WRITTEN_BY_SOFT" start="1" description="When written by software, the trigger for this channel is set immediately. This feature should not be used with level triggering when TRIGBURST = 0." /> + </BitField> + <BitField start="3" size="1" name="CLRTRIG" description="Clear Trigger."> + <Enum name="NOT_CLEARED" start="0" description="Not cleared. The trigger is not cleared when this descriptor is exhausted. If there is a reload, the next descriptor will be started." /> + <Enum name="CLEARED" start="1" description="Cleared. The trigger is cleared when this descriptor is exhausted." /> + </BitField> + <BitField start="4" size="1" name="SETINTA" description="Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed."> + <Enum name="NO_EFFECT" start="0" description="No effect." /> + <Enum name="SET" start="1" description="Set. The INTA flag for this channel will be set when the current descriptor is exhausted." /> + </BitField> + <BitField start="5" size="1" name="SETINTB" description="Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed."> + <Enum name="NO_EFFECT" start="0" description="No effect." /> + <Enum name="SET" start="1" description="Set. The INTB flag for this channel will be set when the current descriptor is exhausted." /> + </BitField> + <BitField start="6" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="8" size="2" name="WIDTH" description="Transfer width used for this DMA channel."> + <Enum name="8_BIT_TRANSFERS" start="0x0" description="8-bit transfers are performed (8-bit source reads and destination writes)." /> + <Enum name="16_BIT_TRANSFERS" start="0x1" description="16-bit transfers are performed (16-bit source reads and destination writes)." /> + <Enum name="32_BIT_TRANSFERS" start="0x2" description="32-bit transfers are performed (32-bit source reads and destination writes)." /> + <Enum name="RESERVED" start="0x3" description="Reserved setting, do not use." /> + </BitField> + <BitField start="10" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="12" size="2" name="SRCINC" description="Determines whether the source address is incremented for each DMA transfer."> + <Enum name="NO_INCREMENT" start="0x0" description="No increment. The source address is not incremented for each transfer. This is the usual case when the source is a peripheral device." /> + <Enum name="1_X_WIDTH" start="0x1" description="1 x width. The source address is incremented by the amount specified by Width for each transfer. This is the usual case when the source is memory." /> + <Enum name="2_X_WIDTH" start="0x2" description="2 x width. The source address is incremented by 2 times the amount specified by Width for each transfer." /> + <Enum name="4_X_WIDTH" start="0x3" description="4 x width. The source address is incremented by 4 times the amount specified by Width for each transfer." /> + </BitField> + <BitField start="14" size="2" name="DSTINC" description="Determines whether the destination address is incremented for each DMA transfer."> + <Enum name="NO_INCREMENT" start="0x0" description="No increment. The destination address is not incremented for each transfer. This is the usual case when the destination is a peripheral device." /> + <Enum name="1_X_WIDTH" start="0x1" description="1 x width. The destination address is incremented by the amount specified by Width for each transfer. This is the usual case when the destination is memory." /> + <Enum name="2_X_WIDTH" start="0x2" description="2 x width. The destination address is incremented by 2 times the amount specified by Width for each transfer." /> + <Enum name="4_X_WIDTH" start="0x3" description="4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer." /> + </BitField> + <BitField start="16" size="10" name="XFERCOUNT" description="Total number of transfers to be performed, minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence, it cannot be used by software to read back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 transfer will be performed. 0x1 = a total of 2 transfers will be performed. ... 0x3FF = a total of 1,024 transfers will be performed." /> + <BitField start="26" size="6" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x408+144" size="4" name="XFERCFG9" access="Read/Write" description="Transfer configuration register for DMA channel 0." reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="CFGVALID" description="Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon, if all other activation criteria are fulfilled."> + <Enum name="NOT_VALID" start="0" description="Not valid. The current channel descriptor is not considered valid." /> + <Enum name="VALID" start="1" description="Valid. The current channel descriptor is considered valid." /> + </BitField> + <BitField start="1" size="1" name="RELOAD" description="Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers."> + <Enum name="DISABLED" start="0" description="Disabled. Do not reload the channels' control structure when the current descriptor is exhausted." /> + <Enum name="ENABLED" start="1" description="Enabled. Reload the channels' control structure when the current descriptor is exhausted." /> + </BitField> + <BitField start="2" size="1" name="SWTRIG" description="Software Trigger."> + <Enum name="WHEN_WRITTEN_BY_SOFT" start="0" description="When written by software, the trigger for this channel is not set. A new trigger, as defined by the HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the channel." /> + <Enum name="WHEN_WRITTEN_BY_SOFT" start="1" description="When written by software, the trigger for this channel is set immediately. This feature should not be used with level triggering when TRIGBURST = 0." /> + </BitField> + <BitField start="3" size="1" name="CLRTRIG" description="Clear Trigger."> + <Enum name="NOT_CLEARED" start="0" description="Not cleared. The trigger is not cleared when this descriptor is exhausted. If there is a reload, the next descriptor will be started." /> + <Enum name="CLEARED" start="1" description="Cleared. The trigger is cleared when this descriptor is exhausted." /> + </BitField> + <BitField start="4" size="1" name="SETINTA" description="Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed."> + <Enum name="NO_EFFECT" start="0" description="No effect." /> + <Enum name="SET" start="1" description="Set. The INTA flag for this channel will be set when the current descriptor is exhausted." /> + </BitField> + <BitField start="5" size="1" name="SETINTB" description="Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed."> + <Enum name="NO_EFFECT" start="0" description="No effect." /> + <Enum name="SET" start="1" description="Set. The INTB flag for this channel will be set when the current descriptor is exhausted." /> + </BitField> + <BitField start="6" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="8" size="2" name="WIDTH" description="Transfer width used for this DMA channel."> + <Enum name="8_BIT_TRANSFERS" start="0x0" description="8-bit transfers are performed (8-bit source reads and destination writes)." /> + <Enum name="16_BIT_TRANSFERS" start="0x1" description="16-bit transfers are performed (16-bit source reads and destination writes)." /> + <Enum name="32_BIT_TRANSFERS" start="0x2" description="32-bit transfers are performed (32-bit source reads and destination writes)." /> + <Enum name="RESERVED" start="0x3" description="Reserved setting, do not use." /> + </BitField> + <BitField start="10" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="12" size="2" name="SRCINC" description="Determines whether the source address is incremented for each DMA transfer."> + <Enum name="NO_INCREMENT" start="0x0" description="No increment. The source address is not incremented for each transfer. This is the usual case when the source is a peripheral device." /> + <Enum name="1_X_WIDTH" start="0x1" description="1 x width. The source address is incremented by the amount specified by Width for each transfer. This is the usual case when the source is memory." /> + <Enum name="2_X_WIDTH" start="0x2" description="2 x width. The source address is incremented by 2 times the amount specified by Width for each transfer." /> + <Enum name="4_X_WIDTH" start="0x3" description="4 x width. The source address is incremented by 4 times the amount specified by Width for each transfer." /> + </BitField> + <BitField start="14" size="2" name="DSTINC" description="Determines whether the destination address is incremented for each DMA transfer."> + <Enum name="NO_INCREMENT" start="0x0" description="No increment. The destination address is not incremented for each transfer. This is the usual case when the destination is a peripheral device." /> + <Enum name="1_X_WIDTH" start="0x1" description="1 x width. The destination address is incremented by the amount specified by Width for each transfer. This is the usual case when the destination is memory." /> + <Enum name="2_X_WIDTH" start="0x2" description="2 x width. The destination address is incremented by 2 times the amount specified by Width for each transfer." /> + <Enum name="4_X_WIDTH" start="0x3" description="4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer." /> + </BitField> + <BitField start="16" size="10" name="XFERCOUNT" description="Total number of transfers to be performed, minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence, it cannot be used by software to read back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 transfer will be performed. 0x1 = a total of 2 transfers will be performed. ... 0x3FF = a total of 1,024 transfers will be performed." /> + <BitField start="26" size="6" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x408+160" size="4" name="XFERCFG10" access="Read/Write" description="Transfer configuration register for DMA channel 0." reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="CFGVALID" description="Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon, if all other activation criteria are fulfilled."> + <Enum name="NOT_VALID" start="0" description="Not valid. The current channel descriptor is not considered valid." /> + <Enum name="VALID" start="1" description="Valid. The current channel descriptor is considered valid." /> + </BitField> + <BitField start="1" size="1" name="RELOAD" description="Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers."> + <Enum name="DISABLED" start="0" description="Disabled. Do not reload the channels' control structure when the current descriptor is exhausted." /> + <Enum name="ENABLED" start="1" description="Enabled. Reload the channels' control structure when the current descriptor is exhausted." /> + </BitField> + <BitField start="2" size="1" name="SWTRIG" description="Software Trigger."> + <Enum name="WHEN_WRITTEN_BY_SOFT" start="0" description="When written by software, the trigger for this channel is not set. A new trigger, as defined by the HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the channel." /> + <Enum name="WHEN_WRITTEN_BY_SOFT" start="1" description="When written by software, the trigger for this channel is set immediately. This feature should not be used with level triggering when TRIGBURST = 0." /> + </BitField> + <BitField start="3" size="1" name="CLRTRIG" description="Clear Trigger."> + <Enum name="NOT_CLEARED" start="0" description="Not cleared. The trigger is not cleared when this descriptor is exhausted. If there is a reload, the next descriptor will be started." /> + <Enum name="CLEARED" start="1" description="Cleared. The trigger is cleared when this descriptor is exhausted." /> + </BitField> + <BitField start="4" size="1" name="SETINTA" description="Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed."> + <Enum name="NO_EFFECT" start="0" description="No effect." /> + <Enum name="SET" start="1" description="Set. The INTA flag for this channel will be set when the current descriptor is exhausted." /> + </BitField> + <BitField start="5" size="1" name="SETINTB" description="Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed."> + <Enum name="NO_EFFECT" start="0" description="No effect." /> + <Enum name="SET" start="1" description="Set. The INTB flag for this channel will be set when the current descriptor is exhausted." /> + </BitField> + <BitField start="6" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="8" size="2" name="WIDTH" description="Transfer width used for this DMA channel."> + <Enum name="8_BIT_TRANSFERS" start="0x0" description="8-bit transfers are performed (8-bit source reads and destination writes)." /> + <Enum name="16_BIT_TRANSFERS" start="0x1" description="16-bit transfers are performed (16-bit source reads and destination writes)." /> + <Enum name="32_BIT_TRANSFERS" start="0x2" description="32-bit transfers are performed (32-bit source reads and destination writes)." /> + <Enum name="RESERVED" start="0x3" description="Reserved setting, do not use." /> + </BitField> + <BitField start="10" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="12" size="2" name="SRCINC" description="Determines whether the source address is incremented for each DMA transfer."> + <Enum name="NO_INCREMENT" start="0x0" description="No increment. The source address is not incremented for each transfer. This is the usual case when the source is a peripheral device." /> + <Enum name="1_X_WIDTH" start="0x1" description="1 x width. The source address is incremented by the amount specified by Width for each transfer. This is the usual case when the source is memory." /> + <Enum name="2_X_WIDTH" start="0x2" description="2 x width. The source address is incremented by 2 times the amount specified by Width for each transfer." /> + <Enum name="4_X_WIDTH" start="0x3" description="4 x width. The source address is incremented by 4 times the amount specified by Width for each transfer." /> + </BitField> + <BitField start="14" size="2" name="DSTINC" description="Determines whether the destination address is incremented for each DMA transfer."> + <Enum name="NO_INCREMENT" start="0x0" description="No increment. The destination address is not incremented for each transfer. This is the usual case when the destination is a peripheral device." /> + <Enum name="1_X_WIDTH" start="0x1" description="1 x width. The destination address is incremented by the amount specified by Width for each transfer. This is the usual case when the destination is memory." /> + <Enum name="2_X_WIDTH" start="0x2" description="2 x width. The destination address is incremented by 2 times the amount specified by Width for each transfer." /> + <Enum name="4_X_WIDTH" start="0x3" description="4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer." /> + </BitField> + <BitField start="16" size="10" name="XFERCOUNT" description="Total number of transfers to be performed, minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence, it cannot be used by software to read back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 transfer will be performed. 0x1 = a total of 2 transfers will be performed. ... 0x3FF = a total of 1,024 transfers will be performed." /> + <BitField start="26" size="6" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x408+176" size="4" name="XFERCFG11" access="Read/Write" description="Transfer configuration register for DMA channel 0." reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="CFGVALID" description="Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon, if all other activation criteria are fulfilled."> + <Enum name="NOT_VALID" start="0" description="Not valid. The current channel descriptor is not considered valid." /> + <Enum name="VALID" start="1" description="Valid. The current channel descriptor is considered valid." /> + </BitField> + <BitField start="1" size="1" name="RELOAD" description="Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers."> + <Enum name="DISABLED" start="0" description="Disabled. Do not reload the channels' control structure when the current descriptor is exhausted." /> + <Enum name="ENABLED" start="1" description="Enabled. Reload the channels' control structure when the current descriptor is exhausted." /> + </BitField> + <BitField start="2" size="1" name="SWTRIG" description="Software Trigger."> + <Enum name="WHEN_WRITTEN_BY_SOFT" start="0" description="When written by software, the trigger for this channel is not set. A new trigger, as defined by the HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the channel." /> + <Enum name="WHEN_WRITTEN_BY_SOFT" start="1" description="When written by software, the trigger for this channel is set immediately. This feature should not be used with level triggering when TRIGBURST = 0." /> + </BitField> + <BitField start="3" size="1" name="CLRTRIG" description="Clear Trigger."> + <Enum name="NOT_CLEARED" start="0" description="Not cleared. The trigger is not cleared when this descriptor is exhausted. If there is a reload, the next descriptor will be started." /> + <Enum name="CLEARED" start="1" description="Cleared. The trigger is cleared when this descriptor is exhausted." /> + </BitField> + <BitField start="4" size="1" name="SETINTA" description="Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed."> + <Enum name="NO_EFFECT" start="0" description="No effect." /> + <Enum name="SET" start="1" description="Set. The INTA flag for this channel will be set when the current descriptor is exhausted." /> + </BitField> + <BitField start="5" size="1" name="SETINTB" description="Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed."> + <Enum name="NO_EFFECT" start="0" description="No effect." /> + <Enum name="SET" start="1" description="Set. The INTB flag for this channel will be set when the current descriptor is exhausted." /> + </BitField> + <BitField start="6" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="8" size="2" name="WIDTH" description="Transfer width used for this DMA channel."> + <Enum name="8_BIT_TRANSFERS" start="0x0" description="8-bit transfers are performed (8-bit source reads and destination writes)." /> + <Enum name="16_BIT_TRANSFERS" start="0x1" description="16-bit transfers are performed (16-bit source reads and destination writes)." /> + <Enum name="32_BIT_TRANSFERS" start="0x2" description="32-bit transfers are performed (32-bit source reads and destination writes)." /> + <Enum name="RESERVED" start="0x3" description="Reserved setting, do not use." /> + </BitField> + <BitField start="10" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="12" size="2" name="SRCINC" description="Determines whether the source address is incremented for each DMA transfer."> + <Enum name="NO_INCREMENT" start="0x0" description="No increment. The source address is not incremented for each transfer. This is the usual case when the source is a peripheral device." /> + <Enum name="1_X_WIDTH" start="0x1" description="1 x width. The source address is incremented by the amount specified by Width for each transfer. This is the usual case when the source is memory." /> + <Enum name="2_X_WIDTH" start="0x2" description="2 x width. The source address is incremented by 2 times the amount specified by Width for each transfer." /> + <Enum name="4_X_WIDTH" start="0x3" description="4 x width. The source address is incremented by 4 times the amount specified by Width for each transfer." /> + </BitField> + <BitField start="14" size="2" name="DSTINC" description="Determines whether the destination address is incremented for each DMA transfer."> + <Enum name="NO_INCREMENT" start="0x0" description="No increment. The destination address is not incremented for each transfer. This is the usual case when the destination is a peripheral device." /> + <Enum name="1_X_WIDTH" start="0x1" description="1 x width. The destination address is incremented by the amount specified by Width for each transfer. This is the usual case when the destination is memory." /> + <Enum name="2_X_WIDTH" start="0x2" description="2 x width. The destination address is incremented by 2 times the amount specified by Width for each transfer." /> + <Enum name="4_X_WIDTH" start="0x3" description="4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer." /> + </BitField> + <BitField start="16" size="10" name="XFERCOUNT" description="Total number of transfers to be performed, minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence, it cannot be used by software to read back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 transfer will be performed. 0x1 = a total of 2 transfers will be performed. ... 0x3FF = a total of 1,024 transfers will be performed." /> + <BitField start="26" size="6" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x408+192" size="4" name="XFERCFG12" access="Read/Write" description="Transfer configuration register for DMA channel 0." reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="CFGVALID" description="Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon, if all other activation criteria are fulfilled."> + <Enum name="NOT_VALID" start="0" description="Not valid. The current channel descriptor is not considered valid." /> + <Enum name="VALID" start="1" description="Valid. The current channel descriptor is considered valid." /> + </BitField> + <BitField start="1" size="1" name="RELOAD" description="Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers."> + <Enum name="DISABLED" start="0" description="Disabled. Do not reload the channels' control structure when the current descriptor is exhausted." /> + <Enum name="ENABLED" start="1" description="Enabled. Reload the channels' control structure when the current descriptor is exhausted." /> + </BitField> + <BitField start="2" size="1" name="SWTRIG" description="Software Trigger."> + <Enum name="WHEN_WRITTEN_BY_SOFT" start="0" description="When written by software, the trigger for this channel is not set. A new trigger, as defined by the HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the channel." /> + <Enum name="WHEN_WRITTEN_BY_SOFT" start="1" description="When written by software, the trigger for this channel is set immediately. This feature should not be used with level triggering when TRIGBURST = 0." /> + </BitField> + <BitField start="3" size="1" name="CLRTRIG" description="Clear Trigger."> + <Enum name="NOT_CLEARED" start="0" description="Not cleared. The trigger is not cleared when this descriptor is exhausted. If there is a reload, the next descriptor will be started." /> + <Enum name="CLEARED" start="1" description="Cleared. The trigger is cleared when this descriptor is exhausted." /> + </BitField> + <BitField start="4" size="1" name="SETINTA" description="Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed."> + <Enum name="NO_EFFECT" start="0" description="No effect." /> + <Enum name="SET" start="1" description="Set. The INTA flag for this channel will be set when the current descriptor is exhausted." /> + </BitField> + <BitField start="5" size="1" name="SETINTB" description="Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed."> + <Enum name="NO_EFFECT" start="0" description="No effect." /> + <Enum name="SET" start="1" description="Set. The INTB flag for this channel will be set when the current descriptor is exhausted." /> + </BitField> + <BitField start="6" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="8" size="2" name="WIDTH" description="Transfer width used for this DMA channel."> + <Enum name="8_BIT_TRANSFERS" start="0x0" description="8-bit transfers are performed (8-bit source reads and destination writes)." /> + <Enum name="16_BIT_TRANSFERS" start="0x1" description="16-bit transfers are performed (16-bit source reads and destination writes)." /> + <Enum name="32_BIT_TRANSFERS" start="0x2" description="32-bit transfers are performed (32-bit source reads and destination writes)." /> + <Enum name="RESERVED" start="0x3" description="Reserved setting, do not use." /> + </BitField> + <BitField start="10" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="12" size="2" name="SRCINC" description="Determines whether the source address is incremented for each DMA transfer."> + <Enum name="NO_INCREMENT" start="0x0" description="No increment. The source address is not incremented for each transfer. This is the usual case when the source is a peripheral device." /> + <Enum name="1_X_WIDTH" start="0x1" description="1 x width. The source address is incremented by the amount specified by Width for each transfer. This is the usual case when the source is memory." /> + <Enum name="2_X_WIDTH" start="0x2" description="2 x width. The source address is incremented by 2 times the amount specified by Width for each transfer." /> + <Enum name="4_X_WIDTH" start="0x3" description="4 x width. The source address is incremented by 4 times the amount specified by Width for each transfer." /> + </BitField> + <BitField start="14" size="2" name="DSTINC" description="Determines whether the destination address is incremented for each DMA transfer."> + <Enum name="NO_INCREMENT" start="0x0" description="No increment. The destination address is not incremented for each transfer. This is the usual case when the destination is a peripheral device." /> + <Enum name="1_X_WIDTH" start="0x1" description="1 x width. The destination address is incremented by the amount specified by Width for each transfer. This is the usual case when the destination is memory." /> + <Enum name="2_X_WIDTH" start="0x2" description="2 x width. The destination address is incremented by 2 times the amount specified by Width for each transfer." /> + <Enum name="4_X_WIDTH" start="0x3" description="4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer." /> + </BitField> + <BitField start="16" size="10" name="XFERCOUNT" description="Total number of transfers to be performed, minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence, it cannot be used by software to read back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 transfer will be performed. 0x1 = a total of 2 transfers will be performed. ... 0x3FF = a total of 1,024 transfers will be performed." /> + <BitField start="26" size="6" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x408+208" size="4" name="XFERCFG13" access="Read/Write" description="Transfer configuration register for DMA channel 0." reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="CFGVALID" description="Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon, if all other activation criteria are fulfilled."> + <Enum name="NOT_VALID" start="0" description="Not valid. The current channel descriptor is not considered valid." /> + <Enum name="VALID" start="1" description="Valid. The current channel descriptor is considered valid." /> + </BitField> + <BitField start="1" size="1" name="RELOAD" description="Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers."> + <Enum name="DISABLED" start="0" description="Disabled. Do not reload the channels' control structure when the current descriptor is exhausted." /> + <Enum name="ENABLED" start="1" description="Enabled. Reload the channels' control structure when the current descriptor is exhausted." /> + </BitField> + <BitField start="2" size="1" name="SWTRIG" description="Software Trigger."> + <Enum name="WHEN_WRITTEN_BY_SOFT" start="0" description="When written by software, the trigger for this channel is not set. A new trigger, as defined by the HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the channel." /> + <Enum name="WHEN_WRITTEN_BY_SOFT" start="1" description="When written by software, the trigger for this channel is set immediately. This feature should not be used with level triggering when TRIGBURST = 0." /> + </BitField> + <BitField start="3" size="1" name="CLRTRIG" description="Clear Trigger."> + <Enum name="NOT_CLEARED" start="0" description="Not cleared. The trigger is not cleared when this descriptor is exhausted. If there is a reload, the next descriptor will be started." /> + <Enum name="CLEARED" start="1" description="Cleared. The trigger is cleared when this descriptor is exhausted." /> + </BitField> + <BitField start="4" size="1" name="SETINTA" description="Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed."> + <Enum name="NO_EFFECT" start="0" description="No effect." /> + <Enum name="SET" start="1" description="Set. The INTA flag for this channel will be set when the current descriptor is exhausted." /> + </BitField> + <BitField start="5" size="1" name="SETINTB" description="Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed."> + <Enum name="NO_EFFECT" start="0" description="No effect." /> + <Enum name="SET" start="1" description="Set. The INTB flag for this channel will be set when the current descriptor is exhausted." /> + </BitField> + <BitField start="6" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="8" size="2" name="WIDTH" description="Transfer width used for this DMA channel."> + <Enum name="8_BIT_TRANSFERS" start="0x0" description="8-bit transfers are performed (8-bit source reads and destination writes)." /> + <Enum name="16_BIT_TRANSFERS" start="0x1" description="16-bit transfers are performed (16-bit source reads and destination writes)." /> + <Enum name="32_BIT_TRANSFERS" start="0x2" description="32-bit transfers are performed (32-bit source reads and destination writes)." /> + <Enum name="RESERVED" start="0x3" description="Reserved setting, do not use." /> + </BitField> + <BitField start="10" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="12" size="2" name="SRCINC" description="Determines whether the source address is incremented for each DMA transfer."> + <Enum name="NO_INCREMENT" start="0x0" description="No increment. The source address is not incremented for each transfer. This is the usual case when the source is a peripheral device." /> + <Enum name="1_X_WIDTH" start="0x1" description="1 x width. The source address is incremented by the amount specified by Width for each transfer. This is the usual case when the source is memory." /> + <Enum name="2_X_WIDTH" start="0x2" description="2 x width. The source address is incremented by 2 times the amount specified by Width for each transfer." /> + <Enum name="4_X_WIDTH" start="0x3" description="4 x width. The source address is incremented by 4 times the amount specified by Width for each transfer." /> + </BitField> + <BitField start="14" size="2" name="DSTINC" description="Determines whether the destination address is incremented for each DMA transfer."> + <Enum name="NO_INCREMENT" start="0x0" description="No increment. The destination address is not incremented for each transfer. This is the usual case when the destination is a peripheral device." /> + <Enum name="1_X_WIDTH" start="0x1" description="1 x width. The destination address is incremented by the amount specified by Width for each transfer. This is the usual case when the destination is memory." /> + <Enum name="2_X_WIDTH" start="0x2" description="2 x width. The destination address is incremented by 2 times the amount specified by Width for each transfer." /> + <Enum name="4_X_WIDTH" start="0x3" description="4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer." /> + </BitField> + <BitField start="16" size="10" name="XFERCOUNT" description="Total number of transfers to be performed, minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence, it cannot be used by software to read back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 transfer will be performed. 0x1 = a total of 2 transfers will be performed. ... 0x3FF = a total of 1,024 transfers will be performed." /> + <BitField start="26" size="6" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x408+224" size="4" name="XFERCFG14" access="Read/Write" description="Transfer configuration register for DMA channel 0." reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="CFGVALID" description="Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon, if all other activation criteria are fulfilled."> + <Enum name="NOT_VALID" start="0" description="Not valid. The current channel descriptor is not considered valid." /> + <Enum name="VALID" start="1" description="Valid. The current channel descriptor is considered valid." /> + </BitField> + <BitField start="1" size="1" name="RELOAD" description="Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers."> + <Enum name="DISABLED" start="0" description="Disabled. Do not reload the channels' control structure when the current descriptor is exhausted." /> + <Enum name="ENABLED" start="1" description="Enabled. Reload the channels' control structure when the current descriptor is exhausted." /> + </BitField> + <BitField start="2" size="1" name="SWTRIG" description="Software Trigger."> + <Enum name="WHEN_WRITTEN_BY_SOFT" start="0" description="When written by software, the trigger for this channel is not set. A new trigger, as defined by the HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the channel." /> + <Enum name="WHEN_WRITTEN_BY_SOFT" start="1" description="When written by software, the trigger for this channel is set immediately. This feature should not be used with level triggering when TRIGBURST = 0." /> + </BitField> + <BitField start="3" size="1" name="CLRTRIG" description="Clear Trigger."> + <Enum name="NOT_CLEARED" start="0" description="Not cleared. The trigger is not cleared when this descriptor is exhausted. If there is a reload, the next descriptor will be started." /> + <Enum name="CLEARED" start="1" description="Cleared. The trigger is cleared when this descriptor is exhausted." /> + </BitField> + <BitField start="4" size="1" name="SETINTA" description="Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed."> + <Enum name="NO_EFFECT" start="0" description="No effect." /> + <Enum name="SET" start="1" description="Set. The INTA flag for this channel will be set when the current descriptor is exhausted." /> + </BitField> + <BitField start="5" size="1" name="SETINTB" description="Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed."> + <Enum name="NO_EFFECT" start="0" description="No effect." /> + <Enum name="SET" start="1" description="Set. The INTB flag for this channel will be set when the current descriptor is exhausted." /> + </BitField> + <BitField start="6" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="8" size="2" name="WIDTH" description="Transfer width used for this DMA channel."> + <Enum name="8_BIT_TRANSFERS" start="0x0" description="8-bit transfers are performed (8-bit source reads and destination writes)." /> + <Enum name="16_BIT_TRANSFERS" start="0x1" description="16-bit transfers are performed (16-bit source reads and destination writes)." /> + <Enum name="32_BIT_TRANSFERS" start="0x2" description="32-bit transfers are performed (32-bit source reads and destination writes)." /> + <Enum name="RESERVED" start="0x3" description="Reserved setting, do not use." /> + </BitField> + <BitField start="10" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="12" size="2" name="SRCINC" description="Determines whether the source address is incremented for each DMA transfer."> + <Enum name="NO_INCREMENT" start="0x0" description="No increment. The source address is not incremented for each transfer. This is the usual case when the source is a peripheral device." /> + <Enum name="1_X_WIDTH" start="0x1" description="1 x width. The source address is incremented by the amount specified by Width for each transfer. This is the usual case when the source is memory." /> + <Enum name="2_X_WIDTH" start="0x2" description="2 x width. The source address is incremented by 2 times the amount specified by Width for each transfer." /> + <Enum name="4_X_WIDTH" start="0x3" description="4 x width. The source address is incremented by 4 times the amount specified by Width for each transfer." /> + </BitField> + <BitField start="14" size="2" name="DSTINC" description="Determines whether the destination address is incremented for each DMA transfer."> + <Enum name="NO_INCREMENT" start="0x0" description="No increment. The destination address is not incremented for each transfer. This is the usual case when the destination is a peripheral device." /> + <Enum name="1_X_WIDTH" start="0x1" description="1 x width. The destination address is incremented by the amount specified by Width for each transfer. This is the usual case when the destination is memory." /> + <Enum name="2_X_WIDTH" start="0x2" description="2 x width. The destination address is incremented by 2 times the amount specified by Width for each transfer." /> + <Enum name="4_X_WIDTH" start="0x3" description="4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer." /> + </BitField> + <BitField start="16" size="10" name="XFERCOUNT" description="Total number of transfers to be performed, minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence, it cannot be used by software to read back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 transfer will be performed. 0x1 = a total of 2 transfers will be performed. ... 0x3FF = a total of 1,024 transfers will be performed." /> + <BitField start="26" size="6" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x408+240" size="4" name="XFERCFG15" access="Read/Write" description="Transfer configuration register for DMA channel 0." reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="CFGVALID" description="Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon, if all other activation criteria are fulfilled."> + <Enum name="NOT_VALID" start="0" description="Not valid. The current channel descriptor is not considered valid." /> + <Enum name="VALID" start="1" description="Valid. The current channel descriptor is considered valid." /> + </BitField> + <BitField start="1" size="1" name="RELOAD" description="Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers."> + <Enum name="DISABLED" start="0" description="Disabled. Do not reload the channels' control structure when the current descriptor is exhausted." /> + <Enum name="ENABLED" start="1" description="Enabled. Reload the channels' control structure when the current descriptor is exhausted." /> + </BitField> + <BitField start="2" size="1" name="SWTRIG" description="Software Trigger."> + <Enum name="WHEN_WRITTEN_BY_SOFT" start="0" description="When written by software, the trigger for this channel is not set. A new trigger, as defined by the HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the channel." /> + <Enum name="WHEN_WRITTEN_BY_SOFT" start="1" description="When written by software, the trigger for this channel is set immediately. This feature should not be used with level triggering when TRIGBURST = 0." /> + </BitField> + <BitField start="3" size="1" name="CLRTRIG" description="Clear Trigger."> + <Enum name="NOT_CLEARED" start="0" description="Not cleared. The trigger is not cleared when this descriptor is exhausted. If there is a reload, the next descriptor will be started." /> + <Enum name="CLEARED" start="1" description="Cleared. The trigger is cleared when this descriptor is exhausted." /> + </BitField> + <BitField start="4" size="1" name="SETINTA" description="Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed."> + <Enum name="NO_EFFECT" start="0" description="No effect." /> + <Enum name="SET" start="1" description="Set. The INTA flag for this channel will be set when the current descriptor is exhausted." /> + </BitField> + <BitField start="5" size="1" name="SETINTB" description="Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed."> + <Enum name="NO_EFFECT" start="0" description="No effect." /> + <Enum name="SET" start="1" description="Set. The INTB flag for this channel will be set when the current descriptor is exhausted." /> + </BitField> + <BitField start="6" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="8" size="2" name="WIDTH" description="Transfer width used for this DMA channel."> + <Enum name="8_BIT_TRANSFERS" start="0x0" description="8-bit transfers are performed (8-bit source reads and destination writes)." /> + <Enum name="16_BIT_TRANSFERS" start="0x1" description="16-bit transfers are performed (16-bit source reads and destination writes)." /> + <Enum name="32_BIT_TRANSFERS" start="0x2" description="32-bit transfers are performed (32-bit source reads and destination writes)." /> + <Enum name="RESERVED" start="0x3" description="Reserved setting, do not use." /> + </BitField> + <BitField start="10" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="12" size="2" name="SRCINC" description="Determines whether the source address is incremented for each DMA transfer."> + <Enum name="NO_INCREMENT" start="0x0" description="No increment. The source address is not incremented for each transfer. This is the usual case when the source is a peripheral device." /> + <Enum name="1_X_WIDTH" start="0x1" description="1 x width. The source address is incremented by the amount specified by Width for each transfer. This is the usual case when the source is memory." /> + <Enum name="2_X_WIDTH" start="0x2" description="2 x width. The source address is incremented by 2 times the amount specified by Width for each transfer." /> + <Enum name="4_X_WIDTH" start="0x3" description="4 x width. The source address is incremented by 4 times the amount specified by Width for each transfer." /> + </BitField> + <BitField start="14" size="2" name="DSTINC" description="Determines whether the destination address is incremented for each DMA transfer."> + <Enum name="NO_INCREMENT" start="0x0" description="No increment. The destination address is not incremented for each transfer. This is the usual case when the destination is a peripheral device." /> + <Enum name="1_X_WIDTH" start="0x1" description="1 x width. The destination address is incremented by the amount specified by Width for each transfer. This is the usual case when the destination is memory." /> + <Enum name="2_X_WIDTH" start="0x2" description="2 x width. The destination address is incremented by 2 times the amount specified by Width for each transfer." /> + <Enum name="4_X_WIDTH" start="0x3" description="4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer." /> + </BitField> + <BitField start="16" size="10" name="XFERCOUNT" description="Total number of transfers to be performed, minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence, it cannot be used by software to read back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 transfer will be performed. 0x1 = a total of 2 transfers will be performed. ... 0x3FF = a total of 1,024 transfers will be performed." /> + <BitField start="26" size="6" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + </RegisterGroup> + <RegisterGroup name="SCT0" start="0x5000C000" description="State Configurable Timers (SCTimer/PWM)"> + <Register start="+0x000" size="4" name="CONFIG" access="Read/Write" description="SCT configuration register" reset_value="0x00007E00" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="UNIFY" description="SCT operation"> + <Enum name="THE_SCT_OPERATES_AS" start="0" description="The SCT operates as two 16-bit counters named L and H." /> + <Enum name="THE_SCT_OPERATES_AS" start="1" description="The SCT operates as a unified 32-bit counter." /> + </BitField> + <BitField start="1" size="2" name="CLKMODE" description="SCT clock mode"> + <Enum name="THE_BUS_CLOCK_CLOCKS" start="0x0" description="The bus clock clocks the SCT and prescalers." /> + <Enum name="THE_SCT_CLOCK_IS_THE" start="0x1" description="The SCT clock is the bus clock, but the prescalers are enabled to count only when sampling of the input selected by the CKSEL field finds the selected edge. The minimum pulse width on the clock input is 1 bus clock period. This mode is the high-performance sampled-clock mode." /> + <Enum name="THE_INPUT_SELECTED_B" start="0x2" description="The input selected by CKSEL clocks the SCT and prescalers. The input is synchronized to the bus clock and possibly inverted. The minimum pulse width on the clock input is 1 bus clock period. This mode is the low-power sampled-clock mode." /> + <Enum name="PRESCALED_SCT_INPUT" start="0x3" description="Prescaled SCT input. The SCT and prescalers are clocked by the input edge selected by the CKSEL field. In this mode, most of the SCT is clocked by the (selected polarity of the) input. The outputs are switched synchronously to the input clock. The input clock rate must be at least half the system clock rate and can the same or faster than the system clock." /> + </BitField> + <BitField start="3" size="4" name="CKSEL" description="SCT clock select"> + <Enum name="RISING_EDGES_ON_INPU" start="0x0" description="Rising edges on input 0." /> + <Enum name="FALLING_EDGES_ON_INP" start="0x1" description="Falling edges on input 0." /> + <Enum name="RISING_EDGES_ON_INPU" start="0x2" description="Rising edges on input 1." /> + <Enum name="FALLING_EDGES_ON_INP" start="0x3" description="Falling edges on input 1." /> + <Enum name="RISING_EDGES_ON_INPU" start="0x4" description="Rising edges on input 2." /> + <Enum name="FALLING_EDGES_ON_INP" start="0x5" description="Falling edges on input 2." /> + <Enum name="RISING_EDGES_ON_INPU" start="0x6" description="Rising edges on input 3." /> + <Enum name="FALLING_EDGES_ON_INP" start="0x7" description="Falling edges on input 3." /> + </BitField> + <BitField start="7" size="1" name="NORELAOD_L" description="A 1 in this bit prevents the lower match registers from being reloaded from their respective reload registers. Software can write to set or clear this bit at any time. This bit applies to both the higher and lower registers when the UNIFY bit is set." /> + <BitField start="8" size="1" name="NORELOAD_H" description="A 1 in this bit prevents the higher match registers from being reloaded from their respective reload registers. Software can write to set or clear this bit at any time. This bit is not used when the UNIFY bit is set." /> + <BitField start="9" size="8" name="INSYNC" description="Synchronization for input N (bit 9 = input 0, bit 10 = input 1,..., bit 12 = input 3); all other bits are reserved. A 1 in one of these bits subjects the corresponding input to synchronization to the SCT clock, before it is used to create an event. If an input is synchronous to the SCT clock, keep its bit 0 for faster response. When the CKMODE field is 1x, the bit in this field, corresponding to the input selected by the CKSEL field, is not used." /> + <BitField start="17" size="1" name="AUTOLIMIT_L" description="A one in this bit causes a match on match register 0 to be treated as a de-facto LIMIT condition without the need to define an associated event. As with any LIMIT event, this automatic limit causes the counter to be cleared to zero in uni-directional mode or to change the direction of count in bi-directional mode. Software can write to set or clear this bit at any time. This bit applies to both the higher and lower registers when the UNIFY bit is set." /> + <BitField start="18" size="1" name="AUTOLIMIT_H" description="A one in this bit will cause a match on match register 0 to be treated as a de-facto LIMIT condition without the need to define an associated event. As with any LIMIT event, this automatic limit causes the counter to be cleared to zero in uni-directional mode or to change the direction of count in bi-directional mode. Software can write to set or clear this bit at any time. This bit is not used when the UNIFY bit is set." /> + <BitField start="19" size="13" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x004" size="4" name="CTRL" access="Read/Write" description="SCT control register" reset_value="0x00040004" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="DOWN_L" description="This bit is 1 when the L or unified counter is counting down. Hardware sets this bit when the counter limit is reached and BIDIR is 1. Hardware clears this bit when the counter is counting down and a limit condition occurs or when the counter reaches 0." /> + <BitField start="1" size="1" name="STOP_L" description="When this bit is 1 and HALT is 0, the L or unified counter does not run, but I/O events related to the counter can occur. If such an event matches the mask in the Start register, this bit is cleared and counting resumes." /> + <BitField start="2" size="1" name="HALT_L" description="When this bit is 1, the L or unified counter does not run and no events can occur. A reset sets this bit. When the HALT_L bit is one, the STOP_L bit is cleared. If you want to remove the halt condition and keep the SCT in the stop condition (not running), then you can change the halt and stop condition with one single write to this register. Once set, only software can clear this bit to restore counter operation." /> + <BitField start="3" size="1" name="CLRCTR_L" description="Writing a 1 to this bit clears the L or unified counter. This bit always reads as 0." /> + <BitField start="4" size="1" name="BIDIR_L" description="L or unified counter direction select"> + <Enum name="THE_COUNTER_COUNTS_U" start="0" description="The counter counts up to its limit condition, then is cleared to zero." /> + <Enum name="THE_COUNTER_COUNTS_U" start="1" description="The counter counts up to its limit, then counts down to a limit condition or to 0." /> + </BitField> + <BitField start="5" size="8" name="PRE_L" description="Specifies the factor by which the SCT clock is prescaled to produce the L or unified counter clock. The counter clock is clocked at the rate of the SCT clock divided by PRE_L+1. Clear the counter (by writing a 1 to the CLRCTR bit) whenever changing the PRE value." /> + <BitField start="13" size="3" name="RESERVED" description="Reserved" /> + <BitField start="16" size="1" name="DOWN_H" description="This bit is 1 when the H counter is counting down. Hardware sets this bit when the counter limit is reached and BIDIR is 1. Hardware clears this bit when the counter is counting down and a limit condition occurs or when the counter reaches 0." /> + <BitField start="17" size="1" name="STOP_H" description="When this bit is 1 and HALT is 0, the H counter does not, run but I/O events related to the counter can occur. If such an event matches the mask in the Start register, this bit is cleared and counting resumes." /> + <BitField start="18" size="1" name="HALT_H" description="When this bit is 1, the H counter does not run and no events can occur. A reset sets this bit. When the HALT_H bit is one, the STOP_H bit is cleared. If you want to remove the halt condition and keep the SCT in the stop condition (not running), then you can change the halt and stop condition with one single write to this register. Once set, this bit can only be cleared by software to restore counter operation." /> + <BitField start="19" size="1" name="CLRCTR_H" description="Writing a 1 to this bit clears the H counter. This bit always reads as 0." /> + <BitField start="20" size="1" name="BIDIR_H" description="Direction select"> + <Enum name="THE_H_COUNTER_COUNTS" start="0" description="The H counter counts up to its limit condition, then is cleared to zero." /> + <Enum name="THE_H_COUNTER_COUNTS" start="1" description="The H counter counts up to its limit, then counts down to a limit condition or to 0." /> + </BitField> + <BitField start="21" size="8" name="PRE_H" description="Specifies the factor by which the SCT clock is prescaled to produce the H counter clock. The counter clock is clocked at the rate of the SCT clock divided by PRELH+1. Clear the counter (by writing a 1 to the CLRCTR bit) whenever changing the PRE value." /> + <BitField start="29" size="3" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x008" size="4" name="LIMIT" access="Read/Write" description="SCT limit register" reset_value="0x00000000" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="6" name="LIMMSK_L" description="If bit n is one, event n is used as a counter limit for the L or unified counter (event 0 = bit 0, event 1 = bit 1, event 5 = bit 5)." /> + <BitField start="6" size="10" name="RESERVED" description="Reserved." /> + <BitField start="16" size="6" name="LIMMSK_H" description="If bit n is one, event n is used as a counter limit for the H counter (event 0 = bit 16, event 1 = bit 17, event 5 = bit 21)." /> + <BitField start="22" size="10" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x00C" size="4" name="HALT" access="Read/Write" description="SCT halt condition register" reset_value="0x00000000" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="6" name="HALTMSK_L" description="If bit n is one, event n sets the HALT_L bit in the CTRL register (event 0 = bit 0, event 1 = bit 1, event 5 = bit 5)." /> + <BitField start="6" size="10" name="RESERVED" description="Reserved." /> + <BitField start="16" size="6" name="HALTMSK_H" description="If bit n is one, event n sets the HALT_H bit in the CTRL register (event 0 = bit 16, event 1 = bit 17, event 5 = bit 21)." /> + <BitField start="22" size="10" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x010" size="4" name="STOP" access="Read/Write" description="SCT stop condition register" reset_value="0x00000000" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="6" name="STOPMSK_L" description="If bit n is one, event n sets the STOP_L bit in the CTRL register (event 0 = bit 0, event 1 = bit 1, event 5 = bit 5)." /> + <BitField start="6" size="10" name="RESERVED" description="Reserved." /> + <BitField start="16" size="6" name="STOPMSK_H" description="If bit n is one, event n sets the STOP_H bit in the CTRL register (event 0 = bit 16, event 1 = bit 17, event 5 = bit 21)." /> + <BitField start="22" size="10" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x014" size="4" name="START" access="Read/Write" description="SCT start condition register" reset_value="0x00000000" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="6" name="STARTMSK_L" description="If bit n is one, event n clears the STOP_L bit in the CTRL register (event 0 = bit 0, event 1 = bit 1, event 5 = bit 5)." /> + <BitField start="6" size="10" name="RESERVED" description="Reserved." /> + <BitField start="16" size="6" name="STARTMSK_H" description="If bit n is one, event n clears the STOP_H bit in the CTRL register (event 0 = bit 16, event 1 = bit 17, event 5 = bit 21)." /> + <BitField start="22" size="10" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x040" size="4" name="COUNT" access="Read/Write" description="SCT counter register" reset_value="0x00000000" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="16" name="CTR_L" description="When UNIFY = 0, read or write the 16-bit L counter value. When UNIFY = 1, read or write the lower 16 bits of the 32-bit unified counter." /> + <BitField start="16" size="16" name="CTR_H" description="When UNIFY = 0, read or write the 16-bit H counter value. When UNIFY = 1, read or write the upper 16 bits of the 32-bit unified counter." /> + </Register> + <Register start="+0x044" size="4" name="STATE" access="Read/Write" description="SCT state register" reset_value="0x00000000" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="STATE_L" description="State variable." /> + <BitField start="5" size="11" name="RESERVED" description="Reserved." /> + <BitField start="16" size="5" name="STATE_H" description="State variable." /> + <BitField start="21" size="11" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x048" size="4" name="INPUT" access="ReadOnly" description="SCT input register" reset_value="0x00000000" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="AIN0" description="Real-time status of input 0." /> + <BitField start="1" size="1" name="AIN1" description="Real-time status of input 1." /> + <BitField start="2" size="1" name="AIN2" description="Real-time status of input 2." /> + <BitField start="3" size="1" name="AIN3" description="Real-time status of input 3." /> + <BitField start="4" size="12" name="RESERVED" description="Reserved." /> + <BitField start="16" size="1" name="SIN0" description="Input 0 state synchronized to the SCT clock." /> + <BitField start="17" size="1" name="SIN1" description="Input 1 state synchronized to the SCT clock." /> + <BitField start="18" size="1" name="SIN2" description="Input 2 state synchronized to the SCT clock." /> + <BitField start="19" size="1" name="SIN3" description="Input 3 state synchronized to the SCT clock." /> + <BitField start="20" size="12" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x04C" size="4" name="REGMODE" access="Read/Write" description="SCT match/capture registers mode register" reset_value="0x00000000" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="REGMOD_L" description="Each bit controls one pair of match/capture registers (register 0 = bit 0, register 1 = bit 1,..., register 4 = bit 4). 0 = registers operate as match registers. 1 = registers operate as capture registers." /> + <BitField start="5" size="11" name="RESERVED" description="Reserved." /> + <BitField start="16" size="5" name="REGMOD_H" description="Each bit controls one pair of match/capture registers (register 0 = bit 16, register 1 = bit 17,..., register 4 = bit 20). 0 = registers operate as match registers. 1 = registers operate as capture registers." /> + <BitField start="21" size="11" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x050" size="4" name="OUTPUT" access="Read/Write" description="SCT output register" reset_value="0x00000000" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="4" name="OUT" description="Writing a 1 to bit n makes the corresponding output HIGH. 0 makes the corresponding output LOW (output 0 = bit 0, output 1 = bit 1,..., output 3 = bit 3)." /> + <BitField start="4" size="28" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x054" size="4" name="OUTPUTDIRCTRL" access="Read/Write" description="SCT output counter direction control register" reset_value="0x00000000" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="SETCLR0" description="Set/clear operation on output 0. Value 0x3 is reserved. Do not program this value."> + <Enum name="SET_AND_CLEAR_DO_NOT" start="0x0" description="Set and clear do not depend on any counter." /> + <Enum name="SET_AND_CLEAR_ARE_RE" start="0x1" description="Set and clear are reversed when counter L or the unified counter is counting down." /> + <Enum name="SET_AND_CLEAR_ARE_RE" start="0x2" description="Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1." /> + </BitField> + <BitField start="2" size="2" name="SETCLR1" description="Set/clear operation on output 1. Value 0x3 is reserved. Do not program this value."> + <Enum name="SET_AND_CLEAR_DO_NOT" start="0x0" description="Set and clear do not depend on any counter." /> + <Enum name="SET_AND_CLEAR_ARE_RE" start="0x1" description="Set and clear are reversed when counter L or the unified counter is counting down." /> + <Enum name="SET_AND_CLEAR_ARE_RE" start="0x2" description="Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1." /> + </BitField> + <BitField start="4" size="2" name="SETCLR2" description="Set/clear operation on output 2. Value 0x3 is reserved. Do not program this value."> + <Enum name="SET_AND_CLEAR_DO_NOT" start="0x0" description="Set and clear do not depend on any counter." /> + <Enum name="SET_AND_CLEAR_ARE_RE" start="0x1" description="Set and clear are reversed when counter L or the unified counter is counting down." /> + <Enum name="SET_AND_CLEAR_ARE_RE" start="0x2" description="Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1." /> + </BitField> + <BitField start="6" size="2" name="SETCLR3" description="Set/clear operation on output 3. Value 0x3 is reserved. Do not program this value."> + <Enum name="SET_AND_CLEAR_DO_NOT" start="0x0" description="Set and clear do not depend on any counter." /> + <Enum name="SET_AND_CLEAR_ARE_RE" start="0x1" description="Set and clear are reversed when counter L or the unified counter is counting down." /> + <Enum name="SET_AND_CLEAR_ARE_RE" start="0x2" description="Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1." /> + </BitField> + <BitField start="8" size="24" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x058" size="4" name="RES" access="Read/Write" description="SCT conflict resolution register" reset_value="0x00000000" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="O0RES" description="Effect of simultaneous set and clear on output 0."> + <Enum name="NO_CHANGE" start="0x0" description="No change." /> + <Enum name="SET_OUTPUT_OR_CLEAR" start="0x1" description="Set output (or clear based on the SETCLR0 field)." /> + <Enum name="CLEAR_OUTPUT_OR_SET" start="0x2" description="Clear output (or set based on the SETCLR0 field)." /> + <Enum name="TOGGLE_OUTPUT" start="0x3" description="Toggle output." /> + </BitField> + <BitField start="2" size="2" name="O1RES" description="Effect of simultaneous set and clear on output 1."> + <Enum name="NO_CHANGE" start="0x0" description="No change." /> + <Enum name="SET_OUTPUT_OR_CLEAR" start="0x1" description="Set output (or clear based on the SETCLR1 field)." /> + <Enum name="CLEAR_OUTPUT_OR_SET" start="0x2" description="Clear output (or set based on the SETCLR1 field)." /> + <Enum name="TOGGLE_OUTPUT" start="0x3" description="Toggle output." /> + </BitField> + <BitField start="4" size="2" name="O2RES" description="Effect of simultaneous set and clear on output 2."> + <Enum name="NO_CHANGE" start="0x0" description="No change." /> + <Enum name="SET_OUTPUT_OR_CLEAR" start="0x1" description="Set output (or clear based on the SETCLR2 field)." /> + <Enum name="CLEAR_OUTPUT_N_OR_S" start="0x2" description="Clear output n (or set based on the SETCLR2 field)." /> + <Enum name="TOGGLE_OUTPUT" start="0x3" description="Toggle output." /> + </BitField> + <BitField start="6" size="2" name="O3RES" description="Effect of simultaneous set and clear on output 3."> + <Enum name="NO_CHANGE" start="0x0" description="No change." /> + <Enum name="SET_OUTPUT_OR_CLEAR" start="0x1" description="Set output (or clear based on the SETCLR3 field)." /> + <Enum name="CLEAR_OUTPUT_OR_SET" start="0x2" description="Clear output (or set based on the SETCLR3 field)." /> + <Enum name="TOGGLE_OUTPUT" start="0x3" description="Toggle output." /> + </BitField> + <BitField start="8" size="24" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x05C" size="4" name="DMAREQ0" access="Read/Write" description="SCT DMA request 0 register" reset_value="0x00000000" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="6" name="DEV_0" description="If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 5 = bit 5)." /> + <BitField start="6" size="24" name="RESERVED" description="Reserved" /> + <BitField start="30" size="1" name="DRL0" description="A 1 in this bit makes the SCT set DMA request 0 when it loads the Match_L/Unified registers from the Reload_L/Unified registers." /> + <BitField start="31" size="1" name="DRQ0" description="This read-only bit indicates the state of DMA Request 0" /> + </Register> + <Register start="+0x060" size="4" name="DMAREQ1" access="Read/Write" description="SCT DMA request 1 register" reset_value="0x00000000" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="6" name="DEV_1" description="If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 5 = bit 5)." /> + <BitField start="6" size="24" name="RESERVED" description="Reserved" /> + <BitField start="30" size="1" name="DRL1" description="A 1 in this bit makes the SCT set DMA request 1 when it loads the Match L/Unified registers from the Reload L/Unified registers." /> + <BitField start="31" size="1" name="DRQ1" description="This read-only bit indicates the state of DMA Request 1." /> + </Register> + <Register start="+0x0F0" size="4" name="EVEN" access="Read/Write" description="SCT event enable register" reset_value="0x00000000" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="6" name="IEN" description="The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 5 = bit 5)." /> + <BitField start="6" size="26" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x0F4" size="4" name="EVFLAG" access="Read/Write" description="SCT event flag register" reset_value="0x00000000" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="6" name="FLAG" description="Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 5 = bit 5)." /> + <BitField start="6" size="26" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x0F8" size="4" name="CONEN" access="Read/Write" description="SCT conflict enable register" reset_value="0x00000000" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="4" name="NCEN" description="The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 3 = bit 3)." /> + <BitField start="4" size="28" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x0FC" size="4" name="CONFLAG" access="Read/Write" description="SCT conflict flag register" reset_value="0x00000000" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="4" name="NCFLAG" description="Bit n is one if a no-change conflict event occurred on output n since reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 3 = bit 3)." /> + <BitField start="4" size="26" name="RESERVED" description="Reserved." /> + <BitField start="30" size="1" name="BUSERRL" description="The most recent bus error from this SCT involved writing CTR L/Unified, STATE L/Unified, MATCH L/Unified, or the Output register when the L/U counter was not halted. A word write to certain L and H registers can be half successful and half unsuccessful." /> + <BitField start="31" size="1" name="BUSERRH" description="The most recent bus error from this SCT involved writing CTR H, STATE H, MATCH H, or the Output register when the H counter was not halted." /> + </Register> + <Register start="+0x100+0" size="4" name="MATCH0" access="Read/Write" description="SCT match value register of match channels 0 to 4; REGMOD0 to REGMODE4 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="16" name="MATCHn_L" description="When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter." /> + <BitField start="16" size="16" name="MATCHn_H" description="When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter." /> + </Register> + <Register start="+0x100+4" size="4" name="MATCH1" access="Read/Write" description="SCT match value register of match channels 0 to 4; REGMOD0 to REGMODE4 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="16" name="MATCHn_L" description="When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter." /> + <BitField start="16" size="16" name="MATCHn_H" description="When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter." /> + </Register> + <Register start="+0x100+8" size="4" name="MATCH2" access="Read/Write" description="SCT match value register of match channels 0 to 4; REGMOD0 to REGMODE4 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="16" name="MATCHn_L" description="When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter." /> + <BitField start="16" size="16" name="MATCHn_H" description="When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter." /> + </Register> + <Register start="+0x100+12" size="4" name="MATCH3" access="Read/Write" description="SCT match value register of match channels 0 to 4; REGMOD0 to REGMODE4 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="16" name="MATCHn_L" description="When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter." /> + <BitField start="16" size="16" name="MATCHn_H" description="When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter." /> + </Register> + <Register start="+0x100+16" size="4" name="MATCH4" access="Read/Write" description="SCT match value register of match channels 0 to 4; REGMOD0 to REGMODE4 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="16" name="MATCHn_L" description="When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter." /> + <BitField start="16" size="16" name="MATCHn_H" description="When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter." /> + </Register> + <Register start="+0x100+0" size="4" name="CAP0" access="Read/Write" description="SCT capture register of capture channel 0 to 4; REGMOD0 to REGMODE4 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="16" name="CAPn_L" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured." /> + <BitField start="16" size="16" name="CAPn_H" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured." /> + </Register> + <Register start="+0x100+4" size="4" name="CAP1" access="Read/Write" description="SCT capture register of capture channel 0 to 4; REGMOD0 to REGMODE4 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="16" name="CAPn_L" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured." /> + <BitField start="16" size="16" name="CAPn_H" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured." /> + </Register> + <Register start="+0x100+8" size="4" name="CAP2" access="Read/Write" description="SCT capture register of capture channel 0 to 4; REGMOD0 to REGMODE4 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="16" name="CAPn_L" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured." /> + <BitField start="16" size="16" name="CAPn_H" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured." /> + </Register> + <Register start="+0x100+12" size="4" name="CAP3" access="Read/Write" description="SCT capture register of capture channel 0 to 4; REGMOD0 to REGMODE4 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="16" name="CAPn_L" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured." /> + <BitField start="16" size="16" name="CAPn_H" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured." /> + </Register> + <Register start="+0x100+16" size="4" name="CAP4" access="Read/Write" description="SCT capture register of capture channel 0 to 4; REGMOD0 to REGMODE4 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="16" name="CAPn_L" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured." /> + <BitField start="16" size="16" name="CAPn_H" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured." /> + </Register> + <Register start="+0x200+0" size="4" name="MATCHREL0" access="Read/Write" description="SCT match reload value register 0 to 4; REGMOD0 = 0 to REGMODE4 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="16" name="RELOADn_L" description="When UNIFY = 0, read or write the 16-bit value to be loaded into the SCTMATCHn_L register. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be loaded into the MATCHn register." /> + <BitField start="16" size="16" name="RELOADn_H" description="When UNIFY = 0, read or write the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be loaded into the MATCHn register." /> + </Register> + <Register start="+0x200+4" size="4" name="MATCHREL1" access="Read/Write" description="SCT match reload value register 0 to 4; REGMOD0 = 0 to REGMODE4 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="16" name="RELOADn_L" description="When UNIFY = 0, read or write the 16-bit value to be loaded into the SCTMATCHn_L register. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be loaded into the MATCHn register." /> + <BitField start="16" size="16" name="RELOADn_H" description="When UNIFY = 0, read or write the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be loaded into the MATCHn register." /> + </Register> + <Register start="+0x200+8" size="4" name="MATCHREL2" access="Read/Write" description="SCT match reload value register 0 to 4; REGMOD0 = 0 to REGMODE4 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="16" name="RELOADn_L" description="When UNIFY = 0, read or write the 16-bit value to be loaded into the SCTMATCHn_L register. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be loaded into the MATCHn register." /> + <BitField start="16" size="16" name="RELOADn_H" description="When UNIFY = 0, read or write the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be loaded into the MATCHn register." /> + </Register> + <Register start="+0x200+12" size="4" name="MATCHREL3" access="Read/Write" description="SCT match reload value register 0 to 4; REGMOD0 = 0 to REGMODE4 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="16" name="RELOADn_L" description="When UNIFY = 0, read or write the 16-bit value to be loaded into the SCTMATCHn_L register. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be loaded into the MATCHn register." /> + <BitField start="16" size="16" name="RELOADn_H" description="When UNIFY = 0, read or write the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be loaded into the MATCHn register." /> + </Register> + <Register start="+0x200+16" size="4" name="MATCHREL4" access="Read/Write" description="SCT match reload value register 0 to 4; REGMOD0 = 0 to REGMODE4 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="16" name="RELOADn_L" description="When UNIFY = 0, read or write the 16-bit value to be loaded into the SCTMATCHn_L register. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be loaded into the MATCHn register." /> + <BitField start="16" size="16" name="RELOADn_H" description="When UNIFY = 0, read or write the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be loaded into the MATCHn register." /> + </Register> + <Register start="+0x200+0" size="4" name="CAPCTRL0" access="Read/Write" description="SCT capture control register 0 to 4; REGMOD0 = 1 to REGMODE4 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="6" name="CAPCONn_L" description="If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1,..., event 5 = bit 5)." /> + <BitField start="6" size="10" name="RESERVED" description="Reserved." /> + <BitField start="16" size="6" name="CAPCONn_H" description="If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17,..., event 5 = bit 21)." /> + <BitField start="22" size="10" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x200+4" size="4" name="CAPCTRL1" access="Read/Write" description="SCT capture control register 0 to 4; REGMOD0 = 1 to REGMODE4 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="6" name="CAPCONn_L" description="If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1,..., event 5 = bit 5)." /> + <BitField start="6" size="10" name="RESERVED" description="Reserved." /> + <BitField start="16" size="6" name="CAPCONn_H" description="If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17,..., event 5 = bit 21)." /> + <BitField start="22" size="10" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x200+8" size="4" name="CAPCTRL2" access="Read/Write" description="SCT capture control register 0 to 4; REGMOD0 = 1 to REGMODE4 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="6" name="CAPCONn_L" description="If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1,..., event 5 = bit 5)." /> + <BitField start="6" size="10" name="RESERVED" description="Reserved." /> + <BitField start="16" size="6" name="CAPCONn_H" description="If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17,..., event 5 = bit 21)." /> + <BitField start="22" size="10" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x200+12" size="4" name="CAPCTRL3" access="Read/Write" description="SCT capture control register 0 to 4; REGMOD0 = 1 to REGMODE4 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="6" name="CAPCONn_L" description="If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1,..., event 5 = bit 5)." /> + <BitField start="6" size="10" name="RESERVED" description="Reserved." /> + <BitField start="16" size="6" name="CAPCONn_H" description="If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17,..., event 5 = bit 21)." /> + <BitField start="22" size="10" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x200+16" size="4" name="CAPCTRL4" access="Read/Write" description="SCT capture control register 0 to 4; REGMOD0 = 1 to REGMODE4 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="6" name="CAPCONn_L" description="If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1,..., event 5 = bit 5)." /> + <BitField start="6" size="10" name="RESERVED" description="Reserved." /> + <BitField start="16" size="6" name="CAPCONn_H" description="If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17,..., event 5 = bit 21)." /> + <BitField start="22" size="10" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x300+0" size="4" name="EV0_STATE" access="Read/Write" description="SCT event state register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="STATEMSKn" description="If bit m is one, event n (n= 0 to 5) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 7 = bit 7)." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x300+8" size="4" name="EV1_STATE" access="Read/Write" description="SCT event state register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="STATEMSKn" description="If bit m is one, event n (n= 0 to 5) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 7 = bit 7)." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x300+16" size="4" name="EV2_STATE" access="Read/Write" description="SCT event state register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="STATEMSKn" description="If bit m is one, event n (n= 0 to 5) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 7 = bit 7)." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x300+24" size="4" name="EV3_STATE" access="Read/Write" description="SCT event state register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="STATEMSKn" description="If bit m is one, event n (n= 0 to 5) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 7 = bit 7)." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x300+32" size="4" name="EV4_STATE" access="Read/Write" description="SCT event state register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="STATEMSKn" description="If bit m is one, event n (n= 0 to 5) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 7 = bit 7)." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x300+40" size="4" name="EV5_STATE" access="Read/Write" description="SCT event state register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="STATEMSKn" description="If bit m is one, event n (n= 0 to 5) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 7 = bit 7)." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x304+0" size="4" name="EV0_CTRL" access="Read/Write" description="SCT event control register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="4" name="MATCHSEL" description="Selects the Match register associated with this event (if any). A match can occur only when the counter selected by the HEVENT bit is running." /> + <BitField start="4" size="1" name="HEVENT" description="Select L/H counter. Do not set this bit if UNIFY = 1."> + <Enum name="SELECTS_THE_L_STATE" start="0" description="Selects the L state and the L match register selected by MATCHSEL." /> + <Enum name="SELECTS_THE_H_STATE" start="1" description="Selects the H state and the H match register selected by MATCHSEL." /> + </BitField> + <BitField start="5" size="1" name="OUTSEL" description="Input/output select"> + <Enum name="SELECTS_THE_INPUTS_E" start="0" description="Selects the inputs elected by IOSEL." /> + <Enum name="SELECTS_THE_OUTPUTS" start="1" description="Selects the outputs selected by IOSEL." /> + </BitField> + <BitField start="6" size="4" name="IOSEL" description="Selects the input or output signal number (0 to 3) associated with this event (if any). Do not select an input in this register, if CKMODE is 1x. In this case the clock input is an implicit ingredient of every event." /> + <BitField start="10" size="2" name="IOCOND" description="Selects the I/O condition for event n. (The detection of edges on outputs lag the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT clock period ."> + <Enum name="LOW" start="0x0" description="LOW" /> + <Enum name="RISE" start="0x1" description="Rise" /> + <Enum name="FALL" start="0x2" description="Fall" /> + <Enum name="HIGH" start="0x3" description="HIGH" /> + </BitField> + <BitField start="12" size="2" name="COMBMODE" description="Selects how the specified match and I/O condition are used and combined."> + <Enum name="OR" start="0x0" description="OR. The event occurs when either the specified match or I/O condition occurs." /> + <Enum name="MATCH" start="0x1" description="MATCH. Uses the specified match only." /> + <Enum name="IO" start="0x2" description="IO. Uses the specified I/O condition only." /> + <Enum name="AND" start="0x3" description="AND. The event occurs when the specified match and I/O condition occur simultaneously." /> + </BitField> + <BitField start="14" size="1" name="STATELD" description="This bit controls how the STATEV value modifies the state selected by HEVENT when this event is the highest-numbered event occurring for that state."> + <Enum name="STATEV_VALUE_IS_ADDE" start="0" description="STATEV value is added into STATE (the carry-out is ignored)." /> + <Enum name="STATEV_VALUE_IS_LOAD" start="1" description="STATEV value is loaded into STATE." /> + </BitField> + <BitField start="15" size="5" name="STATEV" description="This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state. If STATELD and STATEV are both zero, there is no change to the STATE value." /> + <BitField start="20" size="1" name="MATCHMEM" description="If this bit is one and the COMBMODE field specifies a match component to the triggering of this event, then a match is considered to be active whenever the counter value is GREATER THAN OR EQUAL TO the value specified in the match register when counting up, LESS THEN OR EQUAL TO the match value when counting down. If this bit is zero, a match is only be active during the cycle when the counter is equal to the match value." /> + <BitField start="21" size="2" name="DIRECTION" description="Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved."> + <Enum name="DIRECTION_INDEPENDEN" start="0x0" description="Direction independent. This event is triggered regardless of the count direction." /> + <Enum name="COUNTING_UP" start="0x1" description="Counting up. This event is triggered only during up-counting when BIDIR = 1." /> + <Enum name="COUNTING_DOWN" start="0x2" description="Counting down. This event is triggered only during down-counting when BIDIR = 1." /> + </BitField> + <BitField start="23" size="9" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x304+8" size="4" name="EV1_CTRL" access="Read/Write" description="SCT event control register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="4" name="MATCHSEL" description="Selects the Match register associated with this event (if any). A match can occur only when the counter selected by the HEVENT bit is running." /> + <BitField start="4" size="1" name="HEVENT" description="Select L/H counter. Do not set this bit if UNIFY = 1."> + <Enum name="SELECTS_THE_L_STATE" start="0" description="Selects the L state and the L match register selected by MATCHSEL." /> + <Enum name="SELECTS_THE_H_STATE" start="1" description="Selects the H state and the H match register selected by MATCHSEL." /> + </BitField> + <BitField start="5" size="1" name="OUTSEL" description="Input/output select"> + <Enum name="SELECTS_THE_INPUTS_E" start="0" description="Selects the inputs elected by IOSEL." /> + <Enum name="SELECTS_THE_OUTPUTS" start="1" description="Selects the outputs selected by IOSEL." /> + </BitField> + <BitField start="6" size="4" name="IOSEL" description="Selects the input or output signal number (0 to 3) associated with this event (if any). Do not select an input in this register, if CKMODE is 1x. In this case the clock input is an implicit ingredient of every event." /> + <BitField start="10" size="2" name="IOCOND" description="Selects the I/O condition for event n. (The detection of edges on outputs lag the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT clock period ."> + <Enum name="LOW" start="0x0" description="LOW" /> + <Enum name="RISE" start="0x1" description="Rise" /> + <Enum name="FALL" start="0x2" description="Fall" /> + <Enum name="HIGH" start="0x3" description="HIGH" /> + </BitField> + <BitField start="12" size="2" name="COMBMODE" description="Selects how the specified match and I/O condition are used and combined."> + <Enum name="OR" start="0x0" description="OR. The event occurs when either the specified match or I/O condition occurs." /> + <Enum name="MATCH" start="0x1" description="MATCH. Uses the specified match only." /> + <Enum name="IO" start="0x2" description="IO. Uses the specified I/O condition only." /> + <Enum name="AND" start="0x3" description="AND. The event occurs when the specified match and I/O condition occur simultaneously." /> + </BitField> + <BitField start="14" size="1" name="STATELD" description="This bit controls how the STATEV value modifies the state selected by HEVENT when this event is the highest-numbered event occurring for that state."> + <Enum name="STATEV_VALUE_IS_ADDE" start="0" description="STATEV value is added into STATE (the carry-out is ignored)." /> + <Enum name="STATEV_VALUE_IS_LOAD" start="1" description="STATEV value is loaded into STATE." /> + </BitField> + <BitField start="15" size="5" name="STATEV" description="This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state. If STATELD and STATEV are both zero, there is no change to the STATE value." /> + <BitField start="20" size="1" name="MATCHMEM" description="If this bit is one and the COMBMODE field specifies a match component to the triggering of this event, then a match is considered to be active whenever the counter value is GREATER THAN OR EQUAL TO the value specified in the match register when counting up, LESS THEN OR EQUAL TO the match value when counting down. If this bit is zero, a match is only be active during the cycle when the counter is equal to the match value." /> + <BitField start="21" size="2" name="DIRECTION" description="Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved."> + <Enum name="DIRECTION_INDEPENDEN" start="0x0" description="Direction independent. This event is triggered regardless of the count direction." /> + <Enum name="COUNTING_UP" start="0x1" description="Counting up. This event is triggered only during up-counting when BIDIR = 1." /> + <Enum name="COUNTING_DOWN" start="0x2" description="Counting down. This event is triggered only during down-counting when BIDIR = 1." /> + </BitField> + <BitField start="23" size="9" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x304+16" size="4" name="EV2_CTRL" access="Read/Write" description="SCT event control register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="4" name="MATCHSEL" description="Selects the Match register associated with this event (if any). A match can occur only when the counter selected by the HEVENT bit is running." /> + <BitField start="4" size="1" name="HEVENT" description="Select L/H counter. Do not set this bit if UNIFY = 1."> + <Enum name="SELECTS_THE_L_STATE" start="0" description="Selects the L state and the L match register selected by MATCHSEL." /> + <Enum name="SELECTS_THE_H_STATE" start="1" description="Selects the H state and the H match register selected by MATCHSEL." /> + </BitField> + <BitField start="5" size="1" name="OUTSEL" description="Input/output select"> + <Enum name="SELECTS_THE_INPUTS_E" start="0" description="Selects the inputs elected by IOSEL." /> + <Enum name="SELECTS_THE_OUTPUTS" start="1" description="Selects the outputs selected by IOSEL." /> + </BitField> + <BitField start="6" size="4" name="IOSEL" description="Selects the input or output signal number (0 to 3) associated with this event (if any). Do not select an input in this register, if CKMODE is 1x. In this case the clock input is an implicit ingredient of every event." /> + <BitField start="10" size="2" name="IOCOND" description="Selects the I/O condition for event n. (The detection of edges on outputs lag the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT clock period ."> + <Enum name="LOW" start="0x0" description="LOW" /> + <Enum name="RISE" start="0x1" description="Rise" /> + <Enum name="FALL" start="0x2" description="Fall" /> + <Enum name="HIGH" start="0x3" description="HIGH" /> + </BitField> + <BitField start="12" size="2" name="COMBMODE" description="Selects how the specified match and I/O condition are used and combined."> + <Enum name="OR" start="0x0" description="OR. The event occurs when either the specified match or I/O condition occurs." /> + <Enum name="MATCH" start="0x1" description="MATCH. Uses the specified match only." /> + <Enum name="IO" start="0x2" description="IO. Uses the specified I/O condition only." /> + <Enum name="AND" start="0x3" description="AND. The event occurs when the specified match and I/O condition occur simultaneously." /> + </BitField> + <BitField start="14" size="1" name="STATELD" description="This bit controls how the STATEV value modifies the state selected by HEVENT when this event is the highest-numbered event occurring for that state."> + <Enum name="STATEV_VALUE_IS_ADDE" start="0" description="STATEV value is added into STATE (the carry-out is ignored)." /> + <Enum name="STATEV_VALUE_IS_LOAD" start="1" description="STATEV value is loaded into STATE." /> + </BitField> + <BitField start="15" size="5" name="STATEV" description="This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state. If STATELD and STATEV are both zero, there is no change to the STATE value." /> + <BitField start="20" size="1" name="MATCHMEM" description="If this bit is one and the COMBMODE field specifies a match component to the triggering of this event, then a match is considered to be active whenever the counter value is GREATER THAN OR EQUAL TO the value specified in the match register when counting up, LESS THEN OR EQUAL TO the match value when counting down. If this bit is zero, a match is only be active during the cycle when the counter is equal to the match value." /> + <BitField start="21" size="2" name="DIRECTION" description="Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved."> + <Enum name="DIRECTION_INDEPENDEN" start="0x0" description="Direction independent. This event is triggered regardless of the count direction." /> + <Enum name="COUNTING_UP" start="0x1" description="Counting up. This event is triggered only during up-counting when BIDIR = 1." /> + <Enum name="COUNTING_DOWN" start="0x2" description="Counting down. This event is triggered only during down-counting when BIDIR = 1." /> + </BitField> + <BitField start="23" size="9" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x304+24" size="4" name="EV3_CTRL" access="Read/Write" description="SCT event control register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="4" name="MATCHSEL" description="Selects the Match register associated with this event (if any). A match can occur only when the counter selected by the HEVENT bit is running." /> + <BitField start="4" size="1" name="HEVENT" description="Select L/H counter. Do not set this bit if UNIFY = 1."> + <Enum name="SELECTS_THE_L_STATE" start="0" description="Selects the L state and the L match register selected by MATCHSEL." /> + <Enum name="SELECTS_THE_H_STATE" start="1" description="Selects the H state and the H match register selected by MATCHSEL." /> + </BitField> + <BitField start="5" size="1" name="OUTSEL" description="Input/output select"> + <Enum name="SELECTS_THE_INPUTS_E" start="0" description="Selects the inputs elected by IOSEL." /> + <Enum name="SELECTS_THE_OUTPUTS" start="1" description="Selects the outputs selected by IOSEL." /> + </BitField> + <BitField start="6" size="4" name="IOSEL" description="Selects the input or output signal number (0 to 3) associated with this event (if any). Do not select an input in this register, if CKMODE is 1x. In this case the clock input is an implicit ingredient of every event." /> + <BitField start="10" size="2" name="IOCOND" description="Selects the I/O condition for event n. (The detection of edges on outputs lag the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT clock period ."> + <Enum name="LOW" start="0x0" description="LOW" /> + <Enum name="RISE" start="0x1" description="Rise" /> + <Enum name="FALL" start="0x2" description="Fall" /> + <Enum name="HIGH" start="0x3" description="HIGH" /> + </BitField> + <BitField start="12" size="2" name="COMBMODE" description="Selects how the specified match and I/O condition are used and combined."> + <Enum name="OR" start="0x0" description="OR. The event occurs when either the specified match or I/O condition occurs." /> + <Enum name="MATCH" start="0x1" description="MATCH. Uses the specified match only." /> + <Enum name="IO" start="0x2" description="IO. Uses the specified I/O condition only." /> + <Enum name="AND" start="0x3" description="AND. The event occurs when the specified match and I/O condition occur simultaneously." /> + </BitField> + <BitField start="14" size="1" name="STATELD" description="This bit controls how the STATEV value modifies the state selected by HEVENT when this event is the highest-numbered event occurring for that state."> + <Enum name="STATEV_VALUE_IS_ADDE" start="0" description="STATEV value is added into STATE (the carry-out is ignored)." /> + <Enum name="STATEV_VALUE_IS_LOAD" start="1" description="STATEV value is loaded into STATE." /> + </BitField> + <BitField start="15" size="5" name="STATEV" description="This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state. If STATELD and STATEV are both zero, there is no change to the STATE value." /> + <BitField start="20" size="1" name="MATCHMEM" description="If this bit is one and the COMBMODE field specifies a match component to the triggering of this event, then a match is considered to be active whenever the counter value is GREATER THAN OR EQUAL TO the value specified in the match register when counting up, LESS THEN OR EQUAL TO the match value when counting down. If this bit is zero, a match is only be active during the cycle when the counter is equal to the match value." /> + <BitField start="21" size="2" name="DIRECTION" description="Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved."> + <Enum name="DIRECTION_INDEPENDEN" start="0x0" description="Direction independent. This event is triggered regardless of the count direction." /> + <Enum name="COUNTING_UP" start="0x1" description="Counting up. This event is triggered only during up-counting when BIDIR = 1." /> + <Enum name="COUNTING_DOWN" start="0x2" description="Counting down. This event is triggered only during down-counting when BIDIR = 1." /> + </BitField> + <BitField start="23" size="9" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x304+32" size="4" name="EV4_CTRL" access="Read/Write" description="SCT event control register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="4" name="MATCHSEL" description="Selects the Match register associated with this event (if any). A match can occur only when the counter selected by the HEVENT bit is running." /> + <BitField start="4" size="1" name="HEVENT" description="Select L/H counter. Do not set this bit if UNIFY = 1."> + <Enum name="SELECTS_THE_L_STATE" start="0" description="Selects the L state and the L match register selected by MATCHSEL." /> + <Enum name="SELECTS_THE_H_STATE" start="1" description="Selects the H state and the H match register selected by MATCHSEL." /> + </BitField> + <BitField start="5" size="1" name="OUTSEL" description="Input/output select"> + <Enum name="SELECTS_THE_INPUTS_E" start="0" description="Selects the inputs elected by IOSEL." /> + <Enum name="SELECTS_THE_OUTPUTS" start="1" description="Selects the outputs selected by IOSEL." /> + </BitField> + <BitField start="6" size="4" name="IOSEL" description="Selects the input or output signal number (0 to 3) associated with this event (if any). Do not select an input in this register, if CKMODE is 1x. In this case the clock input is an implicit ingredient of every event." /> + <BitField start="10" size="2" name="IOCOND" description="Selects the I/O condition for event n. (The detection of edges on outputs lag the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT clock period ."> + <Enum name="LOW" start="0x0" description="LOW" /> + <Enum name="RISE" start="0x1" description="Rise" /> + <Enum name="FALL" start="0x2" description="Fall" /> + <Enum name="HIGH" start="0x3" description="HIGH" /> + </BitField> + <BitField start="12" size="2" name="COMBMODE" description="Selects how the specified match and I/O condition are used and combined."> + <Enum name="OR" start="0x0" description="OR. The event occurs when either the specified match or I/O condition occurs." /> + <Enum name="MATCH" start="0x1" description="MATCH. Uses the specified match only." /> + <Enum name="IO" start="0x2" description="IO. Uses the specified I/O condition only." /> + <Enum name="AND" start="0x3" description="AND. The event occurs when the specified match and I/O condition occur simultaneously." /> + </BitField> + <BitField start="14" size="1" name="STATELD" description="This bit controls how the STATEV value modifies the state selected by HEVENT when this event is the highest-numbered event occurring for that state."> + <Enum name="STATEV_VALUE_IS_ADDE" start="0" description="STATEV value is added into STATE (the carry-out is ignored)." /> + <Enum name="STATEV_VALUE_IS_LOAD" start="1" description="STATEV value is loaded into STATE." /> + </BitField> + <BitField start="15" size="5" name="STATEV" description="This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state. If STATELD and STATEV are both zero, there is no change to the STATE value." /> + <BitField start="20" size="1" name="MATCHMEM" description="If this bit is one and the COMBMODE field specifies a match component to the triggering of this event, then a match is considered to be active whenever the counter value is GREATER THAN OR EQUAL TO the value specified in the match register when counting up, LESS THEN OR EQUAL TO the match value when counting down. If this bit is zero, a match is only be active during the cycle when the counter is equal to the match value." /> + <BitField start="21" size="2" name="DIRECTION" description="Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved."> + <Enum name="DIRECTION_INDEPENDEN" start="0x0" description="Direction independent. This event is triggered regardless of the count direction." /> + <Enum name="COUNTING_UP" start="0x1" description="Counting up. This event is triggered only during up-counting when BIDIR = 1." /> + <Enum name="COUNTING_DOWN" start="0x2" description="Counting down. This event is triggered only during down-counting when BIDIR = 1." /> + </BitField> + <BitField start="23" size="9" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x304+40" size="4" name="EV5_CTRL" access="Read/Write" description="SCT event control register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="4" name="MATCHSEL" description="Selects the Match register associated with this event (if any). A match can occur only when the counter selected by the HEVENT bit is running." /> + <BitField start="4" size="1" name="HEVENT" description="Select L/H counter. Do not set this bit if UNIFY = 1."> + <Enum name="SELECTS_THE_L_STATE" start="0" description="Selects the L state and the L match register selected by MATCHSEL." /> + <Enum name="SELECTS_THE_H_STATE" start="1" description="Selects the H state and the H match register selected by MATCHSEL." /> + </BitField> + <BitField start="5" size="1" name="OUTSEL" description="Input/output select"> + <Enum name="SELECTS_THE_INPUTS_E" start="0" description="Selects the inputs elected by IOSEL." /> + <Enum name="SELECTS_THE_OUTPUTS" start="1" description="Selects the outputs selected by IOSEL." /> + </BitField> + <BitField start="6" size="4" name="IOSEL" description="Selects the input or output signal number (0 to 3) associated with this event (if any). Do not select an input in this register, if CKMODE is 1x. In this case the clock input is an implicit ingredient of every event." /> + <BitField start="10" size="2" name="IOCOND" description="Selects the I/O condition for event n. (The detection of edges on outputs lag the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT clock period ."> + <Enum name="LOW" start="0x0" description="LOW" /> + <Enum name="RISE" start="0x1" description="Rise" /> + <Enum name="FALL" start="0x2" description="Fall" /> + <Enum name="HIGH" start="0x3" description="HIGH" /> + </BitField> + <BitField start="12" size="2" name="COMBMODE" description="Selects how the specified match and I/O condition are used and combined."> + <Enum name="OR" start="0x0" description="OR. The event occurs when either the specified match or I/O condition occurs." /> + <Enum name="MATCH" start="0x1" description="MATCH. Uses the specified match only." /> + <Enum name="IO" start="0x2" description="IO. Uses the specified I/O condition only." /> + <Enum name="AND" start="0x3" description="AND. The event occurs when the specified match and I/O condition occur simultaneously." /> + </BitField> + <BitField start="14" size="1" name="STATELD" description="This bit controls how the STATEV value modifies the state selected by HEVENT when this event is the highest-numbered event occurring for that state."> + <Enum name="STATEV_VALUE_IS_ADDE" start="0" description="STATEV value is added into STATE (the carry-out is ignored)." /> + <Enum name="STATEV_VALUE_IS_LOAD" start="1" description="STATEV value is loaded into STATE." /> + </BitField> + <BitField start="15" size="5" name="STATEV" description="This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state. If STATELD and STATEV are both zero, there is no change to the STATE value." /> + <BitField start="20" size="1" name="MATCHMEM" description="If this bit is one and the COMBMODE field specifies a match component to the triggering of this event, then a match is considered to be active whenever the counter value is GREATER THAN OR EQUAL TO the value specified in the match register when counting up, LESS THEN OR EQUAL TO the match value when counting down. If this bit is zero, a match is only be active during the cycle when the counter is equal to the match value." /> + <BitField start="21" size="2" name="DIRECTION" description="Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved."> + <Enum name="DIRECTION_INDEPENDEN" start="0x0" description="Direction independent. This event is triggered regardless of the count direction." /> + <Enum name="COUNTING_UP" start="0x1" description="Counting up. This event is triggered only during up-counting when BIDIR = 1." /> + <Enum name="COUNTING_DOWN" start="0x2" description="Counting down. This event is triggered only during down-counting when BIDIR = 1." /> + </BitField> + <BitField start="23" size="9" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x500+0" size="4" name="OUT0_SET" access="Read/Write" description="SCT output 0 set register" reset_value="0x00000000" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="6" name="SET" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 5 = bit 5." /> + <BitField start="6" size="26" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x500+8" size="4" name="OUT1_SET" access="Read/Write" description="SCT output 0 set register" reset_value="0x00000000" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="6" name="SET" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 5 = bit 5." /> + <BitField start="6" size="26" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x500+16" size="4" name="OUT2_SET" access="Read/Write" description="SCT output 0 set register" reset_value="0x00000000" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="6" name="SET" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 5 = bit 5." /> + <BitField start="6" size="26" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x500+24" size="4" name="OUT3_SET" access="Read/Write" description="SCT output 0 set register" reset_value="0x00000000" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="6" name="SET" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 5 = bit 5." /> + <BitField start="6" size="26" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x504+0" size="4" name="OUT0_CLR" access="Read/Write" description="SCT output 0 clear register" reset_value="0x00000000" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="6" name="CLR" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 5 = bit 5." /> + <BitField start="6" size="26" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x504+8" size="4" name="OUT1_CLR" access="Read/Write" description="SCT output 0 clear register" reset_value="0x00000000" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="6" name="CLR" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 5 = bit 5." /> + <BitField start="6" size="26" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x504+16" size="4" name="OUT2_CLR" access="Read/Write" description="SCT output 0 clear register" reset_value="0x00000000" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="6" name="CLR" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 5 = bit 5." /> + <BitField start="6" size="26" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x504+24" size="4" name="OUT3_CLR" access="Read/Write" description="SCT output 0 clear register" reset_value="0x00000000" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="6" name="CLR" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 5 = bit 5." /> + <BitField start="6" size="26" name="RESERVED" description="Reserved" /> + </Register> + </RegisterGroup> + <RegisterGroup name="SCT1" start="0x5000E000" description="SCT1"> + <Register start="+0x000" size="4" name="CONFIG" access="Read/Write" description="SCT configuration register" reset_value="0x00007E00" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="UNIFY" description="SCT operation"> + <Enum name="THE_SCT_OPERATES_AS" start="0" description="The SCT operates as two 16-bit counters named L and H." /> + <Enum name="THE_SCT_OPERATES_AS" start="1" description="The SCT operates as a unified 32-bit counter." /> + </BitField> + <BitField start="1" size="2" name="CLKMODE" description="SCT clock mode"> + <Enum name="THE_BUS_CLOCK_CLOCKS" start="0x0" description="The bus clock clocks the SCT and prescalers." /> + <Enum name="THE_SCT_CLOCK_IS_THE" start="0x1" description="The SCT clock is the bus clock, but the prescalers are enabled to count only when sampling of the input selected by the CKSEL field finds the selected edge. The minimum pulse width on the clock input is 1 bus clock period. This mode is the high-performance sampled-clock mode." /> + <Enum name="THE_INPUT_SELECTED_B" start="0x2" description="The input selected by CKSEL clocks the SCT and prescalers. The input is synchronized to the bus clock and possibly inverted. The minimum pulse width on the clock input is 1 bus clock period. This mode is the low-power sampled-clock mode." /> + <Enum name="PRESCALED_SCT_INPUT" start="0x3" description="Prescaled SCT input. The SCT and prescalers are clocked by the input edge selected by the CKSEL field. In this mode, most of the SCT is clocked by the (selected polarity of the) input. The outputs are switched synchronously to the input clock. The input clock rate must be at least half the system clock rate and can the same or faster than the system clock." /> + </BitField> + <BitField start="3" size="4" name="CKSEL" description="SCT clock select"> + <Enum name="RISING_EDGES_ON_INPU" start="0x0" description="Rising edges on input 0." /> + <Enum name="FALLING_EDGES_ON_INP" start="0x1" description="Falling edges on input 0." /> + <Enum name="RISING_EDGES_ON_INPU" start="0x2" description="Rising edges on input 1." /> + <Enum name="FALLING_EDGES_ON_INP" start="0x3" description="Falling edges on input 1." /> + <Enum name="RISING_EDGES_ON_INPU" start="0x4" description="Rising edges on input 2." /> + <Enum name="FALLING_EDGES_ON_INP" start="0x5" description="Falling edges on input 2." /> + <Enum name="RISING_EDGES_ON_INPU" start="0x6" description="Rising edges on input 3." /> + <Enum name="FALLING_EDGES_ON_INP" start="0x7" description="Falling edges on input 3." /> + </BitField> + <BitField start="7" size="1" name="NORELAOD_L" description="A 1 in this bit prevents the lower match registers from being reloaded from their respective reload registers. Software can write to set or clear this bit at any time. This bit applies to both the higher and lower registers when the UNIFY bit is set." /> + <BitField start="8" size="1" name="NORELOAD_H" description="A 1 in this bit prevents the higher match registers from being reloaded from their respective reload registers. Software can write to set or clear this bit at any time. This bit is not used when the UNIFY bit is set." /> + <BitField start="9" size="8" name="INSYNC" description="Synchronization for input N (bit 9 = input 0, bit 10 = input 1,..., bit 12 = input 3); all other bits are reserved. A 1 in one of these bits subjects the corresponding input to synchronization to the SCT clock, before it is used to create an event. If an input is synchronous to the SCT clock, keep its bit 0 for faster response. When the CKMODE field is 1x, the bit in this field, corresponding to the input selected by the CKSEL field, is not used." /> + <BitField start="17" size="1" name="AUTOLIMIT_L" description="A one in this bit causes a match on match register 0 to be treated as a de-facto LIMIT condition without the need to define an associated event. As with any LIMIT event, this automatic limit causes the counter to be cleared to zero in uni-directional mode or to change the direction of count in bi-directional mode. Software can write to set or clear this bit at any time. This bit applies to both the higher and lower registers when the UNIFY bit is set." /> + <BitField start="18" size="1" name="AUTOLIMIT_H" description="A one in this bit will cause a match on match register 0 to be treated as a de-facto LIMIT condition without the need to define an associated event. As with any LIMIT event, this automatic limit causes the counter to be cleared to zero in uni-directional mode or to change the direction of count in bi-directional mode. Software can write to set or clear this bit at any time. This bit is not used when the UNIFY bit is set." /> + <BitField start="19" size="13" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x004" size="4" name="CTRL" access="Read/Write" description="SCT control register" reset_value="0x00040004" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="DOWN_L" description="This bit is 1 when the L or unified counter is counting down. Hardware sets this bit when the counter limit is reached and BIDIR is 1. Hardware clears this bit when the counter is counting down and a limit condition occurs or when the counter reaches 0." /> + <BitField start="1" size="1" name="STOP_L" description="When this bit is 1 and HALT is 0, the L or unified counter does not run, but I/O events related to the counter can occur. If such an event matches the mask in the Start register, this bit is cleared and counting resumes." /> + <BitField start="2" size="1" name="HALT_L" description="When this bit is 1, the L or unified counter does not run and no events can occur. A reset sets this bit. When the HALT_L bit is one, the STOP_L bit is cleared. If you want to remove the halt condition and keep the SCT in the stop condition (not running), then you can change the halt and stop condition with one single write to this register. Once set, only software can clear this bit to restore counter operation." /> + <BitField start="3" size="1" name="CLRCTR_L" description="Writing a 1 to this bit clears the L or unified counter. This bit always reads as 0." /> + <BitField start="4" size="1" name="BIDIR_L" description="L or unified counter direction select"> + <Enum name="THE_COUNTER_COUNTS_U" start="0" description="The counter counts up to its limit condition, then is cleared to zero." /> + <Enum name="THE_COUNTER_COUNTS_U" start="1" description="The counter counts up to its limit, then counts down to a limit condition or to 0." /> + </BitField> + <BitField start="5" size="8" name="PRE_L" description="Specifies the factor by which the SCT clock is prescaled to produce the L or unified counter clock. The counter clock is clocked at the rate of the SCT clock divided by PRE_L+1. Clear the counter (by writing a 1 to the CLRCTR bit) whenever changing the PRE value." /> + <BitField start="13" size="3" name="RESERVED" description="Reserved" /> + <BitField start="16" size="1" name="DOWN_H" description="This bit is 1 when the H counter is counting down. Hardware sets this bit when the counter limit is reached and BIDIR is 1. Hardware clears this bit when the counter is counting down and a limit condition occurs or when the counter reaches 0." /> + <BitField start="17" size="1" name="STOP_H" description="When this bit is 1 and HALT is 0, the H counter does not, run but I/O events related to the counter can occur. If such an event matches the mask in the Start register, this bit is cleared and counting resumes." /> + <BitField start="18" size="1" name="HALT_H" description="When this bit is 1, the H counter does not run and no events can occur. A reset sets this bit. When the HALT_H bit is one, the STOP_H bit is cleared. If you want to remove the halt condition and keep the SCT in the stop condition (not running), then you can change the halt and stop condition with one single write to this register. Once set, this bit can only be cleared by software to restore counter operation." /> + <BitField start="19" size="1" name="CLRCTR_H" description="Writing a 1 to this bit clears the H counter. This bit always reads as 0." /> + <BitField start="20" size="1" name="BIDIR_H" description="Direction select"> + <Enum name="THE_H_COUNTER_COUNTS" start="0" description="The H counter counts up to its limit condition, then is cleared to zero." /> + <Enum name="THE_H_COUNTER_COUNTS" start="1" description="The H counter counts up to its limit, then counts down to a limit condition or to 0." /> + </BitField> + <BitField start="21" size="8" name="PRE_H" description="Specifies the factor by which the SCT clock is prescaled to produce the H counter clock. The counter clock is clocked at the rate of the SCT clock divided by PRELH+1. Clear the counter (by writing a 1 to the CLRCTR bit) whenever changing the PRE value." /> + <BitField start="29" size="3" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x008" size="4" name="LIMIT" access="Read/Write" description="SCT limit register" reset_value="0x00000000" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="6" name="LIMMSK_L" description="If bit n is one, event n is used as a counter limit for the L or unified counter (event 0 = bit 0, event 1 = bit 1, event 5 = bit 5)." /> + <BitField start="6" size="10" name="RESERVED" description="Reserved." /> + <BitField start="16" size="6" name="LIMMSK_H" description="If bit n is one, event n is used as a counter limit for the H counter (event 0 = bit 16, event 1 = bit 17, event 5 = bit 21)." /> + <BitField start="22" size="10" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x00C" size="4" name="HALT" access="Read/Write" description="SCT halt condition register" reset_value="0x00000000" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="6" name="HALTMSK_L" description="If bit n is one, event n sets the HALT_L bit in the CTRL register (event 0 = bit 0, event 1 = bit 1, event 5 = bit 5)." /> + <BitField start="6" size="10" name="RESERVED" description="Reserved." /> + <BitField start="16" size="6" name="HALTMSK_H" description="If bit n is one, event n sets the HALT_H bit in the CTRL register (event 0 = bit 16, event 1 = bit 17, event 5 = bit 21)." /> + <BitField start="22" size="10" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x010" size="4" name="STOP" access="Read/Write" description="SCT stop condition register" reset_value="0x00000000" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="6" name="STOPMSK_L" description="If bit n is one, event n sets the STOP_L bit in the CTRL register (event 0 = bit 0, event 1 = bit 1, event 5 = bit 5)." /> + <BitField start="6" size="10" name="RESERVED" description="Reserved." /> + <BitField start="16" size="6" name="STOPMSK_H" description="If bit n is one, event n sets the STOP_H bit in the CTRL register (event 0 = bit 16, event 1 = bit 17, event 5 = bit 21)." /> + <BitField start="22" size="10" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x014" size="4" name="START" access="Read/Write" description="SCT start condition register" reset_value="0x00000000" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="6" name="STARTMSK_L" description="If bit n is one, event n clears the STOP_L bit in the CTRL register (event 0 = bit 0, event 1 = bit 1, event 5 = bit 5)." /> + <BitField start="6" size="10" name="RESERVED" description="Reserved." /> + <BitField start="16" size="6" name="STARTMSK_H" description="If bit n is one, event n clears the STOP_H bit in the CTRL register (event 0 = bit 16, event 1 = bit 17, event 5 = bit 21)." /> + <BitField start="22" size="10" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x040" size="4" name="COUNT" access="Read/Write" description="SCT counter register" reset_value="0x00000000" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="16" name="CTR_L" description="When UNIFY = 0, read or write the 16-bit L counter value. When UNIFY = 1, read or write the lower 16 bits of the 32-bit unified counter." /> + <BitField start="16" size="16" name="CTR_H" description="When UNIFY = 0, read or write the 16-bit H counter value. When UNIFY = 1, read or write the upper 16 bits of the 32-bit unified counter." /> + </Register> + <Register start="+0x044" size="4" name="STATE" access="Read/Write" description="SCT state register" reset_value="0x00000000" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="STATE_L" description="State variable." /> + <BitField start="5" size="11" name="RESERVED" description="Reserved." /> + <BitField start="16" size="5" name="STATE_H" description="State variable." /> + <BitField start="21" size="11" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x048" size="4" name="INPUT" access="ReadOnly" description="SCT input register" reset_value="0x00000000" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="AIN0" description="Real-time status of input 0." /> + <BitField start="1" size="1" name="AIN1" description="Real-time status of input 1." /> + <BitField start="2" size="1" name="AIN2" description="Real-time status of input 2." /> + <BitField start="3" size="1" name="AIN3" description="Real-time status of input 3." /> + <BitField start="4" size="12" name="RESERVED" description="Reserved." /> + <BitField start="16" size="1" name="SIN0" description="Input 0 state synchronized to the SCT clock." /> + <BitField start="17" size="1" name="SIN1" description="Input 1 state synchronized to the SCT clock." /> + <BitField start="18" size="1" name="SIN2" description="Input 2 state synchronized to the SCT clock." /> + <BitField start="19" size="1" name="SIN3" description="Input 3 state synchronized to the SCT clock." /> + <BitField start="20" size="12" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x04C" size="4" name="REGMODE" access="Read/Write" description="SCT match/capture registers mode register" reset_value="0x00000000" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="REGMOD_L" description="Each bit controls one pair of match/capture registers (register 0 = bit 0, register 1 = bit 1,..., register 4 = bit 4). 0 = registers operate as match registers. 1 = registers operate as capture registers." /> + <BitField start="5" size="11" name="RESERVED" description="Reserved." /> + <BitField start="16" size="5" name="REGMOD_H" description="Each bit controls one pair of match/capture registers (register 0 = bit 16, register 1 = bit 17,..., register 4 = bit 20). 0 = registers operate as match registers. 1 = registers operate as capture registers." /> + <BitField start="21" size="11" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x050" size="4" name="OUTPUT" access="Read/Write" description="SCT output register" reset_value="0x00000000" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="4" name="OUT" description="Writing a 1 to bit n makes the corresponding output HIGH. 0 makes the corresponding output LOW (output 0 = bit 0, output 1 = bit 1,..., output 3 = bit 3)." /> + <BitField start="4" size="28" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x054" size="4" name="OUTPUTDIRCTRL" access="Read/Write" description="SCT output counter direction control register" reset_value="0x00000000" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="SETCLR0" description="Set/clear operation on output 0. Value 0x3 is reserved. Do not program this value."> + <Enum name="SET_AND_CLEAR_DO_NOT" start="0x0" description="Set and clear do not depend on any counter." /> + <Enum name="SET_AND_CLEAR_ARE_RE" start="0x1" description="Set and clear are reversed when counter L or the unified counter is counting down." /> + <Enum name="SET_AND_CLEAR_ARE_RE" start="0x2" description="Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1." /> + </BitField> + <BitField start="2" size="2" name="SETCLR1" description="Set/clear operation on output 1. Value 0x3 is reserved. Do not program this value."> + <Enum name="SET_AND_CLEAR_DO_NOT" start="0x0" description="Set and clear do not depend on any counter." /> + <Enum name="SET_AND_CLEAR_ARE_RE" start="0x1" description="Set and clear are reversed when counter L or the unified counter is counting down." /> + <Enum name="SET_AND_CLEAR_ARE_RE" start="0x2" description="Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1." /> + </BitField> + <BitField start="4" size="2" name="SETCLR2" description="Set/clear operation on output 2. Value 0x3 is reserved. Do not program this value."> + <Enum name="SET_AND_CLEAR_DO_NOT" start="0x0" description="Set and clear do not depend on any counter." /> + <Enum name="SET_AND_CLEAR_ARE_RE" start="0x1" description="Set and clear are reversed when counter L or the unified counter is counting down." /> + <Enum name="SET_AND_CLEAR_ARE_RE" start="0x2" description="Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1." /> + </BitField> + <BitField start="6" size="2" name="SETCLR3" description="Set/clear operation on output 3. Value 0x3 is reserved. Do not program this value."> + <Enum name="SET_AND_CLEAR_DO_NOT" start="0x0" description="Set and clear do not depend on any counter." /> + <Enum name="SET_AND_CLEAR_ARE_RE" start="0x1" description="Set and clear are reversed when counter L or the unified counter is counting down." /> + <Enum name="SET_AND_CLEAR_ARE_RE" start="0x2" description="Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1." /> + </BitField> + <BitField start="8" size="24" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x058" size="4" name="RES" access="Read/Write" description="SCT conflict resolution register" reset_value="0x00000000" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="O0RES" description="Effect of simultaneous set and clear on output 0."> + <Enum name="NO_CHANGE" start="0x0" description="No change." /> + <Enum name="SET_OUTPUT_OR_CLEAR" start="0x1" description="Set output (or clear based on the SETCLR0 field)." /> + <Enum name="CLEAR_OUTPUT_OR_SET" start="0x2" description="Clear output (or set based on the SETCLR0 field)." /> + <Enum name="TOGGLE_OUTPUT" start="0x3" description="Toggle output." /> + </BitField> + <BitField start="2" size="2" name="O1RES" description="Effect of simultaneous set and clear on output 1."> + <Enum name="NO_CHANGE" start="0x0" description="No change." /> + <Enum name="SET_OUTPUT_OR_CLEAR" start="0x1" description="Set output (or clear based on the SETCLR1 field)." /> + <Enum name="CLEAR_OUTPUT_OR_SET" start="0x2" description="Clear output (or set based on the SETCLR1 field)." /> + <Enum name="TOGGLE_OUTPUT" start="0x3" description="Toggle output." /> + </BitField> + <BitField start="4" size="2" name="O2RES" description="Effect of simultaneous set and clear on output 2."> + <Enum name="NO_CHANGE" start="0x0" description="No change." /> + <Enum name="SET_OUTPUT_OR_CLEAR" start="0x1" description="Set output (or clear based on the SETCLR2 field)." /> + <Enum name="CLEAR_OUTPUT_N_OR_S" start="0x2" description="Clear output n (or set based on the SETCLR2 field)." /> + <Enum name="TOGGLE_OUTPUT" start="0x3" description="Toggle output." /> + </BitField> + <BitField start="6" size="2" name="O3RES" description="Effect of simultaneous set and clear on output 3."> + <Enum name="NO_CHANGE" start="0x0" description="No change." /> + <Enum name="SET_OUTPUT_OR_CLEAR" start="0x1" description="Set output (or clear based on the SETCLR3 field)." /> + <Enum name="CLEAR_OUTPUT_OR_SET" start="0x2" description="Clear output (or set based on the SETCLR3 field)." /> + <Enum name="TOGGLE_OUTPUT" start="0x3" description="Toggle output." /> + </BitField> + <BitField start="8" size="24" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x05C" size="4" name="DMAREQ0" access="Read/Write" description="SCT DMA request 0 register" reset_value="0x00000000" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="6" name="DEV_0" description="If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 5 = bit 5)." /> + <BitField start="6" size="24" name="RESERVED" description="Reserved" /> + <BitField start="30" size="1" name="DRL0" description="A 1 in this bit makes the SCT set DMA request 0 when it loads the Match_L/Unified registers from the Reload_L/Unified registers." /> + <BitField start="31" size="1" name="DRQ0" description="This read-only bit indicates the state of DMA Request 0" /> + </Register> + <Register start="+0x060" size="4" name="DMAREQ1" access="Read/Write" description="SCT DMA request 1 register" reset_value="0x00000000" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="6" name="DEV_1" description="If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 5 = bit 5)." /> + <BitField start="6" size="24" name="RESERVED" description="Reserved" /> + <BitField start="30" size="1" name="DRL1" description="A 1 in this bit makes the SCT set DMA request 1 when it loads the Match L/Unified registers from the Reload L/Unified registers." /> + <BitField start="31" size="1" name="DRQ1" description="This read-only bit indicates the state of DMA Request 1." /> + </Register> + <Register start="+0x0F0" size="4" name="EVEN" access="Read/Write" description="SCT event enable register" reset_value="0x00000000" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="6" name="IEN" description="The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 5 = bit 5)." /> + <BitField start="6" size="26" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x0F4" size="4" name="EVFLAG" access="Read/Write" description="SCT event flag register" reset_value="0x00000000" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="6" name="FLAG" description="Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 5 = bit 5)." /> + <BitField start="6" size="26" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x0F8" size="4" name="CONEN" access="Read/Write" description="SCT conflict enable register" reset_value="0x00000000" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="4" name="NCEN" description="The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 3 = bit 3)." /> + <BitField start="4" size="28" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x0FC" size="4" name="CONFLAG" access="Read/Write" description="SCT conflict flag register" reset_value="0x00000000" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="4" name="NCFLAG" description="Bit n is one if a no-change conflict event occurred on output n since reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 3 = bit 3)." /> + <BitField start="4" size="26" name="RESERVED" description="Reserved." /> + <BitField start="30" size="1" name="BUSERRL" description="The most recent bus error from this SCT involved writing CTR L/Unified, STATE L/Unified, MATCH L/Unified, or the Output register when the L/U counter was not halted. A word write to certain L and H registers can be half successful and half unsuccessful." /> + <BitField start="31" size="1" name="BUSERRH" description="The most recent bus error from this SCT involved writing CTR H, STATE H, MATCH H, or the Output register when the H counter was not halted." /> + </Register> + <Register start="+0x100+0" size="4" name="MATCH0" access="Read/Write" description="SCT match value register of match channels 0 to 4; REGMOD0 to REGMODE4 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="16" name="MATCHn_L" description="When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter." /> + <BitField start="16" size="16" name="MATCHn_H" description="When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter." /> + </Register> + <Register start="+0x100+4" size="4" name="MATCH1" access="Read/Write" description="SCT match value register of match channels 0 to 4; REGMOD0 to REGMODE4 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="16" name="MATCHn_L" description="When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter." /> + <BitField start="16" size="16" name="MATCHn_H" description="When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter." /> + </Register> + <Register start="+0x100+8" size="4" name="MATCH2" access="Read/Write" description="SCT match value register of match channels 0 to 4; REGMOD0 to REGMODE4 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="16" name="MATCHn_L" description="When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter." /> + <BitField start="16" size="16" name="MATCHn_H" description="When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter." /> + </Register> + <Register start="+0x100+12" size="4" name="MATCH3" access="Read/Write" description="SCT match value register of match channels 0 to 4; REGMOD0 to REGMODE4 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="16" name="MATCHn_L" description="When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter." /> + <BitField start="16" size="16" name="MATCHn_H" description="When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter." /> + </Register> + <Register start="+0x100+16" size="4" name="MATCH4" access="Read/Write" description="SCT match value register of match channels 0 to 4; REGMOD0 to REGMODE4 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="16" name="MATCHn_L" description="When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter." /> + <BitField start="16" size="16" name="MATCHn_H" description="When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter." /> + </Register> + <Register start="+0x100+0" size="4" name="CAP0" access="Read/Write" description="SCT capture register of capture channel 0 to 4; REGMOD0 to REGMODE4 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="16" name="CAPn_L" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured." /> + <BitField start="16" size="16" name="CAPn_H" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured." /> + </Register> + <Register start="+0x100+4" size="4" name="CAP1" access="Read/Write" description="SCT capture register of capture channel 0 to 4; REGMOD0 to REGMODE4 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="16" name="CAPn_L" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured." /> + <BitField start="16" size="16" name="CAPn_H" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured." /> + </Register> + <Register start="+0x100+8" size="4" name="CAP2" access="Read/Write" description="SCT capture register of capture channel 0 to 4; REGMOD0 to REGMODE4 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="16" name="CAPn_L" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured." /> + <BitField start="16" size="16" name="CAPn_H" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured." /> + </Register> + <Register start="+0x100+12" size="4" name="CAP3" access="Read/Write" description="SCT capture register of capture channel 0 to 4; REGMOD0 to REGMODE4 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="16" name="CAPn_L" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured." /> + <BitField start="16" size="16" name="CAPn_H" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured." /> + </Register> + <Register start="+0x100+16" size="4" name="CAP4" access="Read/Write" description="SCT capture register of capture channel 0 to 4; REGMOD0 to REGMODE4 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="16" name="CAPn_L" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured." /> + <BitField start="16" size="16" name="CAPn_H" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured." /> + </Register> + <Register start="+0x200+0" size="4" name="MATCHREL0" access="Read/Write" description="SCT match reload value register 0 to 4; REGMOD0 = 0 to REGMODE4 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="16" name="RELOADn_L" description="When UNIFY = 0, read or write the 16-bit value to be loaded into the SCTMATCHn_L register. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be loaded into the MATCHn register." /> + <BitField start="16" size="16" name="RELOADn_H" description="When UNIFY = 0, read or write the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be loaded into the MATCHn register." /> + </Register> + <Register start="+0x200+4" size="4" name="MATCHREL1" access="Read/Write" description="SCT match reload value register 0 to 4; REGMOD0 = 0 to REGMODE4 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="16" name="RELOADn_L" description="When UNIFY = 0, read or write the 16-bit value to be loaded into the SCTMATCHn_L register. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be loaded into the MATCHn register." /> + <BitField start="16" size="16" name="RELOADn_H" description="When UNIFY = 0, read or write the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be loaded into the MATCHn register." /> + </Register> + <Register start="+0x200+8" size="4" name="MATCHREL2" access="Read/Write" description="SCT match reload value register 0 to 4; REGMOD0 = 0 to REGMODE4 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="16" name="RELOADn_L" description="When UNIFY = 0, read or write the 16-bit value to be loaded into the SCTMATCHn_L register. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be loaded into the MATCHn register." /> + <BitField start="16" size="16" name="RELOADn_H" description="When UNIFY = 0, read or write the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be loaded into the MATCHn register." /> + </Register> + <Register start="+0x200+12" size="4" name="MATCHREL3" access="Read/Write" description="SCT match reload value register 0 to 4; REGMOD0 = 0 to REGMODE4 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="16" name="RELOADn_L" description="When UNIFY = 0, read or write the 16-bit value to be loaded into the SCTMATCHn_L register. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be loaded into the MATCHn register." /> + <BitField start="16" size="16" name="RELOADn_H" description="When UNIFY = 0, read or write the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be loaded into the MATCHn register." /> + </Register> + <Register start="+0x200+16" size="4" name="MATCHREL4" access="Read/Write" description="SCT match reload value register 0 to 4; REGMOD0 = 0 to REGMODE4 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="16" name="RELOADn_L" description="When UNIFY = 0, read or write the 16-bit value to be loaded into the SCTMATCHn_L register. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be loaded into the MATCHn register." /> + <BitField start="16" size="16" name="RELOADn_H" description="When UNIFY = 0, read or write the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be loaded into the MATCHn register." /> + </Register> + <Register start="+0x200+0" size="4" name="CAPCTRL0" access="Read/Write" description="SCT capture control register 0 to 4; REGMOD0 = 1 to REGMODE4 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="6" name="CAPCONn_L" description="If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1,..., event 5 = bit 5)." /> + <BitField start="6" size="10" name="RESERVED" description="Reserved." /> + <BitField start="16" size="6" name="CAPCONn_H" description="If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17,..., event 5 = bit 21)." /> + <BitField start="22" size="10" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x200+4" size="4" name="CAPCTRL1" access="Read/Write" description="SCT capture control register 0 to 4; REGMOD0 = 1 to REGMODE4 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="6" name="CAPCONn_L" description="If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1,..., event 5 = bit 5)." /> + <BitField start="6" size="10" name="RESERVED" description="Reserved." /> + <BitField start="16" size="6" name="CAPCONn_H" description="If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17,..., event 5 = bit 21)." /> + <BitField start="22" size="10" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x200+8" size="4" name="CAPCTRL2" access="Read/Write" description="SCT capture control register 0 to 4; REGMOD0 = 1 to REGMODE4 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="6" name="CAPCONn_L" description="If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1,..., event 5 = bit 5)." /> + <BitField start="6" size="10" name="RESERVED" description="Reserved." /> + <BitField start="16" size="6" name="CAPCONn_H" description="If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17,..., event 5 = bit 21)." /> + <BitField start="22" size="10" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x200+12" size="4" name="CAPCTRL3" access="Read/Write" description="SCT capture control register 0 to 4; REGMOD0 = 1 to REGMODE4 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="6" name="CAPCONn_L" description="If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1,..., event 5 = bit 5)." /> + <BitField start="6" size="10" name="RESERVED" description="Reserved." /> + <BitField start="16" size="6" name="CAPCONn_H" description="If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17,..., event 5 = bit 21)." /> + <BitField start="22" size="10" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x200+16" size="4" name="CAPCTRL4" access="Read/Write" description="SCT capture control register 0 to 4; REGMOD0 = 1 to REGMODE4 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="6" name="CAPCONn_L" description="If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1,..., event 5 = bit 5)." /> + <BitField start="6" size="10" name="RESERVED" description="Reserved." /> + <BitField start="16" size="6" name="CAPCONn_H" description="If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17,..., event 5 = bit 21)." /> + <BitField start="22" size="10" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x300+0" size="4" name="EV0_STATE" access="Read/Write" description="SCT event state register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="STATEMSKn" description="If bit m is one, event n (n= 0 to 5) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 7 = bit 7)." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x300+8" size="4" name="EV1_STATE" access="Read/Write" description="SCT event state register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="STATEMSKn" description="If bit m is one, event n (n= 0 to 5) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 7 = bit 7)." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x300+16" size="4" name="EV2_STATE" access="Read/Write" description="SCT event state register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="STATEMSKn" description="If bit m is one, event n (n= 0 to 5) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 7 = bit 7)." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x300+24" size="4" name="EV3_STATE" access="Read/Write" description="SCT event state register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="STATEMSKn" description="If bit m is one, event n (n= 0 to 5) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 7 = bit 7)." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x300+32" size="4" name="EV4_STATE" access="Read/Write" description="SCT event state register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="STATEMSKn" description="If bit m is one, event n (n= 0 to 5) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 7 = bit 7)." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x300+40" size="4" name="EV5_STATE" access="Read/Write" description="SCT event state register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="STATEMSKn" description="If bit m is one, event n (n= 0 to 5) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 7 = bit 7)." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x304+0" size="4" name="EV0_CTRL" access="Read/Write" description="SCT event control register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="4" name="MATCHSEL" description="Selects the Match register associated with this event (if any). A match can occur only when the counter selected by the HEVENT bit is running." /> + <BitField start="4" size="1" name="HEVENT" description="Select L/H counter. Do not set this bit if UNIFY = 1."> + <Enum name="SELECTS_THE_L_STATE" start="0" description="Selects the L state and the L match register selected by MATCHSEL." /> + <Enum name="SELECTS_THE_H_STATE" start="1" description="Selects the H state and the H match register selected by MATCHSEL." /> + </BitField> + <BitField start="5" size="1" name="OUTSEL" description="Input/output select"> + <Enum name="SELECTS_THE_INPUTS_E" start="0" description="Selects the inputs elected by IOSEL." /> + <Enum name="SELECTS_THE_OUTPUTS" start="1" description="Selects the outputs selected by IOSEL." /> + </BitField> + <BitField start="6" size="4" name="IOSEL" description="Selects the input or output signal number (0 to 3) associated with this event (if any). Do not select an input in this register, if CKMODE is 1x. In this case the clock input is an implicit ingredient of every event." /> + <BitField start="10" size="2" name="IOCOND" description="Selects the I/O condition for event n. (The detection of edges on outputs lag the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT clock period ."> + <Enum name="LOW" start="0x0" description="LOW" /> + <Enum name="RISE" start="0x1" description="Rise" /> + <Enum name="FALL" start="0x2" description="Fall" /> + <Enum name="HIGH" start="0x3" description="HIGH" /> + </BitField> + <BitField start="12" size="2" name="COMBMODE" description="Selects how the specified match and I/O condition are used and combined."> + <Enum name="OR" start="0x0" description="OR. The event occurs when either the specified match or I/O condition occurs." /> + <Enum name="MATCH" start="0x1" description="MATCH. Uses the specified match only." /> + <Enum name="IO" start="0x2" description="IO. Uses the specified I/O condition only." /> + <Enum name="AND" start="0x3" description="AND. The event occurs when the specified match and I/O condition occur simultaneously." /> + </BitField> + <BitField start="14" size="1" name="STATELD" description="This bit controls how the STATEV value modifies the state selected by HEVENT when this event is the highest-numbered event occurring for that state."> + <Enum name="STATEV_VALUE_IS_ADDE" start="0" description="STATEV value is added into STATE (the carry-out is ignored)." /> + <Enum name="STATEV_VALUE_IS_LOAD" start="1" description="STATEV value is loaded into STATE." /> + </BitField> + <BitField start="15" size="5" name="STATEV" description="This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state. If STATELD and STATEV are both zero, there is no change to the STATE value." /> + <BitField start="20" size="1" name="MATCHMEM" description="If this bit is one and the COMBMODE field specifies a match component to the triggering of this event, then a match is considered to be active whenever the counter value is GREATER THAN OR EQUAL TO the value specified in the match register when counting up, LESS THEN OR EQUAL TO the match value when counting down. If this bit is zero, a match is only be active during the cycle when the counter is equal to the match value." /> + <BitField start="21" size="2" name="DIRECTION" description="Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved."> + <Enum name="DIRECTION_INDEPENDEN" start="0x0" description="Direction independent. This event is triggered regardless of the count direction." /> + <Enum name="COUNTING_UP" start="0x1" description="Counting up. This event is triggered only during up-counting when BIDIR = 1." /> + <Enum name="COUNTING_DOWN" start="0x2" description="Counting down. This event is triggered only during down-counting when BIDIR = 1." /> + </BitField> + <BitField start="23" size="9" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x304+8" size="4" name="EV1_CTRL" access="Read/Write" description="SCT event control register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="4" name="MATCHSEL" description="Selects the Match register associated with this event (if any). A match can occur only when the counter selected by the HEVENT bit is running." /> + <BitField start="4" size="1" name="HEVENT" description="Select L/H counter. Do not set this bit if UNIFY = 1."> + <Enum name="SELECTS_THE_L_STATE" start="0" description="Selects the L state and the L match register selected by MATCHSEL." /> + <Enum name="SELECTS_THE_H_STATE" start="1" description="Selects the H state and the H match register selected by MATCHSEL." /> + </BitField> + <BitField start="5" size="1" name="OUTSEL" description="Input/output select"> + <Enum name="SELECTS_THE_INPUTS_E" start="0" description="Selects the inputs elected by IOSEL." /> + <Enum name="SELECTS_THE_OUTPUTS" start="1" description="Selects the outputs selected by IOSEL." /> + </BitField> + <BitField start="6" size="4" name="IOSEL" description="Selects the input or output signal number (0 to 3) associated with this event (if any). Do not select an input in this register, if CKMODE is 1x. In this case the clock input is an implicit ingredient of every event." /> + <BitField start="10" size="2" name="IOCOND" description="Selects the I/O condition for event n. (The detection of edges on outputs lag the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT clock period ."> + <Enum name="LOW" start="0x0" description="LOW" /> + <Enum name="RISE" start="0x1" description="Rise" /> + <Enum name="FALL" start="0x2" description="Fall" /> + <Enum name="HIGH" start="0x3" description="HIGH" /> + </BitField> + <BitField start="12" size="2" name="COMBMODE" description="Selects how the specified match and I/O condition are used and combined."> + <Enum name="OR" start="0x0" description="OR. The event occurs when either the specified match or I/O condition occurs." /> + <Enum name="MATCH" start="0x1" description="MATCH. Uses the specified match only." /> + <Enum name="IO" start="0x2" description="IO. Uses the specified I/O condition only." /> + <Enum name="AND" start="0x3" description="AND. The event occurs when the specified match and I/O condition occur simultaneously." /> + </BitField> + <BitField start="14" size="1" name="STATELD" description="This bit controls how the STATEV value modifies the state selected by HEVENT when this event is the highest-numbered event occurring for that state."> + <Enum name="STATEV_VALUE_IS_ADDE" start="0" description="STATEV value is added into STATE (the carry-out is ignored)." /> + <Enum name="STATEV_VALUE_IS_LOAD" start="1" description="STATEV value is loaded into STATE." /> + </BitField> + <BitField start="15" size="5" name="STATEV" description="This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state. If STATELD and STATEV are both zero, there is no change to the STATE value." /> + <BitField start="20" size="1" name="MATCHMEM" description="If this bit is one and the COMBMODE field specifies a match component to the triggering of this event, then a match is considered to be active whenever the counter value is GREATER THAN OR EQUAL TO the value specified in the match register when counting up, LESS THEN OR EQUAL TO the match value when counting down. If this bit is zero, a match is only be active during the cycle when the counter is equal to the match value." /> + <BitField start="21" size="2" name="DIRECTION" description="Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved."> + <Enum name="DIRECTION_INDEPENDEN" start="0x0" description="Direction independent. This event is triggered regardless of the count direction." /> + <Enum name="COUNTING_UP" start="0x1" description="Counting up. This event is triggered only during up-counting when BIDIR = 1." /> + <Enum name="COUNTING_DOWN" start="0x2" description="Counting down. This event is triggered only during down-counting when BIDIR = 1." /> + </BitField> + <BitField start="23" size="9" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x304+16" size="4" name="EV2_CTRL" access="Read/Write" description="SCT event control register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="4" name="MATCHSEL" description="Selects the Match register associated with this event (if any). A match can occur only when the counter selected by the HEVENT bit is running." /> + <BitField start="4" size="1" name="HEVENT" description="Select L/H counter. Do not set this bit if UNIFY = 1."> + <Enum name="SELECTS_THE_L_STATE" start="0" description="Selects the L state and the L match register selected by MATCHSEL." /> + <Enum name="SELECTS_THE_H_STATE" start="1" description="Selects the H state and the H match register selected by MATCHSEL." /> + </BitField> + <BitField start="5" size="1" name="OUTSEL" description="Input/output select"> + <Enum name="SELECTS_THE_INPUTS_E" start="0" description="Selects the inputs elected by IOSEL." /> + <Enum name="SELECTS_THE_OUTPUTS" start="1" description="Selects the outputs selected by IOSEL." /> + </BitField> + <BitField start="6" size="4" name="IOSEL" description="Selects the input or output signal number (0 to 3) associated with this event (if any). Do not select an input in this register, if CKMODE is 1x. In this case the clock input is an implicit ingredient of every event." /> + <BitField start="10" size="2" name="IOCOND" description="Selects the I/O condition for event n. (The detection of edges on outputs lag the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT clock period ."> + <Enum name="LOW" start="0x0" description="LOW" /> + <Enum name="RISE" start="0x1" description="Rise" /> + <Enum name="FALL" start="0x2" description="Fall" /> + <Enum name="HIGH" start="0x3" description="HIGH" /> + </BitField> + <BitField start="12" size="2" name="COMBMODE" description="Selects how the specified match and I/O condition are used and combined."> + <Enum name="OR" start="0x0" description="OR. The event occurs when either the specified match or I/O condition occurs." /> + <Enum name="MATCH" start="0x1" description="MATCH. Uses the specified match only." /> + <Enum name="IO" start="0x2" description="IO. Uses the specified I/O condition only." /> + <Enum name="AND" start="0x3" description="AND. The event occurs when the specified match and I/O condition occur simultaneously." /> + </BitField> + <BitField start="14" size="1" name="STATELD" description="This bit controls how the STATEV value modifies the state selected by HEVENT when this event is the highest-numbered event occurring for that state."> + <Enum name="STATEV_VALUE_IS_ADDE" start="0" description="STATEV value is added into STATE (the carry-out is ignored)." /> + <Enum name="STATEV_VALUE_IS_LOAD" start="1" description="STATEV value is loaded into STATE." /> + </BitField> + <BitField start="15" size="5" name="STATEV" description="This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state. If STATELD and STATEV are both zero, there is no change to the STATE value." /> + <BitField start="20" size="1" name="MATCHMEM" description="If this bit is one and the COMBMODE field specifies a match component to the triggering of this event, then a match is considered to be active whenever the counter value is GREATER THAN OR EQUAL TO the value specified in the match register when counting up, LESS THEN OR EQUAL TO the match value when counting down. If this bit is zero, a match is only be active during the cycle when the counter is equal to the match value." /> + <BitField start="21" size="2" name="DIRECTION" description="Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved."> + <Enum name="DIRECTION_INDEPENDEN" start="0x0" description="Direction independent. This event is triggered regardless of the count direction." /> + <Enum name="COUNTING_UP" start="0x1" description="Counting up. This event is triggered only during up-counting when BIDIR = 1." /> + <Enum name="COUNTING_DOWN" start="0x2" description="Counting down. This event is triggered only during down-counting when BIDIR = 1." /> + </BitField> + <BitField start="23" size="9" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x304+24" size="4" name="EV3_CTRL" access="Read/Write" description="SCT event control register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="4" name="MATCHSEL" description="Selects the Match register associated with this event (if any). A match can occur only when the counter selected by the HEVENT bit is running." /> + <BitField start="4" size="1" name="HEVENT" description="Select L/H counter. Do not set this bit if UNIFY = 1."> + <Enum name="SELECTS_THE_L_STATE" start="0" description="Selects the L state and the L match register selected by MATCHSEL." /> + <Enum name="SELECTS_THE_H_STATE" start="1" description="Selects the H state and the H match register selected by MATCHSEL." /> + </BitField> + <BitField start="5" size="1" name="OUTSEL" description="Input/output select"> + <Enum name="SELECTS_THE_INPUTS_E" start="0" description="Selects the inputs elected by IOSEL." /> + <Enum name="SELECTS_THE_OUTPUTS" start="1" description="Selects the outputs selected by IOSEL." /> + </BitField> + <BitField start="6" size="4" name="IOSEL" description="Selects the input or output signal number (0 to 3) associated with this event (if any). Do not select an input in this register, if CKMODE is 1x. In this case the clock input is an implicit ingredient of every event." /> + <BitField start="10" size="2" name="IOCOND" description="Selects the I/O condition for event n. (The detection of edges on outputs lag the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT clock period ."> + <Enum name="LOW" start="0x0" description="LOW" /> + <Enum name="RISE" start="0x1" description="Rise" /> + <Enum name="FALL" start="0x2" description="Fall" /> + <Enum name="HIGH" start="0x3" description="HIGH" /> + </BitField> + <BitField start="12" size="2" name="COMBMODE" description="Selects how the specified match and I/O condition are used and combined."> + <Enum name="OR" start="0x0" description="OR. The event occurs when either the specified match or I/O condition occurs." /> + <Enum name="MATCH" start="0x1" description="MATCH. Uses the specified match only." /> + <Enum name="IO" start="0x2" description="IO. Uses the specified I/O condition only." /> + <Enum name="AND" start="0x3" description="AND. The event occurs when the specified match and I/O condition occur simultaneously." /> + </BitField> + <BitField start="14" size="1" name="STATELD" description="This bit controls how the STATEV value modifies the state selected by HEVENT when this event is the highest-numbered event occurring for that state."> + <Enum name="STATEV_VALUE_IS_ADDE" start="0" description="STATEV value is added into STATE (the carry-out is ignored)." /> + <Enum name="STATEV_VALUE_IS_LOAD" start="1" description="STATEV value is loaded into STATE." /> + </BitField> + <BitField start="15" size="5" name="STATEV" description="This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state. If STATELD and STATEV are both zero, there is no change to the STATE value." /> + <BitField start="20" size="1" name="MATCHMEM" description="If this bit is one and the COMBMODE field specifies a match component to the triggering of this event, then a match is considered to be active whenever the counter value is GREATER THAN OR EQUAL TO the value specified in the match register when counting up, LESS THEN OR EQUAL TO the match value when counting down. If this bit is zero, a match is only be active during the cycle when the counter is equal to the match value." /> + <BitField start="21" size="2" name="DIRECTION" description="Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved."> + <Enum name="DIRECTION_INDEPENDEN" start="0x0" description="Direction independent. This event is triggered regardless of the count direction." /> + <Enum name="COUNTING_UP" start="0x1" description="Counting up. This event is triggered only during up-counting when BIDIR = 1." /> + <Enum name="COUNTING_DOWN" start="0x2" description="Counting down. This event is triggered only during down-counting when BIDIR = 1." /> + </BitField> + <BitField start="23" size="9" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x304+32" size="4" name="EV4_CTRL" access="Read/Write" description="SCT event control register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="4" name="MATCHSEL" description="Selects the Match register associated with this event (if any). A match can occur only when the counter selected by the HEVENT bit is running." /> + <BitField start="4" size="1" name="HEVENT" description="Select L/H counter. Do not set this bit if UNIFY = 1."> + <Enum name="SELECTS_THE_L_STATE" start="0" description="Selects the L state and the L match register selected by MATCHSEL." /> + <Enum name="SELECTS_THE_H_STATE" start="1" description="Selects the H state and the H match register selected by MATCHSEL." /> + </BitField> + <BitField start="5" size="1" name="OUTSEL" description="Input/output select"> + <Enum name="SELECTS_THE_INPUTS_E" start="0" description="Selects the inputs elected by IOSEL." /> + <Enum name="SELECTS_THE_OUTPUTS" start="1" description="Selects the outputs selected by IOSEL." /> + </BitField> + <BitField start="6" size="4" name="IOSEL" description="Selects the input or output signal number (0 to 3) associated with this event (if any). Do not select an input in this register, if CKMODE is 1x. In this case the clock input is an implicit ingredient of every event." /> + <BitField start="10" size="2" name="IOCOND" description="Selects the I/O condition for event n. (The detection of edges on outputs lag the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT clock period ."> + <Enum name="LOW" start="0x0" description="LOW" /> + <Enum name="RISE" start="0x1" description="Rise" /> + <Enum name="FALL" start="0x2" description="Fall" /> + <Enum name="HIGH" start="0x3" description="HIGH" /> + </BitField> + <BitField start="12" size="2" name="COMBMODE" description="Selects how the specified match and I/O condition are used and combined."> + <Enum name="OR" start="0x0" description="OR. The event occurs when either the specified match or I/O condition occurs." /> + <Enum name="MATCH" start="0x1" description="MATCH. Uses the specified match only." /> + <Enum name="IO" start="0x2" description="IO. Uses the specified I/O condition only." /> + <Enum name="AND" start="0x3" description="AND. The event occurs when the specified match and I/O condition occur simultaneously." /> + </BitField> + <BitField start="14" size="1" name="STATELD" description="This bit controls how the STATEV value modifies the state selected by HEVENT when this event is the highest-numbered event occurring for that state."> + <Enum name="STATEV_VALUE_IS_ADDE" start="0" description="STATEV value is added into STATE (the carry-out is ignored)." /> + <Enum name="STATEV_VALUE_IS_LOAD" start="1" description="STATEV value is loaded into STATE." /> + </BitField> + <BitField start="15" size="5" name="STATEV" description="This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state. If STATELD and STATEV are both zero, there is no change to the STATE value." /> + <BitField start="20" size="1" name="MATCHMEM" description="If this bit is one and the COMBMODE field specifies a match component to the triggering of this event, then a match is considered to be active whenever the counter value is GREATER THAN OR EQUAL TO the value specified in the match register when counting up, LESS THEN OR EQUAL TO the match value when counting down. If this bit is zero, a match is only be active during the cycle when the counter is equal to the match value." /> + <BitField start="21" size="2" name="DIRECTION" description="Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved."> + <Enum name="DIRECTION_INDEPENDEN" start="0x0" description="Direction independent. This event is triggered regardless of the count direction." /> + <Enum name="COUNTING_UP" start="0x1" description="Counting up. This event is triggered only during up-counting when BIDIR = 1." /> + <Enum name="COUNTING_DOWN" start="0x2" description="Counting down. This event is triggered only during down-counting when BIDIR = 1." /> + </BitField> + <BitField start="23" size="9" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x304+40" size="4" name="EV5_CTRL" access="Read/Write" description="SCT event control register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="4" name="MATCHSEL" description="Selects the Match register associated with this event (if any). A match can occur only when the counter selected by the HEVENT bit is running." /> + <BitField start="4" size="1" name="HEVENT" description="Select L/H counter. Do not set this bit if UNIFY = 1."> + <Enum name="SELECTS_THE_L_STATE" start="0" description="Selects the L state and the L match register selected by MATCHSEL." /> + <Enum name="SELECTS_THE_H_STATE" start="1" description="Selects the H state and the H match register selected by MATCHSEL." /> + </BitField> + <BitField start="5" size="1" name="OUTSEL" description="Input/output select"> + <Enum name="SELECTS_THE_INPUTS_E" start="0" description="Selects the inputs elected by IOSEL." /> + <Enum name="SELECTS_THE_OUTPUTS" start="1" description="Selects the outputs selected by IOSEL." /> + </BitField> + <BitField start="6" size="4" name="IOSEL" description="Selects the input or output signal number (0 to 3) associated with this event (if any). Do not select an input in this register, if CKMODE is 1x. In this case the clock input is an implicit ingredient of every event." /> + <BitField start="10" size="2" name="IOCOND" description="Selects the I/O condition for event n. (The detection of edges on outputs lag the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT clock period ."> + <Enum name="LOW" start="0x0" description="LOW" /> + <Enum name="RISE" start="0x1" description="Rise" /> + <Enum name="FALL" start="0x2" description="Fall" /> + <Enum name="HIGH" start="0x3" description="HIGH" /> + </BitField> + <BitField start="12" size="2" name="COMBMODE" description="Selects how the specified match and I/O condition are used and combined."> + <Enum name="OR" start="0x0" description="OR. The event occurs when either the specified match or I/O condition occurs." /> + <Enum name="MATCH" start="0x1" description="MATCH. Uses the specified match only." /> + <Enum name="IO" start="0x2" description="IO. Uses the specified I/O condition only." /> + <Enum name="AND" start="0x3" description="AND. The event occurs when the specified match and I/O condition occur simultaneously." /> + </BitField> + <BitField start="14" size="1" name="STATELD" description="This bit controls how the STATEV value modifies the state selected by HEVENT when this event is the highest-numbered event occurring for that state."> + <Enum name="STATEV_VALUE_IS_ADDE" start="0" description="STATEV value is added into STATE (the carry-out is ignored)." /> + <Enum name="STATEV_VALUE_IS_LOAD" start="1" description="STATEV value is loaded into STATE." /> + </BitField> + <BitField start="15" size="5" name="STATEV" description="This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state. If STATELD and STATEV are both zero, there is no change to the STATE value." /> + <BitField start="20" size="1" name="MATCHMEM" description="If this bit is one and the COMBMODE field specifies a match component to the triggering of this event, then a match is considered to be active whenever the counter value is GREATER THAN OR EQUAL TO the value specified in the match register when counting up, LESS THEN OR EQUAL TO the match value when counting down. If this bit is zero, a match is only be active during the cycle when the counter is equal to the match value." /> + <BitField start="21" size="2" name="DIRECTION" description="Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved."> + <Enum name="DIRECTION_INDEPENDEN" start="0x0" description="Direction independent. This event is triggered regardless of the count direction." /> + <Enum name="COUNTING_UP" start="0x1" description="Counting up. This event is triggered only during up-counting when BIDIR = 1." /> + <Enum name="COUNTING_DOWN" start="0x2" description="Counting down. This event is triggered only during down-counting when BIDIR = 1." /> + </BitField> + <BitField start="23" size="9" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x500+0" size="4" name="OUT0_SET" access="Read/Write" description="SCT output 0 set register" reset_value="0x00000000" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="6" name="SET" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 5 = bit 5." /> + <BitField start="6" size="26" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x500+8" size="4" name="OUT1_SET" access="Read/Write" description="SCT output 0 set register" reset_value="0x00000000" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="6" name="SET" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 5 = bit 5." /> + <BitField start="6" size="26" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x500+16" size="4" name="OUT2_SET" access="Read/Write" description="SCT output 0 set register" reset_value="0x00000000" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="6" name="SET" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 5 = bit 5." /> + <BitField start="6" size="26" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x500+24" size="4" name="OUT3_SET" access="Read/Write" description="SCT output 0 set register" reset_value="0x00000000" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="6" name="SET" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 5 = bit 5." /> + <BitField start="6" size="26" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x504+0" size="4" name="OUT0_CLR" access="Read/Write" description="SCT output 0 clear register" reset_value="0x00000000" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="6" name="CLR" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 5 = bit 5." /> + <BitField start="6" size="26" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x504+8" size="4" name="OUT1_CLR" access="Read/Write" description="SCT output 0 clear register" reset_value="0x00000000" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="6" name="CLR" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 5 = bit 5." /> + <BitField start="6" size="26" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x504+16" size="4" name="OUT2_CLR" access="Read/Write" description="SCT output 0 clear register" reset_value="0x00000000" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="6" name="CLR" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 5 = bit 5." /> + <BitField start="6" size="26" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x504+24" size="4" name="OUT3_CLR" access="Read/Write" description="SCT output 0 clear register" reset_value="0x00000000" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="6" name="CLR" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 5 = bit 5." /> + <BitField start="6" size="26" name="RESERVED" description="Reserved" /> + </Register> + </RegisterGroup> + <RegisterGroup name="GPIO_PORT" start="0xA0000000" description="General Purpose I/O (GPIO) "> + <Register start="+0x0000+0" size="1" name="B[0]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." /> + </Register> + <Register start="+0x0000+1" size="1" name="B[1]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." /> + </Register> + <Register start="+0x0000+2" size="1" name="B[2]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." /> + </Register> + <Register start="+0x0000+3" size="1" name="B[3]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." /> + </Register> + <Register start="+0x0000+4" size="1" name="B[4]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." /> + </Register> + <Register start="+0x0000+5" size="1" name="B[5]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." /> + </Register> + <Register start="+0x0000+6" size="1" name="B[6]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." /> + </Register> + <Register start="+0x0000+7" size="1" name="B[7]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." /> + </Register> + <Register start="+0x0000+8" size="1" name="B[8]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." /> + </Register> + <Register start="+0x0000+9" size="1" name="B[9]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." /> + </Register> + <Register start="+0x0000+10" size="1" name="B[10]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." /> + </Register> + <Register start="+0x0000+11" size="1" name="B[11]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." /> + </Register> + <Register start="+0x0000+12" size="1" name="B[12]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." /> + </Register> + <Register start="+0x0000+13" size="1" name="B[13]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." /> + </Register> + <Register start="+0x0000+14" size="1" name="B[14]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." /> + </Register> + <Register start="+0x0000+15" size="1" name="B[15]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." /> + </Register> + <Register start="+0x0000+16" size="1" name="B[16]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." /> + </Register> + <Register start="+0x0000+17" size="1" name="B[17]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." /> + </Register> + <Register start="+0x0000+18" size="1" name="B[18]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." /> + </Register> + <Register start="+0x0000+19" size="1" name="B[19]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." /> + </Register> + <Register start="+0x0000+20" size="1" name="B[20]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." /> + </Register> + <Register start="+0x0000+21" size="1" name="B[21]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." /> + </Register> + <Register start="+0x0000+22" size="1" name="B[22]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." /> + </Register> + <Register start="+0x0000+23" size="1" name="B[23]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." /> + </Register> + <Register start="+0x0000+24" size="1" name="B[24]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." /> + </Register> + <Register start="+0x0000+25" size="1" name="B[25]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." /> + </Register> + <Register start="+0x0000+26" size="1" name="B[26]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." /> + </Register> + <Register start="+0x0000+27" size="1" name="B[27]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." /> + </Register> + <Register start="+0x0000+28" size="1" name="B[28]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." /> + </Register> + <Register start="+0x0000+29" size="1" name="B[29]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." /> + </Register> + <Register start="+0x0000+30" size="1" name="B[30]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." /> + </Register> + <Register start="+0x0000+31" size="1" name="B[31]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." /> + </Register> + <Register start="+0x0000+32" size="1" name="B[32]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." /> + </Register> + <Register start="+0x0000+33" size="1" name="B[33]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." /> + </Register> + <Register start="+0x0000+34" size="1" name="B[34]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." /> + </Register> + <Register start="+0x0000+35" size="1" name="B[35]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." /> + </Register> + <Register start="+0x0000+36" size="1" name="B[36]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." /> + </Register> + <Register start="+0x0000+37" size="1" name="B[37]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." /> + </Register> + <Register start="+0x0000+38" size="1" name="B[38]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." /> + </Register> + <Register start="+0x0000+39" size="1" name="B[39]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." /> + </Register> + <Register start="+0x0000+40" size="1" name="B[40]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." /> + </Register> + <Register start="+0x0000+41" size="1" name="B[41]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." /> + </Register> + <Register start="+0x0000+42" size="1" name="B[42]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." /> + </Register> + <Register start="+0x0000+43" size="1" name="B[43]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." /> + </Register> + <Register start="+0x0000+44" size="1" name="B[44]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." /> + </Register> + <Register start="+0x0000+45" size="1" name="B[45]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." /> + </Register> + <Register start="+0x0000+46" size="1" name="B[46]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." /> + </Register> + <Register start="+0x0000+47" size="1" name="B[47]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." /> + </Register> + <Register start="+0x0000+48" size="1" name="B[48]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." /> + </Register> + <Register start="+0x0000+49" size="1" name="B[49]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." /> + </Register> + <Register start="+0x0000+50" size="1" name="B[50]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." /> + </Register> + <Register start="+0x0000+51" size="1" name="B[51]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." /> + </Register> + <Register start="+0x0000+52" size="1" name="B[52]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." /> + </Register> + <Register start="+0x0000+53" size="1" name="B[53]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." /> + </Register> + <Register start="+0x0000+54" size="1" name="B[54]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." /> + </Register> + <Register start="+0x0000+55" size="1" name="B[55]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." /> + </Register> + <Register start="+0x0000+56" size="1" name="B[56]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." /> + </Register> + <Register start="+0x0000+57" size="1" name="B[57]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." /> + </Register> + <Register start="+0x0000+58" size="1" name="B[58]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." /> + </Register> + <Register start="+0x0000+59" size="1" name="B[59]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." /> + </Register> + <Register start="+0x0000+60" size="1" name="B[60]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." /> + </Register> + <Register start="+0x0000+61" size="1" name="B[61]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." /> + </Register> + <Register start="+0x0000+62" size="1" name="B[62]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." /> + </Register> + <Register start="+0x0000+63" size="1" name="B[63]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." /> + </Register> + <Register start="+0x0000+64" size="1" name="B[64]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." /> + </Register> + <Register start="+0x0000+65" size="1" name="B[65]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." /> + </Register> + <Register start="+0x0000+66" size="1" name="B[66]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." /> + </Register> + <Register start="+0x0000+67" size="1" name="B[67]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." /> + </Register> + <Register start="+0x0000+68" size="1" name="B[68]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." /> + </Register> + <Register start="+0x0000+69" size="1" name="B[69]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." /> + </Register> + <Register start="+0x0000+70" size="1" name="B[70]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." /> + </Register> + <Register start="+0x0000+71" size="1" name="B[71]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." /> + </Register> + <Register start="+0x0000+72" size="1" name="B[72]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." /> + </Register> + <Register start="+0x0000+73" size="1" name="B[73]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." /> + </Register> + <Register start="+0x0000+74" size="1" name="B[74]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." /> + </Register> + <Register start="+0x0000+75" size="1" name="B[75]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." /> + </Register> + <Register start="+0x0000+76" size="1" name="B[76]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." /> + </Register> + <Register start="+0x0000+77" size="1" name="B[77]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." /> + </Register> + <Register start="+0x0000+78" size="1" name="B[78]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." /> + </Register> + <Register start="+0x0000+79" size="1" name="B[79]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." /> + </Register> + <Register start="+0x0000+80" size="1" name="B[80]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." /> + </Register> + <Register start="+0x0000+81" size="1" name="B[81]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." /> + </Register> + <Register start="+0x0000+82" size="1" name="B[82]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." /> + </Register> + <Register start="+0x0000+83" size="1" name="B[83]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." /> + </Register> + <Register start="+0x0000+84" size="1" name="B[84]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." /> + </Register> + <Register start="+0x0000+85" size="1" name="B[85]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." /> + </Register> + <Register start="+0x0000+86" size="1" name="B[86]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." /> + </Register> + <Register start="+0x0000+87" size="1" name="B[87]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." /> + </Register> + <Register start="+0x1000+0" size="4" name="W[0]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." /> + </Register> + <Register start="+0x1000+4" size="4" name="W[1]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." /> + </Register> + <Register start="+0x1000+8" size="4" name="W[2]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." /> + </Register> + <Register start="+0x1000+12" size="4" name="W[3]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." /> + </Register> + <Register start="+0x1000+16" size="4" name="W[4]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." /> + </Register> + <Register start="+0x1000+20" size="4" name="W[5]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." /> + </Register> + <Register start="+0x1000+24" size="4" name="W[6]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." /> + </Register> + <Register start="+0x1000+28" size="4" name="W[7]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." /> + </Register> + <Register start="+0x1000+32" size="4" name="W[8]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." /> + </Register> + <Register start="+0x1000+36" size="4" name="W[9]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." /> + </Register> + <Register start="+0x1000+40" size="4" name="W[10]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." /> + </Register> + <Register start="+0x1000+44" size="4" name="W[11]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." /> + </Register> + <Register start="+0x1000+48" size="4" name="W[12]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." /> + </Register> + <Register start="+0x1000+52" size="4" name="W[13]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." /> + </Register> + <Register start="+0x1000+56" size="4" name="W[14]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." /> + </Register> + <Register start="+0x1000+60" size="4" name="W[15]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." /> + </Register> + <Register start="+0x1000+64" size="4" name="W[16]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." /> + </Register> + <Register start="+0x1000+68" size="4" name="W[17]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." /> + </Register> + <Register start="+0x1000+72" size="4" name="W[18]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." /> + </Register> + <Register start="+0x1000+76" size="4" name="W[19]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." /> + </Register> + <Register start="+0x1000+80" size="4" name="W[20]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." /> + </Register> + <Register start="+0x1000+84" size="4" name="W[21]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." /> + </Register> + <Register start="+0x1000+88" size="4" name="W[22]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." /> + </Register> + <Register start="+0x1000+92" size="4" name="W[23]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." /> + </Register> + <Register start="+0x1000+96" size="4" name="W[24]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." /> + </Register> + <Register start="+0x1000+100" size="4" name="W[25]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." /> + </Register> + <Register start="+0x1000+104" size="4" name="W[26]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." /> + </Register> + <Register start="+0x1000+108" size="4" name="W[27]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." /> + </Register> + <Register start="+0x1000+112" size="4" name="W[28]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." /> + </Register> + <Register start="+0x1000+116" size="4" name="W[29]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." /> + </Register> + <Register start="+0x1000+120" size="4" name="W[30]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." /> + </Register> + <Register start="+0x1000+124" size="4" name="W[31]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." /> + </Register> + <Register start="+0x1000+128" size="4" name="W[32]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." /> + </Register> + <Register start="+0x1000+132" size="4" name="W[33]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." /> + </Register> + <Register start="+0x1000+136" size="4" name="W[34]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." /> + </Register> + <Register start="+0x1000+140" size="4" name="W[35]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." /> + </Register> + <Register start="+0x1000+144" size="4" name="W[36]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." /> + </Register> + <Register start="+0x1000+148" size="4" name="W[37]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." /> + </Register> + <Register start="+0x1000+152" size="4" name="W[38]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." /> + </Register> + <Register start="+0x1000+156" size="4" name="W[39]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." /> + </Register> + <Register start="+0x1000+160" size="4" name="W[40]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." /> + </Register> + <Register start="+0x1000+164" size="4" name="W[41]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." /> + </Register> + <Register start="+0x1000+168" size="4" name="W[42]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." /> + </Register> + <Register start="+0x1000+172" size="4" name="W[43]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." /> + </Register> + <Register start="+0x1000+176" size="4" name="W[44]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." /> + </Register> + <Register start="+0x1000+180" size="4" name="W[45]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." /> + </Register> + <Register start="+0x1000+184" size="4" name="W[46]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." /> + </Register> + <Register start="+0x1000+188" size="4" name="W[47]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." /> + </Register> + <Register start="+0x1000+192" size="4" name="W[48]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." /> + </Register> + <Register start="+0x1000+196" size="4" name="W[49]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." /> + </Register> + <Register start="+0x1000+200" size="4" name="W[50]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." /> + </Register> + <Register start="+0x1000+204" size="4" name="W[51]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." /> + </Register> + <Register start="+0x1000+208" size="4" name="W[52]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." /> + </Register> + <Register start="+0x1000+212" size="4" name="W[53]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." /> + </Register> + <Register start="+0x1000+216" size="4" name="W[54]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." /> + </Register> + <Register start="+0x1000+220" size="4" name="W[55]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." /> + </Register> + <Register start="+0x1000+224" size="4" name="W[56]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." /> + </Register> + <Register start="+0x1000+228" size="4" name="W[57]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." /> + </Register> + <Register start="+0x1000+232" size="4" name="W[58]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." /> + </Register> + <Register start="+0x1000+236" size="4" name="W[59]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." /> + </Register> + <Register start="+0x1000+240" size="4" name="W[60]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." /> + </Register> + <Register start="+0x1000+244" size="4" name="W[61]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." /> + </Register> + <Register start="+0x1000+248" size="4" name="W[62]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." /> + </Register> + <Register start="+0x1000+252" size="4" name="W[63]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." /> + </Register> + <Register start="+0x1000+256" size="4" name="W[64]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." /> + </Register> + <Register start="+0x1000+260" size="4" name="W[65]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." /> + </Register> + <Register start="+0x1000+264" size="4" name="W[66]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." /> + </Register> + <Register start="+0x1000+268" size="4" name="W[67]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." /> + </Register> + <Register start="+0x1000+272" size="4" name="W[68]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." /> + </Register> + <Register start="+0x1000+276" size="4" name="W[69]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." /> + </Register> + <Register start="+0x1000+280" size="4" name="W[70]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." /> + </Register> + <Register start="+0x1000+284" size="4" name="W[71]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." /> + </Register> + <Register start="+0x1000+288" size="4" name="W[72]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." /> + </Register> + <Register start="+0x1000+292" size="4" name="W[73]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." /> + </Register> + <Register start="+0x1000+296" size="4" name="W[74]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." /> + </Register> + <Register start="+0x1000+300" size="4" name="W[75]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." /> + </Register> + <Register start="+0x1000+304" size="4" name="W[76]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." /> + </Register> + <Register start="+0x1000+308" size="4" name="W[77]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." /> + </Register> + <Register start="+0x1000+312" size="4" name="W[78]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." /> + </Register> + <Register start="+0x1000+316" size="4" name="W[79]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." /> + </Register> + <Register start="+0x1000+320" size="4" name="W[80]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." /> + </Register> + <Register start="+0x1000+324" size="4" name="W[81]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." /> + </Register> + <Register start="+0x1000+328" size="4" name="W[82]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." /> + </Register> + <Register start="+0x1000+332" size="4" name="W[83]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." /> + </Register> + <Register start="+0x1000+336" size="4" name="W[84]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." /> + </Register> + <Register start="+0x1000+340" size="4" name="W[85]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." /> + </Register> + <Register start="+0x1000+344" size="4" name="W[86]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." /> + </Register> + <Register start="+0x1000+348" size="4" name="W[87]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." /> + </Register> + <Register start="+0x2000+0" size="4" name="DIR[0]" access="Read/Write" description="Port Direction registers " reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="DIRP0" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." /> + <BitField start="1" size="1" name="DIRP1" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." /> + <BitField start="2" size="1" name="DIRP2" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." /> + <BitField start="3" size="1" name="DIRP3" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." /> + <BitField start="4" size="1" name="DIRP4" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." /> + <BitField start="5" size="1" name="DIRP5" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." /> + <BitField start="6" size="1" name="DIRP6" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." /> + <BitField start="7" size="1" name="DIRP7" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." /> + <BitField start="8" size="1" name="DIRP8" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." /> + <BitField start="9" size="1" name="DIRP9" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." /> + <BitField start="10" size="1" name="DIRP10" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." /> + <BitField start="11" size="1" name="DIRP11" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." /> + <BitField start="12" size="1" name="DIRP12" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." /> + <BitField start="13" size="1" name="DIRP13" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." /> + <BitField start="14" size="1" name="DIRP14" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." /> + <BitField start="15" size="1" name="DIRP15" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." /> + <BitField start="16" size="1" name="DIRP16" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." /> + <BitField start="17" size="1" name="DIRP17" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." /> + <BitField start="18" size="1" name="DIRP18" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." /> + <BitField start="19" size="1" name="DIRP19" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." /> + <BitField start="20" size="1" name="DIRP20" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." /> + <BitField start="21" size="1" name="DIRP21" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." /> + <BitField start="22" size="1" name="DIRP22" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." /> + <BitField start="23" size="1" name="DIRP23" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." /> + <BitField start="24" size="1" name="DIRP24" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." /> + <BitField start="25" size="1" name="DIRP25" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." /> + <BitField start="26" size="1" name="DIRP26" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." /> + <BitField start="27" size="1" name="DIRP27" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." /> + <BitField start="28" size="1" name="DIRP28" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." /> + <BitField start="29" size="1" name="DIRP29" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." /> + <BitField start="30" size="1" name="DIRP30" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." /> + <BitField start="31" size="1" name="DIRP31" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." /> + </Register> + <Register start="+0x2000+4" size="4" name="DIR[1]" access="Read/Write" description="Port Direction registers " reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="DIRP0" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." /> + <BitField start="1" size="1" name="DIRP1" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." /> + <BitField start="2" size="1" name="DIRP2" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." /> + <BitField start="3" size="1" name="DIRP3" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." /> + <BitField start="4" size="1" name="DIRP4" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." /> + <BitField start="5" size="1" name="DIRP5" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." /> + <BitField start="6" size="1" name="DIRP6" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." /> + <BitField start="7" size="1" name="DIRP7" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." /> + <BitField start="8" size="1" name="DIRP8" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." /> + <BitField start="9" size="1" name="DIRP9" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." /> + <BitField start="10" size="1" name="DIRP10" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." /> + <BitField start="11" size="1" name="DIRP11" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." /> + <BitField start="12" size="1" name="DIRP12" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." /> + <BitField start="13" size="1" name="DIRP13" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." /> + <BitField start="14" size="1" name="DIRP14" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." /> + <BitField start="15" size="1" name="DIRP15" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." /> + <BitField start="16" size="1" name="DIRP16" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." /> + <BitField start="17" size="1" name="DIRP17" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." /> + <BitField start="18" size="1" name="DIRP18" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." /> + <BitField start="19" size="1" name="DIRP19" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." /> + <BitField start="20" size="1" name="DIRP20" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." /> + <BitField start="21" size="1" name="DIRP21" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." /> + <BitField start="22" size="1" name="DIRP22" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." /> + <BitField start="23" size="1" name="DIRP23" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." /> + <BitField start="24" size="1" name="DIRP24" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." /> + <BitField start="25" size="1" name="DIRP25" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." /> + <BitField start="26" size="1" name="DIRP26" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." /> + <BitField start="27" size="1" name="DIRP27" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." /> + <BitField start="28" size="1" name="DIRP28" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." /> + <BitField start="29" size="1" name="DIRP29" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." /> + <BitField start="30" size="1" name="DIRP30" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." /> + <BitField start="31" size="1" name="DIRP31" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." /> + </Register> + <Register start="+0x2000+8" size="4" name="DIR[2]" access="Read/Write" description="Port Direction registers " reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="DIRP0" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." /> + <BitField start="1" size="1" name="DIRP1" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." /> + <BitField start="2" size="1" name="DIRP2" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." /> + <BitField start="3" size="1" name="DIRP3" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." /> + <BitField start="4" size="1" name="DIRP4" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." /> + <BitField start="5" size="1" name="DIRP5" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." /> + <BitField start="6" size="1" name="DIRP6" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." /> + <BitField start="7" size="1" name="DIRP7" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." /> + <BitField start="8" size="1" name="DIRP8" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." /> + <BitField start="9" size="1" name="DIRP9" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." /> + <BitField start="10" size="1" name="DIRP10" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." /> + <BitField start="11" size="1" name="DIRP11" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." /> + <BitField start="12" size="1" name="DIRP12" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." /> + <BitField start="13" size="1" name="DIRP13" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." /> + <BitField start="14" size="1" name="DIRP14" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." /> + <BitField start="15" size="1" name="DIRP15" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." /> + <BitField start="16" size="1" name="DIRP16" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." /> + <BitField start="17" size="1" name="DIRP17" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." /> + <BitField start="18" size="1" name="DIRP18" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." /> + <BitField start="19" size="1" name="DIRP19" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." /> + <BitField start="20" size="1" name="DIRP20" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." /> + <BitField start="21" size="1" name="DIRP21" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." /> + <BitField start="22" size="1" name="DIRP22" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." /> + <BitField start="23" size="1" name="DIRP23" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." /> + <BitField start="24" size="1" name="DIRP24" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." /> + <BitField start="25" size="1" name="DIRP25" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." /> + <BitField start="26" size="1" name="DIRP26" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." /> + <BitField start="27" size="1" name="DIRP27" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." /> + <BitField start="28" size="1" name="DIRP28" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." /> + <BitField start="29" size="1" name="DIRP29" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." /> + <BitField start="30" size="1" name="DIRP30" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." /> + <BitField start="31" size="1" name="DIRP31" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." /> + </Register> + <Register start="+0x2080+0" size="4" name="MASK[0]" access="Read/Write" description="Port Mask register " reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="MASKP0" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." /> + <BitField start="1" size="1" name="MASKP1" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." /> + <BitField start="2" size="1" name="MASKP2" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." /> + <BitField start="3" size="1" name="MASKP3" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." /> + <BitField start="4" size="1" name="MASKP4" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." /> + <BitField start="5" size="1" name="MASKP5" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." /> + <BitField start="6" size="1" name="MASKP6" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." /> + <BitField start="7" size="1" name="MASKP7" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." /> + <BitField start="8" size="1" name="MASKP8" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." /> + <BitField start="9" size="1" name="MASKP9" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." /> + <BitField start="10" size="1" name="MASKP10" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." /> + <BitField start="11" size="1" name="MASKP11" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." /> + <BitField start="12" size="1" name="MASKP12" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." /> + <BitField start="13" size="1" name="MASKP13" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." /> + <BitField start="14" size="1" name="MASKP14" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." /> + <BitField start="15" size="1" name="MASKP15" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." /> + <BitField start="16" size="1" name="MASKP16" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." /> + <BitField start="17" size="1" name="MASKP17" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." /> + <BitField start="18" size="1" name="MASKP18" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." /> + <BitField start="19" size="1" name="MASKP19" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." /> + <BitField start="20" size="1" name="MASKP20" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." /> + <BitField start="21" size="1" name="MASKP21" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." /> + <BitField start="22" size="1" name="MASKP22" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." /> + <BitField start="23" size="1" name="MASKP23" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." /> + <BitField start="24" size="1" name="MASKP24" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." /> + <BitField start="25" size="1" name="MASKP25" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." /> + <BitField start="26" size="1" name="MASKP26" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." /> + <BitField start="27" size="1" name="MASKP27" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." /> + <BitField start="28" size="1" name="MASKP28" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." /> + <BitField start="29" size="1" name="MASKP29" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." /> + <BitField start="30" size="1" name="MASKP30" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." /> + <BitField start="31" size="1" name="MASKP31" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." /> + </Register> + <Register start="+0x2080+4" size="4" name="MASK[1]" access="Read/Write" description="Port Mask register " reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="MASKP0" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." /> + <BitField start="1" size="1" name="MASKP1" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." /> + <BitField start="2" size="1" name="MASKP2" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." /> + <BitField start="3" size="1" name="MASKP3" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." /> + <BitField start="4" size="1" name="MASKP4" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." /> + <BitField start="5" size="1" name="MASKP5" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." /> + <BitField start="6" size="1" name="MASKP6" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." /> + <BitField start="7" size="1" name="MASKP7" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." /> + <BitField start="8" size="1" name="MASKP8" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." /> + <BitField start="9" size="1" name="MASKP9" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." /> + <BitField start="10" size="1" name="MASKP10" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." /> + <BitField start="11" size="1" name="MASKP11" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." /> + <BitField start="12" size="1" name="MASKP12" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." /> + <BitField start="13" size="1" name="MASKP13" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." /> + <BitField start="14" size="1" name="MASKP14" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." /> + <BitField start="15" size="1" name="MASKP15" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." /> + <BitField start="16" size="1" name="MASKP16" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." /> + <BitField start="17" size="1" name="MASKP17" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." /> + <BitField start="18" size="1" name="MASKP18" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." /> + <BitField start="19" size="1" name="MASKP19" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." /> + <BitField start="20" size="1" name="MASKP20" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." /> + <BitField start="21" size="1" name="MASKP21" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." /> + <BitField start="22" size="1" name="MASKP22" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." /> + <BitField start="23" size="1" name="MASKP23" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." /> + <BitField start="24" size="1" name="MASKP24" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." /> + <BitField start="25" size="1" name="MASKP25" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." /> + <BitField start="26" size="1" name="MASKP26" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." /> + <BitField start="27" size="1" name="MASKP27" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." /> + <BitField start="28" size="1" name="MASKP28" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." /> + <BitField start="29" size="1" name="MASKP29" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." /> + <BitField start="30" size="1" name="MASKP30" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." /> + <BitField start="31" size="1" name="MASKP31" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." /> + </Register> + <Register start="+0x2080+8" size="4" name="MASK[2]" access="Read/Write" description="Port Mask register " reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="MASKP0" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." /> + <BitField start="1" size="1" name="MASKP1" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." /> + <BitField start="2" size="1" name="MASKP2" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." /> + <BitField start="3" size="1" name="MASKP3" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." /> + <BitField start="4" size="1" name="MASKP4" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." /> + <BitField start="5" size="1" name="MASKP5" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." /> + <BitField start="6" size="1" name="MASKP6" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." /> + <BitField start="7" size="1" name="MASKP7" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." /> + <BitField start="8" size="1" name="MASKP8" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." /> + <BitField start="9" size="1" name="MASKP9" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." /> + <BitField start="10" size="1" name="MASKP10" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." /> + <BitField start="11" size="1" name="MASKP11" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." /> + <BitField start="12" size="1" name="MASKP12" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." /> + <BitField start="13" size="1" name="MASKP13" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." /> + <BitField start="14" size="1" name="MASKP14" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." /> + <BitField start="15" size="1" name="MASKP15" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." /> + <BitField start="16" size="1" name="MASKP16" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." /> + <BitField start="17" size="1" name="MASKP17" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." /> + <BitField start="18" size="1" name="MASKP18" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." /> + <BitField start="19" size="1" name="MASKP19" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." /> + <BitField start="20" size="1" name="MASKP20" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." /> + <BitField start="21" size="1" name="MASKP21" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." /> + <BitField start="22" size="1" name="MASKP22" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." /> + <BitField start="23" size="1" name="MASKP23" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." /> + <BitField start="24" size="1" name="MASKP24" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." /> + <BitField start="25" size="1" name="MASKP25" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." /> + <BitField start="26" size="1" name="MASKP26" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." /> + <BitField start="27" size="1" name="MASKP27" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." /> + <BitField start="28" size="1" name="MASKP28" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." /> + <BitField start="29" size="1" name="MASKP29" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." /> + <BitField start="30" size="1" name="MASKP30" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." /> + <BitField start="31" size="1" name="MASKP31" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." /> + </Register> + <Register start="+0x2100+0" size="4" name="PIN[0]" access="Read/Write" description="Port pin register " reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="PORT0" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." /> + <BitField start="1" size="1" name="PORT1" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." /> + <BitField start="2" size="1" name="PORT2" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." /> + <BitField start="3" size="1" name="PORT3" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." /> + <BitField start="4" size="1" name="PORT4" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." /> + <BitField start="5" size="1" name="PORT5" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." /> + <BitField start="6" size="1" name="PORT6" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." /> + <BitField start="7" size="1" name="PORT7" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." /> + <BitField start="8" size="1" name="PORT8" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." /> + <BitField start="9" size="1" name="PORT9" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." /> + <BitField start="10" size="1" name="PORT10" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." /> + <BitField start="11" size="1" name="PORT11" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." /> + <BitField start="12" size="1" name="PORT12" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." /> + <BitField start="13" size="1" name="PORT13" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." /> + <BitField start="14" size="1" name="PORT14" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." /> + <BitField start="15" size="1" name="PORT15" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." /> + <BitField start="16" size="1" name="PORT16" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." /> + <BitField start="17" size="1" name="PORT17" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." /> + <BitField start="18" size="1" name="PORT18" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." /> + <BitField start="19" size="1" name="PORT19" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." /> + <BitField start="20" size="1" name="PORT20" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." /> + <BitField start="21" size="1" name="PORT21" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." /> + <BitField start="22" size="1" name="PORT22" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." /> + <BitField start="23" size="1" name="PORT23" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." /> + <BitField start="24" size="1" name="PORT24" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." /> + <BitField start="25" size="1" name="PORT25" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." /> + <BitField start="26" size="1" name="PORT26" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." /> + <BitField start="27" size="1" name="PORT27" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." /> + <BitField start="28" size="1" name="PORT28" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." /> + <BitField start="29" size="1" name="PORT29" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." /> + <BitField start="30" size="1" name="PORT30" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." /> + <BitField start="31" size="1" name="PORT31" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." /> + </Register> + <Register start="+0x2100+4" size="4" name="PIN[1]" access="Read/Write" description="Port pin register " reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="PORT0" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." /> + <BitField start="1" size="1" name="PORT1" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." /> + <BitField start="2" size="1" name="PORT2" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." /> + <BitField start="3" size="1" name="PORT3" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." /> + <BitField start="4" size="1" name="PORT4" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." /> + <BitField start="5" size="1" name="PORT5" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." /> + <BitField start="6" size="1" name="PORT6" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." /> + <BitField start="7" size="1" name="PORT7" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." /> + <BitField start="8" size="1" name="PORT8" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." /> + <BitField start="9" size="1" name="PORT9" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." /> + <BitField start="10" size="1" name="PORT10" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." /> + <BitField start="11" size="1" name="PORT11" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." /> + <BitField start="12" size="1" name="PORT12" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." /> + <BitField start="13" size="1" name="PORT13" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." /> + <BitField start="14" size="1" name="PORT14" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." /> + <BitField start="15" size="1" name="PORT15" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." /> + <BitField start="16" size="1" name="PORT16" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." /> + <BitField start="17" size="1" name="PORT17" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." /> + <BitField start="18" size="1" name="PORT18" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." /> + <BitField start="19" size="1" name="PORT19" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." /> + <BitField start="20" size="1" name="PORT20" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." /> + <BitField start="21" size="1" name="PORT21" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." /> + <BitField start="22" size="1" name="PORT22" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." /> + <BitField start="23" size="1" name="PORT23" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." /> + <BitField start="24" size="1" name="PORT24" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." /> + <BitField start="25" size="1" name="PORT25" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." /> + <BitField start="26" size="1" name="PORT26" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." /> + <BitField start="27" size="1" name="PORT27" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." /> + <BitField start="28" size="1" name="PORT28" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." /> + <BitField start="29" size="1" name="PORT29" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." /> + <BitField start="30" size="1" name="PORT30" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." /> + <BitField start="31" size="1" name="PORT31" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." /> + </Register> + <Register start="+0x2100+8" size="4" name="PIN[2]" access="Read/Write" description="Port pin register " reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="PORT0" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." /> + <BitField start="1" size="1" name="PORT1" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." /> + <BitField start="2" size="1" name="PORT2" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." /> + <BitField start="3" size="1" name="PORT3" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." /> + <BitField start="4" size="1" name="PORT4" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." /> + <BitField start="5" size="1" name="PORT5" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." /> + <BitField start="6" size="1" name="PORT6" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." /> + <BitField start="7" size="1" name="PORT7" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." /> + <BitField start="8" size="1" name="PORT8" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." /> + <BitField start="9" size="1" name="PORT9" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." /> + <BitField start="10" size="1" name="PORT10" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." /> + <BitField start="11" size="1" name="PORT11" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." /> + <BitField start="12" size="1" name="PORT12" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." /> + <BitField start="13" size="1" name="PORT13" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." /> + <BitField start="14" size="1" name="PORT14" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." /> + <BitField start="15" size="1" name="PORT15" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." /> + <BitField start="16" size="1" name="PORT16" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." /> + <BitField start="17" size="1" name="PORT17" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." /> + <BitField start="18" size="1" name="PORT18" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." /> + <BitField start="19" size="1" name="PORT19" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." /> + <BitField start="20" size="1" name="PORT20" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." /> + <BitField start="21" size="1" name="PORT21" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." /> + <BitField start="22" size="1" name="PORT22" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." /> + <BitField start="23" size="1" name="PORT23" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." /> + <BitField start="24" size="1" name="PORT24" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." /> + <BitField start="25" size="1" name="PORT25" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." /> + <BitField start="26" size="1" name="PORT26" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." /> + <BitField start="27" size="1" name="PORT27" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." /> + <BitField start="28" size="1" name="PORT28" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." /> + <BitField start="29" size="1" name="PORT29" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." /> + <BitField start="30" size="1" name="PORT30" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." /> + <BitField start="31" size="1" name="PORT31" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." /> + </Register> + <Register start="+0x2180+0" size="4" name="MPIN[0]" access="Read/Write" description="Masked port register " reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="MPORTP0" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." /> + <BitField start="1" size="1" name="MPORTP1" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." /> + <BitField start="2" size="1" name="MPORTP2" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." /> + <BitField start="3" size="1" name="MPORTP3" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." /> + <BitField start="4" size="1" name="MPORTP4" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." /> + <BitField start="5" size="1" name="MPORTP5" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." /> + <BitField start="6" size="1" name="MPORTP6" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." /> + <BitField start="7" size="1" name="MPORTP7" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." /> + <BitField start="8" size="1" name="MPORTP8" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." /> + <BitField start="9" size="1" name="MPORTP9" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." /> + <BitField start="10" size="1" name="MPORTP10" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." /> + <BitField start="11" size="1" name="MPORTP11" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." /> + <BitField start="12" size="1" name="MPORTP12" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." /> + <BitField start="13" size="1" name="MPORTP13" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." /> + <BitField start="14" size="1" name="MPORTP14" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." /> + <BitField start="15" size="1" name="MPORTP15" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." /> + <BitField start="16" size="1" name="MPORTP16" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." /> + <BitField start="17" size="1" name="MPORTP17" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." /> + <BitField start="18" size="1" name="MPORTP18" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." /> + <BitField start="19" size="1" name="MPORTP19" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." /> + <BitField start="20" size="1" name="MPORTP20" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." /> + <BitField start="21" size="1" name="MPORTP21" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." /> + <BitField start="22" size="1" name="MPORTP22" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." /> + <BitField start="23" size="1" name="MPORTP23" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." /> + <BitField start="24" size="1" name="MPORTP24" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." /> + <BitField start="25" size="1" name="MPORTP25" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." /> + <BitField start="26" size="1" name="MPORTP26" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." /> + <BitField start="27" size="1" name="MPORTP27" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." /> + <BitField start="28" size="1" name="MPORTP28" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." /> + <BitField start="29" size="1" name="MPORTP29" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." /> + <BitField start="30" size="1" name="MPORTP30" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." /> + <BitField start="31" size="1" name="MPORTP31" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." /> + </Register> + <Register start="+0x2180+4" size="4" name="MPIN[1]" access="Read/Write" description="Masked port register " reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="MPORTP0" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." /> + <BitField start="1" size="1" name="MPORTP1" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." /> + <BitField start="2" size="1" name="MPORTP2" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." /> + <BitField start="3" size="1" name="MPORTP3" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." /> + <BitField start="4" size="1" name="MPORTP4" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." /> + <BitField start="5" size="1" name="MPORTP5" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." /> + <BitField start="6" size="1" name="MPORTP6" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." /> + <BitField start="7" size="1" name="MPORTP7" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." /> + <BitField start="8" size="1" name="MPORTP8" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." /> + <BitField start="9" size="1" name="MPORTP9" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." /> + <BitField start="10" size="1" name="MPORTP10" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." /> + <BitField start="11" size="1" name="MPORTP11" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." /> + <BitField start="12" size="1" name="MPORTP12" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." /> + <BitField start="13" size="1" name="MPORTP13" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." /> + <BitField start="14" size="1" name="MPORTP14" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." /> + <BitField start="15" size="1" name="MPORTP15" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." /> + <BitField start="16" size="1" name="MPORTP16" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." /> + <BitField start="17" size="1" name="MPORTP17" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." /> + <BitField start="18" size="1" name="MPORTP18" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." /> + <BitField start="19" size="1" name="MPORTP19" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." /> + <BitField start="20" size="1" name="MPORTP20" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." /> + <BitField start="21" size="1" name="MPORTP21" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." /> + <BitField start="22" size="1" name="MPORTP22" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." /> + <BitField start="23" size="1" name="MPORTP23" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." /> + <BitField start="24" size="1" name="MPORTP24" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." /> + <BitField start="25" size="1" name="MPORTP25" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." /> + <BitField start="26" size="1" name="MPORTP26" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." /> + <BitField start="27" size="1" name="MPORTP27" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." /> + <BitField start="28" size="1" name="MPORTP28" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." /> + <BitField start="29" size="1" name="MPORTP29" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." /> + <BitField start="30" size="1" name="MPORTP30" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." /> + <BitField start="31" size="1" name="MPORTP31" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." /> + </Register> + <Register start="+0x2180+8" size="4" name="MPIN[2]" access="Read/Write" description="Masked port register " reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="MPORTP0" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." /> + <BitField start="1" size="1" name="MPORTP1" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." /> + <BitField start="2" size="1" name="MPORTP2" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." /> + <BitField start="3" size="1" name="MPORTP3" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." /> + <BitField start="4" size="1" name="MPORTP4" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." /> + <BitField start="5" size="1" name="MPORTP5" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." /> + <BitField start="6" size="1" name="MPORTP6" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." /> + <BitField start="7" size="1" name="MPORTP7" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." /> + <BitField start="8" size="1" name="MPORTP8" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." /> + <BitField start="9" size="1" name="MPORTP9" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." /> + <BitField start="10" size="1" name="MPORTP10" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." /> + <BitField start="11" size="1" name="MPORTP11" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." /> + <BitField start="12" size="1" name="MPORTP12" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." /> + <BitField start="13" size="1" name="MPORTP13" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." /> + <BitField start="14" size="1" name="MPORTP14" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." /> + <BitField start="15" size="1" name="MPORTP15" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." /> + <BitField start="16" size="1" name="MPORTP16" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." /> + <BitField start="17" size="1" name="MPORTP17" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." /> + <BitField start="18" size="1" name="MPORTP18" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." /> + <BitField start="19" size="1" name="MPORTP19" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." /> + <BitField start="20" size="1" name="MPORTP20" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." /> + <BitField start="21" size="1" name="MPORTP21" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." /> + <BitField start="22" size="1" name="MPORTP22" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." /> + <BitField start="23" size="1" name="MPORTP23" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." /> + <BitField start="24" size="1" name="MPORTP24" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." /> + <BitField start="25" size="1" name="MPORTP25" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." /> + <BitField start="26" size="1" name="MPORTP26" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." /> + <BitField start="27" size="1" name="MPORTP27" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." /> + <BitField start="28" size="1" name="MPORTP28" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." /> + <BitField start="29" size="1" name="MPORTP29" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." /> + <BitField start="30" size="1" name="MPORTP30" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." /> + <BitField start="31" size="1" name="MPORTP31" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." /> + </Register> + <Register start="+0x2200+0" size="4" name="SET[0]" access="Read/Write" description="Write: Set port register Read: port output bits " reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="SETP00" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." /> + <BitField start="1" size="1" name="SETP01" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." /> + <BitField start="2" size="1" name="SETP02" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." /> + <BitField start="3" size="1" name="SETP03" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." /> + <BitField start="4" size="1" name="SETP04" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." /> + <BitField start="5" size="1" name="SETP05" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." /> + <BitField start="6" size="1" name="SETP06" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." /> + <BitField start="7" size="1" name="SETP07" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." /> + <BitField start="8" size="1" name="SETP08" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." /> + <BitField start="9" size="1" name="SETP09" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." /> + <BitField start="10" size="1" name="SETP010" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." /> + <BitField start="11" size="1" name="SETP011" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." /> + <BitField start="12" size="1" name="SETP012" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." /> + <BitField start="13" size="1" name="SETP013" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." /> + <BitField start="14" size="1" name="SETP014" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." /> + <BitField start="15" size="1" name="SETP015" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." /> + <BitField start="16" size="1" name="SETP016" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." /> + <BitField start="17" size="1" name="SETP017" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." /> + <BitField start="18" size="1" name="SETP018" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." /> + <BitField start="19" size="1" name="SETP019" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." /> + <BitField start="20" size="1" name="SETP020" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." /> + <BitField start="21" size="1" name="SETP021" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." /> + <BitField start="22" size="1" name="SETP022" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." /> + <BitField start="23" size="1" name="SETP023" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." /> + <BitField start="24" size="1" name="SETP024" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." /> + <BitField start="25" size="1" name="SETP025" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." /> + <BitField start="26" size="1" name="SETP026" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." /> + <BitField start="27" size="1" name="SETP027" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." /> + <BitField start="28" size="1" name="SETP028" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." /> + <BitField start="29" size="1" name="SETP029" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." /> + <BitField start="30" size="1" name="SETP030" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." /> + <BitField start="31" size="1" name="SETP031" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." /> + </Register> + <Register start="+0x2200+4" size="4" name="SET[1]" access="Read/Write" description="Write: Set port register Read: port output bits " reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="SETP00" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." /> + <BitField start="1" size="1" name="SETP01" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." /> + <BitField start="2" size="1" name="SETP02" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." /> + <BitField start="3" size="1" name="SETP03" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." /> + <BitField start="4" size="1" name="SETP04" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." /> + <BitField start="5" size="1" name="SETP05" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." /> + <BitField start="6" size="1" name="SETP06" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." /> + <BitField start="7" size="1" name="SETP07" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." /> + <BitField start="8" size="1" name="SETP08" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." /> + <BitField start="9" size="1" name="SETP09" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." /> + <BitField start="10" size="1" name="SETP010" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." /> + <BitField start="11" size="1" name="SETP011" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." /> + <BitField start="12" size="1" name="SETP012" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." /> + <BitField start="13" size="1" name="SETP013" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." /> + <BitField start="14" size="1" name="SETP014" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." /> + <BitField start="15" size="1" name="SETP015" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." /> + <BitField start="16" size="1" name="SETP016" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." /> + <BitField start="17" size="1" name="SETP017" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." /> + <BitField start="18" size="1" name="SETP018" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." /> + <BitField start="19" size="1" name="SETP019" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." /> + <BitField start="20" size="1" name="SETP020" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." /> + <BitField start="21" size="1" name="SETP021" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." /> + <BitField start="22" size="1" name="SETP022" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." /> + <BitField start="23" size="1" name="SETP023" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." /> + <BitField start="24" size="1" name="SETP024" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." /> + <BitField start="25" size="1" name="SETP025" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." /> + <BitField start="26" size="1" name="SETP026" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." /> + <BitField start="27" size="1" name="SETP027" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." /> + <BitField start="28" size="1" name="SETP028" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." /> + <BitField start="29" size="1" name="SETP029" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." /> + <BitField start="30" size="1" name="SETP030" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." /> + <BitField start="31" size="1" name="SETP031" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." /> + </Register> + <Register start="+0x2200+8" size="4" name="SET[2]" access="Read/Write" description="Write: Set port register Read: port output bits " reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="SETP00" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." /> + <BitField start="1" size="1" name="SETP01" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." /> + <BitField start="2" size="1" name="SETP02" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." /> + <BitField start="3" size="1" name="SETP03" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." /> + <BitField start="4" size="1" name="SETP04" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." /> + <BitField start="5" size="1" name="SETP05" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." /> + <BitField start="6" size="1" name="SETP06" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." /> + <BitField start="7" size="1" name="SETP07" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." /> + <BitField start="8" size="1" name="SETP08" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." /> + <BitField start="9" size="1" name="SETP09" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." /> + <BitField start="10" size="1" name="SETP010" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." /> + <BitField start="11" size="1" name="SETP011" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." /> + <BitField start="12" size="1" name="SETP012" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." /> + <BitField start="13" size="1" name="SETP013" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." /> + <BitField start="14" size="1" name="SETP014" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." /> + <BitField start="15" size="1" name="SETP015" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." /> + <BitField start="16" size="1" name="SETP016" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." /> + <BitField start="17" size="1" name="SETP017" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." /> + <BitField start="18" size="1" name="SETP018" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." /> + <BitField start="19" size="1" name="SETP019" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." /> + <BitField start="20" size="1" name="SETP020" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." /> + <BitField start="21" size="1" name="SETP021" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." /> + <BitField start="22" size="1" name="SETP022" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." /> + <BitField start="23" size="1" name="SETP023" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." /> + <BitField start="24" size="1" name="SETP024" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." /> + <BitField start="25" size="1" name="SETP025" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." /> + <BitField start="26" size="1" name="SETP026" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." /> + <BitField start="27" size="1" name="SETP027" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." /> + <BitField start="28" size="1" name="SETP028" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." /> + <BitField start="29" size="1" name="SETP029" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." /> + <BitField start="30" size="1" name="SETP030" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." /> + <BitField start="31" size="1" name="SETP031" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." /> + </Register> + <Register start="+0x2280+0" size="4" name="CLR[0]" access="WriteOnly" description="Clear port" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="CLRP00" description="Clear output bits: 0 = No operation. 1 = Clear output bit." /> + <BitField start="1" size="1" name="CLRP01" description="Clear output bits: 0 = No operation. 1 = Clear output bit." /> + <BitField start="2" size="1" name="CLRP02" description="Clear output bits: 0 = No operation. 1 = Clear output bit." /> + <BitField start="3" size="1" name="CLRP03" description="Clear output bits: 0 = No operation. 1 = Clear output bit." /> + <BitField start="4" size="1" name="CLRP04" description="Clear output bits: 0 = No operation. 1 = Clear output bit." /> + <BitField start="5" size="1" name="CLRP05" description="Clear output bits: 0 = No operation. 1 = Clear output bit." /> + <BitField start="6" size="1" name="CLRP06" description="Clear output bits: 0 = No operation. 1 = Clear output bit." /> + <BitField start="7" size="1" name="CLRP07" description="Clear output bits: 0 = No operation. 1 = Clear output bit." /> + <BitField start="8" size="1" name="CLRP08" description="Clear output bits: 0 = No operation. 1 = Clear output bit." /> + <BitField start="9" size="1" name="CLRP09" description="Clear output bits: 0 = No operation. 1 = Clear output bit." /> + <BitField start="10" size="1" name="CLRP010" description="Clear output bits: 0 = No operation. 1 = Clear output bit." /> + <BitField start="11" size="1" name="CLRP011" description="Clear output bits: 0 = No operation. 1 = Clear output bit." /> + <BitField start="12" size="1" name="CLRP012" description="Clear output bits: 0 = No operation. 1 = Clear output bit." /> + <BitField start="13" size="1" name="CLRP013" description="Clear output bits: 0 = No operation. 1 = Clear output bit." /> + <BitField start="14" size="1" name="CLRP014" description="Clear output bits: 0 = No operation. 1 = Clear output bit." /> + <BitField start="15" size="1" name="CLRP015" description="Clear output bits: 0 = No operation. 1 = Clear output bit." /> + <BitField start="16" size="1" name="CLRP016" description="Clear output bits: 0 = No operation. 1 = Clear output bit." /> + <BitField start="17" size="1" name="CLRP017" description="Clear output bits: 0 = No operation. 1 = Clear output bit." /> + <BitField start="18" size="1" name="CLRP018" description="Clear output bits: 0 = No operation. 1 = Clear output bit." /> + <BitField start="19" size="1" name="CLRP019" description="Clear output bits: 0 = No operation. 1 = Clear output bit." /> + <BitField start="20" size="1" name="CLRP020" description="Clear output bits: 0 = No operation. 1 = Clear output bit." /> + <BitField start="21" size="1" name="CLRP021" description="Clear output bits: 0 = No operation. 1 = Clear output bit." /> + <BitField start="22" size="1" name="CLRP022" description="Clear output bits: 0 = No operation. 1 = Clear output bit." /> + <BitField start="23" size="1" name="CLRP023" description="Clear output bits: 0 = No operation. 1 = Clear output bit." /> + <BitField start="24" size="1" name="CLRP024" description="Clear output bits: 0 = No operation. 1 = Clear output bit." /> + <BitField start="25" size="1" name="CLRP025" description="Clear output bits: 0 = No operation. 1 = Clear output bit." /> + <BitField start="26" size="1" name="CLRP026" description="Clear output bits: 0 = No operation. 1 = Clear output bit." /> + <BitField start="27" size="1" name="CLRP027" description="Clear output bits: 0 = No operation. 1 = Clear output bit." /> + <BitField start="28" size="1" name="CLRP028" description="Clear output bits: 0 = No operation. 1 = Clear output bit." /> + <BitField start="29" size="1" name="CLRP029" description="Clear output bits: 0 = No operation. 1 = Clear output bit." /> + <BitField start="30" size="1" name="CLRP030" description="Clear output bits: 0 = No operation. 1 = Clear output bit." /> + <BitField start="31" size="1" name="CLRP031" description="Clear output bits: 0 = No operation. 1 = Clear output bit." /> + </Register> + <Register start="+0x2280+4" size="4" name="CLR[1]" access="WriteOnly" description="Clear port" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="CLRP00" description="Clear output bits: 0 = No operation. 1 = Clear output bit." /> + <BitField start="1" size="1" name="CLRP01" description="Clear output bits: 0 = No operation. 1 = Clear output bit." /> + <BitField start="2" size="1" name="CLRP02" description="Clear output bits: 0 = No operation. 1 = Clear output bit." /> + <BitField start="3" size="1" name="CLRP03" description="Clear output bits: 0 = No operation. 1 = Clear output bit." /> + <BitField start="4" size="1" name="CLRP04" description="Clear output bits: 0 = No operation. 1 = Clear output bit." /> + <BitField start="5" size="1" name="CLRP05" description="Clear output bits: 0 = No operation. 1 = Clear output bit." /> + <BitField start="6" size="1" name="CLRP06" description="Clear output bits: 0 = No operation. 1 = Clear output bit." /> + <BitField start="7" size="1" name="CLRP07" description="Clear output bits: 0 = No operation. 1 = Clear output bit." /> + <BitField start="8" size="1" name="CLRP08" description="Clear output bits: 0 = No operation. 1 = Clear output bit." /> + <BitField start="9" size="1" name="CLRP09" description="Clear output bits: 0 = No operation. 1 = Clear output bit." /> + <BitField start="10" size="1" name="CLRP010" description="Clear output bits: 0 = No operation. 1 = Clear output bit." /> + <BitField start="11" size="1" name="CLRP011" description="Clear output bits: 0 = No operation. 1 = Clear output bit." /> + <BitField start="12" size="1" name="CLRP012" description="Clear output bits: 0 = No operation. 1 = Clear output bit." /> + <BitField start="13" size="1" name="CLRP013" description="Clear output bits: 0 = No operation. 1 = Clear output bit." /> + <BitField start="14" size="1" name="CLRP014" description="Clear output bits: 0 = No operation. 1 = Clear output bit." /> + <BitField start="15" size="1" name="CLRP015" description="Clear output bits: 0 = No operation. 1 = Clear output bit." /> + <BitField start="16" size="1" name="CLRP016" description="Clear output bits: 0 = No operation. 1 = Clear output bit." /> + <BitField start="17" size="1" name="CLRP017" description="Clear output bits: 0 = No operation. 1 = Clear output bit." /> + <BitField start="18" size="1" name="CLRP018" description="Clear output bits: 0 = No operation. 1 = Clear output bit." /> + <BitField start="19" size="1" name="CLRP019" description="Clear output bits: 0 = No operation. 1 = Clear output bit." /> + <BitField start="20" size="1" name="CLRP020" description="Clear output bits: 0 = No operation. 1 = Clear output bit." /> + <BitField start="21" size="1" name="CLRP021" description="Clear output bits: 0 = No operation. 1 = Clear output bit." /> + <BitField start="22" size="1" name="CLRP022" description="Clear output bits: 0 = No operation. 1 = Clear output bit." /> + <BitField start="23" size="1" name="CLRP023" description="Clear output bits: 0 = No operation. 1 = Clear output bit." /> + <BitField start="24" size="1" name="CLRP024" description="Clear output bits: 0 = No operation. 1 = Clear output bit." /> + <BitField start="25" size="1" name="CLRP025" description="Clear output bits: 0 = No operation. 1 = Clear output bit." /> + <BitField start="26" size="1" name="CLRP026" description="Clear output bits: 0 = No operation. 1 = Clear output bit." /> + <BitField start="27" size="1" name="CLRP027" description="Clear output bits: 0 = No operation. 1 = Clear output bit." /> + <BitField start="28" size="1" name="CLRP028" description="Clear output bits: 0 = No operation. 1 = Clear output bit." /> + <BitField start="29" size="1" name="CLRP029" description="Clear output bits: 0 = No operation. 1 = Clear output bit." /> + <BitField start="30" size="1" name="CLRP030" description="Clear output bits: 0 = No operation. 1 = Clear output bit." /> + <BitField start="31" size="1" name="CLRP031" description="Clear output bits: 0 = No operation. 1 = Clear output bit." /> + </Register> + <Register start="+0x2280+8" size="4" name="CLR[2]" access="WriteOnly" description="Clear port" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="CLRP00" description="Clear output bits: 0 = No operation. 1 = Clear output bit." /> + <BitField start="1" size="1" name="CLRP01" description="Clear output bits: 0 = No operation. 1 = Clear output bit." /> + <BitField start="2" size="1" name="CLRP02" description="Clear output bits: 0 = No operation. 1 = Clear output bit." /> + <BitField start="3" size="1" name="CLRP03" description="Clear output bits: 0 = No operation. 1 = Clear output bit." /> + <BitField start="4" size="1" name="CLRP04" description="Clear output bits: 0 = No operation. 1 = Clear output bit." /> + <BitField start="5" size="1" name="CLRP05" description="Clear output bits: 0 = No operation. 1 = Clear output bit." /> + <BitField start="6" size="1" name="CLRP06" description="Clear output bits: 0 = No operation. 1 = Clear output bit." /> + <BitField start="7" size="1" name="CLRP07" description="Clear output bits: 0 = No operation. 1 = Clear output bit." /> + <BitField start="8" size="1" name="CLRP08" description="Clear output bits: 0 = No operation. 1 = Clear output bit." /> + <BitField start="9" size="1" name="CLRP09" description="Clear output bits: 0 = No operation. 1 = Clear output bit." /> + <BitField start="10" size="1" name="CLRP010" description="Clear output bits: 0 = No operation. 1 = Clear output bit." /> + <BitField start="11" size="1" name="CLRP011" description="Clear output bits: 0 = No operation. 1 = Clear output bit." /> + <BitField start="12" size="1" name="CLRP012" description="Clear output bits: 0 = No operation. 1 = Clear output bit." /> + <BitField start="13" size="1" name="CLRP013" description="Clear output bits: 0 = No operation. 1 = Clear output bit." /> + <BitField start="14" size="1" name="CLRP014" description="Clear output bits: 0 = No operation. 1 = Clear output bit." /> + <BitField start="15" size="1" name="CLRP015" description="Clear output bits: 0 = No operation. 1 = Clear output bit." /> + <BitField start="16" size="1" name="CLRP016" description="Clear output bits: 0 = No operation. 1 = Clear output bit." /> + <BitField start="17" size="1" name="CLRP017" description="Clear output bits: 0 = No operation. 1 = Clear output bit." /> + <BitField start="18" size="1" name="CLRP018" description="Clear output bits: 0 = No operation. 1 = Clear output bit." /> + <BitField start="19" size="1" name="CLRP019" description="Clear output bits: 0 = No operation. 1 = Clear output bit." /> + <BitField start="20" size="1" name="CLRP020" description="Clear output bits: 0 = No operation. 1 = Clear output bit." /> + <BitField start="21" size="1" name="CLRP021" description="Clear output bits: 0 = No operation. 1 = Clear output bit." /> + <BitField start="22" size="1" name="CLRP022" description="Clear output bits: 0 = No operation. 1 = Clear output bit." /> + <BitField start="23" size="1" name="CLRP023" description="Clear output bits: 0 = No operation. 1 = Clear output bit." /> + <BitField start="24" size="1" name="CLRP024" description="Clear output bits: 0 = No operation. 1 = Clear output bit." /> + <BitField start="25" size="1" name="CLRP025" description="Clear output bits: 0 = No operation. 1 = Clear output bit." /> + <BitField start="26" size="1" name="CLRP026" description="Clear output bits: 0 = No operation. 1 = Clear output bit." /> + <BitField start="27" size="1" name="CLRP027" description="Clear output bits: 0 = No operation. 1 = Clear output bit." /> + <BitField start="28" size="1" name="CLRP028" description="Clear output bits: 0 = No operation. 1 = Clear output bit." /> + <BitField start="29" size="1" name="CLRP029" description="Clear output bits: 0 = No operation. 1 = Clear output bit." /> + <BitField start="30" size="1" name="CLRP030" description="Clear output bits: 0 = No operation. 1 = Clear output bit." /> + <BitField start="31" size="1" name="CLRP031" description="Clear output bits: 0 = No operation. 1 = Clear output bit." /> + </Register> + <Register start="+0x2300+0" size="4" name="NOT[0]" access="WriteOnly" description="Toggle port " reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="NOTP00" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." /> + <BitField start="1" size="1" name="NOTP01" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." /> + <BitField start="2" size="1" name="NOTP02" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." /> + <BitField start="3" size="1" name="NOTP03" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." /> + <BitField start="4" size="1" name="NOTP04" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." /> + <BitField start="5" size="1" name="NOTP05" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." /> + <BitField start="6" size="1" name="NOTP06" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." /> + <BitField start="7" size="1" name="NOTP07" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." /> + <BitField start="8" size="1" name="NOTP08" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." /> + <BitField start="9" size="1" name="NOTP09" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." /> + <BitField start="10" size="1" name="NOTP010" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." /> + <BitField start="11" size="1" name="NOTP011" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." /> + <BitField start="12" size="1" name="NOTP012" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." /> + <BitField start="13" size="1" name="NOTP013" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." /> + <BitField start="14" size="1" name="NOTP014" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." /> + <BitField start="15" size="1" name="NOTP015" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." /> + <BitField start="16" size="1" name="NOTP016" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." /> + <BitField start="17" size="1" name="NOTP017" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." /> + <BitField start="18" size="1" name="NOTP018" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." /> + <BitField start="19" size="1" name="NOTP019" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." /> + <BitField start="20" size="1" name="NOTP020" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." /> + <BitField start="21" size="1" name="NOTP021" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." /> + <BitField start="22" size="1" name="NOTP022" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." /> + <BitField start="23" size="1" name="NOTP023" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." /> + <BitField start="24" size="1" name="NOTP024" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." /> + <BitField start="25" size="1" name="NOTP025" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." /> + <BitField start="26" size="1" name="NOTP026" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." /> + <BitField start="27" size="1" name="NOTP027" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." /> + <BitField start="28" size="1" name="NOTP028" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." /> + <BitField start="29" size="1" name="NOTP029" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." /> + <BitField start="30" size="1" name="NOTP030" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." /> + <BitField start="31" size="1" name="NOTP031" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." /> + </Register> + <Register start="+0x2300+4" size="4" name="NOT[1]" access="WriteOnly" description="Toggle port " reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="NOTP00" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." /> + <BitField start="1" size="1" name="NOTP01" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." /> + <BitField start="2" size="1" name="NOTP02" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." /> + <BitField start="3" size="1" name="NOTP03" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." /> + <BitField start="4" size="1" name="NOTP04" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." /> + <BitField start="5" size="1" name="NOTP05" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." /> + <BitField start="6" size="1" name="NOTP06" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." /> + <BitField start="7" size="1" name="NOTP07" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." /> + <BitField start="8" size="1" name="NOTP08" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." /> + <BitField start="9" size="1" name="NOTP09" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." /> + <BitField start="10" size="1" name="NOTP010" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." /> + <BitField start="11" size="1" name="NOTP011" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." /> + <BitField start="12" size="1" name="NOTP012" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." /> + <BitField start="13" size="1" name="NOTP013" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." /> + <BitField start="14" size="1" name="NOTP014" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." /> + <BitField start="15" size="1" name="NOTP015" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." /> + <BitField start="16" size="1" name="NOTP016" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." /> + <BitField start="17" size="1" name="NOTP017" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." /> + <BitField start="18" size="1" name="NOTP018" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." /> + <BitField start="19" size="1" name="NOTP019" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." /> + <BitField start="20" size="1" name="NOTP020" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." /> + <BitField start="21" size="1" name="NOTP021" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." /> + <BitField start="22" size="1" name="NOTP022" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." /> + <BitField start="23" size="1" name="NOTP023" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." /> + <BitField start="24" size="1" name="NOTP024" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." /> + <BitField start="25" size="1" name="NOTP025" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." /> + <BitField start="26" size="1" name="NOTP026" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." /> + <BitField start="27" size="1" name="NOTP027" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." /> + <BitField start="28" size="1" name="NOTP028" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." /> + <BitField start="29" size="1" name="NOTP029" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." /> + <BitField start="30" size="1" name="NOTP030" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." /> + <BitField start="31" size="1" name="NOTP031" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." /> + </Register> + <Register start="+0x2300+8" size="4" name="NOT[2]" access="WriteOnly" description="Toggle port " reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="NOTP00" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." /> + <BitField start="1" size="1" name="NOTP01" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." /> + <BitField start="2" size="1" name="NOTP02" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." /> + <BitField start="3" size="1" name="NOTP03" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." /> + <BitField start="4" size="1" name="NOTP04" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." /> + <BitField start="5" size="1" name="NOTP05" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." /> + <BitField start="6" size="1" name="NOTP06" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." /> + <BitField start="7" size="1" name="NOTP07" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." /> + <BitField start="8" size="1" name="NOTP08" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." /> + <BitField start="9" size="1" name="NOTP09" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." /> + <BitField start="10" size="1" name="NOTP010" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." /> + <BitField start="11" size="1" name="NOTP011" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." /> + <BitField start="12" size="1" name="NOTP012" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." /> + <BitField start="13" size="1" name="NOTP013" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." /> + <BitField start="14" size="1" name="NOTP014" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." /> + <BitField start="15" size="1" name="NOTP015" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." /> + <BitField start="16" size="1" name="NOTP016" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." /> + <BitField start="17" size="1" name="NOTP017" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." /> + <BitField start="18" size="1" name="NOTP018" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." /> + <BitField start="19" size="1" name="NOTP019" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." /> + <BitField start="20" size="1" name="NOTP020" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." /> + <BitField start="21" size="1" name="NOTP021" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." /> + <BitField start="22" size="1" name="NOTP022" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." /> + <BitField start="23" size="1" name="NOTP023" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." /> + <BitField start="24" size="1" name="NOTP024" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." /> + <BitField start="25" size="1" name="NOTP025" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." /> + <BitField start="26" size="1" name="NOTP026" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." /> + <BitField start="27" size="1" name="NOTP027" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." /> + <BitField start="28" size="1" name="NOTP028" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." /> + <BitField start="29" size="1" name="NOTP029" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." /> + <BitField start="30" size="1" name="NOTP030" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." /> + <BitField start="31" size="1" name="NOTP031" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." /> + </Register> + </RegisterGroup> + <RegisterGroup name="PINT" start="0xA0004000" description=" Pin interrupt
and pattern match (PINT) "> + <Register start="+0x000" size="4" name="ISEL" access="Read/Write" description="Pin Interrupt Mode register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="PMODE0" description="Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive" /> + <BitField start="1" size="1" name="PMODE1" description="Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive" /> + <BitField start="2" size="1" name="PMODE2" description="Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive" /> + <BitField start="3" size="1" name="PMODE3" description="Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive" /> + <BitField start="4" size="1" name="PMODE4" description="Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive" /> + <BitField start="5" size="1" name="PMODE5" description="Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive" /> + <BitField start="6" size="1" name="PMODE6" description="Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive" /> + <BitField start="7" size="1" name="PMODE7" description="Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive" /> + <BitField start="8" size="24" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x004" size="4" name="IENR" access="Read/Write" description="Pin interrupt level or rising edge interrupt enable register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="ENRL0" description="Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt." /> + <BitField start="1" size="1" name="ENRL1" description="Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt." /> + <BitField start="2" size="1" name="ENRL2" description="Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt." /> + <BitField start="3" size="1" name="ENRL3" description="Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt." /> + <BitField start="4" size="1" name="ENRL4" description="Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt." /> + <BitField start="5" size="1" name="ENRL5" description="Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt." /> + <BitField start="6" size="1" name="ENRL6" description="Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt." /> + <BitField start="7" size="1" name="ENRL7" description="Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x008" size="4" name="SIENR" access="WriteOnly" description="Pin interrupt level or rising edge interrupt set register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="SETENRL0" description="Ones written to this address set bits in the IENR, thus enabling interrupts. Bit n sets bit n in the IENR register. 0 = No operation. 1 = Enable rising edge or level interrupt." /> + <BitField start="1" size="1" name="SETENRL1" description="Ones written to this address set bits in the IENR, thus enabling interrupts. Bit n sets bit n in the IENR register. 0 = No operation. 1 = Enable rising edge or level interrupt." /> + <BitField start="2" size="1" name="SETENRL2" description="Ones written to this address set bits in the IENR, thus enabling interrupts. Bit n sets bit n in the IENR register. 0 = No operation. 1 = Enable rising edge or level interrupt." /> + <BitField start="3" size="1" name="SETENRL3" description="Ones written to this address set bits in the IENR, thus enabling interrupts. Bit n sets bit n in the IENR register. 0 = No operation. 1 = Enable rising edge or level interrupt." /> + <BitField start="4" size="1" name="SETENRL4" description="Ones written to this address set bits in the IENR, thus enabling interrupts. Bit n sets bit n in the IENR register. 0 = No operation. 1 = Enable rising edge or level interrupt." /> + <BitField start="5" size="1" name="SETENRL5" description="Ones written to this address set bits in the IENR, thus enabling interrupts. Bit n sets bit n in the IENR register. 0 = No operation. 1 = Enable rising edge or level interrupt." /> + <BitField start="6" size="1" name="SETENRL6" description="Ones written to this address set bits in the IENR, thus enabling interrupts. Bit n sets bit n in the IENR register. 0 = No operation. 1 = Enable rising edge or level interrupt." /> + <BitField start="7" size="1" name="SETENRL7" description="Ones written to this address set bits in the IENR, thus enabling interrupts. Bit n sets bit n in the IENR register. 0 = No operation. 1 = Enable rising edge or level interrupt." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x00C" size="4" name="CIENR" access="WriteOnly" description="Pin interrupt level (rising edge interrupt) clear register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="CENRL0" description="Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt." /> + <BitField start="1" size="1" name="CENRL1" description="Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt." /> + <BitField start="2" size="1" name="CENRL2" description="Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt." /> + <BitField start="3" size="1" name="CENRL3" description="Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt." /> + <BitField start="4" size="1" name="CENRL4" description="Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt." /> + <BitField start="5" size="1" name="CENRL5" description="Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt." /> + <BitField start="6" size="1" name="CENRL6" description="Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt." /> + <BitField start="7" size="1" name="CENRL7" description="Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x010" size="4" name="IENF" access="Read/Write" description="Pin interrupt active level or falling edge interrupt enable register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="ENAF0" description="Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH." /> + <BitField start="1" size="1" name="ENAF1" description="Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH." /> + <BitField start="2" size="1" name="ENAF2" description="Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH." /> + <BitField start="3" size="1" name="ENAF3" description="Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH." /> + <BitField start="4" size="1" name="ENAF4" description="Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH." /> + <BitField start="5" size="1" name="ENAF5" description="Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH." /> + <BitField start="6" size="1" name="ENAF6" description="Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH." /> + <BitField start="7" size="1" name="ENAF7" description="Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x014" size="4" name="SIENF" access="WriteOnly" description="Pin interrupt active level or falling edge interrupt set register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="SETENAF0" description="Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt." /> + <BitField start="1" size="1" name="SETENAF1" description="Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt." /> + <BitField start="2" size="1" name="SETENAF2" description="Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt." /> + <BitField start="3" size="1" name="SETENAF3" description="Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt." /> + <BitField start="4" size="1" name="SETENAF4" description="Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt." /> + <BitField start="5" size="1" name="SETENAF5" description="Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt." /> + <BitField start="6" size="1" name="SETENAF6" description="Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt." /> + <BitField start="7" size="1" name="SETENAF7" description="Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x018" size="4" name="CIENF" access="WriteOnly" description="Pin interrupt active level or falling edge interrupt clear register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="CENAF0" description="Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled." /> + <BitField start="1" size="1" name="CENAF1" description="Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled." /> + <BitField start="2" size="1" name="CENAF2" description="Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled." /> + <BitField start="3" size="1" name="CENAF3" description="Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled." /> + <BitField start="4" size="1" name="CENAF4" description="Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled." /> + <BitField start="5" size="1" name="CENAF5" description="Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled." /> + <BitField start="6" size="1" name="CENAF6" description="Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled." /> + <BitField start="7" size="1" name="CENAF7" description="Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x01C" size="4" name="RISE" access="Read/Write" description="Pin interrupt rising edge register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RDET0" description="Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin." /> + <BitField start="1" size="1" name="RDET1" description="Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin." /> + <BitField start="2" size="1" name="RDET2" description="Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin." /> + <BitField start="3" size="1" name="RDET3" description="Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin." /> + <BitField start="4" size="1" name="RDET4" description="Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin." /> + <BitField start="5" size="1" name="RDET5" description="Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin." /> + <BitField start="6" size="1" name="RDET6" description="Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin." /> + <BitField start="7" size="1" name="RDET7" description="Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x020" size="4" name="FALL" access="Read/Write" description="Pin interrupt falling edge register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="FDET0" description="Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin." /> + <BitField start="1" size="1" name="FDET1" description="Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin." /> + <BitField start="2" size="1" name="FDET2" description="Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin." /> + <BitField start="3" size="1" name="FDET3" description="Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin." /> + <BitField start="4" size="1" name="FDET4" description="Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin." /> + <BitField start="5" size="1" name="FDET5" description="Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin." /> + <BitField start="6" size="1" name="FDET6" description="Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin." /> + <BitField start="7" size="1" name="FDET7" description="Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x024" size="4" name="IST" access="Read/Write" description="Pin interrupt status register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="PSTAT0" description="Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin. Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the IENF register)." /> + <BitField start="1" size="1" name="PSTAT1" description="Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin. Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the IENF register)." /> + <BitField start="2" size="1" name="PSTAT2" description="Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin. Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the IENF register)." /> + <BitField start="3" size="1" name="PSTAT3" description="Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin. Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the IENF register)." /> + <BitField start="4" size="1" name="PSTAT4" description="Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin. Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the IENF register)." /> + <BitField start="5" size="1" name="PSTAT5" description="Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin. Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the IENF register)." /> + <BitField start="6" size="1" name="PSTAT6" description="Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin. Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the IENF register)." /> + <BitField start="7" size="1" name="PSTAT7" description="Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin. Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the IENF register)." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x028" size="4" name="PMCTRL" access="Read/Write" description="Pattern match interrupt control register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="SEL_PMATCH" description="Specifies whether the 8 pin interrupts are controlled by the pin interrupt function or by the pattern match function."> + <Enum name="PIN_INTERRUPT_INTER" start="0" description="Pin interrupt. Interrupts are driven in response to the standard pin interrupt function" /> + <Enum name="PATTERN_MATCH_INTER" start="1" description="Pattern match. Interrupts are driven in response to pattern matches." /> + </BitField> + <BitField start="1" size="1" name="ENA_RXEV" description="Enables the RXEV output to the ARM cpu and/or to a GPIO output when the specified boolean expression evaluates to true."> + <Enum name="DISABLED_RXEV_OUTPU" start="0" description="Disabled. RXEV output to the cpu is disabled." /> + <Enum name="ENABLED_RXEV_OUTPUT" start="1" description="Enabled. RXEV output to the cpu is enabled." /> + </BitField> + <BitField start="2" size="22" name="RESERVED" description="Reserved. Do not write 1s to unused bits." /> + <BitField start="24" size="8" name="PMAT" description="This field displays the current state of pattern matches. A 1 in any bit of this field indicates that the corresponding product term is matched by the current state of the appropriate inputs." /> + </Register> + <Register start="+0x02C" size="4" name="PMSRC" access="Read/Write" description="Pattern match interrupt bit-slice source register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="Reserved" description="Software should not write 1s to unused bits." /> + <BitField start="8" size="3" name="SRC0" description="Selects the input source for bit slice 0"> + <Enum name="INPUT_0_SELECTS_PIN" start="0x0" description="Input 0. Selects the output of pin interrupt select register 0 as the source to bit slice 0." /> + <Enum name="INPUT_1_SELECTS_PIN" start="0x1" description="Input 1. Selects the output of pin interrupt select register 1 as the source to bit slice 0." /> + <Enum name="INPUT_2_SELECTS_PIN" start="0x2" description="Input 2. Selects the output of pin interrupt select register 2 as the source to bit slice 0." /> + <Enum name="INPUT_3_SELECTS_PIN" start="0x3" description="Input 3. Selects the output of pin interrupt select register 3 as the source to bit slice 0." /> + <Enum name="INPUT_4_SELECTS_PIN" start="0x4" description="Input 4. Selects the output of pin interrupt select register 4 as the source to bit slice 0." /> + <Enum name="INPUT_5_SELECTS_PIN" start="0x5" description="Input 5. Selects the output of pin interrupt select register 5 as the source to bit slice 0." /> + <Enum name="INPUT_6_SELECTS_PIN" start="0x6" description="Input 6. Selects the output of pin interrupt select register 6 as the source to bit slice 0." /> + <Enum name="INPUT_7_SELECTS_PIN" start="0x7" description="Input 7. Selects the output of pin interrupt select register 7 as the source to bit slice 0." /> + </BitField> + <BitField start="11" size="3" name="SRC1" description="Selects the input source for bit slice 1"> + <Enum name="INPUT_0_SELECTS_PIN" start="0x0" description="Input 0. Selects pin interrupt input 0 as the source to bit slice 1." /> + <Enum name="INPUT_1_SELECTS_PIN" start="0x1" description="Input 1. Selects pin interrupt input 1 as the source to bit slice 1." /> + <Enum name="INPUT_2_SELECTS_PIN" start="0x2" description="Input 2. Selects pin interrupt input 2 as the source to bit slice 1." /> + <Enum name="INPUT_3_SELECTS_PIN" start="0x3" description="Input 3. Selects pin interrupt input 3 as the source to bit slice 1." /> + <Enum name="INPUT_4_SELECTS_PIN" start="0x4" description="Input 4. Selects pin interrupt input 4 as the source to bit slice 1." /> + <Enum name="INPUT_5_SELECTS_PIN" start="0x5" description="Input 5. Selects pin interrupt input 5 as the source to bit slice 1." /> + <Enum name="INPUT_6_SELECTS_PIN" start="0x6" description="Input 6. Selects pin interrupt input 6 as the source to bit slice 1." /> + <Enum name="INPUT_7_SELECTS_PIN" start="0x7" description="Input 7. Selects pin interrupt input 7 as the source to bit slice 1." /> + </BitField> + <BitField start="14" size="3" name="SRC2" description="Selects the input source for bit slice 2"> + <Enum name="INPUT_0_SELECTS_PIN" start="0x0" description="Input 0. Selects pin interrupt input 0 as the source to bit slice 2." /> + <Enum name="INPUT_1_SELECTS_PIN" start="0x1" description="Input 1. Selects pin interrupt input 1 as the source to bit slice 2." /> + <Enum name="INPUT_2_SELECTS_PIN" start="0x2" description="Input 2. Selects pin interrupt input 2 as the source to bit slice 2." /> + <Enum name="INPUT_3_SELECTS_PIN" start="0x3" description="Input 3. Selects pin interrupt input 3 as the source to bit slice 2." /> + <Enum name="INPUT_4_SELECTS_PIN" start="0x4" description="Input 4. Selects pin interrupt input 4 as the source to bit slice 2." /> + <Enum name="INPUT_5_SELECTS_PIN" start="0x5" description="Input 5. Selects pin interrupt input 5 as the source to bit slice 2." /> + <Enum name="INPUT_6_SELECTS_PIN" start="0x6" description="Input 6. Selects pin interrupt input 6 as the source to bit slice 2." /> + <Enum name="INPUT_7_SELECTS_PIN" start="0x7" description="Input 7. Selects pin interrupt input 7 as the source to bit slice 2." /> + </BitField> + <BitField start="17" size="3" name="SRC3" description="Selects the input source for bit slice 3"> + <Enum name="INPUT_0_SELECTS_PIN" start="0x0" description="Input 0. Selects pin interrupt input 0 as the source to bit slice 3." /> + <Enum name="INPUT_1_SELECTS_PIN" start="0x1" description="Input 1. Selects pin interrupt input 1 as the source to bit slice 3." /> + <Enum name="INPUT_2_SELECTS_PIN" start="0x2" description="Input 2. Selects pin interrupt input 2 as the source to bit slice 3." /> + <Enum name="INPUT_3_SELECTS_PIN" start="0x3" description="Input 3. Selects pin interrupt input 3 as the source to bit slice 3." /> + <Enum name="INPUT_4_SELECTS_PIN" start="0x4" description="Input 4. Selects pin interrupt input 4 as the source to bit slice 3." /> + <Enum name="INPUT_5_SELECTS_PIN" start="0x5" description="Input 5. Selects pin interrupt input 5 as the source to bit slice 3." /> + <Enum name="INPUT_6_SELECTS_PIN" start="0x6" description="Input 6. Selects pin interrupt input 6 as the source to bit slice 3." /> + <Enum name="INPUT_7_SELECTS_PIN" start="0x7" description="Input 7. Selects pin interrupt input 7 as the source to bit slice 3." /> + </BitField> + <BitField start="20" size="3" name="SRC4" description="Selects the input source for bit slice 4"> + <Enum name="INPUT_0_SELECTS_PIN" start="0x0" description="Input 0. Selects pin interrupt input 0 as the source to bit slice 4." /> + <Enum name="INPUT_1_SELECTS_PIN" start="0x1" description="Input 1. Selects pin interrupt input 1 as the source to bit slice 4." /> + <Enum name="INPUT_2_SELECTS_PIN" start="0x2" description="Input 2. Selects pin interrupt input 2 as the source to bit slice 4." /> + <Enum name="INPUT_3_SELECTS_PIN" start="0x3" description="Input 3. Selects pin interrupt input 3 as the source to bit slice 4." /> + <Enum name="INPUT_4_SELECTS_PIN" start="0x4" description="Input 4. Selects pin interrupt input 4 as the source to bit slice 4." /> + <Enum name="INPUT_5_SELECTS_PIN" start="0x5" description="Input 5. Selects pin interrupt input 5 as the source to bit slice 4." /> + <Enum name="INPUT_6_SELECTS_PIN" start="0x6" description="Input 6. Selects pin interrupt input 6 as the source to bit slice 4." /> + <Enum name="INPUT_7_SELECTS_PIN" start="0x7" description="Input 7. Selects pin interrupt input 7 as the source to bit slice 4." /> + </BitField> + <BitField start="23" size="3" name="SRC5" description="Selects the input source for bit slice 5"> + <Enum name="INPUT_0_SELECTS_PIN" start="0x0" description="Input 0. Selects pin interrupt input 0 as the source to bit slice 5." /> + <Enum name="INPUT_1_SELECTS_PIN" start="0x1" description="Input 1. Selects pin interrupt input 1 as the source to bit slice 5." /> + <Enum name="INPUT_2_SELECTS_PIN" start="0x2" description="Input 2. Selects pin interrupt input 2 as the source to bit slice 5." /> + <Enum name="INPUT_3_SELECTS_PIN" start="0x3" description="Input 3. Selects pin interrupt input 3 as the source to bit slice 5." /> + <Enum name="INPUT_4_SELECTS_PIN" start="0x4" description="Input 4. Selects pin interrupt input 4 as the source to bit slice 5." /> + <Enum name="INPUT_5_SELECTS_PIN" start="0x5" description="Input 5. Selects pin interrupt input 5 as the source to bit slice 5." /> + <Enum name="INPUT_6_SELECTS_PIN" start="0x6" description="Input 6. Selects pin interrupt input 6 as the source to bit slice 5." /> + <Enum name="INPUT_7_SELECTS_PIN" start="0x7" description="Input 7. Selects pin interrupt input 7 as the source to bit slice 5." /> + </BitField> + <BitField start="26" size="3" name="SRC6" description="Selects the input source for bit slice 6"> + <Enum name="INPUT_0_SELECTS_PIN" start="0x0" description="Input 0. Selects pin interrupt input 0 as the source to bit slice 6." /> + <Enum name="INPUT_1_SELECTS_PIN" start="0x1" description="Input 1. Selects pin interrupt input 1 as the source to bit slice 6." /> + <Enum name="INPUT_2_SELECTS_PIN" start="0x2" description="Input 2. Selects pin interrupt input 2 as the source to bit slice 6." /> + <Enum name="INPUT_3_SELECTS_PIN" start="0x3" description="Input 3. Selects pin interrupt input 3 as the source to bit slice 6." /> + <Enum name="INPUT_4_SELECTS_PIN" start="0x4" description="Input 4. Selects pin interrupt input 4 as the source to bit slice 6." /> + <Enum name="INPUT_5_SELECTS_PIN" start="0x5" description="Input 5. Selects pin interrupt input 5 as the source to bit slice 6." /> + <Enum name="INPUT_6_SELECTS_PIN" start="0x6" description="Input 6. Selects pin interrupt input 6 as the source to bit slice 6." /> + <Enum name="INPUT_7_SELECTS_PIN" start="0x7" description="Input 7. Selects pin interrupt input 7 as the source to bit slice 6." /> + </BitField> + <BitField start="29" size="3" name="SRC7" description="Selects the input source for bit slice 7"> + <Enum name="INPUT_0_SELECTS_PIN" start="0x0" description="Input 0. Selects pin interrupt input 0 as the source to bit slice 7." /> + <Enum name="INPUT_1_SELECTS_PIN" start="0x1" description="Input 1. Selects pin interrupt input 1 as the source to bit slice 7." /> + <Enum name="INPUT_2_SELECTS_PIN" start="0x2" description="Input 2. Selects pin interrupt input 2 as the source to bit slice 7." /> + <Enum name="INPUT_3_SELECTS_PIN" start="0x3" description="Input 3. Selects pin interrupt input 3 as the source to bit slice 7." /> + <Enum name="INPUT_4_SELECTS_PIN" start="0x4" description="Input 4. Selects pin interrupt input 4 as the source to bit slice 7." /> + <Enum name="INPUT_5_SELECTS_PIN" start="0x5" description="Input 5. Selects pin interrupt input 5 as the source to bit slice 7." /> + <Enum name="INPUT_6_SELECTS_PIN" start="0x6" description="Input 6. Selects pin interrupt input 6 as the source to bit slice 7." /> + <Enum name="INPUT_7_SELECTS_PIN" start="0x7" description="Input 7. Selects pin interrupt input 7 as the source to bit slice 7." /> + </BitField> + </Register> + <Register start="+0x030" size="4" name="PMCFG" access="Read/Write" description="Pattern match interrupt bit slice configuration register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="7" name="PROD_ENDPTS" description="A 1 in any bit of this field causes the corresponding bit slice to be the final component of a product term in the boolean expression. This has two effects: 1. The interrupt request associated with this bit-slice will be asserted whenever a match to that product term is detected. 2. The next bit slice will start a new, independent product term in the boolean expression (i.e. an OR will be inserted in the boolean expression following the element controlled by this bit slice)." /> + <BitField start="7" size="1" name="RESERVED" description="Reserved. Bit slice 7 is automatically considered a product end point." /> + <BitField start="8" size="3" name="CFG0" description="Specifies the match contribution condition for bit slice 0."> + <Enum name="CONSTANT_HIGH_THIS_" start="0x0" description="Constant HIGH. This bit slice always contributes to a product term match." /> + <Enum name="STICKY_RISING_EDGEMA" start="0x1" description="Sticky rising edgeMatch occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to." /> + <Enum name="STICKY_FALLING_EDGE_" start="0x2" description="Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to." /> + <Enum name="STICKY_RISING_OR_FAL" start="0x3" description="Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to." /> + <Enum name="HIGH_LEVEL_MATCH_F" start="0x4" description="High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register." /> + <Enum name="LOW_LEVEL_MATCH_OCC" start="0x5" description="Low level. Match occurs when there is a low level on the specified input." /> + <Enum name="CONSTANT_0_THIS_BIT" start="0x6" description="Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices)." /> + <Enum name="EVENT_NON_STICKY_RI" start="0x7" description="Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of option 3) . This bit is cleared after one clock cycle." /> + </BitField> + <BitField start="11" size="3" name="CFG1" description="Specifies the match contribution condition for bit slice 1."> + <Enum name="CONSTANT_HIGH_THIS_" start="0x0" description="Constant HIGH. This bit slice always contributes to a product term match." /> + <Enum name="STICKY_RISING_EDGEMA" start="0x1" description="Sticky rising edgeMatch occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to." /> + <Enum name="STICKY_FALLING_EDGE_" start="0x2" description="Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to." /> + <Enum name="STICKY_RISING_OR_FAL" start="0x3" description="Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to." /> + <Enum name="HIGH_LEVEL_MATCH_F" start="0x4" description="High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register." /> + <Enum name="LOW_LEVEL_MATCH_OCC" start="0x5" description="Low level. Match occurs when there is a low level on the specified input." /> + <Enum name="CONSTANT_0_THIS_BIT" start="0x6" description="Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices)." /> + <Enum name="EVENT_NON_STICKY_RI" start="0x7" description="Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of option 3) . This bit is cleared after one clock cycle." /> + </BitField> + <BitField start="14" size="3" name="CFG2" description="Specifies the match contribution condition for bit slice 2."> + <Enum name="CONSTANT_HIGH_THIS_" start="0x0" description="Constant HIGH. This bit slice always contributes to a product term match." /> + <Enum name="STICKY_RISING_EDGEMA" start="0x1" description="Sticky rising edgeMatch occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to." /> + <Enum name="STICKY_FALLING_EDGE_" start="0x2" description="Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to." /> + <Enum name="STICKY_RISING_OR_FAL" start="0x3" description="Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to." /> + <Enum name="HIGH_LEVEL_MATCH_F" start="0x4" description="High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register." /> + <Enum name="LOW_LEVEL_MATCH_OCC" start="0x5" description="Low level. Match occurs when there is a low level on the specified input." /> + <Enum name="CONSTANT_0_THIS_BIT" start="0x6" description="Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices)." /> + <Enum name="EVENT_NON_STICKY_RI" start="0x7" description="Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of option 3) . This bit is cleared after one clock cycle." /> + </BitField> + <BitField start="17" size="3" name="CFG3" description="Specifies the match contribution condition for bit slice 3."> + <Enum name="CONSTANT_HIGH_THIS_" start="0x0" description="Constant HIGH. This bit slice always contributes to a product term match." /> + <Enum name="STICKY_RISING_EDGEMA" start="0x1" description="Sticky rising edgeMatch occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to." /> + <Enum name="STICKY_FALLING_EDGE_" start="0x2" description="Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to." /> + <Enum name="STICKY_RISING_OR_FAL" start="0x3" description="Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to." /> + <Enum name="HIGH_LEVEL_MATCH_F" start="0x4" description="High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register." /> + <Enum name="LOW_LEVEL_MATCH_OCC" start="0x5" description="Low level. Match occurs when there is a low level on the specified input." /> + <Enum name="CONSTANT_0_THIS_BIT" start="0x6" description="Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices)." /> + <Enum name="EVENT_NON_STICKY_RI" start="0x7" description="Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of option 3) . This bit is cleared after one clock cycle." /> + </BitField> + <BitField start="20" size="3" name="CFG4" description="Specifies the match contribution condition for bit slice 4."> + <Enum name="CONSTANT_HIGH_THIS_" start="0x0" description="Constant HIGH. This bit slice always contributes to a product term match." /> + <Enum name="STICKY_RISING_EDGEMA" start="0x1" description="Sticky rising edgeMatch occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to." /> + <Enum name="STICKY_FALLING_EDGE_" start="0x2" description="Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to." /> + <Enum name="STICKY_RISING_OR_FAL" start="0x3" description="Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to." /> + <Enum name="HIGH_LEVEL_MATCH_F" start="0x4" description="High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register." /> + <Enum name="LOW_LEVEL_MATCH_OCC" start="0x5" description="Low level. Match occurs when there is a low level on the specified input." /> + <Enum name="CONSTANT_0_THIS_BIT" start="0x6" description="Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices)." /> + <Enum name="EVENT_NON_STICKY_RI" start="0x7" description="Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of option 3) . This bit is cleared after one clock cycle." /> + </BitField> + <BitField start="23" size="3" name="CFG5" description="Specifies the match contribution condition for bit slice 5."> + <Enum name="CONSTANT_HIGH_THIS_" start="0x0" description="Constant HIGH. This bit slice always contributes to a product term match." /> + <Enum name="STICKY_RISING_EDGEMA" start="0x1" description="Sticky rising edgeMatch occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to." /> + <Enum name="STICKY_FALLING_EDGE_" start="0x2" description="Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to." /> + <Enum name="STICKY_RISING_OR_FAL" start="0x3" description="Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to." /> + <Enum name="HIGH_LEVEL_MATCH_F" start="0x4" description="High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register." /> + <Enum name="LOW_LEVEL_MATCH_OCC" start="0x5" description="Low level. Match occurs when there is a low level on the specified input." /> + <Enum name="CONSTANT_0_THIS_BIT" start="0x6" description="Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices)." /> + <Enum name="EVENT_NON_STICKY_RI" start="0x7" description="Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of option 3) . This bit is cleared after one clock cycle." /> + </BitField> + <BitField start="26" size="3" name="CFG6" description="Specifies the match contribution condition for bit slice 6."> + <Enum name="CONSTANT_HIGH_THIS_" start="0x0" description="Constant HIGH. This bit slice always contributes to a product term match." /> + <Enum name="STICKY_RISING_EDGEMA" start="0x1" description="Sticky rising edgeMatch occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to." /> + <Enum name="STICKY_FALLING_EDGE_" start="0x2" description="Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to." /> + <Enum name="STICKY_RISING_OR_FAL" start="0x3" description="Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to." /> + <Enum name="HIGH_LEVEL_MATCH_F" start="0x4" description="High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register." /> + <Enum name="LOW_LEVEL_MATCH_OCC" start="0x5" description="Low level. Match occurs when there is a low level on the specified input." /> + <Enum name="CONSTANT_0_THIS_BIT" start="0x6" description="Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices)." /> + <Enum name="EVENT_NON_STICKY_RI" start="0x7" description="Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of option 3) . This bit is cleared after one clock cycle." /> + </BitField> + <BitField start="29" size="3" name="CFG7" description="Specifies the match contribution condition for bit slice 7."> + <Enum name="CONSTANT_HIGH_THIS_" start="0x0" description="Constant HIGH. This bit slice always contributes to a product term match." /> + <Enum name="STICKY_RISING_EDGEMA" start="0x1" description="Sticky rising edgeMatch occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to." /> + <Enum name="STICKY_FALLING_EDGE_" start="0x2" description="Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to." /> + <Enum name="STICKY_RISING_OR_FAL" start="0x3" description="Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to." /> + <Enum name="HIGH_LEVEL_MATCH_F" start="0x4" description="High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register." /> + <Enum name="LOW_LEVEL_MATCH_OCC" start="0x5" description="Low level. Match occurs when there is a low level on the specified input." /> + <Enum name="CONSTANT_0_THIS_BIT" start="0x6" description="Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices)." /> + <Enum name="EVENT_NON_STICKY_RI" start="0x7" description="Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of option 3) . This bit is cleared after one clock cycle." /> + </BitField> + </Register> + </RegisterGroup> + <RegisterGroup name="NVIC" start="0xE000E100" description="Nested Vectored Interrupt Controller"> + <Register name="NVIC_ISER0" description="Interrupt Set-Enable Register 0" start="0xE000E100"> + <BitField name="PIN_INT0" start="0" size="1" /> + <BitField name="PIN_INT1" start="1" size="1" /> + <BitField name="PIN_INT2" start="2" size="1" /> + <BitField name="PIN_INT3" start="3" size="1" /> + <BitField name="PIN_INT4" start="4" size="1" /> + <BitField name="PIN_INT5" start="5" size="1" /> + <BitField name="PIN_INT6" start="6" size="1" /> + <BitField name="PIN_INT7" start="7" size="1" /> + <BitField name="GINT0" start="8" size="1" /> + <BitField name="GINT1" start="9" size="1" /> + <BitField name="I2C1" start="10" size="1" /> + <BitField name="USART1_4" start="11" size="1" /> + <BitField name="USART2_3" start="12" size="1" /> + <BitField name="SCT0_1" start="13" size="1" /> + <BitField name="SSP1" start="14" size="1" /> + <BitField name="I2C0" start="15" size="1" /> + <BitField name="CT16B0" start="16" size="1" /> + <BitField name="CT16B1" start="17" size="1" /> + <BitField name="CT32B0" start="18" size="1" /> + <BitField name="CT32B1" start="19" size="1" /> + <BitField name="SSP0" start="20" size="1" /> + <BitField name="USART" start="21" size="1" /> + <BitField name="USB" start="22" size="1" /> + <BitField name="USB_FIQ" start="23" size="1" /> + <BitField name="ADC_A" start="24" size="1" /> + <BitField name="RTC" start="25" size="1" /> + <BitField name="BOD_WDT" start="26" size="1" /> + <BitField name="FLASH" start="27" size="1" /> + <BitField name="DMA" start="28" size="1" /> + <BitField name="USBWAKEUP" start="30" size="1" /> + </Register> + <Register name="NVIC_ICER0" description="Interrupt Clear-Enable Register 0" start="0xE000E180"> + <BitField name="PIN_INT0" start="0" size="1" /> + <BitField name="PIN_INT1" start="1" size="1" /> + <BitField name="PIN_INT2" start="2" size="1" /> + <BitField name="PIN_INT3" start="3" size="1" /> + <BitField name="PIN_INT4" start="4" size="1" /> + <BitField name="PIN_INT5" start="5" size="1" /> + <BitField name="PIN_INT6" start="6" size="1" /> + <BitField name="PIN_INT7" start="7" size="1" /> + <BitField name="GINT0" start="8" size="1" /> + <BitField name="GINT1" start="9" size="1" /> + <BitField name="I2C1" start="10" size="1" /> + <BitField name="USART1_4" start="11" size="1" /> + <BitField name="USART2_3" start="12" size="1" /> + <BitField name="SCT0_1" start="13" size="1" /> + <BitField name="SSP1" start="14" size="1" /> + <BitField name="I2C0" start="15" size="1" /> + <BitField name="CT16B0" start="16" size="1" /> + <BitField name="CT16B1" start="17" size="1" /> + <BitField name="CT32B0" start="18" size="1" /> + <BitField name="CT32B1" start="19" size="1" /> + <BitField name="SSP0" start="20" size="1" /> + <BitField name="USART" start="21" size="1" /> + <BitField name="USB" start="22" size="1" /> + <BitField name="USB_FIQ" start="23" size="1" /> + <BitField name="ADC_A" start="24" size="1" /> + <BitField name="RTC" start="25" size="1" /> + <BitField name="BOD_WDT" start="26" size="1" /> + <BitField name="FLASH" start="27" size="1" /> + <BitField name="DMA" start="28" size="1" /> + <BitField name="USBWAKEUP" start="30" size="1" /> + </Register> + <Register name="NVIC_ISPR0" description="Interrupt Set-Pending Register 0" start="0xE000E200"> + <BitField name="PIN_INT0" start="0" size="1" /> + <BitField name="PIN_INT1" start="1" size="1" /> + <BitField name="PIN_INT2" start="2" size="1" /> + <BitField name="PIN_INT3" start="3" size="1" /> + <BitField name="PIN_INT4" start="4" size="1" /> + <BitField name="PIN_INT5" start="5" size="1" /> + <BitField name="PIN_INT6" start="6" size="1" /> + <BitField name="PIN_INT7" start="7" size="1" /> + <BitField name="GINT0" start="8" size="1" /> + <BitField name="GINT1" start="9" size="1" /> + <BitField name="I2C1" start="10" size="1" /> + <BitField name="USART1_4" start="11" size="1" /> + <BitField name="USART2_3" start="12" size="1" /> + <BitField name="SCT0_1" start="13" size="1" /> + <BitField name="SSP1" start="14" size="1" /> + <BitField name="I2C0" start="15" size="1" /> + <BitField name="CT16B0" start="16" size="1" /> + <BitField name="CT16B1" start="17" size="1" /> + <BitField name="CT32B0" start="18" size="1" /> + <BitField name="CT32B1" start="19" size="1" /> + <BitField name="SSP0" start="20" size="1" /> + <BitField name="USART" start="21" size="1" /> + <BitField name="USB" start="22" size="1" /> + <BitField name="USB_FIQ" start="23" size="1" /> + <BitField name="ADC_A" start="24" size="1" /> + <BitField name="RTC" start="25" size="1" /> + <BitField name="BOD_WDT" start="26" size="1" /> + <BitField name="FLASH" start="27" size="1" /> + <BitField name="DMA" start="28" size="1" /> + <BitField name="USBWAKEUP" start="30" size="1" /> + </Register> + <Register name="NVIC_ICPR0" description="Interrupt Clear-Pending Register 0" start="0xE000E280"> + <BitField name="PIN_INT0" start="0" size="1" /> + <BitField name="PIN_INT1" start="1" size="1" /> + <BitField name="PIN_INT2" start="2" size="1" /> + <BitField name="PIN_INT3" start="3" size="1" /> + <BitField name="PIN_INT4" start="4" size="1" /> + <BitField name="PIN_INT5" start="5" size="1" /> + <BitField name="PIN_INT6" start="6" size="1" /> + <BitField name="PIN_INT7" start="7" size="1" /> + <BitField name="GINT0" start="8" size="1" /> + <BitField name="GINT1" start="9" size="1" /> + <BitField name="I2C1" start="10" size="1" /> + <BitField name="USART1_4" start="11" size="1" /> + <BitField name="USART2_3" start="12" size="1" /> + <BitField name="SCT0_1" start="13" size="1" /> + <BitField name="SSP1" start="14" size="1" /> + <BitField name="I2C0" start="15" size="1" /> + <BitField name="CT16B0" start="16" size="1" /> + <BitField name="CT16B1" start="17" size="1" /> + <BitField name="CT32B0" start="18" size="1" /> + <BitField name="CT32B1" start="19" size="1" /> + <BitField name="SSP0" start="20" size="1" /> + <BitField name="USART" start="21" size="1" /> + <BitField name="USB" start="22" size="1" /> + <BitField name="USB_FIQ" start="23" size="1" /> + <BitField name="ADC_A" start="24" size="1" /> + <BitField name="RTC" start="25" size="1" /> + <BitField name="BOD_WDT" start="26" size="1" /> + <BitField name="FLASH" start="27" size="1" /> + <BitField name="DMA" start="28" size="1" /> + <BitField name="USBWAKEUP" start="30" size="1" /> + </Register> + <Register name="NVIC_IABR0" description="Interrupt Active Bit Register 0" start="0xE000E300" access="ReadOnly"> + <BitField name="PIN_INT0" start="0" size="1" /> + <BitField name="PIN_INT1" start="1" size="1" /> + <BitField name="PIN_INT2" start="2" size="1" /> + <BitField name="PIN_INT3" start="3" size="1" /> + <BitField name="PIN_INT4" start="4" size="1" /> + <BitField name="PIN_INT5" start="5" size="1" /> + <BitField name="PIN_INT6" start="6" size="1" /> + <BitField name="PIN_INT7" start="7" size="1" /> + <BitField name="GINT0" start="8" size="1" /> + <BitField name="GINT1" start="9" size="1" /> + <BitField name="I2C1" start="10" size="1" /> + <BitField name="USART1_4" start="11" size="1" /> + <BitField name="USART2_3" start="12" size="1" /> + <BitField name="SCT0_1" start="13" size="1" /> + <BitField name="SSP1" start="14" size="1" /> + <BitField name="I2C0" start="15" size="1" /> + <BitField name="CT16B0" start="16" size="1" /> + <BitField name="CT16B1" start="17" size="1" /> + <BitField name="CT32B0" start="18" size="1" /> + <BitField name="CT32B1" start="19" size="1" /> + <BitField name="SSP0" start="20" size="1" /> + <BitField name="USART" start="21" size="1" /> + <BitField name="USB" start="22" size="1" /> + <BitField name="USB_FIQ" start="23" size="1" /> + <BitField name="ADC_A" start="24" size="1" /> + <BitField name="RTC" start="25" size="1" /> + <BitField name="BOD_WDT" start="26" size="1" /> + <BitField name="FLASH" start="27" size="1" /> + <BitField name="DMA" start="28" size="1" /> + <BitField name="USBWAKEUP" start="30" size="1" /> + </Register> + <Register name="NVIC_IPR0" description="Interrupt Priority Register 0" start="0xE000E400"> + <BitField name="PIN_INT0" start="4" size="4" /> + <BitField name="PIN_INT1" start="12" size="4" /> + <BitField name="PIN_INT2" start="20" size="4" /> + <BitField name="PIN_INT3" start="28" size="4" /> + </Register> + <Register name="NVIC_IPR1" description="Interrupt Priority Register 1" start="0xE000E404"> + <BitField name="PIN_INT4" start="4" size="4" /> + <BitField name="PIN_INT5" start="12" size="4" /> + <BitField name="PIN_INT6" start="20" size="4" /> + <BitField name="PIN_INT7" start="28" size="4" /> + </Register> + <Register name="NVIC_IPR2" description="Interrupt Priority Register 2" start="0xE000E408"> + <BitField name="GINT0" start="4" size="4" /> + <BitField name="GINT1" start="12" size="4" /> + <BitField name="I2C1" start="20" size="4" /> + <BitField name="USART1_4" start="28" size="4" /> + </Register> + <Register name="NVIC_IPR3" description="Interrupt Priority Register 3" start="0xE000E40C"> + <BitField name="USART2_3" start="4" size="4" /> + <BitField name="SCT0_1" start="12" size="4" /> + <BitField name="SSP1" start="20" size="4" /> + <BitField name="I2C0" start="28" size="4" /> + </Register> + <Register name="NVIC_IPR4" description="Interrupt Priority Register 4" start="0xE000E410"> + <BitField name="CT16B0" start="4" size="4" /> + <BitField name="CT16B1" start="12" size="4" /> + <BitField name="CT32B0" start="20" size="4" /> + <BitField name="CT32B1" start="28" size="4" /> + </Register> + <Register name="NVIC_IPR5" description="Interrupt Priority Register 5" start="0xE000E414"> + <BitField name="SSP0" start="4" size="4" /> + <BitField name="USART" start="12" size="4" /> + <BitField name="USB" start="20" size="4" /> + <BitField name="USB_FIQ" start="28" size="4" /> + </Register> + <Register name="NVIC_IPR6" description="Interrupt Priority Register 6" start="0xE000E418"> + <BitField name="ADC_A" start="4" size="4" /> + <BitField name="RTC" start="12" size="4" /> + <BitField name="BOD_WDT" start="20" size="4" /> + <BitField name="FLASH" start="28" size="4" /> + </Register> + <Register name="NVIC_IPR7" description="Interrupt Priority Register 7" start="0xE000E41C"> + <BitField name="DMA" start="4" size="4" /> + <BitField name="USBWAKEUP" start="20" size="4" /> + </Register> + </RegisterGroup> + <RegisterGroup name="SysTick" start="0xe000e010" description="24-bit System Timer"> + <Register name="SYST_CSR" start="0xe000e010" description="SysTick Control and Status Register"> + <BitField name="COUNTFLAG" start="16" size="1" description="Counter Flag" /> + <BitField name="CLKSOURCE" start="2" size="1" description="Timer Clock Source" /> + <BitField name="TICKINT" start="1" size="1" description="Tick Interrupt Enable" /> + <BitField name="ENABLE" start="0" size="1" description="Enable SysTick Timer" /> + </Register> + <Register name="SYST_RVR" start="0xe000e014" description="SysTick Reload Value Register"> + <BitField name="RELOAD" start="0" size="24" description="Value to load into the SYST_CVR when the counter is enabled and when it reaches 0" /> + </Register> + <Register name="SYST_CVR" start="0xe000e018" description="SysTick Current Value Register Register"> + <BitField name="CURRENT" start="0" size="24" description="The current value of the SysTick counter" /> + </Register> + <Register name="SYST_CALIB" start="0xe000e01c" access="ReadOnly" description="SysTick Calibration Value Register"> + <BitField name="NOREF" start="31" size="1" description="Indicates whether the device provides a reference clock to the processor" /> + <BitField name="SKEW" start="30" size="1" description="Indicates whether the TENMS value is exact" /> + <BitField name="TENMS" start="0" size="24" description="Reload value for 10ms (100Hz) timing, subject to system clock skew errors" /> + </Register> + </RegisterGroup> + <RegisterGroup name="SCB" start="0xe000e000" description="System Control Block"> + <Register name="CPUID" start="0xe000ed00" access="ReadOnly" description="CPUID Register"> + <BitField name="IMPLEMENTER" start="24" size="8" description="Implementer Code" /> + <BitField name="VARIANT" start="20" size="4" description="Variant Number" /> + <BitField name="PARTNO" start="4" size="12" description="Part Number" /> + <BitField name="REVISION" start="0" size="4" description="Revision Number" /> + </Register> + <Register name="ICSR" start="0xe000ed04" description="Interrupt Control and State Register"> + <BitField name="NMIPENDSET" start="31" size="1" description="NMI set-pending bit" /> + <BitField name="PENDSVSET" start="28" size="1" description="PendSV set-pending bit" /> + <BitField name="PENDSVCLR" start="27" size="1" description="PendSV clear-pending bit" /> + <BitField name="PENDSTSET" start="26" size="1" description="SysTick exception set-pending bit" /> + <BitField name="PENDSTCLR" start="25" size="1" description="SysTick exception clear-pending bit" /> + <BitField name="ISRPREEMPT" start="23" size="1" description="" /> + <BitField name="ISRPENDING" start="22" size="1" description="Interrupt pending flag" /> + <BitField name="VECTPENDING" start="12" size="9" description="Indicates the exception number of the highest priority pending enabled exception" /> + <BitField name="VECTACTIVE" start="0" size="9" description="Contains the active exception number" /> + </Register> + <Register name="VTOR" start="0xe000ed08" description="Vector Table Offset Register"> + <BitField name="TBLOFF" start="7" size="25" description="Vector table base offset field" /> + </Register> + <Register name="AIRCR" start="0xe000ed0c" description="Application Interrupt and Reset Control Register"> + <BitField name="VECTKEY" start="16" size="16" description="Register key" /> + <BitField name="ENDIANESS" start="15" size="1" description="Data endianness bit" /> + <BitField name="SYSRESETREQ" start="2" size="1" description="System reset request bit" /> + <BitField name="VECTCLRACTIVE" start="1" size="1" description="" /> + </Register> + <Register name="SCR" start="0xe000ed10" description="System Control Register"> + <BitField name="SEVONPEND" start="4" size="1" description="Send event on pending bit" /> + <BitField name="SLEEPDEEP" start="2" size="1" description="Controls whether the processor uses sleep or deep sleep as its low power mode" /> + <BitField name="SLEEPONEXIT" start="1" size="1" description="Indicates sleep-on-exit when returning from Handler mode to Thread mode" /> + </Register> + <Register name="CCR" start="0xe000ed14" access="ReadOnly" description="Configuration and Control Register"> + <BitField name="STKALIGN" start="9" size="1" description="Indicates stack alignment on exception entry" /> + <BitField name="UNALIGN_TRP" start="3" size="1" description="Enables unaligned access traps" /> + </Register> + <Register name="SHPR2" start="0xe000ed1c" description="System Handler Priority Register 2"> + <BitField name="PRI_11(SVCall)" start="28" size="4" description="Priority of system handler 11 (SVCall)" /> + </Register> + <Register name="SHPR3" start="0xe000ed20" description="System Handler Priority Register 3"> + <BitField name="PRI_15(SysTick)" start="28" size="4" description="Priority of system handler 15 (SysTick)" /> + <BitField name="PRI_14(PendSV)" start="20" size="4" description="Priority of system handler 14 (PendSV)" /> + </Register> + <Register name="SHCSR" start="0xE000ED24" description="System Handler Control and State Register"> + <BitField name="SVCALLPENDED" start="15" size="1" description="SVCall Pending Bit" /> + </Register> + <Register name="DFSR" start="0xE000ED30" description="Debug Fault Status Register"> + <BitField name="EXTERNAL" start="4" size="1" description="" /> + <BitField name="VCATCH" start="3" size="1" description="" /> + <BitField name="DWTTRAP" start="2" size="1" description="" /> + <BitField name="BKPT" start="1" size="1" description="" /> + <BitField name="HALTED" start="0" size="1" description="" /> + </Register> + </RegisterGroup> +</Processor> diff --git a/examples/device/cdc_msc_hid/ses/lpc11u6x/LPC11U6x_Vectors.s b/examples/device/cdc_msc_hid/ses/lpc11u6x/LPC11U6x_Vectors.s new file mode 100644 index 000000000..4d661df37 --- /dev/null +++ b/examples/device/cdc_msc_hid/ses/lpc11u6x/LPC11U6x_Vectors.s @@ -0,0 +1,405 @@ +/********************************************************************* +* SEGGER Microcontroller GmbH * +* The Embedded Experts * +********************************************************************** +* * +* (c) 2014 - 2018 SEGGER Microcontroller GmbH * +* * +* www.segger.com Support: [email protected] * +* * +********************************************************************** +* * +* All rights reserved. * +* * +* Redistribution and use in source and binary forms, with or * +* without modification, are permitted provided that the following * +* conditions are met: * +* * +* - Redistributions of source code must retain the above copyright * +* notice, this list of conditions and the following disclaimer. * +* * +* - Neither the name of SEGGER Microcontroller GmbH * +* nor the names of its contributors may be used to endorse or * +* promote products derived from this software without specific * +* prior written permission. * +* * +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND * +* CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, * +* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * +* DISCLAIMED. * +* IN NO EVENT SHALL SEGGER Microcontroller GmbH BE LIABLE FOR * +* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT * +* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * +* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF * +* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE * +* USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH * +* DAMAGE. * +* * +*********************************************************************/ + +/***************************************************************************** + * Preprocessor Definitions * + * ------------------------ * + * VECTORS_IN_RAM * + * * + * If defined, an area of RAM will large enough to store the vector table * + * will be reserved. * + * * + *****************************************************************************/ + + .syntax unified + .code 16 + + .section .init, "ax" + .align 2 + +/***************************************************************************** + * Default Exception Handlers * + *****************************************************************************/ + + .thumb_func + .weak NMI_Handler +NMI_Handler: + b . + + .thumb_func + .weak HardFault_Handler +HardFault_Handler: + b . + + .thumb_func + .weak SVC_Handler +SVC_Handler: + b . + + .thumb_func + .weak PendSV_Handler +PendSV_Handler: + b . + + .thumb_func + .weak SysTick_Handler +SysTick_Handler: + b . + + .thumb_func +Dummy_Handler: + b . + +#if defined(__OPTIMIZATION_SMALL) + + .weak PIN_INT0_IRQHandler + .thumb_set PIN_INT0_IRQHandler,Dummy_Handler + + .weak PIN_INT1_IRQHandler + .thumb_set PIN_INT1_IRQHandler,Dummy_Handler + + .weak PIN_INT2_IRQHandler + .thumb_set PIN_INT2_IRQHandler,Dummy_Handler + + .weak PIN_INT3_IRQHandler + .thumb_set PIN_INT3_IRQHandler,Dummy_Handler + + .weak PIN_INT4_IRQHandler + .thumb_set PIN_INT4_IRQHandler,Dummy_Handler + + .weak PIN_INT5_IRQHandler + .thumb_set PIN_INT5_IRQHandler,Dummy_Handler + + .weak PIN_INT6_IRQHandler + .thumb_set PIN_INT6_IRQHandler,Dummy_Handler + + .weak PIN_INT7_IRQHandler + .thumb_set PIN_INT7_IRQHandler,Dummy_Handler + + .weak GINT0_IRQHandler + .thumb_set GINT0_IRQHandler,Dummy_Handler + + .weak GINT1_IRQHandler + .thumb_set GINT1_IRQHandler,Dummy_Handler + + .weak I2C1_IRQHandler + .thumb_set I2C1_IRQHandler,Dummy_Handler + + .weak USART1_4_IRQHandler + .thumb_set USART1_4_IRQHandler,Dummy_Handler + + .weak USART2_3_IRQHandler + .thumb_set USART2_3_IRQHandler,Dummy_Handler + + .weak SCT0_1_IRQHandler + .thumb_set SCT0_1_IRQHandler,Dummy_Handler + + .weak SSP1_IRQHandler + .thumb_set SSP1_IRQHandler,Dummy_Handler + + .weak I2C0_IRQHandler + .thumb_set I2C0_IRQHandler,Dummy_Handler + + .weak CT16B0_IRQHandler + .thumb_set CT16B0_IRQHandler,Dummy_Handler + + .weak CT16B1_IRQHandler + .thumb_set CT16B1_IRQHandler,Dummy_Handler + + .weak CT32B0_IRQHandler + .thumb_set CT32B0_IRQHandler,Dummy_Handler + + .weak CT32B1_IRQHandler + .thumb_set CT32B1_IRQHandler,Dummy_Handler + + .weak SSP0_IRQHandler + .thumb_set SSP0_IRQHandler,Dummy_Handler + + .weak USART_IRQHandler + .thumb_set USART_IRQHandler,Dummy_Handler + + .weak USB_IRQHandler + .thumb_set USB_IRQHandler,Dummy_Handler + + .weak USB_FIQ_IRQHandler + .thumb_set USB_FIQ_IRQHandler,Dummy_Handler + + .weak ADC_A_IRQHandler + .thumb_set ADC_A_IRQHandler,Dummy_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Dummy_Handler + + .weak BOD_WDT_IRQHandler + .thumb_set BOD_WDT_IRQHandler,Dummy_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Dummy_Handler + + .weak DMA_IRQHandler + .thumb_set DMA_IRQHandler,Dummy_Handler + + .weak USBWAKEUP_IRQHandler + .thumb_set USBWAKEUP_IRQHandler,Dummy_Handler + +#else + + .thumb_func + .weak PIN_INT0_IRQHandler +PIN_INT0_IRQHandler: + b . + + .thumb_func + .weak PIN_INT1_IRQHandler +PIN_INT1_IRQHandler: + b . + + .thumb_func + .weak PIN_INT2_IRQHandler +PIN_INT2_IRQHandler: + b . + + .thumb_func + .weak PIN_INT3_IRQHandler +PIN_INT3_IRQHandler: + b . + + .thumb_func + .weak PIN_INT4_IRQHandler +PIN_INT4_IRQHandler: + b . + + .thumb_func + .weak PIN_INT5_IRQHandler +PIN_INT5_IRQHandler: + b . + + .thumb_func + .weak PIN_INT6_IRQHandler +PIN_INT6_IRQHandler: + b . + + .thumb_func + .weak PIN_INT7_IRQHandler +PIN_INT7_IRQHandler: + b . + + .thumb_func + .weak GINT0_IRQHandler +GINT0_IRQHandler: + b . + + .thumb_func + .weak GINT1_IRQHandler +GINT1_IRQHandler: + b . + + .thumb_func + .weak I2C1_IRQHandler +I2C1_IRQHandler: + b . + + .thumb_func + .weak USART1_4_IRQHandler +USART1_4_IRQHandler: + b . + + .thumb_func + .weak USART2_3_IRQHandler +USART2_3_IRQHandler: + b . + + .thumb_func + .weak SCT0_1_IRQHandler +SCT0_1_IRQHandler: + b . + + .thumb_func + .weak SSP1_IRQHandler +SSP1_IRQHandler: + b . + + .thumb_func + .weak I2C0_IRQHandler +I2C0_IRQHandler: + b . + + .thumb_func + .weak CT16B0_IRQHandler +CT16B0_IRQHandler: + b . + + .thumb_func + .weak CT16B1_IRQHandler +CT16B1_IRQHandler: + b . + + .thumb_func + .weak CT32B0_IRQHandler +CT32B0_IRQHandler: + b . + + .thumb_func + .weak CT32B1_IRQHandler +CT32B1_IRQHandler: + b . + + .thumb_func + .weak SSP0_IRQHandler +SSP0_IRQHandler: + b . + + .thumb_func + .weak USART_IRQHandler +USART_IRQHandler: + b . + + .thumb_func + .weak USB_IRQHandler +USB_IRQHandler: + b . + + .thumb_func + .weak USB_FIQ_IRQHandler +USB_FIQ_IRQHandler: + b . + + .thumb_func + .weak ADC_A_IRQHandler +ADC_A_IRQHandler: + b . + + .thumb_func + .weak RTC_IRQHandler +RTC_IRQHandler: + b . + + .thumb_func + .weak BOD_WDT_IRQHandler +BOD_WDT_IRQHandler: + b . + + .thumb_func + .weak FLASH_IRQHandler +FLASH_IRQHandler: + b . + + .thumb_func + .weak DMA_IRQHandler +DMA_IRQHandler: + b . + + .thumb_func + .weak USBWAKEUP_IRQHandler +USBWAKEUP_IRQHandler: + b . + +#endif + +/***************************************************************************** + * Vector Table * + *****************************************************************************/ + + .section .vectors, "ax" + .align 2 + .global _vectors + .extern __stack_end__ + .extern Reset_Handler + +_vectors: + .word __stack_end__ + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word SVC_Handler + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word PendSV_Handler + .word SysTick_Handler + .word PIN_INT0_IRQHandler + .word PIN_INT1_IRQHandler + .word PIN_INT2_IRQHandler + .word PIN_INT3_IRQHandler + .word PIN_INT4_IRQHandler + .word PIN_INT5_IRQHandler + .word PIN_INT6_IRQHandler + .word PIN_INT7_IRQHandler + .word GINT0_IRQHandler + .word GINT1_IRQHandler + .word I2C1_IRQHandler + .word USART1_4_IRQHandler + .word USART2_3_IRQHandler + .word SCT0_1_IRQHandler + .word SSP1_IRQHandler + .word I2C0_IRQHandler + .word CT16B0_IRQHandler + .word CT16B1_IRQHandler + .word CT32B0_IRQHandler + .word CT32B1_IRQHandler + .word SSP0_IRQHandler + .word USART_IRQHandler + .word USB_IRQHandler + .word USB_FIQ_IRQHandler + .word ADC_A_IRQHandler + .word RTC_IRQHandler + .word BOD_WDT_IRQHandler + .word FLASH_IRQHandler + .word DMA_IRQHandler + .word Dummy_Handler /* Reserved */ + .word USBWAKEUP_IRQHandler +_vectors_end: + +#ifdef VECTORS_IN_RAM + .section .vectors_ram, "ax" + .align 2 + .global _vectors_ram + +_vectors_ram: + .space _vectors_end - _vectors, 0 +#endif diff --git a/examples/device/cdc_msc_hid/ses/lpc11u6x/flash_placement.xml b/examples/device/cdc_msc_hid/ses/lpc11u6x/flash_placement.xml new file mode 100644 index 000000000..27a63d5be --- /dev/null +++ b/examples/device/cdc_msc_hid/ses/lpc11u6x/flash_placement.xml @@ -0,0 +1,41 @@ +<!DOCTYPE Linker_Placement_File> +<Root name="Flash Section Placement"> + <MemorySegment name="$(FLASH_NAME:FLASH)"> + <ProgramSection alignment="0x100" load="Yes" name=".vectors" start="$(FLASH_START:)" /> + <ProgramSection alignment="4" load="Yes" name=".init" /> + <ProgramSection alignment="4" load="Yes" name=".init_rodata" /> + <ProgramSection alignment="4" load="Yes" name=".text" /> + <ProgramSection alignment="4" load="Yes" name=".dtors" /> + <ProgramSection alignment="4" load="Yes" name=".ctors" /> + <ProgramSection alignment="4" load="Yes" name=".rodata" /> + <ProgramSection alignment="4" load="Yes" name=".ARM.exidx" address_symbol="__exidx_start" end_symbol="__exidx_end" /> + <ProgramSection alignment="4" load="Yes" runin=".fast_run" name=".fast" /> + <ProgramSection alignment="4" load="Yes" runin=".data_run" name=".data" /> + <ProgramSection alignment="4" load="Yes" runin=".tdata_run" name=".tdata" /> + </MemorySegment> + <MemorySegment name="$(RAM_NAME:RAM);SRAM"> + <ProgramSection alignment="0x100" load="No" name=".vectors_ram" start="$(RAM_START:$(SRAM_START:))" /> + <ProgramSection alignment="4" load="No" name=".fast_run" /> + <ProgramSection alignment="4" load="No" name=".data_run" /> + <ProgramSection alignment="4" load="No" name=".bss" /> + <ProgramSection alignment="4" load="No" name=".tbss" /> + <ProgramSection alignment="4" load="No" name=".tdata_run" /> + <ProgramSection alignment="4" load="No" name=".non_init" /> + <ProgramSection alignment="4" size="__HEAPSIZE__" load="No" name=".heap" /> + <ProgramSection alignment="8" size="__STACKSIZE__" load="No" place_from_segment_end="Yes" name=".stack" /> + <ProgramSection alignment="8" size="__STACKSIZE_PROCESS__" load="No" name=".stack_process" /> + </MemorySegment> + <MemorySegment name="$(FLASH2_NAME:FLASH2)"> + <ProgramSection alignment="4" load="Yes" name=".text2" /> + <ProgramSection alignment="4" load="Yes" name=".rodata2" /> + <ProgramSection alignment="4" load="Yes" runin=".data2_run" name=".data2" /> + </MemorySegment> + <MemorySegment name="$(RAM2_NAME:RAM2)"> + <ProgramSection alignment="4" load="No" name=".data2_run" /> + <ProgramSection alignment="4" load="No" name=".bss2" /> + </MemorySegment> + <MemorySegment name="$(RAM3_NAME:RAM3)"> + <ProgramSection alignment="4" load="No" name=".data3_run" /> + <ProgramSection alignment="4" load="No" name=".bss3" /> + </MemorySegment> +</Root> diff --git a/examples/device/cdc_msc_hid/ses/lpc11u6x/lpc11u6x.emProject b/examples/device/cdc_msc_hid/ses/lpc11u6x/lpc11u6x.emProject new file mode 100644 index 000000000..a85a42eab --- /dev/null +++ b/examples/device/cdc_msc_hid/ses/lpc11u6x/lpc11u6x.emProject @@ -0,0 +1,124 @@ +<!DOCTYPE CrossStudio_Project_File> +<solution Name="lpc11u6x" target="8" version="2"> + <project Name="lpc11u6x"> + <configuration + CMSIS_CORE="Yes" + Name="Common" + Placement="Flash" + Target="LPC11U68" + arm_architecture="v6M" + arm_core_type="Cortex-M0+" + arm_endian="Little" + arm_fpu_type="None" + arm_interwork="No" + arm_linker_heap_size="256" + arm_linker_process_stack_size="0" + arm_linker_stack_size="256" + arm_simulator_memory_simulation_parameter="ROM;0x00000000;0x00040000;RAM;0x10000000;0x00008000;RAM;0x20000000;0x00000800" + arm_target_debug_interface_type="ADIv5" + arm_target_device_name="LPC11U68" + arm_target_interface_type="SWD" + build_treat_warnings_as_errors="Yes" + c_preprocessor_definitions="__LPC11U68__;__LPC1100_FAMILY;__LPC11U00_SUBFAMILY;ARM_MATH_CM0PLUS;FLASH_PLACEMENT=1;CORE_M0PLUS;BOARD_LPCXPRESSO11U68;CFG_TUSB_MCU=OPT_MCU_LPC11UXX;CFG_TUSB_MEM_SECTION= __attribute__((section(".bss3")));CFG_TUSB_MEM_ALIGN=__attribute__ ((aligned(64)))" + c_user_include_directories="../../src;$(rootDir)/hw;$(rootDir)/src;$(lpcDir)/inc" + debug_register_definition_file="$(ProjectDir)/LPC11U6x_Registers.xml" + debug_target_connection="J-Link" + gcc_enable_all_warnings="Yes" + gcc_entry_point="Reset_Handler" + linker_memory_map_file="$(ProjectDir)/LPC11U68_MemoryMap.xml" + linker_section_placement_file="$(ProjectDir)/flash_placement.xml" + macros="DeviceFamily=LPC1100;DeviceSubFamily=LPC11U00;Target=LPC11U68;Placement=Flash;rootDir=../../../../..;lpcDir=../../../../../hw/mcu/nxp/lpc_chip_11u6x" + project_directory="" + project_type="Executable" + target_reset_script="Reset();" + target_script_file="$(ProjectDir)/LPC1100_Target.js" + target_trace_initialize_script="EnableTrace("$(TraceInterfaceType)")" /> + <folder Name="System Files"> + <file file_name="thumb_crt0.s" /> + <file file_name="LPC1100_Startup.s" /> + <file file_name="LPC11U6x_Vectors.s"> + <configuration Name="Common" file_type="Assembly" /> + </file> + <file file_name="LPC1100_Target.js"> + <configuration Name="Common" file_type="Reset Script" /> + </file> + <file file_name="LPC11U68_MemoryMap.xml" /> + <file file_name="flash_placement.xml" /> + </folder> + <configuration + Name="LPCXpresso 11U68" + link_use_linker_script_file="No" + linker_section_placement_file="flash_placement.xml" /> + <folder Name="hw"> + <folder Name="bsp"> + <file file_name="../../../../../hw/bsp/ansi_escape.h" /> + <file file_name="../../../../../hw/bsp/board.h" /> + <folder + Name="lpcxpresso11u68" + exclude="" + filter="*.*" + path="../../../../../hw/bsp/lpcxpresso11u68" + recurse="No" /> + </folder> + <folder Name="mcu"> + <folder Name="nxp"> + <folder Name="lpc_chip_11u6x"> + <folder Name="inc"> + <file file_name="../../../../../hw/mcu/nxp/lpc_chip_11u6x/inc/chip.h" /> + <file file_name="../../../../../hw/mcu/nxp/lpc_chip_11u6x/inc/clock_11u6x.h" /> + <file file_name="../../../../../hw/mcu/nxp/lpc_chip_11u6x/inc/cmsis.h" /> + <file file_name="../../../../../hw/mcu/nxp/lpc_chip_11u6x/inc/core_cm0.h" /> + <file file_name="../../../../../hw/mcu/nxp/lpc_chip_11u6x/inc/core_cm0plus.h" /> + <file file_name="../../../../../hw/mcu/nxp/lpc_chip_11u6x/inc/core_cm3.h" /> + <file file_name="../../../../../hw/mcu/nxp/lpc_chip_11u6x/inc/core_cm4.h" /> + <file file_name="../../../../../hw/mcu/nxp/lpc_chip_11u6x/inc/core_cm4_simd.h" /> + <file file_name="../../../../../hw/mcu/nxp/lpc_chip_11u6x/inc/core_cmFunc.h" /> + <file file_name="../../../../../hw/mcu/nxp/lpc_chip_11u6x/inc/core_cmInstr.h" /> + <file file_name="../../../../../hw/mcu/nxp/lpc_chip_11u6x/inc/error.h" /> + <file file_name="../../../../../hw/mcu/nxp/lpc_chip_11u6x/inc/gpio_11u6x.h" /> + <file file_name="../../../../../hw/mcu/nxp/lpc_chip_11u6x/inc/gpiogroup_11u6x.h" /> + <file file_name="../../../../../hw/mcu/nxp/lpc_chip_11u6x/inc/iocon_11u6x.h" /> + <file file_name="../../../../../hw/mcu/nxp/lpc_chip_11u6x/inc/lpc_types.h" /> + <file file_name="../../../../../hw/mcu/nxp/lpc_chip_11u6x/inc/sys_config.h" /> + <file file_name="../../../../../hw/mcu/nxp/lpc_chip_11u6x/inc/syscon_11u6x.h" /> + <file file_name="../../../../../hw/mcu/nxp/lpc_chip_11u6x/inc/uart_0_11u6x.h" /> + <file file_name="../../../../../hw/mcu/nxp/lpc_chip_11u6x/inc/usbd_11u6x.h" /> + </folder> + <folder Name="src"> + <file file_name="../../../../../hw/mcu/nxp/lpc_chip_11u6x/src/chip_11u6x.c" /> + <file file_name="../../../../../hw/mcu/nxp/lpc_chip_11u6x/src/clock_11u6x.c" /> + <file file_name="../../../../../hw/mcu/nxp/lpc_chip_11u6x/src/gpio_11u6x.c" /> + <file file_name="../../../../../hw/mcu/nxp/lpc_chip_11u6x/src/syscon_11u6x.c" /> + <file file_name="../../../../../hw/mcu/nxp/lpc_chip_11u6x/src/sysinit_11u6x.c" /> + <file file_name="../../../../../hw/mcu/nxp/lpc_chip_11u6x/src/uart_0_11u6x.c" /> + <file file_name="../../../../../hw/mcu/nxp/lpc_chip_11u6x/src/iocon_11u6x.c" /> + </folder> + </folder> + </folder> + </folder> + </folder> + <folder + Name="segger_rtt" + exclude="" + filter="*.c;*.h" + path="../../../../../lib/segger_rtt" + recurse="No" /> + <folder + Name="src" + exclude="" + filter="*.c;*.h" + path="../../src" + recurse="Yes" /> + <folder + Name="tinyusb" + exclude="" + filter="*.c;*.h" + path="../../../../../src" + recurse="Yes" /> + </project> + <configuration + Name="LPCXpresso 11U68" + c_preprocessor_definitions="DEBUG" + gcc_debugging_level="Level 3" + gcc_optimization_level="None" /> +</solution> diff --git a/examples/device/device_virtual_com/segger/thumb_crt0.s b/examples/device/cdc_msc_hid/ses/lpc11u6x/thumb_crt0.s index 71820cb51..17f88e0ca 100644 --- a/examples/device/device_virtual_com/segger/thumb_crt0.s +++ b/examples/device/cdc_msc_hid/ses/lpc11u6x/thumb_crt0.s @@ -1,13 +1,45 @@ -// SEGGER Embedded Studio, runtime support. -// -// Copyright (c) 2014-2017 SEGGER Microcontroller GmbH & Co KG -// Copyright (c) 2001-2017 Rowley Associates Limited. -// -// This file may be distributed under the terms of the License Agreement -// provided with this software. -// -// THIS FILE IS PROVIDED AS IS WITH NO WARRANTY OF ANY KIND, INCLUDING THE -// WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. +// ********************************************************************** +// * SEGGER Microcontroller GmbH * +// * The Embedded Experts * +// ********************************************************************** +// * * +// * (c) 2014 - 2018 SEGGER Microcontroller GmbH * +// * (c) 2001 - 2018 Rowley Associates Limited * +// * * +// * www.segger.com Support: [email protected] * +// * * +// ********************************************************************** +// * * +// * All rights reserved. * +// * * +// * Redistribution and use in source and binary forms, with or * +// * without modification, are permitted provided that the following * +// * conditions are met: * +// * * +// * - Redistributions of source code must retain the above copyright * +// * notice, this list of conditions and the following disclaimer. * +// * * +// * - Neither the name of SEGGER Microcontroller GmbH * +// * nor the names of its contributors may be used to endorse or * +// * promote products derived from this software without specific * +// * prior written permission. * +// * * +// * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND * +// * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, * +// * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * +// * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * +// * DISCLAIMED. * +// * IN NO EVENT SHALL SEGGER Microcontroller GmbH BE LIABLE FOR * +// * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * +// * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT * +// * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * +// * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF * +// * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * +// * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE * +// * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH * +// * DAMAGE. * +// * * +// ********************************************************************** // // // Preprocessor Definitions @@ -69,7 +101,7 @@ .section .init, "ax" .code 16 - .align 2 + .balign 2 .thumb_func _start: @@ -303,6 +335,7 @@ memory_set: .macro HELPER helper_name .section .text.\helper_name, "ax", %progbits + .balign 2 .global \helper_name .weak \helper_name \helper_name: @@ -324,50 +357,12 @@ memory_set: HELPER __aeabi_read_tp ldr r0, =__tbss_start__-8 bx lr -HELPER __heap_lock - bx lr -HELPER __heap_unlock - bx lr -HELPER __printf_lock - bx lr -HELPER __printf_unlock - bx lr -HELPER __scanf_lock - bx lr -HELPER __scanf_unlock - bx lr -HELPER __debug_io_lock - bx lr -HELPER __debug_io_unlock - bx lr HELPER abort b . HELPER __assert b . HELPER __aeabi_assert b . -HELPER __cxa_pure_virtual - b . -HELPER __cxa_guard_acquire - ldr r3, [r0] -#if defined(__thumb__) && !defined(__thumb2__) - movs r0, #1 - tst r3, r0 -#else - tst r3, #1 -#endif - beq 1f - movs r0, #0 - bx lr -1: - movs r0, #1 - bx lr -HELPER __cxa_guard_release - movs r3, #1 - str r3, [r0] - bx lr -HELPER __cxa_guard_abort - bx lr HELPER __sync_synchronize bx lr HELPER __getchar diff --git a/examples/device/cdc_msc_hid/ses/lpc13xx/LPC1300_Startup.s b/examples/device/cdc_msc_hid/ses/lpc13xx/LPC1300_Startup.s new file mode 100644 index 000000000..ad41afb99 --- /dev/null +++ b/examples/device/cdc_msc_hid/ses/lpc13xx/LPC1300_Startup.s @@ -0,0 +1,113 @@ +/***************************************************************************** + * SEGGER Microcontroller GmbH & Co. KG * + * Solutions for real time microcontroller applications * + ***************************************************************************** + * * + * (c) 2017 SEGGER Microcontroller GmbH & Co. KG * + * * + * Internet: www.segger.com Support: [email protected] * + * * + *****************************************************************************/ + +/***************************************************************************** + * Preprocessor Definitions * + * ------------------------ * + * NO_STACK_INIT * + * * + * If defined, the stack pointer will not be initialised. * + * * + * NO_SYSTEM_INIT * + * * + * If defined, the SystemInit() function will not be called. By default * + * SystemInit() is called after reset to enable the clocks and memories to * + * be initialised prior to any C startup initialisation. * + * * + * NO_VTOR_CONFIG * + * * + * If defined, the vector table offset register will not be configured. * + * * + * MEMORY_INIT * + * * + * If defined, the MemoryInit() function will be called. By default * + * MemoryInit() is called after SystemInit() to enable an external memory * + * controller. * + * * + * STACK_INIT_VAL * + * * + * If defined, specifies the initial stack pointer value. If undefined, * + * the stack pointer will be initialised to point to the end of the * + * RAM segment. * + * * + * VECTORS_IN_RAM * + * * + * If defined, the exception vectors will be copied from Flash to RAM. * + * * + *****************************************************************************/ + + .syntax unified + + .global Reset_Handler + .extern _vectors + + .section .init, "ax" + .thumb_func + + .equ VTOR_REG, 0xE000ED08 + +#ifndef STACK_INIT_VAL +#define STACK_INIT_VAL __RAM_segment_end__ +#endif + +Reset_Handler: +#ifndef NO_STACK_INIT + /* Initialise main stack */ + ldr r0, =STACK_INIT_VAL + bic r0, #0x7 + mov sp, r0 +#endif + +#ifndef NO_SYSTEM_INIT + /* Initialise system */ + ldr r0, =SystemInit + blx r0 + .pushsection .init_array, "aw", %init_array + .word SystemCoreClockUpdate + .popsection +#endif + +#ifdef MEMORY_INIT + ldr r0, =MemoryInit + blx r0 +#endif + +#ifdef VECTORS_IN_RAM + /* Copy exception vectors into RAM */ + ldr r0, =__vectors_start__ + ldr r1, =__vectors_end__ + ldr r2, =__vectors_ram_start__ +1: + cmp r0, r1 + beq 2f + ldr r3, [r0] + str r3, [r2] + adds r0, r0, #4 + adds r2, r2, #4 + b 1b +2: +#endif + +#ifndef NO_VTOR_CONFIG + /* Configure vector table offset register */ + ldr r0, =VTOR_REG +#ifdef VECTORS_IN_RAM + ldr r1, =_vectors_ram +#else + ldr r1, =_vectors +#endif + str r1, [r0] +#endif + + /* Jump to program start */ + b _start + + diff --git a/examples/device/device_virtual_com/segger/LPC4300_Target.js b/examples/device/cdc_msc_hid/ses/lpc13xx/LPC1300_Target.js index 20560af43..20560af43 100644 --- a/examples/device/device_virtual_com/segger/LPC4300_Target.js +++ b/examples/device/cdc_msc_hid/ses/lpc13xx/LPC1300_Target.js diff --git a/examples/device/cdc_msc_hid/ses/lpc13xx/LPC1347FBD64_MemoryMap.xml b/examples/device/cdc_msc_hid/ses/lpc13xx/LPC1347FBD64_MemoryMap.xml new file mode 100644 index 000000000..298645289 --- /dev/null +++ b/examples/device/cdc_msc_hid/ses/lpc13xx/LPC1347FBD64_MemoryMap.xml @@ -0,0 +1,7 @@ +<!DOCTYPE Board_Memory_Definition_File> +<root name="LPC1347FBD64"> + <MemorySegment name="FLASH" start="0x00000000" size="0x00010000" access="ReadOnly" /> + <MemorySegment name="RAM" start="0x10000000" size="0x00002000" access="Read/Write" /> + <MemorySegment name="RAM2" start="0x20000000" size="0x00000800" access="Read/Write" /> + <MemorySegment name="RAM3" start="0x20004000" size="0x00000800" access="Read/Write" /> +</root> diff --git a/examples/device/cdc_msc_hid/ses/lpc13xx/LPC13Uxx_Registers.xml b/examples/device/cdc_msc_hid/ses/lpc13xx/LPC13Uxx_Registers.xml new file mode 100644 index 000000000..0f605ce04 --- /dev/null +++ b/examples/device/cdc_msc_hid/ses/lpc13xx/LPC13Uxx_Registers.xml @@ -0,0 +1,5515 @@ +<!DOCTYPE Register_Definition_File> +<Processor name="LPC13Uxx" description="LPC1315/16/17/35/36/37 Cortex-M3 MCU; up to 64 kB flash; up to 12 kB SRAM; USB device; USART; EEPROM"> + <RegisterGroup name="I2C" start="0x40000000" description="I2C"> + <Register start="+0x000" size="4" name="CONSET" access="Read/Write" description="I2C Control Set Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is set. Writing a zero has no effect on the corresponding bit in the I2C control register." reset_value="0x00" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + <BitField start="2" size="1" name="AA" description="Assert acknowledge flag." /> + <BitField start="3" size="1" name="SI" description="I2C interrupt flag." /> + <BitField start="4" size="1" name="STO" description="STOP flag." /> + <BitField start="5" size="1" name="STA" description="START flag." /> + <BitField start="6" size="1" name="I2EN" description="I2C interface enable." /> + <BitField start="7" size="25" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x004" size="4" name="STAT" access="ReadOnly" description="I2C Status Register. During I2C operation, this register provides detailed status codes that allow software to determine the next action needed." reset_value="0xF8" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="RESERVED" description="These bits are unused and are always 0." /> + <BitField start="3" size="5" name="Status" description="These bits give the actual status information about the I2C interface." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x008" size="4" name="DAT" access="Read/Write" description="I2C Data Register. During master or slave transmit mode, data to be transmitted is written to this register. During master or slave receive mode, data that has been received may be read from this register." reset_value="0x00" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="Data" description="This register holds data values that have been received or are to be transmitted." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x00C" size="4" name="ADR0" access="Read/Write" description="I2C Slave Address Register 0. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="GC" description="General Call enable bit." /> + <BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x010" size="4" name="SCLH" access="Read/Write" description="SCH Duty Cycle Register High Half Word. Determines the high time of the I2C clock." reset_value="0x04" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="16" name="SCLH" description="Count for SCL HIGH time period selection." /> + <BitField start="16" size="16" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x014" size="4" name="SCLL" access="Read/Write" description="SCL Duty Cycle Register Low Half Word. Determines the low time of the I2C clock. I2nSCLL and I2nSCLH together determine the clock frequency generated by an I2C master and certain times used in slave mode." reset_value="0x04" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="16" name="SCLL" description="Count for SCL low time period selection." /> + <BitField start="16" size="16" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x018" size="4" name="CONCLR" access="WriteOnly" description="I2C Control Clear Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is cleared. Writing a zero has no effect on the corresponding bit in the I2C control register." reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="2" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + <BitField start="2" size="1" name="AAC" description="Assert acknowledge Clear bit." /> + <BitField start="3" size="1" name="SIC" description="I2C interrupt Clear bit." /> + <BitField start="4" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + <BitField start="5" size="1" name="STAC" description="START flag Clear bit." /> + <BitField start="6" size="1" name="I2ENC" description="I2C interface Disable bit." /> + <BitField start="7" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x01C" size="4" name="MMCTRL" access="Read/Write" description="Monitor mode control register." reset_value="0x00" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="MM_ENA" description="Monitor mode enable."> + <Enum name="MONITOR_MODE_DISABLE" start="0" description="Monitor mode disabled." /> + <Enum name="THE_I2C_MODULE_WILL_" start="1" description="The I2C module will enter monitor mode. In this mode the SDA output will be forced high. This will prevent the I2C module from outputting data of any kind (including ACK) onto the I 2C data bus. Depending on the state of the ENA_SCL bit, the output may be also forced high, preventing the module from having control over the I2C clock line." /> + </BitField> + <BitField start="1" size="1" name="ENA_SCL" description="SCL output enable."> + <Enum name="HIGH" start="0" description="When this bit is cleared to 0, the SCL output will be forced high when the module is in monitor mode. As described above, this will prevent the module from having any control over the I2C clock line." /> + <Enum name="NORMAL" start="1" description="When this bit is set, the I2C module may exercise the same control over the clock line that it would in normal operation. This means that, acting as a slave peripheral, the I2C module can stretch the clock line (hold it low) until it has had time to respond to an I2C interrupt.[1]" /> + </BitField> + <BitField start="2" size="1" name="MATCH_ALL" description="Select interrupt register match."> + <Enum name="MATCH" start="0" description="When this bit is cleared, an interrupt will only be generated when a match occurs to one of the (up-to) four address registers described above. That is, the module will respond as a normal slave as far as address-recognition is concerned." /> + <Enum name="ANYADDRESS" start="1" description="When this bit is set to 1 and the I2C is in monitor mode, an interrupt will be generated on ANY address received. This will enable the part to monitor all traffic on the bus." /> + </BitField> + <BitField start="3" size="29" name="RESERVED" description="Reserved. The value read from reserved bits is not defined." /> + </Register> + <Register start="+0x020+0" size="4" name="ADR1" access="Read/Write" description="I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="GC" description="General Call enable bit." /> + <BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x020+4" size="4" name="ADR2" access="Read/Write" description="I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="GC" description="General Call enable bit." /> + <BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x020+8" size="4" name="ADR3" access="Read/Write" description="I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="GC" description="General Call enable bit." /> + <BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x02C" size="4" name="DATA_BUFFER" access="ReadOnly" description="Data buffer register. The contents of the 8 MSBs of the I2DAT shift register will be transferred to the DATA_BUFFER automatically after every nine bits (8 bits of data plus ACK or NACK) has been received on the bus." reset_value="0x00" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="Data" description="This register holds contents of the 8 MSBs of the DAT shift register." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x030+0" size="4" name="MASK0" access="Read/Write" description="I2C Slave address mask register. This mask register is associated with I2ADR0 to determine an address match. The mask register has no effect when comparing to the General Call address (0000000)." reset_value="0x00" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." /> + <BitField start="1" size="7" name="MASK" description="Mask bits." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from reserved bits is undefined." /> + </Register> + <Register start="+0x030+4" size="4" name="MASK1" access="Read/Write" description="I2C Slave address mask register. This mask register is associated with I2ADR0 to determine an address match. The mask register has no effect when comparing to the General Call address (0000000)." reset_value="0x00" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." /> + <BitField start="1" size="7" name="MASK" description="Mask bits." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from reserved bits is undefined." /> + </Register> + <Register start="+0x030+8" size="4" name="MASK2" access="Read/Write" description="I2C Slave address mask register. This mask register is associated with I2ADR0 to determine an address match. The mask register has no effect when comparing to the General Call address (0000000)." reset_value="0x00" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." /> + <BitField start="1" size="7" name="MASK" description="Mask bits." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from reserved bits is undefined." /> + </Register> + <Register start="+0x030+12" size="4" name="MASK3" access="Read/Write" description="I2C Slave address mask register. This mask register is associated with I2ADR0 to determine an address match. The mask register has no effect when comparing to the General Call address (0000000)." reset_value="0x00" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." /> + <BitField start="1" size="7" name="MASK" description="Mask bits." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from reserved bits is undefined." /> + </Register> + </RegisterGroup> + <RegisterGroup name="WWDT" start="0x40004000" description="Windowed Watchdog Timer (WWDT) "> + <Register start="+0x000" size="4" name="MOD" access="Read/Write" description="Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="WDEN" description="Watchdog enable bit. Once this bit has been written with a 1 it cannot be rewritten with a 0."> + <Enum name="STOPPED" start="0" description="The watchdog timer is stopped." /> + <Enum name="RUNNING" start="1" description="The watchdog timer is running." /> + </BitField> + <BitField start="1" size="1" name="WDRESET" description="Watchdog reset enable bit. Once this bit has been written with a 1 it cannot be rewritten with a 0."> + <Enum name="INTERRUPT" start="0" description="A watchdog timeout will not cause a chip reset." /> + <Enum name="RESET" start="1" description="A watchdog timeout will cause a chip reset." /> + </BitField> + <BitField start="2" size="1" name="WDTOF" description="Watchdog time-out flag. Set when the watchdog timer times out, by a feed error, or by events associated with WDPROTECT. Cleared by software. Causes a chip reset if WDRESET = 1." /> + <BitField start="3" size="1" name="WDINT" description="Warning interrupt flag. Set when the timer reaches the value in WDWARNINT. Cleared by software." /> + <BitField start="4" size="1" name="WDPROTECT" description="Watchdog update mode. This bit can be set once by software and is only cleared by a reset."> + <Enum name="NOT_LOCKED" start="0" description="The watchdog time-out value (TC) can be changed at any time." /> + <Enum name="LOCKED" start="1" description="The watchdog time-out value (TC) can be changed only after the counter is below the value of WDWARNINT and WDWINDOW." /> + </BitField> + <BitField start="5" size="1" name="LOCK" description="A 1 in this bit prevents disabling or powering down the clock source selected by bit 0 of the WDCLKSRC register and also prevents switching to a clock source that is disabled or powered down. This bit can be set once by software and is only cleared by any reset. If this bit is one and the WWDT clock source is the IRC when Deep-sleep or Power-down modes are entered, the IRC remains running thereby increasing power consumption in Deep-sleep mode and potentially preventing the part of entering Power-down mode correctly (see Section 15.7)." /> + <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x004" size="4" name="TC" access="Read/Write" description="Watchdog timer constant register. This 24-bit register determines the time-out value." reset_value="0xFF" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="24" name="COUNT" description="Watchdog time-out value." /> + <BitField start="24" size="8" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x008" size="4" name="FEED" access="WriteOnly" description="Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in WDTC." reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="8" name="FEED" description="Feed value should be 0xAA followed by 0x55." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x00C" size="4" name="TV" access="ReadOnly" description="Watchdog timer value register. This 24-bit register reads out the current value of the Watchdog timer." reset_value="0xFF" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="24" name="COUNT" description="Counter timer value." /> + <BitField start="24" size="8" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x010" size="4" name="CLKSEL" access="Read/Write" description="Watchdog clock select register." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="CLKSEL" description="Selects source of WDT clock"> + <Enum name="IRC" start="0" description="IRC" /> + <Enum name="WATCHDOG_OSCILLATOR_" start="1" description="Watchdog oscillator (WDOSC)" /> + </BitField> + <BitField start="1" size="30" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + <BitField start="31" size="1" name="LOCK" description="If this bit is set to one writing to this register does not affect bit 0. The clock source can only be changed by first clearing this bit, then writing the new value of bit 0." /> + </Register> + <Register start="+0x014" size="4" name="WARNINT" access="Read/Write" description="Watchdog Warning Interrupt compare value." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="10" name="WARNINT" description="Watchdog warning interrupt compare value." /> + <BitField start="10" size="22" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x018" size="4" name="WINDOW" access="Read/Write" description="Watchdog Window compare value." reset_value="0xFFFFFF" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="24" name="WINDOW" description="Watchdog window value." /> + <BitField start="24" size="8" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + </RegisterGroup> + <RegisterGroup name="CT16B0" start="0x4000C000" description="16-bit counter/timers CT16B0"> + <Register start="+0x000" size="4" name="IR" access="Read/Write" description="Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="MR0INT" description="Interrupt flag for match channel 0." /> + <BitField start="1" size="1" name="MR1INT" description="Interrupt flag for match channel 1." /> + <BitField start="2" size="1" name="MR2INT" description="Interrupt flag for match channel 2." /> + <BitField start="3" size="1" name="MR3INT" description="Interrupt flag for match channel 3." /> + <BitField start="4" size="1" name="CR0INT" description="Interrupt flag for capture channel 0 event." /> + <BitField start="5" size="1" name="RESERVED" description="Reserved." /> + <BitField start="6" size="1" name="CR1INT" description="Interrupt flag for capture channel 1 event." /> + <BitField start="7" size="25" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x004" size="4" name="TCR" access="Read/Write" description="Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="CEN" description="Counter enable."> + <Enum name="THE_COUNTERS_ARE_DIS" start="0" description="The counters are disabled." /> + <Enum name="THE_TIMER_COUNTER_AN" start="1" description="The Timer Counter and Prescale Counter are enabled for counting." /> + </BitField> + <BitField start="1" size="1" name="CRST" description="Counter reset."> + <Enum name="DO_NOTHING_" start="0" description="Do nothing." /> + <Enum name="THE_TIMER_COUNTER_AN" start="1" description="The Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero." /> + </BitField> + <BitField start="2" size="30" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x008" size="4" name="TC" access="Read/Write" description="Timer Counter. The 16-bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="16" name="TC" description="Timer counter value." /> + <BitField start="16" size="16" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x00C" size="4" name="PR" access="Read/Write" description="Prescale Register. When the Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="16" name="PCVAL" description="Prescale value." /> + <BitField start="16" size="16" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x010" size="4" name="PC" access="Read/Write" description="Prescale Counter. The 16-bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="16" name="PC" description="Prescale counter value." /> + <BitField start="16" size="16" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x014" size="4" name="MCR" access="Read/Write" description="Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="MR0I" description="Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC."> + <Enum name="ENABLED" start="1" description="Enabled" /> + <Enum name="DISABLED" start="0" description="Disabled" /> + </BitField> + <BitField start="1" size="1" name="MR0R" description="Reset on MR0: the TC will be reset if MR0 matches it."> + <Enum name="ENABLED" start="1" description="Enabled" /> + <Enum name="DISABLED" start="0" description="Disabled" /> + </BitField> + <BitField start="2" size="1" name="MR0S" description="Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC."> + <Enum name="ENABLED" start="1" description="Enabled" /> + <Enum name="DISABLED" start="0" description="Disabled" /> + </BitField> + <BitField start="3" size="1" name="MR1I" description="Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC."> + <Enum name="ENABLED" start="1" description="Enabled" /> + <Enum name="DISABLED" start="0" description="Disabled" /> + </BitField> + <BitField start="4" size="1" name="MR1R" description="Reset on MR1: the TC will be reset if MR1 matches it."> + <Enum name="ENABLED" start="1" description="Enabled" /> + <Enum name="DISABLED" start="0" description="Disabled" /> + </BitField> + <BitField start="5" size="1" name="MR1S" description="Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC."> + <Enum name="ENABLED" start="1" description="Enabled" /> + <Enum name="DISABLED" start="0" description="Disabled" /> + </BitField> + <BitField start="6" size="1" name="MR2I" description="Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC."> + <Enum name="ENABLED" start="1" description="Enabled" /> + <Enum name="DISABLED" start="0" description="Disabled" /> + </BitField> + <BitField start="7" size="1" name="MR2R" description="Reset on MR2: the TC will be reset if MR2 matches it."> + <Enum name="ENABLED" start="1" description="Enabled" /> + <Enum name="DISABLED" start="0" description="Disabled" /> + </BitField> + <BitField start="8" size="1" name="MR2S" description="Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC."> + <Enum name="ENABLED" start="1" description="Enabled" /> + <Enum name="DISABLED" start="0" description="Disabled" /> + </BitField> + <BitField start="9" size="1" name="MR3I" description="Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC."> + <Enum name="ENABLED" start="1" description="Enabled" /> + <Enum name="DISABLED" start="0" description="Disabled" /> + </BitField> + <BitField start="10" size="1" name="MR3R" description="Reset on MR3: the TC will be reset if MR3 matches it."> + <Enum name="ENABLED" start="1" description="Enabled" /> + <Enum name="DISABLED" start="0" description="Disabled" /> + </BitField> + <BitField start="11" size="1" name="MR3S" description="Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC."> + <Enum name="ENABLED" start="1" description="Enabled" /> + <Enum name="DISABLED" start="0" description="Disabled" /> + </BitField> + <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x018+0" size="4" name="MR0" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="16" name="MATCH" description="Timer counter match value." /> + <BitField start="16" size="16" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x018+4" size="4" name="MR1" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="16" name="MATCH" description="Timer counter match value." /> + <BitField start="16" size="16" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x018+8" size="4" name="MR2" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="16" name="MATCH" description="Timer counter match value." /> + <BitField start="16" size="16" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x018+12" size="4" name="MR3" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="16" name="MATCH" description="Timer counter match value." /> + <BitField start="16" size="16" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x028" size="4" name="CCR" access="Read/Write" description="Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="CAP0RE" description="Capture on CT16B0_CAP0 rising edge: a sequence of 0 then 1 on CT16B0_CAP0 will cause CR0 to be loaded with the contents of TC."> + <Enum name="ENABLED_" start="1" description="Enabled." /> + <Enum name="DISABLED_" start="0" description="Disabled." /> + </BitField> + <BitField start="1" size="1" name="CAP0FE" description="Capture on CT16B0_CAP0 falling edge: a sequence of 1 then 0 on CT16B0_CAP0 will cause CR0 to be loaded with the contents of TC."> + <Enum name="ENABLED_" start="1" description="Enabled." /> + <Enum name="DISABLED_" start="0" description="Disabled." /> + </BitField> + <BitField start="2" size="1" name="CAP0I" description="Interrupt on CT16B0_CAP0 event: a CR0 load due to a CT16B0_CAP0 event will generate an interrupt."> + <Enum name="ENABLED_" start="1" description="Enabled." /> + <Enum name="DISABLED_" start="0" description="Disabled." /> + </BitField> + <BitField start="3" size="1" name="RESERVED" description="Reserved." /> + <BitField start="4" size="1" name="RESERVED" description="Reserved." /> + <BitField start="5" size="1" name="RESERVED" description="Reserved." /> + <BitField start="6" size="1" name="CAP1RE" description="Capture on CT16B0_CAP1 rising edge: a sequence of 0 then 1 on CT16B0_CAP1 will cause CR1 to be loaded with the contents of TC. This bit is reserved for 16-bit timer1 CT16B1."> + <Enum name="ENABLED_" start="1" description="Enabled." /> + <Enum name="DISABLED_" start="0" description="Disabled." /> + </BitField> + <BitField start="7" size="1" name="CAP1FE" description="Capture on CT16B0_CAP1 falling edge: a sequence of 1 then 0 on CT16B0_CAP1 will cause CR1 to be loaded with the contents of TC. This bit is reserved for 16-bit timer1 CT16B1."> + <Enum name="ENABLED_" start="1" description="Enabled." /> + <Enum name="DISABLED_" start="0" description="Disabled." /> + </BitField> + <BitField start="8" size="1" name="CAP1I" description="Interrupt on CT16B0_CAP1 event: a CR1 load due to a CT16B0_CAP1 event will generate an interrupt. This bit is reserved for 16-bit timer1 CT16B1."> + <Enum name="ENABLED_" start="1" description="Enabled." /> + <Enum name="DISABLED_" start="0" description="Disabled." /> + </BitField> + <BitField start="9" size="23" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x02C" size="4" name="CR0" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CT16B0_CAP0 input." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="16" name="CAP" description="Timer counter capture value." /> + <BitField start="16" size="16" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x034" size="4" name="CR1" access="ReadOnly" description="Capture Register 1. CR1 is loaded with the value of TC when there is an event on the CT16B0_CAP1 input." reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="16" name="CAP" description="Timer counter capture value." /> + <BitField start="16" size="16" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x03C" size="4" name="EMR" access="Read/Write" description="External Match Register. The EMR controls the match function and the external match pins CT16B0_MAT[1:0] and CT16B1_MAT[1:0]." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="EM0" description="External Match 0. This bit reflects the state of output CT16B0_MAT0/CT16B1_MAT0, whether or not this output is connected to its pin. When a match occurs between the TC and MR0, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[5:4] control the functionality of this output. This bit is driven to the CT16B0_MAT0/CT16B1_MAT0 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH)." /> + <BitField start="1" size="1" name="EM1" description="External Match 1. This bit reflects the state of output CT16B0_MAT1/CT16B1_MAT1, whether or not this output is connected to its pin. When a match occurs between the TC and MR1, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[7:6] control the functionality of this output. This bit is driven to the CT16B0_MAT0/CT16B1_MAT0 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH)." /> + <BitField start="2" size="1" name="EM2" description="External Match 2. This bit reflects the state of match channel 2. When a match occurs between the TC and MR2, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[9:8] control the functionality of this output." /> + <BitField start="3" size="1" name="EM3" description="External Match 3. This bit reflects the state of output of match channel 3. When a match occurs between the TC and MR3, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[11:10] control the functionality of this output." /> + <BitField start="4" size="2" name="EMC0" description="External Match Control 0. Determines the functionality of External Match 0. Table 296 shows the encoding of these bits."> + <Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." /> + <Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (CT16Bn_MAT0 pin is LOW if pinned out)." /> + <Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (CT16Bn_MAT0 pin is HIGH if pinned out)." /> + <Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." /> + </BitField> + <BitField start="6" size="2" name="EMC1" description="External Match Control 1. Determines the functionality of External Match 1."> + <Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." /> + <Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (CT16Bn_MAT1 pin is LOW if pinned out)." /> + <Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (CT16Bn_MAT1 pin is HIGH if pinned out)." /> + <Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." /> + </BitField> + <BitField start="8" size="2" name="EMC2" description="External Match Control 2. Determines the functionality of External Match 2."> + <Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." /> + <Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (CT16Bn_MAT2 pin is LOW if pinned out)." /> + <Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (CT16Bn_MAT2 pin is HIGH if pinned out)." /> + <Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." /> + </BitField> + <BitField start="10" size="2" name="EMC3" description="External Match Control 3. Determines the functionality of External Match 3."> + <Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." /> + <Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (CT16Bn_MAT3 pin is LOW if pinned out)." /> + <Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (CT16Bn_MAT3 pin is HIGH if pinned out)." /> + <Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." /> + </BitField> + <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x070" size="4" name="CTCR" access="Read/Write" description="Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="CTM" description="Counter/Timer Mode. This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). If Counter mode is selected in the CTCR, bits 2:0 in the Capture Control Register (CCR) must be programmed as 000."> + <Enum name="TIMER_MODE_EVERY_RI" start="0x0" description="Timer Mode: every rising PCLK edge" /> + <Enum name="COUNTER_MODE_TC_IS_" start="0x1" description="Counter Mode: TC is incremented on rising edges on the CAP input selected by bits 3:2." /> + <Enum name="COUNTER_MODE_TC_IS_" start="0x2" description="Counter Mode: TC is incremented on falling edges on the CAP input selected by bits 3:2." /> + <Enum name="COUNTER_MODE_TC_IS_" start="0x3" description="Counter Mode: TC is incremented on both edges on the CAP input selected by bits 3:2." /> + </BitField> + <BitField start="2" size="2" name="CIS" description="Count Input Select. In counter mode (when bits 1:0 in this register are not 00), these bits select which CAP pin or comparator output is sampled for clocking. Values 0x1 and 0x3 are reserved."> + <Enum name="CT16B0_CAP0_" start="0x0" description="CT16B0_CAP0." /> + <Enum name="RESERVED_" start="0x1" description="Reserved." /> + <Enum name="CT16B0_CAP1_" start="0x2" description="CT16B0_CAP1." /> + </BitField> + <BitField start="4" size="1" name="ENCC" description="Setting this bit to 1 enables clearing of the timer and the prescaler when the capture-edge event specified in bits 7:5 occurs." /> + <BitField start="5" size="3" name="SELCC" description="Edge select. When bit 4 is 1, these bits select which capture input edge will cause the timer and prescaler to be cleared. These bits have no effect when bit 4 is low. Values 0x2 to 0x3 and 0x6 to 0x7 are reserved."> + <Enum name="RISING_EDGE_OF_CT16B" start="0x0" description="Rising Edge of CT16B0_CAP0 clears the timer (if bit 4 is set)." /> + <Enum name="FALLING_EDGE_OF_CT16" start="0x1" description="Falling Edge of CT16B0_CCAP0 clears the timer (if bit 4 is set)." /> + <Enum name="RESERVED_" start="0x2" description="Reserved." /> + <Enum name="RESERVED_" start="0x3" description="Reserved." /> + <Enum name="RISING_EDGE_OF_CT16B" start="0x4" description="Rising Edge of CT16B0_CAP1 clears the timer (if bit 4 is set)." /> + <Enum name="FALLING_EDGE_OF_CT16" start="0x5" description="Falling Edge of CT16B0_CAP1 clears the timer (if bit 4 is set)." /> + </BitField> + <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x074" size="4" name="PWMC" access="Read/Write" description="PWM Control Register. The PWMCON enables PWM mode for the external match pins CT16B0_MAT[1:0] and CT16B1_MAT[1:0]." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="PWMEN0" description="PWM mode enable for channel0."> + <Enum name="CT16BN_MAT0_IS_CONTR" start="0" description="CT16Bn_MAT0 is controlled by EM0." /> + <Enum name="PWM_MODE_IS_ENABLED_" start="1" description="PWM mode is enabled for CT16Bn_MAT0." /> + </BitField> + <BitField start="1" size="1" name="PWMEN1" description="PWM mode enable for channel1."> + <Enum name="CT16BN_MAT01_IS_CONT" start="0" description="CT16Bn_MAT01 is controlled by EM1." /> + <Enum name="PWM_MODE_IS_ENABLED_" start="1" description="PWM mode is enabled for CT16Bn_MAT1." /> + </BitField> + <BitField start="2" size="1" name="PWMEN2" description="PWM mode enable for channel2."> + <Enum name="CT16BN_MAT2_IS_CONTR" start="0" description="CT16Bn_MAT2 is controlled by EM2." /> + <Enum name="PWM_MODE_IS_ENABLED_" start="1" description="PWM mode is enabled for CT16Bn_MAT2." /> + </BitField> + <BitField start="3" size="1" name="PWMEN3" description="PWM mode enable for channel3."> + <Enum name="CT16BN_MAT3_IS_CONTR" start="0" description="CT16Bn_MAT3 is controlled by EM3." /> + <Enum name="PWM_MODE_IS_ENABLED_" start="1" description="PWM mode is enabled for CT16Bn_MAT3." /> + </BitField> + <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + </RegisterGroup> + <RegisterGroup name="CT16B1" start="0x40010000" description="16-bit counter/timers CT16B1"> + <Register start="+0x000" size="4" name="IR" access="Read/Write" description="Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="MR0INT" description="Interrupt flag for match channel 0." /> + <BitField start="1" size="1" name="MR1INT" description="Interrupt flag for match channel 1." /> + <BitField start="2" size="1" name="MR2INT" description="Interrupt flag for match channel 2." /> + <BitField start="3" size="1" name="MR3INT" description="Interrupt flag for match channel 3." /> + <BitField start="4" size="1" name="CR0INT" description="Interrupt flag for capture channel 0 event." /> + <BitField start="5" size="1" name="CR1INT" description="Interrupt flag for capture channel 1 event." /> + <BitField start="6" size="1" name="RESERVED" description="Reserved." /> + <BitField start="7" size="25" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x004" size="4" name="TCR" access="Read/Write" description="Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="CEN" description="Counter enable."> + <Enum name="THE_COUNTERS_ARE_DIS" start="0" description="The counters are disabled." /> + <Enum name="THE_TIMER_COUNTER_AN" start="1" description="The Timer Counter and Prescale Counter are enabled for counting." /> + </BitField> + <BitField start="1" size="1" name="CRST" description="Counter reset."> + <Enum name="DO_NOTHING_" start="0" description="Do nothing." /> + <Enum name="THE_TIMER_COUNTER_AN" start="1" description="The Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero." /> + </BitField> + <BitField start="2" size="30" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x008" size="4" name="TC" access="Read/Write" description="Timer Counter. The 16-bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="16" name="TC" description="Timer counter value." /> + <BitField start="16" size="16" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x00C" size="4" name="PR" access="Read/Write" description="Prescale Register. When the Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="16" name="PCVAL" description="Prescale value." /> + <BitField start="16" size="16" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x010" size="4" name="PC" access="Read/Write" description="Prescale Counter. The 16-bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="16" name="PC" description="Prescale counter value." /> + <BitField start="16" size="16" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x014" size="4" name="MCR" access="Read/Write" description="Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="MR0I" description="Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC."> + <Enum name="ENABLED" start="1" description="Enabled" /> + <Enum name="DISABLED" start="0" description="Disabled" /> + </BitField> + <BitField start="1" size="1" name="MR0R" description="Reset on MR0: the TC will be reset if MR0 matches it."> + <Enum name="ENABLED" start="1" description="Enabled" /> + <Enum name="DISABLED" start="0" description="Disabled" /> + </BitField> + <BitField start="2" size="1" name="MR0S" description="Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC."> + <Enum name="ENABLED" start="1" description="Enabled" /> + <Enum name="DISABLED" start="0" description="Disabled" /> + </BitField> + <BitField start="3" size="1" name="MR1I" description="Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC."> + <Enum name="ENABLED" start="1" description="Enabled" /> + <Enum name="DISABLED" start="0" description="Disabled" /> + </BitField> + <BitField start="4" size="1" name="MR1R" description="Reset on MR1: the TC will be reset if MR1 matches it."> + <Enum name="ENABLED" start="1" description="Enabled" /> + <Enum name="DISABLED" start="0" description="Disabled" /> + </BitField> + <BitField start="5" size="1" name="MR1S" description="Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC."> + <Enum name="ENABLED" start="1" description="Enabled" /> + <Enum name="DISABLED" start="0" description="Disabled" /> + </BitField> + <BitField start="6" size="1" name="MR2I" description="Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC."> + <Enum name="ENABLED" start="1" description="Enabled" /> + <Enum name="DISABLED" start="0" description="Disabled" /> + </BitField> + <BitField start="7" size="1" name="MR2R" description="Reset on MR2: the TC will be reset if MR2 matches it."> + <Enum name="ENABLED" start="1" description="Enabled" /> + <Enum name="DISABLED" start="0" description="Disabled" /> + </BitField> + <BitField start="8" size="1" name="MR2S" description="Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC."> + <Enum name="ENABLED" start="1" description="Enabled" /> + <Enum name="DISABLED" start="0" description="Disabled" /> + </BitField> + <BitField start="9" size="1" name="MR3I" description="Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC."> + <Enum name="ENABLED" start="1" description="Enabled" /> + <Enum name="DISABLED" start="0" description="Disabled" /> + </BitField> + <BitField start="10" size="1" name="MR3R" description="Reset on MR3: the TC will be reset if MR3 matches it."> + <Enum name="ENABLED" start="1" description="Enabled" /> + <Enum name="DISABLED" start="0" description="Disabled" /> + </BitField> + <BitField start="11" size="1" name="MR3S" description="Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC."> + <Enum name="ENABLED" start="1" description="Enabled" /> + <Enum name="DISABLED" start="0" description="Disabled" /> + </BitField> + <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x018+0" size="4" name="MR0" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="16" name="MATCH" description="Timer counter match value." /> + <BitField start="16" size="16" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x018+4" size="4" name="MR1" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="16" name="MATCH" description="Timer counter match value." /> + <BitField start="16" size="16" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x018+8" size="4" name="MR2" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="16" name="MATCH" description="Timer counter match value." /> + <BitField start="16" size="16" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x018+12" size="4" name="MR3" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="16" name="MATCH" description="Timer counter match value." /> + <BitField start="16" size="16" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x028" size="4" name="CCR" access="Read/Write" description="Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="CAP0RE" description="Capture on CT16B1_CAP0 rising edge: a sequence of 0 then 1 on CT16B1_CAP0 will cause CR0 to be loaded with the contents of TC."> + <Enum name="ENABLED_" start="1" description="Enabled." /> + <Enum name="DISABLED_" start="0" description="Disabled." /> + </BitField> + <BitField start="1" size="1" name="CAP0FE" description="Capture on CT16B11_CAP0 falling edge: a sequence of 1 then 0 on CT16B1_CAP0 will cause CR0 to be loaded with the contents of TC."> + <Enum name="ENABLED_" start="1" description="Enabled." /> + <Enum name="DISABLED_" start="0" description="Disabled." /> + </BitField> + <BitField start="2" size="1" name="CAP0I" description="Interrupt on CT16B1_CAP0 event: a CR0 load due to a CT16B1_CAP0 event will generate an interrupt."> + <Enum name="ENABLED_" start="1" description="Enabled." /> + <Enum name="DISABLED_" start="0" description="Disabled." /> + </BitField> + <BitField start="3" size="1" name="CAP1RE" description="Capture on CT16B1_CAP1 rising edge: a sequence of 0 then 1 on CT16B1_CAP1 will cause CR1 to be loaded with the contents of TC."> + <Enum name="ENABLED_" start="1" description="Enabled." /> + <Enum name="DISABLED_" start="0" description="Disabled." /> + </BitField> + <BitField start="4" size="1" name="CAP1FE" description="Capture on CT16B1_CAP1 falling edge: a sequence of 1 then 0 on CT16B1_CAP1 will cause CR1 to be loaded with the contents of TC."> + <Enum name="ENABLED_" start="1" description="Enabled." /> + <Enum name="DISABLED_" start="0" description="Disabled." /> + </BitField> + <BitField start="5" size="1" name="CAP1I" description="Interrupt on CT16B1_CAP1 event: a CR1 load due to a CT16B0_CAP1 event will generate an interrupt."> + <Enum name="ENABLED_" start="1" description="Enabled." /> + <Enum name="DISABLED_" start="0" description="Disabled." /> + </BitField> + <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x02C" size="4" name="CR0" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CT16B0_CAP0 input." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="16" name="CAP" description="Timer counter capture value." /> + <BitField start="16" size="16" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x030" size="4" name="CR1" access="ReadOnly" description="Capture Register 1. CR1 is loaded with the value of TC when there is an event on the CT16B1_CAP1 input." reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="16" name="CAP" description="Timer counter capture value." /> + <BitField start="16" size="16" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x03C" size="4" name="EMR" access="Read/Write" description="External Match Register. The EMR controls the match function and the external match pins CT16B0_MAT[1:0] and CT16B1_MAT[1:0]." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="EM0" description="External Match 0. This bit reflects the state of output CT16B0_MAT0/CT16B1_MAT0, whether or not this output is connected to its pin. When a match occurs between the TC and MR0, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[5:4] control the functionality of this output. This bit is driven to the CT16B0_MAT0/CT16B1_MAT0 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH)." /> + <BitField start="1" size="1" name="EM1" description="External Match 1. This bit reflects the state of output CT16B0_MAT1/CT16B1_MAT1, whether or not this output is connected to its pin. When a match occurs between the TC and MR1, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[7:6] control the functionality of this output. This bit is driven to the CT16B0_MAT0/CT16B1_MAT0 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH)." /> + <BitField start="2" size="1" name="EM2" description="External Match 2. This bit reflects the state of match channel 2. When a match occurs between the TC and MR2, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[9:8] control the functionality of this output." /> + <BitField start="3" size="1" name="EM3" description="External Match 3. This bit reflects the state of output of match channel 3. When a match occurs between the TC and MR3, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[11:10] control the functionality of this output." /> + <BitField start="4" size="2" name="EMC0" description="External Match Control 0. Determines the functionality of External Match 0. Table 296 shows the encoding of these bits."> + <Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." /> + <Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (CT16Bn_MAT0 pin is LOW if pinned out)." /> + <Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (CT16Bn_MAT0 pin is HIGH if pinned out)." /> + <Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." /> + </BitField> + <BitField start="6" size="2" name="EMC1" description="External Match Control 1. Determines the functionality of External Match 1."> + <Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." /> + <Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (CT16Bn_MAT1 pin is LOW if pinned out)." /> + <Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (CT16Bn_MAT1 pin is HIGH if pinned out)." /> + <Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." /> + </BitField> + <BitField start="8" size="2" name="EMC2" description="External Match Control 2. Determines the functionality of External Match 2."> + <Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." /> + <Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (CT16Bn_MAT2 pin is LOW if pinned out)." /> + <Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (CT16Bn_MAT2 pin is HIGH if pinned out)." /> + <Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." /> + </BitField> + <BitField start="10" size="2" name="EMC3" description="External Match Control 3. Determines the functionality of External Match 3."> + <Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." /> + <Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (CT16Bn_MAT3 pin is LOW if pinned out)." /> + <Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (CT16Bn_MAT3 pin is HIGH if pinned out)." /> + <Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." /> + </BitField> + <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x070" size="4" name="CTCR" access="Read/Write" description="Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="CTM" description="Counter/Timer Mode. This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). If Counter mode is selected in the CTCR, bits 2:0 in the Capture Control Register (CCR) must be programmed as 000."> + <Enum name="TIMER_MODE_EVERY_RI" start="0x0" description="Timer Mode: every rising PCLK edge" /> + <Enum name="COUNTER_MODE_TC_IS_" start="0x1" description="Counter Mode: TC is incremented on rising edges on the CAP input selected by bits 3:2." /> + <Enum name="COUNTER_MODE_TC_IS_" start="0x2" description="Counter Mode: TC is incremented on falling edges on the CAP input selected by bits 3:2." /> + <Enum name="COUNTER_MODE_TC_IS_" start="0x3" description="Counter Mode: TC is incremented on both edges on the CAP input selected by bits 3:2." /> + </BitField> + <BitField start="2" size="2" name="CIS" description="Count Input Select. In counter mode (when bits 1:0 in this register are not 00), these bits select which CAP pin or comparator output is sampled for clocking. Values 0x2 to 0x3 are reserved."> + <Enum name="CT16B1_CAP0_" start="0x0" description="CT16B1_CAP0." /> + <Enum name="CT16B1_CAP1_" start="0x1" description="CT16B1_CAP1." /> + </BitField> + <BitField start="4" size="1" name="ENCC" description="Setting this bit to 1 enables clearing of the timer and the prescaler when the capture-edge event specified in bits 7:5 occurs." /> + <BitField start="5" size="3" name="SELCC" description="When bit 4 is a 1, these bits select which capture input edge will cause the timer and prescaler to be cleared. These bits have no effect when bit 4 is low. Values 0x6 to 0x7 are reserved."> + <Enum name="RISING_EDGE_OF_CT16B" start="0x0" description="Rising Edge of CT16B1_CAP0 clears the timer (if bit 4 is set)." /> + <Enum name="FALLING_EDGE_OF_CT16" start="0x1" description="Falling Edge of CT16B1_CAP0 clears the timer (if bit 4 is set)." /> + <Enum name="RISING_EDGE_OF_CT16B" start="0x2" description="Rising Edge of CT16B1_CAP1 clears the timer (if bit 4 is set)." /> + <Enum name="FALLING_EDGE_OF_CT16" start="0x3" description="Falling Edge of CT16B1_CAP1 clears the timer (if bit 4 is set)." /> + <Enum name="RESERVED_" start="0x4" description="Reserved." /> + <Enum name="RESERVED_" start="0x5" description="Reserved." /> + </BitField> + <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x074" size="4" name="PWMC" access="Read/Write" description="PWM Control Register. The PWMCON enables PWM mode for the external match pins CT16B0_MAT[1:0] and CT16B1_MAT[1:0]." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="PWMEN0" description="PWM mode enable for channel0."> + <Enum name="CT16BN_MAT0_IS_CONTR" start="0" description="CT16Bn_MAT0 is controlled by EM0." /> + <Enum name="PWM_MODE_IS_ENABLED_" start="1" description="PWM mode is enabled for CT16Bn_MAT0." /> + </BitField> + <BitField start="1" size="1" name="PWMEN1" description="PWM mode enable for channel1."> + <Enum name="CT16BN_MAT01_IS_CONT" start="0" description="CT16Bn_MAT01 is controlled by EM1." /> + <Enum name="PWM_MODE_IS_ENABLED_" start="1" description="PWM mode is enabled for CT16Bn_MAT1." /> + </BitField> + <BitField start="2" size="1" name="PWMEN2" description="PWM mode enable for channel2."> + <Enum name="CT16BN_MAT2_IS_CONTR" start="0" description="CT16Bn_MAT2 is controlled by EM2." /> + <Enum name="PWM_MODE_IS_ENABLED_" start="1" description="PWM mode is enabled for CT16Bn_MAT2." /> + </BitField> + <BitField start="3" size="1" name="PWMEN3" description="PWM mode enable for channel3."> + <Enum name="CT16BN_MAT3_IS_CONTR" start="0" description="CT16Bn_MAT3 is controlled by EM3." /> + <Enum name="PWM_MODE_IS_ENABLED_" start="1" description="PWM mode is enabled for CT16Bn_MAT3." /> + </BitField> + <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + </RegisterGroup> + <RegisterGroup name="CT32B0" start="0x40014000" description="32-bit counter/timers CT32B0"> + <Register start="+0x000" size="4" name="IR" access="Read/Write" description="Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="MR0INT" description="Interrupt flag for match channel 0." /> + <BitField start="1" size="1" name="MR1INT" description="Interrupt flag for match channel 1." /> + <BitField start="2" size="1" name="MR2INT" description="Interrupt flag for match channel 2." /> + <BitField start="3" size="1" name="MR3INT" description="Interrupt flag for match channel 3." /> + <BitField start="4" size="1" name="CR0INT" description="Interrupt flag for capture channel 0 event." /> + <BitField start="5" size="1" name="RESERVED" description="Reserved," /> + <BitField start="6" size="1" name="CR1INT" description="Interrupt flag for capture channel 1 event." /> + <BitField start="7" size="25" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x004" size="4" name="TCR" access="Read/Write" description="Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="CEN" description="Counter enable."> + <Enum name="THE_COUNTERS_ARE_DIS" start="0" description="The counters are disabled." /> + <Enum name="THE_TIMER_COUNTER_AN" start="1" description="The Timer Counter and Prescale Counter are enabled for counting." /> + </BitField> + <BitField start="1" size="1" name="CRST" description="Counter reset."> + <Enum name="DO_NOTHING_" start="0" description="Do nothing." /> + <Enum name="THE_TIMER_COUNTER_AN" start="1" description="The Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero." /> + </BitField> + <BitField start="2" size="30" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x008" size="4" name="TC" access="Read/Write" description="Timer Counter. The 32-bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="TC" description="Timer counter value." /> + </Register> + <Register start="+0x00C" size="4" name="PR" access="Read/Write" description="Prescale Register. When the Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="PCVAL" description="Prescaler value." /> + </Register> + <Register start="+0x010" size="4" name="PC" access="Read/Write" description="Prescale Counter. The 32-bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="PC" description="Prescale counter value." /> + </Register> + <Register start="+0x014" size="4" name="MCR" access="Read/Write" description="Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="MR0I" description="Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC."> + <Enum name="ENABLED" start="1" description="Enabled" /> + <Enum name="DISABLED" start="0" description="Disabled" /> + </BitField> + <BitField start="1" size="1" name="MR0R" description="Reset on MR0: the TC will be reset if MR0 matches it."> + <Enum name="ENABLED" start="1" description="Enabled" /> + <Enum name="DISABLED" start="0" description="Disabled" /> + </BitField> + <BitField start="2" size="1" name="MR0S" description="Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC."> + <Enum name="ENABLED" start="1" description="Enabled" /> + <Enum name="DISABLED" start="0" description="Disabled" /> + </BitField> + <BitField start="3" size="1" name="MR1I" description="Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC."> + <Enum name="ENABLED" start="1" description="Enabled" /> + <Enum name="DISABLED" start="0" description="Disabled" /> + </BitField> + <BitField start="4" size="1" name="MR1R" description="Reset on MR1: the TC will be reset if MR1 matches it."> + <Enum name="ENABLED" start="1" description="Enabled" /> + <Enum name="DISABLED" start="0" description="Disabled" /> + </BitField> + <BitField start="5" size="1" name="MR1S" description="Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC."> + <Enum name="ENABLED" start="1" description="Enabled" /> + <Enum name="DISABLED" start="0" description="Disabled" /> + </BitField> + <BitField start="6" size="1" name="MR2I" description="Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC."> + <Enum name="ENABLED" start="1" description="Enabled" /> + <Enum name="DISABLED" start="0" description="Disabled" /> + </BitField> + <BitField start="7" size="1" name="MR2R" description="Reset on MR2: the TC will be reset if MR2 matches it."> + <Enum name="ENABLED" start="1" description="Enabled" /> + <Enum name="DISABLED" start="0" description="Disabled" /> + </BitField> + <BitField start="8" size="1" name="MR2S" description="Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC."> + <Enum name="ENABLED" start="1" description="Enabled" /> + <Enum name="DISABLED" start="0" description="Disabled" /> + </BitField> + <BitField start="9" size="1" name="MR3I" description="Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC."> + <Enum name="ENABLED" start="1" description="Enabled" /> + <Enum name="DISABLED" start="0" description="Disabled" /> + </BitField> + <BitField start="10" size="1" name="MR3R" description="Reset on MR3: the TC will be reset if MR3 matches it."> + <Enum name="ENABLED" start="1" description="Enabled" /> + <Enum name="DISABLED" start="0" description="Disabled" /> + </BitField> + <BitField start="11" size="1" name="MR3S" description="Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC."> + <Enum name="ENABLED" start="1" description="Enabled" /> + <Enum name="DISABLED" start="0" description="Disabled" /> + </BitField> + <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x018+0" size="4" name="MR0" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="MATCH" description="Timer counter match value." /> + </Register> + <Register start="+0x018+4" size="4" name="MR1" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="MATCH" description="Timer counter match value." /> + </Register> + <Register start="+0x018+8" size="4" name="MR2" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="MATCH" description="Timer counter match value." /> + </Register> + <Register start="+0x018+12" size="4" name="MR3" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="MATCH" description="Timer counter match value." /> + </Register> + <Register start="+0x028" size="4" name="CCR" access="Read/Write" description="Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="CAP0RE" description="Capture on CT32B0_CAP0 rising edge: a sequence of 0 then 1 on CT32B0_CAP0 will cause CR0 to be loaded with the contents of TC."> + <Enum name="ENABLED_" start="1" description="Enabled." /> + <Enum name="DISABLED_" start="0" description="Disabled." /> + </BitField> + <BitField start="1" size="1" name="CAP0FE" description="Capture on CT32B0_CAP0 falling edge: a sequence of 1 then 0 on CT32B0_CAP0 will cause CR0 to be loaded with the contents of TC."> + <Enum name="ENABLED_" start="1" description="Enabled." /> + <Enum name="DISABLED_" start="0" description="Disabled." /> + </BitField> + <BitField start="2" size="1" name="CAP0I" description="Interrupt on CT32B0_CAP0 event: a CR0 load due to a CT32B0_CAP0 event will generate an interrupt."> + <Enum name="ENABLED_" start="1" description="Enabled." /> + <Enum name="DISABLED_" start="0" description="Disabled." /> + </BitField> + <BitField start="3" size="3" name="RESERVED" description="Reserved." /> + <BitField start="6" size="1" name="CAP1RE" description="Capture on CT32B0_CAP1 rising edge: a sequence of 0 then 1 on CT32B0_CAP1 will cause CR1 to be loaded with the contents of TC."> + <Enum name="ENABLED_" start="1" description="Enabled." /> + <Enum name="DISABLED_" start="0" description="Disabled." /> + </BitField> + <BitField start="7" size="1" name="CAP1FE" description="Capture on CT32B0_CAP1 falling edge: a sequence of 1 then 0 on CT32B0_CAP1 will cause CR1 to be loaded with the contents of TC."> + <Enum name="ENABLED_" start="1" description="Enabled." /> + <Enum name="DISABLED_" start="0" description="Disabled." /> + </BitField> + <BitField start="8" size="1" name="CAP1I" description="Interrupt on CT32B0_CAP1 event: a CR1 load due to a CT32B0_CAP1 event will generate an interrupt."> + <Enum name="ENABLED_" start="1" description="Enabled." /> + <Enum name="DISABLED_" start="0" description="Disabled." /> + </BitField> + <BitField start="9" size="23" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x02C" size="4" name="CR0" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CT32B0_CAP0 input." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CAP" description="Timer counter capture value." /> + </Register> + <Register start="+0x034" size="4" name="CR1" access="Read/Write" description="Capture Register 1. CR1 is loaded with the value of TC when there is an event on the CT32B0_CAP1 input." reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="CAP" description="Timer counter capture value." /> + </Register> + <Register start="+0x03C" size="4" name="EMR" access="Read/Write" description="External Match Register. The EMR controls the match function and the external match pins CT32Bn_MAT[3:0]." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="EM0" description="External Match 0. This bit reflects the state of output CT32Bn_MAT0, whether or not this output is connected to its pin. When a match occurs between the TC and MR0, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[5:4] control the functionality of this output. This bit is driven to the CT32B0_MAT0/CT32B1_MAT0 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH)." /> + <BitField start="1" size="1" name="EM1" description="External Match 1. This bit reflects the state of output CT32Bn_MAT1, whether or not this output is connected to its pin. When a match occurs between the TC and MR1, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[7:6] control the functionality of this output. This bit is driven to the CT32B0_MAT1/CT32B1_MAT1 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH)." /> + <BitField start="2" size="1" name="EM2" description="External Match 2. This bit reflects the state of output CT32Bn_MAT2, whether or not this output is connected to its pin. When a match occurs between the TC and MR2, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[9:8] control the functionality of this output. This bit is driven to the CT32B0_MAT2/CT32B1_MAT2 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH)." /> + <BitField start="3" size="1" name="EM3" description="External Match 3. This bit reflects the state of output CT32Bn_MAT3, whether or not this output is connected to its pin. When a match occurs between the TC and MR3, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[11:10] control the functionality of this output. This bit is driven to the CT32B3_MAT0/CT32B1_MAT3 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH)." /> + <BitField start="4" size="2" name="EMC0" description="External Match Control 0. Determines the functionality of External Match 0."> + <Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." /> + <Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (CT32Bi_MAT0 pin is LOW if pinned out)." /> + <Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (CT32Bi_MAT0 pin is HIGH if pinned out)." /> + <Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." /> + </BitField> + <BitField start="6" size="2" name="EMC1" description="External Match Control 1. Determines the functionality of External Match 1."> + <Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." /> + <Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (CT32Bi_MAT1 pin is LOW if pinned out)." /> + <Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (CT32Bi_MAT1 pin is HIGH if pinned out)." /> + <Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." /> + </BitField> + <BitField start="8" size="2" name="EMC2" description="External Match Control 2. Determines the functionality of External Match 2."> + <Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." /> + <Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (CT32Bi_MAT2 pin is LOW if pinned out)." /> + <Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (CT32Bi_MAT2 pin is HIGH if pinned out)." /> + <Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." /> + </BitField> + <BitField start="10" size="2" name="EMC3" description="External Match Control 3. Determines the functionality of External Match 3."> + <Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." /> + <Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (CT32Bi_MAT3 pin is LOW if pinned out)." /> + <Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (CT32Bi_MAT3 pin is HIGH if pinned out)." /> + <Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." /> + </BitField> + <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x070" size="4" name="CTCR" access="Read/Write" description="Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="CTM" description="Counter/Timer Mode. This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). If Counter mode is selected in the CTCR, bits 2:0 in the Capture Control Register (CCR) must be programmed as 000."> + <Enum name="TIMER_MODE_EVERY_RI" start="0x0" description="Timer Mode: every rising PCLK edge" /> + <Enum name="COUNTER_MODE_TC_IS_" start="0x1" description="Counter Mode: TC is incremented on rising edges on the CAP input selected by bits 3:2." /> + <Enum name="COUNTER_MODE_TC_IS_" start="0x2" description="Counter Mode: TC is incremented on falling edges on the CAP input selected by bits 3:2." /> + <Enum name="COUNTER_MODE_TC_IS_" start="0x3" description="Counter Mode: TC is incremented on both edges on the CAP input selected by bits 3:2." /> + </BitField> + <BitField start="2" size="2" name="CIS" description="Count Input Select. In counter mode (when bits 1:0 in this register are not 00), these bits select which CAP pin or comparator output is sampled for clocking. If Counter mode is selected in the CTCR, the 3 bits for that input in the Capture Control Register (CCR) must be programmed as 000. Values 0x1 and0x3 are reserved."> + <Enum name="CT32B0_CAP0" start="0x0" description="CT32B0_CAP0" /> + <Enum name="RESERVED_" start="0x1" description="Reserved." /> + <Enum name="CT32B0_CAP1" start="0x2" description="CT32B0_CAP1" /> + </BitField> + <BitField start="4" size="1" name="ENCC" description="Setting this bit to 1 enables clearing of the timer and the prescaler when the capture-edge event specified in bits 7:5 occurs." /> + <BitField start="5" size="3" name="SElCC" description="When bit 4 is a 1, these bits select which capture input edge will cause the timer and prescaler to be cleared. These bits have no effect when bit 4 is low. Values 0x2 to 0x3 and 0x6 to 0x7 are reserved."> + <Enum name="RISING_EDGE_OF_CT32B" start="0x0" description="Rising Edge of CT32B0_CAP0 clears the timer (if bit 4 is set)" /> + <Enum name="FALLING_EDGE_OF_CT32" start="0x1" description="Falling Edge of CT32B0_CAP0 clears the timer (if bit 4 is set)" /> + <Enum name="RESERVED" start="0x2" description="Reserved," /> + <Enum name="RESERVED_" start="0x3" description="Reserved." /> + <Enum name="RISING_EDGE_OF_CT32B" start="0x4" description="Rising Edge of CT32B0_CAP1 clears the timer (if bit 4 is set)" /> + <Enum name="FALLING_EDGE_OF_CT32" start="0x5" description="Falling Edge of CT32B0_CAP1 clears the timer (if bit 4 is set)" /> + </BitField> + <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x074" size="4" name="PWMC" access="Read/Write" description="PWM Control Register. The PWMCON enables PWM mode for the external match pins CT32Bn_MAT[3:0]." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="PWMEN0" description="PWM mode enable for channel0."> + <Enum name="CT32BN_MAT0_IS_CONTR" start="0" description="CT32Bn_MAT0 is controlled by EM0." /> + <Enum name="PWM_MODE_IS_ENABLED_" start="1" description="PWM mode is enabled for CT32Bn_MAT0." /> + </BitField> + <BitField start="1" size="1" name="PWMEN1" description="PWM mode enable for channel1."> + <Enum name="CT32BN_MAT01_IS_CONT" start="0" description="CT32Bn_MAT01 is controlled by EM1." /> + <Enum name="PWM_MODE_IS_ENABLED_" start="1" description="PWM mode is enabled for CT32Bn_MAT1." /> + </BitField> + <BitField start="2" size="1" name="PWMEN2" description="PWM mode enable for channel2."> + <Enum name="CT32BN_MAT2_IS_CONTR" start="0" description="CT32Bn_MAT2 is controlled by EM2." /> + <Enum name="PWM_MODE_IS_ENABLED_" start="1" description="PWM mode is enabled for CT32Bn_MAT2." /> + </BitField> + <BitField start="3" size="1" name="PWMEN3" description="PWM mode enable for channel3. Note: It is recommended to use match channel 3 to set the PWM cycle."> + <Enum name="CT32BN_MAT3_IS_CONTR" start="0" description="CT32Bn_MAT3 is controlled by EM3." /> + <Enum name="PWM_MODE_IS_ENABLED_" start="1" description="PWM mode is enabled for CT132Bn_MAT3." /> + </BitField> + <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + </RegisterGroup> + <RegisterGroup name="CT32B1" start="0x40018000" description="32-bit counter/timers CT32B1"> + <Register start="+0x000" size="4" name="IR" access="Read/Write" description="Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="MR0INT" description="Interrupt flag for match channel 0." /> + <BitField start="1" size="1" name="MR1INT" description="Interrupt flag for match channel 1." /> + <BitField start="2" size="1" name="MR2INT" description="Interrupt flag for match channel 2." /> + <BitField start="3" size="1" name="MR3INT" description="Interrupt flag for match channel 3." /> + <BitField start="4" size="1" name="CR0INT" description="Interrupt flag for capture channel 0 event." /> + <BitField start="5" size="1" name="CR1INT" description="Interrupt flag for capture channel 1 event." /> + <BitField start="6" size="26" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x004" size="4" name="TCR" access="Read/Write" description="Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="CEN" description="Counter enable."> + <Enum name="THE_COUNTERS_ARE_DIS" start="0" description="The counters are disabled." /> + <Enum name="THE_TIMER_COUNTER_AN" start="1" description="The Timer Counter and Prescale Counter are enabled for counting." /> + </BitField> + <BitField start="1" size="1" name="CRST" description="Counter reset."> + <Enum name="DO_NOTHING_" start="0" description="Do nothing." /> + <Enum name="THE_TIMER_COUNTER_AN" start="1" description="The Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero." /> + </BitField> + <BitField start="2" size="30" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x008" size="4" name="TC" access="Read/Write" description="Timer Counter. The 32-bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="TC" description="Timer counter value." /> + </Register> + <Register start="+0x00C" size="4" name="PR" access="Read/Write" description="Prescale Register. When the Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="PCVAL" description="Prescaler value." /> + </Register> + <Register start="+0x010" size="4" name="PC" access="Read/Write" description="Prescale Counter. The 32-bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="PC" description="Prescale counter value." /> + </Register> + <Register start="+0x014" size="4" name="MCR" access="Read/Write" description="Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="MR0I" description="Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC."> + <Enum name="ENABLED" start="1" description="Enabled" /> + <Enum name="DISABLED" start="0" description="Disabled" /> + </BitField> + <BitField start="1" size="1" name="MR0R" description="Reset on MR0: the TC will be reset if MR0 matches it."> + <Enum name="ENABLED" start="1" description="Enabled" /> + <Enum name="DISABLED" start="0" description="Disabled" /> + </BitField> + <BitField start="2" size="1" name="MR0S" description="Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC."> + <Enum name="ENABLED" start="1" description="Enabled" /> + <Enum name="DISABLED" start="0" description="Disabled" /> + </BitField> + <BitField start="3" size="1" name="MR1I" description="Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC."> + <Enum name="ENABLED" start="1" description="Enabled" /> + <Enum name="DISABLED" start="0" description="Disabled" /> + </BitField> + <BitField start="4" size="1" name="MR1R" description="Reset on MR1: the TC will be reset if MR1 matches it."> + <Enum name="ENABLED" start="1" description="Enabled" /> + <Enum name="DISABLED" start="0" description="Disabled" /> + </BitField> + <BitField start="5" size="1" name="MR1S" description="Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC."> + <Enum name="ENABLED" start="1" description="Enabled" /> + <Enum name="DISABLED" start="0" description="Disabled" /> + </BitField> + <BitField start="6" size="1" name="MR2I" description="Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC."> + <Enum name="ENABLED" start="1" description="Enabled" /> + <Enum name="DISABLED" start="0" description="Disabled" /> + </BitField> + <BitField start="7" size="1" name="MR2R" description="Reset on MR2: the TC will be reset if MR2 matches it."> + <Enum name="ENABLED" start="1" description="Enabled" /> + <Enum name="DISABLED" start="0" description="Disabled" /> + </BitField> + <BitField start="8" size="1" name="MR2S" description="Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC."> + <Enum name="ENABLED" start="1" description="Enabled" /> + <Enum name="DISABLED" start="0" description="Disabled" /> + </BitField> + <BitField start="9" size="1" name="MR3I" description="Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC."> + <Enum name="ENABLED" start="1" description="Enabled" /> + <Enum name="DISABLED" start="0" description="Disabled" /> + </BitField> + <BitField start="10" size="1" name="MR3R" description="Reset on MR3: the TC will be reset if MR3 matches it."> + <Enum name="ENABLED" start="1" description="Enabled" /> + <Enum name="DISABLED" start="0" description="Disabled" /> + </BitField> + <BitField start="11" size="1" name="MR3S" description="Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC."> + <Enum name="ENABLED" start="1" description="Enabled" /> + <Enum name="DISABLED" start="0" description="Disabled" /> + </BitField> + <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x018+0" size="4" name="MR0" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="MATCH" description="Timer counter match value." /> + </Register> + <Register start="+0x018+4" size="4" name="MR1" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="MATCH" description="Timer counter match value." /> + </Register> + <Register start="+0x018+8" size="4" name="MR2" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="MATCH" description="Timer counter match value." /> + </Register> + <Register start="+0x018+12" size="4" name="MR3" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="MATCH" description="Timer counter match value." /> + </Register> + <Register start="+0x028" size="4" name="CCR" access="Read/Write" description="Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="CAP0RE" description="Capture on CT32B1_CAP0 rising edge: a sequence of 0 then 1 on CT32B1_CAP0 will cause CR0 to be loaded with the contents of TC."> + <Enum name="ENABLED_" start="1" description="Enabled." /> + <Enum name="DISABLED_" start="0" description="Disabled." /> + </BitField> + <BitField start="1" size="1" name="CAP0FE" description="Capture on CT32B1_CAP0 falling edge: a sequence of 1 then 0 on CT32B1_CAP0 will cause CR0 to be loaded with the contents of TC."> + <Enum name="ENABLED_" start="1" description="Enabled." /> + <Enum name="DISABLED_" start="0" description="Disabled." /> + </BitField> + <BitField start="2" size="1" name="CAP0I" description="Interrupt on CT32B1_CAP0 event: a CR0 load due to a CT32B1_CAP0 event will generate an interrupt."> + <Enum name="ENABLED_" start="1" description="Enabled." /> + <Enum name="DISABLED_" start="0" description="Disabled." /> + </BitField> + <BitField start="3" size="1" name="CAP1RE" description="Capture on CT32B1_CAP1 rising edge: a sequence of 0 then 1 on CT32B1_CAP1 will cause CR1 to be loaded with the contents of TC."> + <Enum name="ENABLED_" start="1" description="Enabled." /> + <Enum name="DISABLED_" start="0" description="Disabled." /> + </BitField> + <BitField start="4" size="1" name="CAP1FE" description="Capture on CT32B1_CAP1 falling edge: a sequence of 1 then 0 on CT32B1_CAP1 will cause CR1 to be loaded with the contents of TC."> + <Enum name="ENABLED_" start="1" description="Enabled." /> + <Enum name="DISABLED_" start="0" description="Disabled." /> + </BitField> + <BitField start="5" size="1" name="CAP1I" description="Interrupt on CT32B1_CAP1 event: a CR1 load due to a CT32B1_CAP1 event will generate an interrupt."> + <Enum name="ENABLED_" start="1" description="Enabled." /> + <Enum name="DISABLED_" start="0" description="Disabled." /> + </BitField> + <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x02C" size="4" name="CR0" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CT32B0_CAP0 input." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CAP" description="Timer counter capture value." /> + </Register> + <Register start="+0x030" size="4" name="CR1" access="Read/Write" description="Capture Register 1. CR1 is loaded with the value of TC when there is an event on the CT32B1_CAP1 input." reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="CAP" description="Timer counter capture value." /> + </Register> + <Register start="+0x03C" size="4" name="EMR" access="Read/Write" description="External Match Register. The EMR controls the match function and the external match pins CT32Bn_MAT[3:0]." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="EM0" description="External Match 0. This bit reflects the state of output CT32Bn_MAT0, whether or not this output is connected to its pin. When a match occurs between the TC and MR0, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[5:4] control the functionality of this output. This bit is driven to the CT32B0_MAT0/CT32B1_MAT0 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH)." /> + <BitField start="1" size="1" name="EM1" description="External Match 1. This bit reflects the state of output CT32Bn_MAT1, whether or not this output is connected to its pin. When a match occurs between the TC and MR1, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[7:6] control the functionality of this output. This bit is driven to the CT32B0_MAT1/CT32B1_MAT1 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH)." /> + <BitField start="2" size="1" name="EM2" description="External Match 2. This bit reflects the state of output CT32Bn_MAT2, whether or not this output is connected to its pin. When a match occurs between the TC and MR2, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[9:8] control the functionality of this output. This bit is driven to the CT32B0_MAT2/CT32B1_MAT2 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH)." /> + <BitField start="3" size="1" name="EM3" description="External Match 3. This bit reflects the state of output CT32Bn_MAT3, whether or not this output is connected to its pin. When a match occurs between the TC and MR3, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[11:10] control the functionality of this output. This bit is driven to the CT32B3_MAT0/CT32B1_MAT3 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH)." /> + <BitField start="4" size="2" name="EMC0" description="External Match Control 0. Determines the functionality of External Match 0."> + <Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." /> + <Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (CT32Bi_MAT0 pin is LOW if pinned out)." /> + <Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (CT32Bi_MAT0 pin is HIGH if pinned out)." /> + <Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." /> + </BitField> + <BitField start="6" size="2" name="EMC1" description="External Match Control 1. Determines the functionality of External Match 1."> + <Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." /> + <Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (CT32Bi_MAT1 pin is LOW if pinned out)." /> + <Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (CT32Bi_MAT1 pin is HIGH if pinned out)." /> + <Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." /> + </BitField> + <BitField start="8" size="2" name="EMC2" description="External Match Control 2. Determines the functionality of External Match 2."> + <Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." /> + <Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (CT32Bi_MAT2 pin is LOW if pinned out)." /> + <Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (CT32Bi_MAT2 pin is HIGH if pinned out)." /> + <Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." /> + </BitField> + <BitField start="10" size="2" name="EMC3" description="External Match Control 3. Determines the functionality of External Match 3."> + <Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." /> + <Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (CT32Bi_MAT3 pin is LOW if pinned out)." /> + <Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (CT32Bi_MAT3 pin is HIGH if pinned out)." /> + <Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." /> + </BitField> + <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x070" size="4" name="CTCR" access="Read/Write" description="Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="CTM" description="Counter/Timer Mode. This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). If Counter mode is selected in the CTCR, bits 2:0 in the Capture Control Register (CCR) must be programmed as 000."> + <Enum name="TIMER_MODE_EVERY_RI" start="0x0" description="Timer Mode: every rising PCLK edge" /> + <Enum name="COUNTER_MODE_TC_IS_" start="0x1" description="Counter Mode: TC is incremented on rising edges on the CAP input selected by bits 3:2." /> + <Enum name="COUNTER_MODE_TC_IS_" start="0x2" description="Counter Mode: TC is incremented on falling edges on the CAP input selected by bits 3:2." /> + <Enum name="COUNTER_MODE_TC_IS_" start="0x3" description="Counter Mode: TC is incremented on both edges on the CAP input selected by bits 3:2." /> + </BitField> + <BitField start="2" size="2" name="CIS" description="Count Input Select. In counter mode (when bits 1:0 in this register are not 00), these bits select which CAP pin or comparator output is sampled for clocking. If Counter mode is selected in the CTCR, the 3 bits for that input in the Capture Control Register (CCR) must be programmed as 000. Values 0x2 to 0x3 are reserved."> + <Enum name="CT32B1_CAP0" start="0x0" description="CT32B1_CAP0" /> + <Enum name="CT32B1_CAP1" start="0x1" description="CT32B1_CAP1" /> + </BitField> + <BitField start="4" size="1" name="ENCC" description="Setting this bit to 1 enables clearing of the timer and the prescaler when the capture-edge event specified in bits 7:5 occurs." /> + <BitField start="5" size="3" name="SElCC" description="When bit 4 is a 1, these bits select which capture input edge will cause the timer and prescaler to be cleared. These bits have no effect when bit 4 is low. Values 0x3 to 0x7 are reserved."> + <Enum name="RISING_EDGE_OF_CT32B" start="0x0" description="Rising Edge of CT32B1_CAP0 clears the timer (if bit 4 is set)" /> + <Enum name="FALLING_EDGE_OF_CT32" start="0x1" description="Falling Edge of CT32B1_CAP0 clears the timer (if bit 4 is set)" /> + <Enum name="RISING_EDGE_OF_CT32B" start="0x2" description="Rising Edge of CT32B1_CAP1 clears the timer (if bit 4 is set)" /> + <Enum name="FALLING_EDGE_OF_CT32" start="0x3" description="Falling Edge of CT32B1_CAP1 clears the timer (if bit 4 is set)" /> + </BitField> + <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x074" size="4" name="PWMC" access="Read/Write" description="PWM Control Register. The PWMCON enables PWM mode for the external match pins CT32Bn_MAT[3:0]." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="PWMEN0" description="PWM mode enable for channel0."> + <Enum name="CT32BN_MAT0_IS_CONTR" start="0" description="CT32Bn_MAT0 is controlled by EM0." /> + <Enum name="PWM_MODE_IS_ENABLED_" start="1" description="PWM mode is enabled for CT32Bn_MAT0." /> + </BitField> + <BitField start="1" size="1" name="PWMEN1" description="PWM mode enable for channel1."> + <Enum name="CT32BN_MAT01_IS_CONT" start="0" description="CT32Bn_MAT01 is controlled by EM1." /> + <Enum name="PWM_MODE_IS_ENABLED_" start="1" description="PWM mode is enabled for CT32Bn_MAT1." /> + </BitField> + <BitField start="2" size="1" name="PWMEN2" description="PWM mode enable for channel2."> + <Enum name="CT32BN_MAT2_IS_CONTR" start="0" description="CT32Bn_MAT2 is controlled by EM2." /> + <Enum name="PWM_MODE_IS_ENABLED_" start="1" description="PWM mode is enabled for CT32Bn_MAT2." /> + </BitField> + <BitField start="3" size="1" name="PWMEN3" description="PWM mode enable for channel3. Note: It is recommended to use match channel 3 to set the PWM cycle."> + <Enum name="CT32BN_MAT3_IS_CONTR" start="0" description="CT32Bn_MAT3 is controlled by EM3." /> + <Enum name="PWM_MODE_IS_ENABLED_" start="1" description="PWM mode is enabled for CT132Bn_MAT3." /> + </BitField> + <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + </RegisterGroup> + <RegisterGroup name="USART" start="0x40008000" description="USART"> + <Register start="+0x000" size="4" name="RBR" access="None" description="Receiver Buffer Register. Contains the next received character to be read. (DLAB=0)" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="8" name="RBR" description="The USART Receiver Buffer Register contains the oldest received byte in the USART RX FIFO." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x000" size="4" name="THR" access="None" description="Transmit Holding Register. The next character to be transmitted is written here. (DLAB=0)" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="8" name="THR" description="Writing to the USART Transmit Holding Register causes the data to be stored in the USART transmit FIFO. The byte will be sent when it is the oldest byte in the FIFO and the transmitter is available." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x000" size="4" name="DLL" access="Read/Write" description="Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. (DLAB=1)" reset_value="0x01" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="DLLSB" description="The USART Divisor Latch LSB Register, along with the DLM register, determines the baud rate of the USART." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x004" size="4" name="DLM" access="Read/Write" description="Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. (DLAB=1)" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="DLMSB" description="The USART Divisor Latch MSB Register, along with the DLL register, determines the baud rate of the USART." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x004" size="4" name="IER" access="Read/Write" description="Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential USART interrupts. (DLAB=0)" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RBRINTEN" description="RBR Interrupt Enable. Enables the Receive Data Available interrupt. It also controls the Character Receive Time-out interrupt."> + <Enum name="DISABLE_THE_RDA_INTE" start="0" description="Disable the RDA interrupt." /> + <Enum name="ENABLE_THE_RDA_INTER" start="1" description="Enable the RDA interrupt." /> + </BitField> + <BitField start="1" size="1" name="THREINTEN" description="THRE Interrupt Enable. Enables the THRE interrupt. The status of this interrupt can be read from LSR[5]."> + <Enum name="DISABLE_THE_THRE_INT" start="0" description="Disable the THRE interrupt." /> + <Enum name="ENABLE_THE_THRE_INTE" start="1" description="Enable the THRE interrupt." /> + </BitField> + <BitField start="2" size="1" name="RLSINTEN" description="Enables the Receive Line Status interrupt. The status of this interrupt can be read from LSR[4:1]."> + <Enum name="DISABLE_THE_RLS_INTE" start="0" description="Disable the RLS interrupt." /> + <Enum name="ENABLE_THE_RLS_INTER" start="1" description="Enable the RLS interrupt." /> + </BitField> + <BitField start="3" size="1" name="MSINTEN" description="Enables the Modem Status interrupt. The components of this interrupt can be read from the MSR."> + <Enum name="DISABLE_THE_MS_INTER" start="0" description="Disable the MS interrupt." /> + <Enum name="ENABLE_THE_MS_INTERR" start="1" description="Enable the MS interrupt." /> + </BitField> + <BitField start="4" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + <BitField start="8" size="1" name="ABEOINTEN" description="Enables the end of auto-baud interrupt."> + <Enum name="DISABLE_END_OF_AUTO_" start="0" description="Disable end of auto-baud Interrupt." /> + <Enum name="ENABLE_END_OF_AUTO_B" start="1" description="Enable end of auto-baud Interrupt." /> + </BitField> + <BitField start="9" size="1" name="ABTOINTEN" description="Enables the auto-baud time-out interrupt."> + <Enum name="DISABLE_AUTO_BAUD_TI" start="0" description="Disable auto-baud time-out Interrupt." /> + <Enum name="ENABLE_AUTO_BAUD_TIM" start="1" description="Enable auto-baud time-out Interrupt." /> + </BitField> + <BitField start="10" size="22" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x008" size="4" name="IIR" access="ReadOnly" description="Interrupt ID Register. Identifies which interrupt(s) are pending." reset_value="0x01" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="INTSTATUS" description="Interrupt status. Note that IIR[0] is active low. The pending interrupt can be determined by evaluating IIR[3:1]."> + <Enum name="AT_LEAST_ONE_INTERRU" start="0" description="At least one interrupt is pending." /> + <Enum name="NO_INTERRUPT_IS_PEND" start="1" description="No interrupt is pending." /> + </BitField> + <BitField start="1" size="3" name="INTID" description="Interrupt identification. IER[3:1] identifies an interrupt corresponding to the USART Rx FIFO. All other values of IER[3:1] not listed below are reserved."> + <Enum name="1_RECEIVE_LINE_S" start="0x3" description="1 - Receive Line Status (RLS)." /> + <Enum name="2A__RECEIVE_DATA_AV" start="0x2" description="2a - Receive Data Available (RDA)." /> + <Enum name="2B__CHARACTER_TIME_" start="0x6" description="2b - Character Time-out Indicator (CTI)." /> + <Enum name="3_THRE_INTERRUPT" start="0x1" description="3 - THRE Interrupt." /> + <Enum name="4_MODEM_STATUS" start="0x0" description="4 - Modem status" /> + </BitField> + <BitField start="4" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + <BitField start="6" size="2" name="FIFOEN" description="These bits are equivalent to FCR[0]." /> + <BitField start="8" size="1" name="ABEOINT" description="End of auto-baud interrupt. True if auto-baud has finished successfully and interrupt is enabled." /> + <BitField start="9" size="1" name="ABTOINT" description="Auto-baud time-out interrupt. True if auto-baud has timed out and interrupt is enabled." /> + <BitField start="10" size="22" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x008" size="4" name="FCR" access="WriteOnly" description="FIFO Control Register. Controls USART FIFO usage and modes." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="FIFOEN" description="FIFO enable"> + <Enum name="DISABLED" start="0" description="USART FIFOs are disabled. Must not be used in the application." /> + <Enum name="ENABLED" start="1" description="Active high enable for both USART Rx and TX FIFOs and FCR[7:1] access. This bit must be set for proper USART operation. Any transition on this bit will automatically clear the USART FIFOs." /> + </BitField> + <BitField start="1" size="1" name="RXFIFORES" description="RX FIFO Reset"> + <Enum name="NO_IMPACT" start="0" description="No impact on either of USART FIFOs." /> + <Enum name="CLEAR" start="1" description="Writing a logic 1 to FCR[1] will clear all bytes in USART Rx FIFO, reset the pointer logic. This bit is self-clearing." /> + </BitField> + <BitField start="2" size="1" name="TXFIFORES" description="TX FIFO Reset"> + <Enum name="NO_IMPACT" start="0" description="No impact on either of USART FIFOs." /> + <Enum name="CLEAR" start="1" description="Writing a logic 1 to FCR[2] will clear all bytes in USART TX FIFO, reset the pointer logic. This bit is self-clearing." /> + </BitField> + <BitField start="3" size="1" name="RESERVED" description="Reserved" /> + <BitField start="4" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + <BitField start="6" size="2" name="RXTL" description="RX Trigger Level. These two bits determine how many receiver USART FIFO characters must be written before an interrupt is activated."> + <Enum name="TRIGGER_LEVEL_0_1_C" start="0x0" description="Trigger level 0 (1 character or 0x01)." /> + <Enum name="TRIGGER_LEVEL_1_4_C" start="0x1" description="Trigger level 1 (4 characters or 0x04)." /> + <Enum name="TRIGGER_LEVEL_2_8_C" start="0x2" description="Trigger level 2 (8 characters or 0x08)." /> + <Enum name="TRIGGER_LEVEL_3_14_" start="0x3" description="Trigger level 3 (14 characters or 0x0E)." /> + </BitField> + <BitField start="8" size="24" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x00C" size="4" name="LCR" access="Read/Write" description="Line Control Register. Contains controls for frame formatting and break generation." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="WLS" description="Word Length Select"> + <Enum name="5_BIT_CHARACTER_LENG" start="0x0" description="5-bit character length." /> + <Enum name="6_BIT_CHARACTER_LENG" start="0x1" description="6-bit character length." /> + <Enum name="7_BIT_CHARACTER_LENG" start="0x2" description="7-bit character length." /> + <Enum name="8_BIT_CHARACTER_LENG" start="0x3" description="8-bit character length." /> + </BitField> + <BitField start="2" size="1" name="SBS" description="Stop Bit Select"> + <Enum name="1_STOP_BIT_" start="0" description="1 stop bit." /> + <Enum name="2_STOP_BITS_1_5_IF_" start="1" description="2 stop bits (1.5 if LCR[1:0]=00)." /> + </BitField> + <BitField start="3" size="1" name="PE" description="Parity Enable"> + <Enum name="DISABLE_PARITY_GENER" start="0" description="Disable parity generation and checking." /> + <Enum name="ENABLE_PARITY_GENERA" start="1" description="Enable parity generation and checking." /> + </BitField> + <BitField start="4" size="2" name="PS" description="Parity Select"> + <Enum name="ODD_PARITY_NUMBER_O" start="0x0" description="Odd parity. Number of 1s in the transmitted character and the attached parity bit will be odd." /> + <Enum name="EVEN_PARITY_NUMBER_" start="0x1" description="Even Parity. Number of 1s in the transmitted character and the attached parity bit will be even." /> + <Enum name="FORCED_1_STICK_PARIT" start="0x2" description="Forced 1 stick parity." /> + <Enum name="FORCED_0_STICK_PARIT" start="0x3" description="Forced 0 stick parity." /> + </BitField> + <BitField start="6" size="1" name="BC" description="Break Control"> + <Enum name="DISABLE_BREAK_TRANSM" start="0" description="Disable break transmission." /> + <Enum name="ENABLE_BREAK_TRANSMI" start="1" description="Enable break transmission. Output pin USART TXD is forced to logic 0 when LCR[6] is active high." /> + </BitField> + <BitField start="7" size="1" name="DLAB" description="Divisor Latch Access Bit"> + <Enum name="DISABLE_ACCESS_TO_DI" start="0" description="Disable access to Divisor Latches." /> + <Enum name="ENABLE_ACCESS_TO_DIV" start="1" description="Enable access to Divisor Latches." /> + </BitField> + <BitField start="8" size="24" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x010" size="4" name="MCR" access="Read/Write" description="Modem Control Register." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="DTRCTRL" description="Source for modem output pin DTR. This bit reads as 0 when modem loopback mode is active." /> + <BitField start="1" size="1" name="RTSCTRL" description="Source for modem output pin RTS. This bit reads as 0 when modem loopback mode is active." /> + <BitField start="2" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + <BitField start="4" size="1" name="LMS" description="Loopback Mode Select. The modem loopback mode provides a mechanism to perform diagnostic loopback testing. Serial data from the transmitter is connected internally to serial input of the receiver. Input pin, RXD, has no effect on loopback and output pin, TXD is held in marking state. The DSR, CTS, DCD, and RI pins are ignored. Externally, DTR and RTS are set inactive. Internally, the upper four bits of the MSR are driven by the lower four bits of the MCR. This permits modem status interrupts to be generated in loopback mode by writing the lower four bits of MCR."> + <Enum name="DISABLE_MODEM_LOOPBA" start="0" description="Disable modem loopback mode." /> + <Enum name="ENABLE_MODEM_LOOPBAC" start="1" description="Enable modem loopback mode." /> + </BitField> + <BitField start="5" size="1" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + <BitField start="6" size="1" name="RTSEN" description="RTS enable"> + <Enum name="DISABLE_AUTO_RTS_FLO" start="0" description="Disable auto-rts flow control." /> + <Enum name="ENABLE_AUTO_RTS_FLOW" start="1" description="Enable auto-rts flow control." /> + </BitField> + <BitField start="7" size="1" name="CTSEN" description="CTS enable"> + <Enum name="DISABLE_AUTO_CTS_FLO" start="0" description="Disable auto-cts flow control." /> + <Enum name="ENABLE_AUTO_CTS_FLOW" start="1" description="Enable auto-cts flow control." /> + </BitField> + <BitField start="8" size="24" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x014" size="4" name="LSR" access="None" description="Line Status Register. Contains flags for transmit and receive status, including line errors." reset_value="0x60" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RDR" description="Receiver Data Ready:LSR[0] is set when the RBR holds an unread character and is cleared when the USART RBR FIFO is empty."> + <Enum name="RBR_IS_EMPTY_" start="0" description="RBR is empty." /> + <Enum name="RBR_CONTAINS_VALID_D" start="1" description="RBR contains valid data." /> + </BitField> + <BitField start="1" size="1" name="OE" description="Overrun Error. The overrun error condition is set as soon as it occurs. A LSR read clears LSR[1]. LSR[1] is set when USART RSR has a new character assembled and the USART RBR FIFO is full. In this case, the USART RBR FIFO will not be overwritten and the character in the USART RSR will be lost."> + <Enum name="INACTIVE" start="0" description="Overrun error status is inactive." /> + <Enum name="ACTIVE" start="1" description="Overrun error status is active." /> + </BitField> + <BitField start="2" size="1" name="PE" description="Parity Error. When the parity bit of a received character is in the wrong state, a parity error occurs. A LSR read clears LSR[2]. Time of parity error detection is dependent on FCR[0]. Note: A parity error is associated with the character at the top of the USART RBR FIFO."> + <Enum name="INACTIVE" start="0" description="Parity error status is inactive." /> + <Enum name="ACTIVE" start="1" description="Parity error status is active." /> + </BitField> + <BitField start="3" size="1" name="FE" description="Framing Error. When the stop bit of a received character is a logic 0, a framing error occurs. A LSR read clears LSR[3]. The time of the framing error detection is dependent on FCR0. Upon detection of a framing error, the RX will attempt to re-synchronize to the data and assume that the bad stop bit is actually an early start bit. However, it cannot be assumed that the next received byte will be correct even if there is no Framing Error. Note: A framing error is associated with the character at the top of the USART RBR FIFO."> + <Enum name="INACTIVE" start="0" description="Framing error status is inactive." /> + <Enum name="ACTIVE" start="1" description="Framing error status is active." /> + </BitField> + <BitField start="4" size="1" name="BI" description="Break Interrupt. When RXD1 is held in the spacing state (all zeros) for one full character transmission (start, data, parity, stop), a break interrupt occurs. Once the break condition has been detected, the receiver goes idle until RXD1 goes to marking state (all ones). A LSR read clears this status bit. The time of break detection is dependent on FCR[0]. Note: The break interrupt is associated with the character at the top of the USART RBR FIFO."> + <Enum name="INACTIVE" start="0" description="Break interrupt status is inactive." /> + <Enum name="ACTIVE" start="1" description="Break interrupt status is active." /> + </BitField> + <BitField start="5" size="1" name="THRE" description="Transmitter Holding Register Empty. THRE is set immediately upon detection of an empty USART THR and is cleared on a THR write."> + <Enum name="THR_CONTAINS_VALID_D" start="0" description="THR contains valid data." /> + <Enum name="THR_IS_EMPTY_" start="1" description="THR is empty." /> + </BitField> + <BitField start="6" size="1" name="TEMT" description="Transmitter Empty. TEMT is set when both THR and TSR are empty; TEMT is cleared when either the TSR or the THR contain valid data."> + <Enum name="VALID_D" start="0" description="THR and/or the TSR contains valid data." /> + <Enum name="EMPTY" start="1" description="THR and the TSR are empty." /> + </BitField> + <BitField start="7" size="1" name="RXFE" description="Error in RX FIFO. LSR[7] is set when a character with a RX error such as framing error, parity error or break interrupt, is loaded into the RBR. This bit is cleared when the LSR register is read and there are no subsequent errors in the USART FIFO."> + <Enum name="NO_ERROR" start="0" description="RBR contains no USART RX errors or FCR[0]=0." /> + <Enum name="ERRO" start="1" description="USART RBR contains at least one USART RX error." /> + </BitField> + <BitField start="8" size="1" name="TXERR" description="Tx Error. In smart card T=0 operation, this bit is set when the smart card has NACKed a transmitted character, one more than the number of times indicated by the TXRETRY field." /> + <BitField start="9" size="23" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x018" size="4" name="MSR" access="None" description="Modem Status Register." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="DCTS" description="Delta CTS. Set upon state change of input CTS. Cleared on an MSR read."> + <Enum name="NO_CHANGE_DETECTED_O" start="0" description="No change detected on modem input, CTS." /> + <Enum name="STATE_CHANGE_DETECTE" start="1" description="State change detected on modem input, CTS." /> + </BitField> + <BitField start="1" size="1" name="DDSR" description="Delta DSR. Set upon state change of input DSR. Cleared on an MSR read."> + <Enum name="NO_CHANGE_DETECTED_O" start="0" description="No change detected on modem input, DSR." /> + <Enum name="STATE_CHANGE_DETECTE" start="1" description="State change detected on modem input, DSR." /> + </BitField> + <BitField start="2" size="1" name="TERI" description="Trailing Edge RI. Set upon low to high transition of input RI. Cleared on an MSR read."> + <Enum name="NO_CHANGE_DETECTED_O" start="0" description="No change detected on modem input, RI." /> + <Enum name="LOW_TO_HIGH_TRANSITI" start="1" description="Low-to-high transition detected on RI." /> + </BitField> + <BitField start="3" size="1" name="DDCD" description="Delta DCD. Set upon state change of input DCD. Cleared on an MSR read."> + <Enum name="NO_CHANGE_DETECTED_O" start="0" description="No change detected on modem input, DCD." /> + <Enum name="STATE_CHANGE_DETECTE" start="1" description="State change detected on modem input, DCD." /> + </BitField> + <BitField start="4" size="1" name="CTS" description="Clear To Send State. Complement of input signal CTS. This bit is connected to MCR[1] in modem loopback mode." /> + <BitField start="5" size="1" name="DSR" description="Data Set Ready State. Complement of input signal DSR. This bit is connected to MCR[0] in modem loopback mode." /> + <BitField start="6" size="1" name="RI" description="Ring Indicator State. Complement of input RI. This bit is connected to MCR[2] in modem loopback mode." /> + <BitField start="7" size="1" name="DCD" description="Data Carrier Detect State. Complement of input DCD. This bit is connected to MCR[3] in modem loopback mode." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x01C" size="4" name="SCR" access="Read/Write" description="Scratch Pad Register. Eight-bit temporary storage for software." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="PAD" description="A readable, writable byte." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x020" size="4" name="ACR" access="Read/Write" description="Auto-baud Control Register. Contains controls for the auto-baud feature." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="START" description="This bit is automatically cleared after auto-baud completion."> + <Enum name="AUTO_BAUD_STOP_AUTO" start="0" description="Auto-baud stop (auto-baud is not running)." /> + <Enum name="AUTO_BAUD_START_AUT" start="1" description="Auto-baud start (auto-baud is running). Auto-baud run bit. This bit is automatically cleared after auto-baud completion." /> + </BitField> + <BitField start="1" size="1" name="MODE" description="Auto-baud mode select bit."> + <Enum name="MODE_0_" start="0" description="Mode 0." /> + <Enum name="MODE_1_" start="1" description="Mode 1." /> + </BitField> + <BitField start="2" size="1" name="AUTORESTART" description="Start mode"> + <Enum name="NO_RESTART" start="0" description="No restart" /> + <Enum name="RESTART_IN_CASE_OF_T" start="1" description="Restart in case of time-out (counter restarts at next USART Rx falling edge)" /> + </BitField> + <BitField start="3" size="5" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + <BitField start="8" size="1" name="ABEOINTCLR" description="End of auto-baud interrupt clear bit (write only accessible)."> + <Enum name="NO_IMPACT" start="0" description="Writing a 0 has no impact." /> + <Enum name="CLEAR" start="1" description="Writing a 1 will clear the corresponding interrupt in the IIR." /> + </BitField> + <BitField start="9" size="1" name="ABTOINTCLR" description="Auto-baud time-out interrupt clear bit (write only accessible)."> + <Enum name="NO_IMPACT" start="0" description="Writing a 0 has no impact." /> + <Enum name="CLEAR" start="1" description="Writing a 1 will clear the corresponding interrupt in the IIR." /> + </BitField> + <BitField start="10" size="22" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x024" size="4" name="ICR" access="Read/Write" description="IrDA Control Register. Enables and configures the IrDA (remote control) mode." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="IRDAEN" description="IrDA mode enable"> + <Enum name="IRDA_MODE_IS_DISABLE" start="0" description="IrDA mode is disabled, USARTn acts as a standard USART." /> + <Enum name="IRDA_MODE_IS_ENABLED" start="1" description="IrDA mode is enabled." /> + </BitField> + <BitField start="1" size="1" name="IRDAINV" description="Serial input inverter"> + <Enum name="INVERTED" start="0" description="The serial input is not inverted." /> + <Enum name="NOT_INVERTED" start="1" description="The serial input is inverted. This has no effect on the serial output." /> + </BitField> + <BitField start="2" size="1" name="FIXPULSEEN" description="IrDA fixed pulse width mode."> + <Enum name="DISABLED" start="0" description="IrDA fixed pulse width mode disabled." /> + <Enum name="ENABLED" start="1" description="IrDA fixed pulse width mode enabled." /> + </BitField> + <BitField start="3" size="3" name="PULSEDIV" description="Configures the pulse width when FixPulseEn = 1."> + <Enum name="3_DIV_16_X_BAUD_RATE" start="0x0" description="3 / (16 x baud rate)" /> + <Enum name="2_X_TPCLK" start="0x1" description="2 x TPCLK" /> + <Enum name="4_X_TPCLK" start="0x2" description="4 x TPCLK" /> + <Enum name="8_X_TPCLK" start="0x3" description="8 x TPCLK" /> + <Enum name="16_X_TPCLK" start="0x4" description="16 x TPCLK" /> + <Enum name="32_X_TPCLK" start="0x5" description="32 x TPCLK" /> + <Enum name="64_X_TPCLK" start="0x6" description="64 x TPCLK" /> + <Enum name="128_X_TPCLK" start="0x7" description="128 x TPCLK" /> + </BitField> + <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x028" size="4" name="FDR" access="Read/Write" description="Fractional Divider Register. Generates a clock input for the baud rate divider." reset_value="0x10" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="4" name="DIVADDVAL" description="Baud rate generation pre-scaler divisor value. If this field is 0, fractional baud rate generator will not impact the USART baud rate." /> + <BitField start="4" size="4" name="MULVAL" description="Baud rate pre-scaler multiplier value. This field must be greater or equal 1 for USART to operate properly, regardless of whether the fractional baud rate generator is used or not." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x02C" size="4" name="OSR" access="Read/Write" description="Oversampling Register. Controls the degree of oversampling during each bit time." reset_value="0xF0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + <BitField start="1" size="3" name="OSFRAC" description="Fractional part of the oversampling ratio, in units of 1/8th of an input clock period. (001 = 0.125, ..., 111 = 0.875)" /> + <BitField start="4" size="4" name="OSINT" description="Integer part of the oversampling ratio, minus 1. The reset values equate to the normal operating mode of 16 input clocks per bit time." /> + <BitField start="8" size="7" name="FDINT" description="In Smart Card mode, these bits act as a more-significant extension of the OSint field, allowing an oversampling ratio up to 2048 as required by ISO7816-3. In Smart Card mode, bits 14:4 should initially be set to 371, yielding an oversampling ratio of 372." /> + <BitField start="15" size="17" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x030" size="4" name="TER" access="Read/Write" description="Transmit Enable Register. Turns off USART transmitter for use with software flow control." reset_value="0x80" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="7" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + <BitField start="7" size="1" name="TXEN" description="When this bit is 1, as it is after a Reset, data written to the THR is output on the TXD pin as soon as any preceding data has been sent. If this bit cleared to 0 while a character is being sent, the transmission of that character is completed, but no further characters are sent until this bit is set again. In other words, a 0 in this bit blocks the transfer of characters from the THR or TX FIFO into the transmit shift register. Software can clear this bit when it detects that the a hardware-handshaking TX-permit signal (CTS) has gone false, or with software handshaking, when it receives an XOFF character (DC3). Software can set this bit again when it detects that the TX-permit signal has gone true, or when it receives an XON (DC1) character." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x040" size="4" name="HDEN" access="Read/Write" description="Half duplex enable register." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="HDEN" description="Half-duplex mode enable"> + <Enum name="DISABLE_HALF_DUPLEX_" start="0" description="Disable half-duplex mode." /> + <Enum name="ENABLE_HALF_DUPLEX_M" start="1" description="Enable half-duplex mode." /> + </BitField> + <BitField start="1" size="31" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x048" size="4" name="SCICTRL" access="Read/Write" description="Smart Card Interface Control register. Enables and configures the Smart Card Interface feature." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="SCIEN" description="Smart Card Interface Enable."> + <Enum name="SMART_CARD_INTERFACE" start="0" description="Smart card interface disabled." /> + <Enum name="ASYNCHRONOUS_HALF_DU" start="1" description="Asynchronous half duplex smart card interface is enabled." /> + </BitField> + <BitField start="1" size="1" name="NACKDIS" description="NACK response disable. Only applicable in T=0."> + <Enum name="ENABLED" start="0" description="A NACK response is enabled." /> + <Enum name="DISABLED" start="1" description="A NACK response is inhibited." /> + </BitField> + <BitField start="2" size="1" name="PROTSEL" description="Protocol selection as defined in the ISO7816-3 standard."> + <Enum name="T_EQ_0" start="0" description="T = 0" /> + <Enum name="T_EQ_1" start="1" description="T = 1" /> + </BitField> + <BitField start="3" size="2" name="RESERVED" description="Reserved." /> + <BitField start="5" size="3" name="TXRETRY" description="When the protocol selection T bit (above) is 0, the field controls the maximum number of retransmissions that the USART will attempt if the remote device signals NACK. When NACK has occurred this number of times plus one, the Tx Error bit in the LSR is set, an interrupt is requested if enabled, and the USART is locked until the FIFO is cleared." /> + <BitField start="8" size="8" name="XTRAGUARD" description="When the protocol selection T bit (above) is 0, this field indicates the number of bit times (ETUs) by which the guard time after a character transmitted by the USART should exceed the nominal 2 bit times. 0xFF in this field may indicate that there is just a single bit after a character and 11 bit times/character" /> + <BitField start="16" size="16" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x04C" size="4" name="RS485CTRL" access="Read/Write" description="RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="NMMEN" description="NMM enable."> + <Enum name="RS_485_EIA_485_NORMA" start="0" description="RS-485/EIA-485 Normal Multidrop Mode (NMM) is disabled." /> + <Enum name="RS_485_EIA_485_NORMA" start="1" description="RS-485/EIA-485 Normal Multidrop Mode (NMM) is enabled. In this mode, an address is detected when a received byte causes the USART to set the parity error and generate an interrupt." /> + </BitField> + <BitField start="1" size="1" name="RXDIS" description="Receiver enable."> + <Enum name="THE_RECEIVER_IS_ENAB" start="0" description="The receiver is enabled." /> + <Enum name="THE_RECEIVER_IS_DISA" start="1" description="The receiver is disabled." /> + </BitField> + <BitField start="2" size="1" name="AADEN" description="AAD enable."> + <Enum name="AUTO_ADDRESS_DETECT_" start="0" description="Auto Address Detect (AAD) is disabled." /> + <Enum name="AUTO_ADDRESS_DETECT_" start="1" description="Auto Address Detect (AAD) is enabled." /> + </BitField> + <BitField start="3" size="1" name="SEL" description="Select direction control pin"> + <Enum name="RTS" start="0" description="If direction control is enabled (bit DCTRL = 1), pin RTS is used for direction control." /> + <Enum name="DTR" start="1" description="If direction control is enabled (bit DCTRL = 1), pin DTR is used for direction control." /> + </BitField> + <BitField start="4" size="1" name="DCTRL" description="Auto direction control enable."> + <Enum name="DISABLE_AUTO_DIRECTI" start="0" description="Disable Auto Direction Control." /> + <Enum name="ENABLE_AUTO_DIRECTIO" start="1" description="Enable Auto Direction Control." /> + </BitField> + <BitField start="5" size="1" name="OINV" description="Polarity control. This bit reverses the polarity of the direction control signal on the RTS (or DTR) pin."> + <Enum name="LOW" start="0" description="The direction control pin will be driven to logic 0 when the transmitter has data to be sent. It will be driven to logic 1 after the last bit of data has been transmitted." /> + <Enum name="HIGH" start="1" description="The direction control pin will be driven to logic 1 when the transmitter has data to be sent. It will be driven to logic 0 after the last bit of data has been transmitted." /> + </BitField> + <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x050" size="4" name="RS485ADRMATCH" access="Read/Write" description="RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="ADRMATCH" description="Contains the address match value." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x054" size="4" name="RS485DLY" access="Read/Write" description="RS-485/EIA-485 direction control delay." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="DLY" description="Contains the direction control (RTS or DTR) delay value. This register works in conjunction with an 8-bit counter." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x058" size="4" name="SYNCCTRL" access="Read/Write" description="Synchronous mode control register." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="SYNC" description="Enables synchronous mode."> + <Enum name="DISABLED" start="0" description="Disabled" /> + <Enum name="ENABLED" start="1" description="Enabled" /> + </BitField> + <BitField start="1" size="1" name="CSRC" description="Clock source select."> + <Enum name="SYNCHRONOUS_SLAVE_MO" start="0" description="Synchronous slave mode (SCLK in)" /> + <Enum name="SYNCHRONOUS_MASTER_M" start="1" description="Synchronous master mode (SCLK out)" /> + </BitField> + <BitField start="2" size="1" name="FES" description="Falling edge sampling."> + <Enum name="RISING" start="0" description="RxD is sampled on the rising edge of SCLK " /> + <Enum name="FALLING" start="1" description="RxD is sampled on the falling edge of SCLK" /> + </BitField> + <BitField start="3" size="1" name="TSBYPASS" description="Transmit synchronization bypass in synchronous slave mode."> + <Enum name="SYNC" start="0" description="The input clock is synchronized prior to being used in clock edge detection logic" /> + <Enum name="NOSYNC" start="1" description="The input clock is not synchronized prior to being used in clock edge detection logic. This allows for a high er input clock rate at the expense of potential metastability." /> + </BitField> + <BitField start="4" size="1" name="CSCEN" description="Continuous master clock enable (used only when CSRC is 1)"> + <Enum name="SCLK_CYCLES_ONLY_WHE" start="0" description="SCLK cycles only when characters are being sent on TxD" /> + <Enum name="SCLK_RUNS_CONTINUOUS" start="1" description="SCLK runs continuously (characters can be received on RxD independently from transmission on TxD)" /> + </BitField> + <BitField start="5" size="1" name="SSDIS" description="Start/stop bits"> + <Enum name="SEND_START_STOP" start="0" description="Send start and stop bits as in other modes." /> + <Enum name="NOT_SEND_START_STOP" start="1" description="Do not send start/stop bits." /> + </BitField> + <BitField start="6" size="1" name="CCCLR" description="Continuous clock clear"> + <Enum name="CSCEN_IS_UNDER_SOFTW" start="0" description="CSCEN is under software control." /> + <Enum name="HARDWARE_CLEARS_CSCE" start="1" description="Hardware clears CSCEN after each character is received." /> + </BitField> + <BitField start="7" size="25" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + </RegisterGroup> + <RegisterGroup name="ADC" start="0x4001C000" description="ADC"> + <Register start="+0x000" size="4" name="CR" access="Read/Write" description="A/D Control Register. The CR register must be written to select the operating mode before A/D conversion can occur." reset_value="0x00000000" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="SEL" description="Selects which of the AD7:0 pins is (are) to be sampled and converted. Bit 0 selects Pin AD0, bit 1 selects pin AD1,..., and bit 7 selects pin AD7. In software-controlled mode (BURST = 0), only one channel can be selected, i.e. only one of these bits should be 1. In hardware scan mode (BURST = 1), any numbers of channels can be selected, i.e any or all bits can be set to 1. If all bits are set to 0, channel 0 is selected automatically (SEL = 0x01)." /> + <BitField start="8" size="8" name="CLKDIV" description="The main clock (PCLK_ADC) is divided by (this value plus one) to produce the clock for the A/D converter. The clock should be less than or equal to 15.5 MHz(12-bit mode) or 31 MHz (10-bit mode) in software-controlled mode (BURST bit = 0).. Typically, software should program the smallest value in this field that yields a clock of 15.5 MHz or slightly less, but in certain cases (such as a high-impedance analog source) a slower clock may be desirable." /> + <BitField start="16" size="1" name="BURST" description="Burst mode If BURST is set to 1, the ADGINTEN bit in the INTEN register (Table 327) must be set to 0."> + <Enum name="SOFTWARE_CONTROLLED_" start="0" description="Software-controlled mode: Conversions are software-controlled and require 31 clocks." /> + <Enum name="HARDWARE_SCAN_MODE_" start="1" description="Hardware scan mode: The AD converter does repeated conversions at the rate selected by the CLKS field, scanning (if necessary) through the pins selected by ones in the SEL field. The first conversion after the start corresponds to the least-significant bit set to 1 in the SEL field, then the next higher bits (pins) set to one are scanned if applicable. Repeated conversions can be terminated by clearing this bit, but the conversion in progress when this bit is cleared will be completed. Important: START bits must be 000 when BURST = 1, or conversions will not start." /> + </BitField> + <BitField start="17" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + <BitField start="21" size="1" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + <BitField start="22" size="1" name="LPWRMODE" description="Low-power mode"> + <Enum name="DISABLE_THE_LOW_POWE" start="0" description="Disable the low-power ADC mode. The analog circuitry remains activated when no conversions are requested." /> + <Enum name="ENABLE_THE_LOW_POWER" start="1" description="Enable the low-power ADC mode. The analog circuitry is automatically powered-down when no conversions are taking place. When any (hardware or software) triggering event is detected, the analog circuitry is enabled. After the required start-up time, the requested conversion will be launched. Once the conversion completes, the analog-circuitry will again be powered-down provided no further conversions are pending. This mode will NOT power-up the A/D if the ADC is powered down (ADC_PD bit in the PDRUNCFG register is HIGH) or if the part is in Deep-sleep, Power-down, or Deep power-down mode." /> + </BitField> + <BitField start="23" size="1" name="MODE10BIT" description="10-bit conversion rate mode"> + <Enum name="DISABLE_THE_10_BIT_C" start="0" description="Disable the 10-bit conversion rate mode." /> + <Enum name="ENABLE_THE_10_BIT_CO" start="1" description="Enable the 10-bit conversion rate mode with high conversion rate.The A/D resolution is reduced to 10 bits (the two LSB of the conversion result will be forced to 0). The clock rate (set via the CLKDIV field) can be doubled to up to 31 MHz to achieve a conversion rate of up to one million samples per second." /> + </BitField> + <BitField start="24" size="3" name="START" description="When the BURST bit is 0, these bits control whether and when an A/D conversion is started:"> + <Enum name="NO_START_THIS_VALUE" start="0x0" description="No start (this value should be used when clearing PDN to 0)." /> + <Enum name="START_CONVERSION_NOW" start="0x1" description="Start conversion now." /> + <Enum name="PIO0_2" start="0x2" description="Start conversion when the edge selected by bit 27 occurs on PIO0_2/SSEL/CT16B0_CAP0." /> + <Enum name="PIO1_5" start="0x3" description="Start conversion when the edge selected by bit 27 occurs on PIO1_5/DIR/CT32B0_CAP0." /> + <Enum name="CT32B0_MAT0" start="0x4" description="Start conversion when the edge selected by bit 27 occurs on CT32B0_MAT0[1]." /> + <Enum name="CT32B0_MAT1" start="0x5" description="Start conversion when the edge selected by bit 27 occurs on CT32B0_MAT1[1]." /> + <Enum name="CT16B0_MAT0" start="0x6" description="Start conversion when the edge selected by bit 27 occurs on CT16B0_MAT0[1]." /> + <Enum name="CT16B0_MAT1" start="0x7" description="Start conversion when the edge selected by bit 27 occurs on CT16B0_MAT1[1]." /> + </BitField> + <BitField start="27" size="1" name="EDGE" description="Edge control. This bit is significant only when the START field contains 010-111."> + <Enum name="RISING" start="0" description="Start conversion on a rising edge on the selected CAP/MAT signal." /> + <Enum name="FALLING" start="1" description="Start conversion on a falling edge on the selected CAP/MAT signal." /> + </BitField> + <BitField start="28" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x004" size="4" name="GDR" access="Read/Write" description="A/D Global Data Register. Contains the result of the most recent A/D conversion." reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="4" name="RESERVED" description="Reserved. These bits always read as zeros." /> + <BitField start="4" size="12" name="V_VREF" description="When DONE is 1, this field contains a binary fraction representing the voltage on the ADn pin selected by the SEL field, divided by the voltage on the VDD pin or as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on the ADn pin was less than, equal to, or close to that on VSS/VREFN, while 0xFFF indicates that the voltage on ADn was close to, equal to, or greater than that on VDD/VREFP." /> + <BitField start="16" size="8" name="RESERVED" description="Reserved. These bits always read as zeros." /> + <BitField start="24" size="3" name="CHN" description="These bits contain the channel from which the result bits V_VREF were converted." /> + <BitField start="27" size="3" name="RESERVED" description="Reserved. These bits always read as zeros." /> + <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits." /> + <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read and when the ADCR is written. If the ADCR is written while a conversion is still in progress, this bit is set and a new conversion is started." /> + </Register> + <Register start="+0x00C" size="4" name="INTEN" access="Read/Write" description="A/D Interrupt Enable Register. This register contains enable bits that allow the DONE flag of each A/D channel to be included or excluded from contributing to the generation of an A/D interrupt." reset_value="0x00000100" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="ADINTEN" description="These bits allow control over which A/D channels generate interrupts for conversion completion. When bit 0 is one, completion of a conversion on A/D channel 0 will generate an interrupt, when bit 1 is one, completion of a conversion on A/D channel 1 will generate an interrupt, etc." /> + <BitField start="8" size="1" name="ADGINTEN" description="When 1, enables the global DONE flag in ADDR to generate an interrupt. When 0, only the individual A/D channels enabled by ADINTEN 7:0 will generate interrupts. This bit must be set to 0 in burst mode (BURST = 1 in the CR register)." /> + <BitField start="9" size="23" name="RESERVED" description="Reserved. Unused, always 0." /> + </Register> + <Register start="+0x010+0" size="4" name="DR[0]" access="Read/Write" description="A/D Channel N Data
Register. This register contains the result of the most recent conversion
completed on channel n" reset_value="0x00000100" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="4" name="RESERVED" description="Reserved." /> + <BitField start="4" size="12" name="V_VREF" description="When DONE is 1, this field contains a binary fraction representing the voltage on the ADn pin as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on the ADn pin was less than, equal to, or close to that on VREFN/VSS, while 0xFFF indicates that the voltage on AD input was close to, equal to, or greater than that on VREFP/VDD." /> + <BitField start="16" size="14" name="RESERVED" description="Reserved." /> + <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits.This bit is cleared by reading this register." /> + <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." /> + </Register> + <Register start="+0x010+4" size="4" name="DR[1]" access="Read/Write" description="A/D Channel N Data
Register. This register contains the result of the most recent conversion
completed on channel n" reset_value="0x00000100" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="4" name="RESERVED" description="Reserved." /> + <BitField start="4" size="12" name="V_VREF" description="When DONE is 1, this field contains a binary fraction representing the voltage on the ADn pin as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on the ADn pin was less than, equal to, or close to that on VREFN/VSS, while 0xFFF indicates that the voltage on AD input was close to, equal to, or greater than that on VREFP/VDD." /> + <BitField start="16" size="14" name="RESERVED" description="Reserved." /> + <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits.This bit is cleared by reading this register." /> + <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." /> + </Register> + <Register start="+0x010+8" size="4" name="DR[2]" access="Read/Write" description="A/D Channel N Data
Register. This register contains the result of the most recent conversion
completed on channel n" reset_value="0x00000100" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="4" name="RESERVED" description="Reserved." /> + <BitField start="4" size="12" name="V_VREF" description="When DONE is 1, this field contains a binary fraction representing the voltage on the ADn pin as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on the ADn pin was less than, equal to, or close to that on VREFN/VSS, while 0xFFF indicates that the voltage on AD input was close to, equal to, or greater than that on VREFP/VDD." /> + <BitField start="16" size="14" name="RESERVED" description="Reserved." /> + <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits.This bit is cleared by reading this register." /> + <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." /> + </Register> + <Register start="+0x010+12" size="4" name="DR[3]" access="Read/Write" description="A/D Channel N Data
Register. This register contains the result of the most recent conversion
completed on channel n" reset_value="0x00000100" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="4" name="RESERVED" description="Reserved." /> + <BitField start="4" size="12" name="V_VREF" description="When DONE is 1, this field contains a binary fraction representing the voltage on the ADn pin as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on the ADn pin was less than, equal to, or close to that on VREFN/VSS, while 0xFFF indicates that the voltage on AD input was close to, equal to, or greater than that on VREFP/VDD." /> + <BitField start="16" size="14" name="RESERVED" description="Reserved." /> + <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits.This bit is cleared by reading this register." /> + <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." /> + </Register> + <Register start="+0x010+16" size="4" name="DR[4]" access="Read/Write" description="A/D Channel N Data
Register. This register contains the result of the most recent conversion
completed on channel n" reset_value="0x00000100" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="4" name="RESERVED" description="Reserved." /> + <BitField start="4" size="12" name="V_VREF" description="When DONE is 1, this field contains a binary fraction representing the voltage on the ADn pin as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on the ADn pin was less than, equal to, or close to that on VREFN/VSS, while 0xFFF indicates that the voltage on AD input was close to, equal to, or greater than that on VREFP/VDD." /> + <BitField start="16" size="14" name="RESERVED" description="Reserved." /> + <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits.This bit is cleared by reading this register." /> + <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." /> + </Register> + <Register start="+0x010+20" size="4" name="DR[5]" access="Read/Write" description="A/D Channel N Data
Register. This register contains the result of the most recent conversion
completed on channel n" reset_value="0x00000100" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="4" name="RESERVED" description="Reserved." /> + <BitField start="4" size="12" name="V_VREF" description="When DONE is 1, this field contains a binary fraction representing the voltage on the ADn pin as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on the ADn pin was less than, equal to, or close to that on VREFN/VSS, while 0xFFF indicates that the voltage on AD input was close to, equal to, or greater than that on VREFP/VDD." /> + <BitField start="16" size="14" name="RESERVED" description="Reserved." /> + <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits.This bit is cleared by reading this register." /> + <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." /> + </Register> + <Register start="+0x010+24" size="4" name="DR[6]" access="Read/Write" description="A/D Channel N Data
Register. This register contains the result of the most recent conversion
completed on channel n" reset_value="0x00000100" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="4" name="RESERVED" description="Reserved." /> + <BitField start="4" size="12" name="V_VREF" description="When DONE is 1, this field contains a binary fraction representing the voltage on the ADn pin as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on the ADn pin was less than, equal to, or close to that on VREFN/VSS, while 0xFFF indicates that the voltage on AD input was close to, equal to, or greater than that on VREFP/VDD." /> + <BitField start="16" size="14" name="RESERVED" description="Reserved." /> + <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits.This bit is cleared by reading this register." /> + <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." /> + </Register> + <Register start="+0x010+28" size="4" name="DR[7]" access="Read/Write" description="A/D Channel N Data
Register. This register contains the result of the most recent conversion
completed on channel n" reset_value="0x00000100" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="4" name="RESERVED" description="Reserved." /> + <BitField start="4" size="12" name="V_VREF" description="When DONE is 1, this field contains a binary fraction representing the voltage on the ADn pin as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on the ADn pin was less than, equal to, or close to that on VREFN/VSS, while 0xFFF indicates that the voltage on AD input was close to, equal to, or greater than that on VREFP/VDD." /> + <BitField start="16" size="14" name="RESERVED" description="Reserved." /> + <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits.This bit is cleared by reading this register." /> + <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." /> + </Register> + <Register start="+0x030" size="4" name="STAT" access="ReadOnly" description="A/D Status Register. This register contains DONE and OVERRUN flags for all of the A/D channels, as well as the A/D interrupt flag." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="DONE" description="These bits mirror the DONE status flags that appear in the result register for each A/D channel n." /> + <BitField start="8" size="8" name="OVERRUN" description="These bits mirror the OVERRRUN status flags that appear in the result register for each A/D channel n. Reading ADSTAT allows checking the status of all A/D channels simultaneously." /> + <BitField start="16" size="1" name="ADINT" description="This bit is the A/D interrupt flag. It is one when any of the individual A/D channel Done flags is asserted and enabled to contribute to the A/D interrupt via the ADINTEN register." /> + <BitField start="17" size="15" name="RESERVED" description="Reserved. Unused, always 0." /> + </Register> + <Register start="+0x034" size="4" name="TRM" access="Read/Write" description="A/D trim register" reset_value="0xF00" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="4" name="RESERVED" description="Reserved." /> + <BitField start="4" size="4" name="ADCOFFS" description="Offset trim bits for ADC operation. Initialized by the boot code. Can be overwritten by the user." /> + <BitField start="8" size="4" name="TRIM" description="Written-to by boot code. Can not be overwritten by the user. These bits are locked after boot code write." /> + <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + </RegisterGroup> + <RegisterGroup name="PMU" start="0x40038000" description="Power Management Unit (PMU)"> + <Register start="+0x000" size="4" name="PCON" access="Read/Write" description="Power control register" reset_value="0x0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="PM" description="Power mode"> + <Enum name="DEFAULT" start="0x0" description="Default. The part is in active or sleep mode." /> + <Enum name="DEEPSLEEP" start="0x1" description="ARM WFI will enter Deep-sleep mode." /> + <Enum name="POWERDOWN" start="0x2" description="ARM WFI will enter Power-down mode." /> + <Enum name="DEEPPOWERDOWN" start="0x3" description="ARM WFI will enter Deep-power down mode (ARM Cortex-M0 core powered-down)." /> + </BitField> + <BitField start="3" size="1" name="NODPD" description="A 1 in this bit prevents entry to Deep power-down mode when 0x3 is written to the PM field above, the SLEEPDEEP bit is set, and a WFI is executed. Execution continues after the WFI if this bit is 1. This bit is cleared only by power-on reset, so writing a one to this bit locks the part in a mode in which Deep power-down mode is blocked." /> + <BitField start="4" size="4" name="RESERVED" description="Reserved. Do not write ones to this bit." /> + <BitField start="8" size="1" name="SLEEPFLAG" description="Sleep mode flag"> + <Enum name="NOPOWERDOWN" start="0" description="Read: No power-down mode entered. LPC11U1x is in Active mode. Write: No effect." /> + <Enum name="POWERDOWN" start="1" description="Read: Sleep/Deep-sleep or Deep power-down mode entered. Write: Writing a 1 clears the SLEEPFLAG bit to 0." /> + </BitField> + <BitField start="9" size="2" name="RESERVED" description="Reserved. Do not write ones to this bit." /> + <BitField start="11" size="1" name="DPDFLAG" description="Deep power-down flag"> + <Enum name="DPNOTENTERED" start="0" description="Read: Deep power-down mode not entered. Write: No effect." /> + <Enum name="DPENTERED" start="1" description="Read: Deep power-down mode entered. Write: Clear the Deep power-down flag." /> + </BitField> + <BitField start="12" size="20" name="RESERVED" description="Reserved. Do not write ones to this bit." /> + </Register> + <Register start="+0x004+0" size="4" name="GPREG0" access="Read/Write" description="General purpose register 0" reset_value="0x0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="GPDATA" description="Data retained during Deep power-down mode." /> + </Register> + <Register start="+0x004+4" size="4" name="GPREG1" access="Read/Write" description="General purpose register 0" reset_value="0x0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="GPDATA" description="Data retained during Deep power-down mode." /> + </Register> + <Register start="+0x004+8" size="4" name="GPREG2" access="Read/Write" description="General purpose register 0" reset_value="0x0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="GPDATA" description="Data retained during Deep power-down mode." /> + </Register> + <Register start="+0x004+12" size="4" name="GPREG3" access="Read/Write" description="General purpose register 0" reset_value="0x0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="GPDATA" description="Data retained during Deep power-down mode." /> + </Register> + <Register start="+0x014" size="4" name="GPREG4" access="Read/Write" description="General purpose register 4" reset_value="0x0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="10" name="RESERVED" description="Reserved. Do not write ones to this bit." /> + <BitField start="10" size="1" name="WAKEUPHYS" description="WAKEUP pin hysteresis enable"> + <Enum name="DISABLED" start="0" description="Hysteresis for WAKEUP pin disabled." /> + <Enum name="ENABLED" start="1" description="Hysteresis for WAKEUP pin enabled." /> + </BitField> + <BitField start="11" size="21" name="GPDATA" description="Data retained during Deep power-down mode." /> + </Register> + </RegisterGroup> + <RegisterGroup name="FLASHCTRL" start="0x4003C000" description="Flash programming firmware "> + <Register start="+0x09C" size="4" name="EEMSSTART" access="Read/Write" description="EEPROM BIST start address register" reset_value="0x0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="14" name="STARTA" description="BIST start address: Bit 0 is fixed zero since only even addresses are allowed." /> + <BitField start="14" size="18" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x0A0" size="4" name="EEMSSTOP" access="Read/Write" description="EEPROM BIST stop address register" reset_value="0x0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="14" name="STOPA" description="BIST stop address: Bit 0 is fixed zero since only even addresses are allowed." /> + <BitField start="14" size="16" name="RESERVED" description="Reserved" /> + <BitField start="30" size="1" name="DEVSEL" description="BIST device select bit 0: the BIST signature is generated over the total memory space. Singe pages are interleaved over the EEPROM devices when multiple devices are used, the signature is generated over memory of multiple devices. 1: the BIST signature is generated only over a memory range located on a single EEPROM device. Therefore the internal address generation is done such that the address' CS bits are kept stable to select only the same device. The address' MSB and LSB bits are used to step through the memory range specified by the start and stop address fields. Note: if this bit is set the start and stop address fields must be programmed such that they both address the same EEPROM device. Therefore the address' CS bits in both the start and stop address must be the same." /> + <BitField start="31" size="1" name="STRTBIST" description="BIST start bit Setting this bit will start the BIST. This bit is self-clearing." /> + </Register> + <Register start="+0x0A4" size="4" name="EEMSSIG" access="ReadOnly" description="EEPROM 24-bit BIST signature register" reset_value="0x0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="16" name="DATA_SIG" description="BIST 16-bit signature calculated from only the data bytes" /> + <BitField start="16" size="16" name="PARITY_SIG" description="BIST 16-bit signature calculated from only the parity bits of the data bytes" /> + </Register> + <Register start="+0x010" size="4" name="FLASHCFG" access="Read/Write" description="Flash memory access time configuration register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="2" name="FLASHTIM" description="Flash memory access time. FLASHTIM +1 is equal to the number of system clocks used for flash access."> + <Enum name="1_SYSTEM_CLOCK_FLASH" start="0x0" description="1 system clock flash access time (for system clock frequencies of up to 20 MHz)." /> + <Enum name="2_SYSTEM_CLOCKS_FLAS" start="0x1" description="2 system clocks flash access time (for system clock frequencies of up to 40 MHz)." /> + <Enum name="3_SYSTEM_CLOCKS_FLAS" start="0x2" description="3 system clocks flash access time (for system clock frequencies of up to 50 MHz)." /> + </BitField> + <BitField start="2" size="30" name="RESERVED" description="Reserved. User software must not change the value of these bits. Bits 31:2 must be written back exactly as read." /> + </Register> + <Register start="+0x020" size="4" name="FMSSTART" access="Read/Write" description="Signature start address register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="17" name="START" description="Signature generation start address (corresponds to AHB byte address bits[20:4])." /> + <BitField start="17" size="15" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x024" size="4" name="FMSSTOP" access="Read/Write" description="Signature stop-address register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="17" name="STOP" description="BIST stop address divided by 16 (corresponds to AHB byte address [20:4])." /> + <BitField start="17" size="1" name="SIG_START" description="Start control bit for signature generation."> + <Enum name="SIGNATURE_GENERATION" start="0" description="Signature generation is stopped" /> + <Enum name="INITIATE_SIGNATURE_G" start="1" description="Initiate signature generation" /> + </BitField> + <BitField start="18" size="14" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x02C" size="4" name="FMSW0" access="ReadOnly" description="Word 0 [31:0]" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="SW0_31_0" description="Word 0 of 128-bit signature (bits 31 to 0)." /> + </Register> + <Register start="+0x030" size="4" name="FMSW1" access="ReadOnly" description="Word 1 [63:32]" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="SW1_63_32" description="Word 1 of 128-bit signature (bits 63 to 32)." /> + </Register> + <Register start="+0x034" size="4" name="FMSW2" access="ReadOnly" description="Word 2 [95:64]" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="SW2_95_64" description="Word 2 of 128-bit signature (bits 95 to 64)." /> + </Register> + <Register start="+0x038" size="4" name="FMSW3" access="ReadOnly" description="Word 3 [127:96]" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="SW3_127_96" description="Word 3 of 128-bit signature (bits 127 to 96)." /> + </Register> + <Register start="+0xFE0" size="4" name="FMSTAT" access="ReadOnly" description="Signature generation status register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + <BitField start="2" size="1" name="SIG_DONE" description="When 1, a previously started signature generation has completed. See FMSTATCLR register description for clearing this flag." /> + <BitField start="3" size="29" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0xFE8" size="4" name="FMSTATCLR" access="WriteOnly" description="Signature generation status clear register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + <BitField start="2" size="1" name="SIG_DONE_CLR" description="Writing a 1 to this bits clears the signature generation completion flag (SIG_DONE) in the FMSTAT register." /> + <BitField start="3" size="29" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + </RegisterGroup> + <RegisterGroup name="SSP0" start="0x40040000" description="SSP/SPI"> + <Register start="+0x000" size="4" name="CR0" access="Read/Write" description="Control Register 0. Selects the serial clock rate, bus type, and data size." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="4" name="DSS" description="Data Size Select. This field controls the number of bits transferred in each frame. Values 0000-0010 are not supported and should not be used."> + <Enum name="4_BIT_TRANSFER" start="0x3" description="4-bit transfer" /> + <Enum name="5_BIT_TRANSFER" start="0x4" description="5-bit transfer" /> + <Enum name="6_BIT_TRANSFER" start="0x5" description="6-bit transfer" /> + <Enum name="7_BIT_TRANSFER" start="0x6" description="7-bit transfer" /> + <Enum name="8_BIT_TRANSFER" start="0x7" description="8-bit transfer" /> + <Enum name="9_BIT_TRANSFER" start="0x8" description="9-bit transfer" /> + <Enum name="10_BIT_TRANSFER" start="0x9" description="10-bit transfer" /> + <Enum name="11_BIT_TRANSFER" start="0xA" description="11-bit transfer" /> + <Enum name="12_BIT_TRANSFER" start="0xB" description="12-bit transfer" /> + <Enum name="13_BIT_TRANSFER" start="0xC" description="13-bit transfer" /> + <Enum name="14_BIT_TRANSFER" start="0xD" description="14-bit transfer" /> + <Enum name="15_BIT_TRANSFER" start="0xE" description="15-bit transfer" /> + <Enum name="16_BIT_TRANSFER" start="0xF" description="16-bit transfer" /> + </BitField> + <BitField start="4" size="2" name="FRF" description="Frame Format."> + <Enum name="SPI" start="0x0" description="SPI" /> + <Enum name="TI" start="0x1" description="TI" /> + <Enum name="MICROWIRE" start="0x2" description="Microwire" /> + <Enum name="RESERVED" start="0x3" description="This combination is not supported and should not be used." /> + </BitField> + <BitField start="6" size="1" name="CPOL" description="Clock Out Polarity. This bit is only used in SPI mode."> + <Enum name="LOW" start="0" description="SPI controller maintains the bus clock low between frames." /> + <Enum name="HIGH" start="1" description="SPI controller maintains the bus clock high between frames." /> + </BitField> + <BitField start="7" size="1" name="CPHA" description="Clock Out Phase. This bit is only used in SPI mode."> + <Enum name="FIRSTCLOCK" start="0" description="SPI controller captures serial data on the first clock transition of the frame, that is, the transition away from the inter-frame state of the clock line." /> + <Enum name="SECONDCLOCK" start="1" description="SPI controller captures serial data on the second clock transition of the frame, that is, the transition back to the inter-frame state of the clock line." /> + </BitField> + <BitField start="8" size="8" name="SCR" description="Serial Clock Rate. The number of prescaler output clocks per bit on the bus, minus one. Given that CPSDVSR is the prescale divider, and the APB clock PCLK clocks the prescaler, the bit frequency is PCLK / (CPSDVSR X [SCR+1])." /> + <BitField start="16" size="16" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x004" size="4" name="CR1" access="Read/Write" description="Control Register 1. Selects master/slave and other modes." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="LBM" description="Loop Back Mode."> + <Enum name="DURING_NORMAL_OPERAT" start="0" description="During normal operation." /> + <Enum name="SERIAL_INPUT_IS_TAKE" start="1" description="Serial input is taken from the serial output (MOSI or MISO) rather than the serial input pin (MISO or MOSI respectively)." /> + </BitField> + <BitField start="1" size="1" name="SSE" description="SPI Enable."> + <Enum name="DISABLED" start="0" description="The SPI controller is disabled." /> + <Enum name="ENABLED" start="1" description="The SPI controller will interact with other devices on the serial bus. Software should write the appropriate control information to the other SSP/SPI registers and interrupt controller registers, before setting this bit." /> + </BitField> + <BitField start="2" size="1" name="MS" description="Master/Slave Mode.This bit can only be written when the SSE bit is 0."> + <Enum name="MASTER" start="0" description="The SPI controller acts as a master on the bus, driving the SCLK, MOSI, and SSEL lines and receiving the MISO line." /> + <Enum name="SLAVE" start="1" description="The SPI controller acts as a slave on the bus, driving MISO line and receiving SCLK, MOSI, and SSEL lines." /> + </BitField> + <BitField start="3" size="1" name="SOD" description="Slave Output Disable. This bit is relevant only in slave mode (MS = 1). If it is 1, this blocks this SPI controller from driving the transmit data line (MISO)." /> + <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x008" size="4" name="DR" access="None" description="Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="16" name="DATA" description="Write: software can write data to be sent in a future frame to this register whenever the TNF bit in the Status register is 1, indicating that the Tx FIFO is not full. If the Tx FIFO was previously empty and the SPI controller is not busy on the bus, transmission of the data will begin immediately. Otherwise the data written to this register will be sent as soon as all previous data has been sent (and received). If the data length is less than 16 bit, software must right-justify the data written to this register. Read: software can read data from this register whenever the RNE bit in the Status register is 1, indicating that the Rx FIFO is not empty. When software reads this register, the SPI controller returns data from the least recent frame in the Rx FIFO. If the data length is less than 16 bit, the data is right-justified in this field with higher order bits filled with 0s." /> + <BitField start="16" size="16" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x00C" size="4" name="SR" access="ReadOnly" description="Status Register" reset_value="0x00000003" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="TFE" description="Transmit FIFO Empty. This bit is 1 is the Transmit FIFO is empty, 0 if not." /> + <BitField start="1" size="1" name="TNF" description="Transmit FIFO Not Full. This bit is 0 if the Tx FIFO is full, 1 if not." /> + <BitField start="2" size="1" name="RNE" description="Receive FIFO Not Empty. This bit is 0 if the Receive FIFO is empty, 1 if not." /> + <BitField start="3" size="1" name="RFF" description="Receive FIFO Full. This bit is 1 if the Receive FIFO is full, 0 if not." /> + <BitField start="4" size="1" name="BSY" description="Busy. This bit is 0 if the SPI controller is idle, 1 if it is currently sending/receiving a frame and/or the Tx FIFO is not empty." /> + <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x010" size="4" name="CPSR" access="Read/Write" description="Clock Prescale Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="CPSDVSR" description="This even value between 2 and 254, by which SPI_PCLK is divided to yield the prescaler output clock. Bit 0 always reads as 0." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x014" size="4" name="IMSC" access="Read/Write" description="Interrupt Mask Set and Clear Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RORIM" description="Software should set this bit to enable interrupt when a Receive Overrun occurs, that is, when the Rx FIFO is full and another frame is completely received. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs." /> + <BitField start="1" size="1" name="RTIM" description="Software should set this bit to enable interrupt when a Receive Time-out condition occurs. A Receive Time-out occurs when the Rx FIFO is not empty, and no has not been read for a time-out period. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1])." /> + <BitField start="2" size="1" name="RXIM" description="Software should set this bit to enable interrupt when the Rx FIFO is at least half full." /> + <BitField start="3" size="1" name="TXIM" description="Software should set this bit to enable interrupt when the Tx FIFO is at least half empty." /> + <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x018" size="4" name="RIS" access="ReadOnly" description="Raw Interrupt Status Register" reset_value="0x00000008" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RORRIS" description="This bit is 1 if another frame was completely received while the RxFIFO was full. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs." /> + <BitField start="1" size="1" name="RTRIS" description="This bit is 1 if the Rx FIFO is not empty, and has not been read for a time-out period. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1])." /> + <BitField start="2" size="1" name="RXRIS" description="This bit is 1 if the Rx FIFO is at least half full." /> + <BitField start="3" size="1" name="TXRIS" description="This bit is 1 if the Tx FIFO is at least half empty." /> + <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x01C" size="4" name="MIS" access="ReadOnly" description="Masked Interrupt Status Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RORMIS" description="This bit is 1 if another frame was completely received while the RxFIFO was full, and this interrupt is enabled." /> + <BitField start="1" size="1" name="RTMIS" description="This bit is 1 if the Rx FIFO is not empty, has not been read for a time-out period, and this interrupt is enabled. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1])." /> + <BitField start="2" size="1" name="RXMIS" description="This bit is 1 if the Rx FIFO is at least half full, and this interrupt is enabled." /> + <BitField start="3" size="1" name="TXMIS" description="This bit is 1 if the Tx FIFO is at least half empty, and this interrupt is enabled." /> + <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x020" size="4" name="ICR" access="WriteOnly" description="SSPICR Interrupt Clear Register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="RORIC" description="Writing a 1 to this bit clears the frame was received when RxFIFO was full interrupt." /> + <BitField start="1" size="1" name="RTIC" description="Writing a 1 to this bit clears the Rx FIFO was not empty and has not been read for a timeout period interrupt. The timeout period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1])." /> + <BitField start="2" size="30" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + </RegisterGroup> + <RegisterGroup name="IOCON" start="0x40044000" description="IO ocnfiguration"> + <Register start="+0x000" size="4" name="RESET_PIO0_0" access="Read/Write" description="I/O configuration for pin RESET/PIO0_0" reset_value="0x0000090" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function. Values 0x2 to 0x7 are reserved."> + <Enum name="RESET_" start="0x0" description="RESET." /> + <Enum name="PIO0_0_" start="0x1" description="PIO0_0." /> + </BitField> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." /> + </BitField> + <BitField start="7" size="3" name="RESERVED" description="Reserved." /> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x004" size="4" name="PIO0_1" access="Read/Write" description="I/O configuration for pin PIO0_1/CLKOUT/CT32B0_MAT2/ USB_FTOGGLE" reset_value="0x0000090" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function. Values 0x4 to 0x7 are reserved."> + <Enum name="PIO0_1_" start="0x0" description="PIO0_1." /> + <Enum name="CLKOUT_" start="0x1" description="CLKOUT." /> + <Enum name="CT32B0_MAT2_" start="0x2" description="CT32B0_MAT2." /> + <Enum name="USB_FTOGGLE_" start="0x3" description="USB_FTOGGLE." /> + </BitField> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." /> + </BitField> + <BitField start="7" size="3" name="RESERVED" description="Reserved." /> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x008" size="4" name="PIO0_2" access="Read/Write" description="I/O configuration for pin PIO0_2/SSEL0/CT16B0_CAP0" reset_value="0x0000090" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function. Values 0x3 to 0x7 are reserved."> + <Enum name="PIO0_2_" start="0x0" description="PIO0_2." /> + <Enum name="SSEL0_" start="0x1" description="SSEL0." /> + <Enum name="CT16B0_CAP0_" start="0x2" description="CT16B0_CAP0." /> + </BitField> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." /> + </BitField> + <BitField start="7" size="3" name="RESERVED" description="Reserved." /> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x00C" size="4" name="PIO0_3" access="Read/Write" description="I/O configuration for pin PIO0_3/USB_VBUS" reset_value="0x0000090" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function. Values 0x2 to 0x7 are reserved."> + <Enum name="PIO0_3_" start="0x0" description="PIO0_3." /> + <Enum name="USB_VBUS_" start="0x1" description="USB_VBUS." /> + </BitField> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." /> + </BitField> + <BitField start="7" size="3" name="RESERVED" description="Reserved." /> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x010" size="4" name="PIO0_4" access="Read/Write" description="I/O configuration for pin PIO0_4/SCL" reset_value="0x0000080" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function. Values 0x2 to 0x7 are reserved."> + <Enum name="PIO0_4_OPEN_DRAIN_P" start="0x0" description="PIO0_4 (open-drain pin)." /> + <Enum name="I2C_SCL_OPEN_DRAIN_" start="0x1" description="I2C SCL (open-drain pin)." /> + </BitField> + <BitField start="3" size="5" name="RESERVED" description="Reserved." /> + <BitField start="8" size="2" name="I2CMODE" description="Selects I2C mode (see Section 6.3.8). Select Standard mode (I2CMODE = 0, default) or Standard I/O functionality (I2CMODE = 1) if the pin function is GPIO (FUNC = 0)."> + <Enum name="STANDARD_MODE_FAST" start="0x0" description="Standard mode/ Fast-mode I2C." /> + <Enum name="STANDARD_IO_FUNCTIO" start="0x1" description="Standard I/O functionality" /> + <Enum name="FAST_MODE_PLUS_I2C" start="0x2" description="Fast-mode Plus I2C" /> + <Enum name="RESERVED_" start="0x3" description="Reserved." /> + </BitField> + <BitField start="10" size="22" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x014" size="4" name="PIO0_5" access="Read/Write" description="I/O configuration for pin PIO0_5/SDA" reset_value="0x0000080" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function. Values 0x2 to 0x7 are reserved."> + <Enum name="PIO0_5_OPEN_DRAIN_P" start="0x0" description="PIO0_5 (open-drain pin)." /> + <Enum name="I2C_SDA_OPEN_DRAIN_" start="0x1" description="I2C SDA (open-drain pin)." /> + </BitField> + <BitField start="8" size="2" name="I2CMODE" description="Selects I2C mode (see Section 6.3.8). Select Standard mode (I2CMODE = 00, default) or Standard I/O functionality (I2CMODE = 01) if the pin function is GPIO (FUNC = 0)."> + <Enum name="STANDARD_MODE_FAST" start="0x0" description="Standard mode/ Fast-mode I2C." /> + <Enum name="STANDARD_IO_FUNCTIO" start="0x1" description="Standard I/O functionality" /> + <Enum name="FAST_MODE_PLUS_I2C" start="0x2" description="Fast-mode Plus I2C" /> + <Enum name="RESERVED_" start="0x3" description="Reserved." /> + </BitField> + <BitField start="10" size="22" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x018" size="4" name="PIO0_6" access="Read/Write" description="I/O configuration for pin PIO0_6/USB_CONNECT/SCK0" reset_value="0x0000090" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function. Values 0x3 to 0x7 are reserved."> + <Enum name="PIO0_6_" start="0x0" description="PIO0_6." /> + <Enum name="USB_CONNECT_" start="0x1" description="USB_CONNECT." /> + <Enum name="SCK0_" start="0x2" description="SCK0." /> + </BitField> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." /> + </BitField> + <BitField start="7" size="3" name="RESERVED" description="Reserved." /> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x01C" size="4" name="PIO0_7" access="Read/Write" description="I/O configuration for pin PIO0_7/CTS" reset_value="0x0000090" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function. Values 0x2 to 0x7 are reserved."> + <Enum name="PIO0_7_" start="0x0" description="PIO0_7." /> + <Enum name="CTS_" start="0x1" description="CTS." /> + </BitField> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." /> + </BitField> + <BitField start="7" size="3" name="RESERVED" description="Reserved." /> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x020" size="4" name="PIO0_8" access="Read/Write" description="I/O configuration for pin PIO0_8/MISO0/CT16B0_MAT0/ ARM_TRACE_CLK" reset_value="0x0000090" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function. Values 0x4 to 0x7 are reserved."> + <Enum name="PIO0_8_" start="0x0" description="PIO0_8." /> + <Enum name="MISO0_" start="0x1" description="MISO0." /> + <Enum name="CT16B0_MAT0_" start="0x2" description="CT16B0_MAT0." /> + <Enum name="ARM_TRACE_CLK" start="0x3" description="ARM_TRACE_CLK" /> + </BitField> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." /> + </BitField> + <BitField start="7" size="3" name="RESERVED" description="Reserved." /> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x024" size="4" name="PIO0_9" access="Read/Write" description="I/O configuration for pin PIO0_9/MOSI0/CT16B0_MAT1/ ARM_TRACE_SWV" reset_value="0x0000090" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function. Values 0x4 to 0x7 are reserved."> + <Enum name="PIO0_9_" start="0x0" description="PIO0_9." /> + <Enum name="MOSI0_" start="0x1" description="MOSI0." /> + <Enum name="CT16B0_MAT1_" start="0x2" description="CT16B0_MAT1." /> + <Enum name="ARM_TRACE_SWV" start="0x3" description="ARM_TRACE_SWV" /> + </BitField> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." /> + </BitField> + <BitField start="7" size="3" name="RESERVED" description="Reserved." /> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x028" size="4" name="SWCLK_PIO0_10" access="Read/Write" description="I/O configuration for pin SWCLK/PIO0_10/ SCK0/CT16B0_MAT2" reset_value="0x0000090" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function. Values 0x4 to 0x7 are reserved."> + <Enum name="SWCLK_" start="0x0" description="SWCLK." /> + <Enum name="PIO0_10_" start="0x1" description="PIO0_10." /> + <Enum name="SCK0_" start="0x2" description="SCK0." /> + <Enum name="CT16B0_MAT2_" start="0x3" description="CT16B0_MAT2." /> + </BitField> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." /> + </BitField> + <BitField start="7" size="3" name="RESERVED" description="Reserved." /> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x02C" size="4" name="TDI_PIO0_11" access="Read/Write" description="I/O configuration for pin TDI/PIO0_11/AD0/CT32B0_MAT3" reset_value="0x0000090" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function. Values 0x4 to 0x7 are reserved."> + <Enum name="TDI_" start="0x0" description="TDI." /> + <Enum name="PIO0_11_" start="0x1" description="PIO0_11." /> + <Enum name="AD0_" start="0x2" description="AD0." /> + <Enum name="CT32B0_MAT3_" start="0x3" description="CT32B0_MAT3." /> + </BitField> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." /> + </BitField> + <BitField start="7" size="1" name="ADMODE" description="Selects Analog/Digital mode."> + <Enum name="ANALOG_INPUT_MODE_" start="0" description="Analog input mode." /> + <Enum name="DIGITAL_FUNCTIONAL_M" start="1" description="Digital functional mode." /> + </BitField> + <BitField start="8" size="1" name="FILTR" description="Selects 10 ns input glitch filter."> + <Enum name="FILTER_ENABLED_" start="0" description="Filter enabled." /> + <Enum name="FILTER_DISABLED_" start="1" description="Filter disabled." /> + </BitField> + <BitField start="9" size="1" name="RESERVED" description="Reserved." /> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x030" size="4" name="TMS_PIO0_12" access="Read/Write" description="I/O configuration for pin TMS/PIO0_12/AD1/CT32B1_CAP0" reset_value="0x0000090" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function. Values 0x4 to 0x7 are reserved."> + <Enum name="TMS_" start="0x0" description="TMS." /> + <Enum name="PIO0_12_" start="0x1" description="PIO0_12." /> + <Enum name="AD1_" start="0x2" description="AD1." /> + <Enum name="CT32B1_CAP0_" start="0x3" description="CT32B1_CAP0." /> + </BitField> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." /> + </BitField> + <BitField start="7" size="1" name="ADMODE" description="Selects Analog/Digital mode."> + <Enum name="ANALOG_INPUT_MODE_" start="0" description="Analog input mode." /> + <Enum name="DIGITAL_FUNCTIONAL_M" start="1" description="Digital functional mode." /> + </BitField> + <BitField start="8" size="1" name="FILTR" description="Selects 10 ns input glitch filter."> + <Enum name="FILTER_ENABLED_" start="0" description="Filter enabled." /> + <Enum name="FILTER_DISABLED_" start="1" description="Filter disabled." /> + </BitField> + <BitField start="9" size="1" name="RESERVED" description="Reserved." /> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x034" size="4" name="TDO_PIO0_13" access="Read/Write" description="I/O configuration for pin TDO/PIO0_13/AD2/CT32B1_MAT0" reset_value="0x0000090" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function. Values 0x4 to 0x7 are reserved."> + <Enum name="TDO_" start="0x0" description="TDO." /> + <Enum name="PIO0_13_" start="0x1" description="PIO0_13." /> + <Enum name="AD2_" start="0x2" description="AD2." /> + <Enum name="CT32B1_MAT0_" start="0x3" description="CT32B1_MAT0." /> + </BitField> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." /> + </BitField> + <BitField start="7" size="1" name="ADMODE" description="Selects Analog/Digital mode."> + <Enum name="ANALOG_INPUT_MODE_" start="0" description="Analog input mode." /> + <Enum name="DIGITAL_FUNCTIONAL_M" start="1" description="Digital functional mode." /> + </BitField> + <BitField start="8" size="1" name="FILTR" description="Selects 10 ns input glitch filter."> + <Enum name="FILTER_ENABLED_" start="0" description="Filter enabled." /> + <Enum name="FILTER_DISABLED_" start="1" description="Filter disabled." /> + </BitField> + <BitField start="9" size="1" name="RESERVED" description="Reserved." /> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x038" size="4" name="TRST_PIO0_14" access="Read/Write" description="I/O configuration for pin TRST/PIO0_14/AD3/CT32B1_MAT1" reset_value="0x0000090" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function. Values 0x4 to 0x7 are reserved."> + <Enum name="TRST_" start="0x0" description="TRST." /> + <Enum name="PIO0_14_" start="0x1" description="PIO0_14." /> + <Enum name="AD3_" start="0x2" description="AD3." /> + <Enum name="CT32B1_MAT1_" start="0x3" description="CT32B1_MAT1." /> + </BitField> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." /> + </BitField> + <BitField start="7" size="1" name="ADMODE" description="Selects Analog/Digital mode."> + <Enum name="ANALOG_INPUT_MODE_" start="0" description="Analog input mode." /> + <Enum name="DIGITAL_FUNCTIONAL_M" start="1" description="Digital functional mode." /> + </BitField> + <BitField start="8" size="1" name="FILTR" description="Selects 10 ns input glitch filter."> + <Enum name="FILTER_ENABLED_" start="0" description="Filter enabled." /> + <Enum name="FILTER_DISABLED_" start="1" description="Filter disabled." /> + </BitField> + <BitField start="9" size="1" name="RESERVED" description="Reserved." /> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x03C" size="4" name="SWDIO_PIO0_15" access="Read/Write" description="I/O configuration for pin SWDIO/PIO0_15/AD4/CT32B1_MAT2" reset_value="0x0000090" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function. Values 0x4 to 0x7 are reserved."> + <Enum name="SWDIO_" start="0x0" description="SWDIO." /> + <Enum name="PIO0_15_" start="0x1" description="PIO0_15." /> + <Enum name="AD4_" start="0x2" description="AD4." /> + <Enum name="CT32B1_MAT2_" start="0x3" description="CT32B1_MAT2." /> + </BitField> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." /> + </BitField> + <BitField start="7" size="1" name="ADMODE" description="Selects Analog/Digital mode."> + <Enum name="ANALOG_INPUT_MODE_" start="0" description="Analog input mode." /> + <Enum name="DIGITAL_FUNCTIONAL_M" start="1" description="Digital functional mode." /> + </BitField> + <BitField start="8" size="1" name="FILTR" description="Selects 10 ns input glitch filter."> + <Enum name="FILTER_ENABLED_" start="0" description="Filter enabled." /> + <Enum name="FILTER_DISABLED_" start="1" description="Filter disabled." /> + </BitField> + <BitField start="9" size="1" name="RESERVED" description="Reserved." /> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x040" size="4" name="PIO0_16" access="Read/Write" description="I/O configuration for pin PIO0_16/AD5/CT32B1_MAT3/ WAKEUP" reset_value="0x0000090" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function. This pin functions as WAKEUP pin if the LPC1315/16/17/45/46/47 is in Deep power-down mode regardless of the value of FUNC. Values 0x3 to 0x7 are reserved."> + <Enum name="PIO0_16_" start="0x0" description="PIO0_16." /> + <Enum name="AD5_" start="0x1" description="AD5." /> + <Enum name="CT32B1_MAT3_" start="0x2" description="CT32B1_MAT3." /> + </BitField> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." /> + </BitField> + <BitField start="7" size="1" name="ADMODE" description="Selects Analog/Digital mode."> + <Enum name="ANALOG_INPUT_MODE_" start="0" description="Analog input mode." /> + <Enum name="DIGITAL_FUNCTIONAL_M" start="1" description="Digital functional mode." /> + </BitField> + <BitField start="8" size="1" name="FILTR" description="Selects 10 ns input glitch filter."> + <Enum name="FILTER_ENABLED_" start="0" description="Filter enabled." /> + <Enum name="FILTER_DISABLED_" start="1" description="Filter disabled." /> + </BitField> + <BitField start="9" size="1" name="RESERVED" description="Reserved." /> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x044" size="4" name="PIO0_17" access="Read/Write" description="I/O configuration for pin PIO0_17/RTS/CT32B0_CAP0/SCLK" reset_value="0x0000090" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function. Values 0x4 to 0x7 are reserved."> + <Enum name="PIO0_17_" start="0x0" description="PIO0_17." /> + <Enum name="RTS_" start="0x1" description="RTS." /> + <Enum name="CT32B0_CAP0_" start="0x2" description="CT32B0_CAP0." /> + <Enum name="SCLK_UART_SYNCHRONO" start="0x3" description="SCLK (UART synchronous clock)." /> + </BitField> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." /> + </BitField> + <BitField start="7" size="3" name="RESERVED" description="Reserved." /> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x048" size="4" name="PIO0_18" access="Read/Write" description="I/O configuration for pin PIO0_18/RXD/CT32B0_MAT0" reset_value="0x0000090" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function. Values 0x3 to 0x7 are reserved."> + <Enum name="PIO0_18_" start="0x0" description="PIO0_18." /> + <Enum name="RXD_" start="0x1" description="RXD." /> + <Enum name="CT32B0_MAT0_" start="0x2" description="CT32B0_MAT0." /> + </BitField> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." /> + </BitField> + <BitField start="7" size="3" name="RESERVED" description="Reserved." /> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x04C" size="4" name="PIO0_19" access="Read/Write" description="I/O configuration for pin PIO0_19/TXD/CT32B0_MAT1" reset_value="0x0000090" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function. Values 0x3 to 0x7 are reserved."> + <Enum name="PIO0_19_" start="0x0" description="PIO0_19." /> + <Enum name="TXD_" start="0x1" description="TXD." /> + <Enum name="CT32B0_MAT1_" start="0x2" description="CT32B0_MAT1." /> + </BitField> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." /> + </BitField> + <BitField start="7" size="3" name="RESERVED" description="Reserved." /> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x050" size="4" name="PIO0_20" access="Read/Write" description="I/O configuration for pin PIO0_20/CT16B1_CAP0" reset_value="0x0000090" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function. Values 0x2 to 0x7 are reserved."> + <Enum name="PIO0_20_" start="0x0" description="PIO0_20." /> + <Enum name="CT16B1_CAP0_" start="0x1" description="CT16B1_CAP0." /> + </BitField> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." /> + </BitField> + <BitField start="7" size="3" name="RESERVED" description="Reserved." /> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x054" size="4" name="PIO0_21" access="Read/Write" description="I/O configuration for pin PIO0_21/CT16B1_MAT0/MOSI1" reset_value="0x0000090" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function. Values 0x3 to 0x7 are reserved."> + <Enum name="PIO0_21_" start="0x0" description="PIO0_21." /> + <Enum name="CT16B1_MAT0_" start="0x1" description="CT16B1_MAT0." /> + <Enum name="MOSI1_" start="0x2" description="MOSI1." /> + </BitField> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." /> + </BitField> + <BitField start="7" size="3" name="RESERVED" description="Reserved." /> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x058" size="4" name="PIO0_22" access="Read/Write" description="I/O configuration for pin PIO0_22/AD6/CT16B1_MAT1/MISO1" reset_value="0x0000090" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function. Values 0x4 to 0x7 are reserved."> + <Enum name="PIO0_22_" start="0x0" description="PIO0_22." /> + <Enum name="AD6_" start="0x1" description="AD6." /> + <Enum name="CT16B1_MAT1_" start="0x2" description="CT16B1_MAT1." /> + <Enum name="MISO1_" start="0x3" description="MISO1." /> + </BitField> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." /> + </BitField> + <BitField start="7" size="1" name="ADMODE" description="Selects Analog/Digital mode."> + <Enum name="ANALOG_INPUT_MODE_" start="0" description="Analog input mode." /> + <Enum name="DIGITAL_FUNCTIONAL_M" start="1" description="Digital functional mode." /> + </BitField> + <BitField start="8" size="1" name="FILTR" description="Selects 10 ns input glitch filter."> + <Enum name="FILTER_ENABLED_" start="0" description="Filter enabled." /> + <Enum name="FILTER_DISABLED_" start="1" description="Filter disabled." /> + </BitField> + <BitField start="9" size="1" name="RESERVED" description="Reserved." /> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x05C" size="4" name="PIO0_23" access="Read/Write" description="I/O configuration for pin PIO0_23/AD7" reset_value="0x0000090" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function. Values 0x2 to 0x7 are reserved."> + <Enum name="PIO0_23_" start="0x0" description="PIO0_23." /> + <Enum name="AD7_" start="0x1" description="AD7." /> + </BitField> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." /> + </BitField> + <BitField start="7" size="1" name="ADMODE" description="Selects Analog/Digital mode."> + <Enum name="ANALOG_INPUT_MODE_" start="0" description="Analog input mode." /> + <Enum name="DIGITAL_FUNCTIONAL_M" start="1" description="Digital functional mode." /> + </BitField> + <BitField start="8" size="1" name="FILTR" description="Selects 10 ns input glitch filter."> + <Enum name="FILTER_ENABLED_" start="0" description="Filter enabled." /> + <Enum name="FILTER_DISABLED_" start="1" description="Filter disabled." /> + </BitField> + <BitField start="9" size="1" name="RESERVED" description="Reserved." /> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x060" size="4" name="PIO1_0" access="Read/Write" description="I/O configuration for pin PIO1_0/CT32B1_MAT0" reset_value="0x0000090" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function. Values 0x2 to 0x7 are reserved."> + <Enum name="PIO1_0_" start="0x0" description="PIO1_0." /> + <Enum name="CT32B1_MAT1_" start="0x1" description="CT32B1_MAT1." /> + </BitField> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." /> + </BitField> + <BitField start="7" size="3" name="RESERVED" description="Reserved." /> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x064" size="4" name="PIO1_1" access="Read/Write" description="I/O configuration for pin PIO1_1/CT32B1_MAT1" reset_value="0x0000090" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function. Values 0x2 to 0x7 are reserved."> + <Enum name="PIO1_1_" start="0x0" description="PIO1_1." /> + <Enum name="CT32B1_MAT1_" start="0x1" description="CT32B1_MAT1." /> + </BitField> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." /> + </BitField> + <BitField start="7" size="3" name="RESERVED" description="Reserved." /> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x068" size="4" name="PIO1_2" access="Read/Write" description="I/O configuration for pin PIO1_2/CT32B1_MAT2" reset_value="0x0000090" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function. Values 0x2 to 0x7 are reserved."> + <Enum name="PIO1_2_" start="0x0" description="PIO1_2." /> + <Enum name="CT32B1_MAT2_" start="0x1" description="CT32B1_MAT2." /> + </BitField> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." /> + </BitField> + <BitField start="7" size="3" name="RESERVED" description="Reserved." /> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x06C" size="4" name="PIO1_3" access="Read/Write" description="I/O configuration for pin PIO1_3/CT32B1_MAT3" reset_value="0x0000090" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function. Values 0x2 to 0x7 are reserved."> + <Enum name="PIO1_3_" start="0x0" description="PIO1_3." /> + <Enum name="CT32B1_MAT3_" start="0x1" description="CT32B1_MAT3." /> + </BitField> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." /> + </BitField> + <BitField start="7" size="3" name="RESERVED" description="Reserved." /> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x070" size="4" name="PIO1_4" access="Read/Write" description="I/O configuration for pin PIO1_4/CT32B1_CAP0" reset_value="0x0000090" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function. Values 0x2 to 0x7 are reserved."> + <Enum name="PIO1_4_" start="0x0" description="PIO1_4." /> + <Enum name="CT32B1_CAP0_" start="0x1" description="CT32B1_CAP0." /> + </BitField> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." /> + </BitField> + <BitField start="7" size="3" name="RESERVED" description="Reserved." /> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x074" size="4" name="PIO1_5" access="Read/Write" description="I/O configuration for pin PIO1_5/CT32B1_CAP1" reset_value="0x0000090" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function. Values 0x2 to 0x7 are reserved."> + <Enum name="PIO1_5_" start="0x0" description="PIO1_5." /> + <Enum name="CT32B1_CAP1_" start="0x1" description="CT32B1_CAP1." /> + </BitField> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." /> + </BitField> + <BitField start="7" size="3" name="RESERVED" description="Reserved." /> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x07C" size="4" name="PIO1_7" access="Read/Write" description="I/O configuration for pin PIO1_7" reset_value="0x0000090" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function. Values 0x2 to 0x7 are reserved."> + <Enum name="PIO1_7_" start="0x0" description="PIO1_7." /> + </BitField> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." /> + </BitField> + <BitField start="7" size="3" name="RESERVED" description="Reserved." /> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x080" size="4" name="PIO1_8" access="Read/Write" description="I/O configuration for pin PIO1_8" reset_value="0x0000090" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function. Values 0x1 to 0x7 are reserved."> + <Enum name="PIO1_8_" start="0x0" description="PIO1_8." /> + </BitField> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." /> + </BitField> + <BitField start="7" size="3" name="RESERVED" description="Reserved." /> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x088" size="4" name="PIO1_10" access="Read/Write" description="I/O configuration for pin PIO1_10" reset_value="0x0000090" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function. Values 0x1 to 0x7 are reserved."> + <Enum name="PIO1_10_" start="0x0" description="PIO1_10." /> + </BitField> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." /> + </BitField> + <BitField start="7" size="3" name="RESERVED" description="Reserved." /> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x08C" size="4" name="PIO1_11" access="Read/Write" description="I/O configuration for pin PIO1_11" reset_value="0x0000090" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function. Values 0x1 to 0x7 are reserved."> + <Enum name="PIO1_11_" start="0x0" description="PIO1_11." /> + </BitField> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." /> + </BitField> + <BitField start="7" size="3" name="RESERVED" description="Reserved." /> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x094" size="4" name="PIO1_13" access="Read/Write" description="I/O configuration for PIO1_13/DTR/CT16B0_MAT0/TXD" reset_value="0x0000090" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function. Values 0x4 to 0x7 are reserved."> + <Enum name="PIO1_13" start="0x0" description="PIO1_13" /> + <Enum name="DTR" start="0x1" description="DTR" /> + <Enum name="CT16B0_MAT0" start="0x2" description="CT16B0_MAT0" /> + <Enum name="TXD" start="0x3" description="TXD" /> + </BitField> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." /> + </BitField> + <BitField start="7" size="3" name="RESERVED" description="Reserved." /> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x098" size="4" name="PIO1_14" access="Read/Write" description="I/O configuration for PIO1_14/DSR/CT16B0_MAT1/RXD" reset_value="0x0000090" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function. Values 0x4 to 0x7 are reserved."> + <Enum name="PIO1_14_" start="0x0" description="PIO1_14." /> + <Enum name="DSR" start="0x1" description="DSR" /> + <Enum name="CT16B0_MAT1" start="0x2" description="CT16B0_MAT1" /> + <Enum name="RXD" start="0x3" description="RXD" /> + </BitField> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." /> + </BitField> + <BitField start="7" size="3" name="RESERVED" description="Reserved." /> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x09C" size="4" name="PIO1_15" access="Read/Write" description="I/O configuration for pin PIO1_15/DCD/ CT16B0_MAT2/SCK1" reset_value="0x0000090" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function. Values 0x4 to 0x7 are reserved."> + <Enum name="PIO1_15_" start="0x0" description="PIO1_15." /> + <Enum name="DCD_" start="0x1" description="DCD." /> + <Enum name="CT16B0_MAT2_" start="0x2" description="CT16B0_MAT2." /> + <Enum name="SCK1_" start="0x3" description="SCK1." /> + </BitField> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." /> + </BitField> + <BitField start="7" size="3" name="RESERVED" description="Reserved." /> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x0A0" size="4" name="PIO1_16" access="Read/Write" description="I/O configuration for pin PIO1_16/RI/CT16B0_CAP0" reset_value="0x0000090" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function. Values 0x3 to 0x7 are reserved."> + <Enum name="PIO1_16_" start="0x0" description="PIO1_16." /> + <Enum name="RI_" start="0x1" description="RI." /> + <Enum name="CT16B0_CAP0_" start="0x2" description="CT16B0_CAP0." /> + </BitField> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." /> + </BitField> + <BitField start="7" size="3" name="RESERVED" description="Reserved." /> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x0A4" size="4" name="PIO1_17" access="Read/Write" description="I/O configuration for PIO1_17/CT16B0_CAP1/RXD" reset_value="0x0000090" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function. Values 0x3 to 0x7 are reserved."> + <Enum name="PIO1_17_" start="0x0" description="PIO1_17." /> + <Enum name="CT16B0_CAP1" start="0x1" description="CT16B0_CAP1" /> + <Enum name="RXD" start="0x2" description="RXD" /> + </BitField> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." /> + </BitField> + <BitField start="7" size="3" name="RESERVED" description="Reserved." /> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x0A8" size="4" name="PIO1_18" access="Read/Write" description="I/O configuration for PIO1_18/CT16B1_CAP1/TXD" reset_value="0x0000090" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function. Values 0x3 to 0x7 are reserved."> + <Enum name="PIO1_18" start="0x0" description="PIO1_18" /> + <Enum name="CT16B1_CAP1" start="0x1" description="CT16B1_CAP1" /> + <Enum name="TXD" start="0x2" description="TXD" /> + </BitField> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." /> + </BitField> + <BitField start="7" size="3" name="RESERVED" description="Reserved." /> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x0AC" size="4" name="PIO1_19" access="Read/Write" description="I/O configuration for pin PIO1_19/DTR/SSEL1" reset_value="0x0000090" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function. Values 0x3 to 0x7 are reserved."> + <Enum name="PIO1_19_" start="0x0" description="PIO1_19." /> + <Enum name="DTR_" start="0x1" description="DTR." /> + <Enum name="SSEL1_" start="0x2" description="SSEL1." /> + </BitField> + <BitField start="3" size="2" name="MODE" description="mode (on-chip pull-up/pull-down resistor control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." /> + </BitField> + <BitField start="7" size="3" name="RESERVED" description="Reserved." /> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x0B0" size="4" name="PIO1_20" access="Read/Write" description="I/O configuration for pin PIO1_20/DSR/SCK1" reset_value="0x0000090" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function. Values 0x3 to 0x7 are reserved."> + <Enum name="PIO1_20_" start="0x0" description="PIO1_20." /> + <Enum name="DSR_" start="0x1" description="DSR." /> + <Enum name="SCK1_" start="0x2" description="SCK1." /> + </BitField> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." /> + </BitField> + <BitField start="7" size="3" name="RESERVED" description="Reserved." /> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x0B4" size="4" name="PIO1_21" access="Read/Write" description="I/O configuration for pin PIO1_21/DCD/MISO1" reset_value="0x0000090" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function. Values 0x3 to 0x7 are reserved."> + <Enum name="PIO1_21_" start="0x0" description="PIO1_21." /> + <Enum name="DCD_" start="0x1" description="DCD." /> + <Enum name="MISO1_" start="0x2" description="MISO1." /> + </BitField> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." /> + </BitField> + <BitField start="7" size="3" name="RESERVED" description="Reserved." /> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x0B8" size="4" name="PIO1_22" access="Read/Write" description="I/O configuration for pin PIO1_22/RI/MOSI1" reset_value="0x0000090" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function. Values 0x3 to 0x7 are reserved."> + <Enum name="PIO1_22_" start="0x0" description="PIO1_22." /> + <Enum name="RI_" start="0x1" description="RI." /> + <Enum name="MOSI1_" start="0x2" description="MOSI1." /> + </BitField> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." /> + </BitField> + <BitField start="7" size="3" name="RESERVED" description="Reserved." /> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x0BC" size="4" name="PIO1_23" access="Read/Write" description="I/O configuration for pin PIO1_23/CT16B1_MAT1/SSEL1" reset_value="0x0000090" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function. Values 0x3 to 0x7 are reserved."> + <Enum name="PIO1_23_" start="0x0" description="PIO1_23." /> + <Enum name="CT16B1_MAT1_" start="0x1" description="CT16B1_MAT1." /> + <Enum name="SSEL1_" start="0x2" description="SSEL1." /> + </BitField> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." /> + </BitField> + <BitField start="7" size="3" name="RESERVED" description="Reserved." /> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x0C0" size="4" name="PIO1_24" access="Read/Write" description="I/O configuration for pin PIO1_24/ CT32B0_MAT0" reset_value="0x0000090" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function. Values 0x2 to 0x7 are reserved."> + <Enum name="PIO1_24_" start="0x0" description="PIO1_24." /> + <Enum name="CT32B0_MAT0_" start="0x1" description="CT32B0_MAT0." /> + </BitField> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." /> + </BitField> + <BitField start="7" size="3" name="RESERVED" description="Reserved." /> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x0C4" size="4" name="PIO1_25" access="Read/Write" description="I/O configuration for pin PIO1_25/CT32B0_MAT1" reset_value="0x0000090" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function. Values 0x2 to 0x7 are reserved."> + <Enum name="PIO1_25_" start="0x0" description="PIO1_25." /> + <Enum name="CT32B0_MAT1_" start="0x1" description="CT32B0_MAT1." /> + </BitField> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." /> + </BitField> + <BitField start="7" size="3" name="RESERVED" description="Reserved." /> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x0C8" size="4" name="PIO1_26" access="Read/Write" description="I/O configuration for pin PIO1_26/CT32B0_MAT2/ RXD" reset_value="0x0000090" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function. Values 0x3 to 0x7 are reserved."> + <Enum name="PIO1_26_" start="0x0" description="PIO1_26." /> + <Enum name="CT32B0_MAT2" start="0x1" description="CT32B0_MAT2" /> + <Enum name="RXD_" start="0x2" description="RXD." /> + </BitField> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." /> + </BitField> + <BitField start="7" size="3" name="RESERVED" description="Reserved." /> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x0CC" size="4" name="PIO1_27" access="Read/Write" description="I/O configuration for pin PIO1_27/CT32B0_MAT3/ TXD" reset_value="0x0000090" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function. Values 0x3 to 0x7 are reserved."> + <Enum name="PIO1_27_" start="0x0" description="PIO1_27." /> + <Enum name="CT32B0_MAT3_" start="0x1" description="CT32B0_MAT3." /> + <Enum name="TXD_" start="0x2" description="TXD." /> + </BitField> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." /> + </BitField> + <BitField start="7" size="3" name="RESERVED" description="Reserved." /> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x0D0" size="4" name="PIO1_28" access="Read/Write" description="I/O configuration for pin PIO1_28/CT32B0_CAP0/ SCLK" reset_value="0x0000090" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function. Values 0x3 to 0x7 are reserved."> + <Enum name="PIO1_28_" start="0x0" description="PIO1_28." /> + <Enum name="CT32B0_CAP0_" start="0x1" description="CT32B0_CAP0." /> + <Enum name="SCLK_" start="0x2" description="SCLK." /> + </BitField> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." /> + </BitField> + <BitField start="7" size="3" name="RESERVED" description="Reserved." /> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x0D4" size="4" name="PIO1_29" access="Read/Write" description="I/O configuration for pin PIO1_29/SCK0/ CT32B0_CAP1" reset_value="0x0000090" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function. Values 0x3 to 0x7 are reserved."> + <Enum name="PIO1_29_" start="0x0" description="PIO1_29." /> + <Enum name="SCK0_" start="0x1" description="SCK0." /> + <Enum name="CT32B0_CAP1_" start="0x2" description="CT32B0_CAP1." /> + </BitField> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." /> + </BitField> + <BitField start="7" size="3" name="RESERVED" description="Reserved." /> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x0DC" size="4" name="PIO1_31" access="Read/Write" description="I/O configuration for pin PIO1_31" reset_value="0x0000090" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function. Values 0x1 to 0x7 are reserved."> + <Enum name="PIO1_31_" start="0x0" description="PIO1_31." /> + </BitField> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." /> + </BitField> + <BitField start="7" size="3" name="RESERVED" description="Reserved." /> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved." /> + </Register> + </RegisterGroup> + <RegisterGroup name="SYSCON" start="0x40048000" description="System control block "> + <Register start="+0x000" size="4" name="SYSMEMREMAP" access="Read/Write" description="System memory remap" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="MAP" description="System memory remap. Value 0x3 is reserved."> + <Enum name="BOOT_LOADER_MODE_IN" start="0x0" description="Boot Loader Mode. Interrupt vectors are re-mapped to Boot ROM." /> + <Enum name="USER_RAM_MODE_INTER" start="0x1" description="User RAM Mode. Interrupt vectors are re-mapped to Static RAM." /> + <Enum name="USER_FLASH_MODE_INT" start="0x2" description="User Flash Mode. Interrupt vectors are not re-mapped and reside in Flash." /> + </BitField> + <BitField start="2" size="30" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x004" size="4" name="PRESETCTRL" access="Read/Write" description="Peripheral reset control" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="SSP0_RST_N" description="SSP0 reset control"> + <Enum name="RESETS_THE_SSP0_PERI" start="0" description="Resets the SSP0 peripheral." /> + <Enum name="SSP0_RESET_DE_ASSERT" start="1" description="SSP0 reset de-asserted." /> + </BitField> + <BitField start="1" size="1" name="I2C_RST_N" description="I2C reset control"> + <Enum name="RESETS_THE_I2C_PERIP" start="0" description="Resets the I2C peripheral." /> + <Enum name="I2C_RESET_DE_ASSERTE" start="1" description="I2C reset de-asserted." /> + </BitField> + <BitField start="2" size="1" name="SSP1_RST_N" description="SSP1 reset control"> + <Enum name="RESETS_THE_SSP0_PERI" start="0" description="Resets the SSP0 peripheral." /> + <Enum name="SSP1_RESET_DE_ASSERT" start="1" description="SSP1 reset de-asserted." /> + </BitField> + <BitField start="3" size="1" name="RESERVED" description="Reserved" /> + <BitField start="4" size="28" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x008" size="4" name="SYSPLLCTRL" access="Read/Write" description="System PLL control" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="MSEL" description="Feedback divider value. The division value M is the programmed MSEL value + 1. 00000: Division ratio M = 1 to 11111: Division ratio M = 32" /> + <BitField start="5" size="2" name="PSEL" description="Post divider ratio P. The division ratio is 2 x P."> + <Enum name="P_EQ_1" start="0x0" description="P = 1" /> + <Enum name="P_EQ_2" start="0x1" description="P = 2" /> + <Enum name="P_EQ_4" start="0x2" description="P = 4" /> + <Enum name="P_EQ_8" start="0x3" description="P = 8" /> + </BitField> + <BitField start="7" size="25" name="RESERVED" description="Reserved. Do not write ones to reserved bits." /> + </Register> + <Register start="+0x00C" size="4" name="SYSPLLSTAT" access="ReadOnly" description="System PLL status" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="LOCK" description="PLL lock status"> + <Enum name="PLL_NOT_LOCKED" start="0" description="PLL not locked" /> + <Enum name="PLL_LOCKED" start="1" description="PLL locked" /> + </BitField> + <BitField start="1" size="31" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x010" size="4" name="USBPLLCTRL" access="Read/Write" description="USB PLL control" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="MSEL" description="Feedback divider value. The division value M is the programmed MSEL value + 1. 00000: Division ratio M = 1 to 11111: Division ratio M = 32" /> + <BitField start="5" size="2" name="PSEL" description="Post divider ratio P. The division ratio is 2 x P."> + <Enum name="P_EQ_1" start="0x0" description="P = 1" /> + <Enum name="P_EQ_2" start="0x1" description="P = 2" /> + <Enum name="P_EQ_4" start="0x2" description="P = 4" /> + <Enum name="P_EQ_8" start="0x3" description="P = 8" /> + </BitField> + <BitField start="7" size="25" name="RESERVED" description="Reserved. Do not write ones to reserved bits." /> + </Register> + <Register start="+0x014" size="4" name="USBPLLSTAT" access="ReadOnly" description="USB PLL status" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="LOCK" description="PLL lock status"> + <Enum name="PLL_NOT_LOCKED" start="0" description="PLL not locked" /> + <Enum name="PLL_LOCKED" start="1" description="PLL locked" /> + </BitField> + <BitField start="1" size="31" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x020" size="4" name="SYSOSCCTRL" access="Read/Write" description="System oscillator control" reset_value="0x000" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="BYPASS" description="Bypass system oscillator"> + <Enum name="OSCILLATOR_IS_NOT_BY" start="0" description="Oscillator is not bypassed." /> + <Enum name="BYPASS_ENABLED_PLL_" start="1" description="Bypass enabled. PLL input (sys_osc_clk) is fed directly from the XTALIN pin bypassing the oscillator. Use this mode when using an external clock source instead of the crystal oscillator." /> + </BitField> + <BitField start="1" size="1" name="FREQRANGE" description="Determines frequency range for Low-power oscillator."> + <Enum name="1__20_MHZ_FREQUENCY" start="0" description="1 - 20 MHz frequency range." /> + <Enum name="15__25_MHZ_FREQUENC" start="1" description="15 - 25 MHz frequency range" /> + </BitField> + <BitField start="2" size="30" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x024" size="4" name="WDTOSCCTRL" access="Read/Write" description="Watchdog oscillator control" reset_value="0x0A0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="DIVSEL" description="Select divider for Fclkana. wdt_osc_clk = Fclkana/ (2 x (1 + DIVSEL)) 00000: 2 x (1 + DIVSEL) = 2 00001: 2 x (1 + DIVSEL) = 4 to 11111: 2 x (1 + DIVSEL) = 64" /> + <BitField start="5" size="4" name="FREQSEL" description="Select watchdog oscillator analog output frequency (Fclkana)."> + <Enum name="0_6_MHZ" start="0x1" description="0.6 MHz" /> + <Enum name="1_05_MHZ" start="0x2" description="1.05 MHz" /> + <Enum name="1_4_MHZ" start="0x3" description="1.4 MHz" /> + <Enum name="1_75_MHZ" start="0x4" description="1.75 MHz" /> + <Enum name="2_1_MHZ" start="0x5" description="2.1 MHz" /> + <Enum name="2_4_MHZ" start="0x6" description="2.4 MHz" /> + <Enum name="2_7_MHZ" start="0x7" description="2.7 MHz" /> + <Enum name="3_0_MHZ" start="0x8" description="3.0 MHz" /> + <Enum name="3_25_MHZ" start="0x9" description="3.25 MHz" /> + <Enum name="3_5_MHZ" start="0xA" description="3.5 MHz" /> + <Enum name="3_75_MHZ" start="0xB" description="3.75 MHz" /> + <Enum name="4_0_MHZ" start="0xC" description="4.0 MHz" /> + <Enum name="4_2_MHZ" start="0xD" description="4.2 MHz" /> + <Enum name="4_4_MHZ" start="0xE" description="4.4 MHz" /> + <Enum name="4_6_MHZ" start="0xF" description="4.6 MHz" /> + </BitField> + <BitField start="9" size="23" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x030" size="4" name="SYSRSTSTAT" access="Read/Write" description="System reset status register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="POR" description="POR reset status"> + <Enum name="NO_POR_DETECTED" start="0" description="No POR detected" /> + <Enum name="POR_DETECTED" start="1" description="POR detected" /> + </BitField> + <BitField start="1" size="1" name="EXTRST" description="Status of the external RESET pin"> + <Enum name="NO_RESET_EVENT_DETEC" start="0" description="No reset event detected" /> + <Enum name="RESET_DETECTED" start="1" description="Reset detected" /> + </BitField> + <BitField start="2" size="1" name="WDT" description="Status of the Watchdog reset"> + <Enum name="NO_WDT_RESET_DETECTE" start="0" description="No WDT reset detected" /> + <Enum name="WDT_RESET_DETECTED" start="1" description="WDT reset detected" /> + </BitField> + <BitField start="3" size="1" name="BOD" description="Status of the Brown-out detect reset"> + <Enum name="NO_BOD_RESET_DETECTE" start="0" description="No BOD reset detected" /> + <Enum name="BOD_RESET_DETECTED" start="1" description="BOD reset detected" /> + </BitField> + <BitField start="4" size="1" name="SYSRST" description="Status of the software system reset"> + <Enum name="NO_SYSTEM_RESET_DETE" start="0" description="No System reset detected" /> + <Enum name="SYSTEM_RESET_DETECTE" start="1" description="System reset detected" /> + </BitField> + <BitField start="5" size="27" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x040" size="4" name="SYSPLLCLKSEL" access="Read/Write" description="System PLL clock source select" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="SEL" description="System PLL clock source"> + <Enum name="IRC" start="0x0" description="IRC" /> + <Enum name="CRYSTAL_OSCILLATOR_" start="0x1" description="Crystal Oscillator (SYSOSC)" /> + <Enum name="RESERVED" start="0x2" description="Reserved" /> + <Enum name="RESERVED" start="0x3" description="Reserved" /> + </BitField> + <BitField start="2" size="30" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x048" size="4" name="USBPLLCLKSEL" access="Read/Write" description="USB PLL clock source select" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="SEL" description="USB PLL clock source"> + <Enum name="IRC_THE_USB_PLL_CLO" start="0x0" description="IRC. The USB PLL clock source must be switched to system oscillator for correct USB operation." /> + <Enum name="SYSTEM_OSCILLATOR" start="0x1" description="System oscillator" /> + <Enum name="RESERVED" start="0x2" description="Reserved" /> + <Enum name="RESERVED" start="0x3" description="Reserved" /> + </BitField> + <BitField start="2" size="30" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x070" size="4" name="MAINCLKSEL" access="Read/Write" description="Main clock source select" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="SEL" description="Clock source for main clock"> + <Enum name="IRC_OSCILLATOR" start="0x0" description="IRC Oscillator" /> + <Enum name="PLL_INPUT" start="0x1" description="PLL input" /> + <Enum name="WATCHDOG_OSCILLATOR" start="0x2" description="Watchdog oscillator" /> + <Enum name="PLL_OUTPUT" start="0x3" description="PLL output" /> + </BitField> + <BitField start="2" size="30" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x078" size="4" name="SYSAHBCLKDIV" access="Read/Write" description="System clock divider" reset_value="0x001" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="DIV" description="System AHB clock divider values 0: System clock disabled. 1: Divide by 1. to 255: Divide by 255." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x080" size="4" name="SYSAHBCLKCTRL" access="Read/Write" description="System clock control" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="SYS" description="Enables the clock for the AHB, the APB bridge, the Cortex-M3 FCLK and HCLK, SysCon, and the PMU. This bit is read only and always reads as 1."> + <Enum name="RESERVED" start="0" description="Reserved" /> + <Enum name="ENABLE" start="1" description="Enable" /> + </BitField> + <BitField start="1" size="1" name="ROM" description="Enables clock for ROM."> + <Enum name="DISABLE" start="0" description="Disable" /> + <Enum name="ENABLE" start="1" description="Enable" /> + </BitField> + <BitField start="2" size="1" name="RAM0" description="Enables clock for SRAM0."> + <Enum name="DISABLE" start="0" description="Disable" /> + <Enum name="ENABLE" start="1" description="Enable" /> + </BitField> + <BitField start="3" size="1" name="FLASHREG" description="Enables clock for flash register interface."> + <Enum name="DISABLED" start="0" description="Disabled" /> + <Enum name="ENABLED" start="1" description="Enabled" /> + </BitField> + <BitField start="4" size="1" name="FLASHARRAY" description="Enables clock for flash array access."> + <Enum name="DISABLED" start="0" description="Disabled" /> + <Enum name="ENABLED" start="1" description="Enabled" /> + </BitField> + <BitField start="5" size="1" name="I2C" description="Enables clock for I2C."> + <Enum name="DISABLE" start="0" description="Disable" /> + <Enum name="ENABLE" start="1" description="Enable" /> + </BitField> + <BitField start="6" size="1" name="GPIO" description="Enables clock for GPIO port registers."> + <Enum name="DISABLE" start="0" description="Disable" /> + <Enum name="ENABLE" start="1" description="Enable" /> + </BitField> + <BitField start="7" size="1" name="CT16B0" description="Enables clock for 16-bit counter/timer 0."> + <Enum name="DISABLE" start="0" description="Disable" /> + <Enum name="ENABLE" start="1" description="Enable" /> + </BitField> + <BitField start="8" size="1" name="CT16B1" description="Enables clock for 16-bit counter/timer 1."> + <Enum name="DISABLE" start="0" description="Disable" /> + <Enum name="ENABLE" start="1" description="Enable" /> + </BitField> + <BitField start="9" size="1" name="CT32B0" description="Enables clock for 32-bit counter/timer 0."> + <Enum name="DISABLE" start="0" description="Disable" /> + <Enum name="ENABLE" start="1" description="Enable" /> + </BitField> + <BitField start="10" size="1" name="CT32B1" description="Enables clock for 32-bit counter/timer 1."> + <Enum name="DISABLE" start="0" description="Disable" /> + <Enum name="ENABLE" start="1" description="Enable" /> + </BitField> + <BitField start="11" size="1" name="SSP0" description="Enables clock for SSP0."> + <Enum name="DISABLE" start="0" description="Disable" /> + <Enum name="ENABLE" start="1" description="Enable" /> + </BitField> + <BitField start="12" size="1" name="USART" description="Enables clock for UART."> + <Enum name="DISABLE" start="0" description="Disable" /> + <Enum name="ENABLE" start="1" description="Enable" /> + </BitField> + <BitField start="13" size="1" name="ADC" description="Enables clock for ADC."> + <Enum name="DISABLE" start="0" description="Disable" /> + <Enum name="ENABLE" start="1" description="Enable" /> + </BitField> + <BitField start="14" size="1" name="USB" description="Enables clock to the USB register interface."> + <Enum name="DISABLE" start="0" description="Disable" /> + <Enum name="ENABLE" start="1" description="Enable" /> + </BitField> + <BitField start="15" size="1" name="WWDT" description="Enables clock for WWDT."> + <Enum name="DISABLE" start="0" description="Disable" /> + <Enum name="ENABLE" start="1" description="Enable" /> + </BitField> + <BitField start="16" size="1" name="IOCON" description="Enables clock for I/O configuration block."> + <Enum name="DISABLE" start="0" description="Disable" /> + <Enum name="ENABLE" start="1" description="Enable" /> + </BitField> + <BitField start="17" size="1" name="RESERVED" description="Reserved" /> + <BitField start="18" size="1" name="SSP1" description="Enables clock for SSP1."> + <Enum name="DISABLE" start="0" description="Disable" /> + <Enum name="ENABLE" start="1" description="Enable" /> + </BitField> + <BitField start="19" size="1" name="PINT" description="Enables clock to GPIO Pin interrupts register interface."> + <Enum name="DISABLE" start="0" description="Disable" /> + <Enum name="ENABLE" start="1" description="Enable" /> + </BitField> + <BitField start="20" size="3" name="RESERVED" description="Reserved" /> + <BitField start="23" size="1" name="GROUP0INT" description="Enables clock to GPIO GROUP0 interrupt register interface."> + <Enum name="DISABLE" start="0" description="Disable" /> + <Enum name="ENABLE" start="1" description="Enable" /> + </BitField> + <BitField start="24" size="1" name="GROUP1INT" description="Enables clock to GPIO GROUP1 interrupt register interface."> + <Enum name="DISABLE" start="0" description="Disable" /> + <Enum name="ENABLE" start="1" description="Enable" /> + </BitField> + <BitField start="25" size="1" name="RESERVED" description="Reserved" /> + <BitField start="26" size="1" name="RAM1" description="Enables clock for SRAM1 located at 0x2000 0000 to 0x2000 0800."> + <Enum name="DISABLE" start="0" description="Disable" /> + <Enum name="ENABLE" start="1" description="Enable" /> + </BitField> + <BitField start="27" size="1" name="USBSRAM" description="Enables USB SRAM block located at 0x2000 4000 to 0x2000 4800."> + <Enum name="DISABLE" start="0" description="Disable" /> + <Enum name="ENABLE" start="1" description="Enable" /> + </BitField> + <BitField start="28" size="4" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x094" size="4" name="SSP0CLKDIV" access="Read/Write" description="SSP0 clock divider" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="DIV" description="SPI0_PCLK clock divider values. 0: System clock disabled. 1: Divide by 1. to 255: Divide by 255." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x098" size="4" name="UARTCLKDIV" access="Read/Write" description="UART clock divider" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="DIV" description="UART_PCLK clock divider values 0: Disable UART_PCLK. 1: Divide by 1. to 255: Divide by 255." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x09C" size="4" name="SSP1CLKDIV" access="Read/Write" description="SSP1 clock divider" reset_value="0x0000" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="DIV" description="SSP1_PCLK clock divider values 0: Disable SSP1_PCLK. 1: Divide by 1. to 255: Divide by 255." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x0AC" size="4" name="TRACECLKDIV" access="Read/Write" description="ARM trace clock divider" reset_value="0x00000000" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="DIV" description="ARM trace clock divider values. 0: Disable TRACE_CLK. 1: Divide by 1. to 255: Divide by 255." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x0B0" size="4" name="SYSTICKCLKDIV" access="Read/Write" description="SYSTICK clock divider" reset_value="0x00000000" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="DIV" description="SYSTICK clock divider values. 0: Disable SYSTICK timer clock. 1: Divide by 1. to 255: Divide by 255." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x0C0" size="4" name="USBCLKSEL" access="Read/Write" description="USB clock source select" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="SEL" description="USB clock source. Values 0x2 and 0x3 are reserved."> + <Enum name="USB_PLL_OUT" start="0x0" description="USB PLL out" /> + <Enum name="MAIN_CLOCK" start="0x1" description="Main clock" /> + </BitField> + <BitField start="2" size="30" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x0C8" size="4" name="USBCLKDIV" access="Read/Write" description="USB clock source divider" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="DIV" description="USB clock divider values 0: Disable USB clock. 1: Divide by 1. to 255: Divide by 255." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x0E0" size="4" name="CLKOUTSEL" access="Read/Write" description="CLKOUT clock source select" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="SEL" description="CLKOUT clock source"> + <Enum name="IRC_OSCILLATOR" start="0x0" description="IRC oscillator" /> + <Enum name="CRYSTAL_OSCILLATOR_" start="0x1" description="Crystal oscillator (SYSOSC)" /> + <Enum name="WATCHDOG_OSCILLATOR" start="0x2" description="Watchdog oscillator" /> + <Enum name="MAIN_CLOCK" start="0x3" description="Main clock" /> + </BitField> + <BitField start="2" size="30" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x0E8" size="4" name="CLKOUTDIV" access="Read/Write" description="CLKOUT clock divider" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="DIV" description="CLKOUT clock divider values 0: Disable CLKOUT clock divider. 1: Divide by 1. to 255: Divide by 255." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x100" size="4" name="PIOPORCAP0" access="ReadOnly" description="POR captured PIO status 0" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="24" name="PIOSTAT" description="State of P0_23 through P0_0 at power-on reset" /> + <BitField start="24" size="8" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x104" size="4" name="PIOPORCAP1" access="ReadOnly" description="POR captured PIO status 1" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="PIOSTAT" description="State of P1_31 through P1_0 at power-on reset" /> + </Register> + <Register start="+0x150" size="4" name="BODCTRL" access="Read/Write" description="Brown-Out Detect" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="BODRSTLEV" description="BOD reset level"> + <Enum name="LEVEL_0_THE_RESET_A" start="0x0" description="Level 0: The reset assertion threshold voltage is 1.46 V; the reset de-assertion threshold voltage is 1.63 V." /> + <Enum name="LEVEL_1_THE_RESET_A" start="0x1" description="Level 1: The reset assertion threshold voltage is 2.06 V; the reset de-assertion threshold voltage is 2.15 V." /> + <Enum name="LEVEL_2_THE_RESET_A" start="0x2" description="Level 2: The reset assertion threshold voltage is 2.35 V; the reset de-assertion threshold voltage is 2.43 V." /> + <Enum name="LEVEL_3_THE_RESET_A" start="0x3" description="Level 3: The reset assertion threshold voltage is 2.63 V; the reset de-assertion threshold voltage is 2.71 V." /> + </BitField> + <BitField start="2" size="2" name="BODINTVAL" description="BOD interrupt level"> + <Enum name="RESERVED_" start="0x0" description="Reserved." /> + <Enum name="LEVEL_1THE_INTERRUP" start="0x1" description="Level 1:The interrupt assertion threshold voltage is 2.22 V; the interrupt de-assertion threshold voltage is 2.35 V." /> + <Enum name="LEVEL_2_THE_INTERRU" start="0x2" description="Level 2: The interrupt assertion threshold voltage is 2.52 V; the interrupt de-assertion threshold voltage is 2.66 V." /> + <Enum name="LEVEL_3_THE_INTERRU" start="0x3" description="Level 3: The interrupt assertion threshold voltage is 2.80 V; the interrupt de-assertion threshold voltage is 2.90 V." /> + </BitField> + <BitField start="4" size="1" name="BODRSTENA" description="BOD reset enable"> + <Enum name="DISABLE_RESET_FUNCTI" start="0" description="Disable reset function." /> + <Enum name="ENABLE_RESET_FUNCTIO" start="1" description="Enable reset function." /> + </BitField> + <BitField start="5" size="27" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x154" size="4" name="SYSTCKCAL" access="Read/Write" description="System tick counter calibration" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="26" name="CAL" description="System tick timer calibration value" /> + <BitField start="26" size="6" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x170" size="4" name="IRQLATENCY" access="Read/Write" description="IQR delay. Allows trade-off between interrupt latency and determinism." reset_value="0x00000010" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="LATENCY" description="8-bit latency value" /> + <BitField start="8" size="24" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x174" size="4" name="NMISRC" access="Read/Write" description="NMI Source Control" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="IRQNO" description="The IRQ number of the interrupt that acts as the Non-Maskable Interrupt (NMI) if bit 31 is 1. See Table 53 for the list of interrupt sources and their IRQ numbers." /> + <BitField start="5" size="26" name="RESERVED" description="Reserved" /> + <BitField start="31" size="1" name="NMIEN" description="Write a 1 to this bit to enable the Non-Maskable Interrupt (NMI) source selected by bits 4:0." /> + </Register> + <Register start="+0x178+0" size="4" name="PINTSEL0" access="Read/Write" description="GPIO Pin Interrupt Select register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="INTPIN" description="Pin number within the port selected by the PORTSEL bit in this register." /> + <BitField start="5" size="1" name="PORTSEL" description="Select the port for the pin number to be selected in the INTPIN bits of this register."> + <Enum name="PORT_0" start="0" description="Port 0" /> + <Enum name="PORT_1" start="1" description="Port 1" /> + </BitField> + <BitField start="6" size="26" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x178+4" size="4" name="PINTSEL1" access="Read/Write" description="GPIO Pin Interrupt Select register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="INTPIN" description="Pin number within the port selected by the PORTSEL bit in this register." /> + <BitField start="5" size="1" name="PORTSEL" description="Select the port for the pin number to be selected in the INTPIN bits of this register."> + <Enum name="PORT_0" start="0" description="Port 0" /> + <Enum name="PORT_1" start="1" description="Port 1" /> + </BitField> + <BitField start="6" size="26" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x178+8" size="4" name="PINTSEL2" access="Read/Write" description="GPIO Pin Interrupt Select register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="INTPIN" description="Pin number within the port selected by the PORTSEL bit in this register." /> + <BitField start="5" size="1" name="PORTSEL" description="Select the port for the pin number to be selected in the INTPIN bits of this register."> + <Enum name="PORT_0" start="0" description="Port 0" /> + <Enum name="PORT_1" start="1" description="Port 1" /> + </BitField> + <BitField start="6" size="26" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x178+12" size="4" name="PINTSEL3" access="Read/Write" description="GPIO Pin Interrupt Select register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="INTPIN" description="Pin number within the port selected by the PORTSEL bit in this register." /> + <BitField start="5" size="1" name="PORTSEL" description="Select the port for the pin number to be selected in the INTPIN bits of this register."> + <Enum name="PORT_0" start="0" description="Port 0" /> + <Enum name="PORT_1" start="1" description="Port 1" /> + </BitField> + <BitField start="6" size="26" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x178+16" size="4" name="PINTSEL4" access="Read/Write" description="GPIO Pin Interrupt Select register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="INTPIN" description="Pin number within the port selected by the PORTSEL bit in this register." /> + <BitField start="5" size="1" name="PORTSEL" description="Select the port for the pin number to be selected in the INTPIN bits of this register."> + <Enum name="PORT_0" start="0" description="Port 0" /> + <Enum name="PORT_1" start="1" description="Port 1" /> + </BitField> + <BitField start="6" size="26" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x178+20" size="4" name="PINTSEL5" access="Read/Write" description="GPIO Pin Interrupt Select register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="INTPIN" description="Pin number within the port selected by the PORTSEL bit in this register." /> + <BitField start="5" size="1" name="PORTSEL" description="Select the port for the pin number to be selected in the INTPIN bits of this register."> + <Enum name="PORT_0" start="0" description="Port 0" /> + <Enum name="PORT_1" start="1" description="Port 1" /> + </BitField> + <BitField start="6" size="26" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x178+24" size="4" name="PINTSEL6" access="Read/Write" description="GPIO Pin Interrupt Select register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="INTPIN" description="Pin number within the port selected by the PORTSEL bit in this register." /> + <BitField start="5" size="1" name="PORTSEL" description="Select the port for the pin number to be selected in the INTPIN bits of this register."> + <Enum name="PORT_0" start="0" description="Port 0" /> + <Enum name="PORT_1" start="1" description="Port 1" /> + </BitField> + <BitField start="6" size="26" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x178+28" size="4" name="PINTSEL7" access="Read/Write" description="GPIO Pin Interrupt Select register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="INTPIN" description="Pin number within the port selected by the PORTSEL bit in this register." /> + <BitField start="5" size="1" name="PORTSEL" description="Select the port for the pin number to be selected in the INTPIN bits of this register."> + <Enum name="PORT_0" start="0" description="Port 0" /> + <Enum name="PORT_1" start="1" description="Port 1" /> + </BitField> + <BitField start="6" size="26" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x198" size="4" name="USBCLKCTRL" access="Read/Write" description="USB clock control" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="AP_CLK" description="USB need_clock signal control"> + <Enum name="UNDER_HARDWARE_CONTR" start="0" description="Under hardware control." /> + <Enum name="FORCED_HIGH_" start="1" description="Forced HIGH." /> + </BitField> + <BitField start="1" size="1" name="POL_CLK" description="USB need_clock polarity for triggering the USB wake-up interrupt"> + <Enum name="FALLING_EDGE_OF_THE_" start="0" description="Falling edge of the USB need_clock triggers the USB wake-up (default)." /> + <Enum name="RISING_EDGE_OF_THE_U" start="1" description="Rising edge of the USB need_clock triggers the USB wake-up." /> + </BitField> + <BitField start="2" size="30" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x19C" size="4" name="USBCLKST" access="ReadOnly" description="USB clock status" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="NEED_CLKST" description="USB need_clock signal status"> + <Enum name="LOW" start="0" description="LOW" /> + <Enum name="HIGH" start="1" description="HIGH" /> + </BitField> + <BitField start="1" size="31" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x204" size="4" name="STARTERP0" access="Read/Write" description="Start logic 0 interrupt wake-up enable register 0" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="PINT0" description="Pin interrupt 0 wake-up"> + <Enum name="DISABLED" start="0" description="Disabled" /> + <Enum name="ENABLED" start="1" description="Enabled" /> + </BitField> + <BitField start="1" size="1" name="PINT1" description="Pin interrupt 1 wake-up"> + <Enum name="DISABLED" start="0" description="Disabled" /> + <Enum name="ENABLED" start="1" description="Enabled" /> + </BitField> + <BitField start="2" size="1" name="PINT2" description="Pin interrupt 2 wake-up"> + <Enum name="DISABLED" start="0" description="Disabled" /> + <Enum name="ENABLED" start="1" description="Enabled" /> + </BitField> + <BitField start="3" size="1" name="PINT3" description="Pin interrupt 3 wake-up"> + <Enum name="DISABLED" start="0" description="Disabled" /> + <Enum name="ENABLED" start="1" description="Enabled" /> + </BitField> + <BitField start="4" size="1" name="PINT4" description="Pin interrupt 4 wake-up"> + <Enum name="DISABLED" start="0" description="Disabled" /> + <Enum name="ENABLED" start="1" description="Enabled" /> + </BitField> + <BitField start="5" size="1" name="PINT5" description="Pin interrupt 5 wake-up"> + <Enum name="DISABLED" start="0" description="Disabled" /> + <Enum name="ENABLED" start="1" description="Enabled" /> + </BitField> + <BitField start="6" size="1" name="PINT6" description="Pin interrupt 6 wake-up"> + <Enum name="DISABLED" start="0" description="Disabled" /> + <Enum name="ENABLED" start="1" description="Enabled" /> + </BitField> + <BitField start="7" size="1" name="PINT7" description="Pin interrupt 7 wake-up"> + <Enum name="DISABLED" start="0" description="Disabled" /> + <Enum name="ENABLED" start="1" description="Enabled" /> + </BitField> + <BitField start="8" size="24" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x214" size="4" name="STARTERP1" access="Read/Write" description="Start logic 1 interrupt wake-up enable register 1" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="12" size="1" name="WWDTINT" description="WWDT interrupt wake-up"> + <Enum name="DISABLED" start="0" description="Disabled" /> + <Enum name="ENABLED" start="1" description="Enabled" /> + </BitField> + <BitField start="13" size="1" name="BODINT" description="Brown Out Detect (BOD) interrupt wake-up"> + <Enum name="DISABLED" start="0" description="Disabled" /> + <Enum name="ENABLED" start="1" description="Enabled" /> + </BitField> + <BitField start="14" size="5" name="RESERVED" description="Reserved" /> + <BitField start="19" size="1" name="USB_WAKEUP" description="USB need_clock signal wake-up"> + <Enum name="DISABLED" start="0" description="Disabled" /> + <Enum name="ENABLED" start="1" description="Enabled" /> + </BitField> + <BitField start="20" size="1" name="GPIOINT0" description="GPIO GROUP0 interrupt wake-up"> + <Enum name="DISABLED" start="0" description="Disabled" /> + <Enum name="ENABLED" start="1" description="Enabled" /> + </BitField> + <BitField start="21" size="1" name="GPIOINT1" description="GPIO GROUP1 interrupt wake-up"> + <Enum name="DISABLED" start="0" description="Disabled" /> + <Enum name="ENABLED" start="1" description="Enabled" /> + </BitField> + </Register> + <Register start="+0x230" size="4" name="PDSLEEPCFG" access="Read/Write" description="Power-down states in deep-sleep mode" reset_value="0" reset_mask="0x00000000"> + <BitField start="3" size="1" name="BOD_PD" description="BOD power-down control for Deep-sleep and Power-down mode"> + <Enum name="POWERED_DOWN" start="1" description="Powered down" /> + <Enum name="POWERED" start="0" description="Powered" /> + </BitField> + <BitField start="6" size="1" name="WDTOSC_PD" description="Watchdog oscillator power-down control for Deep-sleep and Power-down mode"> + <Enum name="POWERED_DOWN" start="1" description="Powered down" /> + <Enum name="POWERED" start="0" description="Powered" /> + </BitField> + <BitField start="7" size="25" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x234" size="4" name="PDAWAKECFG" access="Read/Write" description="Power-down states for wake-up from deep-sleep" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="IRCOUT_PD" description="IRC oscillator output wake-up configuration"> + <Enum name="POWERED_DOWN" start="1" description="Powered down" /> + <Enum name="POWERED" start="0" description="Powered" /> + </BitField> + <BitField start="1" size="1" name="IRC_PD" description="IRC oscillator power-down wake-up configuration"> + <Enum name="POWERED_DOWN" start="1" description="Powered down" /> + <Enum name="POWERED" start="0" description="Powered" /> + </BitField> + <BitField start="2" size="1" name="FLASH_PD" description="Flash wake-up configuration"> + <Enum name="POWERED_DOWN" start="1" description="Powered down" /> + <Enum name="POWERED" start="0" description="Powered" /> + </BitField> + <BitField start="3" size="1" name="BOD_PD" description="BOD wake-up configuration"> + <Enum name="POWERED_DOWN" start="1" description="Powered down" /> + <Enum name="POWERED" start="0" description="Powered" /> + </BitField> + <BitField start="4" size="1" name="ADC_PD" description="ADC wake-up configuration"> + <Enum name="POWERED_DOWN" start="1" description="Powered down" /> + <Enum name="POWERED" start="0" description="Powered" /> + </BitField> + <BitField start="5" size="1" name="SYSOSC_PD" description="Crystal oscillator wake-up configuration"> + <Enum name="POWERED_DOWN" start="1" description="Powered down" /> + <Enum name="POWERED" start="0" description="Powered" /> + </BitField> + <BitField start="6" size="1" name="WDTOSC_PD" description="Watchdog oscillator wake-up configuration"> + <Enum name="POWERED_DOWN" start="1" description="Powered down" /> + <Enum name="POWERED" start="0" description="Powered" /> + </BitField> + <BitField start="7" size="1" name="SYSPLL_PD" description="System PLL wake-up configuration"> + <Enum name="POWERED_DOWN" start="1" description="Powered down" /> + <Enum name="POWERED" start="0" description="Powered" /> + </BitField> + <BitField start="8" size="1" name="USBPLL_PD" description="USB PLL wake-up configuration"> + <Enum name="POWERED" start="0" description="Powered" /> + <Enum name="POWERED_DOWN" start="1" description="Powered down" /> + </BitField> + <BitField start="9" size="1" name="RESERVED" description="Reserved. Always write this bit as 0." /> + <BitField start="10" size="1" name="USBPAD_PD" description="USB transceiver wake-up configuration"> + <Enum name="USB_TRANSCEIVER_POWE" start="0" description="USB transceiver powered" /> + <Enum name="USB_TRANSCEIVER_POWE" start="1" description="USB transceiver powered down" /> + </BitField> + <BitField start="11" size="1" name="RESERVED" description="Reserved. This bit must be set to one in Run mode." /> + <BitField start="12" size="1" name="RESERVED" description="Reserved." /> + <BitField start="13" size="19" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x238" size="4" name="PDRUNCFG" access="Read/Write" description="Power configuration register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="IRCOUT_PD" description="IRC oscillator output power-down"> + <Enum name="POWERED_DOWN" start="1" description="Powered down" /> + <Enum name="POWERED" start="0" description="Powered" /> + </BitField> + <BitField start="1" size="1" name="IRC_PD" description="IRC oscillator power-down"> + <Enum name="POWERED_DOWN" start="1" description="Powered down" /> + <Enum name="POWERED" start="0" description="Powered" /> + </BitField> + <BitField start="2" size="1" name="FLASH_PD" description="Flash power-down"> + <Enum name="POWERED_DOWN" start="1" description="Powered down" /> + <Enum name="POWERED" start="0" description="Powered" /> + </BitField> + <BitField start="3" size="1" name="BOD_PD" description="BOD power-down"> + <Enum name="POWERED_DOWN" start="1" description="Powered down" /> + <Enum name="POWERED" start="0" description="Powered" /> + </BitField> + <BitField start="4" size="1" name="ADC_PD" description="ADC power-down"> + <Enum name="POWERED_DOWN" start="1" description="Powered down" /> + <Enum name="POWERED" start="0" description="Powered" /> + </BitField> + <BitField start="5" size="1" name="SYSOSC_PD" description="Crystal oscillator power-down"> + <Enum name="POWERED_DOWN" start="1" description="Powered down" /> + <Enum name="POWERED" start="0" description="Powered" /> + </BitField> + <BitField start="6" size="1" name="WDTOSC_PD" description="Watchdog oscillator power-down"> + <Enum name="POWERED_DOWN" start="1" description="Powered down" /> + <Enum name="POWERED" start="0" description="Powered" /> + </BitField> + <BitField start="7" size="1" name="SYSPLL_PD" description="System PLL power-down"> + <Enum name="POWERED_DOWN" start="1" description="Powered down" /> + <Enum name="POWERED" start="0" description="Powered" /> + </BitField> + <BitField start="8" size="1" name="USBPLL_PD" description="USB PLL power-down"> + <Enum name="POWERED" start="0" description="Powered" /> + <Enum name="POWERED_DOWN" start="1" description="Powered down" /> + </BitField> + <BitField start="9" size="1" name="RESERVED" description="Reserved. Always write this bit as 0." /> + <BitField start="10" size="1" name="USBPAD_PD" description="USB transceiver power-down configuration"> + <Enum name="USB_TRANSCEIVER_POWE" start="0" description="USB transceiver powered" /> + <Enum name="USB_TRANSCEIVER_POWE" start="1" description="USB transceiver powered down (suspend mode)" /> + </BitField> + <BitField start="11" size="1" name="RESERVED" description="Reserved. This bit must be set to one in Run mode." /> + <BitField start="12" size="1" name="RESERVED" description="Reserved." /> + <BitField start="13" size="3" name="RESERVED" description="Reserved. Always write these bits as 111." /> + <BitField start="16" size="16" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x3F8" size="4" name="DEVICE_ID" access="ReadOnly" description="Device ID" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="DEVICEID" description="LPC1345FHN33 = 0x2801 0541 LPC1345FBD48 = 0x2801 0541 LPC1346FHN33 = 0x0801 8542 LPC1346FBD48 = 0x0801 8542 LPC1347FHN33 = 0x0802 0543 LPC1347FBD48 = 0x0802 0543 LPC1347FBD64 = 0x0802 0543 LPC1315FHN33 = 0x3A01 0523 LPC1315FBD48 = 0x3A01 0523 LPC1316FHN33 = 0x1A01 8524 LPC1316FBD48 = 0x1A01 8524 LPC1317FHN33 = 0x1A02 0525 LPC1317FBD48 = 0x1A02 0525 LPC1317FBD64 = 0x1A02 0525" /> + </Register> + </RegisterGroup> + <RegisterGroup name="GPIO_PIN_INT" start="0x4004C000" description="GPIO pin interrupt "> + <Register start="+0x000" size="4" name="ISEL" access="Read/Write" description="Pin Interrupt Mode register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="PMODE0" description="Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive" /> + <BitField start="1" size="1" name="PMODE1" description="Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive" /> + <BitField start="2" size="1" name="PMODE2" description="Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive" /> + <BitField start="3" size="1" name="PMODE3" description="Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive" /> + <BitField start="4" size="1" name="PMODE4" description="Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive" /> + <BitField start="5" size="1" name="PMODE5" description="Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive" /> + <BitField start="6" size="1" name="PMODE6" description="Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive" /> + <BitField start="7" size="1" name="PMODE7" description="Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive" /> + <BitField start="8" size="24" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x004" size="4" name="IENR" access="Read/Write" description="Pin Interrupt Enable (Rising) register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="ENRL0" description="Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt." /> + <BitField start="1" size="1" name="ENRL1" description="Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt." /> + <BitField start="2" size="1" name="ENRL2" description="Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt." /> + <BitField start="3" size="1" name="ENRL3" description="Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt." /> + <BitField start="4" size="1" name="ENRL4" description="Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt." /> + <BitField start="5" size="1" name="ENRL5" description="Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt." /> + <BitField start="6" size="1" name="ENRL6" description="Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt." /> + <BitField start="7" size="1" name="ENRL7" description="Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x008" size="4" name="SIENR" access="WriteOnly" description="Set Pin Interrupt Enable (Rising) register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="SETENRL0" description="Ones written to this address set bits in the PINTEN_R, thus enabling interrupts. Bit n sets bit n in the PINTEN_R register. 0 = No operation. 1 = Enable rising edge or level interrupt." /> + <BitField start="1" size="1" name="SETENRL1" description="Ones written to this address set bits in the PINTEN_R, thus enabling interrupts. Bit n sets bit n in the PINTEN_R register. 0 = No operation. 1 = Enable rising edge or level interrupt." /> + <BitField start="2" size="1" name="SETENRL2" description="Ones written to this address set bits in the PINTEN_R, thus enabling interrupts. Bit n sets bit n in the PINTEN_R register. 0 = No operation. 1 = Enable rising edge or level interrupt." /> + <BitField start="3" size="1" name="SETENRL3" description="Ones written to this address set bits in the PINTEN_R, thus enabling interrupts. Bit n sets bit n in the PINTEN_R register. 0 = No operation. 1 = Enable rising edge or level interrupt." /> + <BitField start="4" size="1" name="SETENRL4" description="Ones written to this address set bits in the PINTEN_R, thus enabling interrupts. Bit n sets bit n in the PINTEN_R register. 0 = No operation. 1 = Enable rising edge or level interrupt." /> + <BitField start="5" size="1" name="SETENRL5" description="Ones written to this address set bits in the PINTEN_R, thus enabling interrupts. Bit n sets bit n in the PINTEN_R register. 0 = No operation. 1 = Enable rising edge or level interrupt." /> + <BitField start="6" size="1" name="SETENRL6" description="Ones written to this address set bits in the PINTEN_R, thus enabling interrupts. Bit n sets bit n in the PINTEN_R register. 0 = No operation. 1 = Enable rising edge or level interrupt." /> + <BitField start="7" size="1" name="SETENRL7" description="Ones written to this address set bits in the PINTEN_R, thus enabling interrupts. Bit n sets bit n in the PINTEN_R register. 0 = No operation. 1 = Enable rising edge or level interrupt." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x00C" size="4" name="CIENR" access="WriteOnly" description="Clear Pin Interrupt Enable (Rising) register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="CENRL0" description="Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt." /> + <BitField start="1" size="1" name="CENRL1" description="Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt." /> + <BitField start="2" size="1" name="CENRL2" description="Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt." /> + <BitField start="3" size="1" name="CENRL3" description="Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt." /> + <BitField start="4" size="1" name="CENRL4" description="Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt." /> + <BitField start="5" size="1" name="CENRL5" description="Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt." /> + <BitField start="6" size="1" name="CENRL6" description="Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt." /> + <BitField start="7" size="1" name="CENRL7" description="Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x010" size="4" name="IENF" access="Read/Write" description="Pin Interrupt Enable Falling Edge / Active Level register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="ENAF0" description="Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH." /> + <BitField start="1" size="1" name="ENAF1" description="Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH." /> + <BitField start="2" size="1" name="ENAF2" description="Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH." /> + <BitField start="3" size="1" name="ENAF3" description="Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH." /> + <BitField start="4" size="1" name="ENAF4" description="Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH." /> + <BitField start="5" size="1" name="ENAF5" description="Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH." /> + <BitField start="6" size="1" name="ENAF6" description="Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH." /> + <BitField start="7" size="1" name="ENAF7" description="Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x014" size="4" name="SIENF" access="WriteOnly" description="Set Pin Interrupt Enable Falling Edge / Active Level register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="SETENAF0" description="Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt." /> + <BitField start="1" size="1" name="SETENAF1" description="Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt." /> + <BitField start="2" size="1" name="SETENAF2" description="Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt." /> + <BitField start="3" size="1" name="SETENAF3" description="Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt." /> + <BitField start="4" size="1" name="SETENAF4" description="Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt." /> + <BitField start="5" size="1" name="SETENAF5" description="Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt." /> + <BitField start="6" size="1" name="SETENAF6" description="Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt." /> + <BitField start="7" size="1" name="SETENAF7" description="Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x018" size="4" name="CIENF" access="WriteOnly" description="Clear Pin Interrupt Enable Falling Edge / Active Level address" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="CENAF0" description="Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled." /> + <BitField start="1" size="1" name="CENAF1" description="Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled." /> + <BitField start="2" size="1" name="CENAF2" description="Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled." /> + <BitField start="3" size="1" name="CENAF3" description="Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled." /> + <BitField start="4" size="1" name="CENAF4" description="Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled." /> + <BitField start="5" size="1" name="CENAF5" description="Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled." /> + <BitField start="6" size="1" name="CENAF6" description="Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled." /> + <BitField start="7" size="1" name="CENAF7" description="Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x01C" size="4" name="RISE" access="Read/Write" description="Pin Interrupt Rising Edge register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RDET0" description="Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin." /> + <BitField start="1" size="1" name="RDET1" description="Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin." /> + <BitField start="2" size="1" name="RDET2" description="Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin." /> + <BitField start="3" size="1" name="RDET3" description="Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin." /> + <BitField start="4" size="1" name="RDET4" description="Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin." /> + <BitField start="5" size="1" name="RDET5" description="Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin." /> + <BitField start="6" size="1" name="RDET6" description="Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin." /> + <BitField start="7" size="1" name="RDET7" description="Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x020" size="4" name="FALL" access="Read/Write" description="Pin Interrupt Falling Edge register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="FDET0" description="Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin." /> + <BitField start="1" size="1" name="FDET1" description="Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin." /> + <BitField start="2" size="1" name="FDET2" description="Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin." /> + <BitField start="3" size="1" name="FDET3" description="Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin." /> + <BitField start="4" size="1" name="FDET4" description="Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin." /> + <BitField start="5" size="1" name="FDET5" description="Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin." /> + <BitField start="6" size="1" name="FDET6" description="Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin." /> + <BitField start="7" size="1" name="FDET7" description="Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x024" size="4" name="IST" access="Read/Write" description="Pin Interrupt Status register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="PSTAT0" description="Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin. Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the PINTENT_F register)." /> + <BitField start="1" size="1" name="PSTAT1" description="Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin. Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the PINTENT_F register)." /> + <BitField start="2" size="1" name="PSTAT2" description="Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin. Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the PINTENT_F register)." /> + <BitField start="3" size="1" name="PSTAT3" description="Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin. Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the PINTENT_F register)." /> + <BitField start="4" size="1" name="PSTAT4" description="Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin. Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the PINTENT_F register)." /> + <BitField start="5" size="1" name="PSTAT5" description="Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin. Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the PINTENT_F register)." /> + <BitField start="6" size="1" name="PSTAT6" description="Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin. Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the PINTENT_F register)." /> + <BitField start="7" size="1" name="PSTAT7" description="Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin. Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the PINTENT_F register)." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved." /> + </Register> + </RegisterGroup> + <RegisterGroup name="SSP1" start="0x40058000" description="SSP/SPI"> + <Register start="+0x000" size="4" name="CR0" access="Read/Write" description="Control Register 0. Selects the serial clock rate, bus type, and data size." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="4" name="DSS" description="Data Size Select. This field controls the number of bits transferred in each frame. Values 0000-0010 are not supported and should not be used."> + <Enum name="4_BIT_TRANSFER" start="0x3" description="4-bit transfer" /> + <Enum name="5_BIT_TRANSFER" start="0x4" description="5-bit transfer" /> + <Enum name="6_BIT_TRANSFER" start="0x5" description="6-bit transfer" /> + <Enum name="7_BIT_TRANSFER" start="0x6" description="7-bit transfer" /> + <Enum name="8_BIT_TRANSFER" start="0x7" description="8-bit transfer" /> + <Enum name="9_BIT_TRANSFER" start="0x8" description="9-bit transfer" /> + <Enum name="10_BIT_TRANSFER" start="0x9" description="10-bit transfer" /> + <Enum name="11_BIT_TRANSFER" start="0xA" description="11-bit transfer" /> + <Enum name="12_BIT_TRANSFER" start="0xB" description="12-bit transfer" /> + <Enum name="13_BIT_TRANSFER" start="0xC" description="13-bit transfer" /> + <Enum name="14_BIT_TRANSFER" start="0xD" description="14-bit transfer" /> + <Enum name="15_BIT_TRANSFER" start="0xE" description="15-bit transfer" /> + <Enum name="16_BIT_TRANSFER" start="0xF" description="16-bit transfer" /> + </BitField> + <BitField start="4" size="2" name="FRF" description="Frame Format."> + <Enum name="SPI" start="0x0" description="SPI" /> + <Enum name="TI" start="0x1" description="TI" /> + <Enum name="MICROWIRE" start="0x2" description="Microwire" /> + <Enum name="RESERVED" start="0x3" description="This combination is not supported and should not be used." /> + </BitField> + <BitField start="6" size="1" name="CPOL" description="Clock Out Polarity. This bit is only used in SPI mode."> + <Enum name="LOW" start="0" description="SPI controller maintains the bus clock low between frames." /> + <Enum name="HIGH" start="1" description="SPI controller maintains the bus clock high between frames." /> + </BitField> + <BitField start="7" size="1" name="CPHA" description="Clock Out Phase. This bit is only used in SPI mode."> + <Enum name="FIRSTCLOCK" start="0" description="SPI controller captures serial data on the first clock transition of the frame, that is, the transition away from the inter-frame state of the clock line." /> + <Enum name="SECONDCLOCK" start="1" description="SPI controller captures serial data on the second clock transition of the frame, that is, the transition back to the inter-frame state of the clock line." /> + </BitField> + <BitField start="8" size="8" name="SCR" description="Serial Clock Rate. The number of prescaler output clocks per bit on the bus, minus one. Given that CPSDVSR is the prescale divider, and the APB clock PCLK clocks the prescaler, the bit frequency is PCLK / (CPSDVSR X [SCR+1])." /> + <BitField start="16" size="16" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x004" size="4" name="CR1" access="Read/Write" description="Control Register 1. Selects master/slave and other modes." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="LBM" description="Loop Back Mode."> + <Enum name="DURING_NORMAL_OPERAT" start="0" description="During normal operation." /> + <Enum name="SERIAL_INPUT_IS_TAKE" start="1" description="Serial input is taken from the serial output (MOSI or MISO) rather than the serial input pin (MISO or MOSI respectively)." /> + </BitField> + <BitField start="1" size="1" name="SSE" description="SPI Enable."> + <Enum name="DISABLED" start="0" description="The SPI controller is disabled." /> + <Enum name="ENABLED" start="1" description="The SPI controller will interact with other devices on the serial bus. Software should write the appropriate control information to the other SSP/SPI registers and interrupt controller registers, before setting this bit." /> + </BitField> + <BitField start="2" size="1" name="MS" description="Master/Slave Mode.This bit can only be written when the SSE bit is 0."> + <Enum name="MASTER" start="0" description="The SPI controller acts as a master on the bus, driving the SCLK, MOSI, and SSEL lines and receiving the MISO line." /> + <Enum name="SLAVE" start="1" description="The SPI controller acts as a slave on the bus, driving MISO line and receiving SCLK, MOSI, and SSEL lines." /> + </BitField> + <BitField start="3" size="1" name="SOD" description="Slave Output Disable. This bit is relevant only in slave mode (MS = 1). If it is 1, this blocks this SPI controller from driving the transmit data line (MISO)." /> + <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x008" size="4" name="DR" access="None" description="Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="16" name="DATA" description="Write: software can write data to be sent in a future frame to this register whenever the TNF bit in the Status register is 1, indicating that the Tx FIFO is not full. If the Tx FIFO was previously empty and the SPI controller is not busy on the bus, transmission of the data will begin immediately. Otherwise the data written to this register will be sent as soon as all previous data has been sent (and received). If the data length is less than 16 bit, software must right-justify the data written to this register. Read: software can read data from this register whenever the RNE bit in the Status register is 1, indicating that the Rx FIFO is not empty. When software reads this register, the SPI controller returns data from the least recent frame in the Rx FIFO. If the data length is less than 16 bit, the data is right-justified in this field with higher order bits filled with 0s." /> + <BitField start="16" size="16" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x00C" size="4" name="SR" access="ReadOnly" description="Status Register" reset_value="0x00000003" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="TFE" description="Transmit FIFO Empty. This bit is 1 is the Transmit FIFO is empty, 0 if not." /> + <BitField start="1" size="1" name="TNF" description="Transmit FIFO Not Full. This bit is 0 if the Tx FIFO is full, 1 if not." /> + <BitField start="2" size="1" name="RNE" description="Receive FIFO Not Empty. This bit is 0 if the Receive FIFO is empty, 1 if not." /> + <BitField start="3" size="1" name="RFF" description="Receive FIFO Full. This bit is 1 if the Receive FIFO is full, 0 if not." /> + <BitField start="4" size="1" name="BSY" description="Busy. This bit is 0 if the SPI controller is idle, 1 if it is currently sending/receiving a frame and/or the Tx FIFO is not empty." /> + <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x010" size="4" name="CPSR" access="Read/Write" description="Clock Prescale Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="CPSDVSR" description="This even value between 2 and 254, by which SPI_PCLK is divided to yield the prescaler output clock. Bit 0 always reads as 0." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x014" size="4" name="IMSC" access="Read/Write" description="Interrupt Mask Set and Clear Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RORIM" description="Software should set this bit to enable interrupt when a Receive Overrun occurs, that is, when the Rx FIFO is full and another frame is completely received. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs." /> + <BitField start="1" size="1" name="RTIM" description="Software should set this bit to enable interrupt when a Receive Time-out condition occurs. A Receive Time-out occurs when the Rx FIFO is not empty, and no has not been read for a time-out period. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1])." /> + <BitField start="2" size="1" name="RXIM" description="Software should set this bit to enable interrupt when the Rx FIFO is at least half full." /> + <BitField start="3" size="1" name="TXIM" description="Software should set this bit to enable interrupt when the Tx FIFO is at least half empty." /> + <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x018" size="4" name="RIS" access="ReadOnly" description="Raw Interrupt Status Register" reset_value="0x00000008" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RORRIS" description="This bit is 1 if another frame was completely received while the RxFIFO was full. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs." /> + <BitField start="1" size="1" name="RTRIS" description="This bit is 1 if the Rx FIFO is not empty, and has not been read for a time-out period. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1])." /> + <BitField start="2" size="1" name="RXRIS" description="This bit is 1 if the Rx FIFO is at least half full." /> + <BitField start="3" size="1" name="TXRIS" description="This bit is 1 if the Tx FIFO is at least half empty." /> + <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x01C" size="4" name="MIS" access="ReadOnly" description="Masked Interrupt Status Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RORMIS" description="This bit is 1 if another frame was completely received while the RxFIFO was full, and this interrupt is enabled." /> + <BitField start="1" size="1" name="RTMIS" description="This bit is 1 if the Rx FIFO is not empty, has not been read for a time-out period, and this interrupt is enabled. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1])." /> + <BitField start="2" size="1" name="RXMIS" description="This bit is 1 if the Rx FIFO is at least half full, and this interrupt is enabled." /> + <BitField start="3" size="1" name="TXMIS" description="This bit is 1 if the Tx FIFO is at least half empty, and this interrupt is enabled." /> + <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x020" size="4" name="ICR" access="WriteOnly" description="SSPICR Interrupt Clear Register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="RORIC" description="Writing a 1 to this bit clears the frame was received when RxFIFO was full interrupt." /> + <BitField start="1" size="1" name="RTIC" description="Writing a 1 to this bit clears the Rx FIFO was not empty and has not been read for a timeout period interrupt. The timeout period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1])." /> + <BitField start="2" size="30" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + </RegisterGroup> + <RegisterGroup name="GPIO_GROUP_INT0" start="0x4005C000" description="GPIO group interrupt "> + <Register start="+0x000" size="4" name="CTRL" access="Read/Write" description="GPIO grouped interrupt control register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="INT" description="Group interrupt status. This bit is cleared by writing a one to it. Writing zero has no effect."> + <Enum name="NO_INTERRUPT_REQUEST" start="0" description="No interrupt request is pending." /> + <Enum name="INTERRUPT_REQUEST_IS" start="1" description="Interrupt request is active." /> + </BitField> + <BitField start="1" size="1" name="COMB" description="Combine enabled inputs for group interrupt"> + <Enum name="OR_FUNCTIONALITY_A_" start="0" description="OR functionality: A grouped interrupt is generated when any one of the enabled inputs is active (based on its programmed polarity)." /> + <Enum name="AND_FUNCTIONALITY_A" start="1" description="AND functionality: An interrupt is generated when all enabled bits are active (based on their programmed polarity)." /> + </BitField> + <BitField start="2" size="1" name="TRIG" description="Group interrupt trigger"> + <Enum name="EDGE_TRIGGERED" start="0" description="Edge-triggered" /> + <Enum name="LEVEL_TRIGGERED" start="1" description="Level-triggered" /> + </BitField> + <BitField start="3" size="29" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x020+0" size="4" name="PORT_POL0" access="Read/Write" description="GPIO grouped interrupt port 0 polarity register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="POL_0" description="Configure pin polarity of port pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1 . 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="1" size="1" name="POL_1" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="2" size="1" name="POL_2" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="3" size="1" name="POL_3" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="4" size="1" name="POL_4" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="5" size="1" name="POL_5" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="6" size="1" name="POL_6" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="7" size="1" name="POL_7" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="8" size="1" name="POL_8" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="9" size="1" name="POL_9" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="10" size="1" name="POL_10" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="11" size="1" name="POL_11" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="12" size="1" name="POL_12" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="13" size="1" name="POL_13" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="14" size="1" name="POL_14" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="15" size="1" name="POL_15" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="16" size="1" name="POL_16" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="17" size="1" name="POL_17" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="18" size="1" name="POL_18" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="19" size="1" name="POL_19" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="20" size="1" name="POL_20" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="21" size="1" name="POL_21" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="22" size="1" name="POL_22" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="23" size="1" name="POL_23" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="24" size="1" name="POL_24" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="25" size="1" name="POL_25" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="26" size="1" name="POL_26" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="27" size="1" name="POL_27" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="28" size="1" name="POL_28" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="29" size="1" name="POL_29" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="30" size="1" name="POL_30" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="31" size="1" name="POL_31" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + </Register> + <Register start="+0x020+4" size="4" name="PORT_POL1" access="Read/Write" description="GPIO grouped interrupt port 0 polarity register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="POL_0" description="Configure pin polarity of port pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1 . 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="1" size="1" name="POL_1" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="2" size="1" name="POL_2" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="3" size="1" name="POL_3" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="4" size="1" name="POL_4" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="5" size="1" name="POL_5" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="6" size="1" name="POL_6" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="7" size="1" name="POL_7" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="8" size="1" name="POL_8" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="9" size="1" name="POL_9" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="10" size="1" name="POL_10" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="11" size="1" name="POL_11" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="12" size="1" name="POL_12" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="13" size="1" name="POL_13" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="14" size="1" name="POL_14" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="15" size="1" name="POL_15" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="16" size="1" name="POL_16" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="17" size="1" name="POL_17" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="18" size="1" name="POL_18" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="19" size="1" name="POL_19" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="20" size="1" name="POL_20" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="21" size="1" name="POL_21" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="22" size="1" name="POL_22" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="23" size="1" name="POL_23" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="24" size="1" name="POL_24" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="25" size="1" name="POL_25" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="26" size="1" name="POL_26" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="27" size="1" name="POL_27" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="28" size="1" name="POL_28" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="29" size="1" name="POL_29" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="30" size="1" name="POL_30" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="31" size="1" name="POL_31" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + </Register> + <Register start="+0x040+0" size="4" name="PORT_ENA0" access="Read/Write" description="GPIO grouped interrupt port 0/1 enable register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="ENA_0" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="1" size="1" name="ENA_1" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="2" size="1" name="ENA_2" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="3" size="1" name="ENA_3" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="4" size="1" name="ENA_4" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="5" size="1" name="ENA_5" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="6" size="1" name="ENA_6" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="7" size="1" name="ENA_7" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="8" size="1" name="ENA_8" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="9" size="1" name="ENA_9" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="10" size="1" name="ENA_10" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="11" size="1" name="ENA_11" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="12" size="1" name="ENA_12" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="13" size="1" name="ENA_13" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="14" size="1" name="ENA_14" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="15" size="1" name="ENA_15" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="16" size="1" name="ENA_16" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="17" size="1" name="ENA_17" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="18" size="1" name="ENA_18" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="19" size="1" name="ENA_19" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="20" size="1" name="ENA_20" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="21" size="1" name="ENA_21" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="22" size="1" name="ENA_22" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="23" size="1" name="ENA_23" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="24" size="1" name="ENA_24" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="25" size="1" name="ENA_25" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="26" size="1" name="ENA_26" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="27" size="1" name="ENA_27" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="28" size="1" name="ENA_28" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="29" size="1" name="ENA_29" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="30" size="1" name="ENA_30" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="31" size="1" name="ENA_31" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." /> + </Register> + <Register start="+0x040+4" size="4" name="PORT_ENA1" access="Read/Write" description="GPIO grouped interrupt port 0/1 enable register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="ENA_0" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="1" size="1" name="ENA_1" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="2" size="1" name="ENA_2" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="3" size="1" name="ENA_3" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="4" size="1" name="ENA_4" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="5" size="1" name="ENA_5" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="6" size="1" name="ENA_6" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="7" size="1" name="ENA_7" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="8" size="1" name="ENA_8" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="9" size="1" name="ENA_9" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="10" size="1" name="ENA_10" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="11" size="1" name="ENA_11" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="12" size="1" name="ENA_12" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="13" size="1" name="ENA_13" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="14" size="1" name="ENA_14" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="15" size="1" name="ENA_15" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="16" size="1" name="ENA_16" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="17" size="1" name="ENA_17" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="18" size="1" name="ENA_18" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="19" size="1" name="ENA_19" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="20" size="1" name="ENA_20" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="21" size="1" name="ENA_21" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="22" size="1" name="ENA_22" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="23" size="1" name="ENA_23" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="24" size="1" name="ENA_24" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="25" size="1" name="ENA_25" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="26" size="1" name="ENA_26" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="27" size="1" name="ENA_27" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="28" size="1" name="ENA_28" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="29" size="1" name="ENA_29" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="30" size="1" name="ENA_30" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="31" size="1" name="ENA_31" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." /> + </Register> + </RegisterGroup> + <RegisterGroup name="GPIO_GROUP_INT1" start="0x40060000" description="GPIO group interrupt "> + <Register start="+0x000" size="4" name="CTRL" access="Read/Write" description="GPIO grouped interrupt control register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="INT" description="Group interrupt status. This bit is cleared by writing a one to it. Writing zero has no effect."> + <Enum name="NO_INTERRUPT_REQUEST" start="0" description="No interrupt request is pending." /> + <Enum name="INTERRUPT_REQUEST_IS" start="1" description="Interrupt request is active." /> + </BitField> + <BitField start="1" size="1" name="COMB" description="Combine enabled inputs for group interrupt"> + <Enum name="OR_FUNCTIONALITY_A_" start="0" description="OR functionality: A grouped interrupt is generated when any one of the enabled inputs is active (based on its programmed polarity)." /> + <Enum name="AND_FUNCTIONALITY_A" start="1" description="AND functionality: An interrupt is generated when all enabled bits are active (based on their programmed polarity)." /> + </BitField> + <BitField start="2" size="1" name="TRIG" description="Group interrupt trigger"> + <Enum name="EDGE_TRIGGERED" start="0" description="Edge-triggered" /> + <Enum name="LEVEL_TRIGGERED" start="1" description="Level-triggered" /> + </BitField> + <BitField start="3" size="29" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x020+0" size="4" name="PORT_POL0" access="Read/Write" description="GPIO grouped interrupt port 0 polarity register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="POL_0" description="Configure pin polarity of port pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1 . 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="1" size="1" name="POL_1" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="2" size="1" name="POL_2" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="3" size="1" name="POL_3" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="4" size="1" name="POL_4" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="5" size="1" name="POL_5" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="6" size="1" name="POL_6" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="7" size="1" name="POL_7" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="8" size="1" name="POL_8" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="9" size="1" name="POL_9" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="10" size="1" name="POL_10" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="11" size="1" name="POL_11" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="12" size="1" name="POL_12" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="13" size="1" name="POL_13" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="14" size="1" name="POL_14" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="15" size="1" name="POL_15" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="16" size="1" name="POL_16" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="17" size="1" name="POL_17" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="18" size="1" name="POL_18" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="19" size="1" name="POL_19" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="20" size="1" name="POL_20" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="21" size="1" name="POL_21" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="22" size="1" name="POL_22" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="23" size="1" name="POL_23" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="24" size="1" name="POL_24" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="25" size="1" name="POL_25" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="26" size="1" name="POL_26" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="27" size="1" name="POL_27" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="28" size="1" name="POL_28" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="29" size="1" name="POL_29" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="30" size="1" name="POL_30" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="31" size="1" name="POL_31" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + </Register> + <Register start="+0x020+4" size="4" name="PORT_POL1" access="Read/Write" description="GPIO grouped interrupt port 0 polarity register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="POL_0" description="Configure pin polarity of port pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1 . 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="1" size="1" name="POL_1" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="2" size="1" name="POL_2" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="3" size="1" name="POL_3" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="4" size="1" name="POL_4" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="5" size="1" name="POL_5" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="6" size="1" name="POL_6" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="7" size="1" name="POL_7" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="8" size="1" name="POL_8" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="9" size="1" name="POL_9" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="10" size="1" name="POL_10" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="11" size="1" name="POL_11" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="12" size="1" name="POL_12" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="13" size="1" name="POL_13" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="14" size="1" name="POL_14" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="15" size="1" name="POL_15" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="16" size="1" name="POL_16" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="17" size="1" name="POL_17" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="18" size="1" name="POL_18" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="19" size="1" name="POL_19" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="20" size="1" name="POL_20" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="21" size="1" name="POL_21" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="22" size="1" name="POL_22" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="23" size="1" name="POL_23" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="24" size="1" name="POL_24" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="25" size="1" name="POL_25" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="26" size="1" name="POL_26" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="27" size="1" name="POL_27" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="28" size="1" name="POL_28" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="29" size="1" name="POL_29" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="30" size="1" name="POL_30" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + <BitField start="31" size="1" name="POL_31" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." /> + </Register> + <Register start="+0x040+0" size="4" name="PORT_ENA0" access="Read/Write" description="GPIO grouped interrupt port 0/1 enable register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="ENA_0" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="1" size="1" name="ENA_1" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="2" size="1" name="ENA_2" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="3" size="1" name="ENA_3" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="4" size="1" name="ENA_4" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="5" size="1" name="ENA_5" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="6" size="1" name="ENA_6" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="7" size="1" name="ENA_7" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="8" size="1" name="ENA_8" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="9" size="1" name="ENA_9" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="10" size="1" name="ENA_10" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="11" size="1" name="ENA_11" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="12" size="1" name="ENA_12" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="13" size="1" name="ENA_13" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="14" size="1" name="ENA_14" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="15" size="1" name="ENA_15" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="16" size="1" name="ENA_16" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="17" size="1" name="ENA_17" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="18" size="1" name="ENA_18" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="19" size="1" name="ENA_19" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="20" size="1" name="ENA_20" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="21" size="1" name="ENA_21" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="22" size="1" name="ENA_22" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="23" size="1" name="ENA_23" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="24" size="1" name="ENA_24" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="25" size="1" name="ENA_25" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="26" size="1" name="ENA_26" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="27" size="1" name="ENA_27" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="28" size="1" name="ENA_28" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="29" size="1" name="ENA_29" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="30" size="1" name="ENA_30" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="31" size="1" name="ENA_31" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." /> + </Register> + <Register start="+0x040+4" size="4" name="PORT_ENA1" access="Read/Write" description="GPIO grouped interrupt port 0/1 enable register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="ENA_0" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="1" size="1" name="ENA_1" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="2" size="1" name="ENA_2" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="3" size="1" name="ENA_3" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="4" size="1" name="ENA_4" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="5" size="1" name="ENA_5" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="6" size="1" name="ENA_6" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="7" size="1" name="ENA_7" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="8" size="1" name="ENA_8" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="9" size="1" name="ENA_9" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="10" size="1" name="ENA_10" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="11" size="1" name="ENA_11" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="12" size="1" name="ENA_12" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="13" size="1" name="ENA_13" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="14" size="1" name="ENA_14" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="15" size="1" name="ENA_15" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="16" size="1" name="ENA_16" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="17" size="1" name="ENA_17" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="18" size="1" name="ENA_18" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="19" size="1" name="ENA_19" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="20" size="1" name="ENA_20" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="21" size="1" name="ENA_21" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="22" size="1" name="ENA_22" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="23" size="1" name="ENA_23" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="24" size="1" name="ENA_24" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="25" size="1" name="ENA_25" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="26" size="1" name="ENA_26" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="27" size="1" name="ENA_27" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="28" size="1" name="ENA_28" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="29" size="1" name="ENA_29" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="30" size="1" name="ENA_30" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." /> + <BitField start="31" size="1" name="ENA_31" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." /> + </Register> + </RegisterGroup> + <RegisterGroup name="RITIMER" start="0x40064000" description="Repetitive Interrupt Timer (RI timer)"> + <Register start="+0x000" size="4" name="COMPVAL" access="Read/Write" description="Compare value LSB register. Holds the 32 LSBs of the compare value." reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="RICOMP" description="Compare register. Holds the 32 LSBs of the compare value which is compared to the counter." /> + </Register> + <Register start="+0x004" size="4" name="MASK" access="Read/Write" description="Mask LSB register. This register holds the 32 LSB s of the mask value. A one written to any bit will force a compare on the corresponding bit of the counter and compare register." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="RIMASK" description="Mask register. This register holds the 32 LSBs of the mask value. A one written to any bit overrides the result of the comparison for the corresponding bit of the counter and compare register (causes the comparison of the register bits to be always true)." /> + </Register> + <Register start="+0x008" size="4" name="CTRL" access="Read/Write" description="Control register." reset_value="0xC" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RITINT" description="Interrupt flag"> + <Enum name="MASK" start="1" description="This bit is set to 1 by hardware whenever the counter value equals the masked compare value specified by the contents of RICOMPVAL and RIMASK registers. Writing a 1 to this bit will clear it to 0. Writing a 0 has no effect." /> + <Enum name="NO_MASK" start="0" description="The counter value does not equal the masked compare value." /> + </BitField> + <BitField start="1" size="1" name="RITENCLR" description="Timer enable clear"> + <Enum name="CLEAR_ON_O" start="1" description="The timer will be cleared to 0 whenever the counter value equals the masked compare value specified by the contents of COMPVAL/COMPVAL_H and MASK/MASK_H registers. This will occur on the same clock that sets the interrupt flag." /> + <Enum name="NOT_CLEAR_ON_0" start="0" description="The timer will not be cleared to 0." /> + </BitField> + <BitField start="2" size="1" name="RITENBR" description="Timer enable for debug"> + <Enum name="HALT_ON_DEBUG" start="1" description="The timer is halted when the processor is halted for debugging." /> + <Enum name="NO_EFFECT_ON_DEBUG" start="0" description="Debug has no effect on the timer operation." /> + </BitField> + <BitField start="3" size="1" name="RITEN" description="Timer enable."> + <Enum name="TIMER_ENABLED" start="1" description="Timer enabled. This can be overruled by a debug halt if enabled in bit 2." /> + <Enum name="TIMER_DISABLED_" start="0" description="Timer disabled." /> + </BitField> + <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x00C" size="4" name="COUNTER" access="Read/Write" description="Counter LSB register. 32 LSBs of the counter." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="RICOUNTER" description="32 LSBs of the up counter. Counts continuously unless RITEN bit in CTRL register is cleared or debug mode is entered (if enabled by the RITNEBR bit in RICTRL). Can be loaded to any value in software." /> + </Register> + <Register start="+0x010" size="4" name="COMPVAL_H" access="Read/Write" description="Compare value MSB register. Holds the 16 MSBs of the compare value." reset_value="0x0000FFFF" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="16" name="RICOMP" description="Compare value MSB register. Holds the 16 MSBs of the compare value which is compared to the counter." /> + <BitField start="16" size="16" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x014" size="4" name="MASK_H" access="Read/Write" description="Mask MSB register. This register holds the 16 MSBs of the mask value. A one written to any bit will force a compare on the corresponding bit of the counter and compare register." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="16" name="RIMASK" description="Mask register. This register holds the 16 MSBs of the mask value. A one written to any bit overrides the result of the comparison for the corresponding bit of the counter and compare register (causes the comparison of the register bits to be always true)." /> + <BitField start="16" size="16" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x018" size="4" name="COUNTER_H" access="Read/Write" description="Counter MSB register. 16 MSBs of the counter." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="16" name="RICOUNTER" description="16 LSBs of the up counter. Counts continuously unless RITEN bit in RICTRL register is cleared or debug mode is entered (if enabled by the RITNEBR bit in RICTRL). Can be loaded to any value in software." /> + <BitField start="16" size="16" name="RESERVED" description="Reserved." /> + </Register> + </RegisterGroup> + <RegisterGroup name="USB" start="0x40080000" description="USB2.0 device controller"> + <Register start="+0x000" size="4" name="DEVCMDSTAT" access="Read/Write" description="USB Device Command/Status register" reset_value="0x00000800" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="7" name="DEV_ADDR" description="USB device address. After bus reset, the address is reset to 0x00. If the enable bit is set, the device will respond on packets for function address DEV_ADDR. When receiving a SetAddress Control Request from the USB host, software must program the new address before completing the status phase of the SetAddress Control Request." /> + <BitField start="7" size="1" name="DEV_EN" description="USB device enable. If this bit is set, the HW will start responding on packets for function address DEV_ADDR." /> + <BitField start="8" size="1" name="SETUP" description="SETUP token received. If a SETUP token is received and acknowledged by the device, this bit is set. As long as this bit is set all received IN and OUT tokens will be NAKed by HW. SW must clear this bit by writing a one. If this bit is zero, HW will handle the tokens to the CTRL EP0 as indicated by the CTRL EP0 IN and OUT data information programmed by SW." /> + <BitField start="9" size="1" name="PLL_ON" description="Always PLL Clock on:"> + <Enum name="USB_NEEDCLK_FUNCTION" start="0" description="USB_NeedClk functional" /> + <Enum name="USB_NEEDCLK_ALWAYS_1" start="1" description="USB_NeedClk always 1. Clock will not be stopped in case of suspend." /> + </BitField> + <BitField start="10" size="1" name="RESERVED" description="Reserved." /> + <BitField start="11" size="1" name="LPM_SUP" description="LPM Supported:"> + <Enum name="LPM_NOT_SUPPORTED_" start="0" description="LPM not supported." /> + <Enum name="LPM_SUPPORTED_" start="1" description="LPM supported." /> + </BitField> + <BitField start="12" size="1" name="INTONNAK_AO" description="Interrupt on NAK for interrupt and bulk OUT EP"> + <Enum name="ACKNOW" start="0" description="Only acknowledged packets generate an interrupt" /> + <Enum name="ACKNOW_NAK" start="1" description="Both acknowledged and NAKed packets generate interrupts." /> + </BitField> + <BitField start="13" size="1" name="INTONNAK_AI" description="Interrupt on NAK for interrupt and bulk IN EP"> + <Enum name="ACKNOW" start="0" description="Only acknowledged packets generate an interrupt" /> + <Enum name="ACKNOW_NAK" start="1" description="Both acknowledged and NAKed packets generate interrupts." /> + </BitField> + <BitField start="14" size="1" name="INTONNAK_CO" description="Interrupt on NAK for control OUT EP"> + <Enum name="ACKNOW" start="0" description="Only acknowledged packets generate an interrupt" /> + <Enum name="ACKNOW_NAK" start="1" description="Both acknowledged and NAKed packets generate interrupts." /> + </BitField> + <BitField start="15" size="1" name="INTONNAK_CI" description="Interrupt on NAK for control IN EP"> + <Enum name="ACKNOW" start="0" description="Only acknowledged packets generate an interrupt" /> + <Enum name="ACKNOW_NAK" start="1" description="Both acknowledged and NAKed packets generate interrupts." /> + </BitField> + <BitField start="16" size="1" name="DCON" description="Device status - connect. The connect bit must be set by SW to indicate that the device must signal a connect. The pull-up resistor on USB_DP will be enabled when this bit is set and the VbusDebounced bit is one." /> + <BitField start="17" size="1" name="DSUS" description="Device status - suspend. The suspend bit indicates the current suspend state. It is set to 1 when the device hasn't seen any activity on its upstream port for more than 3 milliseconds. It is reset to 0 on any activity. When the device is suspended (Suspend bit DSUS = 1) and the software writes a 0 to it, the device will generate a remote wake-up. This will only happen when the device is connected (Connect bit = 1). When the device is not connected or not suspended, a writing a 0 has no effect. Writing a 1 never has an effect." /> + <BitField start="18" size="1" name="RESERVED" description="Reserved." /> + <BitField start="19" size="1" name="LPM_SUS" description="Device status - LPM Suspend. This bit represents the current LPM suspend state. It is set to 1 by HW when the device has acknowledged the LPM request from the USB host and the Token Retry Time of 10us has elapsed. When the device is in the LPM suspended state (LPM suspend bit = 1) and the software writes a zero to this bit, the device will generate a remote walk-up. Software can only write a zero to this bit when the LPM_REWP bit is set to 1. HW resets this bit when it receives a host initiated resume. HW only updates the LPM_SUS bit when the LPM_SUPP bit is equal to one." /> + <BitField start="20" size="1" name="LPM_REWP" description="LPM Remote Wake-up Enabled by USB host. HW sets this bit to one when the bRemoteWake bit in the LPM extended token is set to 1. HW will reset this bit to 0 when it receives the host initiated LPM resume, when a remote wake-up is sent by the device or when a USB bus reset is received. Software can use this bit to check if the remote wake-up feature is enabled by the host for the LPM transaction." /> + <BitField start="21" size="3" name="RESERVED" description="Reserved." /> + <BitField start="24" size="1" name="DCON_C" description="Device status - connect change. The Connect Change bit is set when the device's pull-up resistor is disconnected because VBus disappeared. The bit is reset by writing a one to it." /> + <BitField start="25" size="1" name="DSUS_C" description="Device status - suspend change. The suspend change bit is set to 1 when the suspend bit toggles. The suspend bit can toggle because: - The device goes in the suspended state - The device is disconnected - The device receives resume signaling on its upstream port. The bit is reset by writing a one to it." /> + <BitField start="26" size="1" name="DRES_C" description="Device status - reset change. This bit is set when the device received a bus reset. On a bus reset the device will automatically go to the default state (unconfigured and responding to address 0). The bit is reset by writing a one to it." /> + <BitField start="27" size="1" name="RESERVED" description="Reserved." /> + <BitField start="28" size="1" name="VBUSDEBOUNCED" description="This bit indicates if Vbus is detected or not. The bit raises immediately when Vbus becomes high. It drops to zero if Vbus is low for at least 3 ms. If this bit is high and the DCon bit is set, the HW will enable the pull-up resistor to signal a connect." /> + <BitField start="29" size="3" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x004" size="4" name="INFO" access="Read/Write" description="USB Info register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="11" name="FRAME_NR" description="Frame number. This contains the frame number of the last successfully received SOF. In case no SOF was received by the device at the beginning of a frame, the frame number returned is that of the last successfully received SOF. In case the SOF frame number contained a CRC error, the frame number returned will be the corrupted frame number as received by the device." /> + <BitField start="11" size="4" name="ERR_CODE" description="The error code which last occurred:"> + <Enum name="NO_ERROR" start="0x0" description="No error" /> + <Enum name="PID_ENCODING_ERROR" start="0x1" description="PID encoding error" /> + <Enum name="PID_UNKNOWN" start="0x2" description="PID unknown" /> + <Enum name="PACKET_UNEXPECTED" start="0x3" description="Packet unexpected" /> + <Enum name="TOKEN_CRC_ERROR" start="0x4" description="Token CRC error" /> + <Enum name="DATA_CRC_ERROR" start="0x5" description="Data CRC error" /> + <Enum name="TIME_OUT" start="0x6" description="Time out" /> + <Enum name="BABBLE" start="0x7" description="Babble" /> + <Enum name="TRUNCATED_EOP" start="0x8" description="Truncated EOP" /> + <Enum name="SENT_RECEIVED_NAK" start="0x9" description="Sent/Received NAK" /> + <Enum name="SENT_STALL" start="0xA" description="Sent Stall" /> + <Enum name="OVERRUN" start="0xB" description="Overrun" /> + <Enum name="SENT_EMPTY_PACKET" start="0xC" description="Sent empty packet" /> + <Enum name="BITSTUFF_ERROR" start="0xD" description="Bitstuff error" /> + <Enum name="SYNC_ERROR" start="0xE" description="Sync error" /> + <Enum name="WRONG_DATA_TOGGLE" start="0xF" description="Wrong data toggle" /> + </BitField> + <BitField start="15" size="1" name="RESERVED" description="Reserved." /> + <BitField start="16" size="16" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x008" size="4" name="EPLISTSTART" access="Read/Write" description="USB EP Command/Status List start address" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="RESERVED" description="Reserved" /> + <BitField start="8" size="24" name="EP_LIST" description="Start address of the USB EP Command/Status List." /> + </Register> + <Register start="+0x00C" size="4" name="DATABUFSTART" access="Read/Write" description="USB Data buffer start address" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="22" name="RESERVED" description="Reserved" /> + <BitField start="22" size="10" name="DA_BUF" description="Start address of the buffer pointer page where all endpoint data buffers are located." /> + </Register> + <Register start="+0x010" size="4" name="LPM" access="Read/Write" description="Link Power Management register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="4" name="HIRD_HW" description="Host Initiated Resume Duration - HW. This is the HIRD value from the last received LPM token" /> + <BitField start="4" size="4" name="HIRD_SW" description="Host Initiated Resume Duration - SW. This is the time duration required by the USB device system to come out of LPM initiated suspend after receiving the host initiated LPM resume." /> + <BitField start="8" size="1" name="DATA_PENDING" description="As long as this bit is set to one and LPM supported bit is set to one, HW will return a NYET handshake on every LPM token it receives. If LPM supported bit is set to one and this bit is zero, HW will return an ACK handshake on every LPM token it receives. If SW has still data pending and LPM is supported, it must set this bit to 1." /> + <BitField start="9" size="23" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x014" size="4" name="EPSKIP" access="Read/Write" description="USB Endpoint skip" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="30" name="SKIP" description="Endpoint skip: Writing 1 to one of these bits, will indicate to HW that it must deactivate the buffer assigned to this endpoint and return control back to software. When HW has deactivated the endpoint, it will clear this bit, but it will not modify the EPINUSE bit. An interrupt will be generated when the Active bit goes from 1 to 0. Note: In case of double-buffering, HW will only clear the Active bit of the buffer indicated by the EPINUSE bit." /> + <BitField start="30" size="2" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x018" size="4" name="EPINUSE" access="Read/Write" description="USB Endpoint Buffer in use" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="RESERVED" description="Reserved. Fixed to zero because the control endpoint zero is fixed to single-buffering for each physical endpoint." /> + <BitField start="2" size="8" name="BUF" description="Buffer in use: This register has one bit per physical endpoint. 0: HW is accessing buffer 0. 1: HW is accessing buffer 1." /> + <BitField start="10" size="22" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x01C" size="4" name="EPBUFCFG" access="Read/Write" description="USB Endpoint Buffer Configuration register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="RESERVED" description="Reserved. Fixed to zero because the control endpoint zero is fixed to single-buffering for each physical endpoint." /> + <BitField start="2" size="8" name="BUF_SB" description="Buffer usage: This register has one bit per physical endpoint. 0: Single-buffer. 1: Double-buffer. If the bit is set to single-buffer (0), it will not toggle the corresponding EPINUSE bit when it clears the active bit. If the bit is set to double-buffer (1), HW will toggle the EPINUSE bit when it clears the Active bit for the buffer." /> + <BitField start="10" size="22" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x020" size="4" name="INTSTAT" access="Read/Write" description="USB interrupt status register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="EP0OUT" description="Interrupt status register bit for the Control EP0 OUT direction. This bit will be set if NBytes transitions to zero or the skip bit is set by software or a SETUP packet is successfully received for the control EP0. If the IntOnNAK_CO is set, this bit will also be set when a NAK is transmitted for the Control EP0 OUT direction. Software can clear this bit by writing a one to it." /> + <BitField start="1" size="1" name="EP0IN" description="Interrupt status register bit for the Control EP0 IN direction. This bit will be set if NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_CI is set, this bit will also be set when a NAK is transmitted for the Control EP0 IN direction. Software can clear this bit by writing a one to it." /> + <BitField start="2" size="1" name="EP1OUT" description="Interrupt status register bit for the EP1 OUT direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AO is set, this bit will also be set when a NAK is transmitted for the EP1 OUT direction. Software can clear this bit by writing a one to it." /> + <BitField start="3" size="1" name="EP1IN" description="Interrupt status register bit for the EP1 IN direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AI is set, this bit will also be set when a NAK is transmitted for the EP1 IN direction. Software can clear this bit by writing a one to it." /> + <BitField start="4" size="1" name="EP2OUT" description="Interrupt status register bit for the EP2 OUT direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AO is set, this bit will also be set when a NAK is transmitted for the EP2 OUT direction. Software can clear this bit by writing a one to it." /> + <BitField start="5" size="1" name="EP2IN" description="Interrupt status register bit for the EP2 IN direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AI is set, this bit will also be set when a NAK is transmitted for the EP2 IN direction. Software can clear this bit by writing a one to it." /> + <BitField start="6" size="1" name="EP3OUT" description="Interrupt status register bit for the EP3 OUT direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AO is set, this bit will also be set when a NAK is transmitted for the EP3 OUT direction. Software can clear this bit by writing a one to it." /> + <BitField start="7" size="1" name="EP3IN" description="Interrupt status register bit for the EP3 IN direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AI is set, this bit will also be set when a NAK is transmitted for the EP3 IN direction. Software can clear this bit by writing a one to it." /> + <BitField start="8" size="1" name="EP4OUT" description="Interrupt status register bit for the EP4 OUT direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AO is set, this bit will also be set when a NAK is transmitted for the EP4 OUT direction. Software can clear this bit by writing a one to it." /> + <BitField start="9" size="1" name="EP4IN" description="Interrupt status register bit for the EP4 IN direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AI is set, this bit will also be set when a NAK is transmitted for the EP4 IN direction. Software can clear this bit by writing a one to it." /> + <BitField start="10" size="20" name="RESERVED" description="Reserved" /> + <BitField start="30" size="1" name="FRAME_INT" description="Frame interrupt. This bit is set to one every millisecond when the VbusDebounced bit and the DCON bit are set. This bit can be used by software when handling isochronous endpoints. Software can clear this bit by writing a one to it." /> + <BitField start="31" size="1" name="DEV_INT" description="Device status interrupt. This bit is set by HW when one of the bits in the Device Status Change register are set. Software can clear this bit by writing a one to it." /> + </Register> + <Register start="+0x024" size="4" name="INTEN" access="Read/Write" description="USB interrupt enable register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="10" name="EP_INT_EN" description="If this bit is set and the corresponding USB interrupt status bit is set, a HW interrupt is generated on the interrupt line indicated by the corresponding USB interrupt routing bit." /> + <BitField start="10" size="20" name="RESERVED" description="Reserved" /> + <BitField start="30" size="1" name="FRAME_INT_EN" description="If this bit is set and the corresponding USB interrupt status bit is set, a HW interrupt is generated on the interrupt line indicated by the corresponding USB interrupt routing bit." /> + <BitField start="31" size="1" name="DEV_INT_EN" description="If this bit is set and the corresponding USB interrupt status bit is set, a HW interrupt is generated on the interrupt line indicated by the corresponding USB interrupt routing bit." /> + </Register> + <Register start="+0x028" size="4" name="INTSETSTAT" access="Read/Write" description="USB set interrupt status register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="10" name="EP_SET_INT" description="If software writes a one to one of these bits, the corresponding USB interrupt status bit is set. When this register is read, the same value as the USB interrupt status register is returned." /> + <BitField start="10" size="20" name="RESERVED" description="Reserved" /> + <BitField start="30" size="1" name="FRAME_SET_INT" description="If software writes a one to one of these bits, the corresponding USB interrupt status bit is set. When this register is read, the same value as the USB interrupt status register is returned." /> + <BitField start="31" size="1" name="DEV_SET_INT" description="If software writes a one to one of these bits, the corresponding USB interrupt status bit is set. When this register is read, the same value as the USB interrupt status register is returned." /> + </Register> + <Register start="+0x02C" size="4" name="INTROUTING" access="Read/Write" description="USB interrupt routing register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="10" name="ROUTE_INT9_0" description="This bit can control on which hardware interrupt line the interrupt will be generated: 0: IRQ interrupt line is selected for this interrupt bit 1: FIQ interrupt line is selected for this interrupt bit" /> + <BitField start="10" size="20" name="RESERVED" description="Reserved" /> + <BitField start="30" size="1" name="ROUTE_INT30" description="This bit can control on which hardware interrupt line the interrupt will be generated: 0: IRQ interrupt line is selected for this interrupt bit 1: FIQ interrupt line is selected for this interrupt bit" /> + <BitField start="31" size="1" name="ROUTE_INT31" description="This bit can control on which hardware interrupt line the interrupt will be generated: 0: IRQ interrupt line is selected for this interrupt bit 1: FIQ interrupt line is selected for this interrupt bit" /> + </Register> + <Register start="+0x034" size="4" name="EPTOGGLE" access="ReadOnly" description="USB Endpoint toggle register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="10" name="TOGGLE" description="Endpoint data toggle: This field indicates the current value of the data toggle for the corresponding endpoint." /> + <BitField start="10" size="22" name="RESERVED" description="Reserved" /> + </Register> + </RegisterGroup> + <RegisterGroup name="GPIO_PORT" start="0x50000000" description="GPIO port "> + <Register start="+0x0000+0" size="1" name="B[0]" access="Read/Write" description="Byte pin registers port 0/1; pins PIO0/1_0 to PIO0/1_31" reset_value="0" reset_mask="0xFF"> + <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin P0/1_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." /> + </Register> + <Register start="+0x0000+1" size="1" name="B[1]" access="Read/Write" description="Byte pin registers port 0/1; pins PIO0/1_0 to PIO0/1_31" reset_value="0" reset_mask="0xFF"> + <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin P0/1_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." /> + </Register> + <Register start="+0x0000+2" size="1" name="B[2]" access="Read/Write" description="Byte pin registers port 0/1; pins PIO0/1_0 to PIO0/1_31" reset_value="0" reset_mask="0xFF"> + <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin P0/1_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." /> + </Register> + <Register start="+0x0000+3" size="1" name="B[3]" access="Read/Write" description="Byte pin registers port 0/1; pins PIO0/1_0 to PIO0/1_31" reset_value="0" reset_mask="0xFF"> + <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin P0/1_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." /> + </Register> + <Register start="+0x0000+4" size="1" name="B[4]" access="Read/Write" description="Byte pin registers port 0/1; pins PIO0/1_0 to PIO0/1_31" reset_value="0" reset_mask="0xFF"> + <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin P0/1_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." /> + </Register> + <Register start="+0x0000+5" size="1" name="B[5]" access="Read/Write" description="Byte pin registers port 0/1; pins PIO0/1_0 to PIO0/1_31" reset_value="0" reset_mask="0xFF"> + <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin P0/1_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." /> + </Register> + <Register start="+0x0000+6" size="1" name="B[6]" access="Read/Write" description="Byte pin registers port 0/1; pins PIO0/1_0 to PIO0/1_31" reset_value="0" reset_mask="0xFF"> + <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin P0/1_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." /> + </Register> + <Register start="+0x0000+7" size="1" name="B[7]" access="Read/Write" description="Byte pin registers port 0/1; pins PIO0/1_0 to PIO0/1_31" reset_value="0" reset_mask="0xFF"> + <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin P0/1_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." /> + </Register> + <Register start="+0x0000+8" size="1" name="B[8]" access="Read/Write" description="Byte pin registers port 0/1; pins PIO0/1_0 to PIO0/1_31" reset_value="0" reset_mask="0xFF"> + <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin P0/1_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." /> + </Register> + <Register start="+0x0000+9" size="1" name="B[9]" access="Read/Write" description="Byte pin registers port 0/1; pins PIO0/1_0 to PIO0/1_31" reset_value="0" reset_mask="0xFF"> + <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin P0/1_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." /> + </Register> + <Register start="+0x0000+10" size="1" name="B[10]" access="Read/Write" description="Byte pin registers port 0/1; pins PIO0/1_0 to PIO0/1_31" reset_value="0" reset_mask="0xFF"> + <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin P0/1_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." /> + </Register> + <Register start="+0x0000+11" size="1" name="B[11]" access="Read/Write" description="Byte pin registers port 0/1; pins PIO0/1_0 to PIO0/1_31" reset_value="0" reset_mask="0xFF"> + <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin P0/1_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." /> + </Register> + <Register start="+0x0000+12" size="1" name="B[12]" access="Read/Write" description="Byte pin registers port 0/1; pins PIO0/1_0 to PIO0/1_31" reset_value="0" reset_mask="0xFF"> + <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin P0/1_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." /> + </Register> + <Register start="+0x0000+13" size="1" name="B[13]" access="Read/Write" description="Byte pin registers port 0/1; pins PIO0/1_0 to PIO0/1_31" reset_value="0" reset_mask="0xFF"> + <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin P0/1_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." /> + </Register> + <Register start="+0x0000+14" size="1" name="B[14]" access="Read/Write" description="Byte pin registers port 0/1; pins PIO0/1_0 to PIO0/1_31" reset_value="0" reset_mask="0xFF"> + <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin P0/1_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." /> + </Register> + <Register start="+0x0000+15" size="1" name="B[15]" access="Read/Write" description="Byte pin registers port 0/1; pins PIO0/1_0 to PIO0/1_31" reset_value="0" reset_mask="0xFF"> + <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin P0/1_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." /> + </Register> + <Register start="+0x0000+16" size="1" name="B[16]" access="Read/Write" description="Byte pin registers port 0/1; pins PIO0/1_0 to PIO0/1_31" reset_value="0" reset_mask="0xFF"> + <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin P0/1_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." /> + </Register> + <Register start="+0x0000+17" size="1" name="B[17]" access="Read/Write" description="Byte pin registers port 0/1; pins PIO0/1_0 to PIO0/1_31" reset_value="0" reset_mask="0xFF"> + <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin P0/1_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." /> + </Register> + <Register start="+0x0000+18" size="1" name="B[18]" access="Read/Write" description="Byte pin registers port 0/1; pins PIO0/1_0 to PIO0/1_31" reset_value="0" reset_mask="0xFF"> + <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin P0/1_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." /> + </Register> + <Register start="+0x0000+19" size="1" name="B[19]" access="Read/Write" description="Byte pin registers port 0/1; pins PIO0/1_0 to PIO0/1_31" reset_value="0" reset_mask="0xFF"> + <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin P0/1_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." /> + </Register> + <Register start="+0x0000+20" size="1" name="B[20]" access="Read/Write" description="Byte pin registers port 0/1; pins PIO0/1_0 to PIO0/1_31" reset_value="0" reset_mask="0xFF"> + <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin P0/1_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." /> + </Register> + <Register start="+0x0000+21" size="1" name="B[21]" access="Read/Write" description="Byte pin registers port 0/1; pins PIO0/1_0 to PIO0/1_31" reset_value="0" reset_mask="0xFF"> + <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin P0/1_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." /> + </Register> + <Register start="+0x0000+22" size="1" name="B[22]" access="Read/Write" description="Byte pin registers port 0/1; pins PIO0/1_0 to PIO0/1_31" reset_value="0" reset_mask="0xFF"> + <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin P0/1_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." /> + </Register> + <Register start="+0x0000+23" size="1" name="B[23]" access="Read/Write" description="Byte pin registers port 0/1; pins PIO0/1_0 to PIO0/1_31" reset_value="0" reset_mask="0xFF"> + <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin P0/1_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." /> + </Register> + <Register start="+0x0000+24" size="1" name="B[24]" access="Read/Write" description="Byte pin registers port 0/1; pins PIO0/1_0 to PIO0/1_31" reset_value="0" reset_mask="0xFF"> + <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin P0/1_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." /> + </Register> + <Register start="+0x0000+25" size="1" name="B[25]" access="Read/Write" description="Byte pin registers port 0/1; pins PIO0/1_0 to PIO0/1_31" reset_value="0" reset_mask="0xFF"> + <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin P0/1_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." /> + </Register> + <Register start="+0x0000+26" size="1" name="B[26]" access="Read/Write" description="Byte pin registers port 0/1; pins PIO0/1_0 to PIO0/1_31" reset_value="0" reset_mask="0xFF"> + <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin P0/1_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." /> + </Register> + <Register start="+0x0000+27" size="1" name="B[27]" access="Read/Write" description="Byte pin registers port 0/1; pins PIO0/1_0 to PIO0/1_31" reset_value="0" reset_mask="0xFF"> + <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin P0/1_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." /> + </Register> + <Register start="+0x0000+28" size="1" name="B[28]" access="Read/Write" description="Byte pin registers port 0/1; pins PIO0/1_0 to PIO0/1_31" reset_value="0" reset_mask="0xFF"> + <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin P0/1_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." /> + </Register> + <Register start="+0x0000+29" size="1" name="B[29]" access="Read/Write" description="Byte pin registers port 0/1; pins PIO0/1_0 to PIO0/1_31" reset_value="0" reset_mask="0xFF"> + <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin P0/1_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." /> + </Register> + <Register start="+0x0000+30" size="1" name="B[30]" access="Read/Write" description="Byte pin registers port 0/1; pins PIO0/1_0 to PIO0/1_31" reset_value="0" reset_mask="0xFF"> + <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin P0/1_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." /> + </Register> + <Register start="+0x0000+31" size="1" name="B[31]" access="Read/Write" description="Byte pin registers port 0/1; pins PIO0/1_0 to PIO0/1_31" reset_value="0" reset_mask="0xFF"> + <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin P0/1_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." /> + </Register> + <Register start="+0x0000+32" size="1" name="B[32]" access="Read/Write" description="Byte pin registers port 0/1; pins PIO0/1_0 to PIO0/1_31" reset_value="0" reset_mask="0xFF"> + <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin P0/1_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." /> + </Register> + <Register start="+0x0000+33" size="1" name="B[33]" access="Read/Write" description="Byte pin registers port 0/1; pins PIO0/1_0 to PIO0/1_31" reset_value="0" reset_mask="0xFF"> + <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin P0/1_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." /> + </Register> + <Register start="+0x0000+34" size="1" name="B[34]" access="Read/Write" description="Byte pin registers port 0/1; pins PIO0/1_0 to PIO0/1_31" reset_value="0" reset_mask="0xFF"> + <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin P0/1_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." /> + </Register> + <Register start="+0x0000+35" size="1" name="B[35]" access="Read/Write" description="Byte pin registers port 0/1; pins PIO0/1_0 to PIO0/1_31" reset_value="0" reset_mask="0xFF"> + <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin P0/1_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." /> + </Register> + <Register start="+0x0000+36" size="1" name="B[36]" access="Read/Write" description="Byte pin registers port 0/1; pins PIO0/1_0 to PIO0/1_31" reset_value="0" reset_mask="0xFF"> + <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin P0/1_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." /> + </Register> + <Register start="+0x0000+37" size="1" name="B[37]" access="Read/Write" description="Byte pin registers port 0/1; pins PIO0/1_0 to PIO0/1_31" reset_value="0" reset_mask="0xFF"> + <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin P0/1_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." /> + </Register> + <Register start="+0x0000+38" size="1" name="B[38]" access="Read/Write" description="Byte pin registers port 0/1; pins PIO0/1_0 to PIO0/1_31" reset_value="0" reset_mask="0xFF"> + <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin P0/1_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." /> + </Register> + <Register start="+0x0000+39" size="1" name="B[39]" access="Read/Write" description="Byte pin registers port 0/1; pins PIO0/1_0 to PIO0/1_31" reset_value="0" reset_mask="0xFF"> + <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin P0/1_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." /> + </Register> + <Register start="+0x0000+40" size="1" name="B[40]" access="Read/Write" description="Byte pin registers port 0/1; pins PIO0/1_0 to PIO0/1_31" reset_value="0" reset_mask="0xFF"> + <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin P0/1_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." /> + </Register> + <Register start="+0x0000+41" size="1" name="B[41]" access="Read/Write" description="Byte pin registers port 0/1; pins PIO0/1_0 to PIO0/1_31" reset_value="0" reset_mask="0xFF"> + <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin P0/1_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." /> + </Register> + <Register start="+0x0000+42" size="1" name="B[42]" access="Read/Write" description="Byte pin registers port 0/1; pins PIO0/1_0 to PIO0/1_31" reset_value="0" reset_mask="0xFF"> + <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin P0/1_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." /> + </Register> + <Register start="+0x0000+43" size="1" name="B[43]" access="Read/Write" description="Byte pin registers port 0/1; pins PIO0/1_0 to PIO0/1_31" reset_value="0" reset_mask="0xFF"> + <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin P0/1_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." /> + </Register> + <Register start="+0x0000+44" size="1" name="B[44]" access="Read/Write" description="Byte pin registers port 0/1; pins PIO0/1_0 to PIO0/1_31" reset_value="0" reset_mask="0xFF"> + <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin P0/1_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." /> + </Register> + <Register start="+0x0000+45" size="1" name="B[45]" access="Read/Write" description="Byte pin registers port 0/1; pins PIO0/1_0 to PIO0/1_31" reset_value="0" reset_mask="0xFF"> + <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin P0/1_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." /> + </Register> + <Register start="+0x0000+46" size="1" name="B[46]" access="Read/Write" description="Byte pin registers port 0/1; pins PIO0/1_0 to PIO0/1_31" reset_value="0" reset_mask="0xFF"> + <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin P0/1_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." /> + </Register> + <Register start="+0x0000+47" size="1" name="B[47]" access="Read/Write" description="Byte pin registers port 0/1; pins PIO0/1_0 to PIO0/1_31" reset_value="0" reset_mask="0xFF"> + <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin P0/1_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." /> + </Register> + <Register start="+0x0000+48" size="1" name="B[48]" access="Read/Write" description="Byte pin registers port 0/1; pins PIO0/1_0 to PIO0/1_31" reset_value="0" reset_mask="0xFF"> + <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin P0/1_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." /> + </Register> + <Register start="+0x0000+49" size="1" name="B[49]" access="Read/Write" description="Byte pin registers port 0/1; pins PIO0/1_0 to PIO0/1_31" reset_value="0" reset_mask="0xFF"> + <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin P0/1_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." /> + </Register> + <Register start="+0x0000+50" size="1" name="B[50]" access="Read/Write" description="Byte pin registers port 0/1; pins PIO0/1_0 to PIO0/1_31" reset_value="0" reset_mask="0xFF"> + <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin P0/1_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." /> + </Register> + <Register start="+0x0000+51" size="1" name="B[51]" access="Read/Write" description="Byte pin registers port 0/1; pins PIO0/1_0 to PIO0/1_31" reset_value="0" reset_mask="0xFF"> + <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin P0/1_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." /> + </Register> + <Register start="+0x0000+52" size="1" name="B[52]" access="Read/Write" description="Byte pin registers port 0/1; pins PIO0/1_0 to PIO0/1_31" reset_value="0" reset_mask="0xFF"> + <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin P0/1_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." /> + </Register> + <Register start="+0x0000+53" size="1" name="B[53]" access="Read/Write" description="Byte pin registers port 0/1; pins PIO0/1_0 to PIO0/1_31" reset_value="0" reset_mask="0xFF"> + <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin P0/1_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." /> + </Register> + <Register start="+0x0000+54" size="1" name="B[54]" access="Read/Write" description="Byte pin registers port 0/1; pins PIO0/1_0 to PIO0/1_31" reset_value="0" reset_mask="0xFF"> + <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin P0/1_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." /> + </Register> + <Register start="+0x0000+55" size="1" name="B[55]" access="Read/Write" description="Byte pin registers port 0/1; pins PIO0/1_0 to PIO0/1_31" reset_value="0" reset_mask="0xFF"> + <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin P0/1_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." /> + </Register> + <Register start="+0x0000+56" size="1" name="B[56]" access="Read/Write" description="Byte pin registers port 0/1; pins PIO0/1_0 to PIO0/1_31" reset_value="0" reset_mask="0xFF"> + <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin P0/1_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." /> + </Register> + <Register start="+0x0000+57" size="1" name="B[57]" access="Read/Write" description="Byte pin registers port 0/1; pins PIO0/1_0 to PIO0/1_31" reset_value="0" reset_mask="0xFF"> + <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin P0/1_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." /> + </Register> + <Register start="+0x0000+58" size="1" name="B[58]" access="Read/Write" description="Byte pin registers port 0/1; pins PIO0/1_0 to PIO0/1_31" reset_value="0" reset_mask="0xFF"> + <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin P0/1_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." /> + </Register> + <Register start="+0x0000+59" size="1" name="B[59]" access="Read/Write" description="Byte pin registers port 0/1; pins PIO0/1_0 to PIO0/1_31" reset_value="0" reset_mask="0xFF"> + <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin P0/1_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." /> + </Register> + <Register start="+0x0000+60" size="1" name="B[60]" access="Read/Write" description="Byte pin registers port 0/1; pins PIO0/1_0 to PIO0/1_31" reset_value="0" reset_mask="0xFF"> + <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin P0/1_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." /> + </Register> + <Register start="+0x0000+61" size="1" name="B[61]" access="Read/Write" description="Byte pin registers port 0/1; pins PIO0/1_0 to PIO0/1_31" reset_value="0" reset_mask="0xFF"> + <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin P0/1_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." /> + </Register> + <Register start="+0x0000+62" size="1" name="B[62]" access="Read/Write" description="Byte pin registers port 0/1; pins PIO0/1_0 to PIO0/1_31" reset_value="0" reset_mask="0xFF"> + <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin P0/1_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." /> + </Register> + <Register start="+0x0000+63" size="1" name="B[63]" access="Read/Write" description="Byte pin registers port 0/1; pins PIO0/1_0 to PIO0/1_31" reset_value="0" reset_mask="0xFF"> + <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin P0/1_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." /> + </Register> + <Register start="+0x1000+0" size="4" name="W[0]" access="Read/Write" description="Word pin registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." /> + </Register> + <Register start="+0x1000+4" size="4" name="W[1]" access="Read/Write" description="Word pin registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." /> + </Register> + <Register start="+0x1000+8" size="4" name="W[2]" access="Read/Write" description="Word pin registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." /> + </Register> + <Register start="+0x1000+12" size="4" name="W[3]" access="Read/Write" description="Word pin registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." /> + </Register> + <Register start="+0x1000+16" size="4" name="W[4]" access="Read/Write" description="Word pin registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." /> + </Register> + <Register start="+0x1000+20" size="4" name="W[5]" access="Read/Write" description="Word pin registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." /> + </Register> + <Register start="+0x1000+24" size="4" name="W[6]" access="Read/Write" description="Word pin registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." /> + </Register> + <Register start="+0x1000+28" size="4" name="W[7]" access="Read/Write" description="Word pin registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." /> + </Register> + <Register start="+0x1000+32" size="4" name="W[8]" access="Read/Write" description="Word pin registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." /> + </Register> + <Register start="+0x1000+36" size="4" name="W[9]" access="Read/Write" description="Word pin registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." /> + </Register> + <Register start="+0x1000+40" size="4" name="W[10]" access="Read/Write" description="Word pin registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." /> + </Register> + <Register start="+0x1000+44" size="4" name="W[11]" access="Read/Write" description="Word pin registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." /> + </Register> + <Register start="+0x1000+48" size="4" name="W[12]" access="Read/Write" description="Word pin registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." /> + </Register> + <Register start="+0x1000+52" size="4" name="W[13]" access="Read/Write" description="Word pin registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." /> + </Register> + <Register start="+0x1000+56" size="4" name="W[14]" access="Read/Write" description="Word pin registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." /> + </Register> + <Register start="+0x1000+60" size="4" name="W[15]" access="Read/Write" description="Word pin registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." /> + </Register> + <Register start="+0x1000+64" size="4" name="W[16]" access="Read/Write" description="Word pin registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." /> + </Register> + <Register start="+0x1000+68" size="4" name="W[17]" access="Read/Write" description="Word pin registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." /> + </Register> + <Register start="+0x1000+72" size="4" name="W[18]" access="Read/Write" description="Word pin registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." /> + </Register> + <Register start="+0x1000+76" size="4" name="W[19]" access="Read/Write" description="Word pin registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." /> + </Register> + <Register start="+0x1000+80" size="4" name="W[20]" access="Read/Write" description="Word pin registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." /> + </Register> + <Register start="+0x1000+84" size="4" name="W[21]" access="Read/Write" description="Word pin registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." /> + </Register> + <Register start="+0x1000+88" size="4" name="W[22]" access="Read/Write" description="Word pin registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." /> + </Register> + <Register start="+0x1000+92" size="4" name="W[23]" access="Read/Write" description="Word pin registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." /> + </Register> + <Register start="+0x1000+96" size="4" name="W[24]" access="Read/Write" description="Word pin registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." /> + </Register> + <Register start="+0x1000+100" size="4" name="W[25]" access="Read/Write" description="Word pin registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." /> + </Register> + <Register start="+0x1000+104" size="4" name="W[26]" access="Read/Write" description="Word pin registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." /> + </Register> + <Register start="+0x1000+108" size="4" name="W[27]" access="Read/Write" description="Word pin registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." /> + </Register> + <Register start="+0x1000+112" size="4" name="W[28]" access="Read/Write" description="Word pin registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." /> + </Register> + <Register start="+0x1000+116" size="4" name="W[29]" access="Read/Write" description="Word pin registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." /> + </Register> + <Register start="+0x1000+120" size="4" name="W[30]" access="Read/Write" description="Word pin registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." /> + </Register> + <Register start="+0x1000+124" size="4" name="W[31]" access="Read/Write" description="Word pin registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." /> + </Register> + <Register start="+0x1000+128" size="4" name="W[32]" access="Read/Write" description="Word pin registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." /> + </Register> + <Register start="+0x1000+132" size="4" name="W[33]" access="Read/Write" description="Word pin registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." /> + </Register> + <Register start="+0x1000+136" size="4" name="W[34]" access="Read/Write" description="Word pin registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." /> + </Register> + <Register start="+0x1000+140" size="4" name="W[35]" access="Read/Write" description="Word pin registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." /> + </Register> + <Register start="+0x1000+144" size="4" name="W[36]" access="Read/Write" description="Word pin registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." /> + </Register> + <Register start="+0x1000+148" size="4" name="W[37]" access="Read/Write" description="Word pin registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." /> + </Register> + <Register start="+0x1000+152" size="4" name="W[38]" access="Read/Write" description="Word pin registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." /> + </Register> + <Register start="+0x1000+156" size="4" name="W[39]" access="Read/Write" description="Word pin registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." /> + </Register> + <Register start="+0x1000+160" size="4" name="W[40]" access="Read/Write" description="Word pin registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." /> + </Register> + <Register start="+0x1000+164" size="4" name="W[41]" access="Read/Write" description="Word pin registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." /> + </Register> + <Register start="+0x1000+168" size="4" name="W[42]" access="Read/Write" description="Word pin registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." /> + </Register> + <Register start="+0x1000+172" size="4" name="W[43]" access="Read/Write" description="Word pin registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." /> + </Register> + <Register start="+0x1000+176" size="4" name="W[44]" access="Read/Write" description="Word pin registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." /> + </Register> + <Register start="+0x1000+180" size="4" name="W[45]" access="Read/Write" description="Word pin registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." /> + </Register> + <Register start="+0x1000+184" size="4" name="W[46]" access="Read/Write" description="Word pin registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." /> + </Register> + <Register start="+0x1000+188" size="4" name="W[47]" access="Read/Write" description="Word pin registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." /> + </Register> + <Register start="+0x1000+192" size="4" name="W[48]" access="Read/Write" description="Word pin registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." /> + </Register> + <Register start="+0x1000+196" size="4" name="W[49]" access="Read/Write" description="Word pin registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." /> + </Register> + <Register start="+0x1000+200" size="4" name="W[50]" access="Read/Write" description="Word pin registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." /> + </Register> + <Register start="+0x1000+204" size="4" name="W[51]" access="Read/Write" description="Word pin registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." /> + </Register> + <Register start="+0x1000+208" size="4" name="W[52]" access="Read/Write" description="Word pin registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." /> + </Register> + <Register start="+0x1000+212" size="4" name="W[53]" access="Read/Write" description="Word pin registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." /> + </Register> + <Register start="+0x1000+216" size="4" name="W[54]" access="Read/Write" description="Word pin registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." /> + </Register> + <Register start="+0x1000+220" size="4" name="W[55]" access="Read/Write" description="Word pin registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." /> + </Register> + <Register start="+0x1000+224" size="4" name="W[56]" access="Read/Write" description="Word pin registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." /> + </Register> + <Register start="+0x1000+228" size="4" name="W[57]" access="Read/Write" description="Word pin registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." /> + </Register> + <Register start="+0x1000+232" size="4" name="W[58]" access="Read/Write" description="Word pin registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." /> + </Register> + <Register start="+0x1000+236" size="4" name="W[59]" access="Read/Write" description="Word pin registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." /> + </Register> + <Register start="+0x1000+240" size="4" name="W[60]" access="Read/Write" description="Word pin registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." /> + </Register> + <Register start="+0x1000+244" size="4" name="W[61]" access="Read/Write" description="Word pin registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." /> + </Register> + <Register start="+0x1000+248" size="4" name="W[62]" access="Read/Write" description="Word pin registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." /> + </Register> + <Register start="+0x1000+252" size="4" name="W[63]" access="Read/Write" description="Word pin registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." /> + </Register> + <Register start="+0x2000+0" size="4" name="DIR0" access="Read/Write" description="Direction registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="DIRP0" description="Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output." /> + <BitField start="1" size="1" name="DIRP1" description="Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output." /> + <BitField start="2" size="1" name="DIRP2" description="Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output." /> + <BitField start="3" size="1" name="DIRP3" description="Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output." /> + <BitField start="4" size="1" name="DIRP4" description="Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output." /> + <BitField start="5" size="1" name="DIRP5" description="Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output." /> + <BitField start="6" size="1" name="DIRP6" description="Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output." /> + <BitField start="7" size="1" name="DIRP7" description="Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output." /> + <BitField start="8" size="1" name="DIRP8" description="Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output." /> + <BitField start="9" size="1" name="DIRP9" description="Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output." /> + <BitField start="10" size="1" name="DIRP10" description="Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output." /> + <BitField start="11" size="1" name="DIRP11" description="Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output." /> + <BitField start="12" size="1" name="DIRP12" description="Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output." /> + <BitField start="13" size="1" name="DIRP13" description="Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output." /> + <BitField start="14" size="1" name="DIRP14" description="Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output." /> + <BitField start="15" size="1" name="DIRP15" description="Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output." /> + <BitField start="16" size="1" name="DIRP16" description="Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output." /> + <BitField start="17" size="1" name="DIRP17" description="Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output." /> + <BitField start="18" size="1" name="DIRP18" description="Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output." /> + <BitField start="19" size="1" name="DIRP19" description="Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output." /> + <BitField start="20" size="1" name="DIRP20" description="Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output." /> + <BitField start="21" size="1" name="DIRP21" description="Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output." /> + <BitField start="22" size="1" name="DIRP22" description="Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output." /> + <BitField start="23" size="1" name="DIRP23" description="Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output." /> + <BitField start="24" size="1" name="DIRP24" description="Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output." /> + <BitField start="25" size="1" name="DIRP25" description="Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output." /> + <BitField start="26" size="1" name="DIRP26" description="Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output." /> + <BitField start="27" size="1" name="DIRP27" description="Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output." /> + <BitField start="28" size="1" name="DIRP28" description="Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output." /> + <BitField start="29" size="1" name="DIRP29" description="Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output." /> + <BitField start="30" size="1" name="DIRP30" description="Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output." /> + <BitField start="31" size="1" name="DIRP31" description="Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output." /> + </Register> + <Register start="+0x2000+4" size="4" name="DIR1" access="Read/Write" description="Direction registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="DIRP0" description="Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output." /> + <BitField start="1" size="1" name="DIRP1" description="Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output." /> + <BitField start="2" size="1" name="DIRP2" description="Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output." /> + <BitField start="3" size="1" name="DIRP3" description="Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output." /> + <BitField start="4" size="1" name="DIRP4" description="Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output." /> + <BitField start="5" size="1" name="DIRP5" description="Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output." /> + <BitField start="6" size="1" name="DIRP6" description="Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output." /> + <BitField start="7" size="1" name="DIRP7" description="Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output." /> + <BitField start="8" size="1" name="DIRP8" description="Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output." /> + <BitField start="9" size="1" name="DIRP9" description="Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output." /> + <BitField start="10" size="1" name="DIRP10" description="Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output." /> + <BitField start="11" size="1" name="DIRP11" description="Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output." /> + <BitField start="12" size="1" name="DIRP12" description="Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output." /> + <BitField start="13" size="1" name="DIRP13" description="Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output." /> + <BitField start="14" size="1" name="DIRP14" description="Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output." /> + <BitField start="15" size="1" name="DIRP15" description="Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output." /> + <BitField start="16" size="1" name="DIRP16" description="Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output." /> + <BitField start="17" size="1" name="DIRP17" description="Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output." /> + <BitField start="18" size="1" name="DIRP18" description="Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output." /> + <BitField start="19" size="1" name="DIRP19" description="Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output." /> + <BitField start="20" size="1" name="DIRP20" description="Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output." /> + <BitField start="21" size="1" name="DIRP21" description="Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output." /> + <BitField start="22" size="1" name="DIRP22" description="Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output." /> + <BitField start="23" size="1" name="DIRP23" description="Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output." /> + <BitField start="24" size="1" name="DIRP24" description="Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output." /> + <BitField start="25" size="1" name="DIRP25" description="Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output." /> + <BitField start="26" size="1" name="DIRP26" description="Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output." /> + <BitField start="27" size="1" name="DIRP27" description="Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output." /> + <BitField start="28" size="1" name="DIRP28" description="Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output." /> + <BitField start="29" size="1" name="DIRP29" description="Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output." /> + <BitField start="30" size="1" name="DIRP30" description="Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output." /> + <BitField start="31" size="1" name="DIRP31" description="Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output." /> + </Register> + <Register start="+0x2080+0" size="4" name="MASK0" access="Read/Write" description="Mask register port 0/1" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="MASKP0" description="Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." /> + <BitField start="1" size="1" name="MASKP1" description="Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." /> + <BitField start="2" size="1" name="MASKP2" description="Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." /> + <BitField start="3" size="1" name="MASKP3" description="Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." /> + <BitField start="4" size="1" name="MASKP4" description="Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." /> + <BitField start="5" size="1" name="MASKP5" description="Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." /> + <BitField start="6" size="1" name="MASKP6" description="Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." /> + <BitField start="7" size="1" name="MASKP7" description="Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." /> + <BitField start="8" size="1" name="MASKP8" description="Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." /> + <BitField start="9" size="1" name="MASKP9" description="Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." /> + <BitField start="10" size="1" name="MASKP10" description="Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." /> + <BitField start="11" size="1" name="MASKP11" description="Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." /> + <BitField start="12" size="1" name="MASKP12" description="Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." /> + <BitField start="13" size="1" name="MASKP13" description="Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." /> + <BitField start="14" size="1" name="MASKP14" description="Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." /> + <BitField start="15" size="1" name="MASKP15" description="Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." /> + <BitField start="16" size="1" name="MASKP16" description="Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." /> + <BitField start="17" size="1" name="MASKP17" description="Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." /> + <BitField start="18" size="1" name="MASKP18" description="Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." /> + <BitField start="19" size="1" name="MASKP19" description="Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." /> + <BitField start="20" size="1" name="MASKP20" description="Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." /> + <BitField start="21" size="1" name="MASKP21" description="Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." /> + <BitField start="22" size="1" name="MASKP22" description="Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." /> + <BitField start="23" size="1" name="MASKP23" description="Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." /> + <BitField start="24" size="1" name="MASKP24" description="Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." /> + <BitField start="25" size="1" name="MASKP25" description="Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." /> + <BitField start="26" size="1" name="MASKP26" description="Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." /> + <BitField start="27" size="1" name="MASKP27" description="Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." /> + <BitField start="28" size="1" name="MASKP28" description="Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." /> + <BitField start="29" size="1" name="MASKP29" description="Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." /> + <BitField start="30" size="1" name="MASKP30" description="Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." /> + <BitField start="31" size="1" name="MASKP31" description="Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." /> + </Register> + <Register start="+0x2080+4" size="4" name="MASK1" access="Read/Write" description="Mask register port 0/1" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="MASKP0" description="Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." /> + <BitField start="1" size="1" name="MASKP1" description="Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." /> + <BitField start="2" size="1" name="MASKP2" description="Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." /> + <BitField start="3" size="1" name="MASKP3" description="Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." /> + <BitField start="4" size="1" name="MASKP4" description="Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." /> + <BitField start="5" size="1" name="MASKP5" description="Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." /> + <BitField start="6" size="1" name="MASKP6" description="Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." /> + <BitField start="7" size="1" name="MASKP7" description="Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." /> + <BitField start="8" size="1" name="MASKP8" description="Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." /> + <BitField start="9" size="1" name="MASKP9" description="Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." /> + <BitField start="10" size="1" name="MASKP10" description="Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." /> + <BitField start="11" size="1" name="MASKP11" description="Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." /> + <BitField start="12" size="1" name="MASKP12" description="Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." /> + <BitField start="13" size="1" name="MASKP13" description="Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." /> + <BitField start="14" size="1" name="MASKP14" description="Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." /> + <BitField start="15" size="1" name="MASKP15" description="Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." /> + <BitField start="16" size="1" name="MASKP16" description="Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." /> + <BitField start="17" size="1" name="MASKP17" description="Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." /> + <BitField start="18" size="1" name="MASKP18" description="Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." /> + <BitField start="19" size="1" name="MASKP19" description="Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." /> + <BitField start="20" size="1" name="MASKP20" description="Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." /> + <BitField start="21" size="1" name="MASKP21" description="Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." /> + <BitField start="22" size="1" name="MASKP22" description="Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." /> + <BitField start="23" size="1" name="MASKP23" description="Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." /> + <BitField start="24" size="1" name="MASKP24" description="Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." /> + <BitField start="25" size="1" name="MASKP25" description="Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." /> + <BitField start="26" size="1" name="MASKP26" description="Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." /> + <BitField start="27" size="1" name="MASKP27" description="Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." /> + <BitField start="28" size="1" name="MASKP28" description="Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." /> + <BitField start="29" size="1" name="MASKP29" description="Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." /> + <BitField start="30" size="1" name="MASKP30" description="Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." /> + <BitField start="31" size="1" name="MASKP31" description="Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." /> + </Register> + <Register start="+0x2100+0" size="4" name="PIN0" access="Read/Write" description="Portpin register port 0" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="PORT0" description="Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." /> + <BitField start="1" size="1" name="PORT1" description="Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." /> + <BitField start="2" size="1" name="PORT2" description="Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." /> + <BitField start="3" size="1" name="PORT3" description="Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." /> + <BitField start="4" size="1" name="PORT4" description="Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." /> + <BitField start="5" size="1" name="PORT5" description="Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." /> + <BitField start="6" size="1" name="PORT6" description="Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." /> + <BitField start="7" size="1" name="PORT7" description="Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." /> + <BitField start="8" size="1" name="PORT8" description="Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." /> + <BitField start="9" size="1" name="PORT9" description="Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." /> + <BitField start="10" size="1" name="PORT10" description="Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." /> + <BitField start="11" size="1" name="PORT11" description="Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." /> + <BitField start="12" size="1" name="PORT12" description="Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." /> + <BitField start="13" size="1" name="PORT13" description="Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." /> + <BitField start="14" size="1" name="PORT14" description="Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." /> + <BitField start="15" size="1" name="PORT15" description="Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." /> + <BitField start="16" size="1" name="PORT16" description="Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." /> + <BitField start="17" size="1" name="PORT17" description="Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." /> + <BitField start="18" size="1" name="PORT18" description="Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." /> + <BitField start="19" size="1" name="PORT19" description="Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." /> + <BitField start="20" size="1" name="PORT20" description="Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." /> + <BitField start="21" size="1" name="PORT21" description="Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." /> + <BitField start="22" size="1" name="PORT22" description="Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." /> + <BitField start="23" size="1" name="PORT23" description="Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." /> + <BitField start="24" size="1" name="PORT24" description="Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." /> + <BitField start="25" size="1" name="PORT25" description="Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." /> + <BitField start="26" size="1" name="PORT26" description="Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." /> + <BitField start="27" size="1" name="PORT27" description="Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." /> + <BitField start="28" size="1" name="PORT28" description="Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." /> + <BitField start="29" size="1" name="PORT29" description="Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." /> + <BitField start="30" size="1" name="PORT30" description="Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." /> + <BitField start="31" size="1" name="PORT31" description="Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." /> + </Register> + <Register start="+0x2100+4" size="4" name="PIN1" access="Read/Write" description="Portpin register port 0" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="PORT0" description="Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." /> + <BitField start="1" size="1" name="PORT1" description="Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." /> + <BitField start="2" size="1" name="PORT2" description="Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." /> + <BitField start="3" size="1" name="PORT3" description="Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." /> + <BitField start="4" size="1" name="PORT4" description="Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." /> + <BitField start="5" size="1" name="PORT5" description="Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." /> + <BitField start="6" size="1" name="PORT6" description="Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." /> + <BitField start="7" size="1" name="PORT7" description="Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." /> + <BitField start="8" size="1" name="PORT8" description="Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." /> + <BitField start="9" size="1" name="PORT9" description="Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." /> + <BitField start="10" size="1" name="PORT10" description="Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." /> + <BitField start="11" size="1" name="PORT11" description="Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." /> + <BitField start="12" size="1" name="PORT12" description="Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." /> + <BitField start="13" size="1" name="PORT13" description="Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." /> + <BitField start="14" size="1" name="PORT14" description="Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." /> + <BitField start="15" size="1" name="PORT15" description="Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." /> + <BitField start="16" size="1" name="PORT16" description="Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." /> + <BitField start="17" size="1" name="PORT17" description="Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." /> + <BitField start="18" size="1" name="PORT18" description="Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." /> + <BitField start="19" size="1" name="PORT19" description="Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." /> + <BitField start="20" size="1" name="PORT20" description="Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." /> + <BitField start="21" size="1" name="PORT21" description="Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." /> + <BitField start="22" size="1" name="PORT22" description="Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." /> + <BitField start="23" size="1" name="PORT23" description="Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." /> + <BitField start="24" size="1" name="PORT24" description="Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." /> + <BitField start="25" size="1" name="PORT25" description="Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." /> + <BitField start="26" size="1" name="PORT26" description="Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." /> + <BitField start="27" size="1" name="PORT27" description="Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." /> + <BitField start="28" size="1" name="PORT28" description="Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." /> + <BitField start="29" size="1" name="PORT29" description="Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." /> + <BitField start="30" size="1" name="PORT30" description="Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." /> + <BitField start="31" size="1" name="PORT31" description="Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." /> + </Register> + <Register start="+0x2180+0" size="4" name="MPIN0" access="Read/Write" description="Masked port register port 0/1" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="MPORTP0" description="Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." /> + <BitField start="1" size="1" name="MPORTP1" description="Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." /> + <BitField start="2" size="1" name="MPORTP2" description="Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." /> + <BitField start="3" size="1" name="MPORTP3" description="Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." /> + <BitField start="4" size="1" name="MPORTP4" description="Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." /> + <BitField start="5" size="1" name="MPORTP5" description="Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." /> + <BitField start="6" size="1" name="MPORTP6" description="Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." /> + <BitField start="7" size="1" name="MPORTP7" description="Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." /> + <BitField start="8" size="1" name="MPORTP8" description="Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." /> + <BitField start="9" size="1" name="MPORTP9" description="Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." /> + <BitField start="10" size="1" name="MPORTP10" description="Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." /> + <BitField start="11" size="1" name="MPORTP11" description="Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." /> + <BitField start="12" size="1" name="MPORTP12" description="Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." /> + <BitField start="13" size="1" name="MPORTP13" description="Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." /> + <BitField start="14" size="1" name="MPORTP14" description="Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." /> + <BitField start="15" size="1" name="MPORTP15" description="Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." /> + <BitField start="16" size="1" name="MPORTP16" description="Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." /> + <BitField start="17" size="1" name="MPORTP17" description="Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." /> + <BitField start="18" size="1" name="MPORTP18" description="Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." /> + <BitField start="19" size="1" name="MPORTP19" description="Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." /> + <BitField start="20" size="1" name="MPORTP20" description="Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." /> + <BitField start="21" size="1" name="MPORTP21" description="Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." /> + <BitField start="22" size="1" name="MPORTP22" description="Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." /> + <BitField start="23" size="1" name="MPORTP23" description="Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." /> + <BitField start="24" size="1" name="MPORTP24" description="Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." /> + <BitField start="25" size="1" name="MPORTP25" description="Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." /> + <BitField start="26" size="1" name="MPORTP26" description="Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." /> + <BitField start="27" size="1" name="MPORTP27" description="Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." /> + <BitField start="28" size="1" name="MPORTP28" description="Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." /> + <BitField start="29" size="1" name="MPORTP29" description="Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." /> + <BitField start="30" size="1" name="MPORTP30" description="Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." /> + <BitField start="31" size="1" name="MPORTP31" description="Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." /> + </Register> + <Register start="+0x2180+4" size="4" name="MPIN1" access="Read/Write" description="Masked port register port 0/1" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="MPORTP0" description="Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." /> + <BitField start="1" size="1" name="MPORTP1" description="Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." /> + <BitField start="2" size="1" name="MPORTP2" description="Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." /> + <BitField start="3" size="1" name="MPORTP3" description="Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." /> + <BitField start="4" size="1" name="MPORTP4" description="Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." /> + <BitField start="5" size="1" name="MPORTP5" description="Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." /> + <BitField start="6" size="1" name="MPORTP6" description="Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." /> + <BitField start="7" size="1" name="MPORTP7" description="Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." /> + <BitField start="8" size="1" name="MPORTP8" description="Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." /> + <BitField start="9" size="1" name="MPORTP9" description="Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." /> + <BitField start="10" size="1" name="MPORTP10" description="Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." /> + <BitField start="11" size="1" name="MPORTP11" description="Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." /> + <BitField start="12" size="1" name="MPORTP12" description="Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." /> + <BitField start="13" size="1" name="MPORTP13" description="Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." /> + <BitField start="14" size="1" name="MPORTP14" description="Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." /> + <BitField start="15" size="1" name="MPORTP15" description="Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." /> + <BitField start="16" size="1" name="MPORTP16" description="Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." /> + <BitField start="17" size="1" name="MPORTP17" description="Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." /> + <BitField start="18" size="1" name="MPORTP18" description="Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." /> + <BitField start="19" size="1" name="MPORTP19" description="Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." /> + <BitField start="20" size="1" name="MPORTP20" description="Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." /> + <BitField start="21" size="1" name="MPORTP21" description="Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." /> + <BitField start="22" size="1" name="MPORTP22" description="Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." /> + <BitField start="23" size="1" name="MPORTP23" description="Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." /> + <BitField start="24" size="1" name="MPORTP24" description="Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." /> + <BitField start="25" size="1" name="MPORTP25" description="Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." /> + <BitField start="26" size="1" name="MPORTP26" description="Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." /> + <BitField start="27" size="1" name="MPORTP27" description="Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." /> + <BitField start="28" size="1" name="MPORTP28" description="Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." /> + <BitField start="29" size="1" name="MPORTP29" description="Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." /> + <BitField start="30" size="1" name="MPORTP30" description="Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." /> + <BitField start="31" size="1" name="MPORTP31" description="Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." /> + </Register> + <Register start="+0x2200+0" size="4" name="SET0" access="Read/Write" description="Write: Set register for port 0/1 Read: output bits for port 0/1" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="SETP0" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." /> + <BitField start="1" size="1" name="SETP1" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." /> + <BitField start="2" size="1" name="SETP2" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." /> + <BitField start="3" size="1" name="SETP3" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." /> + <BitField start="4" size="1" name="SETP4" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." /> + <BitField start="5" size="1" name="SETP5" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." /> + <BitField start="6" size="1" name="SETP6" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." /> + <BitField start="7" size="1" name="SETP7" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." /> + <BitField start="8" size="1" name="SETP8" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." /> + <BitField start="9" size="1" name="SETP9" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." /> + <BitField start="10" size="1" name="SETP10" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." /> + <BitField start="11" size="1" name="SETP11" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." /> + <BitField start="12" size="1" name="SETP12" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." /> + <BitField start="13" size="1" name="SETP13" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." /> + <BitField start="14" size="1" name="SETP14" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." /> + <BitField start="15" size="1" name="SETP15" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." /> + <BitField start="16" size="1" name="SETP16" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." /> + <BitField start="17" size="1" name="SETP17" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." /> + <BitField start="18" size="1" name="SETP18" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." /> + <BitField start="19" size="1" name="SETP19" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." /> + <BitField start="20" size="1" name="SETP20" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." /> + <BitField start="21" size="1" name="SETP21" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." /> + <BitField start="22" size="1" name="SETP22" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." /> + <BitField start="23" size="1" name="SETP23" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." /> + <BitField start="24" size="1" name="SETP24" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." /> + <BitField start="25" size="1" name="SETP25" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." /> + <BitField start="26" size="1" name="SETP26" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." /> + <BitField start="27" size="1" name="SETP27" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." /> + <BitField start="28" size="1" name="SETP28" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." /> + <BitField start="29" size="1" name="SETP29" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." /> + <BitField start="30" size="1" name="SETP30" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." /> + <BitField start="31" size="1" name="SETP31" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." /> + </Register> + <Register start="+0x2200+4" size="4" name="SET1" access="Read/Write" description="Write: Set register for port 0/1 Read: output bits for port 0/1" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="SETP0" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." /> + <BitField start="1" size="1" name="SETP1" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." /> + <BitField start="2" size="1" name="SETP2" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." /> + <BitField start="3" size="1" name="SETP3" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." /> + <BitField start="4" size="1" name="SETP4" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." /> + <BitField start="5" size="1" name="SETP5" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." /> + <BitField start="6" size="1" name="SETP6" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." /> + <BitField start="7" size="1" name="SETP7" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." /> + <BitField start="8" size="1" name="SETP8" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." /> + <BitField start="9" size="1" name="SETP9" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." /> + <BitField start="10" size="1" name="SETP10" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." /> + <BitField start="11" size="1" name="SETP11" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." /> + <BitField start="12" size="1" name="SETP12" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." /> + <BitField start="13" size="1" name="SETP13" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." /> + <BitField start="14" size="1" name="SETP14" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." /> + <BitField start="15" size="1" name="SETP15" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." /> + <BitField start="16" size="1" name="SETP16" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." /> + <BitField start="17" size="1" name="SETP17" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." /> + <BitField start="18" size="1" name="SETP18" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." /> + <BitField start="19" size="1" name="SETP19" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." /> + <BitField start="20" size="1" name="SETP20" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." /> + <BitField start="21" size="1" name="SETP21" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." /> + <BitField start="22" size="1" name="SETP22" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." /> + <BitField start="23" size="1" name="SETP23" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." /> + <BitField start="24" size="1" name="SETP24" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." /> + <BitField start="25" size="1" name="SETP25" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." /> + <BitField start="26" size="1" name="SETP26" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." /> + <BitField start="27" size="1" name="SETP27" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." /> + <BitField start="28" size="1" name="SETP28" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." /> + <BitField start="29" size="1" name="SETP29" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." /> + <BitField start="30" size="1" name="SETP30" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." /> + <BitField start="31" size="1" name="SETP31" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." /> + </Register> + <Register start="+0x2280+0" size="4" name="CLR0" access="WriteOnly" description="Clear port 0/1" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="CLRP00" description="Clear output bits: 0 = No operation. 1 = Clear output bit." /> + <BitField start="1" size="1" name="CLRP01" description="Clear output bits: 0 = No operation. 1 = Clear output bit." /> + <BitField start="2" size="1" name="CLRP02" description="Clear output bits: 0 = No operation. 1 = Clear output bit." /> + <BitField start="3" size="1" name="CLRP03" description="Clear output bits: 0 = No operation. 1 = Clear output bit." /> + <BitField start="4" size="1" name="CLRP04" description="Clear output bits: 0 = No operation. 1 = Clear output bit." /> + <BitField start="5" size="1" name="CLRP05" description="Clear output bits: 0 = No operation. 1 = Clear output bit." /> + <BitField start="6" size="1" name="CLRP06" description="Clear output bits: 0 = No operation. 1 = Clear output bit." /> + <BitField start="7" size="1" name="CLRP07" description="Clear output bits: 0 = No operation. 1 = Clear output bit." /> + <BitField start="8" size="1" name="CLRP08" description="Clear output bits: 0 = No operation. 1 = Clear output bit." /> + <BitField start="9" size="1" name="CLRP09" description="Clear output bits: 0 = No operation. 1 = Clear output bit." /> + <BitField start="10" size="1" name="CLRP010" description="Clear output bits: 0 = No operation. 1 = Clear output bit." /> + <BitField start="11" size="1" name="CLRP011" description="Clear output bits: 0 = No operation. 1 = Clear output bit." /> + <BitField start="12" size="1" name="CLRP012" description="Clear output bits: 0 = No operation. 1 = Clear output bit." /> + <BitField start="13" size="1" name="CLRP013" description="Clear output bits: 0 = No operation. 1 = Clear output bit." /> + <BitField start="14" size="1" name="CLRP014" description="Clear output bits: 0 = No operation. 1 = Clear output bit." /> + <BitField start="15" size="1" name="CLRP015" description="Clear output bits: 0 = No operation. 1 = Clear output bit." /> + <BitField start="16" size="1" name="CLRP016" description="Clear output bits: 0 = No operation. 1 = Clear output bit." /> + <BitField start="17" size="1" name="CLRP017" description="Clear output bits: 0 = No operation. 1 = Clear output bit." /> + <BitField start="18" size="1" name="CLRP018" description="Clear output bits: 0 = No operation. 1 = Clear output bit." /> + <BitField start="19" size="1" name="CLRP019" description="Clear output bits: 0 = No operation. 1 = Clear output bit." /> + <BitField start="20" size="1" name="CLRP020" description="Clear output bits: 0 = No operation. 1 = Clear output bit." /> + <BitField start="21" size="1" name="CLRP021" description="Clear output bits: 0 = No operation. 1 = Clear output bit." /> + <BitField start="22" size="1" name="CLRP022" description="Clear output bits: 0 = No operation. 1 = Clear output bit." /> + <BitField start="23" size="1" name="CLRP023" description="Clear output bits: 0 = No operation. 1 = Clear output bit." /> + <BitField start="24" size="1" name="CLRP024" description="Clear output bits: 0 = No operation. 1 = Clear output bit." /> + <BitField start="25" size="1" name="CLRP025" description="Clear output bits: 0 = No operation. 1 = Clear output bit." /> + <BitField start="26" size="1" name="CLRP026" description="Clear output bits: 0 = No operation. 1 = Clear output bit." /> + <BitField start="27" size="1" name="CLRP027" description="Clear output bits: 0 = No operation. 1 = Clear output bit." /> + <BitField start="28" size="1" name="CLRP028" description="Clear output bits: 0 = No operation. 1 = Clear output bit." /> + <BitField start="29" size="1" name="CLRP029" description="Clear output bits: 0 = No operation. 1 = Clear output bit." /> + <BitField start="30" size="1" name="CLRP030" description="Clear output bits: 0 = No operation. 1 = Clear output bit." /> + <BitField start="31" size="1" name="CLRP031" description="Clear output bits: 0 = No operation. 1 = Clear output bit." /> + </Register> + <Register start="+0x2280+4" size="4" name="CLR1" access="WriteOnly" description="Clear port 0/1" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="CLRP00" description="Clear output bits: 0 = No operation. 1 = Clear output bit." /> + <BitField start="1" size="1" name="CLRP01" description="Clear output bits: 0 = No operation. 1 = Clear output bit." /> + <BitField start="2" size="1" name="CLRP02" description="Clear output bits: 0 = No operation. 1 = Clear output bit." /> + <BitField start="3" size="1" name="CLRP03" description="Clear output bits: 0 = No operation. 1 = Clear output bit." /> + <BitField start="4" size="1" name="CLRP04" description="Clear output bits: 0 = No operation. 1 = Clear output bit." /> + <BitField start="5" size="1" name="CLRP05" description="Clear output bits: 0 = No operation. 1 = Clear output bit." /> + <BitField start="6" size="1" name="CLRP06" description="Clear output bits: 0 = No operation. 1 = Clear output bit." /> + <BitField start="7" size="1" name="CLRP07" description="Clear output bits: 0 = No operation. 1 = Clear output bit." /> + <BitField start="8" size="1" name="CLRP08" description="Clear output bits: 0 = No operation. 1 = Clear output bit." /> + <BitField start="9" size="1" name="CLRP09" description="Clear output bits: 0 = No operation. 1 = Clear output bit." /> + <BitField start="10" size="1" name="CLRP010" description="Clear output bits: 0 = No operation. 1 = Clear output bit." /> + <BitField start="11" size="1" name="CLRP011" description="Clear output bits: 0 = No operation. 1 = Clear output bit." /> + <BitField start="12" size="1" name="CLRP012" description="Clear output bits: 0 = No operation. 1 = Clear output bit." /> + <BitField start="13" size="1" name="CLRP013" description="Clear output bits: 0 = No operation. 1 = Clear output bit." /> + <BitField start="14" size="1" name="CLRP014" description="Clear output bits: 0 = No operation. 1 = Clear output bit." /> + <BitField start="15" size="1" name="CLRP015" description="Clear output bits: 0 = No operation. 1 = Clear output bit." /> + <BitField start="16" size="1" name="CLRP016" description="Clear output bits: 0 = No operation. 1 = Clear output bit." /> + <BitField start="17" size="1" name="CLRP017" description="Clear output bits: 0 = No operation. 1 = Clear output bit." /> + <BitField start="18" size="1" name="CLRP018" description="Clear output bits: 0 = No operation. 1 = Clear output bit." /> + <BitField start="19" size="1" name="CLRP019" description="Clear output bits: 0 = No operation. 1 = Clear output bit." /> + <BitField start="20" size="1" name="CLRP020" description="Clear output bits: 0 = No operation. 1 = Clear output bit." /> + <BitField start="21" size="1" name="CLRP021" description="Clear output bits: 0 = No operation. 1 = Clear output bit." /> + <BitField start="22" size="1" name="CLRP022" description="Clear output bits: 0 = No operation. 1 = Clear output bit." /> + <BitField start="23" size="1" name="CLRP023" description="Clear output bits: 0 = No operation. 1 = Clear output bit." /> + <BitField start="24" size="1" name="CLRP024" description="Clear output bits: 0 = No operation. 1 = Clear output bit." /> + <BitField start="25" size="1" name="CLRP025" description="Clear output bits: 0 = No operation. 1 = Clear output bit." /> + <BitField start="26" size="1" name="CLRP026" description="Clear output bits: 0 = No operation. 1 = Clear output bit." /> + <BitField start="27" size="1" name="CLRP027" description="Clear output bits: 0 = No operation. 1 = Clear output bit." /> + <BitField start="28" size="1" name="CLRP028" description="Clear output bits: 0 = No operation. 1 = Clear output bit." /> + <BitField start="29" size="1" name="CLRP029" description="Clear output bits: 0 = No operation. 1 = Clear output bit." /> + <BitField start="30" size="1" name="CLRP030" description="Clear output bits: 0 = No operation. 1 = Clear output bit." /> + <BitField start="31" size="1" name="CLRP031" description="Clear output bits: 0 = No operation. 1 = Clear output bit." /> + </Register> + <Register start="+0x2300+0" size="4" name="NOT0" access="WriteOnly" description="Toggle port 0/1" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="NOTP0" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." /> + <BitField start="1" size="1" name="NOTP1" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." /> + <BitField start="2" size="1" name="NOTP2" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." /> + <BitField start="3" size="1" name="NOTP3" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." /> + <BitField start="4" size="1" name="NOTP4" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." /> + <BitField start="5" size="1" name="NOTP5" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." /> + <BitField start="6" size="1" name="NOTP6" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." /> + <BitField start="7" size="1" name="NOTP7" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." /> + <BitField start="8" size="1" name="NOTP8" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." /> + <BitField start="9" size="1" name="NOTP9" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." /> + <BitField start="10" size="1" name="NOTP10" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." /> + <BitField start="11" size="1" name="NOTP11" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." /> + <BitField start="12" size="1" name="NOTP12" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." /> + <BitField start="13" size="1" name="NOTP13" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." /> + <BitField start="14" size="1" name="NOTP14" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." /> + <BitField start="15" size="1" name="NOTP15" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." /> + <BitField start="16" size="1" name="NOTP16" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." /> + <BitField start="17" size="1" name="NOTP17" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." /> + <BitField start="18" size="1" name="NOTP18" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." /> + <BitField start="19" size="1" name="NOTP19" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." /> + <BitField start="20" size="1" name="NOTP20" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." /> + <BitField start="21" size="1" name="NOTP21" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." /> + <BitField start="22" size="1" name="NOTP22" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." /> + <BitField start="23" size="1" name="NOTP23" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." /> + <BitField start="24" size="1" name="NOTP24" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." /> + <BitField start="25" size="1" name="NOTP25" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." /> + <BitField start="26" size="1" name="NOTP26" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." /> + <BitField start="27" size="1" name="NOTP27" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." /> + <BitField start="28" size="1" name="NOTP28" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." /> + <BitField start="29" size="1" name="NOTP29" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." /> + <BitField start="30" size="1" name="NOTP30" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." /> + <BitField start="31" size="1" name="NOTP31" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." /> + </Register> + <Register start="+0x2300+4" size="4" name="NOT1" access="WriteOnly" description="Toggle port 0/1" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="NOTP0" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." /> + <BitField start="1" size="1" name="NOTP1" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." /> + <BitField start="2" size="1" name="NOTP2" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." /> + <BitField start="3" size="1" name="NOTP3" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." /> + <BitField start="4" size="1" name="NOTP4" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." /> + <BitField start="5" size="1" name="NOTP5" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." /> + <BitField start="6" size="1" name="NOTP6" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." /> + <BitField start="7" size="1" name="NOTP7" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." /> + <BitField start="8" size="1" name="NOTP8" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." /> + <BitField start="9" size="1" name="NOTP9" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." /> + <BitField start="10" size="1" name="NOTP10" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." /> + <BitField start="11" size="1" name="NOTP11" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." /> + <BitField start="12" size="1" name="NOTP12" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." /> + <BitField start="13" size="1" name="NOTP13" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." /> + <BitField start="14" size="1" name="NOTP14" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." /> + <BitField start="15" size="1" name="NOTP15" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." /> + <BitField start="16" size="1" name="NOTP16" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." /> + <BitField start="17" size="1" name="NOTP17" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." /> + <BitField start="18" size="1" name="NOTP18" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." /> + <BitField start="19" size="1" name="NOTP19" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." /> + <BitField start="20" size="1" name="NOTP20" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." /> + <BitField start="21" size="1" name="NOTP21" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." /> + <BitField start="22" size="1" name="NOTP22" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." /> + <BitField start="23" size="1" name="NOTP23" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." /> + <BitField start="24" size="1" name="NOTP24" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." /> + <BitField start="25" size="1" name="NOTP25" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." /> + <BitField start="26" size="1" name="NOTP26" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." /> + <BitField start="27" size="1" name="NOTP27" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." /> + <BitField start="28" size="1" name="NOTP28" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." /> + <BitField start="29" size="1" name="NOTP29" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." /> + <BitField start="30" size="1" name="NOTP30" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." /> + <BitField start="31" size="1" name="NOTP31" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." /> + </Register> + </RegisterGroup> + <RegisterGroup name="NVIC" start="0xE000E100" description="Nested Vectored Interrupt Controller"> + <Register name="NVIC_ISER0" description="Interrupt Set-Enable Register 0" start="0xE000E100"> + <BitField name="PIN_INT0" start="0" size="1" /> + <BitField name="PIN_INT1" start="1" size="1" /> + <BitField name="PIN_INT2" start="2" size="1" /> + <BitField name="PIN_INT3" start="3" size="1" /> + <BitField name="PIN_INT4" start="4" size="1" /> + <BitField name="PIN_INT5" start="5" size="1" /> + <BitField name="PIN_INT6" start="6" size="1" /> + <BitField name="PIN_INT7" start="7" size="1" /> + <BitField name="GINT0" start="8" size="1" /> + <BitField name="GINT1" start="9" size="1" /> + <BitField name="RIT" start="12" size="1" /> + <BitField name="SSP1" start="14" size="1" /> + <BitField name="I2C" start="15" size="1" /> + <BitField name="CT16B0" start="16" size="1" /> + <BitField name="CT16B1" start="17" size="1" /> + <BitField name="CT32B0" start="18" size="1" /> + <BitField name="CT32B1" start="19" size="1" /> + <BitField name="SSP0" start="20" size="1" /> + <BitField name="USART" start="21" size="1" /> + <BitField name="USB" start="22" size="1" /> + <BitField name="USB_FIQ" start="23" size="1" /> + <BitField name="ADC" start="24" size="1" /> + <BitField name="WWDT" start="25" size="1" /> + <BitField name="BOD" start="26" size="1" /> + <BitField name="FLASH" start="27" size="1" /> + <BitField name="USBWAKEUP" start="30" size="1" /> + </Register> + <Register name="NVIC_ICER0" description="Interrupt Clear-Enable Register 0" start="0xE000E180"> + <BitField name="PIN_INT0" start="0" size="1" /> + <BitField name="PIN_INT1" start="1" size="1" /> + <BitField name="PIN_INT2" start="2" size="1" /> + <BitField name="PIN_INT3" start="3" size="1" /> + <BitField name="PIN_INT4" start="4" size="1" /> + <BitField name="PIN_INT5" start="5" size="1" /> + <BitField name="PIN_INT6" start="6" size="1" /> + <BitField name="PIN_INT7" start="7" size="1" /> + <BitField name="GINT0" start="8" size="1" /> + <BitField name="GINT1" start="9" size="1" /> + <BitField name="RIT" start="12" size="1" /> + <BitField name="SSP1" start="14" size="1" /> + <BitField name="I2C" start="15" size="1" /> + <BitField name="CT16B0" start="16" size="1" /> + <BitField name="CT16B1" start="17" size="1" /> + <BitField name="CT32B0" start="18" size="1" /> + <BitField name="CT32B1" start="19" size="1" /> + <BitField name="SSP0" start="20" size="1" /> + <BitField name="USART" start="21" size="1" /> + <BitField name="USB" start="22" size="1" /> + <BitField name="USB_FIQ" start="23" size="1" /> + <BitField name="ADC" start="24" size="1" /> + <BitField name="WWDT" start="25" size="1" /> + <BitField name="BOD" start="26" size="1" /> + <BitField name="FLASH" start="27" size="1" /> + <BitField name="USBWAKEUP" start="30" size="1" /> + </Register> + <Register name="NVIC_ISPR0" description="Interrupt Set-Pending Register 0" start="0xE000E200"> + <BitField name="PIN_INT0" start="0" size="1" /> + <BitField name="PIN_INT1" start="1" size="1" /> + <BitField name="PIN_INT2" start="2" size="1" /> + <BitField name="PIN_INT3" start="3" size="1" /> + <BitField name="PIN_INT4" start="4" size="1" /> + <BitField name="PIN_INT5" start="5" size="1" /> + <BitField name="PIN_INT6" start="6" size="1" /> + <BitField name="PIN_INT7" start="7" size="1" /> + <BitField name="GINT0" start="8" size="1" /> + <BitField name="GINT1" start="9" size="1" /> + <BitField name="RIT" start="12" size="1" /> + <BitField name="SSP1" start="14" size="1" /> + <BitField name="I2C" start="15" size="1" /> + <BitField name="CT16B0" start="16" size="1" /> + <BitField name="CT16B1" start="17" size="1" /> + <BitField name="CT32B0" start="18" size="1" /> + <BitField name="CT32B1" start="19" size="1" /> + <BitField name="SSP0" start="20" size="1" /> + <BitField name="USART" start="21" size="1" /> + <BitField name="USB" start="22" size="1" /> + <BitField name="USB_FIQ" start="23" size="1" /> + <BitField name="ADC" start="24" size="1" /> + <BitField name="WWDT" start="25" size="1" /> + <BitField name="BOD" start="26" size="1" /> + <BitField name="FLASH" start="27" size="1" /> + <BitField name="USBWAKEUP" start="30" size="1" /> + </Register> + <Register name="NVIC_ICPR0" description="Interrupt Clear-Pending Register 0" start="0xE000E280"> + <BitField name="PIN_INT0" start="0" size="1" /> + <BitField name="PIN_INT1" start="1" size="1" /> + <BitField name="PIN_INT2" start="2" size="1" /> + <BitField name="PIN_INT3" start="3" size="1" /> + <BitField name="PIN_INT4" start="4" size="1" /> + <BitField name="PIN_INT5" start="5" size="1" /> + <BitField name="PIN_INT6" start="6" size="1" /> + <BitField name="PIN_INT7" start="7" size="1" /> + <BitField name="GINT0" start="8" size="1" /> + <BitField name="GINT1" start="9" size="1" /> + <BitField name="RIT" start="12" size="1" /> + <BitField name="SSP1" start="14" size="1" /> + <BitField name="I2C" start="15" size="1" /> + <BitField name="CT16B0" start="16" size="1" /> + <BitField name="CT16B1" start="17" size="1" /> + <BitField name="CT32B0" start="18" size="1" /> + <BitField name="CT32B1" start="19" size="1" /> + <BitField name="SSP0" start="20" size="1" /> + <BitField name="USART" start="21" size="1" /> + <BitField name="USB" start="22" size="1" /> + <BitField name="USB_FIQ" start="23" size="1" /> + <BitField name="ADC" start="24" size="1" /> + <BitField name="WWDT" start="25" size="1" /> + <BitField name="BOD" start="26" size="1" /> + <BitField name="FLASH" start="27" size="1" /> + <BitField name="USBWAKEUP" start="30" size="1" /> + </Register> + <Register name="NVIC_IABR0" description="Interrupt Active Bit Register 0" start="0xE000E300" access="ReadOnly"> + <BitField name="PIN_INT0" start="0" size="1" /> + <BitField name="PIN_INT1" start="1" size="1" /> + <BitField name="PIN_INT2" start="2" size="1" /> + <BitField name="PIN_INT3" start="3" size="1" /> + <BitField name="PIN_INT4" start="4" size="1" /> + <BitField name="PIN_INT5" start="5" size="1" /> + <BitField name="PIN_INT6" start="6" size="1" /> + <BitField name="PIN_INT7" start="7" size="1" /> + <BitField name="GINT0" start="8" size="1" /> + <BitField name="GINT1" start="9" size="1" /> + <BitField name="RIT" start="12" size="1" /> + <BitField name="SSP1" start="14" size="1" /> + <BitField name="I2C" start="15" size="1" /> + <BitField name="CT16B0" start="16" size="1" /> + <BitField name="CT16B1" start="17" size="1" /> + <BitField name="CT32B0" start="18" size="1" /> + <BitField name="CT32B1" start="19" size="1" /> + <BitField name="SSP0" start="20" size="1" /> + <BitField name="USART" start="21" size="1" /> + <BitField name="USB" start="22" size="1" /> + <BitField name="USB_FIQ" start="23" size="1" /> + <BitField name="ADC" start="24" size="1" /> + <BitField name="WWDT" start="25" size="1" /> + <BitField name="BOD" start="26" size="1" /> + <BitField name="FLASH" start="27" size="1" /> + <BitField name="USBWAKEUP" start="30" size="1" /> + </Register> + <Register name="NVIC_IPR0" description="Interrupt Priority Register 0" start="0xE000E400"> + <BitField name="PIN_INT0" start="4" size="4" /> + <BitField name="PIN_INT1" start="12" size="4" /> + <BitField name="PIN_INT2" start="20" size="4" /> + <BitField name="PIN_INT3" start="28" size="4" /> + </Register> + <Register name="NVIC_IPR1" description="Interrupt Priority Register 1" start="0xE000E404"> + <BitField name="PIN_INT4" start="4" size="4" /> + <BitField name="PIN_INT5" start="12" size="4" /> + <BitField name="PIN_INT6" start="20" size="4" /> + <BitField name="PIN_INT7" start="28" size="4" /> + </Register> + <Register name="NVIC_IPR2" description="Interrupt Priority Register 2" start="0xE000E408"> + <BitField name="GINT0" start="4" size="4" /> + <BitField name="GINT1" start="12" size="4" /> + </Register> + <Register name="NVIC_IPR3" description="Interrupt Priority Register 3" start="0xE000E40C"> + <BitField name="RIT" start="4" size="4" /> + <BitField name="SSP1" start="20" size="4" /> + <BitField name="I2C" start="28" size="4" /> + </Register> + <Register name="NVIC_IPR4" description="Interrupt Priority Register 4" start="0xE000E410"> + <BitField name="CT16B0" start="4" size="4" /> + <BitField name="CT16B1" start="12" size="4" /> + <BitField name="CT32B0" start="20" size="4" /> + <BitField name="CT32B1" start="28" size="4" /> + </Register> + <Register name="NVIC_IPR5" description="Interrupt Priority Register 5" start="0xE000E414"> + <BitField name="SSP0" start="4" size="4" /> + <BitField name="USART" start="12" size="4" /> + <BitField name="USB" start="20" size="4" /> + <BitField name="USB_FIQ" start="28" size="4" /> + </Register> + <Register name="NVIC_IPR6" description="Interrupt Priority Register 6" start="0xE000E418"> + <BitField name="ADC" start="4" size="4" /> + <BitField name="WWDT" start="12" size="4" /> + <BitField name="BOD" start="20" size="4" /> + <BitField name="FLASH" start="28" size="4" /> + </Register> + <Register name="NVIC_IPR7" description="Interrupt Priority Register 7" start="0xE000E41C"> + <BitField name="USBWAKEUP" start="20" size="4" /> + </Register> + </RegisterGroup> + <RegisterGroup name="SysTick" start="0xE000E010" description="24-bit System Timer"> + <Register name="SYST_CSR" start="0xE000E010" description="SysTick Control and Status Register"> + <BitField name="COUNTFLAG" start="16" size="1" description="Counter Flag" /> + <BitField name="CLKSOURCE" start="2" size="1" description="Timer Clock Source" /> + <BitField name="TICKINT" start="1" size="1" description="Tick Interrupt Enable" /> + <BitField name="ENABLE" start="0" size="1" description="Enable SysTick Timer" /> + </Register> + <Register name="SYST_RVR" start="0xE000E014" description="SysTick Reload Value Register"> + <BitField name="RELOAD" start="0" size="24" description="Value to load into the SYST_CVR when the counter is enabled and when it reaches 0" /> + </Register> + <Register name="SYST_CVR" start="0xE000E018" description="SysTick Current Value Register Register"> + <BitField name="CURRENT" start="0" size="24" description="The current value of the SysTick counter" /> + </Register> + <Register name="SYST_CALIB" start="0xE000E01C" access="ReadOnly" description="SysTick Calibration Value Register"> + <BitField name="NOREF" start="31" size="1" description="Indicates whether the device provides a reference clock to the processor" /> + <BitField name="SKEW" start="30" size="1" description="Indicates whether the TENMS value is exact" /> + <BitField name="TENMS" start="0" size="24" description="Reload value for 10ms (100Hz) timing, subject to system clock skew errors" /> + </Register> + </RegisterGroup> + <RegisterGroup name="SCB" start="" description="System Control Block"> + <Register name="ACTLR" start="0xE000E008" description="Auxiliary Control Register"> + <BitField name="DISFOLD" start="2" size="1" description="When set to 1, disables write buffer use during default memory map accesses" /> + <BitField name="DISDEFWBUF" start="1" size="1" description="When set to 1, disables write buffer use during default memory map accesses" /> + <BitField name="DISMCYCINT" start="0" size="1" description="When set to 1, disables interruption of load multiple and store multiple instructions" /> + </Register> + <Register name="CPUID" start="0xE000ED00" access="ReadOnly" description="CPUID Register"> + <BitField name="IMPLEMENTER" start="24" size="8" description="Implementer Code" /> + <BitField name="VARIANT" start="20" size="4" description="Variant Number" /> + <BitField name="PARTNO" start="4" size="12" description="Part Number" /> + <BitField name="REVISION" start="0" size="4" description="Revision Number" /> + </Register> + <Register name="ICSR" start="0xE000ED04" description="Interrupt Control and State Register"> + <BitField name="NMIPENDSET" start="31" size="1" description="NMI set-pending bit" /> + <BitField name="PENDSVSET" start="28" size="1" description="PendSV set-pending bit" /> + <BitField name="PENDSVCLR" start="27" size="1" description="PendSV clear-pending bit" /> + <BitField name="PENDSTSET" start="26" size="1" description="SysTick exception set-pending bit" /> + <BitField name="PENDSTCLR" start="25" size="1" description="SysTick exception clear-pending bit" /> + <BitField name="ISRPREEMPT" start="23" size="1" description="" /> + <BitField name="ISRPENDING" start="22" size="1" description="Interrupt pending flag" /> + <BitField name="VECTPENDING" start="12" size="9" description="Indicates the exception number of the highest priority pending enabled exception" /> + <BitField name="RETTOBASE" start="11" size="1" description="Indicates whether there are preempted active exceptions" /> + <BitField name="VECTACTIVE" start="0" size="9" description="Contains the active exception number" /> + </Register> + <Register name="VTOR" start="0xE000ED08" description="Vector Table Offset Register"> + <BitField name="TBLOFF" start="7" size="25" description="Vector table base offset field" /> + </Register> + <Register name="AIRCR" start="0xE000ED0C" description="Application Interrupt and Reset Control Register"> + <BitField name="VECTKEY" start="16" size="16" description="Register key" /> + <BitField name="ENDIANESS" start="15" size="1" description="Data endianness bit" /> + <BitField name="PRIGROUP" start="8" size="3" description="Interrupt priority grouping field" /> + <BitField name="SYSRESETREQ" start="2" size="1" description="System reset request bit" /> + <BitField name="VECTCLRACTIVE" start="1" size="1" description="" /> + <BitField name="VECTRESET" start="0" size="1" description="" /> + </Register> + <Register name="SCR" start="0xE000ED10" description="System Control Register"> + <BitField name="SEVONPEND" start="4" size="1" description="Send event on pending bit" /> + <BitField name="SLEEPDEEP" start="2" size="1" description="Controls whether the processor uses sleep or deep sleep as its low power mode" /> + <BitField name="SLEEPONEXIT" start="1" size="1" description="Indicates sleep-on-exit when returning from Handler mode to Thread mode" /> + </Register> + <Register name="CCR" start="0xE000ED14" access="ReadOnly" description="Configuration and Control Register"> + <BitField name="STKALIGN" start="9" size="1" description="Indicates stack alignment on exception entry" /> + <BitField name="BFHFNMIGN" start="8" size="1" description="Enables handlers with priority -1 or-2 to ignore data BusFaults caused by load and store instructions" /> + <BitField name="DIV_0_TRP" start="4" size="1" description="Enables faulting or halting when the processor executes an SDIVor UDIV instruction with a divisor of 0" /> + <BitField name="UNALIGN_TRP" start="3" size="1" description="Enables unaligned access traps" /> + <BitField name="USERSETMPEND" start="1" size="1" description="Enables unprivileged software access to the STIR" /> + <BitField name="NONBASETHRDENA" start="0" size="1" description="Indicates how the processor enters Thread mode" /> + </Register> + <Register name="SHPR1" start="0xE000ED18" description="System Handler Priority Register 1"> + <BitField name="PRI_6" start="20" size="4" description="Priority of system handler 6 (UsageFault)" /> + <BitField name="PRI_5" start="12" size="4" description="Priority of system handler 5 (BusFault)" /> + <BitField name="PRI_4" start="4" size="4" description="Priority of system handler 4 (MemManage)" /> + </Register> + <Register name="SHPR2" start="0xE000ED1C" description="System Handler Priority Register 2"> + <BitField name="PRI_11" start="28" size="4" description="Priority of system handler 11 (SVCall)" /> + </Register> + <Register name="SHPR3" start="0xE000ED20" description="System Handler Priority Register 3"> + <BitField name="PRI_15" start="28" size="4" description="Priority of system handler 15 (SysTick)" /> + <BitField name="PRI_14" start="20" size="4" description="Priority of system handler 14 (PendSV)" /> + </Register> + <Register name="SHCSR" start="0xE000ED24" description="System Handler Control and State Register"> + <BitField name="USGFAULTENA" start="18" size="1" description="UsageFault enable Bit" /> + <BitField name="BUSFAULTENA" start="17" size="1" description="BusFault Enable Bit" /> + <BitField name="MEMFAULTENA" start="16" size="1" description="MemManage Enable Bit" /> + <BitField name="SVCALLPENDED" start="15" size="1" description="SVCall Pending Bit" /> + <BitField name="BUSFAULTPENDED" start="14" size="1" description="BusFault Exception Pending Bit" /> + <BitField name="MEMFAULTPENDED" start="13" size="1" description="MemManage Exception Pending Bit" /> + <BitField name="USGFAULTPENDED" start="12" size="1" description="UsageFault Exception Pending Bit" /> + <BitField name="SYSTICKACT" start="11" size="1" description="SysTick Exception Active Bit" /> + <BitField name="PENDSVACT" start="10" size="1" description="PendSV Exception Active Bit" /> + <BitField name="MONITORACT" start="8" size="1" description="Debug Monitor Active Bit" /> + <BitField name="SVCALLACT" start="7" size="1" description="SVCall Active Bit" /> + <BitField name="USGFAULTACT" start="3" size="1" description="UsageFault Exception Active Bit" /> + <BitField name="BUSFAULTACT" start="1" size="1" description="BusFault Exception Active Bit" /> + <BitField name="MEMFAULTACT" start="0" size="1" description="MemManage Exception Active Bit" /> + </Register> + <Register name="MMSR" start="0xE000ED28" size="1" description="MemManage Fault Status Register"> + <BitField name="MMARVALID" start="7" size="1" description="MemManage Fault Address Register(MMFAR) valid flag" /> + <BitField name="MSTKERR" start="4" size="1" description="MemManage fault on stacking for exception entry" /> + <BitField name="MUNSTKERR" start="3" size="1" description="MemManage fault on unstacking for a return from exception" /> + <BitField name="DACCVIOL" start="1" size="1" description="Data access violation flag" /> + <BitField name="IACCVIOL" start="0" size="1" description="Instruction access violation flag" /> + </Register> + <Register name="BFSR" start="0xE000ED29" size="1" description="BusFault Status Register"> + <BitField name="BFARVALID" start="7" size="1" description="BusFault Address Register(BFAR) valid flag" /> + <BitField name="STKERR" start="4" size="1" description="BusFault on stacking for exception entry" /> + <BitField name="UNSTKERR" start="3" size="1" description="BusFault on unstacking for a return from exception" /> + <BitField name="IMPRECISERR" start="2" size="1" description="Imprecise data bus error" /> + <BitField name="PRECISERR" start="1" size="1" description="Precise data bus error" /> + <BitField name="IBUSERR" start="0" size="1" description="Instruction bus error" /> + </Register> + <Register name="UFSR" start="0xE000ED2A" size="2" description="UsageFault Status Register"> + <BitField name="DIVBYZERO" start="9" size="1" description="Divide by zero UsageFault" /> + <BitField name="UNALIGNED" start="8" size="1" description="Unaligned access UsageFault" /> + <BitField name="NOCP" start="3" size="1" description="No coprocessor UsageFault" /> + <BitField name="INVPC" start="2" size="1" description="Invalid PC load UsageFault, causedby an invalid PC load by EXC_RETURN" /> + <BitField name="INVSTATE" start="1" size="1" description="Invalid state UsageFault" /> + <BitField name="UNDEFINSTR" start="0" size="1" description="Undefined instruction UsageFault" /> + </Register> + <Register name="HFSR" start="0xE000ED2C" description="HardFault Status Register"> + <BitField name="DEBUGEVT" start="31" size="1" description="" /> + <BitField name="FORCED" start="30" size="1" description="Indicates a forced hard fault, generated by escalation of a fault with configurable priority that cannot be handled, either because of priority or because it is disabled" /> + <BitField name="VECTTBL" start="1" size="1" description="Indicates a BusFault on a vectortable read during exception processing" /> + </Register> + <Register name="DFSR" start="0xE000ED30" description="Debug Fault Status Register"> + <BitField name="EXTERNAL" start="4" size="1" description="" /> + <BitField name="VCATCH" start="3" size="1" description="" /> + <BitField name="DWTTRAP" start="2" size="1" description="" /> + <BitField name="BKPT" start="1" size="1" description="" /> + <BitField name="HALTED" start="0" size="1" description="" /> + </Register> + <Register name="MMAR" start="0xE000ED34" description="MemManage Fault Address Register"> + <BitField name="ADDRESS" start="0" size="32" description="When the MMARVALID bit of the MMFSR is set to 1, this field holds the address of the location that generated the MemManage fault" /> + </Register> + <Register name="BFAR" start="0xE000ED38" description="BusFault Address Register"> + <BitField name="ADDRESS" start="0" size="32" description="When the BFARVALID bit of the BFSR is set to1, this field holds the address of the location that generated the BusFault" /> + </Register> + <Register name="AFSR" start="0xE000ED3C" description="Auxiliary Fault Status Register"> + <BitField name="IMPDEF" start="0" size="32" description="Implementation defined, the bits map to the AUXFAULT input signals" /> + </Register> + </RegisterGroup> +</Processor> diff --git a/examples/device/cdc_msc_hid/ses/lpc13xx/LPC13Uxx_Vectors.s b/examples/device/cdc_msc_hid/ses/lpc13xx/LPC13Uxx_Vectors.s new file mode 100644 index 000000000..1cbd4bb22 --- /dev/null +++ b/examples/device/cdc_msc_hid/ses/lpc13xx/LPC13Uxx_Vectors.s @@ -0,0 +1,342 @@ +/***************************************************************************** + * SEGGER Microcontroller GmbH & Co. KG * + * Solutions for real time microcontroller applications * + ***************************************************************************** + * * + * (c) 2017 SEGGER Microcontroller GmbH & Co. KG * + * * + * Internet: www.segger.com Support: [email protected] * + * * + *****************************************************************************/ + +/***************************************************************************** + * Preprocessor Definitions * + * ------------------------ * + * VECTORS_IN_RAM * + * * + * If defined, an area of RAM will large enough to store the vector table * + * will be reserved. * + * * + *****************************************************************************/ + + .syntax unified + .code 16 + + .section .init, "ax" + .align 0 + +/***************************************************************************** + * Default Exception Handlers * + *****************************************************************************/ + + .thumb_func + .weak NMI_Handler +NMI_Handler: + b . + + .thumb_func + .weak HardFault_Handler +HardFault_Handler: + b . + + .thumb_func + .weak SVC_Handler +SVC_Handler: + b . + + .thumb_func + .weak PendSV_Handler +PendSV_Handler: + b . + + .thumb_func + .weak SysTick_Handler +SysTick_Handler: + b . + + .thumb_func +Dummy_Handler: + b . + +#if defined(__OPTIMIZATION_SMALL) + + .weak PIN_INT0_IRQHandler + .thumb_set PIN_INT0_IRQHandler,Dummy_Handler + + .weak PIN_INT1_IRQHandler + .thumb_set PIN_INT1_IRQHandler,Dummy_Handler + + .weak PIN_INT2_IRQHandler + .thumb_set PIN_INT2_IRQHandler,Dummy_Handler + + .weak PIN_INT3_IRQHandler + .thumb_set PIN_INT3_IRQHandler,Dummy_Handler + + .weak PIN_INT4_IRQHandler + .thumb_set PIN_INT4_IRQHandler,Dummy_Handler + + .weak PIN_INT5_IRQHandler + .thumb_set PIN_INT5_IRQHandler,Dummy_Handler + + .weak PIN_INT6_IRQHandler + .thumb_set PIN_INT6_IRQHandler,Dummy_Handler + + .weak PIN_INT7_IRQHandler + .thumb_set PIN_INT7_IRQHandler,Dummy_Handler + + .weak GINT0_IRQHandler + .thumb_set GINT0_IRQHandler,Dummy_Handler + + .weak GINT1_IRQHandler + .thumb_set GINT1_IRQHandler,Dummy_Handler + + .weak RIT_IRQHandler + .thumb_set RIT_IRQHandler,Dummy_Handler + + .weak SSP1_IRQHandler + .thumb_set SSP1_IRQHandler,Dummy_Handler + + .weak I2C_IRQHandler + .thumb_set I2C_IRQHandler,Dummy_Handler + + .weak CT16B0_IRQHandler + .thumb_set CT16B0_IRQHandler,Dummy_Handler + + .weak CT16B1_IRQHandler + .thumb_set CT16B1_IRQHandler,Dummy_Handler + + .weak CT32B0_IRQHandler + .thumb_set CT32B0_IRQHandler,Dummy_Handler + + .weak CT32B1_IRQHandler + .thumb_set CT32B1_IRQHandler,Dummy_Handler + + .weak SSP0_IRQHandler + .thumb_set SSP0_IRQHandler,Dummy_Handler + + .weak USART_IRQHandler + .thumb_set USART_IRQHandler,Dummy_Handler + + .weak USB_IRQHandler + .thumb_set USB_IRQHandler,Dummy_Handler + + .weak USB_FIQ_IRQHandler + .thumb_set USB_FIQ_IRQHandler,Dummy_Handler + + .weak ADC_IRQHandler + .thumb_set ADC_IRQHandler,Dummy_Handler + + .weak WWDT_IRQHandler + .thumb_set WWDT_IRQHandler,Dummy_Handler + + .weak BOD_IRQHandler + .thumb_set BOD_IRQHandler,Dummy_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Dummy_Handler + + .weak USBWAKEUP_IRQHandler + .thumb_set USBWAKEUP_IRQHandler,Dummy_Handler + +#else + + .thumb_func + .weak PIN_INT0_IRQHandler +PIN_INT0_IRQHandler: + b . + + .thumb_func + .weak PIN_INT1_IRQHandler +PIN_INT1_IRQHandler: + b . + + .thumb_func + .weak PIN_INT2_IRQHandler +PIN_INT2_IRQHandler: + b . + + .thumb_func + .weak PIN_INT3_IRQHandler +PIN_INT3_IRQHandler: + b . + + .thumb_func + .weak PIN_INT4_IRQHandler +PIN_INT4_IRQHandler: + b . + + .thumb_func + .weak PIN_INT5_IRQHandler +PIN_INT5_IRQHandler: + b . + + .thumb_func + .weak PIN_INT6_IRQHandler +PIN_INT6_IRQHandler: + b . + + .thumb_func + .weak PIN_INT7_IRQHandler +PIN_INT7_IRQHandler: + b . + + .thumb_func + .weak GINT0_IRQHandler +GINT0_IRQHandler: + b . + + .thumb_func + .weak GINT1_IRQHandler +GINT1_IRQHandler: + b . + + .thumb_func + .weak RIT_IRQHandler +RIT_IRQHandler: + b . + + .thumb_func + .weak SSP1_IRQHandler +SSP1_IRQHandler: + b . + + .thumb_func + .weak I2C_IRQHandler +I2C_IRQHandler: + b . + + .thumb_func + .weak CT16B0_IRQHandler +CT16B0_IRQHandler: + b . + + .thumb_func + .weak CT16B1_IRQHandler +CT16B1_IRQHandler: + b . + + .thumb_func + .weak CT32B0_IRQHandler +CT32B0_IRQHandler: + b . + + .thumb_func + .weak CT32B1_IRQHandler +CT32B1_IRQHandler: + b . + + .thumb_func + .weak SSP0_IRQHandler +SSP0_IRQHandler: + b . + + .thumb_func + .weak USART_IRQHandler +USART_IRQHandler: + b . + + .thumb_func + .weak USB_IRQHandler +USB_IRQHandler: + b . + + .thumb_func + .weak USB_FIQ_IRQHandler +USB_FIQ_IRQHandler: + b . + + .thumb_func + .weak ADC_IRQHandler +ADC_IRQHandler: + b . + + .thumb_func + .weak WWDT_IRQHandler +WWDT_IRQHandler: + b . + + .thumb_func + .weak BOD_IRQHandler +BOD_IRQHandler: + b . + + .thumb_func + .weak FLASH_IRQHandler +FLASH_IRQHandler: + b . + + .thumb_func + .weak USBWAKEUP_IRQHandler +USBWAKEUP_IRQHandler: + b . + +#endif + +/***************************************************************************** + * Vector Table * + *****************************************************************************/ + + .section .vectors, "ax" + .align 0 + .global _vectors + .extern __stack_end__ + .extern Reset_Handler + +_vectors: + .word __stack_end__ + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word SVC_Handler + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word PendSV_Handler + .word SysTick_Handler + .word PIN_INT0_IRQHandler + .word PIN_INT1_IRQHandler + .word PIN_INT2_IRQHandler + .word PIN_INT3_IRQHandler + .word PIN_INT4_IRQHandler + .word PIN_INT5_IRQHandler + .word PIN_INT6_IRQHandler + .word PIN_INT7_IRQHandler + .word GINT0_IRQHandler + .word GINT1_IRQHandler + .word Dummy_Handler /* Reserved */ + .word Dummy_Handler /* Reserved */ + .word RIT_IRQHandler + .word Dummy_Handler /* Reserved */ + .word SSP1_IRQHandler + .word I2C_IRQHandler + .word CT16B0_IRQHandler + .word CT16B1_IRQHandler + .word CT32B0_IRQHandler + .word CT32B1_IRQHandler + .word SSP0_IRQHandler + .word USART_IRQHandler + .word USB_IRQHandler + .word USB_FIQ_IRQHandler + .word ADC_IRQHandler + .word WWDT_IRQHandler + .word BOD_IRQHandler + .word FLASH_IRQHandler + .word Dummy_Handler /* Reserved */ + .word Dummy_Handler /* Reserved */ + .word USBWAKEUP_IRQHandler +_vectors_end: + +#ifdef VECTORS_IN_RAM + .section .vectors_ram, "ax" + .align 0 + .global _vectors_ram + +_vectors_ram: + .space _vectors_end - _vectors, 0 +#endif diff --git a/examples/device/cdc_msc_hid/ses/lpc13xx/flash_placement.xml b/examples/device/cdc_msc_hid/ses/lpc13xx/flash_placement.xml new file mode 100644 index 000000000..27a63d5be --- /dev/null +++ b/examples/device/cdc_msc_hid/ses/lpc13xx/flash_placement.xml @@ -0,0 +1,41 @@ +<!DOCTYPE Linker_Placement_File> +<Root name="Flash Section Placement"> + <MemorySegment name="$(FLASH_NAME:FLASH)"> + <ProgramSection alignment="0x100" load="Yes" name=".vectors" start="$(FLASH_START:)" /> + <ProgramSection alignment="4" load="Yes" name=".init" /> + <ProgramSection alignment="4" load="Yes" name=".init_rodata" /> + <ProgramSection alignment="4" load="Yes" name=".text" /> + <ProgramSection alignment="4" load="Yes" name=".dtors" /> + <ProgramSection alignment="4" load="Yes" name=".ctors" /> + <ProgramSection alignment="4" load="Yes" name=".rodata" /> + <ProgramSection alignment="4" load="Yes" name=".ARM.exidx" address_symbol="__exidx_start" end_symbol="__exidx_end" /> + <ProgramSection alignment="4" load="Yes" runin=".fast_run" name=".fast" /> + <ProgramSection alignment="4" load="Yes" runin=".data_run" name=".data" /> + <ProgramSection alignment="4" load="Yes" runin=".tdata_run" name=".tdata" /> + </MemorySegment> + <MemorySegment name="$(RAM_NAME:RAM);SRAM"> + <ProgramSection alignment="0x100" load="No" name=".vectors_ram" start="$(RAM_START:$(SRAM_START:))" /> + <ProgramSection alignment="4" load="No" name=".fast_run" /> + <ProgramSection alignment="4" load="No" name=".data_run" /> + <ProgramSection alignment="4" load="No" name=".bss" /> + <ProgramSection alignment="4" load="No" name=".tbss" /> + <ProgramSection alignment="4" load="No" name=".tdata_run" /> + <ProgramSection alignment="4" load="No" name=".non_init" /> + <ProgramSection alignment="4" size="__HEAPSIZE__" load="No" name=".heap" /> + <ProgramSection alignment="8" size="__STACKSIZE__" load="No" place_from_segment_end="Yes" name=".stack" /> + <ProgramSection alignment="8" size="__STACKSIZE_PROCESS__" load="No" name=".stack_process" /> + </MemorySegment> + <MemorySegment name="$(FLASH2_NAME:FLASH2)"> + <ProgramSection alignment="4" load="Yes" name=".text2" /> + <ProgramSection alignment="4" load="Yes" name=".rodata2" /> + <ProgramSection alignment="4" load="Yes" runin=".data2_run" name=".data2" /> + </MemorySegment> + <MemorySegment name="$(RAM2_NAME:RAM2)"> + <ProgramSection alignment="4" load="No" name=".data2_run" /> + <ProgramSection alignment="4" load="No" name=".bss2" /> + </MemorySegment> + <MemorySegment name="$(RAM3_NAME:RAM3)"> + <ProgramSection alignment="4" load="No" name=".data3_run" /> + <ProgramSection alignment="4" load="No" name=".bss3" /> + </MemorySegment> +</Root> diff --git a/examples/device/cdc_msc_hid/ses/lpc13xx/lpc13xx.emProject b/examples/device/cdc_msc_hid/ses/lpc13xx/lpc13xx.emProject new file mode 100644 index 000000000..aa571424c --- /dev/null +++ b/examples/device/cdc_msc_hid/ses/lpc13xx/lpc13xx.emProject @@ -0,0 +1,116 @@ +<!DOCTYPE CrossStudio_Project_File> +<solution Name="lpc13xx" target="8" version="2"> + <project Name="lpc13xx"> + <configuration + Name="Common" + Placement="Flash" + Target="LPC1347FBD64" + arm_architecture="v7M" + arm_core_type="Cortex-M3" + arm_endian="Little" + arm_fpu_type="None" + arm_interwork="No" + arm_linker_heap_size="0" + arm_linker_process_stack_size="0" + arm_linker_stack_size="256" + arm_simulator_memory_simulation_parameter="ROM;0x00000000;0x00010000;RAM;0x10000000;0x00002000;RAM;0x20000000;0x00000800" + arm_target_debug_interface_type="ADIv5" + arm_target_device_name="LPC1347" + arm_target_interface_type="SWD" + build_treat_warnings_as_errors="Yes" + c_preprocessor_definitions="__LPC1347FBD64__;__LPC1300_FAMILY;__LPC134x_SUBFAMILY;ARM_MATH_CM3;FLASH_PLACEMENT=1;CORE_M3;BOARD_LPCXPRESSO1347;CFG_TUSB_MCU=OPT_MCU_LPC13XX;CFG_TUSB_MEM_SECTION= __attribute__((section(".bss3")));CFG_TUSB_MEM_ALIGN=__attribute__ ((aligned(64)))" + c_user_include_directories="../../src;$(rootDir)/hw;$(rootDir)/src;$(lpcDir)/inc" + debug_register_definition_file="$(ProjectDir)/LPC13Uxx_Registers.xml" + debug_target_connection="J-Link" + gcc_enable_all_warnings="Yes" + gcc_entry_point="Reset_Handler" + linker_memory_map_file="$(ProjectDir)/LPC1347FBD64_MemoryMap.xml" + linker_section_placement_file="$(ProjectDir)/flash_placement.xml" + macros="DeviceFamily=LPC1300;DeviceSubFamily=LPC134x;Target=LPC1347FBD64;Placement=Flash;rootDir=../../../../..;lpcDir=../../../../../hw/mcu/nxp/lpc_chip_13xx" + package_dependencies="LPC1300" + project_directory="" + project_type="Executable" + target_reset_script="Reset();" + target_trace_initialize_script="EnableTrace("$(TraceInterfaceType)")" /> + <folder Name="System Files"> + <file file_name="thumb_crt0.s" /> + <file file_name="LPC1300_Startup.s" /> + <file file_name="LPC13Uxx_Vectors.s"> + <configuration Name="Common" file_type="Assembly" /> + </file> + <file file_name="LPC1300_Target.js"> + <configuration Name="Common" file_type="Reset Script" /> + </file> + <file file_name="LPC1347FBD64_MemoryMap.xml" /> + <file file_name="flash_placement.xml" /> + </folder> + <configuration + Name="Debug" + link_use_linker_script_file="No" + linker_section_placement_file="flash_placement.xml" /> + <folder Name="hw"> + <folder Name="bsp"> + <file file_name="../../../../../hw/bsp/ansi_escape.h" /> + <file file_name="../../../../../hw/bsp/board.h" /> + <folder Name="lpcxpresso1347"> + <file file_name="../../../../../hw/bsp/lpcxpresso1347/board_lpcxpresso1347.c" /> + <file file_name="../../../../../hw/bsp/lpcxpresso1347/board_lpcxpresso1347.h" /> + </folder> + </folder> + <folder Name="mcu"> + <folder Name="nxp"> + <folder Name="lpc_chip_13xx"> + <folder Name="inc"> + <file file_name="../../../../../hw/mcu/nxp/lpc_chip_13xx/inc/chip.h" /> + <file file_name="../../../../../hw/mcu/nxp/lpc_chip_13xx/inc/clock_13xx.h" /> + <file file_name="../../../../../hw/mcu/nxp/lpc_chip_13xx/inc/cmsis.h" /> + <file file_name="../../../../../hw/mcu/nxp/lpc_chip_13xx/inc/cmsis_1347.h" /> + <file file_name="../../../../../hw/mcu/nxp/lpc_chip_13xx/inc/core_cm3.h" /> + <file file_name="../../../../../hw/mcu/nxp/lpc_chip_13xx/inc/core_cmFunc.h" /> + <file file_name="../../../../../hw/mcu/nxp/lpc_chip_13xx/inc/core_cmInstr.h" /> + <file file_name="../../../../../hw/mcu/nxp/lpc_chip_13xx/inc/gpio_13xx_1.h" /> + <file file_name="../../../../../hw/mcu/nxp/lpc_chip_13xx/inc/gpio_13xx_2.h" /> + <file file_name="../../../../../hw/mcu/nxp/lpc_chip_13xx/inc/iocon_13xx.h" /> + <file file_name="../../../../../hw/mcu/nxp/lpc_chip_13xx/inc/lpc_types.h" /> + <file file_name="../../../../../hw/mcu/nxp/lpc_chip_13xx/inc/sys_config.h" /> + <file file_name="../../../../../hw/mcu/nxp/lpc_chip_13xx/inc/sysctl_13xx.h" /> + <file file_name="../../../../../hw/mcu/nxp/lpc_chip_13xx/inc/uart_13xx.h" /> + </folder> + <folder Name="src"> + <file file_name="../../../../../hw/mcu/nxp/lpc_chip_13xx/src/chip_13xx.c" /> + <file file_name="../../../../../hw/mcu/nxp/lpc_chip_13xx/src/clock_13xx.c" /> + <file file_name="../../../../../hw/mcu/nxp/lpc_chip_13xx/src/gpio_13xx_1.c" /> + <file file_name="../../../../../hw/mcu/nxp/lpc_chip_13xx/src/sysctl_13xx.c" /> + <file file_name="../../../../../hw/mcu/nxp/lpc_chip_13xx/src/sysinit_13xx.c" /> + <file file_name="../../../../../hw/mcu/nxp/lpc_chip_13xx/src/uart_13xx.c" /> + <file file_name="../../../../../hw/mcu/nxp/lpc_chip_13xx/src/iocon_13xx.c" /> + </folder> + </folder> + </folder> + </folder> + </folder> + <folder + Name="src" + exclude="" + filter="*.c;*.h" + path="../../src" + recurse="Yes" /> + <folder + Name="tinyusb" + exclude="" + filter="*.c;*.h" + path="../../../../../src" + recurse="Yes" /> + <folder + Name="segger_rtt" + exclude="" + filter="*.c;*.h" + path="../../../../../lib/segger_rtt" + recurse="No" /> + </project> + <configuration + Name="LPCXpresso 1347" + c_preprocessor_definitions="DEBUG" + gcc_debugging_level="Level 3" + gcc_optimization_level="None" /> +</solution> diff --git a/examples/device/cdc_msc_hid/ses/lpc13xx/thumb_crt0.s b/examples/device/cdc_msc_hid/ses/lpc13xx/thumb_crt0.s new file mode 100644 index 000000000..17f88e0ca --- /dev/null +++ b/examples/device/cdc_msc_hid/ses/lpc13xx/thumb_crt0.s @@ -0,0 +1,415 @@ +// ********************************************************************** +// * SEGGER Microcontroller GmbH * +// * The Embedded Experts * +// ********************************************************************** +// * * +// * (c) 2014 - 2018 SEGGER Microcontroller GmbH * +// * (c) 2001 - 2018 Rowley Associates Limited * +// * * +// * www.segger.com Support: [email protected] * +// * * +// ********************************************************************** +// * * +// * All rights reserved. * +// * * +// * Redistribution and use in source and binary forms, with or * +// * without modification, are permitted provided that the following * +// * conditions are met: * +// * * +// * - Redistributions of source code must retain the above copyright * +// * notice, this list of conditions and the following disclaimer. * +// * * +// * - Neither the name of SEGGER Microcontroller GmbH * +// * nor the names of its contributors may be used to endorse or * +// * promote products derived from this software without specific * +// * prior written permission. * +// * * +// * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND * +// * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, * +// * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * +// * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * +// * DISCLAIMED. * +// * IN NO EVENT SHALL SEGGER Microcontroller GmbH BE LIABLE FOR * +// * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * +// * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT * +// * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * +// * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF * +// * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * +// * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE * +// * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH * +// * DAMAGE. * +// * * +// ********************************************************************** +// +// +// Preprocessor Definitions +// ------------------------ +// APP_ENTRY_POINT +// +// Defines the application entry point function, if undefined this setting +// defaults to "main". +// +// INITIALIZE_STACK +// +// If defined, the contents of the stack will be initialized to a the +// value 0xCC. +// +// INITIALIZE_SECONDARY_SECTIONS +// +// If defined, the .data2, .text2, .rodata2 and .bss2 sections will be initialized. +// +// INITIALIZE_TCM_SECTIONS +// +// If defined, the .data_tcm, .text_tcm, .rodata_tcm and .bss_tcm sections +// will be initialized. +// +// INITIALIZE_USER_SECTIONS +// +// If defined, the function InitializeUserMemorySections will be called prior +// to entering main in order to allow the user to initialize any user defined +// memory sections. +// +// FULL_LIBRARY +// +// If defined then +// - argc, argv are setup by the debug_getargs. +// - the exit symbol is defined and executes on return from main. +// - the exit symbol calls destructors, atexit functions and then debug_exit. +// +// If not defined then +// - argc and argv are zero. +// - the exit symbol is defined, executes on return from main and loops +// + +#ifndef APP_ENTRY_POINT +#define APP_ENTRY_POINT main +#endif + +#ifndef ARGSSPACE +#define ARGSSPACE 128 +#endif + .syntax unified + + .global _start + .extern APP_ENTRY_POINT + .global exit + .weak exit + +#ifdef INITIALIZE_USER_SECTIONS + .extern InitializeUserMemorySections +#endif + + .section .init, "ax" + .code 16 + .balign 2 + .thumb_func + +_start: + /* Set up main stack if size > 0 */ + ldr r1, =__stack_end__ + ldr r0, =__stack_start__ + subs r2, r1, r0 + beq 1f +#ifdef __ARM_EABI__ + movs r2, #0x7 + bics r1, r2 +#endif + mov sp, r1 +#ifdef INITIALIZE_STACK + movs r2, #0xCC + ldr r0, =__stack_start__ + bl memory_set +#endif +1: + + /* Set up process stack if size > 0 */ + ldr r1, =__stack_process_end__ + ldr r0, =__stack_process_start__ + subs r2, r1, r0 + beq 1f +#ifdef __ARM_EABI__ + movs r2, #0x7 + bics r1, r2 +#endif + msr psp, r1 + movs r2, #2 + msr control, r2 +#ifdef INITIALIZE_STACK + movs r2, #0xCC + bl memory_set +#endif +1: + + /* Copy initialized memory sections into RAM (if necessary). */ + ldr r0, =__data_load_start__ + ldr r1, =__data_start__ + ldr r2, =__data_end__ + bl memory_copy + ldr r0, =__text_load_start__ + ldr r1, =__text_start__ + ldr r2, =__text_end__ + bl memory_copy + ldr r0, =__fast_load_start__ + ldr r1, =__fast_start__ + ldr r2, =__fast_end__ + bl memory_copy + ldr r0, =__ctors_load_start__ + ldr r1, =__ctors_start__ + ldr r2, =__ctors_end__ + bl memory_copy + ldr r0, =__dtors_load_start__ + ldr r1, =__dtors_start__ + ldr r2, =__dtors_end__ + bl memory_copy + ldr r0, =__rodata_load_start__ + ldr r1, =__rodata_start__ + ldr r2, =__rodata_end__ + bl memory_copy + ldr r0, =__tdata_load_start__ + ldr r1, =__tdata_start__ + ldr r2, =__tdata_end__ + bl memory_copy +#ifdef INITIALIZE_SECONDARY_SECTIONS + ldr r0, =__data2_load_start__ + ldr r1, =__data2_start__ + ldr r2, =__data2_end__ + bl memory_copy + ldr r0, =__text2_load_start__ + ldr r1, =__text2_start__ + ldr r2, =__text2_end__ + bl memory_copy + ldr r0, =__rodata2_load_start__ + ldr r1, =__rodata2_start__ + ldr r2, =__rodata2_end__ + bl memory_copy +#endif /* #ifdef INITIALIZE_SECONDARY_SECTIONS */ +#ifdef INITIALIZE_TCM_SECTIONS + ldr r0, =__data_tcm_load_start__ + ldr r1, =__data_tcm_start__ + ldr r2, =__data_tcm_end__ + bl memory_copy + ldr r0, =__text_tcm_load_start__ + ldr r1, =__text_tcm_start__ + ldr r2, =__text_tcm_end__ + bl memory_copy + ldr r0, =__rodata_tcm_load_start__ + ldr r1, =__rodata_tcm_start__ + ldr r2, =__rodata_tcm_end__ + bl memory_copy +#endif /* #ifdef INITIALIZE_TCM_SECTIONS */ + + /* Zero the bss. */ + ldr r0, =__bss_start__ + ldr r1, =__bss_end__ + movs r2, #0 + bl memory_set + ldr r0, =__tbss_start__ + ldr r1, =__tbss_end__ + movs r2, #0 + bl memory_set +#ifdef INITIALIZE_SECONDARY_SECTIONS + ldr r0, =__bss2_start__ + ldr r1, =__bss2_end__ + mov r2, #0 + bl memory_set +#endif /* #ifdef INITIALIZE_SECONDARY_SECTIONS */ +#ifdef INITIALIZE_TCM_SECTIONS + ldr r0, =__bss_tcm_start__ + ldr r1, =__bss_tcm_end__ + mov r2, #0 + bl memory_set +#endif /* #ifdef INITIALIZE_TCM_SECTIONS */ + + /* Initialize the heap */ + ldr r0, = __heap_start__ + ldr r1, = __heap_end__ + subs r1, r1, r0 + cmp r1, #8 + blt 1f + movs r2, #0 + str r2, [r0] + adds r0, r0, #4 + str r1, [r0] +1: + +#ifdef INITIALIZE_USER_SECTIONS + ldr r2, =InitializeUserMemorySections + blx r2 +#endif + + /* Call constructors */ + ldr r0, =__ctors_start__ + ldr r1, =__ctors_end__ +ctor_loop: + cmp r0, r1 + beq ctor_end + ldr r2, [r0] + adds r0, #4 + push {r0-r1} + blx r2 + pop {r0-r1} + b ctor_loop +ctor_end: + + /* Setup initial call frame */ + movs r0, #0 + mov lr, r0 + mov r12, sp + + .type start, function +start: + /* Jump to application entry point */ +#ifdef FULL_LIBRARY + movs r0, #ARGSSPACE + ldr r1, =args + ldr r2, =debug_getargs + blx r2 + ldr r1, =args +#else + movs r0, #0 + movs r1, #0 +#endif + ldr r2, =APP_ENTRY_POINT + blx r2 + + .thumb_func +exit: +#ifdef FULL_LIBRARY + mov r5, r0 // save the exit parameter/return result + + /* Call destructors */ + ldr r0, =__dtors_start__ + ldr r1, =__dtors_end__ +dtor_loop: + cmp r0, r1 + beq dtor_end + ldr r2, [r0] + add r0, #4 + push {r0-r1} + blx r2 + pop {r0-r1} + b dtor_loop +dtor_end: + + /* Call atexit functions */ + ldr r2, =_execute_at_exit_fns + blx r2 + + /* Call debug_exit with return result/exit parameter */ + mov r0, r5 + ldr r2, =debug_exit + blx r2 +#endif + + /* Returned from application entry point, loop forever. */ +exit_loop: + b exit_loop + + .thumb_func +memory_copy: + cmp r0, r1 + beq 2f + subs r2, r2, r1 + beq 2f +1: + ldrb r3, [r0] + adds r0, r0, #1 + strb r3, [r1] + adds r1, r1, #1 + subs r2, r2, #1 + bne 1b +2: + bx lr + + .thumb_func +memory_set: + cmp r0, r1 + beq 1f + strb r2, [r0] + adds r0, r0, #1 + b memory_set +1: + bx lr + + // default C/C++ library helpers + +.macro HELPER helper_name + .section .text.\helper_name, "ax", %progbits + .balign 2 + .global \helper_name + .weak \helper_name +\helper_name: + .thumb_func +.endm + +.macro JUMPTO name +#if defined(__thumb__) && !defined(__thumb2__) + mov r12, r0 + ldr r0, =\name + push {r0} + mov r0, r12 + pop {pc} +#else + b \name +#endif +.endm + +HELPER __aeabi_read_tp + ldr r0, =__tbss_start__-8 + bx lr +HELPER abort + b . +HELPER __assert + b . +HELPER __aeabi_assert + b . +HELPER __sync_synchronize + bx lr +HELPER __getchar + JUMPTO debug_getchar +HELPER __putchar + JUMPTO debug_putchar +HELPER __open + JUMPTO debug_fopen +HELPER __close + JUMPTO debug_fclose +HELPER __write + mov r3, r0 + mov r0, r1 + movs r1, #1 + JUMPTO debug_fwrite +HELPER __read + mov r3, r0 + mov r0, r1 + movs r1, #1 + JUMPTO debug_fread +HELPER __seek + push {r4, lr} + mov r4, r0 + bl debug_fseek + cmp r0, #0 + bne 1f + mov r0, r4 + bl debug_ftell + pop {r4, pc} +1: + ldr r0, =-1 + pop {r4, pc} + // char __user_locale_name_buffer[]; + .section .bss.__user_locale_name_buffer, "aw", %nobits + .global __user_locale_name_buffer + .weak __user_locale_name_buffer + __user_locale_name_buffer: + .word 0x0 + +#ifdef FULL_LIBRARY + .bss +args: + .space ARGSSPACE +#endif + + /* Setup attibutes of stack and heap sections so they don't take up room in the elf file */ + .section .stack, "wa", %nobits + .section .stack_process, "wa", %nobits + .section .heap, "wa", %nobits + diff --git a/examples/device/cdc_msc_hid/ses/lpc175x_6x/LPC1700_Startup.s b/examples/device/cdc_msc_hid/ses/lpc175x_6x/LPC1700_Startup.s new file mode 100644 index 000000000..f039ad934 --- /dev/null +++ b/examples/device/cdc_msc_hid/ses/lpc175x_6x/LPC1700_Startup.s @@ -0,0 +1,109 @@ +/***************************************************************************** + * SEGGER Microcontroller GmbH & Co. KG * + * Solutions for real time microcontroller applications * + ***************************************************************************** + * * + * (c) 2015 SEGGER Microcontroller GmbH & Co. KG * + * * + * Internet: www.segger.com Support: [email protected] * + * * + *****************************************************************************/ + +/***************************************************************************** + * Preprocessor Definitions * + * ------------------------ * + * NO_STACK_INIT * + * * + * If defined, the stack pointer will not be initialised. * + * * + * NO_SYSTEM_INIT * + * * + * If defined, the SystemInit() function will not be called. By default * + * SystemInit() is called after reset to enable the clocks and memories to * + * be initialised prior to any C startup initialisation. * + * * + * NO_VTOR_CONFIG * + * * + * If defined, the vector table offset register will not be configured. * + * * + * MEMORY_INIT * + * * + * If defined, the MemoryInit() function will be called. By default * + * MemoryInit() is called after SystemInit() to enable an external memory * + * controller. * + * * + * STACK_INIT_VAL * + * * + * If defined, specifies the initial stack pointer value. If undefined, * + * the stack pointer will be initialised to point to the end of the * + * RAM segment. * + * * + * VECTORS_IN_RAM * + * * + * If defined, the exception vectors will be copied from Flash to RAM. * + * * + *****************************************************************************/ + + .syntax unified + + .global Reset_Handler + .extern _vectors + + .section .init, "ax" + .thumb_func + + .equ VTOR_REG, 0xE000ED08 + +#ifndef STACK_INIT_VAL +#define STACK_INIT_VAL __RAM_segment_end__ +#endif + +Reset_Handler: +#ifndef NO_STACK_INIT + /* Initialise main stack */ + ldr r0, =STACK_INIT_VAL + bic r0, #0x7 + mov sp, r0 +#endif +#ifndef NO_SYSTEM_INIT + /* Initialise system */ + ldr r0, =SystemInit + blx r0 +#endif + +#ifdef MEMORY_INIT + ldr r0, =MemoryInit + blx r0 +#endif + +#ifdef VECTORS_IN_RAM + /* Copy exception vectors into RAM */ + ldr r0, =__vectors_start__ + ldr r1, =__vectors_end__ + ldr r2, =__vectors_ram_start__ +1: + cmp r0, r1 + beq 2f + ldr r3, [r0] + str r3, [r2] + adds r0, r0, #4 + adds r2, r2, #4 + b 1b +2: +#endif + +#ifndef NO_VTOR_CONFIG + /* Configure vector table offset register */ + ldr r0, =VTOR_REG +#ifdef VECTORS_IN_RAM + ldr r1, =_vectors_ram +#else + ldr r1, =_vectors +#endif + str r1, [r0] +#endif + + /* Jump to program start */ + b _start + + diff --git a/examples/device/cdc_msc_hid/ses/lpc175x_6x/LPC1700_Target.js b/examples/device/cdc_msc_hid/ses/lpc175x_6x/LPC1700_Target.js new file mode 100644 index 000000000..7f945a3d2 --- /dev/null +++ b/examples/device/cdc_msc_hid/ses/lpc175x_6x/LPC1700_Target.js @@ -0,0 +1,19 @@ +/***************************************************************************** + * SEGGER Microcontroller GmbH & Co. KG * + * Solutions for real time microcontroller applications * + ***************************************************************************** + * * + * (c) 2015 SEGGER Microcontroller GmbH & Co. KG * + * * + * Internet: www.segger.com Support: [email protected] * + * * + *****************************************************************************/ + +function Reset() { + TargetInterface.resetAndStop(); +} + +function EnableTrace(traceInterfaceType) { + // TODO: Enable trace +} + diff --git a/examples/device/cdc_msc_hid/ses/lpc175x_6x/LPC1769_MemoryMap.xml b/examples/device/cdc_msc_hid/ses/lpc175x_6x/LPC1769_MemoryMap.xml new file mode 100644 index 000000000..d9c07aea3 --- /dev/null +++ b/examples/device/cdc_msc_hid/ses/lpc175x_6x/LPC1769_MemoryMap.xml @@ -0,0 +1,6 @@ +<!DOCTYPE Board_Memory_Definition_File> +<root name="LPC1769"> + <MemorySegment name="FLASH" start="0x00000000" size="0x00080000" access="ReadOnly" /> + <MemorySegment name="RAM" start="0x10000000" size="0x00008000" access="Read/Write" /> + <MemorySegment name="RAM2" start="0x2007C000" size="0x00008000" access="Read/Write" /> +</root> diff --git a/examples/device/cdc_msc_hid/ses/lpc175x_6x/LPC176x5x_Registers.xml b/examples/device/cdc_msc_hid/ses/lpc175x_6x/LPC176x5x_Registers.xml new file mode 100644 index 000000000..fd38966b8 --- /dev/null +++ b/examples/device/cdc_msc_hid/ses/lpc175x_6x/LPC176x5x_Registers.xml @@ -0,0 +1,11058 @@ +<!DOCTYPE Register_Definition_File> +<Processor name="LPC176x5x" description="LPC176x/LPC175x M3"> + <RegisterGroup name="WDT" start="0x40000000" description="Watchdog Timer (WDT) "> + <Register start="+0x000" size="4" name="MOD" access="Read/Write" description="Watchdog mode register. This register determines the basic mode and status of the Watchdog Timer." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="WDEN" description="Watchdog enable bit. This bit is Set Only."> + <Enum name="STOP" start="0" description="The watchdog timer is stopped." /> + <Enum name="RUN" start="1" description="The watchdog timer is running." /> + </BitField> + <BitField start="1" size="1" name="WDRESET" description="Watchdog reset enable bit. This bit is Set Only. See Table 652."> + <Enum name="NORESET" start="0" description="A watchdog timeout will not cause a chip reset." /> + <Enum name="RESET" start="1" description="A watchdog timeout will cause a chip reset." /> + </BitField> + <BitField start="2" size="1" name="WDTOF" description="Watchdog time-out flag. Set when the watchdog timer times out, cleared by software." /> + <BitField start="3" size="1" name="WDINT" description="Watchdog interrupt flag. Cleared by software." /> + <BitField start="4" size="28" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x004" size="4" name="TC" access="Read/Write" description="Watchdog timer constant register. The value in this register determines the time-out value." reset_value="0xFF" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="Count" description="Watchdog time-out interval." /> + </Register> + <Register start="+0x008" size="4" name="FEED" access="WriteOnly" description="Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in WDTC." reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="8" name="Feed" description="Feed value should be 0xAA followed by 0x55." /> + </Register> + <Register start="+0x00C" size="4" name="TV" access="ReadOnly" description="Watchdog timer value register. This register reads out the current value of the Watchdog timer." reset_value="0xFF" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="Count" description="Counter timer value." /> + </Register> + <Register start="+0x010" size="4" name="CLKSEL" access="Read/Write" description="Watchdog clock select register." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="CLKSEL" description="Selects source of WDT clock"> + <Enum name="IRC" start="0x0" description="IRC" /> + <Enum name="PCLK" start="0x1" description="Peripheral clock" /> + <Enum name="RTCOSC" start="0x2" description="RTC oscillator" /> + </BitField> + <BitField start="1" size="30" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + <BitField start="31" size="1" name="LOCK" description="If this bit is set to one writing to this register does not affect bit 0. The clock source can only be changed by first clearing this bit, then writing the new value of bit 0."> + <Enum name="UNLOCKED" start="0" description="This bit is set to 0 on any reset. It cannot be cleared by software." /> + <Enum name="LOCKED" start="1" description="Software can set this bit to 1 at any time. Once WDLOCK is set, the bits of this register
										cannot be modified." /> + </BitField> + </Register> + </RegisterGroup> + <RegisterGroup name="TIMER0" start="0x40004000" description="Timer0/1/2/3 "> + <Register start="+0x000" size="4" name="IR" access="Read/Write" description="Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="MR0INT" description="Interrupt flag for match channel 0." /> + <BitField start="1" size="1" name="MR1INT" description="Interrupt flag for match channel 1." /> + <BitField start="2" size="1" name="MR2INT" description="Interrupt flag for match channel 2." /> + <BitField start="3" size="1" name="MR3INT" description="Interrupt flag for match channel 3." /> + <BitField start="4" size="1" name="CR0INT" description="Interrupt flag for capture channel 0 event." /> + <BitField start="5" size="1" name="CR1INT" description="Interrupt flag for capture channel 1 event." /> + <BitField start="6" size="26" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x004" size="4" name="TCR" access="Read/Write" description="Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="CEN" description="When one, the Timer Counter and Prescale Counter are enabled for counting. When zero, the counters are disabled." /> + <BitField start="1" size="1" name="CRST" description="When one, the Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero." /> + <BitField start="2" size="30" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x008" size="4" name="TC" access="Read/Write" description="Timer Counter. The 32 bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="TC" description="Timer counter value." /> + </Register> + <Register start="+0x00C" size="4" name="PR" access="Read/Write" description="Prescale Register. When the Prescale Counter (PC) is equal to this value, the next clock increments the TC and clears the PC." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="PM" description="Prescale counter maximum value." /> + </Register> + <Register start="+0x010" size="4" name="PC" access="Read/Write" description="Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="PC" description="Prescale counter value." /> + </Register> + <Register start="+0x014" size="4" name="MCR" access="Read/Write" description="Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="MR0I" description="Interrupt on MR0"> + <Enum name="INTERRUPT_IS_GENERAT" start="1" description="Interrupt is generated when MR0 matches the value in the TC." /> + <Enum name="INTERRUPT_IS_DISABLE" start="0" description="Interrupt is disabled" /> + </BitField> + <BitField start="1" size="1" name="MR0R" description="Reset on MR0"> + <Enum name="TC_WILL_BE_RESET_IF_" start="1" description="TC will be reset if MR0 matches it." /> + <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." /> + </BitField> + <BitField start="2" size="1" name="MR0S" description="Stop on MR0"> + <Enum name="TC_AND_PC_WILL_BE_ST" start="1" description="TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC." /> + <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." /> + </BitField> + <BitField start="3" size="1" name="MR1I" description="Interrupt on MR1"> + <Enum name="INTERRUPT_IS_GENERAT" start="1" description="Interrupt is generated when MR1 matches the value in the TC." /> + <Enum name="INTERRUPT_IS_DISABLE" start="0" description="Interrupt is disabled." /> + </BitField> + <BitField start="4" size="1" name="MR1R" description="Reset on MR1"> + <Enum name="TC_WILL_BE_RESET_IF_" start="1" description="TC will be reset if MR1 matches it." /> + <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." /> + </BitField> + <BitField start="5" size="1" name="MR1S" description="Stop on MR1"> + <Enum name="TC_AND_PC_WILL_BE_ST" start="1" description="TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC." /> + <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." /> + </BitField> + <BitField start="6" size="1" name="MR2I" description="Interrupt on MR2"> + <Enum name="INTERRUPT_IS_GENERAT" start="1" description="Interrupt is generated when MR2 matches the value in the TC." /> + <Enum name="INTERRUPT_IS_DISABLE" start="0" description="Interrupt is disabled" /> + </BitField> + <BitField start="7" size="1" name="MR2R" description="Reset on MR2"> + <Enum name="TC_WILL_BE_RESET_IF_" start="1" description="TC will be reset if MR2 matches it." /> + <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." /> + </BitField> + <BitField start="8" size="1" name="MR2S" description="Stop on MR2."> + <Enum name="TC_AND_PC_WILL_BE_ST" start="1" description="TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC" /> + <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." /> + </BitField> + <BitField start="9" size="1" name="MR3I" description="Interrupt on MR3"> + <Enum name="INTERRUPT_IS_GENERAT" start="1" description="Interrupt is generated when MR3 matches the value in the TC." /> + <Enum name="THIS_INTERRUPT_IS_DI" start="0" description="This interrupt is disabled" /> + </BitField> + <BitField start="10" size="1" name="MR3R" description="Reset on MR3"> + <Enum name="TC_WILL_BE_RESET_IF_" start="1" description="TC will be reset if MR3 matches it." /> + <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." /> + </BitField> + <BitField start="11" size="1" name="MR3S" description="Stop on MR3"> + <Enum name="TC_AND_PC_WILL_BE_ST" start="1" description="TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC." /> + <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." /> + </BitField> + <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x018+0" size="4" name="MR[0]" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="MATCH" description="Timer counter match value." /> + </Register> + <Register start="+0x018+4" size="4" name="MR[1]" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="MATCH" description="Timer counter match value." /> + </Register> + <Register start="+0x018+8" size="4" name="MR[2]" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="MATCH" description="Timer counter match value." /> + </Register> + <Register start="+0x018+12" size="4" name="MR[3]" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="MATCH" description="Timer counter match value." /> + </Register> + <Register start="+0x028" size="4" name="CCR" access="Read/Write" description="Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="CAP0RE" description="Capture on CAPn.0 rising edge"> + <Enum name="ENABLE" start="1" description="A sequence of 0 then 1 on CAPn.0 will cause CR0 to be loaded with the contents of TC." /> + <Enum name="DISABLE" start="0" description="This feature is disabled." /> + </BitField> + <BitField start="1" size="1" name="CAP0FE" description="Capture on CAPn.0 falling edge"> + <Enum name="ENABLE" start="1" description="A sequence of 1 then 0 on CAPn.0 will cause CR0 to be loaded with the contents of TC." /> + <Enum name="DISABLE" start="0" description="This feature is disabled." /> + </BitField> + <BitField start="2" size="1" name="CAP0I" description="Interrupt on CAPn.0 event"> + <Enum name="ENABLE" start="1" description="A CR0 load due to a CAPn.0 event will generate an interrupt." /> + <Enum name="DISABLE" start="0" description="This feature is disabled." /> + </BitField> + <BitField start="3" size="1" name="CAP1RE" description="Capture on CAPn.1 rising edge"> + <Enum name="ENABLE" start="1" description="A sequence of 0 then 1 on CAPn.1 will cause CR1 to be loaded with the contents of TC." /> + <Enum name="DISABLE" start="0" description="This feature is disabled." /> + </BitField> + <BitField start="4" size="1" name="CAP1FE" description="Capture on CAPn.1 falling edge"> + <Enum name="ENABLE" start="1" description="A sequence of 1 then 0 on CAPn.1 will cause CR1 to be loaded with the contents of TC." /> + <Enum name="DISABLE" start="0" description="This feature is disabled." /> + </BitField> + <BitField start="5" size="1" name="CAP1I" description="Interrupt on CAPn.1 event"> + <Enum name="ENABLE" start="1" description="A CR1 load due to a CAPn.1 event will generate an interrupt." /> + <Enum name="DISABLE" start="0" description="This feature is disabled." /> + </BitField> + <BitField start="6" size="26" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x02C+0" size="4" name="CR[0]" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CAP" description="Timer counter capture value." /> + </Register> + <Register start="+0x02C+4" size="4" name="CR[1]" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CAP" description="Timer counter capture value." /> + </Register> + <Register start="+0x03C" size="4" name="EMR" access="Read/Write" description="External Match Register. The EMR controls the external match pins." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="EM0" description="External Match 0. When a match occurs between the TC and MR0, this bit can either toggle, go low, go high, or do nothing, depending on bits 5:4 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." /> + <BitField start="1" size="1" name="EM1" description="External Match 1. When a match occurs between the TC and MR1, this bit can either toggle, go low, go high, or do nothing, depending on bits 7:6 of this register. This bit can be driven onto a MATn.1 pin, in a positive-logic manner (0 = low, 1 = high)." /> + <BitField start="2" size="1" name="EM2" description="External Match 2. When a match occurs between the TC and MR2, this bit can either toggle, go low, go high, or do nothing, depending on bits 9:8 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." /> + <BitField start="3" size="1" name="EM3" description="External Match 3. When a match occurs between the TC and MR3, this bit can either toggle, go low, go high, or do nothing, depending on bits 11:10 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." /> + <BitField start="4" size="2" name="EMC0" description="External Match Control 0. Determines the functionality of External Match 0."> + <Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." /> + <Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." /> + <Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." /> + <Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." /> + </BitField> + <BitField start="6" size="2" name="EMC1" description="External Match Control 1. Determines the functionality of External Match 1."> + <Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." /> + <Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." /> + <Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." /> + <Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." /> + </BitField> + <BitField start="8" size="2" name="EMC2" description="External Match Control 2. Determines the functionality of External Match 2."> + <Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." /> + <Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." /> + <Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." /> + <Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." /> + </BitField> + <BitField start="10" size="2" name="EMC3" description="External Match Control 3. Determines the functionality of External Match 3."> + <Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." /> + <Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." /> + <Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." /> + <Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." /> + </BitField> + <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x070" size="4" name="CTCR" access="Read/Write" description="Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="CTMODE" description="Counter/Timer Mode This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale Register."> + <Enum name="TIMER_MODE_EVERY_RI" start="0x0" description="Timer Mode: every rising PCLK edge" /> + <Enum name="RISING" start="0x1" description="Counter Mode: TC is incremented on rising edges on the CAP input selected by bits 3:2." /> + <Enum name="FALLING" start="0x2" description="Counter Mode: TC is incremented on falling edges on the CAP input selected by bits 3:2." /> + <Enum name="DUALEDGE" start="0x3" description="Counter Mode: TC is incremented on both edges on the CAP input selected by bits 3:2." /> + </BitField> + <BitField start="2" size="2" name="CINSEL" description="Count Input Select When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the TnCTCR, the 3 bits for that input in the Capture Control Register (TnCCR) must be programmed as 000. However, capture and/or interrupt can be selected for the other 3 CAPn inputs in the same timer."> + <Enum name="CAPN_0_FOR_TIMERN" start="0x0" description="CAPn.0 for TIMERn" /> + <Enum name="CAPN_1_FOR_TIMERN" start="0x1" description="CAPn.1 for TIMERn" /> + </BitField> + <BitField start="4" size="28" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + </RegisterGroup> + <RegisterGroup name="TIMER1" start="0x40008000" description="Timer0/1/2/3 "> + <Register start="+0x000" size="4" name="IR" access="Read/Write" description="Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="MR0INT" description="Interrupt flag for match channel 0." /> + <BitField start="1" size="1" name="MR1INT" description="Interrupt flag for match channel 1." /> + <BitField start="2" size="1" name="MR2INT" description="Interrupt flag for match channel 2." /> + <BitField start="3" size="1" name="MR3INT" description="Interrupt flag for match channel 3." /> + <BitField start="4" size="1" name="CR0INT" description="Interrupt flag for capture channel 0 event." /> + <BitField start="5" size="1" name="CR1INT" description="Interrupt flag for capture channel 1 event." /> + <BitField start="6" size="26" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x004" size="4" name="TCR" access="Read/Write" description="Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="CEN" description="When one, the Timer Counter and Prescale Counter are enabled for counting. When zero, the counters are disabled." /> + <BitField start="1" size="1" name="CRST" description="When one, the Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero." /> + <BitField start="2" size="30" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x008" size="4" name="TC" access="Read/Write" description="Timer Counter. The 32 bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="TC" description="Timer counter value." /> + </Register> + <Register start="+0x00C" size="4" name="PR" access="Read/Write" description="Prescale Register. When the Prescale Counter (PC) is equal to this value, the next clock increments the TC and clears the PC." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="PM" description="Prescale counter maximum value." /> + </Register> + <Register start="+0x010" size="4" name="PC" access="Read/Write" description="Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="PC" description="Prescale counter value." /> + </Register> + <Register start="+0x014" size="4" name="MCR" access="Read/Write" description="Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="MR0I" description="Interrupt on MR0"> + <Enum name="INTERRUPT_IS_GENERAT" start="1" description="Interrupt is generated when MR0 matches the value in the TC." /> + <Enum name="INTERRUPT_IS_DISABLE" start="0" description="Interrupt is disabled" /> + </BitField> + <BitField start="1" size="1" name="MR0R" description="Reset on MR0"> + <Enum name="TC_WILL_BE_RESET_IF_" start="1" description="TC will be reset if MR0 matches it." /> + <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." /> + </BitField> + <BitField start="2" size="1" name="MR0S" description="Stop on MR0"> + <Enum name="TC_AND_PC_WILL_BE_ST" start="1" description="TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC." /> + <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." /> + </BitField> + <BitField start="3" size="1" name="MR1I" description="Interrupt on MR1"> + <Enum name="INTERRUPT_IS_GENERAT" start="1" description="Interrupt is generated when MR1 matches the value in the TC." /> + <Enum name="INTERRUPT_IS_DISABLE" start="0" description="Interrupt is disabled." /> + </BitField> + <BitField start="4" size="1" name="MR1R" description="Reset on MR1"> + <Enum name="TC_WILL_BE_RESET_IF_" start="1" description="TC will be reset if MR1 matches it." /> + <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." /> + </BitField> + <BitField start="5" size="1" name="MR1S" description="Stop on MR1"> + <Enum name="TC_AND_PC_WILL_BE_ST" start="1" description="TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC." /> + <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." /> + </BitField> + <BitField start="6" size="1" name="MR2I" description="Interrupt on MR2"> + <Enum name="INTERRUPT_IS_GENERAT" start="1" description="Interrupt is generated when MR2 matches the value in the TC." /> + <Enum name="INTERRUPT_IS_DISABLE" start="0" description="Interrupt is disabled" /> + </BitField> + <BitField start="7" size="1" name="MR2R" description="Reset on MR2"> + <Enum name="TC_WILL_BE_RESET_IF_" start="1" description="TC will be reset if MR2 matches it." /> + <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." /> + </BitField> + <BitField start="8" size="1" name="MR2S" description="Stop on MR2."> + <Enum name="TC_AND_PC_WILL_BE_ST" start="1" description="TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC" /> + <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." /> + </BitField> + <BitField start="9" size="1" name="MR3I" description="Interrupt on MR3"> + <Enum name="INTERRUPT_IS_GENERAT" start="1" description="Interrupt is generated when MR3 matches the value in the TC." /> + <Enum name="THIS_INTERRUPT_IS_DI" start="0" description="This interrupt is disabled" /> + </BitField> + <BitField start="10" size="1" name="MR3R" description="Reset on MR3"> + <Enum name="TC_WILL_BE_RESET_IF_" start="1" description="TC will be reset if MR3 matches it." /> + <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." /> + </BitField> + <BitField start="11" size="1" name="MR3S" description="Stop on MR3"> + <Enum name="TC_AND_PC_WILL_BE_ST" start="1" description="TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC." /> + <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." /> + </BitField> + <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x018+0" size="4" name="MR[0]" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="MATCH" description="Timer counter match value." /> + </Register> + <Register start="+0x018+4" size="4" name="MR[1]" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="MATCH" description="Timer counter match value." /> + </Register> + <Register start="+0x018+8" size="4" name="MR[2]" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="MATCH" description="Timer counter match value." /> + </Register> + <Register start="+0x018+12" size="4" name="MR[3]" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="MATCH" description="Timer counter match value." /> + </Register> + <Register start="+0x028" size="4" name="CCR" access="Read/Write" description="Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="CAP0RE" description="Capture on CAPn.0 rising edge"> + <Enum name="ENABLE" start="1" description="A sequence of 0 then 1 on CAPn.0 will cause CR0 to be loaded with the contents of TC." /> + <Enum name="DISABLE" start="0" description="This feature is disabled." /> + </BitField> + <BitField start="1" size="1" name="CAP0FE" description="Capture on CAPn.0 falling edge"> + <Enum name="ENABLE" start="1" description="A sequence of 1 then 0 on CAPn.0 will cause CR0 to be loaded with the contents of TC." /> + <Enum name="DISABLE" start="0" description="This feature is disabled." /> + </BitField> + <BitField start="2" size="1" name="CAP0I" description="Interrupt on CAPn.0 event"> + <Enum name="ENABLE" start="1" description="A CR0 load due to a CAPn.0 event will generate an interrupt." /> + <Enum name="DISABLE" start="0" description="This feature is disabled." /> + </BitField> + <BitField start="3" size="1" name="CAP1RE" description="Capture on CAPn.1 rising edge"> + <Enum name="ENABLE" start="1" description="A sequence of 0 then 1 on CAPn.1 will cause CR1 to be loaded with the contents of TC." /> + <Enum name="DISABLE" start="0" description="This feature is disabled." /> + </BitField> + <BitField start="4" size="1" name="CAP1FE" description="Capture on CAPn.1 falling edge"> + <Enum name="ENABLE" start="1" description="A sequence of 1 then 0 on CAPn.1 will cause CR1 to be loaded with the contents of TC." /> + <Enum name="DISABLE" start="0" description="This feature is disabled." /> + </BitField> + <BitField start="5" size="1" name="CAP1I" description="Interrupt on CAPn.1 event"> + <Enum name="ENABLE" start="1" description="A CR1 load due to a CAPn.1 event will generate an interrupt." /> + <Enum name="DISABLE" start="0" description="This feature is disabled." /> + </BitField> + <BitField start="6" size="26" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x02C+0" size="4" name="CR[0]" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CAP" description="Timer counter capture value." /> + </Register> + <Register start="+0x02C+4" size="4" name="CR[1]" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CAP" description="Timer counter capture value." /> + </Register> + <Register start="+0x03C" size="4" name="EMR" access="Read/Write" description="External Match Register. The EMR controls the external match pins." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="EM0" description="External Match 0. When a match occurs between the TC and MR0, this bit can either toggle, go low, go high, or do nothing, depending on bits 5:4 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." /> + <BitField start="1" size="1" name="EM1" description="External Match 1. When a match occurs between the TC and MR1, this bit can either toggle, go low, go high, or do nothing, depending on bits 7:6 of this register. This bit can be driven onto a MATn.1 pin, in a positive-logic manner (0 = low, 1 = high)." /> + <BitField start="2" size="1" name="EM2" description="External Match 2. When a match occurs between the TC and MR2, this bit can either toggle, go low, go high, or do nothing, depending on bits 9:8 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." /> + <BitField start="3" size="1" name="EM3" description="External Match 3. When a match occurs between the TC and MR3, this bit can either toggle, go low, go high, or do nothing, depending on bits 11:10 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." /> + <BitField start="4" size="2" name="EMC0" description="External Match Control 0. Determines the functionality of External Match 0."> + <Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." /> + <Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." /> + <Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." /> + <Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." /> + </BitField> + <BitField start="6" size="2" name="EMC1" description="External Match Control 1. Determines the functionality of External Match 1."> + <Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." /> + <Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." /> + <Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." /> + <Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." /> + </BitField> + <BitField start="8" size="2" name="EMC2" description="External Match Control 2. Determines the functionality of External Match 2."> + <Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." /> + <Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." /> + <Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." /> + <Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." /> + </BitField> + <BitField start="10" size="2" name="EMC3" description="External Match Control 3. Determines the functionality of External Match 3."> + <Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." /> + <Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." /> + <Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." /> + <Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." /> + </BitField> + <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x070" size="4" name="CTCR" access="Read/Write" description="Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="CTMODE" description="Counter/Timer Mode This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale Register."> + <Enum name="TIMER_MODE_EVERY_RI" start="0x0" description="Timer Mode: every rising PCLK edge" /> + <Enum name="RISING" start="0x1" description="Counter Mode: TC is incremented on rising edges on the CAP input selected by bits 3:2." /> + <Enum name="FALLING" start="0x2" description="Counter Mode: TC is incremented on falling edges on the CAP input selected by bits 3:2." /> + <Enum name="DUALEDGE" start="0x3" description="Counter Mode: TC is incremented on both edges on the CAP input selected by bits 3:2." /> + </BitField> + <BitField start="2" size="2" name="CINSEL" description="Count Input Select When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the TnCTCR, the 3 bits for that input in the Capture Control Register (TnCCR) must be programmed as 000. However, capture and/or interrupt can be selected for the other 3 CAPn inputs in the same timer."> + <Enum name="CAPN_0_FOR_TIMERN" start="0x0" description="CAPn.0 for TIMERn" /> + <Enum name="CAPN_1_FOR_TIMERN" start="0x1" description="CAPn.1 for TIMERn" /> + </BitField> + <BitField start="4" size="28" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + </RegisterGroup> + <RegisterGroup name="UART0" start="0x4000C000" description="UART0/2/3 "> + <Register start="+0x000" size="4" name="RBR" access="None" description="Receiver Buffer Register. Contains the next received character to be read (DLAB =0)." reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="8" name="RBR" description="The UARTn Receiver Buffer Register contains the oldest received byte in the UARTn Rx FIFO." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x000" size="4" name="THR" access="WriteOnly" description="Transmit Holding Regiter. The next character to be transmitted is written here (DLAB =0)." reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="8" name="THR" description="Writing to the UARTn Transmit Holding Register causes the data to be stored in the UARTn transmit FIFO. The byte will be sent when it reaches the bottom of the FIFO and the transmitter is available." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x000" size="4" name="DLL" access="Read/Write" description="Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB =1)." reset_value="0x01" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="DLLSB" description="The UARTn Divisor Latch LSB Register, along with the UnDLM register, determines the baud rate of the UARTn." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x004" size="4" name="DLM" access="Read/Write" description="Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB =1)." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="DLMSB" description="The UARTn Divisor Latch MSB Register, along with the U0DLL register, determines the baud rate of the UARTn." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x004" size="4" name="IER" access="Read/Write" description="Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential UART interrupts (DLAB =0)." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RBRIE" description="RBR Interrupt Enable. Enables the Receive Data Available interrupt for UARTn. It also controls the Character Receive Time-out interrupt."> + <Enum name="DISABLE_THE_RDA_INTE" start="0" description="Disable the RDA interrupts." /> + <Enum name="ENABLE_THE_RDA_INTER" start="1" description="Enable the RDA interrupts." /> + </BitField> + <BitField start="1" size="1" name="THREIE" description="THRE Interrupt Enable. Enables the THRE interrupt for UARTn. The status of this can be read from UnLSR[5]."> + <Enum name="DISABLE_THE_THRE_INT" start="0" description="Disable the THRE interrupts." /> + <Enum name="ENABLE_THE_THRE_INTE" start="1" description="Enable the THRE interrupts." /> + </BitField> + <BitField start="2" size="1" name="RXIE" description="RX Line Status Interrupt Enable. Enables the UARTn RX line status interrupts. The status of this interrupt can be read from UnLSR[4:1]."> + <Enum name="DISABLE_THE_RX_LINE_" start="0" description="Disable the RX line status interrupts." /> + <Enum name="ENABLE_THE_RX_LINE_S" start="1" description="Enable the RX line status interrupts." /> + </BitField> + <BitField start="3" size="5" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="8" size="1" name="ABEOINTEN" description="Enables the end of auto-baud interrupt."> + <Enum name="DISABLE_END_OF_AUTO_" start="0" description="Disable end of auto-baud Interrupt." /> + <Enum name="ENABLE_END_OF_AUTO_B" start="1" description="Enable end of auto-baud Interrupt." /> + </BitField> + <BitField start="9" size="1" name="ABTOINTEN" description="Enables the auto-baud time-out interrupt."> + <Enum name="DISABLE_AUTO_BAUD_TI" start="0" description="Disable auto-baud time-out Interrupt." /> + <Enum name="ENABLE_AUTO_BAUD_TIM" start="1" description="Enable auto-baud time-out Interrupt." /> + </BitField> + <BitField start="10" size="22" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x008" size="4" name="IIR" access="ReadOnly" description="Interrupt ID Register. Identifies which interrupt(s) are pending." reset_value="0x01" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="INTSTATUS" description="Interrupt status. Note that UnIIR[0] is active low. The pending interrupt can be determined by evaluating UnIIR[3:1]."> + <Enum name="AT_LEAST_ONE_INTERRU" start="0" description="At least one interrupt is pending." /> + <Enum name="NO_INTERRUPT_IS_PEND" start="1" description="No interrupt is pending." /> + </BitField> + <BitField start="1" size="3" name="INTID" description="Interrupt identification. UnIER[3:1] identifies an interrupt corresponding to the UARTn Rx or TX FIFO. All other combinations of UnIER[3:1] not listed below are reserved (000,100,101,111)."> + <Enum name="1_RECEIVE_LINE_S" start="0x3" description="1 - Receive Line Status (RLS)." /> + <Enum name="2A__RECEIVE_DATA_AV" start="0x2" description="2a - Receive Data Available (RDA)." /> + <Enum name="2B__CHARACTER_TIME_" start="0x6" description="2b - Character Time-out Indicator (CTI)." /> + <Enum name="3_THRE_INTERRUPT" start="0x1" description="3 - THRE Interrupt" /> + </BitField> + <BitField start="4" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="6" size="2" name="FIFOENABLE" description="Copies of UnFCR[0]." /> + <BitField start="8" size="1" name="ABEOINT" description="End of auto-baud interrupt. True if auto-baud has finished successfully and interrupt is enabled." /> + <BitField start="9" size="1" name="ABTOINT" description="Auto-baud time-out interrupt. True if auto-baud has timed out and interrupt is enabled." /> + <BitField start="10" size="22" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x008" size="4" name="FCR" access="WriteOnly" description="FIFO Control Register. Controls UART FIFO usage and modes." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="FIFOEN" description="FIFO Enable."> + <Enum name="UARTN_FIFOS_ARE_DISA" start="0" description="UARTn FIFOs are disabled. Must not be used in the application." /> + <Enum name="ACTIVE_HIGH_ENABLE_F" start="1" description="Active high enable for both UARTn Rx and TX FIFOs and UnFCR[7:1] access. This bit must be set for proper UART operation. Any transition on this bit will automatically clear the related UART FIFOs." /> + </BitField> + <BitField start="1" size="1" name="RXFIFORES" description="RX FIFO Reset."> + <Enum name="NO_IMPACT_ON_EITHER_" start="0" description="No impact on either of UARTn FIFOs." /> + <Enum name="WRITING_A_LOGIC_1_TO" start="1" description="Writing a logic 1 to UnFCR[1] will clear all bytes in UARTn Rx FIFO, reset the pointer logic. This bit is self-clearing." /> + </BitField> + <BitField start="2" size="1" name="TXFIFORES" description="TX FIFO Reset."> + <Enum name="NO_IMPACT_ON_EITHER_" start="0" description="No impact on either of UARTn FIFOs." /> + <Enum name="WRITING_A_LOGIC_1_TO" start="1" description="Writing a logic 1 to UnFCR[2] will clear all bytes in UARTn TX FIFO, reset the pointer logic. This bit is self-clearing." /> + </BitField> + <BitField start="3" size="1" name="DMAMODE" description="DMA Mode Select. When the FIFO enable (bit 0 of this register) is set, this bit selects the DMA mode. See Section 18.6.6.1." /> + <BitField start="4" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="6" size="2" name="RXTRIGLVL" description="RX Trigger Level. These two bits determine how many receiver UARTn FIFO characters must be written before an interrupt or DMA request is activated."> + <Enum name="TRIGGER_LEVEL_0_1_C" start="0x0" description="Trigger level 0 (1 character or 0x01)." /> + <Enum name="TRIGGER_LEVEL_1_4_C" start="0x1" description="Trigger level 1 (4 characters or 0x04)." /> + <Enum name="TRIGGER_LEVEL_2_8_C" start="0x2" description="Trigger level 2 (8 characters or 0x08)." /> + <Enum name="TRIGGER_LEVEL_3_14_" start="0x3" description="Trigger level 3 (14 characters or 0x0E)." /> + </BitField> + <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x00C" size="4" name="LCR" access="Read/Write" description="Line Control Register. Contains controls for frame formatting and break generation." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="WLS" description="Word Length Select."> + <Enum name="5_BIT_CHARACTER_LENG" start="0x0" description="5-bit character length" /> + <Enum name="6_BIT_CHARACTER_LENG" start="0x1" description="6-bit character length" /> + <Enum name="7_BIT_CHARACTER_LENG" start="0x2" description="7-bit character length" /> + <Enum name="8_BIT_CHARACTER_LENG" start="0x3" description="8-bit character length" /> + </BitField> + <BitField start="2" size="1" name="SBS" description="Stop Bit Select"> + <Enum name="1_STOP_BIT_" start="0" description="1 stop bit." /> + <Enum name="2_STOP_BITS_1_5_IF_" start="1" description="2 stop bits (1.5 if UnLCR[1:0]=00)." /> + </BitField> + <BitField start="3" size="1" name="PE" description="Parity Enable."> + <Enum name="DISABLE_PARITY_GENER" start="0" description="Disable parity generation and checking." /> + <Enum name="ENABLE_PARITY_GENERA" start="1" description="Enable parity generation and checking." /> + </BitField> + <BitField start="4" size="2" name="PS" description="Parity Select"> + <Enum name="ODD_PARITY_NUMBER_O" start="0x0" description="Odd parity. Number of 1s in the transmitted character and the attached parity bit will be odd." /> + <Enum name="EVEN_PARITY_NUMBER_" start="0x1" description="Even Parity. Number of 1s in the transmitted character and the attached parity bit will be even." /> + <Enum name="FORCED_1_STICK_PARIT" start="0x2" description="Forced 1 stick parity." /> + <Enum name="FORCED_0_STICK_PARIT" start="0x3" description="Forced 0 stick parity." /> + </BitField> + <BitField start="6" size="1" name="BC" description="Break Control"> + <Enum name="DISABLE_BREAK_TRANSM" start="0" description="Disable break transmission." /> + <Enum name="ENABLE_BREAK_TRANSMI" start="1" description="Enable break transmission. Output pin UARTn TXD is forced to logic 0 when UnLCR[6] is active high." /> + </BitField> + <BitField start="7" size="1" name="DLAB" description="Divisor Latch Access Bit"> + <Enum name="DISABLE_ACCESS_TO_DI" start="0" description="Disable access to Divisor Latches." /> + <Enum name="ENABLE_ACCESS_TO_DIV" start="1" description="Enable access to Divisor Latches." /> + </BitField> + <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x014" size="4" name="LSR" access="None" description="Line Status Register. Contains flags for transmit and receive status, including line errors." reset_value="0x60" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RDR" description="Receiver Data Ready. UnLSR[0] is set when the UnRBR holds an unread character and is cleared when the UARTn RBR FIFO is empty."> + <Enum name="EMPTY" start="0" description="The UARTn receiver FIFO is empty." /> + <Enum name="NOTEMPTY" start="1" description="The UARTn receiver FIFO is not empty." /> + </BitField> + <BitField start="1" size="1" name="OE" description="Overrun Error. The overrun error condition is set as soon as it occurs. An UnLSR read clears UnLSR[1]. UnLSR[1] is set when UARTn RSR has a new character assembled and the UARTn RBR FIFO is full. In this case, the UARTn RBR FIFO will not be overwritten and the character in the UARTn RSR will be lost."> + <Enum name="INACTIVE" start="0" description="Overrun error status is inactive." /> + <Enum name="ACTIVE" start="1" description="Overrun error status is active." /> + </BitField> + <BitField start="2" size="1" name="PE" description="Parity Error. When the parity bit of a received character is in the wrong state, a parity error occurs. An UnLSR read clears UnLSR[2]. Time of parity error detection is dependent on UnFCR[0]. Note: A parity error is associated with the character at the top of the UARTn RBR FIFO."> + <Enum name="INACTIVE" start="0" description="Parity error status is inactive." /> + <Enum name="ACTIVE" start="1" description="Parity error status is active." /> + </BitField> + <BitField start="3" size="1" name="FE" description="Framing Error. When the stop bit of a received character is a logic 0, a framing error occurs. An UnLSR read clears UnLSR[3]. The time of the framing error detection is dependent on UnFCR[0]. Upon detection of a framing error, the Rx will attempt to resynchronize to the data and assume that the bad stop bit is actually an early start bit. However, it cannot be assumed that the next received byte will be correct even if there is no Framing Error. Note: A framing error is associated with the character at the top of the UARTn RBR FIFO."> + <Enum name="INACTIVE" start="0" description="Framing error status is inactive." /> + <Enum name="ACTIVE" start="1" description="Framing error status is active." /> + </BitField> + <BitField start="4" size="1" name="BI" description="Break Interrupt. When RXDn is held in the spacing state (all zeroes) for one full character transmission (start, data, parity, stop), a break interrupt occurs. Once the break condition has been detected, the receiver goes idle until RXDn goes to marking state (all ones). An UnLSR read clears this status bit. The time of break detection is dependent on UnFCR[0]. Note: The break interrupt is associated with the character at the top of the UARTn RBR FIFO."> + <Enum name="INACTIVE" start="0" description="Break interrupt status is inactive." /> + <Enum name="ACTIVE" start="1" description="Break interrupt status is active." /> + </BitField> + <BitField start="5" size="1" name="THRE" description="Transmitter Holding Register Empty. THRE is set immediately upon detection of an empty UARTn THR and is cleared on a UnTHR write."> + <Enum name="VALIDDATA" start="0" description="UnTHR contains valid data." /> + <Enum name="EMPTY" start="1" description="UnTHR is empty." /> + </BitField> + <BitField start="6" size="1" name="TEMT" description="Transmitter Empty. TEMT is set when both UnTHR and UnTSR are empty; TEMT is cleared when either the UnTSR or the UnTHR contain valid data."> + <Enum name="VALIDDATA" start="0" description="UnTHR and/or the UnTSR contains valid data." /> + <Enum name="EMPTY" start="1" description="UnTHR and the UnTSR are empty." /> + </BitField> + <BitField start="7" size="1" name="RXFE" description="Error in RX FIFO . UnLSR[7] is set when a character with a Rx error such as framing error, parity error or break interrupt, is loaded into the UnRBR. This bit is cleared when the UnLSR register is read and there are no subsequent errors in the UARTn FIFO."> + <Enum name="NOERROR" start="0" description="UnRBR contains no UARTn RX errors or UnFCR[0]=0." /> + <Enum name="ERRORS" start="1" description="UARTn RBR contains at least one UARTn RX error." /> + </BitField> + <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x01C" size="4" name="SCR" access="Read/Write" description="Scratch Pad Register. 8-bit temporary storage for software." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="PAD" description="A readable, writable byte." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x020" size="4" name="ACR" access="Read/Write" description="Auto-baud Control Register. Contains controls for the auto-baud feature." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="START" description="Start bit. This bit is automatically cleared after auto-baud completion."> + <Enum name="AUTO_BAUD_STOP_AUTO" start="0" description="Auto-baud stop (auto-baud is not running)." /> + <Enum name="AUTO_BAUD_START_AUT" start="1" description="Auto-baud start (auto-baud is running). Auto-baud run bit. This bit is automatically cleared after auto-baud completion." /> + </BitField> + <BitField start="1" size="1" name="MODE" description="Auto-baud mode select bit."> + <Enum name="MODE_0_" start="0" description="Mode 0." /> + <Enum name="MODE_1_" start="1" description="Mode 1." /> + </BitField> + <BitField start="2" size="1" name="AUTORESTART" description="Restart bit."> + <Enum name="NO_RESTART_" start="0" description="No restart." /> + <Enum name="RESTART_IN_CASE_OF_T" start="1" description="Restart in case of time-out (counter restarts at next UARTn Rx falling edge)" /> + </BitField> + <BitField start="3" size="5" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="8" size="1" name="ABEOINTCLR" description="End of auto-baud interrupt clear bit (write-only accessible). Writing a 1 will clear the corresponding interrupt in the UnIIR. Writing a 0 has no impact."> + <Enum name="NO_IMPACT_" start="0" description="No impact." /> + <Enum name="CLEAR_THE_CORRESPOND" start="1" description="Clear the corresponding interrupt in the IIR." /> + </BitField> + <BitField start="9" size="1" name="ABTOINTCLR" description="Auto-baud time-out interrupt clear bit (write-only accessible). Writing a 1 will clear the corresponding interrupt in the UnIIR. Writing a 0 has no impact."> + <Enum name="NO_IMPACT_" start="0" description="No impact." /> + <Enum name="CLEAR_THE_CORRESPOND" start="1" description="Clear the corresponding interrupt in the IIR." /> + </BitField> + <BitField start="10" size="22" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x028" size="4" name="FDR" access="Read/Write" description="Fractional Divider Register. Generates a clock input for the baud rate divider." reset_value="0x10" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="4" name="DIVADDVAL" description="Baud-rate generation pre-scaler divisor value. If this field is 0, fractional baud-rate generator will not impact the UARTn baudrate." /> + <BitField start="4" size="4" name="MULVAL" description="Baud-rate pre-scaler multiplier value. This field must be greater or equal 1 for UARTn to operate properly, regardless of whether the fractional baud-rate generator is used or not." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x030" size="4" name="TER" access="Read/Write" description="Transmit Enable Register. Turns off UART transmitter for use with software flow control." reset_value="0x80" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="7" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="7" size="1" name="TXEN" description="When this bit is 1, as it is after a Reset, data written to the THR is output on the TXD pin as soon as any preceding data has been sent. If this bit is cleared to 0 while a character is being sent, the transmission of that character is completed, but no further characters are sent until this bit is set again. In other words, a 0 in this bit blocks the transfer of characters from the THR or TX FIFO into the transmit shift register. Software implementing software-handshaking can clear this bit when it receives an XOFF character (DC3). Software can set this bit again when it receives an XON (DC1) character." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x04C" size="4" name="RS485CTRL" access="Read/Write" description="RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="NMMEN" description="NMM enable."> + <Enum name="DISABLED" start="0" description="RS-485/EIA-485 Normal Multidrop Mode (NMM) is disabled." /> + <Enum name="ENABLED" start="1" description="RS-485/EIA-485 Normal Multidrop Mode (NMM) is enabled. In this mode, an address is detected when a received byte has the parity bit = 1, generating a received data interrupt. See Section 18.6.16 RS-485/EIA-485 modes of operation." /> + </BitField> + <BitField start="1" size="1" name="RXDIS" description="Receiver enable."> + <Enum name="ENABLED" start="0" description="The receiver is enabled." /> + <Enum name="DISABLED" start="1" description="The receiver is disabled." /> + </BitField> + <BitField start="2" size="1" name="AADEN" description="AAD enable."> + <Enum name="DISABLED" start="0" description="Auto Address Detect (AAD) is disabled." /> + <Enum name="ENABLED" start="1" description="Auto Address Detect (AAD) is enabled." /> + </BitField> + <BitField start="3" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="4" size="1" name="DCTRL" description="Direction control enable."> + <Enum name="DISABLE_AUTO_DIRECTI" start="0" description="Disable Auto Direction Control." /> + <Enum name="ENABLE_AUTO_DIRECTIO" start="1" description="Enable Auto Direction Control." /> + </BitField> + <BitField start="5" size="1" name="OINV" description="Direction control pin polarity. This bit reverses the polarity of the direction control signal on the Un_OE pin."> + <Enum name="DIRLOW" start="0" description="The direction control pin will be driven to logic 0 when the transmitter has data to be sent. It will be driven to logic 1 after the last bit of data has been transmitted." /> + <Enum name="DIRHIGH" start="1" description="The direction control pin will be driven to logic 1 when the transmitter has data to be sent. It will be driven to logic 0 after the last bit of data has been transmitted." /> + </BitField> + <BitField start="6" size="26" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x050" size="4" name="RS485ADRMATCH" access="Read/Write" description="RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="ADRMATCH" description="Contains the address match value." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x054" size="4" name="RS485DLY" access="Read/Write" description="RS-485/EIA-485 direction control delay." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="DLY" description="Contains the direction control (UnOE) delay value. This register works in conjunction with an 8-bit counter." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + </RegisterGroup> + <RegisterGroup name="UART1" start="0x40010000" description="UART1 "> + <Register start="+0x000" size="4" name="RBR" access="None" description="DLAB =0 Receiver Buffer Register. Contains the next received character to be read." reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="8" name="RBR" description="The UART1 Receiver Buffer Register contains the oldest received byte in the UART1 RX FIFO." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x000" size="4" name="THR" access="WriteOnly" description="DLAB =0. Transmit Holding Register. The next character to be transmitted is written here." reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="8" name="THR" description="Writing to the UART1 Transmit Holding Register causes the data to be stored in the UART1 transmit FIFO. The byte will be sent when it reaches the bottom of the FIFO and the transmitter is available." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x000" size="4" name="DLL" access="Read/Write" description="DLAB =1. Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider." reset_value="0x01" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="DLLSB" description="The UART1 Divisor Latch LSB Register, along with the U1DLM register, determines the baud rate of the UART1." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x004" size="4" name="DLM" access="Read/Write" description="DLAB =1. Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="DLMSB" description="The UART1 Divisor Latch MSB Register, along with the U1DLL register, determines the baud rate of the UART1." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x004" size="4" name="IER" access="Read/Write" description="DLAB =0. Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential UART1 interrupts." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RBRIE" description="RBR Interrupt Enable. Enables the Receive Data Available interrupt for UART1. It also controls the Character Receive Time-out interrupt."> + <Enum name="DISABLE_THE_RDA_INTE" start="0" description="Disable the RDA interrupts." /> + <Enum name="ENABLE_THE_RDA_INTER" start="1" description="Enable the RDA interrupts." /> + </BitField> + <BitField start="1" size="1" name="THREIE" description="THRE Interrupt Enable. Enables the THRE interrupt for UART1. The status of this interrupt can be read from LSR[5]."> + <Enum name="DISABLE_THE_THRE_INT" start="0" description="Disable the THRE interrupts." /> + <Enum name="ENABLE_THE_THRE_INTE" start="1" description="Enable the THRE interrupts." /> + </BitField> + <BitField start="2" size="1" name="RXIE" description="RX Line Interrupt Enable. Enables the UART1 RX line status interrupts. The status of this interrupt can be read from LSR[4:1]."> + <Enum name="DISABLE_THE_RX_LINE_" start="0" description="Disable the RX line status interrupts." /> + <Enum name="ENABLE_THE_RX_LINE_S" start="1" description="Enable the RX line status interrupts." /> + </BitField> + <BitField start="3" size="1" name="MSIE" description="Modem Status Interrupt Enable. Enables the modem interrupt. The status of this interrupt can be read from MSR[3:0]."> + <Enum name="DISABLE_THE_MODEM_IN" start="0" description="Disable the modem interrupt." /> + <Enum name="ENABLE_THE_MODEM_INT" start="1" description="Enable the modem interrupt." /> + </BitField> + <BitField start="4" size="3" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + <BitField start="7" size="1" name="CTSIE" description="CTS Interrupt Enable. If auto-cts mode is enabled this bit enables/disables the modem status interrupt generation on a CTS1 signal transition. If auto-cts mode is disabled a CTS1 transition will generate an interrupt if Modem Status Interrupt Enable (IER[3]) is set. In normal operation a CTS1 signal transition will generate a Modem Status Interrupt unless the interrupt has been disabled by clearing the IER[3] bit in the IER register. In auto-cts mode a transition on the CTS1 bit will trigger an interrupt only if both the IER[3] and IER[7] bits are set."> + <Enum name="DISABLE_THE_CTS_INTE" start="0" description="Disable the CTS interrupt." /> + <Enum name="ENABLE_THE_CTS_INTER" start="1" description="Enable the CTS interrupt." /> + </BitField> + <BitField start="8" size="1" name="ABEOIE" description="Enables the end of auto-baud interrupt."> + <Enum name="DISABLE_END_OF_AUTO_" start="0" description="Disable end of auto-baud Interrupt." /> + <Enum name="ENABLE_END_OF_AUTO_B" start="1" description="Enable end of auto-baud Interrupt." /> + </BitField> + <BitField start="9" size="1" name="ABTOIE" description="Enables the auto-baud time-out interrupt."> + <Enum name="DISABLE_AUTO_BAUD_TI" start="0" description="Disable auto-baud time-out Interrupt." /> + <Enum name="ENABLE_AUTO_BAUD_TIM" start="1" description="Enable auto-baud time-out Interrupt." /> + </BitField> + <BitField start="10" size="22" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x008" size="4" name="IIR" access="ReadOnly" description="Interrupt ID Register. Identifies which interrupt(s) are pending." reset_value="0x01" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="INTSTATUS" description="Interrupt status. Note that IIR[0] is active low. The pending interrupt can be determined by evaluating IIR[3:1]."> + <Enum name="AT_LEAST_ONE_INTERRU" start="0" description="At least one interrupt is pending." /> + <Enum name="NO_INTERRUPT_IS_PEND" start="1" description="No interrupt is pending." /> + </BitField> + <BitField start="1" size="3" name="INTID" description="Interrupt identification. IER[3:1] identifies an interrupt corresponding to the UART1 Rx or TX FIFO. All other combinations of IER[3:1] not listed below are reserved (100,101,111)."> + <Enum name="RLS" start="0x3" description="1 - Receive Line Status (RLS)." /> + <Enum name="RDA" start="0x2" description="2a - Receive Data Available (RDA)." /> + <Enum name="CTI" start="0x6" description="2b - Character Time-out Indicator (CTI)." /> + <Enum name="THRE" start="0x1" description="3 - THRE Interrupt." /> + <Enum name="MODEM" start="0x0" description="4 - Modem Interrupt." /> + </BitField> + <BitField start="4" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + <BitField start="6" size="2" name="FIFOENABLE" description="Copies of FCR[0]." /> + <BitField start="8" size="1" name="ABEOINT" description="End of auto-baud interrupt. True if auto-baud has finished successfully and interrupt is enabled." /> + <BitField start="9" size="1" name="ABTOINT" description="Auto-baud time-out interrupt. True if auto-baud has timed out and interrupt is enabled." /> + <BitField start="10" size="22" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x008" size="4" name="FCR" access="WriteOnly" description="FIFO Control Register. Controls UART1 FIFO usage and modes." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="FIFOEN" description="FIFO enable."> + <Enum name="MUST_NOT_BE_USED_IN_" start="0" description="Must not be used in the application." /> + <Enum name="ACTIVE_HIGH_ENABLE_F" start="1" description="Active high enable for both UART1 Rx and TX FIFOs and FCR[7:1] access. This bit must be set for proper UART1 operation. Any transition on this bit will automatically clear the UART1 FIFOs." /> + </BitField> + <BitField start="1" size="1" name="RXFIFORES" description="RX FIFO Reset."> + <Enum name="NO_IMPACT_ON_EITHER_" start="0" description="No impact on either of UART1 FIFOs." /> + <Enum name="WRITING_A_LOGIC_1_TO" start="1" description="Writing a logic 1 to FCR[1] will clear all bytes in UART1 Rx FIFO, reset the pointer logic. This bit is self-clearing." /> + </BitField> + <BitField start="2" size="1" name="TXFIFORES" description="TX FIFO Reset."> + <Enum name="NO_IMPACT_ON_EITHER_" start="0" description="No impact on either of UART1 FIFOs." /> + <Enum name="WRITING_A_LOGIC_1_TO" start="1" description="Writing a logic 1 to FCR[2] will clear all bytes in UART1 TX FIFO, reset the pointer logic. This bit is self-clearing." /> + </BitField> + <BitField start="3" size="1" name="DMAMODE" description="DMA Mode Select. When the FIFO enable bit (bit 0 of this register) is set, this bit selects the DMA mode. See Section 36.6.6.1." /> + <BitField start="4" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + <BitField start="6" size="2" name="RXTRIGLVL" description="RX Trigger Level. These two bits determine how many receiver UART1 FIFO characters must be written before an interrupt is activated."> + <Enum name="TRIGGER_LEVEL_0_1_C" start="0x0" description="Trigger level 0 (1 character or 0x01)." /> + <Enum name="TRIGGER_LEVEL_1_4_C" start="0x1" description="Trigger level 1 (4 characters or 0x04)." /> + <Enum name="TRIGGER_LEVEL_2_8_C" start="0x2" description="Trigger level 2 (8 characters or 0x08)." /> + <Enum name="TRIGGER_LEVEL_3_14_" start="0x3" description="Trigger level 3 (14 characters or 0x0E)." /> + </BitField> + <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits." /> + </Register> + <Register start="+0x00C" size="4" name="LCR" access="Read/Write" description="Line Control Register. Contains controls for frame formatting and break generation." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="WLS" description="Word Length Select."> + <Enum name="5_BIT_CHARACTER_LENG" start="0x0" description="5-bit character length." /> + <Enum name="6_BIT_CHARACTER_LENG" start="0x1" description="6-bit character length." /> + <Enum name="7_BIT_CHARACTER_LENG" start="0x2" description="7-bit character length." /> + <Enum name="8_BIT_CHARACTER_LENG" start="0x3" description="8-bit character length." /> + </BitField> + <BitField start="2" size="1" name="SBS" description="Stop Bit Select."> + <Enum name="1_STOP_BIT_" start="0" description="1 stop bit." /> + <Enum name="2_STOP_BITS_1_5_IF_" start="1" description="2 stop bits (1.5 if LCR[1:0]=00)." /> + </BitField> + <BitField start="3" size="1" name="PE" description="Parity Enable."> + <Enum name="DISABLE_PARITY_GENER" start="0" description="Disable parity generation and checking." /> + <Enum name="ENABLE_PARITY_GENERA" start="1" description="Enable parity generation and checking." /> + </BitField> + <BitField start="4" size="2" name="PS" description="Parity Select."> + <Enum name="ODD_PARITY_NUMBER_O" start="0x0" description="Odd parity. Number of 1s in the transmitted character and the attached parity bit will be odd." /> + <Enum name="EVEN_PARITY_NUMBER_" start="0x1" description="Even Parity. Number of 1s in the transmitted character and the attached parity bit will be even." /> + <Enum name="FORCED1STICK_PAR" start="0x2" description="Forced 1 stick parity." /> + <Enum name="FORCED0STICK_PAR" start="0x3" description="Forced 0 stick parity." /> + </BitField> + <BitField start="6" size="1" name="BC" description="Break Control."> + <Enum name="DISABLE_BREAK_TRANSM" start="0" description="Disable break transmission." /> + <Enum name="ENABLE_BREAK_TRANSMI" start="1" description="Enable break transmission. Output pin UART1 TXD is forced to logic 0 when LCR[6] is active high." /> + </BitField> + <BitField start="7" size="1" name="DLAB" description="Divisor Latch Access Bit (DLAB)"> + <Enum name="DISABLE_ACCESS_TO_DI" start="0" description="Disable access to Divisor Latches." /> + <Enum name="ENABLE_ACCESS_TO_DIV" start="1" description="Enable access to Divisor Latches." /> + </BitField> + <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x010" size="4" name="MCR" access="Read/Write" description="Modem Control Register. Contains controls for flow control handshaking and loopback mode." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="DTRCTRL" description="DTR Control. Source for modem output pin, DTR. This bit reads as 0 when modem loopback mode is active." /> + <BitField start="1" size="1" name="RTSCTRL" description="RTS Control. Source for modem output pin RTS. This bit reads as 0 when modem loopback mode is active." /> + <BitField start="2" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + <BitField start="4" size="1" name="LMS" description="Loopback Mode Select. The modem loopback mode provides a mechanism to perform diagnostic loopback testing. Serial data from the transmitter is connected internally to serial input of the receiver. Input pin, RXD1, has no effect on loopback and output pin, TXD1 is held in marking state. The 4 modem inputs (CTS, DSR, RI and DCD) are disconnected externally. Externally, the modem outputs (RTS, DTR) are set inactive. Internally, the 4 modem outputs are connected to the 4 modem inputs. As a result of these connections, the upper 4 bits of the MSR will be driven by the lower 4 bits of the MCR rather than the 4 modem inputs in normal mode. This permits modem status interrupts to be generated in loopback mode by writing the lower 4 bits of MCR."> + <Enum name="DISABLE_MODEM_LOOPBA" start="0" description="Disable modem loopback mode." /> + <Enum name="ENABLE_MODEM_LOOPBAC" start="1" description="Enable modem loopback mode." /> + </BitField> + <BitField start="5" size="1" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + <BitField start="6" size="1" name="RTSEN" description="RTS enable."> + <Enum name="DISABLE_AUTO_RTS_FLO" start="0" description="Disable auto-rts flow control." /> + <Enum name="ENABLE_AUTO_RTS_FLOW" start="1" description="Enable auto-rts flow control." /> + </BitField> + <BitField start="7" size="1" name="CTSEN" description="CTS enable."> + <Enum name="DISABLE_AUTO_CTS_FLO" start="0" description="Disable auto-cts flow control." /> + <Enum name="ENABLE_AUTO_CTS_FLOW" start="1" description="Enable auto-cts flow control." /> + </BitField> + <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x014" size="4" name="LSR" access="None" description="Line Status Register. Contains flags for transmit and receive status, including line errors." reset_value="0x60" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RDR" description="Receiver Data Ready. LSR[0] is set when the RBR holds an unread character and is cleared when the UART1 RBR FIFO is empty."> + <Enum name="EMPTY" start="0" description="The UART1 receiver FIFO is empty." /> + <Enum name="NOTEMPTY" start="1" description="The UART1 receiver FIFO is not empty." /> + </BitField> + <BitField start="1" size="1" name="OE" description="Overrun Error. The overrun error condition is set as soon as it occurs. An LSR read clears LSR[1]. LSR[1] is set when UART1 RSR has a new character assembled and the UART1 RBR FIFO is full. In this case, the UART1 RBR FIFO will not be overwritten and the character in the UART1 RSR will be lost."> + <Enum name="INACTIVE" start="0" description="Overrun error status is inactive." /> + <Enum name="ACTIVE" start="1" description="Overrun error status is active." /> + </BitField> + <BitField start="2" size="1" name="PE" description="Parity Error. When the parity bit of a received character is in the wrong state, a parity error occurs. An LSR read clears LSR[2]. Time of parity error detection is dependent on FCR[0]. Note: A parity error is associated with the character at the top of the UART1 RBR FIFO."> + <Enum name="INACTIVE" start="0" description="Parity error status is inactive." /> + <Enum name="ACTIVE" start="1" description="Parity error status is active." /> + </BitField> + <BitField start="3" size="1" name="FE" description="Framing Error. When the stop bit of a received character is a logic 0, a framing error occurs. An LSR read clears LSR[3]. The time of the framing error detection is dependent on FCR0. Upon detection of a framing error, the RX will attempt to resynchronize to the data and assume that the bad stop bit is actually an early start bit. However, it cannot be assumed that the next received byte will be correct even if there is no Framing Error. Note: A framing error is associated with the character at the top of the UART1 RBR FIFO."> + <Enum name="INACTIVE" start="0" description="Framing error status is inactive." /> + <Enum name="ACTIVE" start="1" description="Framing error status is active." /> + </BitField> + <BitField start="4" size="1" name="BI" description="Break Interrupt. When RXD1 is held in the spacing state (all zeroes) for one full character transmission (start, data, parity, stop), a break interrupt occurs. Once the break condition has been detected, the receiver goes idle until RXD1 goes to marking state (all ones). An LSR read clears this status bit. The time of break detection is dependent on FCR[0]. Note: The break interrupt is associated with the character at the top of the UART1 RBR FIFO."> + <Enum name="INACTIVE" start="0" description="Break interrupt status is inactive." /> + <Enum name="ACTIVE" start="1" description="Break interrupt status is active." /> + </BitField> + <BitField start="5" size="1" name="THRE" description="Transmitter Holding Register Empty. THRE is set immediately upon detection of an empty UART1 THR and is cleared on a THR write."> + <Enum name="VALID" start="0" description="THR contains valid data." /> + <Enum name="THR_IS_EMPTY_" start="1" description="THR is empty." /> + </BitField> + <BitField start="6" size="1" name="TEMT" description="Transmitter Empty. TEMT is set when both THR and TSR are empty; TEMT is cleared when either the TSR or the THR contain valid data."> + <Enum name="VALID" start="0" description="THR and/or the TSR contains valid data." /> + <Enum name="EMPTY" start="1" description="THR and the TSR are empty." /> + </BitField> + <BitField start="7" size="1" name="RXFE" description="Error in RX FIFO. LSR[7] is set when a character with a RX error such as framing error, parity error or break interrupt, is loaded into the RBR. This bit is cleared when the LSR register is read and there are no subsequent errors in the UART1 FIFO."> + <Enum name="NOERROR" start="0" description="RBR contains no UART1 RX errors or FCR[0]=0." /> + <Enum name="ERRORS" start="1" description="UART1 RBR contains at least one UART1 RX error." /> + </BitField> + <BitField start="8" size="24" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x018" size="4" name="MSR" access="None" description="Modem Status Register. Contains handshake signal status flags." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="DCTS" description="Delta CTS. Set upon state change of input CTS. Cleared on an MSR read."> + <Enum name="NO_CHANGE_DETECTED_O" start="0" description="No change detected on modem input, CTS." /> + <Enum name="STATE_CHANGE_DETECTE" start="1" description="State change detected on modem input, CTS." /> + </BitField> + <BitField start="1" size="1" name="DDSR" description="Delta DSR. Set upon state change of input DSR. Cleared on an MSR read."> + <Enum name="NO_CHANGE_DETECTED_O" start="0" description="No change detected on modem input, DSR." /> + <Enum name="STATE_CHANGE_DETECTE" start="1" description="State change detected on modem input, DSR." /> + </BitField> + <BitField start="2" size="1" name="TERI" description="Trailing Edge RI. Set upon low to high transition of input RI. Cleared on an MSR read."> + <Enum name="NO_CHANGE_DETECTED_O" start="0" description="No change detected on modem input, RI." /> + <Enum name="LOW_TO_HIGH_TRANSITI" start="1" description="Low-to-high transition detected on RI." /> + </BitField> + <BitField start="3" size="1" name="DDCD" description="Delta DCD. Set upon state change of input DCD. Cleared on an MSR read."> + <Enum name="NO_CHANGE_DETECTED_O" start="0" description="No change detected on modem input, DCD." /> + <Enum name="STATE_CHANGE_DETECTE" start="1" description="State change detected on modem input, DCD." /> + </BitField> + <BitField start="4" size="1" name="CTS" description="Clear To Send State. Complement of input signal CTS. This bit is connected to MCR[1] in modem loopback mode." /> + <BitField start="5" size="1" name="DSR" description="Data Set Ready State. Complement of input signal DSR. This bit is connected to MCR[0] in modem loopback mode." /> + <BitField start="6" size="1" name="RI" description="Ring Indicator State. Complement of input RI. This bit is connected to MCR[2] in modem loopback mode." /> + <BitField start="7" size="1" name="DCD" description="Data Carrier Detect State. Complement of input DCD. This bit is connected to MCR[3] in modem loopback mode." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x01C" size="4" name="SCR" access="Read/Write" description="Scratch Pad Register. 8-bit temporary storage for software." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="Pad" description="A readable, writable byte." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x020" size="4" name="ACR" access="Read/Write" description="Auto-baud Control Register. Contains controls for the auto-baud feature." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="START" description="Auto-baud start bit. This bit is automatically cleared after auto-baud completion."> + <Enum name="STOP" start="0" description="Auto-baud stop (auto-baud is not running)." /> + <Enum name="START" start="1" description="Auto-baud start (auto-baud is running). Auto-baud run bit. This bit is automatically cleared after auto-baud completion." /> + </BitField> + <BitField start="1" size="1" name="MODE" description="Auto-baud mode select bit."> + <Enum name="MODE_0_" start="0" description="Mode 0." /> + <Enum name="MODE_1_" start="1" description="Mode 1." /> + </BitField> + <BitField start="2" size="1" name="AUTORESTART" description="Auto-baud restart bit."> + <Enum name="NO_RESTART" start="0" description="No restart" /> + <Enum name="RESTART_IN_CASE_OF_T" start="1" description="Restart in case of time-out (counter restarts at next UART1 Rx falling edge)" /> + </BitField> + <BitField start="3" size="5" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + <BitField start="8" size="1" name="ABEOINTCLR" description="End of auto-baud interrupt clear bit (write-only)."> + <Enum name="WRITING_A_0_HAS_NO_I" start="0" description="Writing a 0 has no impact." /> + <Enum name="WRITING_A_1_WILL_CLE" start="1" description="Writing a 1 will clear the corresponding interrupt in the IIR." /> + </BitField> + <BitField start="9" size="1" name="ABTOINTCLR" description="Auto-baud time-out interrupt clear bit (write-only)."> + <Enum name="WRITING_A_0_HAS_NO_I" start="0" description="Writing a 0 has no impact." /> + <Enum name="WRITING_A_1_WILL_CLE" start="1" description="Writing a 1 will clear the corresponding interrupt in the IIR." /> + </BitField> + <BitField start="10" size="22" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x028" size="4" name="FDR" access="Read/Write" description="Fractional Divider Register. Generates a clock input for the baud rate divider." reset_value="0x10" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="4" name="DIVADDVAL" description="Baud rate generation pre-scaler divisor value. If this field is 0, fractional baud rate generator will not impact the UART1 baud rate." /> + <BitField start="4" size="4" name="MULVAL" description="Baud rate pre-scaler multiplier value. This field must be greater or equal 1 for UART1 to operate properly, regardless of whether the fractional baud rate generator is used or not." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x030" size="4" name="TER" access="Read/Write" description="Transmit Enable Register. Turns off UART transmitter for use with software flow control." reset_value="0x80" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="7" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="7" size="1" name="TXEN" description="When this bit is 1, as it is after a Reset, data written to the THR is output on the TXD pin as soon as any preceding data has been sent. If this bit cleared to 0 while a character is being sent, the transmission of that character is completed, but no further characters are sent until this bit is set again. In other words, a 0 in this bit blocks the transfer of characters from the THR or TX FIFO into the transmit shift register. Software can clear this bit when it detects that the a hardware-handshaking TX-permit signal (CTS) has gone false, or with software handshaking, when it receives an XOFF character (DC3). Software can set this bit again when it detects that the TX-permit signal has gone true, or when it receives an XON (DC1) character." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x04C" size="4" name="RS485CTRL" access="Read/Write" description="RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="NMMEN" description="RS-485/EIA-485 Normal Multidrop Mode (NMM) mode select."> + <Enum name="DISABLED_" start="0" description="Disabled." /> + <Enum name="ENABLED_IN_THIS_MOD" start="1" description="Enabled. In this mode, an address is detected when a received byte causes the UART to set the parity error and generate an interrupt." /> + </BitField> + <BitField start="1" size="1" name="RXDIS" description="Receive enable."> + <Enum name="ENABLED_" start="0" description="Enabled." /> + <Enum name="DISABLED_" start="1" description="Disabled." /> + </BitField> + <BitField start="2" size="1" name="AADEN" description="Auto Address Detect (AAD) enable."> + <Enum name="DISABLED_" start="0" description="Disabled." /> + <Enum name="ENABLED_" start="1" description="Enabled." /> + </BitField> + <BitField start="3" size="1" name="SEL" description="Direction control."> + <Enum name="RTS_IF_DIRECTION_CO" start="0" description="RTS. If direction control is enabled (bit DCTRL = 1), pin RTS is used for direction control." /> + <Enum name="DTR_IF_DIRECTION_CO" start="1" description="DTR. If direction control is enabled (bit DCTRL = 1), pin DTR is used for direction control." /> + </BitField> + <BitField start="4" size="1" name="DCTRL" description="Direction control enable."> + <Enum name="DISABLE_AUTO_DIRECTI" start="0" description="Disable Auto Direction Control." /> + <Enum name="ENABLE_AUTO_DIRECTIO" start="1" description="Enable Auto Direction Control." /> + </BitField> + <BitField start="5" size="1" name="OINV" description="Polarity. This bit reverses the polarity of the direction control signal on the RTS (or DTR) pin."> + <Enum name="LOW_THE_DIRECTION_C" start="0" description="LOW. The direction control pin will be driven to logic 0 when the transmitter has data to be sent. It will be driven to logic 1 after the last bit of data has been transmitted." /> + <Enum name="HIGH_THE_DIRECTION_" start="1" description="HIGH. The direction control pin will be driven to logic 1 when the transmitter has data to be sent. It will be driven to logic 0 after the last bit of data has been transmitted." /> + </BitField> + <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x050" size="4" name="RS485ADRMATCH" access="Read/Write" description="RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="ADRMATCH" description="Contains the address match value." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x054" size="4" name="RS485DLY" access="Read/Write" description="RS-485/EIA-485 direction control delay." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="DLY" description="Contains the direction control (RTS or DTR) delay value. This register works in conjunction with an 8-bit counter." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + </RegisterGroup> + <RegisterGroup name="PWM1" start="0x40018000" description="Pulse Width Modulators (PWM1) "> + <Register start="+0x000" size="4" name="IR" access="Read/Write" description="Interrupt Register. The IR can be written to clear interrupts, or read to identify which PWM interrupt sources are pending." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="PWMMR0INT" description="Interrupt flag for PWM match channel 0." /> + <BitField start="1" size="1" name="PWMMR1INT" description="Interrupt flag for PWM match channel 1." /> + <BitField start="2" size="1" name="PWMMR2INT" description="Interrupt flag for PWM match channel 2." /> + <BitField start="3" size="1" name="PWMMR3INT" description="Interrupt flag for PWM match channel 3." /> + <BitField start="4" size="1" name="PWMCAP0INT" description="Interrupt flag for capture input 0" /> + <BitField start="5" size="1" name="PWMCAP1INT" description="Interrupt flag for capture input 1 (available in PWM1IR only; this bit is reserved in PWM0IR)." /> + <BitField start="6" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="8" size="1" name="PWMMR4INT" description="Interrupt flag for PWM match channel 4." /> + <BitField start="9" size="1" name="PWMMR5INT" description="Interrupt flag for PWM match channel 5." /> + <BitField start="10" size="1" name="PWMMR6INT" description="Interrupt flag for PWM match channel 6." /> + <BitField start="11" size="21" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x004" size="4" name="TCR" access="Read/Write" description="Timer Control Register. The TCR is used to control the Timer Counter functions." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="CE" description="Counter Enable"> + <Enum name="THE_PWM_TIMER_COUNTE" start="1" description="The PWM Timer Counter and PWM Prescale Counter are enabled for counting." /> + <Enum name="THE_COUNTERS_ARE_DIS" start="0" description="The counters are disabled." /> + </BitField> + <BitField start="1" size="1" name="CR" description="Counter Reset"> + <Enum name="THE_PWM_TIMER_COUNTE" start="1" description="The PWM Timer Counter and the PWM Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until this bit is returned to zero." /> + <Enum name="CLEAR_RESET_" start="0" description="Clear reset." /> + </BitField> + <BitField start="2" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="3" size="1" name="PWMEN" description="PWM Enable"> + <Enum name="PWM_MODE_IS_ENABLED_" start="1" description="PWM mode is enabled (counter resets to 1). PWM mode causes the shadow registers to operate in connection with the Match registers. A program write to a Match register will not have an effect on the Match result until the corresponding bit in PWMLER has been set, followed by the occurrence of a PWM Match 0 event. Note that the PWM Match register that determines the PWM rate (PWM Match Register 0 - MR0) must be set up prior to the PWM being enabled. Otherwise a Match event will not occur to cause shadow register contents to become effective." /> + <Enum name="TIMER_MODE_IS_ENABLE" start="0" description="Timer mode is enabled (counter resets to 0)." /> + </BitField> + <BitField start="4" size="1" name="MDIS" description="Master Disable (PWM0 only). The two PWMs may be synchronized using the Master Disable control bit. The Master disable bit of the Master PWM (PWM0 module) controls a secondary enable input to both PWMs, as shown in Figure 141. This bit has no function in the Slave PWM (PWM1)."> + <Enum name="MASTER_USE_PWM0_IS_" start="1" description="Master use. PWM0 is the master, and both PWMs are enabled for counting." /> + <Enum name="INDIVIDUAL_USE_THE_" start="0" description="Individual use. The PWMs are used independently, and the individual Counter Enable bits are used to control the PWMs." /> + </BitField> + <BitField start="5" size="27" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x008" size="4" name="TC" access="Read/Write" description="Timer Counter. The 32 bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="TC" description="Timer counter value." /> + </Register> + <Register start="+0x00C" size="4" name="PR" access="Read/Write" description="Prescale Register. Determines how often the PWM counter is incremented." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="PM" description="Prescale counter maximum value." /> + </Register> + <Register start="+0x010" size="4" name="PC" access="Read/Write" description="Prescale Counter. Prescaler for the main PWM counter." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="PC" description="Prescale counter value." /> + </Register> + <Register start="+0x014" size="4" name="MCR" access="Read/Write" description="Match Control Register. The MCR is used to control whether an interrupt is generated and if the PWM counter is reset when a Match occurs." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="PWMMR0I" description="Interrupt PWM0"> + <Enum name="DISABLED_" start="0" description="Disabled." /> + <Enum name="INTERRUPT_ON_PWMMR0" start="1" description="Interrupt on PWMMR0: an interrupt is generated when PWMMR0 matches the value in the PWMTC." /> + </BitField> + <BitField start="1" size="1" name="PWMMR0R" description="Reset PWM0"> + <Enum name="DISABLED_" start="0" description="Disabled." /> + <Enum name="RESET_ON_PWMMR0_THE" start="1" description="Reset on PWMMR0: the PWMTC will be reset if PWMMR0 matches it." /> + </BitField> + <BitField start="2" size="1" name="PWMMR0S" description="Stop PWM0"> + <Enum name="DISABLED" start="0" description="Disabled" /> + <Enum name="STOP_ON_PWMMR0_THE_" start="1" description="Stop on PWMMR0: the PWMTC and PWMPC will be stopped and PWMTCR bit 0 will be set to 0 if PWMMR0 matches the PWMTC." /> + </BitField> + <BitField start="3" size="1" name="PWMMR1I" description="Interrupt PWM1"> + <Enum name="DISABLED_" start="0" description="Disabled." /> + <Enum name="INTERRUPT_ON_PWMMR1" start="1" description="Interrupt on PWMMR1: an interrupt is generated when PWMMR1 matches the value in the PWMTC." /> + </BitField> + <BitField start="4" size="1" name="PWMMR1R" description="Reset PWM1"> + <Enum name="DISABLED_" start="0" description="Disabled." /> + <Enum name="RESET_ON_PWMMR1_THE" start="1" description="Reset on PWMMR1: the PWMTC will be reset if PWMMR1 matches it." /> + </BitField> + <BitField start="5" size="1" name="PWMMR1S" description="Stop PWM1"> + <Enum name="DISABLED" start="0" description="Disabled" /> + <Enum name="STOP_ON_PWMMR1_THE_" start="1" description="Stop on PWMMR1: the PWMTC and PWMPC will be stopped and PWMTCR bit 0 will be set to 0 if PWMMR1 matches the PWMTC." /> + </BitField> + <BitField start="6" size="1" name="PWMMR2I" description="Interrupt PWM0"> + <Enum name="DISABLED_" start="0" description="Disabled." /> + <Enum name="INTERRUPT_ON_PWMMR2" start="1" description="Interrupt on PWMMR2: an interrupt is generated when PWMMR2 matches the value in the PWMTC." /> + </BitField> + <BitField start="7" size="1" name="PWMMR2R" description="Reset PWM0"> + <Enum name="DISABLED_" start="0" description="Disabled." /> + <Enum name="RESET_ON_PWMMR2_THE" start="1" description="Reset on PWMMR2: the PWMTC will be reset if PWMMR2 matches it." /> + </BitField> + <BitField start="8" size="1" name="PWMMR2S" description="Stop PWM0"> + <Enum name="DISABLED" start="0" description="Disabled" /> + <Enum name="STOP_ON_PWMMR2_THE_" start="1" description="Stop on PWMMR2: the PWMTC and PWMPC will be stopped and PWMTCR bit 0 will be set to 0 if PWMMR0 matches the PWMTC." /> + </BitField> + <BitField start="9" size="1" name="PWMMR3I" description="Interrupt PWM3"> + <Enum name="DISABLED_" start="0" description="Disabled." /> + <Enum name="INTERRUPT_ON_PWMMR3" start="1" description="Interrupt on PWMMR3: an interrupt is generated when PWMMR3 matches the value in the PWMTC." /> + </BitField> + <BitField start="10" size="1" name="PWMMR3R" description="Reset PWM3"> + <Enum name="DISABLED_" start="0" description="Disabled." /> + <Enum name="RESET_ON_PWMMR3_THE" start="1" description="Reset on PWMMR3: the PWMTC will be reset if PWMMR3 matches it." /> + </BitField> + <BitField start="11" size="1" name="PWMMR3S" description="Stop PWM0"> + <Enum name="DISABLED" start="0" description="Disabled" /> + <Enum name="STOP_ON_PWMMR3_THE_" start="1" description="Stop on PWMMR3: the PWMTC and PWMPC will be stopped and PWMTCR bit 0 will be set to 0 if PWMMR0 matches the PWMTC." /> + </BitField> + <BitField start="12" size="1" name="PWMMR4I" description="Interrupt PWM4"> + <Enum name="DISABLED_" start="0" description="Disabled." /> + <Enum name="INTERRUPT_ON_PWMMR4" start="1" description="Interrupt on PWMMR4: an interrupt is generated when PWMMR4 matches the value in the PWMTC." /> + </BitField> + <BitField start="13" size="1" name="PWMMR4R" description="Reset PWM4"> + <Enum name="DISABLED_" start="0" description="Disabled." /> + <Enum name="RESET_ON_PWMMR4_THE" start="1" description="Reset on PWMMR4: the PWMTC will be reset if PWMMR4 matches it." /> + </BitField> + <BitField start="14" size="1" name="PWMMR4S" description="Stop PWM4"> + <Enum name="DISABLED" start="0" description="Disabled" /> + <Enum name="STOP_ON_PWMMR4_THE_" start="1" description="Stop on PWMMR4: the PWMTC and PWMPC will be stopped and PWMTCR bit 0 will be set to 0 if PWMMR4 matches the PWMTC." /> + </BitField> + <BitField start="15" size="1" name="PWMMR5I" description="Interrupt PWM5"> + <Enum name="DISABLED_" start="0" description="Disabled." /> + <Enum name="INTERRUPT_ON_PWMMR5" start="1" description="Interrupt on PWMMR5: an interrupt is generated when PWMMR5 matches the value in the PWMTC." /> + </BitField> + <BitField start="16" size="1" name="PWMMR5R" description="Reset PWM5"> + <Enum name="DISABLED_" start="0" description="Disabled." /> + <Enum name="RESET_ON_PWMMR5_THE" start="1" description="Reset on PWMMR5: the PWMTC will be reset if PWMMR5 matches it." /> + </BitField> + <BitField start="17" size="1" name="PWMMR5S" description="Stop PWM5"> + <Enum name="DISABLED" start="0" description="Disabled" /> + <Enum name="STOP_ON_PWMMR5_THE_" start="1" description="Stop on PWMMR5: the PWMTC and PWMPC will be stopped and PWMTCR bit 0 will be set to 0 if PWMMR5 matches the PWMTC." /> + </BitField> + <BitField start="18" size="1" name="PWMMR6I" description="Interrupt PWM6"> + <Enum name="DISABLED_" start="0" description="Disabled." /> + <Enum name="INTERRUPT_ON_PWMMR6" start="1" description="Interrupt on PWMMR6: an interrupt is generated when PWMMR6 matches the value in the PWMTC." /> + </BitField> + <BitField start="19" size="1" name="PWMMR6R" description="Reset PWM6"> + <Enum name="DISABLED_" start="0" description="Disabled." /> + <Enum name="RESET_ON_PWMMR6_THE" start="1" description="Reset on PWMMR6: the PWMTC will be reset if PWMMR6 matches it." /> + </BitField> + <BitField start="20" size="1" name="PWMMR6S" description="Stop PWM6"> + <Enum name="DISABLED" start="0" description="Disabled" /> + <Enum name="STOP_ON_PWMMR6_THE_" start="1" description="Stop on PWMMR6: the PWMTC and PWMPC will be stopped and PWMTCR bit 0 will be set to 0 if PWMMR6 matches the PWMTC." /> + </BitField> + <BitField start="21" size="11" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x018+0" size="4" name="MR0" access="Read/Write" description="Match Register. Match registers
are continuously compared to the PWM counter in order to control PWM
output edges." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="MATCH" description="Timer counter match value." /> + </Register> + <Register start="+0x018+4" size="4" name="MR1" access="Read/Write" description="Match Register. Match registers
are continuously compared to the PWM counter in order to control PWM
output edges." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="MATCH" description="Timer counter match value." /> + </Register> + <Register start="+0x018+8" size="4" name="MR2" access="Read/Write" description="Match Register. Match registers
are continuously compared to the PWM counter in order to control PWM
output edges." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="MATCH" description="Timer counter match value." /> + </Register> + <Register start="+0x018+12" size="4" name="MR3" access="Read/Write" description="Match Register. Match registers
are continuously compared to the PWM counter in order to control PWM
output edges." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="MATCH" description="Timer counter match value." /> + </Register> + <Register start="+0x028" size="4" name="CCR" access="Read/Write" description="Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated for a capture event." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="CAP0_R" description="Capture on PWMn_CAP0 rising edge"> + <Enum name="DISABLED_THIS_FEATU" start="0" description="Disabled. This feature is disabled." /> + <Enum name="RISING_EDGE_A_SYNCH" start="1" description="Rising edge. A synchronously sampled rising edge on PWMn_CAP0 will cause CR0 to be loaded with the contents of the TC." /> + </BitField> + <BitField start="1" size="1" name="CAP0_F" description="Capture on PWMn_CAP0 falling edge"> + <Enum name="DISABLED_THIS_FEATU" start="0" description="Disabled. This feature is disabled." /> + <Enum name="FALLING_EDGE_A_SYNC" start="1" description="Falling edge. A synchronously sampled falling edge on PWMn_CAP0 will cause CR0 to be loaded with the contents of TC." /> + </BitField> + <BitField start="2" size="1" name="CAP0_I" description="Interrupt on PWMn_CAP0 event"> + <Enum name="DISABLED_THIS_FEATU" start="0" description="Disabled. This feature is disabled." /> + <Enum name="INTERRUPT_A_CR0_LOA" start="1" description="Interrupt. A CR0 load due to a PWMn_CAP0 event will generate an interrupt." /> + </BitField> + <BitField start="3" size="1" name="CAP1_R" description="Capture on PWMn_CAP1 rising edge. Reserved for PWM0."> + <Enum name="DISABLED_THIS_FEATU" start="0" description="Disabled. This feature is disabled." /> + <Enum name="RISING_EDGE_A_SYNCH" start="1" description="Rising edge. A synchronously sampled rising edge on PWMn_CAP1 will cause CR1 to be loaded with the contents of the TC." /> + </BitField> + <BitField start="4" size="1" name="CAP1_F" description="Capture on PWMn_CAP1 falling edge. Reserved for PWM0."> + <Enum name="DISABLED_THIS_FEATU" start="0" description="Disabled. This feature is disabled." /> + <Enum name="FALLING_EDGE_A_SYNC" start="1" description="Falling edge. A synchronously sampled falling edge on PWMn_CAP1 will cause CR1 to be loaded with the contents of TC." /> + </BitField> + <BitField start="5" size="1" name="CAP1_I" description="Interrupt on PWMn_CAP1 event. Reserved for PWM0."> + <Enum name="DISABLED_THIS_FEATU" start="0" description="Disabled. This feature is disabled." /> + <Enum name="INTERRUPT_A_CR1_LOA" start="1" description="Interrupt. A CR1 load due to a PWMn_CAP1 event will generate an interrupt." /> + </BitField> + <BitField start="6" size="26" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x02C+0" size="4" name="CR[0]" access="Read/Write" description="PWM Control Register. Enables PWM outputs and selects either single edge or double edge controlled PWM outputs." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="RESERVED" description="Reserved." /> + <BitField start="2" size="1" name="PWMSEL2" description="PWM[2] output single/double edge mode control."> + <Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." /> + <Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." /> + </BitField> + <BitField start="3" size="1" name="PWMSEL3" description="PWM[3] output edge control."> + <Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." /> + <Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." /> + </BitField> + <BitField start="4" size="1" name="PWMSEL4" description="PWM[4] output edge control."> + <Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." /> + <Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." /> + </BitField> + <BitField start="5" size="1" name="PWMSEL5" description="PWM[5] output edge control."> + <Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." /> + <Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." /> + </BitField> + <BitField start="6" size="1" name="PWMSEL6" description="PWM[6] output edge control."> + <Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." /> + <Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." /> + </BitField> + <BitField start="7" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="9" size="1" name="PWMENA1" description="PWM[1] output enable control."> + <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." /> + <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." /> + </BitField> + <BitField start="10" size="1" name="PWMENA2" description="PWM[2] output enable control."> + <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." /> + <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." /> + </BitField> + <BitField start="11" size="1" name="PWMENA3" description="PWM[3] output enable control."> + <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." /> + <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." /> + </BitField> + <BitField start="12" size="1" name="PWMENA4" description="PWM[4] output enable control."> + <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." /> + <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." /> + </BitField> + <BitField start="13" size="1" name="PWMENA5" description="PWM[5] output enable control."> + <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." /> + <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." /> + </BitField> + <BitField start="14" size="1" name="PWMENA6" description="PWM[6] output enable control. See PWMENA1 for details."> + <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." /> + <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." /> + </BitField> + <BitField start="15" size="17" name="RESERVED" description="Unused, always zero." /> + </Register> + <Register start="+0x02C+4" size="4" name="CR[1]" access="Read/Write" description="PWM Control Register. Enables PWM outputs and selects either single edge or double edge controlled PWM outputs." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="RESERVED" description="Reserved." /> + <BitField start="2" size="1" name="PWMSEL2" description="PWM[2] output single/double edge mode control."> + <Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." /> + <Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." /> + </BitField> + <BitField start="3" size="1" name="PWMSEL3" description="PWM[3] output edge control."> + <Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." /> + <Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." /> + </BitField> + <BitField start="4" size="1" name="PWMSEL4" description="PWM[4] output edge control."> + <Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." /> + <Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." /> + </BitField> + <BitField start="5" size="1" name="PWMSEL5" description="PWM[5] output edge control."> + <Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." /> + <Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." /> + </BitField> + <BitField start="6" size="1" name="PWMSEL6" description="PWM[6] output edge control."> + <Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." /> + <Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." /> + </BitField> + <BitField start="7" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="9" size="1" name="PWMENA1" description="PWM[1] output enable control."> + <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." /> + <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." /> + </BitField> + <BitField start="10" size="1" name="PWMENA2" description="PWM[2] output enable control."> + <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." /> + <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." /> + </BitField> + <BitField start="11" size="1" name="PWMENA3" description="PWM[3] output enable control."> + <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." /> + <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." /> + </BitField> + <BitField start="12" size="1" name="PWMENA4" description="PWM[4] output enable control."> + <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." /> + <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." /> + </BitField> + <BitField start="13" size="1" name="PWMENA5" description="PWM[5] output enable control."> + <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." /> + <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." /> + </BitField> + <BitField start="14" size="1" name="PWMENA6" description="PWM[6] output enable control. See PWMENA1 for details."> + <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." /> + <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." /> + </BitField> + <BitField start="15" size="17" name="RESERVED" description="Unused, always zero." /> + </Register> + <Register start="+0x040+0" size="4" name="MR4" access="Read/Write" description="Match Register. Match registers
are continuously compared to the PWM counter in order to control PWM
output edges." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="MATCH" description="Timer counter match value." /> + </Register> + <Register start="+0x040+4" size="4" name="MR5" access="Read/Write" description="Match Register. Match registers
are continuously compared to the PWM counter in order to control PWM
output edges." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="MATCH" description="Timer counter match value." /> + </Register> + <Register start="+0x040+8" size="4" name="MR6" access="Read/Write" description="Match Register. Match registers
are continuously compared to the PWM counter in order to control PWM
output edges." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="MATCH" description="Timer counter match value." /> + </Register> + <Register start="+0x04C" size="4" name="PCR" access="Read/Write" description="PWM Control Register. Enables PWM outputs and selects either single edge or double edge controlled PWM outputs." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="RESERVED" description="Reserved." /> + <BitField start="2" size="1" name="PWMSEL2" description="PWM[2] output single/double edge mode control."> + <Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." /> + <Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." /> + </BitField> + <BitField start="3" size="1" name="PWMSEL3" description="PWM[3] output edge control."> + <Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." /> + <Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." /> + </BitField> + <BitField start="4" size="1" name="PWMSEL4" description="PWM[4] output edge control."> + <Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." /> + <Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." /> + </BitField> + <BitField start="5" size="1" name="PWMSEL5" description="PWM[5] output edge control."> + <Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." /> + <Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." /> + </BitField> + <BitField start="6" size="1" name="PWMSEL6" description="PWM[6] output edge control."> + <Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." /> + <Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." /> + </BitField> + <BitField start="7" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="9" size="1" name="PWMENA1" description="PWM[1] output enable control."> + <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." /> + <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." /> + </BitField> + <BitField start="10" size="1" name="PWMENA2" description="PWM[2] output enable control."> + <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." /> + <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." /> + </BitField> + <BitField start="11" size="1" name="PWMENA3" description="PWM[3] output enable control."> + <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." /> + <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." /> + </BitField> + <BitField start="12" size="1" name="PWMENA4" description="PWM[4] output enable control."> + <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." /> + <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." /> + </BitField> + <BitField start="13" size="1" name="PWMENA5" description="PWM[5] output enable control."> + <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." /> + <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." /> + </BitField> + <BitField start="14" size="1" name="PWMENA6" description="PWM[6] output enable control. See PWMENA1 for details."> + <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." /> + <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." /> + </BitField> + <BitField start="15" size="17" name="RESERVED" description="Unused, always zero." /> + </Register> + <Register start="+0x050" size="4" name="LER" access="Read/Write" description="Load Enable Register. Enables use of updated PWM match values." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="MAT0LATCHEN" description="Enable PWM Match 0 Latch. PWM MR0 register update control. Writing a one to this bit allows the last value written to the PWM Match Register 0 to be become effective when the timer is next reset by a PWM Match event. See Section 27.6.7." /> + <BitField start="1" size="1" name="MAT1LATCHEN" description="Enable PWM Match 1 Latch. PWM MR1 register update control. See bit 0 for details." /> + <BitField start="2" size="1" name="MAT2LATCHEN" description="Enable PWM Match 2 Latch. PWM MR2 register update control. See bit 0 for details." /> + <BitField start="3" size="1" name="MAT3LATCHEN" description="Enable PWM Match 3 Latch. PWM MR3 register update control. See bit 0 for details." /> + <BitField start="4" size="1" name="MAT4LATCHEN" description="Enable PWM Match 4 Latch. PWM MR4 register update control. See bit 0 for details." /> + <BitField start="5" size="1" name="MAT5LATCHEN" description="Enable PWM Match 5 Latch. PWM MR5 register update control. See bit 0 for details." /> + <BitField start="6" size="1" name="MAT6LATCHEN" description="Enable PWM Match 6 Latch. PWM MR6 register update control. See bit 0 for details." /> + <BitField start="7" size="25" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x070" size="4" name="CTCR" access="Read/Write" description="Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="MOD" description="Counter/ Timer Mode"> + <Enum name="TIMER_MODE_THE_TC_I" start="0x0" description="Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale register." /> + <Enum name="RISING_EDGE_COUNTER_" start="0x1" description="Rising edge counter Mode: the TC is incremented on rising edges of the PWM_CAP input selected by bits 3:2." /> + <Enum name="FALLING_EDGE_COUNTER" start="0x2" description="Falling edge counter Mode: the TC is incremented on falling edges of the PWM_CAP input selected by bits 3:2." /> + <Enum name="DUAL_EDGE_COUNTER_MO" start="0x3" description="Dual edge counter Mode: the TC is incremented on both edges of the PWM_CAP input selected by bits 3:2." /> + </BitField> + <BitField start="2" size="2" name="CIS" description="Count Input Select. When bits 1:0 are not 00, these bits select which PWM_CAP pin carries the signal used to increment the TC. Other combinations are reserved."> + <Enum name="FOR_PWM0_00_EQ_PWM0_" start="0x0" description="For PWM0: 00 = PWM0_CAP0 (Other combinations are reserved) For PWM1: 00 = PWM1_CAP0, 01 = PWM1_CAP1 (Other combinations are reserved)" /> + </BitField> + <BitField start="4" size="28" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + </RegisterGroup> + <RegisterGroup name="I2C0" start="0x4001C000" description="I2C bus interface"> + <Register start="+0x000" size="4" name="CONSET" access="Read/Write" description="I2C Control Set Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is set. Writing a zero has no effect on the corresponding bit in the I2C control register." reset_value="0x00" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + <BitField start="2" size="1" name="AA" description="Assert acknowledge flag." /> + <BitField start="3" size="1" name="SI" description="I2C interrupt flag." /> + <BitField start="4" size="1" name="STO" description="STOP flag." /> + <BitField start="5" size="1" name="STA" description="START flag." /> + <BitField start="6" size="1" name="I2EN" description="I2C interface enable." /> + <BitField start="7" size="25" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x004" size="4" name="STAT" access="ReadOnly" description="I2C Status Register. During I2C operation, this register provides detailed status codes that allow software to determine the next action needed." reset_value="0xF8" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="RESERVED" description="These bits are unused and are always 0." /> + <BitField start="3" size="5" name="Status" description="These bits give the actual status information about the I 2C interface." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x008" size="4" name="DAT" access="Read/Write" description="I2C Data Register. During master or slave transmit mode, data to be transmitted is written to this register. During master or slave receive mode, data that has been received may be read from this register." reset_value="0x00" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="Data" description="This register holds data values that have been received or are to be transmitted." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x00C" size="4" name="ADR0" access="Read/Write" description="I2C Slave Address Register 0. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="GC" description="General Call enable bit." /> + <BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x010" size="4" name="SCLH" access="Read/Write" description="SCH Duty Cycle Register High Half Word. Determines the high time of the I2C clock." reset_value="0x04" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="16" name="SCLH" description="Count for SCL HIGH time period selection." /> + <BitField start="16" size="16" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x014" size="4" name="SCLL" access="Read/Write" description="SCL Duty Cycle Register Low Half Word. Determines the low time of the I2C clock. SCLL and SCLH together determine the clock frequency generated by an I2C master and certain times used in slave mode." reset_value="0x04" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="16" name="SCLL" description="Count for SCL low time period selection." /> + <BitField start="16" size="16" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x018" size="4" name="CONCLR" access="WriteOnly" description="I2C Control Clear Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is cleared. Writing a zero has no effect on the corresponding bit in the I2C control register." reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="2" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + <BitField start="2" size="1" name="AAC" description="Assert acknowledge Clear bit." /> + <BitField start="3" size="1" name="SIC" description="I2C interrupt Clear bit." /> + <BitField start="4" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + <BitField start="5" size="1" name="STAC" description="START flag Clear bit." /> + <BitField start="6" size="1" name="I2ENC" description="I2C interface Disable bit." /> + <BitField start="7" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x01C" size="4" name="MMCTRL" access="Read/Write" description="Monitor mode control register." reset_value="0x00" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="MM_ENA" description="Monitor mode enable."> + <Enum name="MONITOR_MODE_DISABLE" start="0" description="Monitor mode disabled." /> + <Enum name="THE_I_2C_MODULE_WILL" start="1" description="The I 2C module will enter monitor mode. In this mode the SDA output will be forced high. This will prevent the I2C module from outputting data of any kind (including ACK) onto the I2C data bus. Depending on the state of the ENA_SCL bit, the output may be also forced high, preventing the module from having control over the I2C clock line." /> + </BitField> + <BitField start="1" size="1" name="ENA_SCL" description="SCL output enable."> + <Enum name="WHEN_THIS_BIT_IS_CLE" start="0" description="When this bit is cleared to 0, the SCL output will be forced high when the module is in monitor mode. As described above, this will prevent the module from having any control over the I2C clock line." /> + <Enum name="WHEN_THIS_BIT_IS_SET" start="1" description="When this bit is set, the I2C module may exercise the same control over the clock line that it would in normal operation. This means that, acting as a slave peripheral, the I2C module can stretch the clock line (hold it low) until it has had time to respond to an I2C interrupt.[1]" /> + </BitField> + <BitField start="2" size="1" name="MATCH_ALL" description="Select interrupt register match."> + <Enum name="WHEN_THIS_BIT_IS_CLE" start="0" description="When this bit is cleared, an interrupt will only be generated when a match occurs to one of the (up-to) four address registers described above. That is, the module will respond as a normal slave as far as address-recognition is concerned." /> + <Enum name="WHEN_THIS_BIT_IS_SET" start="1" description="When this bit is set to 1 and the I2C is in monitor mode, an interrupt will be generated on ANY address received. This will enable the part to monitor all traffic on the bus." /> + </BitField> + <BitField start="3" size="29" name="RESERVED" description="Reserved. The value read from reserved bits is not defined." /> + </Register> + <Register start="+0x020+0" size="4" name="ADR1" access="Read/Write" description="I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="GC" description="General Call enable bit." /> + <BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x020+4" size="4" name="ADR2" access="Read/Write" description="I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="GC" description="General Call enable bit." /> + <BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x020+8" size="4" name="ADR3" access="Read/Write" description="I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="GC" description="General Call enable bit." /> + <BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x02C" size="4" name="DATA_BUFFER" access="ReadOnly" description="Data buffer register. The contents of the 8 MSBs of the DAT shift register will be transferred to the DATA_BUFFER automatically after every nine bits (8 bits of data plus ACK or NACK) has been received on the bus." reset_value="0x00" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="Data" description="This register holds contents of the 8 MSBs of the DAT shift register." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x030+0" size="4" name="MASK[0]" access="Read/Write" description="I2C Slave address mask register" reset_value="0x00" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." /> + <BitField start="1" size="7" name="MASK" description="Mask bits." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x030+4" size="4" name="MASK[1]" access="Read/Write" description="I2C Slave address mask register" reset_value="0x00" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." /> + <BitField start="1" size="7" name="MASK" description="Mask bits." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x030+8" size="4" name="MASK[2]" access="Read/Write" description="I2C Slave address mask register" reset_value="0x00" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." /> + <BitField start="1" size="7" name="MASK" description="Mask bits." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x030+12" size="4" name="MASK[3]" access="Read/Write" description="I2C Slave address mask register" reset_value="0x00" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." /> + <BitField start="1" size="7" name="MASK" description="Mask bits." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + </RegisterGroup> + <RegisterGroup name="SPI" start="0x40020000" description="SPI "> + <Register start="+0x000" size="4" name="CR" access="Read/Write" description="SPI Control Register. This register controls the operation of the SPI." reset_value="0x00" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + <BitField start="2" size="1" name="BITENABLE" description="The SPI controller sends and receives 8 bits of data per transfer."> + <Enum name="THE_SPI_CONTROLLER_S" start="1" description="The SPI controller sends and receives the number of bits selected by bits 11:8." /> + </BitField> + <BitField start="3" size="1" name="CPHA" description="Clock phase control determines the relationship between the data and the clock on SPI transfers, and controls when a slave transfer is defined as starting and ending."> + <Enum name="FIRST_EDGE" start="0" description="Data is sampled on the first clock edge of SCK. A transfer starts and ends with activation and deactivation of the SSEL signal." /> + <Enum name="SECOND_EDGE" start="1" description="Data is sampled on the second clock edge of the SCK. A transfer starts with the first clock edge, and ends with the last sampling edge when the SSEL signal is active." /> + </BitField> + <BitField start="4" size="1" name="CPOL" description="Clock polarity control."> + <Enum name="SCK_IS_ACTIVE_HIGH_" start="0" description="SCK is active high." /> + <Enum name="SCK_IS_ACTIVE_LOW_" start="1" description="SCK is active low." /> + </BitField> + <BitField start="5" size="1" name="MSTR" description="Master mode select."> + <Enum name="SLAVE" start="0" description="The SPI operates in Slave mode." /> + <Enum name="MASTER" start="1" description="The SPI operates in Master mode." /> + </BitField> + <BitField start="6" size="1" name="LSBF" description="LSB First controls which direction each byte is shifted when transferred."> + <Enum name="MSB" start="0" description="SPI data is transferred MSB (bit 7) first." /> + <Enum name="LSB" start="1" description="SPI data is transferred LSB (bit 0) first." /> + </BitField> + <BitField start="7" size="1" name="SPIE" description="Serial peripheral interrupt enable."> + <Enum name="INTBLOCK" start="0" description="SPI interrupts are inhibited." /> + <Enum name="HWINT" start="1" description="A hardware interrupt is generated each time the SPIF or MODF bits are activated." /> + </BitField> + <BitField start="8" size="4" name="BITS" description="When bit 2 of this register is 1, this field controls the number of bits per transfer:"> + <Enum name="8_BITS_PER_TRANSFER" start="0x8" description="8 bits per transfer" /> + <Enum name="9_BITS_PER_TRANSFER" start="0x9" description="9 bits per transfer" /> + <Enum name="10_BITS_PER_TRANSFER" start="0xA" description="10 bits per transfer" /> + <Enum name="11_BITS_PER_TRANSFER" start="0xB" description="11 bits per transfer" /> + <Enum name="12_BITS_PER_TRANSFER" start="0xC" description="12 bits per transfer" /> + <Enum name="13_BITS_PER_TRANSFER" start="0xD" description="13 bits per transfer" /> + <Enum name="14_BITS_PER_TRANSFER" start="0xE" description="14 bits per transfer" /> + <Enum name="15_BITS_PER_TRANSFER" start="0xF" description="15 bits per transfer" /> + <Enum name="16_BITS_PER_TRANSFER" start="0x0" description="16 bits per transfer" /> + </BitField> + <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x004" size="4" name="SR" access="ReadOnly" description="SPI Status Register. This register shows the status of the SPI." reset_value="0x00" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + <BitField start="3" size="1" name="ABRT" description="Slave abort. When 1, this bit indicates that a slave abort has occurred. This bit is cleared by reading this register." /> + <BitField start="4" size="1" name="MODF" description="Mode fault. when 1, this bit indicates that a Mode fault error has occurred. This bit is cleared by reading this register, then writing the SPI0 control register." /> + <BitField start="5" size="1" name="ROVR" description="Read overrun. When 1, this bit indicates that a read overrun has occurred. This bit is cleared by reading this register." /> + <BitField start="6" size="1" name="WCOL" description="Write collision. When 1, this bit indicates that a write collision has occurred. This bit is cleared by reading this register, then accessing the SPI Data Register." /> + <BitField start="7" size="1" name="SPIF" description="SPI transfer complete flag. When 1, this bit indicates when a SPI data transfer is complete. When a master, this bit is set at the end of the last cycle of the transfer. When a slave, this bit is set on the last data sampling edge of the SCK. This bit is cleared by first reading this register, then accessing the SPI Data Register. Note: this is not the SPI interrupt flag. This flag is found in the SPINT register." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x008" size="4" name="DR" access="None" description="SPI Data Register. This bi-directional register provides the transmit and receive data for the SPI. Transmit data is provided to the SPI0 by writing to this register. Data received by the SPI0 can be read from this register." reset_value="0x00" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="DATALOW" description="SPI Bi-directional data port." /> + <BitField start="8" size="8" name="DATAHIGH" description="If bit 2 of the SPCR is 1 and bits 11:8 are other than 1000, some or all of these bits contain the additional transmit and receive bits. When less than 16 bits are selected, the more significant among these bits read as zeroes." /> + <BitField start="16" size="16" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x00C" size="4" name="CCR" access="Read/Write" description="SPI Clock Counter Register. This register controls the frequency of a master's SCK0." reset_value="0x00" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="COUNTER" description="SPI0 Clock counter setting." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x01C" size="4" name="INT" access="Read/Write" description="SPI Interrupt Flag. This register contains the interrupt flag for the SPI interface." reset_value="0x00" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="SPIF" description="SPI interrupt flag. Set by the SPI interface to generate an interrupt. Cleared by writing a 1 to this bit. Note: this bit will be set once when SPIE = 1 and at least one of SPIF and WCOL bits is 1. However, only when the SPI Interrupt bit is set and SPI0 Interrupt is enabled in the NVIC, SPI based interrupt can be processed by interrupt handling software." /> + <BitField start="1" size="7" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + </RegisterGroup> + <RegisterGroup name="RTC" start="0x40024000" description=" Real Time Clock (RTC) "> + <Register start="+0x000" size="4" name="ILR" access="Read/Write" description="Interrupt Location Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RTCCIF" description="When one, the Counter Increment Interrupt block generated an interrupt. Writing a one to this bit location clears the counter increment interrupt." /> + <BitField start="1" size="1" name="RTCALF" description="When one, the alarm registers generated an interrupt. Writing a one to this bit location clears the alarm interrupt." /> + <BitField start="21" size="11" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x008" size="4" name="CCR" access="Read/Write" description="Clock Control Register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="CLKEN" description="Clock Enable."> + <Enum name="THE_TIME_COUNTERS_AR" start="1" description="The time counters are enabled." /> + <Enum name="THE_TIME_COUNTERS_AR" start="0" description="The time counters are disabled so that they may be initialized." /> + </BitField> + <BitField start="1" size="1" name="CTCRST" description="CTC Reset."> + <Enum name="RESET" start="1" description="When one, the elements in the internal oscillator divider are reset, and remain reset until CCR[1] is changed to zero. This is the divider that generates the 1 Hz clock from the 32.768 kHz crystal. The state of the divider is not visible to software." /> + <Enum name="NO_EFFECT_" start="0" description="No effect." /> + </BitField> + <BitField start="2" size="2" name="RESERVED" description="Internal test mode controls. These bits must be 0 for normal RTC operation." /> + <BitField start="4" size="1" name="CCALEN" description="Calibration counter enable."> + <Enum name="THE_CALIBRATION_COUN" start="1" description="The calibration counter is disabled and reset to zero." /> + <Enum name="THE_CALIBRATION_COUN" start="0" description="The calibration counter is enabled and counting, using the 1 Hz clock. When the calibration counter is equal to the value of the CALIBRATION register, the counter resets and repeats counting up to the value of the CALIBRATION register. See Section 30.6.4.2 and Section 30.6.5." /> + </BitField> + <BitField start="5" size="27" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x00C" size="4" name="CIIR" access="Read/Write" description="Counter Increment Interrupt Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="IMSEC" description="When 1, an increment of the Second value generates an interrupt." /> + <BitField start="1" size="1" name="IMMIN" description="When 1, an increment of the Minute value generates an interrupt." /> + <BitField start="2" size="1" name="IMHOUR" description="When 1, an increment of the Hour value generates an interrupt." /> + <BitField start="3" size="1" name="IMDOM" description="When 1, an increment of the Day of Month value generates an interrupt." /> + <BitField start="4" size="1" name="IMDOW" description="When 1, an increment of the Day of Week value generates an interrupt." /> + <BitField start="5" size="1" name="IMDOY" description="When 1, an increment of the Day of Year value generates an interrupt." /> + <BitField start="6" size="1" name="IMMON" description="When 1, an increment of the Month value generates an interrupt." /> + <BitField start="7" size="1" name="IMYEAR" description="When 1, an increment of the Year value generates an interrupt." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x010" size="4" name="AMR" access="Read/Write" description="Alarm Mask Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="AMRSEC" description="When 1, the Second value is not compared for the alarm." /> + <BitField start="1" size="1" name="AMRMIN" description="When 1, the Minutes value is not compared for the alarm." /> + <BitField start="2" size="1" name="AMRHOUR" description="When 1, the Hour value is not compared for the alarm." /> + <BitField start="3" size="1" name="AMRDOM" description="When 1, the Day of Month value is not compared for the alarm." /> + <BitField start="4" size="1" name="AMRDOW" description="When 1, the Day of Week value is not compared for the alarm." /> + <BitField start="5" size="1" name="AMRDOY" description="When 1, the Day of Year value is not compared for the alarm." /> + <BitField start="6" size="1" name="AMRMON" description="When 1, the Month value is not compared for the alarm." /> + <BitField start="7" size="1" name="AMRYEAR" description="When 1, the Year value is not compared for the alarm." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x014" size="4" name="CTIME0" access="ReadOnly" description="Consolidated Time Register 0" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="6" name="SECONDS" description="Seconds value in the range of 0 to 59" /> + <BitField start="6" size="2" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + <BitField start="8" size="6" name="MINUTES" description="Minutes value in the range of 0 to 59" /> + <BitField start="14" size="2" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + <BitField start="16" size="5" name="HOURS" description="Hours value in the range of 0 to 23" /> + <BitField start="21" size="3" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + <BitField start="24" size="3" name="DOW" description="Day of week value in the range of 0 to 6" /> + <BitField start="27" size="5" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x018" size="4" name="CTIME1" access="ReadOnly" description="Consolidated Time Register 1" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="5" name="DOM" description="Day of month value in the range of 1 to 28, 29, 30, or 31 (depending on the month and whether it is a leap year)." /> + <BitField start="5" size="3" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + <BitField start="8" size="4" name="MONTH" description="Month value in the range of 1 to 12." /> + <BitField start="12" size="4" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + <BitField start="16" size="12" name="YEAR" description="Year value in the range of 0 to 4095." /> + <BitField start="28" size="4" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x01C" size="4" name="CTIME2" access="ReadOnly" description="Consolidated Time Register 2" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="12" name="DOY" description="Day of year value in the range of 1 to 365 (366 for leap years)." /> + <BitField start="12" size="20" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x020" size="4" name="SEC" access="Read/Write" description="Seconds Counter" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="6" name="SECONDS" description="Seconds value in the range of 0 to 59" /> + <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x024" size="4" name="MIN" access="Read/Write" description="Minutes Register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="6" name="MINUTES" description="Minutes value in the range of 0 to 59" /> + <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x028" size="4" name="HRS" access="Read/Write" description="Hours Register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="5" name="HOURS" description="Hours value in the range of 0 to 23" /> + <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x02C" size="4" name="DOM" access="Read/Write" description="Day of Month Register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="5" name="DOM" description="Day of month value in the range of 1 to 28, 29, 30, or 31 (depending on the month and whether it is a leap year)." /> + <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x030" size="4" name="DOW" access="Read/Write" description="Day of Week Register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="3" name="DOW" description="Day of week value in the range of 0 to 6." /> + <BitField start="3" size="29" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x034" size="4" name="DOY" access="Read/Write" description="Day of Year Register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="9" name="DOY" description="Day of year value in the range of 1 to 365 (366 for leap years)." /> + <BitField start="9" size="23" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x038" size="4" name="MONTH" access="Read/Write" description="Months Register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="4" name="MONTH" description="Month value in the range of 1 to 12." /> + <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x03C" size="4" name="YEAR" access="Read/Write" description="Years Register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="12" name="YEAR" description="Year value in the range of 0 to 4095." /> + <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x040" size="4" name="CALIBRATION" access="Read/Write" description="Calibration Value Register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="17" name="CALVAL" description="If enabled, the calibration counter counts up to this value. The maximum value is 131, 072 corresponding to about 36.4 hours. Calibration is disabled if CALVAL = 0." /> + <BitField start="17" size="1" name="CALDIR" description="Calibration direction"> + <Enum name="BACKWARD_CALIBRATION" start="1" description="Backward calibration. When CALVAL is equal to the calibration counter, the RTC timers will stop incrementing for 1 second." /> + <Enum name="FORWARD_CALIBRATION_" start="0" description="Forward calibration. When CALVAL is equal to the calibration counter, the RTC timers will jump by 2 seconds." /> + </BitField> + </Register> + <Register start="+0x044+0" size="4" name="GPREG0" access="Read/Write" description="General Purpose Register 0" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="GP" description="General purpose storage." /> + </Register> + <Register start="+0x044+4" size="4" name="GPREG1" access="Read/Write" description="General Purpose Register 0" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="GP" description="General purpose storage." /> + </Register> + <Register start="+0x044+8" size="4" name="GPREG2" access="Read/Write" description="General Purpose Register 0" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="GP" description="General purpose storage." /> + </Register> + <Register start="+0x044+12" size="4" name="GPREG3" access="Read/Write" description="General Purpose Register 0" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="GP" description="General purpose storage." /> + </Register> + <Register start="+0x044+16" size="4" name="GPREG4" access="Read/Write" description="General Purpose Register 0" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="GP" description="General purpose storage." /> + </Register> + <Register start="+0x05C" size="4" name="RTC_AUX" access="Read/Write" description="RTC Auxiliary control register" reset_value="0x10" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="4" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="4" size="1" name="RTC_OSCF" description="RTC Oscillator Fail detect flag. Read: this bit is set if the RTC oscillator stops, and when RTC power is first turned on. An interrupt will occur when this bit is set, the RTC_OSCFEN bit in RTC_AUXEN is a 1, and the RTC interrupt is enabled in the NVIC. Write: writing a 1 to this bit clears the flag." /> + <BitField start="5" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="6" size="1" name="RTC_PDOUT" description="When 0: the RTC_ALARM pin reflects the RTC alarm status. When 1: the RTC_ALARM pin indicates Deep Power-down mode." /> + <BitField start="7" size="25" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x058" size="4" name="RTC_AUXEN" access="Read/Write" description="RTC Auxiliary Enable register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="4" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="4" size="1" name="RTC_OSCFEN" description="Oscillator Fail Detect interrupt enable. When 0: the RTC Oscillator Fail detect interrupt is disabled. When 1: the RTC Oscillator Fail detect interrupt is enabled. See Section 30.6.2.5." /> + <BitField start="5" size="27" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x060" size="4" name="ASEC" access="Read/Write" description="Alarm value for Seconds" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="6" name="SECONDS" description="Seconds value in the range of 0 to 59" /> + <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x64" size="4" name="AMIN" access="Read/Write" description="Alarm value for Minutes" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="6" name="MINUTES" description="Minutes value in the range of 0 to 59" /> + <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x068" size="4" name="AHRS" access="Read/Write" description="Alarm value for Hours" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="5" name="HOURS" description="Hours value in the range of 0 to 23" /> + <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x06C" size="4" name="ADOM" access="Read/Write" description="Alarm value for Day of Month" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="5" name="DOM" description="Day of month value in the range of 1 to 28, 29, 30, or 31 (depending on the month and whether it is a leap year)." /> + <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x070" size="4" name="ADOW" access="Read/Write" description="Alarm value for Day of Week" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="3" name="DOW" description="Day of week value in the range of 0 to 6." /> + <BitField start="3" size="29" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x074" size="4" name="ADOY" access="Read/Write" description="Alarm value for Day of Year" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="9" name="DOY" description="Day of year value in the range of 1 to 365 (366 for leap years)." /> + <BitField start="9" size="23" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x078" size="4" name="AMON" access="Read/Write" description="Alarm value for Months" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="4" name="MONTH" description="Month value in the range of 1 to 12." /> + <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x07C" size="4" name="AYRS" access="Read/Write" description="Alarm value for Year" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="12" name="YEAR" description="Year value in the range of 0 to 4095." /> + <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + </RegisterGroup> + <RegisterGroup name="GPIOINT" start="0x40028080" description="GPIO"> + <Register start="+0x000" size="4" name="STATUS" access="ReadOnly" description="GPIO overall Interrupt Status." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="P0INT" description="Port 0 GPIO interrupt pending."> + <Enum name="NO_PENDING_INTERRUPT" start="0" description="No pending interrupts on Port 0." /> + <Enum name="AT_LEAST_ONE_PENDING" start="1" description="At least one pending interrupt on Port 0." /> + </BitField> + <BitField start="1" size="1" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + <BitField start="2" size="1" name="P2INT" description="Port 2 GPIO interrupt pending."> + <Enum name="NO_PENDING_INTERRUPT" start="0" description="No pending interrupts on Port 2." /> + <Enum name="AT_LEAST_ONE_PENDING" start="1" description="At least one pending interrupt on Port 2." /> + </BitField> + <BitField start="2" size="30" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x004" size="4" name="STATR0" access="ReadOnly" description="GPIO Interrupt Status for Rising edge for Port 0." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="P0_0REI" description="Status of Rising Edge Interrupt for P0[0]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." /> + <BitField start="1" size="1" name="P0_1REI" description="Status of Rising Edge Interrupt for P0[1]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." /> + <BitField start="2" size="1" name="P0_2REI" description="Status of Rising Edge Interrupt for P0[2]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." /> + <BitField start="3" size="1" name="P0_3REI" description="Status of Rising Edge Interrupt for P0[3]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." /> + <BitField start="4" size="1" name="P0_4REI" description="Status of Rising Edge Interrupt for P0[4]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." /> + <BitField start="5" size="1" name="P0_5REI" description="Status of Rising Edge Interrupt for P0[5]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." /> + <BitField start="6" size="1" name="P0_6REI" description="Status of Rising Edge Interrupt for P0[6]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." /> + <BitField start="7" size="1" name="P0_7REI" description="Status of Rising Edge Interrupt for P0[7]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." /> + <BitField start="8" size="1" name="P0_8REI" description="Status of Rising Edge Interrupt for P0[8]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." /> + <BitField start="9" size="1" name="P0_9REI" description="Status of Rising Edge Interrupt for P0[9]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." /> + <BitField start="10" size="1" name="P0_10REI" description="Status of Rising Edge Interrupt for P0[10]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." /> + <BitField start="11" size="1" name="P0_11REI" description="Status of Rising Edge Interrupt for P0[11]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." /> + <BitField start="12" size="1" name="P0_12REI" description="Status of Rising Edge Interrupt for P0[12]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." /> + <BitField start="13" size="1" name="P0_13REI" description="Status of Rising Edge Interrupt for P0[13]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." /> + <BitField start="14" size="1" name="P0_14REI" description="Status of Rising Edge Interrupt for P0[14]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." /> + <BitField start="15" size="1" name="P0_15REI" description="Status of Rising Edge Interrupt for P0[15]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." /> + <BitField start="16" size="1" name="P0_16REI" description="Status of Rising Edge Interrupt for P0[16]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." /> + <BitField start="17" size="1" name="P0_17REI" description="Status of Rising Edge Interrupt for P0[17]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." /> + <BitField start="18" size="1" name="P0_18REI" description="Status of Rising Edge Interrupt for P0[18]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." /> + <BitField start="19" size="1" name="P0_19REI" description="Status of Rising Edge Interrupt for P0[19]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." /> + <BitField start="20" size="1" name="P0_20REI" description="Status of Rising Edge Interrupt for P0[20]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." /> + <BitField start="21" size="1" name="P0_21REI" description="Status of Rising Edge Interrupt for P0[21]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." /> + <BitField start="22" size="1" name="P0_22REI" description="Status of Rising Edge Interrupt for P0[22]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." /> + <BitField start="23" size="1" name="P0_23REI" description="Status of Rising Edge Interrupt for P0[23]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." /> + <BitField start="24" size="1" name="P0_24REI" description="Status of Rising Edge Interrupt for P0[24]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." /> + <BitField start="25" size="1" name="P0_25REI" description="Status of Rising Edge Interrupt for P0[25]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." /> + <BitField start="26" size="1" name="P0_26REI" description="Status of Rising Edge Interrupt for P0[26]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." /> + <BitField start="27" size="1" name="P0_27REI" description="Status of Rising Edge Interrupt for P0[27]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." /> + <BitField start="28" size="1" name="P0_28REI" description="Status of Rising Edge Interrupt for P0[28]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." /> + <BitField start="29" size="1" name="P0_29REI" description="Status of Rising Edge Interrupt for P0[29]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." /> + <BitField start="30" size="1" name="P0_30REI" description="Status of Rising Edge Interrupt for P0[30]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." /> + <BitField start="31" size="1" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x008" size="4" name="STATF0" access="ReadOnly" description="GPIO Interrupt Status for Falling edge for Port 0." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="P0_0FEI" description="Status of Falling Edge Interrupt for P0[0]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." /> + <BitField start="1" size="1" name="P0_1FEI" description="Status of Falling Edge Interrupt for P0[1]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." /> + <BitField start="2" size="1" name="P0_2FEI" description="Status of Falling Edge Interrupt for P0[2]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." /> + <BitField start="3" size="1" name="P0_3FEI" description="Status of Falling Edge Interrupt for P0[3]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." /> + <BitField start="4" size="1" name="P0_4FEI" description="Status of Falling Edge Interrupt for P0[4]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." /> + <BitField start="5" size="1" name="P0_5FEI" description="Status of Falling Edge Interrupt for P0[5]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." /> + <BitField start="6" size="1" name="P0_6FEI" description="Status of Falling Edge Interrupt for P0[6]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." /> + <BitField start="7" size="1" name="P0_7FEI" description="Status of Falling Edge Interrupt for P0[7]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." /> + <BitField start="8" size="1" name="P0_8FEI" description="Status of Falling Edge Interrupt for P0[8]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." /> + <BitField start="9" size="1" name="P0_9FEI" description="Status of Falling Edge Interrupt for P0[9]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." /> + <BitField start="10" size="1" name="P0_10FEI" description="Status of Falling Edge Interrupt for P0[10]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." /> + <BitField start="11" size="1" name="P0_11FEI" description="Status of Falling Edge Interrupt for P0[11]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." /> + <BitField start="12" size="1" name="P0_12FEI" description="Status of Falling Edge Interrupt for P0[12]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." /> + <BitField start="13" size="1" name="P0_13FEI" description="Status of Falling Edge Interrupt for P0[13]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." /> + <BitField start="14" size="1" name="P0_14FEI" description="Status of Falling Edge Interrupt for P0[14]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." /> + <BitField start="15" size="1" name="P0_15FEI" description="Status of Falling Edge Interrupt for P0[15]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." /> + <BitField start="16" size="1" name="P0_16FEI" description="Status of Falling Edge Interrupt for P0[16]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." /> + <BitField start="17" size="1" name="P0_17FEI" description="Status of Falling Edge Interrupt for P0[17]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." /> + <BitField start="18" size="1" name="P0_18FEI" description="Status of Falling Edge Interrupt for P0[18]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." /> + <BitField start="19" size="1" name="P0_19FEI" description="Status of Falling Edge Interrupt for P0[19]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." /> + <BitField start="20" size="1" name="P0_20FEI" description="Status of Falling Edge Interrupt for P0[20]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." /> + <BitField start="21" size="1" name="P0_21FEI" description="Status of Falling Edge Interrupt for P0[21]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." /> + <BitField start="22" size="1" name="P0_22FEI" description="Status of Falling Edge Interrupt for P0[22]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." /> + <BitField start="23" size="1" name="P0_23FEI" description="Status of Falling Edge Interrupt for P0[23]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." /> + <BitField start="24" size="1" name="P0_24FEI" description="Status of Falling Edge Interrupt for P0[24]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." /> + <BitField start="25" size="1" name="P0_25FEI" description="Status of Falling Edge Interrupt for P0[25]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." /> + <BitField start="26" size="1" name="P0_26FEI" description="Status of Falling Edge Interrupt for P0[26]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." /> + <BitField start="27" size="1" name="P0_27FEI" description="Status of Falling Edge Interrupt for P0[27]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." /> + <BitField start="28" size="1" name="P0_28FEI" description="Status of Falling Edge Interrupt for P0[28]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." /> + <BitField start="29" size="1" name="P0_29FEI" description="Status of Falling Edge Interrupt for P0[29]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." /> + <BitField start="30" size="1" name="P0_30FEI" description="Status of Falling Edge Interrupt for P0[30]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." /> + <BitField start="31" size="1" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x00C" size="4" name="CLR0" access="WriteOnly" description="GPIO Interrupt Clear." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="P0_0CI" description="Clear GPIO port Interrupts for P0[0]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." /> + <BitField start="1" size="1" name="P0_1CI" description="Clear GPIO port Interrupts for P0[1]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." /> + <BitField start="2" size="1" name="P0_2CI" description="Clear GPIO port Interrupts for P0[2]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." /> + <BitField start="3" size="1" name="P0_3CI" description="Clear GPIO port Interrupts for P0[3]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." /> + <BitField start="4" size="1" name="P0_4CI" description="Clear GPIO port Interrupts for P0[4]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." /> + <BitField start="5" size="1" name="P0_5CI" description="Clear GPIO port Interrupts for P0[5]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." /> + <BitField start="6" size="1" name="P0_6CI" description="Clear GPIO port Interrupts for P0[6]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." /> + <BitField start="7" size="1" name="P0_7CI" description="Clear GPIO port Interrupts for P0[7]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." /> + <BitField start="8" size="1" name="P0_8CI" description="Clear GPIO port Interrupts for P0[8]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." /> + <BitField start="9" size="1" name="P0_9CI" description="Clear GPIO port Interrupts for P0[9]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." /> + <BitField start="10" size="1" name="P0_10CI" description="Clear GPIO port Interrupts for P0[10]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." /> + <BitField start="11" size="1" name="P0_11CI" description="Clear GPIO port Interrupts for P0[11]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." /> + <BitField start="12" size="1" name="P0_12CI" description="Clear GPIO port Interrupts for P0[12]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." /> + <BitField start="13" size="1" name="P0_13CI" description="Clear GPIO port Interrupts for P0[13]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." /> + <BitField start="14" size="1" name="P0_14CI" description="Clear GPIO port Interrupts for P0[14]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." /> + <BitField start="15" size="1" name="P0_15CI" description="Clear GPIO port Interrupts for P0[15]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." /> + <BitField start="16" size="1" name="P0_16CI" description="Clear GPIO port Interrupts for P0[16]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." /> + <BitField start="17" size="1" name="P0_17CI" description="Clear GPIO port Interrupts for P0[17]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." /> + <BitField start="18" size="1" name="P0_18CI" description="Clear GPIO port Interrupts for P0[18]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." /> + <BitField start="19" size="1" name="P0_19CI" description="Clear GPIO port Interrupts for P0[19]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." /> + <BitField start="20" size="1" name="P0_20CI" description="Clear GPIO port Interrupts for P0[20]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." /> + <BitField start="21" size="1" name="P0_21CI" description="Clear GPIO port Interrupts for P0[21]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." /> + <BitField start="22" size="1" name="P0_22CI" description="Clear GPIO port Interrupts for P0[22]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." /> + <BitField start="23" size="1" name="P0_23CI" description="Clear GPIO port Interrupts for P0[23]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." /> + <BitField start="24" size="1" name="P0_24CI" description="Clear GPIO port Interrupts for P0[24]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." /> + <BitField start="25" size="1" name="P0_25CI" description="Clear GPIO port Interrupts for P0[25]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." /> + <BitField start="26" size="1" name="P0_26CI" description="Clear GPIO port Interrupts for P0[26]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." /> + <BitField start="27" size="1" name="P0_27CI" description="Clear GPIO port Interrupts for P0[27]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." /> + <BitField start="28" size="1" name="P0_28CI" description="Clear GPIO port Interrupts for P0[28]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." /> + <BitField start="29" size="1" name="P0_29CI" description="Clear GPIO port Interrupts for P0[29]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." /> + <BitField start="30" size="1" name="P0_30CI" description="Clear GPIO port Interrupts for P0[30]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." /> + <BitField start="31" size="1" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x010" size="4" name="ENR0" access="Read/Write" description="GPIO Interrupt Enable for Rising edge for Port 0." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="P0_0ER" description="Enable rising edge interrupt for P0[0]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." /> + <BitField start="1" size="1" name="P0_1ER" description="Enable rising edge interrupt for P0[1]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." /> + <BitField start="2" size="1" name="P0_2ER" description="Enable rising edge interrupt for P0[2]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." /> + <BitField start="3" size="1" name="P0_3ER" description="Enable rising edge interrupt for P0[3]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." /> + <BitField start="4" size="1" name="P0_4ER" description="Enable rising edge interrupt for P0[4]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." /> + <BitField start="5" size="1" name="P0_5ER" description="Enable rising edge interrupt for P0[5]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." /> + <BitField start="6" size="1" name="P0_6ER" description="Enable rising edge interrupt for P0[6]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." /> + <BitField start="7" size="1" name="P0_7ER" description="Enable rising edge interrupt for P0[7]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." /> + <BitField start="8" size="1" name="P0_8ER" description="Enable rising edge interrupt for P0[8]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." /> + <BitField start="9" size="1" name="P0_9ER" description="Enable rising edge interrupt for P0[9]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." /> + <BitField start="10" size="1" name="P0_10ER" description="Enable rising edge interrupt for P0[10]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." /> + <BitField start="11" size="1" name="P0_11ER" description="Enable rising edge interrupt for P0[11]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." /> + <BitField start="12" size="1" name="P0_12ER" description="Enable rising edge interrupt for P0[12]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." /> + <BitField start="13" size="1" name="P0_13ER" description="Enable rising edge interrupt for P0[13]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." /> + <BitField start="14" size="1" name="P0_14ER" description="Enable rising edge interrupt for P0[14]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." /> + <BitField start="15" size="1" name="P0_15ER" description="Enable rising edge interrupt for P0[15]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." /> + <BitField start="16" size="1" name="P0_16ER" description="Enable rising edge interrupt for P0[16]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." /> + <BitField start="17" size="1" name="P0_17ER" description="Enable rising edge interrupt for P0[17]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." /> + <BitField start="18" size="1" name="P0_18ER" description="Enable rising edge interrupt for P0[18]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." /> + <BitField start="19" size="1" name="P0_19ER" description="Enable rising edge interrupt for P0[19]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." /> + <BitField start="20" size="1" name="P0_20ER" description="Enable rising edge interrupt for P0[20]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." /> + <BitField start="21" size="1" name="P0_21ER" description="Enable rising edge interrupt for P0[21]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." /> + <BitField start="22" size="1" name="P0_22ER" description="Enable rising edge interrupt for P0[22]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." /> + <BitField start="23" size="1" name="P0_23ER" description="Enable rising edge interrupt for P0[23]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." /> + <BitField start="24" size="1" name="P0_24ER" description="Enable rising edge interrupt for P0[24]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." /> + <BitField start="25" size="1" name="P0_25ER" description="Enable rising edge interrupt for P0[25]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." /> + <BitField start="26" size="1" name="P0_26ER" description="Enable rising edge interrupt for P0[26]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." /> + <BitField start="27" size="1" name="P0_27ER" description="Enable rising edge interrupt for P0[27]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." /> + <BitField start="28" size="1" name="P0_28ER" description="Enable rising edge interrupt for P0[28]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." /> + <BitField start="29" size="1" name="P0_29ER" description="Enable rising edge interrupt for P0[29]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." /> + <BitField start="30" size="1" name="P0_30ER" description="Enable rising edge interrupt for P0[30]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." /> + <BitField start="31" size="1" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x014" size="4" name="ENF0" access="Read/Write" description="GPIO Interrupt Enable for Falling edge for Port 0." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="P0_0EF" description="Enable falling edge interrupt for P0[0]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." /> + <BitField start="1" size="1" name="P0_1EF" description="Enable falling edge interrupt for P0[1]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." /> + <BitField start="2" size="1" name="P0_2EF" description="Enable falling edge interrupt for P0[2]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." /> + <BitField start="3" size="1" name="P0_3EF" description="Enable falling edge interrupt for P0[3]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." /> + <BitField start="4" size="1" name="P0_4EF" description="Enable falling edge interrupt for P0[4]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." /> + <BitField start="5" size="1" name="P0_5EF" description="Enable falling edge interrupt for P0[5]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." /> + <BitField start="6" size="1" name="P0_6EF" description="Enable falling edge interrupt for P0[6]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." /> + <BitField start="7" size="1" name="P0_7EF" description="Enable falling edge interrupt for P0[7]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." /> + <BitField start="8" size="1" name="P0_8EF" description="Enable falling edge interrupt for P0[8]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." /> + <BitField start="9" size="1" name="P0_9EF" description="Enable falling edge interrupt for P0[9]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." /> + <BitField start="10" size="1" name="P0_10EF" description="Enable falling edge interrupt for P0[10]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." /> + <BitField start="11" size="1" name="P0_11EF" description="Enable falling edge interrupt for P0[11]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." /> + <BitField start="12" size="1" name="P0_12EF" description="Enable falling edge interrupt for P0[12]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." /> + <BitField start="13" size="1" name="P0_13EF" description="Enable falling edge interrupt for P0[13]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." /> + <BitField start="14" size="1" name="P0_14EF" description="Enable falling edge interrupt for P0[14]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." /> + <BitField start="15" size="1" name="P0_15EF" description="Enable falling edge interrupt for P0[15]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." /> + <BitField start="16" size="1" name="P0_16EF" description="Enable falling edge interrupt for P0[16]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." /> + <BitField start="17" size="1" name="P0_17EF" description="Enable falling edge interrupt for P0[17]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." /> + <BitField start="18" size="1" name="P0_18EF" description="Enable falling edge interrupt for P0[18]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." /> + <BitField start="19" size="1" name="P0_19EF" description="Enable falling edge interrupt for P0[19]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." /> + <BitField start="20" size="1" name="P0_20EF" description="Enable falling edge interrupt for P0[20]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." /> + <BitField start="21" size="1" name="P0_21EF" description="Enable falling edge interrupt for P0[21]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." /> + <BitField start="22" size="1" name="P0_22EF" description="Enable falling edge interrupt for P0[22]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." /> + <BitField start="23" size="1" name="P0_23EF" description="Enable falling edge interrupt for P0[23]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." /> + <BitField start="24" size="1" name="P0_24EF" description="Enable falling edge interrupt for P0[24]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." /> + <BitField start="25" size="1" name="P0_25EF" description="Enable falling edge interrupt for P0[25]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." /> + <BitField start="26" size="1" name="P0_26EF" description="Enable falling edge interrupt for P0[26]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." /> + <BitField start="27" size="1" name="P0_27EF" description="Enable falling edge interrupt for P0[27]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." /> + <BitField start="28" size="1" name="P0_28EF" description="Enable falling edge interrupt for P0[28]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." /> + <BitField start="29" size="1" name="P0_29EF" description="Enable falling edge interrupt for P0[29]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." /> + <BitField start="30" size="1" name="P0_30EF" description="Enable falling edge interrupt for P0[30]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." /> + <BitField start="31" size="1" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x024" size="4" name="STATR2" access="ReadOnly" description="GPIO Interrupt Status for Rising edge for Port 0." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="P2_0REI" description="Status of Rising Edge Interrupt for P2[0]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." /> + <BitField start="1" size="1" name="P2_1REI" description="Status of Rising Edge Interrupt for P2[1]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." /> + <BitField start="2" size="1" name="P2_2REI" description="Status of Rising Edge Interrupt for P2[2]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." /> + <BitField start="3" size="1" name="P2_3REI" description="Status of Rising Edge Interrupt for P2[3]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." /> + <BitField start="4" size="1" name="P2_4REI" description="Status of Rising Edge Interrupt for P2[4]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." /> + <BitField start="5" size="1" name="P2_5REI" description="Status of Rising Edge Interrupt for P2[5]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." /> + <BitField start="6" size="1" name="P2_6REI" description="Status of Rising Edge Interrupt for P2[6]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." /> + <BitField start="7" size="1" name="P2_7REI" description="Status of Rising Edge Interrupt for P2[7]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." /> + <BitField start="8" size="1" name="P2_8REI" description="Status of Rising Edge Interrupt for P2[8]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." /> + <BitField start="9" size="1" name="P2_9REI" description="Status of Rising Edge Interrupt for P2[9]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." /> + <BitField start="10" size="1" name="P2_10REI" description="Status of Rising Edge Interrupt for P2[10]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." /> + <BitField start="11" size="1" name="P2_11REI" description="Status of Rising Edge Interrupt for P2[11]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." /> + <BitField start="12" size="1" name="P2_12REI" description="Status of Rising Edge Interrupt for P2[12]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." /> + <BitField start="13" size="1" name="P2_13REI" description="Status of Rising Edge Interrupt for P2[13]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." /> + <BitField start="14" size="18" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x028" size="4" name="STATF2" access="ReadOnly" description="GPIO Interrupt Status for Falling edge for Port 0." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="P2_0FEI" description="Status of Falling Edge Interrupt for P2[0]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." /> + <BitField start="1" size="1" name="P2_1FEI" description="Status of Falling Edge Interrupt for P2[1]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." /> + <BitField start="2" size="1" name="P2_2FEI" description="Status of Falling Edge Interrupt for P2[2]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." /> + <BitField start="3" size="1" name="P2_3FEI" description="Status of Falling Edge Interrupt for P2[3]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." /> + <BitField start="4" size="1" name="P2_4FEI" description="Status of Falling Edge Interrupt for P2[4]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." /> + <BitField start="5" size="1" name="P2_5FEI" description="Status of Falling Edge Interrupt for P2[5]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." /> + <BitField start="6" size="1" name="P2_6FEI" description="Status of Falling Edge Interrupt for P2[6]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." /> + <BitField start="7" size="1" name="P2_7FEI" description="Status of Falling Edge Interrupt for P2[7]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." /> + <BitField start="8" size="1" name="P2_8FEI" description="Status of Falling Edge Interrupt for P2[8]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." /> + <BitField start="9" size="1" name="P2_9FEI" description="Status of Falling Edge Interrupt for P2[9]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." /> + <BitField start="10" size="1" name="P2_10FEI" description="Status of Falling Edge Interrupt for P2[10]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." /> + <BitField start="11" size="1" name="P2_11FEI" description="Status of Falling Edge Interrupt for P2[11]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." /> + <BitField start="12" size="1" name="P2_12FEI" description="Status of Falling Edge Interrupt for P2[12]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." /> + <BitField start="13" size="1" name="P2_13FEI" description="Status of Falling Edge Interrupt for P2[13]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." /> + <BitField start="14" size="18" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x02C" size="4" name="CLR2" access="WriteOnly" description="GPIO Interrupt Clear." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="P2_0CI" description="Clear GPIO port Interrupts for P2[0]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." /> + <BitField start="1" size="1" name="P2_1CI" description="Clear GPIO port Interrupts for P2[1]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." /> + <BitField start="2" size="1" name="P2_2CI" description="Clear GPIO port Interrupts for P2[2]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." /> + <BitField start="3" size="1" name="P2_3CI" description="Clear GPIO port Interrupts for P2[3]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." /> + <BitField start="4" size="1" name="P2_4CI" description="Clear GPIO port Interrupts for P2[4]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." /> + <BitField start="5" size="1" name="P2_5CI" description="Clear GPIO port Interrupts for P2[5]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." /> + <BitField start="6" size="1" name="P2_6CI" description="Clear GPIO port Interrupts for P2[6]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." /> + <BitField start="7" size="1" name="P2_7CI" description="Clear GPIO port Interrupts for P2[7]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." /> + <BitField start="8" size="1" name="P2_8CI" description="Clear GPIO port Interrupts for P2[8]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." /> + <BitField start="9" size="1" name="P2_9CI" description="Clear GPIO port Interrupts for P2[9]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." /> + <BitField start="10" size="1" name="P2_10CI" description="Clear GPIO port Interrupts for P2[10]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." /> + <BitField start="11" size="1" name="P2_11CI" description="Clear GPIO port Interrupts for P2[11]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." /> + <BitField start="12" size="1" name="P2_12CI" description="Clear GPIO port Interrupts for P2[12]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." /> + <BitField start="13" size="1" name="P2_13CI" description="Clear GPIO port Interrupts for P2[13]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." /> + <BitField start="14" size="18" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x030" size="4" name="ENR2" access="Read/Write" description="GPIO Interrupt Enable for Rising edge for Port 0." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="P2_0ER" description="Enable rising edge interrupt for P2[0]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." /> + <BitField start="1" size="1" name="P2_1ER" description="Enable rising edge interrupt for P2[1]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." /> + <BitField start="2" size="1" name="P2_2ER" description="Enable rising edge interrupt for P2[2]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." /> + <BitField start="3" size="1" name="P2_3ER" description="Enable rising edge interrupt for P2[3]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." /> + <BitField start="4" size="1" name="P2_4ER" description="Enable rising edge interrupt for P2[4]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." /> + <BitField start="5" size="1" name="P2_5ER" description="Enable rising edge interrupt for P2[5]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." /> + <BitField start="6" size="1" name="P2_6ER" description="Enable rising edge interrupt for P2[6]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." /> + <BitField start="7" size="1" name="P2_7ER" description="Enable rising edge interrupt for P2[7]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." /> + <BitField start="8" size="1" name="P2_8ER" description="Enable rising edge interrupt for P2[8]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." /> + <BitField start="9" size="1" name="P2_9ER" description="Enable rising edge interrupt for P2[9]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." /> + <BitField start="10" size="1" name="P2_10ER" description="Enable rising edge interrupt for P2[10]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." /> + <BitField start="11" size="1" name="P2_11ER" description="Enable rising edge interrupt for P2[11]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." /> + <BitField start="12" size="1" name="P2_12ER" description="Enable rising edge interrupt for P2[12]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." /> + <BitField start="13" size="1" name="P2_13ER" description="Enable rising edge interrupt for P2[13]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." /> + <BitField start="14" size="18" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x034" size="4" name="ENF2" access="Read/Write" description="GPIO Interrupt Enable for Falling edge for Port 0." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="P2_0EF" description="Enable falling edge interrupt for P2[0]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." /> + <BitField start="1" size="1" name="P2_1EF" description="Enable falling edge interrupt for P2[1]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." /> + <BitField start="2" size="1" name="P2_2EF" description="Enable falling edge interrupt for P2[2]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." /> + <BitField start="3" size="1" name="P2_3EF" description="Enable falling edge interrupt for P2[3]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." /> + <BitField start="4" size="1" name="P2_4EF" description="Enable falling edge interrupt for P2[4]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." /> + <BitField start="5" size="1" name="P2_5EF" description="Enable falling edge interrupt for P2[5]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." /> + <BitField start="6" size="1" name="P2_6EF" description="Enable falling edge interrupt for P2[6]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." /> + <BitField start="7" size="1" name="P2_7EF" description="Enable falling edge interrupt for P2[7]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." /> + <BitField start="8" size="1" name="P2_8EF" description="Enable falling edge interrupt for P2[8]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." /> + <BitField start="9" size="1" name="P2_9EF" description="Enable falling edge interrupt for P2[9]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." /> + <BitField start="10" size="1" name="P2_10EF" description="Enable falling edge interrupt for P2[10]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." /> + <BitField start="11" size="1" name="P2_11EF" description="Enable falling edge interrupt for P2[11]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." /> + <BitField start="12" size="1" name="P2_12EF" description="Enable falling edge interrupt for P2[12]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." /> + <BitField start="13" size="1" name="P2_13EF" description="Enable falling edge interrupt for P2[13]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." /> + <BitField start="14" size="18" name="RESERVED" description="Reserved." /> + </Register> + </RegisterGroup> + <RegisterGroup name="PINCONNECT" start="0x4002C000" description="Pin connect block"> + <Register start="+0x000" size="4" name="PINSEL0" access="Read/Write" description="Pin function select register 0." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="P0_0" description="Pin function select P0.0."> + <Enum name="GPIO_P0" start="0x0" description="GPIO P0.0" /> + <Enum name="RD1" start="0x1" description="RD1" /> + <Enum name="TXD3" start="0x2" description="TXD3" /> + <Enum name="SDA1" start="0x3" description="SDA1" /> + </BitField> + <BitField start="2" size="2" name="P0_1" description="Pin function select P0.1."> + <Enum name="GPIO_P0" start="0x0" description="GPIO P0.1" /> + <Enum name="TD1" start="0x1" description="TD1" /> + <Enum name="RXD3" start="0x2" description="RXD3" /> + <Enum name="SCL1" start="0x3" description="SCL1" /> + </BitField> + <BitField start="4" size="2" name="P0_2" description="Pin function select P0.2."> + <Enum name="GPIO_P0" start="0x0" description="GPIO P0.2" /> + <Enum name="TXD0" start="0x1" description="TXD0" /> + <Enum name="AD0" start="0x2" description="AD0.7" /> + <Enum name="RESERVED" start="0x3" description="Reserved" /> + </BitField> + <BitField start="6" size="2" name="P0_3" description="Pin function select P0.3."> + <Enum name="GPIO_P0" start="0x0" description="GPIO P0.3." /> + <Enum name="RXD0" start="0x1" description="RXD0" /> + <Enum name="AD0" start="0x2" description="AD0.6" /> + <Enum name="RESERVED" start="0x3" description="Reserved." /> + </BitField> + <BitField start="8" size="2" name="P0_4" description="Pin function select P0.4."> + <Enum name="GPIO_P0" start="0x0" description="GPIO P0.4." /> + <Enum name="I2SRX_CLK" start="0x1" description="I2SRX_CLK" /> + <Enum name="RD2" start="0x2" description="RD2" /> + <Enum name="CAP2" start="0x3" description="CAP2.0" /> + </BitField> + <BitField start="10" size="2" name="P0_5" description="Pin function select P0.5."> + <Enum name="GPIO_P0" start="0x0" description="GPIO P0.5." /> + <Enum name="I2SRX_WS" start="0x1" description="I2SRX_WS" /> + <Enum name="TD2" start="0x2" description="TD2" /> + <Enum name="CAP2" start="0x3" description="CAP2.1" /> + </BitField> + <BitField start="12" size="2" name="P0_6" description="Pin function select P0.6."> + <Enum name="GPIO_P0" start="0x0" description="GPIO P0.6." /> + <Enum name="I2SRX_SDA" start="0x1" description="I2SRX_SDA" /> + <Enum name="SSEL1" start="0x2" description="SSEL1" /> + <Enum name="MAT2" start="0x3" description="MAT2.0" /> + </BitField> + <BitField start="14" size="2" name="P0_7" description="Pin function select P0.7."> + <Enum name="GPIO_P0" start="0x0" description="GPIO P0.7." /> + <Enum name="I2STX_CLK" start="0x1" description="I2STX_CLK" /> + <Enum name="SCK1" start="0x2" description="SCK1" /> + <Enum name="MAT2" start="0x3" description="MAT2.1" /> + </BitField> + <BitField start="16" size="2" name="P0_8" description="Pin function select P0.8."> + <Enum name="GPIO_P0" start="0x0" description="GPIO P0.8." /> + <Enum name="I2STX_WS" start="0x1" description="I2STX_WS" /> + <Enum name="MISO1" start="0x2" description="MISO1" /> + <Enum name="MAT2" start="0x3" description="MAT2.2" /> + </BitField> + <BitField start="18" size="2" name="P0_9" description="Pin function select P0.9."> + <Enum name="GPIO_P0" start="0x0" description="GPIO P0.9" /> + <Enum name="I2STX_SDA" start="0x1" description="I2STX_SDA" /> + <Enum name="MOSI1" start="0x2" description="MOSI1" /> + <Enum name="MAT2" start="0x3" description="MAT2.3" /> + </BitField> + <BitField start="20" size="2" name="P0_10" description="Pin function select P0.10."> + <Enum name="GPIO_P0" start="0x0" description="GPIO P0.10" /> + <Enum name="TXD2" start="0x1" description="TXD2" /> + <Enum name="SDA2" start="0x2" description="SDA2" /> + <Enum name="MAT3" start="0x3" description="MAT3.0" /> + </BitField> + <BitField start="22" size="2" name="P0_11" description="Pin function select P0.11."> + <Enum name="GPIO_P0" start="0x0" description="GPIO P0.11" /> + <Enum name="RXD2" start="0x1" description="RXD2" /> + <Enum name="SCL2" start="0x2" description="SCL2" /> + <Enum name="MAT3" start="0x3" description="MAT3.1" /> + </BitField> + <BitField start="24" size="6" name="RESERVED" description="Reserved." /> + <BitField start="30" size="2" name="P0_15" description="Pin function select P0.15."> + <Enum name="GPIO_P0" start="0x0" description="GPIO P0.15" /> + <Enum name="TXD1" start="0x1" description="TXD1" /> + <Enum name="SCK0" start="0x2" description="SCK0" /> + <Enum name="SCK" start="0x3" description="SCK" /> + </BitField> + </Register> + <Register start="+0x004" size="4" name="PINSEL1" access="Read/Write" description="Pin function select register 1." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="P0_16" description="Pin function select P0.16."> + <Enum name="GPIO_P0" start="0x0" description="GPIO P0.16" /> + <Enum name="RXD1" start="0x1" description="RXD1" /> + <Enum name="SSEL0" start="0x2" description="SSEL0" /> + <Enum name="SSEL" start="0x3" description="SSEL" /> + </BitField> + <BitField start="2" size="2" name="P0_17" description="Pin function select P0.17."> + <Enum name="GPIO_P0" start="0x0" description="GPIO P0.17" /> + <Enum name="CTS1" start="0x1" description="CTS1" /> + <Enum name="MISO0" start="0x2" description="MISO0" /> + <Enum name="MISO" start="0x3" description="MISO" /> + </BitField> + <BitField start="4" size="2" name="P0_18" description="Pin function select P0.18."> + <Enum name="GPIO_P0" start="0x0" description="GPIO P0.18" /> + <Enum name="DCD1" start="0x1" description="DCD1" /> + <Enum name="MOSI0" start="0x2" description="MOSI0" /> + <Enum name="MOSI" start="0x3" description="MOSI" /> + </BitField> + <BitField start="6" size="2" name="P0_19" description="Pin function select P019."> + <Enum name="GPIO_P0" start="0x0" description="GPIO P0.19." /> + <Enum name="DSR1" start="0x1" description="DSR1" /> + <Enum name="RESERVED" start="0x2" description="Reserved" /> + <Enum name="SDA1" start="0x3" description="SDA1" /> + </BitField> + <BitField start="8" size="2" name="P0_20" description="Pin function select P0.20."> + <Enum name="GPIO_P0" start="0x0" description="GPIO P0.20." /> + <Enum name="DTR1" start="0x1" description="DTR1" /> + <Enum name="RESERVED" start="0x2" description="Reserved" /> + <Enum name="SCL1" start="0x3" description="SCL1" /> + </BitField> + <BitField start="10" size="2" name="P0_21" description="Pin function select P0.21."> + <Enum name="GPIO_PORT_0" start="0x0" description="GPIO Port 0.21." /> + <Enum name="RI1" start="0x1" description="RI1" /> + <Enum name="RESERVED" start="0x2" description="Reserved" /> + <Enum name="RD1" start="0x3" description="RD1" /> + </BitField> + <BitField start="12" size="2" name="P0_22" description="Pin function select P022"> + <Enum name="GPIO_P0" start="0x0" description="GPIO P0.22." /> + <Enum name="RTS1" start="0x1" description="RTS1" /> + <Enum name="RESERVED" start="0x2" description="Reserved" /> + <Enum name="TD1" start="0x3" description="TD1" /> + </BitField> + <BitField start="14" size="2" name="P0_23" description="Pin function select P023."> + <Enum name="GPIO_P0" start="0x0" description="GPIO P0.23." /> + <Enum name="AD0" start="0x1" description="AD0.0" /> + <Enum name="I2SRX_CLK" start="0x2" description="I2SRX_CLK" /> + <Enum name="CAP3" start="0x3" description="CAP3.0" /> + </BitField> + <BitField start="16" size="2" name="P0_24" description="Pin function select P0.24."> + <Enum name="GPIO_P0" start="0x0" description="GPIO P0.24." /> + <Enum name="AD0" start="0x1" description="AD0.1" /> + <Enum name="I2SRX_WS" start="0x2" description="I2SRX_WS" /> + <Enum name="CAP3" start="0x3" description="CAP3.1" /> + </BitField> + <BitField start="18" size="2" name="P0_25" description="Pin function select P0.25."> + <Enum name="GPIO_P0" start="0x0" description="GPIO P0.25" /> + <Enum name="AD0" start="0x1" description="AD0.2" /> + <Enum name="I2SRX_SDA" start="0x2" description="I2SRX_SDA" /> + <Enum name="TXD3" start="0x3" description="TXD3" /> + </BitField> + <BitField start="20" size="2" name="P0_26" description="Pin function select P0.26."> + <Enum name="GPIO_P0" start="0x0" description="GPIO P0.26" /> + <Enum name="AD0" start="0x1" description="AD0.3" /> + <Enum name="AOUT" start="0x2" description="AOUT" /> + <Enum name="RXD3" start="0x3" description="RXD3" /> + </BitField> + <BitField start="22" size="2" name="P0_27" description="Pin function select P0.27."> + <Enum name="GPIO_P0" start="0x0" description="GPIO P0.27" /> + <Enum name="SDA0" start="0x1" description="SDA0" /> + <Enum name="USB_SDA" start="0x2" description="USB_SDA" /> + <Enum name="RESERVED" start="0x3" description="Reserved" /> + </BitField> + <BitField start="24" size="2" name="P0_28" description="Pin function select P0.28."> + <Enum name="GPIO_P0" start="0x0" description="GPIO P0.28" /> + <Enum name="SCL0" start="0x1" description="SCL0" /> + <Enum name="USB_SCL" start="0x2" description="USB_SCL" /> + <Enum name="RESERVED" start="0x3" description="Reserved" /> + </BitField> + <BitField start="26" size="2" name="P0_29" description="Pin function select P0.29"> + <Enum name="GPIO_P0" start="0x0" description="GPIO P0.29" /> + <Enum name="USB_DP" start="0x1" description="USB_D+" /> + <Enum name="RESERVED" start="0x2" description="Reserved" /> + <Enum name="RESERVED" start="0x3" description="Reserved" /> + </BitField> + <BitField start="28" size="2" name="P0_30" description="Pin function select P0.30."> + <Enum name="GPIO_P0" start="0x0" description="GPIO P0.30" /> + <Enum name="USB_DM" start="0x1" description="USB_D-" /> + <Enum name="RESERVED" start="0x2" description="Reserved" /> + <Enum name="RESERVED" start="0x3" description="Reserved" /> + </BitField> + <BitField start="30" size="2" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x008" size="4" name="PINSEL2" access="Read/Write" description="Pin function select register 2." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="P1_0" description="Pin function select P1.0."> + <Enum name="GPIO_P1" start="0x0" description="GPIO P1.0" /> + <Enum name="ENET_TXD0" start="0x1" description="ENET_TXD0" /> + <Enum name="RESERVED" start="0x2" description="Reserved" /> + <Enum name="RESERVED" start="0x3" description="Reserved" /> + </BitField> + <BitField start="2" size="2" name="P1_1" description="Pin function select P1.1."> + <Enum name="GPIO_P1" start="0x0" description="GPIO P1.1" /> + <Enum name="ENET_TXD1" start="0x1" description="ENET_TXD1" /> + <Enum name="RESERVED" start="0x2" description="Reserved" /> + <Enum name="RESERVED" start="0x3" description="Reserved" /> + </BitField> + <BitField start="4" size="4" name="RESERVED" description="Reserved." /> + <BitField start="8" size="2" name="P1_4" description="Pin function select P1.4."> + <Enum name="GPIO_P1" start="0x0" description="GPIO P1.4." /> + <Enum name="ENET_TX_EN" start="0x1" description="ENET_TX_EN" /> + <Enum name="RESERVED" start="0x2" description="Reserved" /> + <Enum name="RESERVED" start="0x3" description="Reserved" /> + </BitField> + <BitField start="10" size="6" name="RESERVED" description="Reserved." /> + <BitField start="16" size="2" name="P1_8" description="Pin function select P1.8."> + <Enum name="GPIO_P1" start="0x0" description="GPIO P1.8." /> + <Enum name="ENET_CRS" start="0x1" description="ENET_CRS" /> + <Enum name="RESERVED" start="0x2" description="Reserved" /> + <Enum name="RESERVED" start="0x3" description="Reserved" /> + </BitField> + <BitField start="18" size="2" name="P1_9" description="Pin function select P1.9."> + <Enum name="GPIO_PORT_1" start="0x0" description="GPIO Port 1.9" /> + <Enum name="ENET_RXD0" start="0x1" description="ENET_RXD0" /> + <Enum name="RESERVED" start="0x2" description="Reserved" /> + <Enum name="RESERVED" start="0x3" description="Reserved" /> + </BitField> + <BitField start="20" size="2" name="P1_10" description="Pin function select P1.10."> + <Enum name="GPIO_P1" start="0x0" description="GPIO P1.10" /> + <Enum name="ENET_RXD1" start="0x1" description="ENET_RXD1" /> + <Enum name="RESERVED" start="0x2" description="Reserved" /> + <Enum name="RESERVED" start="0x3" description="Reserved" /> + </BitField> + <BitField start="24" size="6" name="RESERVED" description="Reserved." /> + <BitField start="22" size="2" name="P1_14" description="Pin function select P1.14."> + <Enum name="GPIO_P1" start="0x0" description="GPIO P1.14" /> + <Enum name="ENET_RX_ER" start="0x1" description="ENET_RX_ER" /> + <Enum name="RESERVED" start="0x2" description="Reserved" /> + <Enum name="RESERVED" start="0x3" description="Reserved" /> + </BitField> + <BitField start="24" size="6" name="RESERVED" description="Reserved." /> + <BitField start="30" size="2" name="P1_15" description="Pin function select P1.15."> + <Enum name="GPIO_P1" start="0x0" description="GPIO P1.15" /> + <Enum name="ENET_REF_CLK" start="0x1" description="ENET_REF_CLK" /> + <Enum name="RESERVED" start="0x2" description="Reserved" /> + <Enum name="RESERVED" start="0x3" description="Reserved" /> + </BitField> + </Register> + <Register start="+0x00C" size="4" name="PINSEL3" access="Read/Write" description="Pin function select register 3." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="P1_16" description="Pin function select P1.16."> + <Enum name="GPIO_P1" start="0x0" description="GPIO P1.16" /> + <Enum name="ENET_MDC" start="0x1" description="ENET_MDC" /> + <Enum name="RESERVED" start="0x2" description="Reserved" /> + <Enum name="RESERVED" start="0x3" description="Reserved" /> + </BitField> + <BitField start="2" size="2" name="P1_17" description="Pin function select P1.17."> + <Enum name="GPIO_P1" start="0x0" description="GPIO P1.17" /> + <Enum name="ENET_MDIO" start="0x1" description="ENET_MDIO" /> + <Enum name="RESERVED" start="0x2" description="Reserved" /> + <Enum name="RESERVED" start="0x3" description="Reserved" /> + </BitField> + <BitField start="4" size="2" name="P1_18" description="Pin function select P1.18."> + <Enum name="GPIO_P1" start="0x0" description="GPIO P1.18" /> + <Enum name="USB_UP_LED" start="0x1" description="USB_UP_LED" /> + <Enum name="PWM1" start="0x2" description="PWM1.1" /> + <Enum name="CAP1" start="0x3" description="CAP1.0" /> + </BitField> + <BitField start="6" size="2" name="P1_19" description="Pin function select P1.19."> + <Enum name="GPIO_P1" start="0x0" description="GPIO P1.19." /> + <Enum name="MCOA0" start="0x1" description="MCOA0" /> + <Enum name="USB_PPWR" start="0x2" description="USB_PPWR" /> + <Enum name="CAP1" start="0x3" description="CAP1.1" /> + </BitField> + <BitField start="8" size="2" name="P1_20" description="Pin function select P1.20."> + <Enum name="GPIO_P1" start="0x0" description="GPIO P1.20." /> + <Enum name="MCI0" start="0x1" description="MCI0" /> + <Enum name="PWM1" start="0x2" description="PWM1.2" /> + <Enum name="SCK0" start="0x3" description="SCK0" /> + </BitField> + <BitField start="10" size="2" name="P1_21" description="Pin function select P1.21."> + <Enum name="GPIO_P1" start="0x0" description="GPIO P1.21." /> + <Enum name="MCABORT" start="0x1" description="MCABORT" /> + <Enum name="PWM1" start="0x2" description="PWM1.3" /> + <Enum name="SSEL0" start="0x3" description="SSEL0" /> + </BitField> + <BitField start="12" size="2" name="P1_22" description="Pin function select P1.22"> + <Enum name="GPIO_P1" start="0x0" description="GPIO P1.22." /> + <Enum name="MCOB0" start="0x1" description="MCOB0" /> + <Enum name="USB_PWRD" start="0x2" description="USB_PWRD" /> + <Enum name="MAT1" start="0x3" description="MAT1.0" /> + </BitField> + <BitField start="14" size="2" name="P1_23" description="Pin function select P1.23."> + <Enum name="GPIO_P1" start="0x0" description="GPIO P1.23." /> + <Enum name="MCI1" start="0x1" description="MCI1" /> + <Enum name="PWM1" start="0x2" description="PWM1.4" /> + <Enum name="MISO0" start="0x3" description="MISO0" /> + </BitField> + <BitField start="16" size="2" name="P1_24" description="Pin function select P1.24."> + <Enum name="GPIO_P1" start="0x0" description="GPIO P1.24." /> + <Enum name="MCI2" start="0x1" description="MCI2" /> + <Enum name="PWM1" start="0x2" description="PWM1.5" /> + <Enum name="MOSI0" start="0x3" description="MOSI0" /> + </BitField> + <BitField start="18" size="2" name="P1_25" description="Pin function select P1.25."> + <Enum name="GPIO_P1" start="0x0" description="GPIO P1.25" /> + <Enum name="MCOA1" start="0x1" description="MCOA1" /> + <Enum name="RESERVED" start="0x2" description="Reserved" /> + <Enum name="MAT1" start="0x3" description="MAT1.1" /> + </BitField> + <BitField start="20" size="2" name="P1_26" description="Pin function select P1.26."> + <Enum name="GPIO_P1" start="0x0" description="GPIO P1.26" /> + <Enum name="MCOB1" start="0x1" description="MCOB1" /> + <Enum name="PWM1" start="0x2" description="PWM1.6" /> + <Enum name="CAP0" start="0x3" description="CAP0.0" /> + </BitField> + <BitField start="22" size="2" name="P1_27" description="Pin function select P1.27."> + <Enum name="GPIO_P1" start="0x0" description="GPIO P1.27" /> + <Enum name="CLKOUT" start="0x1" description="CLKOUT" /> + <Enum name="USB_OVRCR" start="0x2" description="USB_OVRCR" /> + <Enum name="CAP0" start="0x3" description="CAP0.1" /> + </BitField> + <BitField start="24" size="2" name="P1_28" description="Pin function select P1.28."> + <Enum name="GPIO_P1" start="0x0" description="GPIO P1.28" /> + <Enum name="MCOA2" start="0x1" description="MCOA2" /> + <Enum name="PCAP1" start="0x2" description="PCAP1.0" /> + <Enum name="MAT0" start="0x3" description="MAT0.0" /> + </BitField> + <BitField start="26" size="2" name="P1_29" description="Pin function select P1.29"> + <Enum name="GPIO_P1" start="0x0" description="GPIO P1.29" /> + <Enum name="MCOB2" start="0x1" description="MCOB2" /> + <Enum name="PCAP1" start="0x2" description="PCAP1.1" /> + <Enum name="MAT0" start="0x3" description="MAT0.1" /> + </BitField> + <BitField start="28" size="2" name="P1_30" description="Pin function select P1.30."> + <Enum name="GPIO_P1" start="0x0" description="GPIO P1.30" /> + <Enum name="RESERVED" start="0x1" description="Reserved" /> + <Enum name="VBUS" start="0x2" description="VBUS" /> + <Enum name="AD0" start="0x3" description="AD0.4" /> + </BitField> + <BitField start="30" size="2" name="P1_31" description="Pin function select P1.31."> + <Enum name="GPIO_PORT_1" start="0x0" description="GPIO Port 1.31" /> + <Enum name="RESERVED" start="0x1" description="Reserved" /> + <Enum name="SCK1" start="0x2" description="SCK1" /> + <Enum name="AD0" start="0x3" description="AD0.5" /> + </BitField> + </Register> + <Register start="+0x010" size="4" name="PINSEL4" access="Read/Write" description="Pin function select register 4" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="P2_0" description="Pin function select P2.0."> + <Enum name="GPIO_P2" start="0x0" description="GPIO P2.0" /> + <Enum name="PWM1" start="0x1" description="PWM1.1" /> + <Enum name="TXD1" start="0x2" description="TXD1" /> + <Enum name="RESERVED" start="0x3" description="Reserved" /> + </BitField> + <BitField start="2" size="2" name="P2_1" description="Pin function select P2.1."> + <Enum name="GPIO_P2" start="0x0" description="GPIO P2.1" /> + <Enum name="PWM1" start="0x1" description="PWM1.2" /> + <Enum name="RXD1" start="0x2" description="RXD1" /> + <Enum name="RESERVED" start="0x3" description="Reserved" /> + </BitField> + <BitField start="4" size="2" name="P2_2" description="Pin function select P2.2."> + <Enum name="GPIO_P2" start="0x0" description="GPIO P2.2" /> + <Enum name="PWM1" start="0x1" description="PWM1.3" /> + <Enum name="CTS1" start="0x2" description="CTS1" /> + <Enum name="RESERVED" start="0x3" description="Reserved" /> + </BitField> + <BitField start="6" size="2" name="P2_3" description="Pin function select P2.3."> + <Enum name="GPIO_P2" start="0x0" description="GPIO P2.3." /> + <Enum name="PWM1" start="0x1" description="PWM1.4" /> + <Enum name="DCD1" start="0x2" description="DCD1" /> + <Enum name="RESERVED" start="0x3" description="Reserved." /> + </BitField> + <BitField start="8" size="2" name="P2_4" description="Pin function select P2.4."> + <Enum name="GPIO_P2" start="0x0" description="GPIO P2.4." /> + <Enum name="PWM1" start="0x1" description="PWM1.5" /> + <Enum name="DSR1" start="0x2" description="DSR1" /> + <Enum name="RESERVED" start="0x3" description="Reserved." /> + </BitField> + <BitField start="10" size="2" name="P2_5" description="Pin function select P2.5."> + <Enum name="GPIO_P2" start="0x0" description="GPIO P2.5." /> + <Enum name="PWM1" start="0x1" description="PWM1.6" /> + <Enum name="DTR1" start="0x2" description="DTR1" /> + <Enum name="RESERVED" start="0x3" description="Reserved" /> + </BitField> + <BitField start="12" size="2" name="P2_6" description="Pin function select P2.6."> + <Enum name="GPIO_P2" start="0x0" description="GPIO P2.6." /> + <Enum name="PCAP1" start="0x1" description="PCAP1.0" /> + <Enum name="RI1" start="0x2" description="RI1" /> + <Enum name="RESERVED" start="0x3" description="Reserved" /> + </BitField> + <BitField start="14" size="2" name="P2_7" description="Pin function select P2.7."> + <Enum name="GPIO_P2" start="0x0" description="GPIO P2.7." /> + <Enum name="RD2" start="0x1" description="RD2" /> + <Enum name="RTS1" start="0x2" description="RTS1" /> + <Enum name="RESERVED" start="0x3" description="Reserved" /> + </BitField> + <BitField start="16" size="2" name="P2_8" description="Pin function select P2.8."> + <Enum name="GPIO_P2" start="0x0" description="GPIO P2.8." /> + <Enum name="TD2" start="0x1" description="TD2" /> + <Enum name="TXD2" start="0x2" description="TXD2" /> + <Enum name="ENET_MDC" start="0x3" description="ENET_MDC" /> + </BitField> + <BitField start="18" size="2" name="P2_9" description="Pin function select P2.9."> + <Enum name="GPIO_P2" start="0x0" description="GPIO P2.9" /> + <Enum name="USB_CONNECT" start="0x1" description="USB_CONNECT" /> + <Enum name="RXD2" start="0x2" description="RXD2" /> + <Enum name="ENET_MDIO" start="0x3" description="ENET_MDIO" /> + </BitField> + <BitField start="20" size="2" name="P2_10" description="Pin function select P2.10."> + <Enum name="GPIO_P2" start="0x0" description="GPIO P2.10" /> + <Enum name="EINT0" start="0x1" description="EINT0" /> + <Enum name="NMI" start="0x2" description="NMI" /> + <Enum name="RESERVED" start="0x3" description="Reserved" /> + </BitField> + <BitField start="22" size="2" name="P2_11" description="Pin function select P2.11."> + <Enum name="GPIO_P2" start="0x0" description="GPIO P2.11" /> + <Enum name="EINT1" start="0x1" description="EINT1" /> + <Enum name="RESERVED" start="0x2" description="Reserved" /> + <Enum name="I2STX_CLK" start="0x3" description="I2STX_CLK" /> + </BitField> + <BitField start="24" size="2" name="P2_12" description="Pin function select P2.12."> + <Enum name="GPIO_P2" start="0x0" description="GPIO P2.12" /> + <Enum name="EINT2" start="0x1" description="EINT2" /> + <Enum name="RESERVED" start="0x2" description="Reserved" /> + <Enum name="I2STX_WS" start="0x3" description="I2STX_WS" /> + </BitField> + <BitField start="26" size="2" name="P2_13" description="Pin function select P2.13."> + <Enum name="GPIO_P2" start="0x0" description="GPIO P2.13" /> + <Enum name="EINT3" start="0x1" description="EINT3" /> + <Enum name="RESERVED" start="0x2" description="Reserved" /> + <Enum name="I2STX_SDA" start="0x3" description="I2STX_SDA" /> + </BitField> + <BitField start="28" size="4" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x01C" size="4" name="PINSEL7" access="Read/Write" description="Pin function select register 7" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="18" name="RESERVED" description="Reserved." /> + <BitField start="18" size="2" name="P3_25" description="Pin function select P3.25."> + <Enum name="GPIO_P3" start="0x0" description="GPIO P3.25" /> + <Enum name="RESERVED" start="0x1" description="Reserved" /> + <Enum name="MAT0" start="0x2" description="MAT0.0" /> + <Enum name="PWM1" start="0x3" description="PWM1.2" /> + </BitField> + <BitField start="20" size="2" name="P3_26" description="Pin function select P3.26."> + <Enum name="GPIO_P3" start="0x0" description="GPIO P3.26" /> + <Enum name="STCLK" start="0x1" description="STCLK" /> + <Enum name="MAT0" start="0x2" description="MAT0.1" /> + <Enum name="PWM1" start="0x3" description="PWM1.3" /> + </BitField> + <BitField start="22" size="10" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x024" size="4" name="PINSEL9" access="Read/Write" description="Pin function select register 9" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="24" name="RESERVED" description="Reserved." /> + <BitField start="24" size="2" name="P4_28" description="Pin function select P4.28."> + <Enum name="GPIO_P4" start="0x0" description="GPIO P4.28" /> + <Enum name="RX_MCLK" start="0x1" description="RX_MCLK" /> + <Enum name="MAT2" start="0x2" description="MAT2.0" /> + <Enum name="TXD3" start="0x3" description="TXD3" /> + </BitField> + <BitField start="26" size="2" name="P4_29" description="Pin function select P4.29."> + <Enum name="GPIO_P4" start="0x0" description="GPIO P4.29" /> + <Enum name="TX_MCLK" start="0x1" description="TX_MCLK" /> + <Enum name="MAT2" start="0x2" description="MAT2.1" /> + <Enum name="RXD3" start="0x3" description="RXD3" /> + </BitField> + <BitField start="28" size="4" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x028" size="4" name="PINSEL10" access="Read/Write" description="Pin function select register 10" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="RESERVED" description="Reserved. Software should not write 1 to these bits." /> + <BitField start="3" size="1" name="TPIUCTRL" description="TPIU interface pins control."> + <Enum name="DISABLED" start="0" description="Disabled. TPIU interface is disabled." /> + <Enum name="ENABLED" start="1" description="Enabled. TPIU interface is enabled. TPIU signals are available on the pins hosting them regardless of the PINSEL4 content." /> + </BitField> + <BitField start="4" size="28" name="RESERVED" description="Reserved. Software should not write 1 to these bits." /> + </Register> + <Register start="+0x040" size="4" name="PINMODE0" access="Read/Write" description="Pin mode select register 0" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="P0_00MODE" description="Port 0 pin 0 on-chip pull-up/down resistor control."> + <Enum name="PULL_UP" start="0x0" description="Pull-up. P0.0 pin has a pull-up resistor enabled." /> + <Enum name="REPEATER" start="0x1" description="Repeater. P0.0 pin has repeater mode enabled." /> + <Enum name="DISABLED" start="0x2" description="Disabled. P0.0 pin has neither pull-up nor pull-down." /> + <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P0.0 has a pull-down resistor enabled." /> + </BitField> + <BitField start="2" size="2" name="P0_01MODE" description="Port 0 pin 1 control."> + <Enum name="PULL_UP" start="0x0" description="Pull-up. P0.1 pin has a pull-up resistor enabled." /> + <Enum name="REPEATER" start="0x1" description="Repeater. P0.1 pin has repeater mode enabled." /> + <Enum name="DISABLED" start="0x2" description="Disabled. P0.1 pin has neither pull-up nor pull-down." /> + <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P0.1 has a pull-down resistor enabled." /> + </BitField> + <BitField start="4" size="2" name="P0_02MODE" description="Port 0 pin 2 control."> + <Enum name="PULL_UP" start="0x0" description="Pull-up. P0.2 pin has a pull-up resistor enabled." /> + <Enum name="REPEATER" start="0x1" description="Repeater. P0.2 pin has repeater mode enabled." /> + <Enum name="DISABLED" start="0x2" description="Disabled. P0.2 pin has neither pull-up nor pull-down." /> + <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P0.2 has a pull-down resistor enabled." /> + </BitField> + <BitField start="6" size="2" name="P0_03MODE" description="Port 0 pin 3 control."> + <Enum name="PULL_UP" start="0x0" description="Pull-up. P0.3 pin has a pull-up resistor enabled." /> + <Enum name="REPEATER" start="0x1" description="Repeater. P0.3 pin has repeater mode enabled." /> + <Enum name="DISABLED" start="0x2" description="Disabled. P0.3 pin has neither pull-up nor pull-down." /> + <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P0.3 has a pull-down resistor enabled." /> + </BitField> + <BitField start="8" size="2" name="P0_04MODE" description="Port 0 pin 4 control."> + <Enum name="PULL_UP" start="0x0" description="Pull-up. P0.4 pin has a pull-up resistor enabled." /> + <Enum name="REPEATER" start="0x1" description="Repeater. P0.4 pin has repeater mode enabled." /> + <Enum name="DISABLED" start="0x2" description="Disabled. P0.4 pin has neither pull-up nor pull-down." /> + <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P0.4 has a pull-down resistor enabled." /> + </BitField> + <BitField start="10" size="2" name="P0_05MODE" description="Port 0 pin 5 control."> + <Enum name="PULL_UP" start="0x0" description="Pull-up. P0.5 pin has a pull-up resistor enabled." /> + <Enum name="REPEATER" start="0x1" description="Repeater. P0.5 pin has repeater mode enabled." /> + <Enum name="DISABLED" start="0x2" description="Disabled. P0.5 pin has neither pull-up nor pull-down." /> + <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P0.5 has a pull-down resistor enabled." /> + </BitField> + <BitField start="12" size="2" name="P0_06MODE" description="Port 0 pin 6 control."> + <Enum name="PULL_UP" start="0x0" description="Pull-up. P0.6 pin has a pull-up resistor enabled." /> + <Enum name="DISABLED" start="0x1" description="Disabled. Repeater. P0.6 pin has repeater mode enabled." /> + <Enum name="DISABLED" start="0x2" description="Disabled. P0.6 pin has neither pull-up nor pull-down." /> + <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P0.6 has a pull-down resistor enabled." /> + </BitField> + <BitField start="14" size="2" name="P0_07MODE" description="Port 0 pin 7 control."> + <Enum name="PULL_UP" start="0x0" description="Pull-up. P0.7 pin has a pull-up resistor enabled." /> + <Enum name="REPEATER" start="0x1" description="Repeater. P0.7 pin has repeater mode enabled." /> + <Enum name="DISABLED" start="0x2" description="Disabled. P0.7 pin has neither pull-up nor pull-down." /> + <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P0.7 has a pull-down resistor enabled." /> + </BitField> + <BitField start="16" size="2" name="P0_08MODE" description="Port 0 pin 8 control."> + <Enum name="PULL_UP" start="0x0" description="Pull-up. P0.8 pin has a pull-up resistor enabled." /> + <Enum name="REPEATER" start="0x1" description="Repeater. P0.8 pin has repeater mode enabled." /> + <Enum name="DISABLED" start="0x2" description="Disabled. P0.8 pin has neither pull-up nor pull-down." /> + <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P0.8 has a pull-down resistor enabled." /> + </BitField> + <BitField start="18" size="2" name="P0_09MODE" description="Port 0 pin 9 control."> + <Enum name="PULL_UP" start="0x0" description="Pull-up. P0.9 pin has a pull-up resistor enabled." /> + <Enum name="REPEATER" start="0x1" description="Repeater. P0.9 pin has repeater mode enabled." /> + <Enum name="DISABLED" start="0x2" description="Disabled. P0.9 pin has neither pull-up nor pull-down." /> + <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P0.9 has a pull-down resistor enabled." /> + </BitField> + <BitField start="20" size="2" name="P0_10MODE" description="Port 0 pin 10 control."> + <Enum name="PULL_UP" start="0x0" description="Pull-up. P0.10 pin has a pull-up resistor enabled." /> + <Enum name="REPEATER" start="0x1" description="Repeater. P0.10 pin has repeater mode enabled." /> + <Enum name="DISABLED" start="0x2" description="Disabled. P0.10 pin has neither pull-up nor pull-down." /> + <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P0.10 has a pull-down resistor enabled." /> + </BitField> + <BitField start="22" size="2" name="P0_11MODE" description="Port 0 pin 11 control."> + <Enum name="PULL_UP" start="0x0" description="Pull-up. P0.11 pin has a pull-up resistor enabled." /> + <Enum name="REPEATER" start="0x1" description="Repeater. P0.11 pin has repeater mode enabled." /> + <Enum name="DISABLED" start="0x2" description="Disabled. P0.11 pin has neither pull-up nor pull-down." /> + <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P0.11 has a pull-down resistor enabled." /> + </BitField> + <BitField start="24" size="6" name="RESERVED" description="Reserved." /> + <BitField start="30" size="2" name="P0_15MODE" description="Port 0 pin 15 control."> + <Enum name="PULL_UP" start="0x0" description="Pull-up. P0.15 pin has a pull-up resistor enabled." /> + <Enum name="REPEATER" start="0x1" description="Repeater. P0.15 pin has repeater mode enabled." /> + <Enum name="DISABLED" start="0x2" description="Disabled. P0.15 pin has neither pull-up nor pull-down." /> + <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P0.15 has a pull-down resistor enabled." /> + </BitField> + </Register> + <Register start="+0x044" size="4" name="PINMODE1" access="Read/Write" description="Pin mode select register 1" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="P0_16MODE" description="Port 1 pin 16 control."> + <Enum name="PULL_UP" start="0x0" description="Pull-up. P0.16 pin has a pull-up resistor enabled." /> + <Enum name="REPEATER" start="0x1" description="Repeater. P0.16 pin has repeater mode enabled." /> + <Enum name="DISABLED" start="0x2" description="Disabled. P0.16 pin has neither pull-up nor pull-down." /> + <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P0.16 has a pull-down resistor enabled." /> + </BitField> + <BitField start="2" size="2" name="P0_17MODE" description="Port 1 pin 17 control."> + <Enum name="PULL_UP" start="0x0" description="Pull-up. P0.17 pin has a pull-up resistor enabled." /> + <Enum name="REPEATER" start="0x1" description="Repeater. P0.17 pin has repeater mode enabled." /> + <Enum name="DISABLED" start="0x2" description="Disabled. P0.17 pin has neither pull-up nor pull-down." /> + <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P0.17 has a pull-down resistor enabled." /> + </BitField> + <BitField start="4" size="2" name="P0_18MODE" description="Port 1 pin 18 control."> + <Enum name="PULL_UP" start="0x0" description="Pull-up. P0.18 pin has a pull-up resistor enabled." /> + <Enum name="REPEATER" start="0x1" description="Repeater. P0.18 pin has repeater mode enabled." /> + <Enum name="DISABLED" start="0x2" description="Disabled. P0.18 pin has neither pull-up nor pull-down." /> + <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P0.18 has a pull-down resistor enabled." /> + </BitField> + <BitField start="6" size="2" name="P0_19MODE" description="Port 1 pin 19 control."> + <Enum name="PULL_UP" start="0x0" description="Pull-up. P0.19 pin has a pull-up resistor enabled." /> + <Enum name="REPEATER" start="0x1" description="Repeater. P0.19 pin has repeater mode enabled." /> + <Enum name="DISABLED" start="0x2" description="Disabled. P0.19 pin has neither pull-up nor pull-down." /> + <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P0.19 has a pull-down resistor enabled." /> + </BitField> + <BitField start="8" size="2" name="P0_20MODE" description="Port 1 pin 20 control."> + <Enum name="PULL_UP" start="0x0" description="Pull-up. P0.20 pin has a pull-up resistor enabled." /> + <Enum name="REPEATER" start="0x1" description="Repeater. P0.20 pin has repeater mode enabled." /> + <Enum name="DISABLED" start="0x2" description="Disabled. P0.20 pin has neither pull-up nor pull-down." /> + <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P0.20 has a pull-down resistor enabled." /> + </BitField> + <BitField start="10" size="2" name="P0_21MODE" description="Port 1 pin 21 control."> + <Enum name="PULL_UP" start="0x0" description="Pull-up. P0.21 pin has a pull-up resistor enabled." /> + <Enum name="REPEATER" start="0x1" description="Repeater. P0.21 pin has repeater mode enabled." /> + <Enum name="DISABLED" start="0x2" description="Disabled. P0.21 pin has neither pull-up nor pull-down." /> + <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P0.21 has a pull-down resistor enabled." /> + </BitField> + <BitField start="12" size="2" name="P0_22MODE" description="Port 1 pin 22 control."> + <Enum name="PULL_UP" start="0x0" description="Pull-up. P0.22 pin has a pull-up resistor enabled." /> + <Enum name="REPEATER" start="0x1" description="Repeater. P0.22 pin has repeater mode enabled." /> + <Enum name="DISABLED" start="0x2" description="Disabled. P0.22 pin has neither pull-up nor pull-down." /> + <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P0.22 has a pull-down resistor enabled." /> + </BitField> + <BitField start="14" size="2" name="P0_23MODE" description="Port 1 pin 23 control."> + <Enum name="PULL_UP" start="0x0" description="Pull-up. P0.23 pin has a pull-up resistor enabled." /> + <Enum name="REPEATER" start="0x1" description="Repeater. P0.23 pin has repeater mode enabled." /> + <Enum name="DISABLED" start="0x2" description="Disabled. P0.23 pin has neither pull-up nor pull-down." /> + <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P0.23 has a pull-down resistor enabled." /> + </BitField> + <BitField start="16" size="2" name="P0_24MODE" description="Port 1 pin 24 control."> + <Enum name="PULL_UP" start="0x0" description="Pull-up. P0.24 pin has a pull-up resistor enabled." /> + <Enum name="REPEATER" start="0x1" description="Repeater. P0.24 pin has repeater mode enabled." /> + <Enum name="DISABLED" start="0x2" description="Disabled. P0.24 pin has neither pull-up nor pull-down." /> + <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P0.24 has a pull-down resistor enabled." /> + </BitField> + <BitField start="18" size="2" name="P0_25MODE" description="Port 1 pin 25 control."> + <Enum name="PULL_UP" start="0x0" description="Pull-up. P0.25 pin has a pull-up resistor enabled." /> + <Enum name="REPEATER" start="0x1" description="Repeater. P0.25 pin has repeater mode enabled." /> + <Enum name="DISABLED" start="0x2" description="Disabled. P0.25 pin has neither pull-up nor pull-down." /> + <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P0.25 has a pull-down resistor enabled." /> + </BitField> + <BitField start="20" size="2" name="P0_26MODE" description="Port 1 pin 26 control."> + <Enum name="PULL_UP" start="0x0" description="Pull-up. P0.26 pin has a pull-up resistor enabled." /> + <Enum name="REPEATER" start="0x1" description="Repeater. P0.26 pin has repeater mode enabled." /> + <Enum name="DISABLED" start="0x2" description="Disabled. P0.26 pin has neither pull-up nor pull-down." /> + <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P0.26 has a pull-down resistor enabled." /> + </BitField> + <BitField start="22" size="8" name="RESERVED" description="Reserved." /> + <BitField start="30" size="2" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x048" size="4" name="PINMODE2" access="Read/Write" description="Pin mode select register 2" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="P1_00MODE" description="Port 1 pin 0 control."> + <Enum name="PULL_UP" start="0x0" description="Pull-up. P1.0 pin has a pull-up resistor enabled." /> + <Enum name="REPEATER" start="0x1" description="Repeater. P1.0 pin has repeater mode enabled." /> + <Enum name="DISABLED" start="0x2" description="Disabled. P1.0 pin has neither pull-up nor pull-down." /> + <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P1.0 has a pull-down resistor enabled." /> + </BitField> + <BitField start="2" size="2" name="P1_01MODE" description="Port 1 pin 1 control."> + <Enum name="PULL_UP" start="0x0" description="Pull-up. P1.1 pin has a pull-up resistor enabled." /> + <Enum name="REPEATER" start="0x1" description="Repeater. P1.1 pin has repeater mode enabled." /> + <Enum name="DISABLED" start="0x2" description="Disabled. P1.1 pin has neither pull-up nor pull-down." /> + <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P1.1 has a pull-down resistor enabled." /> + </BitField> + <BitField start="4" size="4" name="RESERVED" description="Reserved." /> + <BitField start="8" size="2" name="P1_04MODE" description="Port 1 pin 4 control."> + <Enum name="PULL_UP" start="0x0" description="Pull-up. P1.4 pin has a pull-up resistor enabled." /> + <Enum name="REPEATER" start="0x1" description="Repeater. P1.4 pin has repeater mode enabled." /> + <Enum name="DISABLED" start="0x2" description="Disabled. P1.4 pin has neither pull-up nor pull-down." /> + <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P1.4 has a pull-down resistor enabled." /> + </BitField> + <BitField start="10" size="6" name="RESERVED" description="Reserved." /> + <BitField start="16" size="2" name="P1_08MODE" description="Port 1 pin 8 control."> + <Enum name="PULL_UP" start="0x0" description="Pull-up. P1.8 pin has a pull-up resistor enabled." /> + <Enum name="REPEATER" start="0x1" description="Repeater. P1.8 pin has repeater mode enabled." /> + <Enum name="DISABLED" start="0x2" description="Disabled. P1.8 pin has neither pull-up nor pull-down." /> + <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P1.8 has a pull-down resistor enabled." /> + </BitField> + <BitField start="18" size="2" name="P1_09MODE" description="Port 1 pin 9 control."> + <Enum name="PULL_UP" start="0x0" description="Pull-up. P1.9 pin has a pull-up resistor enabled." /> + <Enum name="REPEATER" start="0x1" description="Repeater. P1.9 pin has repeater mode enabled." /> + <Enum name="DISABLED" start="0x2" description="Disabled. P1.9 pin has neither pull-up nor pull-down." /> + <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P1.9 has a pull-down resistor enabled." /> + </BitField> + <BitField start="20" size="2" name="P1_10MODE" description="Port 1 pin 10 control."> + <Enum name="PULL_UP" start="0x0" description="Pull-up. P1.10 pin has a pull-up resistor enabled." /> + <Enum name="REPEATER" start="0x1" description="Repeater. P1.10 pin has repeater mode enabled." /> + <Enum name="DISABLED" start="0x2" description="Disabled. P1.10 pin has neither pull-up nor pull-down." /> + <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P1.10 has a pull-down resistor enabled." /> + </BitField> + <BitField start="22" size="6" name="RESERVED" description="Reserved." /> + <BitField start="28" size="2" name="P1_14MODE" description="Port 1 pin 14 control."> + <Enum name="PULL_UP" start="0x0" description="Pull-up. P1.14 pin has a pull-up resistor enabled." /> + <Enum name="REPEATER" start="0x1" description="Repeater. P1.14 pin has repeater mode enabled." /> + <Enum name="DISABLED" start="0x2" description="Disabled. P1.14 pin has neither pull-up nor pull-down." /> + <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P1.14 has a pull-down resistor enabled." /> + </BitField> + <BitField start="30" size="2" name="P1_15MODE" description="Port 1 pin 15 control."> + <Enum name="PULL_UP" start="0x0" description="Pull-up. P1.15 pin has a pull-up resistor enabled." /> + <Enum name="REPEATER" start="0x1" description="Repeater. P1.15 pin has repeater mode enabled." /> + <Enum name="DISABLED" start="0x2" description="Disabled. P1.15 pin has neither pull-up nor pull-down." /> + <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P1.15 has a pull-down resistor enabled." /> + </BitField> + </Register> + <Register start="+0x04C" size="4" name="PINMODE3" access="Read/Write" description="Pin mode select register 3." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="P1_16MODE" description="Port 1 pin 16 control."> + <Enum name="PULL_UP" start="0x0" description="Pull-up. P1.16 pin has a pull-up resistor enabled." /> + <Enum name="REPEATER" start="0x1" description="Repeater. P1.16 pin has repeater mode enabled." /> + <Enum name="DISABLED" start="0x2" description="Disabled. P1.16 pin has neither pull-up nor pull-down." /> + <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P1.16 has a pull-down resistor enabled." /> + </BitField> + <BitField start="2" size="2" name="P1_17MODE" description="Port 1 pin 17 control."> + <Enum name="PULL_UP" start="0x0" description="Pull-up. P1.17 pin has a pull-up resistor enabled." /> + <Enum name="REPEATER" start="0x1" description="Repeater. P1.17 pin has repeater mode enabled." /> + <Enum name="DISABLED" start="0x2" description="Disabled. P1.17 pin has neither pull-up nor pull-down." /> + <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P1.17 has a pull-down resistor enabled." /> + </BitField> + <BitField start="4" size="2" name="P1_18MODE" description="Port 1 pin 18 control."> + <Enum name="PULL_UP" start="0x0" description="Pull-up. P1.18 pin has a pull-up resistor enabled." /> + <Enum name="REPEATER" start="0x1" description="Repeater. P1.18 pin has repeater mode enabled." /> + <Enum name="DISABLED" start="0x2" description="Disabled. P1.18 pin has neither pull-up nor pull-down." /> + <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P1.18 has a pull-down resistor enabled." /> + </BitField> + <BitField start="6" size="2" name="P1_19MODE" description="Port 1 pin 19 control."> + <Enum name="PULL_UP" start="0x0" description="Pull-up. P1.19 pin has a pull-up resistor enabled." /> + <Enum name="REPEATER" start="0x1" description="Repeater. P1.19 pin has repeater mode enabled." /> + <Enum name="DISABLED" start="0x2" description="Disabled. P1.19 pin has neither pull-up nor pull-down." /> + <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P1.19 has a pull-down resistor enabled." /> + </BitField> + <BitField start="8" size="2" name="P1_20MODE" description="Port 1 pin 20 control."> + <Enum name="PULL_UP" start="0x0" description="Pull-up. P1.20 pin has a pull-up resistor enabled." /> + <Enum name="REPEATER" start="0x1" description="Repeater. P1.20 pin has repeater mode enabled." /> + <Enum name="DISABLED" start="0x2" description="Disabled. P1.20 pin has neither pull-up nor pull-down." /> + <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P1.20 has a pull-down resistor enabled." /> + </BitField> + <BitField start="10" size="2" name="P1_21MODE" description="Port 1 pin 21 control."> + <Enum name="PULL_UP" start="0x0" description="Pull-up. P1.21 pin has a pull-up resistor enabled." /> + <Enum name="REPEATER" start="0x1" description="Repeater. P1.21 pin has repeater mode enabled." /> + <Enum name="DISABLED" start="0x2" description="Disabled. P1.21 pin has neither pull-up nor pull-down." /> + <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P1.21 has a pull-down resistor enabled." /> + </BitField> + <BitField start="12" size="2" name="P1_22MODE" description="Port 1 pin 22 control."> + <Enum name="PULL_UP" start="0x0" description="Pull-up. P1.22 pin has a pull-up resistor enabled." /> + <Enum name="REPEATER" start="0x1" description="Repeater. P1.22 pin has repeater mode enabled." /> + <Enum name="DISABLED" start="0x2" description="Disabled. P1.22 pin has neither pull-up nor pull-down." /> + <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P1.22 has a pull-down resistor enabled." /> + </BitField> + <BitField start="14" size="2" name="P1_23MODE" description="Port 1 pin 23 control."> + <Enum name="PULL_UP" start="0x0" description="Pull-up. P1.23 pin has a pull-up resistor enabled." /> + <Enum name="REPEATER" start="0x1" description="Repeater. P1.23 pin has repeater mode enabled." /> + <Enum name="DISABLED" start="0x2" description="Disabled. P1.23 pin has neither pull-up nor pull-down." /> + <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P1.23 has a pull-down resistor enabled." /> + </BitField> + <BitField start="16" size="2" name="P1_24MODE" description="Port 1 pin 24 control."> + <Enum name="PULL_UP" start="0x0" description="Pull-up. P1.24 pin has a pull-up resistor enabled." /> + <Enum name="REPEATER" start="0x1" description="Repeater. P1.24 pin has repeater mode enabled." /> + <Enum name="DISABLED" start="0x2" description="Disabled. P1.24 pin has neither pull-up nor pull-down." /> + <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P1.24 has a pull-down resistor enabled." /> + </BitField> + <BitField start="18" size="2" name="P1_25MODE" description="Port 1 pin 25 control."> + <Enum name="PULL_UP" start="0x0" description="Pull-up. P1.25 pin has a pull-up resistor enabled." /> + <Enum name="REPEATER" start="0x1" description="Repeater. P1.25 pin has repeater mode enabled." /> + <Enum name="DISABLED" start="0x2" description="Disabled. P1.25 pin has neither pull-up nor pull-down." /> + <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P1.25 has a pull-down resistor enabled." /> + </BitField> + <BitField start="20" size="2" name="P1_26MODE" description="Port 1 pin 26 control."> + <Enum name="PULL_UP" start="0x0" description="Pull-up. P1.26 pin has a pull-up resistor enabled." /> + <Enum name="REPEATER" start="0x1" description="Repeater. P1.26 pin has repeater mode enabled." /> + <Enum name="DISABLED" start="0x2" description="Disabled. P1.26 pin has neither pull-up nor pull-down." /> + <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P1.26 has a pull-down resistor enabled." /> + </BitField> + <BitField start="22" size="2" name="P1_27MODE" description="Port 1 pin 27 control."> + <Enum name="PULL_UP" start="0x0" description="Pull-up. P1.27 pin has a pull-up resistor enabled." /> + <Enum name="REPEATER" start="0x1" description="Repeater. P1.27 pin has repeater mode enabled." /> + <Enum name="DISABLED" start="0x2" description="Disabled. P1.27 pin has neither pull-up nor pull-down." /> + <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P1.27 has a pull-down resistor enabled." /> + </BitField> + <BitField start="24" size="2" name="P1_28MODE" description="Port 1 pin 28 control."> + <Enum name="PULL_UP" start="0x0" description="Pull-up. P1.28 pin has a pull-up resistor enabled." /> + <Enum name="REPEATER" start="0x1" description="Repeater. P1.28 pin has repeater mode enabled." /> + <Enum name="DISABLED" start="0x2" description="Disabled. P1.28 pin has neither pull-up nor pull-down." /> + <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P1.28 has a pull-down resistor enabled." /> + </BitField> + <BitField start="26" size="2" name="P1_29MODE" description="Port 1 pin 29 control."> + <Enum name="PULL_UP" start="0x0" description="Pull-up. P1.29 pin has a pull-up resistor enabled." /> + <Enum name="REPEATER" start="0x1" description="Repeater. P1.29 pin has repeater mode enabled." /> + <Enum name="DISABLED" start="0x2" description="Disabled. P1.29 pin has neither pull-up nor pull-down." /> + <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P1.29 has a pull-down resistor enabled." /> + </BitField> + <BitField start="28" size="2" name="P1_30MODE" description="Port 1 pin 30 control."> + <Enum name="PULL_UP" start="0x0" description="Pull-up. P1.30 pin has a pull-up resistor enabled." /> + <Enum name="REPEATER" start="0x1" description="Repeater. P1.30 pin has repeater mode enabled." /> + <Enum name="DISABLED" start="0x2" description="Disabled. P1.30 pin has neither pull-up nor pull-down." /> + <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P1.30 has a pull-down resistor enabled." /> + </BitField> + <BitField start="30" size="2" name="P1_31MODE" description="Port 1 pin 31 control."> + <Enum name="PULL_UP" start="0x0" description="Pull-up. P1.31 pin has a pull-up resistor enabled." /> + <Enum name="REPEATER" start="0x1" description="Repeater. P1.31 pin has repeater mode enabled." /> + <Enum name="DISABLED" start="0x2" description="Disabled. P1.31 pin has neither pull-up nor pull-down." /> + <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P1.31 has a pull-down resistor enabled." /> + </BitField> + </Register> + <Register start="+0x050" size="4" name="PINMODE4" access="Read/Write" description="Pin mode select register 4" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="P2_00MODE" description="Port 2 pin 0 control."> + <Enum name="PULL_UP" start="0x0" description="Pull-up. P2.0 pin has a pull-up resistor enabled." /> + <Enum name="REPEATER" start="0x1" description="Repeater. P2.0 pin has repeater mode enabled." /> + <Enum name="DISABLED" start="0x2" description="Disabled. P2.0 pin has neither pull-up nor pull-down." /> + <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P2.0 has a pull-down resistor enabled." /> + </BitField> + <BitField start="2" size="2" name="P2_01MODE" description="Port 2 pin 1 control."> + <Enum name="PULL_UP" start="0x0" description="Pull-up. P2.1 pin has a pull-up resistor enabled." /> + <Enum name="REPEATER" start="0x1" description="Repeater. P2.1 pin has repeater mode enabled." /> + <Enum name="DISABLED" start="0x2" description="Disabled. P2.1 pin has neither pull-up nor pull-down." /> + <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P2.1 has a pull-down resistor enabled." /> + </BitField> + <BitField start="4" size="2" name="P2_02MODE" description="Port 2 pin 2 control."> + <Enum name="PULL_UP" start="0x0" description="Pull-up. P2.2 pin has a pull-up resistor enabled." /> + <Enum name="REPEATER" start="0x1" description="Repeater. P2.2 pin has repeater mode enabled." /> + <Enum name="DISABLED" start="0x2" description="Disabled. P2.2 pin has neither pull-up nor pull-down." /> + <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P2.2 has a pull-down resistor enabled." /> + </BitField> + <BitField start="6" size="2" name="P2_03MODE" description="Port 2 pin 3 control."> + <Enum name="PULL_UP" start="0x0" description="Pull-up. P2.3 pin has a pull-up resistor enabled." /> + <Enum name="REPEATER" start="0x1" description="Repeater. P2.3 pin has repeater mode enabled." /> + <Enum name="DISABLED" start="0x2" description="Disabled. P2.3 pin has neither pull-up nor pull-down." /> + <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P2.3 has a pull-down resistor enabled." /> + </BitField> + <BitField start="8" size="2" name="P2_04MODE" description="Port 2 pin 4 control."> + <Enum name="PULL_UP" start="0x0" description="Pull-up. P2.4 pin has a pull-up resistor enabled." /> + <Enum name="REPEATER" start="0x1" description="Repeater. P2.4 pin has repeater mode enabled." /> + <Enum name="DISABLED" start="0x2" description="Disabled. P2.4 pin has neither pull-up nor pull-down." /> + <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P2.4 has a pull-down resistor enabled." /> + </BitField> + <BitField start="10" size="2" name="P2_05MODE" description="Port 2 pin 5 control."> + <Enum name="PULL_UP" start="0x0" description="Pull-up. P2.5 pin has a pull-up resistor enabled." /> + <Enum name="REPEATER" start="0x1" description="Repeater. P2.5 pin has repeater mode enabled." /> + <Enum name="DISABLED" start="0x2" description="Disabled. P2.5 pin has neither pull-up nor pull-down." /> + <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P2.5 has a pull-down resistor enabled." /> + </BitField> + <BitField start="12" size="2" name="P2_06MODE" description="Port 2 pin 6 control."> + <Enum name="PULL_UP" start="0x0" description="Pull-up. P2.6 pin has a pull-up resistor enabled." /> + <Enum name="REPEATER" start="0x1" description="Repeater. P2.6 pin has repeater mode enabled." /> + <Enum name="DISABLED" start="0x2" description="Disabled. P2.6 pin has neither pull-up nor pull-down." /> + <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P2.6 has a pull-down resistor enabled." /> + </BitField> + <BitField start="14" size="2" name="P2_07MODE" description="Port 2 pin 7 control."> + <Enum name="PULL_UP" start="0x0" description="Pull-up. P2.7 pin has a pull-up resistor enabled." /> + <Enum name="REPEATER" start="0x1" description="Repeater. P2.7 pin has repeater mode enabled." /> + <Enum name="DISABLED" start="0x2" description="Disabled. P2.7 pin has neither pull-up nor pull-down." /> + <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P2.7 has a pull-down resistor enabled." /> + </BitField> + <BitField start="16" size="2" name="P2_08MODE" description="Port 2 pin 8 control."> + <Enum name="PULL_UP" start="0x0" description="Pull-up. P2.8 pin has a pull-up resistor enabled." /> + <Enum name="REPEATER" start="0x1" description="Repeater. P2.8 pin has repeater mode enabled." /> + <Enum name="DISABLED" start="0x2" description="Disabled. P2.8 pin has neither pull-up nor pull-down." /> + <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P2.8 has a pull-down resistor enabled." /> + </BitField> + <BitField start="18" size="2" name="P2_09MODE" description="Port 2 pin 9 control."> + <Enum name="PULL_UP" start="0x0" description="Pull-up. P2.9 pin has a pull-up resistor enabled." /> + <Enum name="REPEATER" start="0x1" description="Repeater. P2.9 pin has repeater mode enabled." /> + <Enum name="DISABLED" start="0x2" description="Disabled. P2.9 pin has neither pull-up nor pull-down." /> + <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P2.9 has a pull-down resistor enabled." /> + </BitField> + <BitField start="20" size="2" name="P2_10MODE" description="Port 2 pin 10 control."> + <Enum name="PULL_UP" start="0x0" description="Pull-up. P2.10 pin has a pull-up resistor enabled." /> + <Enum name="REPEATER" start="0x1" description="Repeater. P2.10 pin has repeater mode enabled." /> + <Enum name="DISABLED" start="0x2" description="Disabled. P2.10 pin has neither pull-up nor pull-down." /> + <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P2.10 has a pull-down resistor enabled." /> + </BitField> + <BitField start="22" size="2" name="P2_11MODE" description="Port 2 pin 11 control."> + <Enum name="PULL_UP" start="0x0" description="Pull-up. P2.11 pin has a pull-up resistor enabled." /> + <Enum name="REPEATER" start="0x1" description="Repeater. P2.11 pin has repeater mode enabled." /> + <Enum name="DISABLED" start="0x2" description="Disabled. P2.11 pin has neither pull-up nor pull-down." /> + <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P2.11 has a pull-down resistor enabled." /> + </BitField> + <BitField start="24" size="2" name="P2_12MODE" description="Port 2 pin 12 control."> + <Enum name="PULL_UP" start="0x0" description="Pull-up. P2.12 pin has a pull-up resistor enabled." /> + <Enum name="REPEATER" start="0x1" description="Repeater. P2.12 pin has repeater mode enabled." /> + <Enum name="DISABLED" start="0x2" description="Disabled. P2.12 pin has neither pull-up nor pull-down." /> + <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P2.12 has a pull-down resistor enabled." /> + </BitField> + <BitField start="26" size="2" name="P2_13MODE" description="Port 2 pin 13 control."> + <Enum name="PULL_UP" start="0x0" description="Pull-up. P2.13 pin has a pull-up resistor enabled." /> + <Enum name="REPEATER" start="0x1" description="Repeater. P2.13 pin has repeater mode enabled." /> + <Enum name="DISABLED" start="0x2" description="Disabled. P2.13 pin has neither pull-up nor pull-down." /> + <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P2.13 has a pull-down resistor enabled." /> + </BitField> + <BitField start="28" size="4" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x05C" size="4" name="PINMODE7" access="Read/Write" description="Pin mode select register 7" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="18" name="RESERVED" description="Reserved" /> + <BitField start="18" size="2" name="P3_25MODE" description="Port 3 pin 25 control."> + <Enum name="PULL_UP" start="0x0" description="Pull-up. P3.25 pin has a pull-up resistor enabled." /> + <Enum name="REPEATER" start="0x1" description="Repeater. P3.25 pin has repeater mode enabled." /> + <Enum name="DISABLED" start="0x2" description="Disabled. P3.25 pin has neither pull-up nor pull-down." /> + <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P3.25 has a pull-down resistor enabled." /> + </BitField> + <BitField start="20" size="2" name="P3_26MODE" description="Port 3 pin 26 control."> + <Enum name="PULL_UP" start="0x0" description="Pull-up. P3.26 pin has a pull-up resistor enabled." /> + <Enum name="REPEATER" start="0x1" description="Repeater. P3.26 pin has repeater mode enabled." /> + <Enum name="DISABLED" start="0x2" description="Disabled. P3.26 pin has neither pull-up nor pull-down." /> + <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P3.26 has a pull-down resistor enabled." /> + </BitField> + <BitField start="22" size="10" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x064" size="4" name="PINMODE9" access="Read/Write" description="Pin mode select register 9" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="24" name="RESERVED" description="Reserved." /> + <BitField start="24" size="2" name="P4_28MODE" description="Port 4 pin 28 control."> + <Enum name="PULL_UP" start="0x0" description="Pull-up. P4.28 pin has a pull-up resistor enabled." /> + <Enum name="REPEATER" start="0x1" description="Repeater. P4.28 pin has repeater mode enabled." /> + <Enum name="DISABLED" start="0x2" description="Disabled. P4.28 pin has neither pull-up nor pull-down." /> + <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P4.28 has a pull-down resistor enabled." /> + </BitField> + <BitField start="26" size="2" name="P4_29MODE" description="Port 4 pin 29 control."> + <Enum name="PULL_UP" start="0x0" description="Pull-up. P4.29 pin has a pull-up resistor enabled." /> + <Enum name="REPEATER" start="0x1" description="Repeater. P4.29 pin has repeater mode enabled." /> + <Enum name="DISABLED" start="0x2" description="Disabled. P4.29 pin has neither pull-up nor pull-down." /> + <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P4.29 has a pull-down resistor enabled." /> + </BitField> + <BitField start="28" size="4" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x068" size="4" name="PINMODE_OD0" access="Read/Write" description="Open drain mode control register 0" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="P0_00OD" description="Port 0 pin 0 open drain mode control. Pins may potentially be used for I2C-buses using standard port pins. If so, they should be configured for open drain mode via the related bits in PINMODE_OD0."> + <Enum name="NORMAL" start="0" description="Normal. P0.0 pin is in the normal (not open drain) mode." /> + <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P0.0 pin is in the open drain mode." /> + </BitField> + <BitField start="1" size="1" name="P0_01OD" description="Port 0 pin 1 open drain mode control. Pins may potentially be used for I2C-buses using standard port pins. If so, they should be configured for open drain mode via the related bits in PINMODE_OD0."> + <Enum name="NORMAL" start="0" description="Normal. P0.1 pin is in the normal (not open drain) mode." /> + <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P0.1 pin is in the open drain mode." /> + </BitField> + <BitField start="2" size="1" name="P0_02OD" description="Port 0 pin 2 open drain mode control"> + <Enum name="NORMAL" start="0" description="Normal. P0.2 pin is in the normal (not open drain) mode." /> + <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P0.2 pin is in the open drain mode." /> + </BitField> + <BitField start="3" size="1" name="P0_03OD" description="Port 0 pin 3 open drain mode control"> + <Enum name="NORMAL" start="0" description="Normal. P0.3 pin is in the normal (not open drain) mode." /> + <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P0.3 pin is in the open drain mode." /> + </BitField> + <BitField start="4" size="1" name="P0_04OD" description="Port 0 pin 4 open drain mode control"> + <Enum name="NORMAL" start="0" description="Normal. P0.4 pin is in the normal (not open drain) mode." /> + <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P0.4 pin is in the open drain mode." /> + </BitField> + <BitField start="5" size="1" name="P0_05OD" description="Port 0 pin 5 open drain mode control"> + <Enum name="NORMAL" start="0" description="Normal. P0.5 pin is in the normal (not open drain) mode." /> + <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P0.5 pin is in the open drain mode." /> + </BitField> + <BitField start="6" size="1" name="P0_06OD" description="Port 0 pin 6 open drain mode control"> + <Enum name="NORMAL" start="0" description="Normal. P0.6 pin is in the normal (not open drain) mode." /> + <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P0.6 pin is in the open drain mode." /> + </BitField> + <BitField start="7" size="1" name="P0_07OD" description="Port 0 pin 7 open drain mode control"> + <Enum name="NORMAL" start="0" description="Normal. P0.7 pin is in the normal (not open drain) mode." /> + <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P0.7 pin is in the open drain mode." /> + </BitField> + <BitField start="8" size="1" name="P0_08OD" description="Port 0 pin 8 open drain mode control"> + <Enum name="NORMAL" start="0" description="Normal. P0.8 pin is in the normal (not open drain) mode." /> + <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P0.8 pin is in the open drain mode." /> + </BitField> + <BitField start="9" size="1" name="P0_09OD" description="Port 0 pin 9 open drain mode control"> + <Enum name="NORMAL" start="0" description="Normal. P0.9 pin is in the normal (not open drain) mode." /> + <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P0.9 pin is in the open drain mode." /> + </BitField> + <BitField start="10" size="1" name="P0_10OD" description="Port 0 pin 10 open drain mode control. Pins may potentially be used for I2C-buses using standard port pins. If so, they should be configured for open drain mode via the related bits in PINMODE_OD0."> + <Enum name="NORMAL" start="0" description="Normal. P0.10 pin is in the normal (not open drain) mode." /> + <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P0.10 pin is in the open drain mode." /> + </BitField> + <BitField start="11" size="1" name="P0_11OD" description="Port 0 pin 11 open drain mode control. Pins may potentially be used for I2C-buses using standard port pins. If so, they should be configured for open drain mode via the related bits in PINMODE_OD0."> + <Enum name="NORMAL" start="0" description="Normal. P0.11 pin is in the normal (not open drain) mode." /> + <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P0.11 pin is in the open drain mode." /> + </BitField> + <BitField start="12" size="3" name="RESERVED" description="Reserved." /> + <BitField start="15" size="1" name="P0_15OD" description="Port 0 pin 15 open drain mode control"> + <Enum name="NORMAL" start="0" description="Normal. P0.15 pin is in the normal (not open drain) mode." /> + <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P0.15 pin is in the open drain mode." /> + </BitField> + <BitField start="16" size="1" name="P0_16OD" description="Port 0 pin 16 open drain mode control"> + <Enum name="NORMAL" start="0" description="Normal. P0.16 pin is in the normal (not open drain) mode." /> + <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P0.16 pin is in the open drain mode." /> + </BitField> + <BitField start="17" size="1" name="P0_17OD" description="Port 0 pin 17 open drain mode control"> + <Enum name="NORMAL" start="0" description="Normal. P0.17 pin is in the normal (not open drain) mode." /> + <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P0.17 pin is in the open drain mode." /> + </BitField> + <BitField start="18" size="1" name="P0_18OD" description="Port 0 pin 18 open drain mode control"> + <Enum name="NORMAL" start="0" description="Normal. P0.18 pin is in the normal (not open drain) mode." /> + <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P0.18 pin is in the open drain mode." /> + </BitField> + <BitField start="19" size="1" name="P0_19OD" description="Port 0 pin 19 open drain mode control. Pins may potentially be used for I2C-buses using standard port pins. If so, they should be configured for open drain mode via the related bits in PINMODE_OD0."> + <Enum name="NORMAL" start="0" description="Normal. P0.19 pin is in the normal (not open drain) mode." /> + <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P0.19 pin is in the open drain mode." /> + </BitField> + <BitField start="20" size="1" name="P0_20OD" description="Port 0 pin 20open drain mode control. Pins may potentially be used for I2C-buses using standard port pins. If so, they should be configured for open drain mode via the related bits in PINMODE_OD0."> + <Enum name="NORMAL" start="0" description="Normal. P0.20 pin is in the normal (not open drain) mode." /> + <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P0.20 pin is in the open drain mode." /> + </BitField> + <BitField start="21" size="1" name="P0_21OD" description="Port 0 pin 21 open drain mode control"> + <Enum name="NORMAL" start="0" description="Normal. P0.21 pin is in the normal (not open drain) mode." /> + <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P0.21 pin is in the open drain mode." /> + </BitField> + <BitField start="22" size="1" name="P0_22OD" description="Port 0 pin 22 open drain mode control"> + <Enum name="NORMAL" start="0" description="Normal. P0.22 pin is in the normal (not open drain) mode." /> + <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P0.22 pin is in the open drain mode." /> + </BitField> + <BitField start="23" size="1" name="P0_23OD" description="Port 0 pin 23 open drain mode control"> + <Enum name="NORMAL" start="0" description="Normal. P0.23 pin is in the normal (not open drain) mode." /> + <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P0.23 pin is in the open drain mode." /> + </BitField> + <BitField start="24" size="1" name="P0_24OD" description="Port 0 pin 24open drain mode control"> + <Enum name="NORMAL" start="0" description="Normal. P0.23 pin is in the normal (not open drain) mode." /> + <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P0.23 pin is in the open drain mode." /> + </BitField> + <BitField start="25" size="1" name="P0_25OD" description="Port 0 pin 25 open drain mode control"> + <Enum name="NORMAL" start="0" description="Normal. P0.25 pin is in the normal (not open drain) mode." /> + <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P0.25 pin is in the open drain mode." /> + </BitField> + <BitField start="26" size="1" name="P0_26OD" description="Port 0 pin 26 open drain mode control"> + <Enum name="NORMAL" start="0" description="Normal. P0.26 pin is in the normal (not open drain) mode." /> + <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P0.26 pin is in the open drain mode." /> + </BitField> + <BitField start="27" size="2" name="RESERVED" description="Reserved." /> + <BitField start="29" size="1" name="P0_29OD" description="Port 0 pin 29 open drain mode control"> + <Enum name="NORMAL" start="0" description="Normal. P0.29 pin is in the normal (not open drain) mode." /> + <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P0.29 pin is in the open drain mode." /> + </BitField> + <BitField start="30" size="1" name="P0_30OD" description="Port 0 pin 30 open drain mode control"> + <Enum name="NORMAL" start="0" description="Normal. P0.30 pin is in the normal (not open drain) mode." /> + <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P0.30 pin is in the open drain mode." /> + </BitField> + <BitField start="31" size="1" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x06C" size="4" name="PINMODE_OD1" access="Read/Write" description="Open drain mode control register 1" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="P1_00OD" description="Port 1 pin 0 open drain mode control."> + <Enum name="NORMAL" start="0" description="Normal. P1.0 pin is in the normal (not open drain) mode." /> + <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P1.0 pin is in the open drain mode." /> + </BitField> + <BitField start="1" size="1" name="P1_01OD" description="Port 1 pin 1 open drain mode control, see P1.00OD"> + <Enum name="NORMAL" start="0" description="Normal. P1.1 pin is in the normal (not open drain) mode." /> + <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P1.1 pin is in the open drain mode." /> + </BitField> + <BitField start="2" size="2" name="RESERVED" description="Reserved." /> + <BitField start="4" size="1" name="P1_04OD" description="Port 1 pin 4 open drain mode control, see P1.00OD"> + <Enum name="NORMAL" start="0" description="Normal. P1.4 pin is in the normal (not open drain) mode." /> + <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P1.4 pin is in the open drain mode." /> + </BitField> + <BitField start="5" size="3" name="RESERVED" description="Reserved." /> + <BitField start="8" size="1" name="P1_08OD" description="Port 1 pin 8 open drain mode control, see P1.00OD"> + <Enum name="NORMAL" start="0" description="Normal. P1.8 pin is in the normal (not open drain) mode." /> + <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P1.8 pin is in the open drain mode." /> + </BitField> + <BitField start="9" size="1" name="P1_09OD" description="Port 1 pin 9 open drain mode control, see P1.00OD"> + <Enum name="NORMAL" start="0" description="Normal. P1.9 pin is in the normal (not open drain) mode." /> + <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P1.9 pin is in the open drain mode." /> + </BitField> + <BitField start="10" size="1" name="P1_10OD" description="Port 1 pin 10 open drain mode control, see P1.00OD"> + <Enum name="NORMAL" start="0" description="Normal. P1.10 pin is in the normal (not open drain) mode." /> + <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P1.10 pin is in the open drain mode." /> + </BitField> + <BitField start="11" size="3" name="RESERVED" description="Reserved." /> + <BitField start="14" size="1" name="P1_14OD" description="Port 1 pin 14 open drain mode control, see P1.00OD"> + <Enum name="NORMAL" start="0" description="Normal. P1.14 pin is in the normal (not open drain) mode." /> + <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P1.14 pin is in the open drain mode." /> + </BitField> + <BitField start="15" size="1" name="P1_15OD" description="Port 1 pin 15 open drain mode control, see P1.00OD"> + <Enum name="NORMAL" start="0" description="Normal. P1.15 pin is in the normal (not open drain) mode." /> + <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P1.15 pin is in the open drain mode." /> + </BitField> + <BitField start="16" size="1" name="P1_16OD" description="Port 1 pin 16 open drain mode control, see P1.00OD"> + <Enum name="NORMAL" start="0" description="Normal. P1.16 pin is in the normal (not open drain) mode." /> + <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P1.16 pin is in the open drain mode." /> + </BitField> + <BitField start="17" size="1" name="P1_17OD" description="Port 1 pin 17 open drain mode control, see P1.00OD"> + <Enum name="NORMAL" start="0" description="Normal. P1.17 pin is in the normal (not open drain) mode." /> + <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P1.17 pin is in the open drain mode." /> + </BitField> + <BitField start="18" size="1" name="P1_18OD" description="Port 1 pin 18 open drain mode control, see P1.00OD"> + <Enum name="NORMAL" start="0" description="Normal. P1.18 pin is in the normal (not open drain) mode." /> + <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P1.18 pin is in the open drain mode." /> + </BitField> + <BitField start="19" size="1" name="P1_19OD" description="Port 1 pin 19 open drain mode control, see P1.00OD"> + <Enum name="NORMAL" start="0" description="Normal. P1.19 pin is in the normal (not open drain) mode." /> + <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P1.19 pin is in the open drain mode." /> + </BitField> + <BitField start="20" size="1" name="P1_20OD" description="Port 1 pin 20open drain mode control, see P1.00OD"> + <Enum name="NORMAL" start="0" description="Normal. P1.20 pin is in the normal (not open drain) mode." /> + <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P1.20 pin is in the open drain mode." /> + </BitField> + <BitField start="21" size="1" name="P1_21OD" description="Port 1 pin 21 open drain mode control, see P1.00OD"> + <Enum name="NORMAL" start="0" description="Normal. P1.21 pin is in the normal (not open drain) mode." /> + <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P1.21 pin is in the open drain mode." /> + </BitField> + <BitField start="22" size="1" name="P1_22OD" description="Port 1 pin 22 open drain mode control, see P1.00OD"> + <Enum name="NORMAL" start="0" description="Normal. P1.22 pin is in the normal (not open drain) mode." /> + <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P1.22 pin is in the open drain mode." /> + </BitField> + <BitField start="23" size="1" name="P1_23OD" description="Port 1 pin 23 open drain mode control, see P1.00OD"> + <Enum name="NORMAL" start="0" description="Normal. P1.23 pin is in the normal (not open drain) mode." /> + <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P1.23 pin is in the open drain mode." /> + </BitField> + <BitField start="24" size="1" name="P1_24OD" description="Port 1 pin 24open drain mode control, see P1.00OD"> + <Enum name="NORMAL" start="0" description="Normal. P1.24 pin is in the normal (not open drain) mode." /> + <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P1.24 pin is in the open drain mode." /> + </BitField> + <BitField start="25" size="1" name="P1_25OD" description="Port 1 pin 25 open drain mode control, see P1.00OD"> + <Enum name="NORMAL" start="0" description="Normal. P1.25 pin is in the normal (not open drain) mode." /> + <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P1.25 pin is in the open drain mode." /> + </BitField> + <BitField start="26" size="1" name="P1_26OD" description="Port 1 pin 26 open drain mode control, see P1.00OD"> + <Enum name="NORMAL" start="0" description="Normal. P1.26 pin is in the normal (not open drain) mode." /> + <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P1.26 pin is in the open drain mode." /> + </BitField> + <BitField start="27" size="1" name="P1_27OD" description="Port 1 pin 27 open drain mode control, see P1.00OD"> + <Enum name="NORMAL" start="0" description="Normal. P1.27 pin is in the normal (not open drain) mode." /> + <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P1.27 pin is in the open drain mode." /> + </BitField> + <BitField start="28" size="1" name="P1_28OD" description="Port 1 pin 28 open drain mode control, see P1.00OD"> + <Enum name="NORMAL" start="0" description="Normal. P1.28 pin is in the normal (not open drain) mode." /> + <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P1.28 pin is in the open drain mode." /> + </BitField> + <BitField start="29" size="1" name="P1_29OD" description="Port 1 pin 29 open drain mode control, see P1.00OD"> + <Enum name="NORMAL" start="0" description="Normal. P1.29 pin is in the normal (not open drain) mode." /> + <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P1.29 pin is in the open drain mode." /> + </BitField> + <BitField start="30" size="1" name="P1_30OD" description="Port 1 pin 30 open drain mode control, see P1.00OD"> + <Enum name="NORMAL" start="0" description="Normal. P1.30 pin is in the normal (not open drain) mode." /> + <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P1.30 pin is in the open drain mode." /> + </BitField> + <BitField start="31" size="1" name="P1_31OD" description="Port 1 pin 31 open drain mode control."> + <Enum name="NORMAL" start="0" description="Normal. P1.31 pin is in the normal (not open drain) mode." /> + <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P1.31 pin is in the open drain mode." /> + </BitField> + </Register> + <Register start="+0x070" size="4" name="PINMODE_OD2" access="Read/Write" description="Open drain mode control register 2" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="P2_00OD" description="Port 2 pin 0 open drain mode control."> + <Enum name="NORMAL" start="0" description="Normal. P2.0 pin is in the normal (not open drain) mode." /> + <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P2.0 pin is in the open drain mode." /> + </BitField> + <BitField start="1" size="1" name="P2_01OD" description="Port 2 pin 1 open drain mode control, see P2.00OD"> + <Enum name="NORMAL" start="0" description="Normal. P2.1 pin is in the normal (not open drain) mode." /> + <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P2.1p in is in the open drain mode." /> + </BitField> + <BitField start="2" size="1" name="P2_02OD" description="Port 2 pin 2 open drain mode control, see P2.00OD"> + <Enum name="NORMAL" start="0" description="Normal. P2.2 pin is in the normal (not open drain) mode." /> + <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P2.2 pin is in the open drain mode." /> + </BitField> + <BitField start="3" size="1" name="P2_03OD" description="Port 2 pin 3 open drain mode control, see P2.00OD"> + <Enum name="NORMAL" start="0" description="Normal. P2.3 pin is in the normal (not open drain) mode." /> + <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P2.3 pin is in the open drain mode." /> + </BitField> + <BitField start="4" size="1" name="P2_04OD" description="Port 2 pin 4 open drain mode control, see P2.00OD"> + <Enum name="NORMAL" start="0" description="Normal. P2.4 pin is in the normal (not open drain) mode." /> + <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P2.4 pin is in the open drain mode." /> + </BitField> + <BitField start="5" size="1" name="P2_05OD" description="Port 2 pin 5 open drain mode control, see P2.00OD"> + <Enum name="NORMAL" start="0" description="Normal. P2.5 pin is in the normal (not open drain) mode." /> + <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P2.5 pin is in the open drain mode." /> + </BitField> + <BitField start="6" size="1" name="P2_06OD" description="Port 2 pin 6 open drain mode control, see P2.00OD"> + <Enum name="NORMAL" start="0" description="Normal. P2.6 pin is in the normal (not open drain) mode." /> + <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P2.6 pin is in the open drain mode." /> + </BitField> + <BitField start="7" size="1" name="P2_07OD" description="Port 2 pin 7 open drain mode control, see P2.00OD"> + <Enum name="NORMAL" start="0" description="Normal. P2.7 pin is in the normal (not open drain) mode." /> + <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P2.7 pin is in the open drain mode." /> + </BitField> + <BitField start="8" size="1" name="P2_08OD" description="Port 2 pin 8 open drain mode control, see P2.00OD"> + <Enum name="NORMAL" start="0" description="Normal. P2.8 pin is in the normal (not open drain) mode." /> + <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P2.8 pin is in the open drain mode." /> + </BitField> + <BitField start="9" size="1" name="P2_09OD" description="Port 2 pin 9 open drain mode control, see P2.00OD"> + <Enum name="NORMAL" start="0" description="Normal. P2.9 pin is in the normal (not open drain) mode." /> + <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P2.9 pin is in the open drain mode." /> + </BitField> + <BitField start="10" size="1" name="P2_10OD" description="Port 2 pin 10 open drain mode control, see P2.00OD"> + <Enum name="NORMAL" start="0" description="Normal. P2.10 pin is in the normal (not open drain) mode." /> + <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P2.10 pin is in the open drain mode." /> + </BitField> + <BitField start="11" size="1" name="P2_11OD" description="Port 2 pin 11 open drain mode control, see P2.00OD"> + <Enum name="NORMAL" start="0" description="Normal. P2.11 pin is in the normal (not open drain) mode." /> + <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P2.11 pin is in the open drain mode." /> + </BitField> + <BitField start="12" size="1" name="P2_12OD" description="Port 2 pin 12 open drain mode control, see P2.00OD"> + <Enum name="NORMAL" start="0" description="Normal. P2.12 pin is in the normal (not open drain) mode." /> + <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P2.12 pin is in the open drain mode." /> + </BitField> + <BitField start="13" size="1" name="P2_13OD" description="Port 2 pin 13 open drain mode control, see P2.00OD"> + <Enum name="NORMAL" start="0" description="Normal. P2.13 pin is in the normal (not open drain) mode." /> + <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P2.13 pin is in the open drain mode." /> + </BitField> + <BitField start="14" size="18" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x074" size="4" name="PINMODE_OD3" access="Read/Write" description="Open drain mode control register 3" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="25" name="RESERVED" description="Reserved." /> + <BitField start="25" size="1" name="P3_25OD" description="Port 3 pin 25 open drain mode control."> + <Enum name="NORMAL" start="0" description="Normal. P3.25 pin is in the normal (not open drain) mode." /> + <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P3.25 pin is in the open drain mode." /> + </BitField> + <BitField start="26" size="1" name="P3_26OD" description="Port 3 pin 26 open drain mode control, see P3.25OD" /> + <BitField start="27" size="5" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x078" size="4" name="PINMODE_OD4" access="Read/Write" description="Open drain mode control register 4" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="28" name="RESERVED" description="Reserved." /> + <BitField start="28" size="1" name="P4_28OD" description="Port 4 pin 28 open drain mode control."> + <Enum name="NORMAL" start="0" description="Normal. P4.28 pin is in the normal (not open drain) mode." /> + <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P4.28 pin is in the open drain mode." /> + </BitField> + <BitField start="29" size="1" name="P4_29OD" description="Port 4 pin 29 open drain mode control, see P4.28OD" /> + <BitField start="30" size="2" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x07C" size="4" name="I2CPADCFG" access="Read/Write" description="I2C Pin Configuration register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="SDADRV0" description="Drive mode control for the SDA0 pin, P0.27."> + <Enum name="STANDARD" start="0" description="Standard. The SDA0 pin is in the standard drive mode." /> + <Enum name="FAST_MODE_PLUS" start="1" description="Fast-mode plus. The SDA0 pin is in Fast Mode Plus drive mode." /> + </BitField> + <BitField start="1" size="1" name="SDAI2C0" description="I 2C filter mode control for the SDA0 pin, P0.27."> + <Enum name="ENABLED" start="0" description="Enabled. The SDA0 pin has I2C glitch filtering and slew rate control enabled." /> + <Enum name="DISABLED" start="1" description="Disabled. The SDA0 pin has I2C glitch filtering and slew rate control disabled." /> + </BitField> + <BitField start="2" size="1" name="SCLDRV0" description="Drive mode control for the SCL0 pin, P0.28."> + <Enum name="STANDARD" start="0" description="Standard. The SCL0 pin is in the standard drive mode." /> + <Enum name="FAST_MODE_PLUS" start="1" description="Fast-mode plus. The SCL0 pin is in Fast Mode Plus drive mode." /> + </BitField> + <BitField start="3" size="1" name="SCLI2C0" description="I 2C filter mode control for the SCL0 pin, P0.28."> + <Enum name="ENABLED" start="0" description="Enabled. The SCL0 pin has I2C glitch filtering and slew rate control enabled." /> + <Enum name="DISABLED" start="1" description="Disabled. The SCL0 pin has I2C glitch filtering and slew rate control disabled." /> + </BitField> + <BitField start="4" size="28" name="RESERVED" description="Reserved." /> + </Register> + </RegisterGroup> + <RegisterGroup name="SSP1" start="0x40030000" description="SSP1 controller"> + <Register start="+0x000" size="4" name="CR0" access="Read/Write" description="Control Register 0. Selects the serial clock rate, bus type, and data size." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="4" name="DSS" description="Data Size Select. This field controls the number of bits transferred in each frame. Values 0000-0010 are not supported and should not be used."> + <Enum name="4_BIT_TRANSFER" start="0x3" description="4-bit transfer" /> + <Enum name="5_BIT_TRANSFER" start="0x4" description="5-bit transfer" /> + <Enum name="6_BIT_TRANSFER" start="0x5" description="6-bit transfer" /> + <Enum name="7_BIT_TRANSFER" start="0x6" description="7-bit transfer" /> + <Enum name="8_BIT_TRANSFER" start="0x7" description="8-bit transfer" /> + <Enum name="9_BIT_TRANSFER" start="0x8" description="9-bit transfer" /> + <Enum name="10_BIT_TRANSFER" start="0x9" description="10-bit transfer" /> + <Enum name="11_BIT_TRANSFER" start="0xA" description="11-bit transfer" /> + <Enum name="12_BIT_TRANSFER" start="0xB" description="12-bit transfer" /> + <Enum name="13_BIT_TRANSFER" start="0xC" description="13-bit transfer" /> + <Enum name="14_BIT_TRANSFER" start="0xD" description="14-bit transfer" /> + <Enum name="15_BIT_TRANSFER" start="0xE" description="15-bit transfer" /> + <Enum name="16_BIT_TRANSFER" start="0xF" description="16-bit transfer" /> + </BitField> + <BitField start="4" size="2" name="FRF" description="Frame Format."> + <Enum name="SPI" start="0x0" description="SPI" /> + <Enum name="TI" start="0x1" description="TI" /> + <Enum name="MICROWIRE" start="0x2" description="Microwire" /> + <Enum name="THIS_COMBINATION_IS_" start="0x3" description="This combination is not supported and should not be used." /> + </BitField> + <BitField start="6" size="1" name="CPOL" description="Clock Out Polarity. This bit is only used in SPI mode."> + <Enum name="BUS_LOW" start="0" description="SSP controller maintains the bus clock low between frames." /> + <Enum name="BUS_HIGH" start="1" description="SSP controller maintains the bus clock high between frames." /> + </BitField> + <BitField start="7" size="1" name="CPHA" description="Clock Out Phase. This bit is only used in SPI mode."> + <Enum name="FIRST_CLOCK" start="0" description="SSP controller captures serial data on the first clock transition of the frame, that is, the transition away from the inter-frame state of the clock line." /> + <Enum name="SECOND_CLOCK" start="1" description="SSP controller captures serial data on the second clock transition of the frame, that is, the transition back to the inter-frame state of the clock line." /> + </BitField> + <BitField start="8" size="8" name="SCR" description="Serial Clock Rate. The number of prescaler-output clocks per bit on the bus, minus one. Given that CPSDVSR is the prescale divider, and the APB clock PCLK clocks the prescaler, the bit frequency is PCLK / (CPSDVSR X [SCR+1])." /> + <BitField start="16" size="16" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x004" size="4" name="CR1" access="Read/Write" description="Control Register 1. Selects master/slave and other modes." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="LBM" description="Loop Back Mode."> + <Enum name="NORMAL" start="0" description="During normal operation." /> + <Enum name="OUPTU" start="1" description="Serial input is taken from the serial output (MOSI or MISO) rather than the serial input pin (MISO or MOSI respectively)." /> + </BitField> + <BitField start="1" size="1" name="SSE" description="SSP Enable."> + <Enum name="DISABLED" start="0" description="The SSP controller is disabled." /> + <Enum name="ENABLED" start="1" description="The SSP controller will interact with other devices on the serial bus. Software should write the appropriate control information to the other SSP registers and interrupt controller registers, before setting this bit." /> + </BitField> + <BitField start="2" size="1" name="MS" description="Master/Slave Mode.This bit can only be written when the SSE bit is 0."> + <Enum name="MASTER" start="0" description="The SSP controller acts as a master on the bus, driving the SCLK, MOSI, and SSEL lines and receiving the MISO line." /> + <Enum name="SLAVE" start="1" description="The SSP controller acts as a slave on the bus, driving MISO line and receiving SCLK, MOSI, and SSEL lines." /> + </BitField> + <BitField start="3" size="1" name="SOD" description="Slave Output Disable. This bit is relevant only in slave mode (MS = 1). If it is 1, this blocks this SSP controller from driving the transmit data line (MISO)." /> + <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x008" size="4" name="DR" access="None" description="Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="16" name="DATA" description="Write: software can write data to be sent in a future frame to this register whenever the TNF bit in the Status register is 1, indicating that the Tx FIFO is not full. If the Tx FIFO was previously empty and the SSP controller is not busy on the bus, transmission of the data will begin immediately. Otherwise the data written to this register will be sent as soon as all previous data has been sent (and received). If the data length is less than 16 bits, software must right-justify the data written to this register. Read: software can read data from this register whenever the RNE bit in the Status register is 1, indicating that the Rx FIFO is not empty. When software reads this register, the SSP controller returns data from the least recent frame in the Rx FIFO. If the data length is less than 16 bits, the data is right-justified in this field with higher order bits filled with 0s." /> + <BitField start="16" size="16" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x00C" size="4" name="SR" access="ReadOnly" description="Status Register" reset_value="0x00000003" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="TFE" description="Transmit FIFO Empty. This bit is 1 is the Transmit FIFO is empty, 0 if not." /> + <BitField start="1" size="1" name="TNF" description="Transmit FIFO Not Full. This bit is 0 if the Tx FIFO is full, 1 if not." /> + <BitField start="2" size="1" name="RNE" description="Receive FIFO Not Empty. This bit is 0 if the Receive FIFO is empty, 1 if not." /> + <BitField start="3" size="1" name="RFF" description="Receive FIFO Full. This bit is 1 if the Receive FIFO is full, 0 if not." /> + <BitField start="4" size="1" name="BSY" description="Busy. This bit is 0 if the SSPn controller is idle, or 1 if it is currently sending/receiving a frame and/or the Tx FIFO is not empty." /> + <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x010" size="4" name="CPSR" access="Read/Write" description="Clock Prescale Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="CPSDVSR" description="This even value between 2 and 254, by which PCLK is divided to yield the prescaler output clock. Bit 0 always reads as 0." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x014" size="4" name="IMSC" access="Read/Write" description="Interrupt Mask Set and Clear Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RORIM" description="Software should set this bit to enable interrupt when a Receive Overrun occurs, that is, when the Rx FIFO is full and another frame is completely received. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs." /> + <BitField start="1" size="1" name="RTIM" description="Software should set this bit to enable interrupt when a Receive Time-out condition occurs. A Receive Time-out occurs when the Rx FIFO is not empty, and no has not been read for a time-out period. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1])." /> + <BitField start="2" size="1" name="RXIM" description="Software should set this bit to enable interrupt when the Rx FIFO is at least half full." /> + <BitField start="3" size="1" name="TXIM" description="Software should set this bit to enable interrupt when the Tx FIFO is at least half empty." /> + <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x018" size="4" name="RIS" access="ReadOnly" description="Raw Interrupt Status Register" reset_value="0x00000008" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RORRIS" description="This bit is 1 if another frame was completely received while the RxFIFO was full. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs." /> + <BitField start="1" size="1" name="RTRIS" description="This bit is 1 if the Rx FIFO is not empty, and has not been read for a time-out period. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1])." /> + <BitField start="2" size="1" name="RXRIS" description="This bit is 1 if the Rx FIFO is at least half full." /> + <BitField start="3" size="1" name="TXRIS" description="This bit is 1 if the Tx FIFO is at least half empty." /> + <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x01C" size="4" name="MIS" access="ReadOnly" description="Masked Interrupt Status Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RORMIS" description="This bit is 1 if another frame was completely received while the RxFIFO was full, and this interrupt is enabled." /> + <BitField start="1" size="1" name="RTMIS" description="This bit is 1 if the Rx FIFO is not empty, has not been read for a time-out period, and this interrupt is enabled. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1])." /> + <BitField start="2" size="1" name="RXMIS" description="This bit is 1 if the Rx FIFO is at least half full, and this interrupt is enabled." /> + <BitField start="3" size="1" name="TXMIS" description="This bit is 1 if the Tx FIFO is at least half empty, and this interrupt is enabled." /> + <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x020" size="4" name="ICR" access="WriteOnly" description="SSPICR Interrupt Clear Register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="RORIC" description="Writing a 1 to this bit clears the frame was received when RxFIFO was full interrupt." /> + <BitField start="1" size="1" name="RTIC" description="Writing a 1 to this bit clears the Rx FIFO was not empty and has not been read for a time-out period interrupt. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR / [SCR+1])." /> + <BitField start="2" size="30" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x024" size="4" name="DMACR" access="Read/Write" description="SSP0 DMA control register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RXDMAE" description="Receive DMA Enable. When this bit is set to one 1, DMA for the receive FIFO is enabled, otherwise receive DMA is disabled." /> + <BitField start="1" size="1" name="TXDMAE" description="Transmit DMA Enable. When this bit is set to one 1, DMA for the transmit FIFO is enabled, otherwise transmit DMA is disabled" /> + <BitField start="2" size="30" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + </RegisterGroup> + <RegisterGroup name="ADC" start="0x40034000" description="Analog-to-Digital Converter (ADC) "> + <Register start="+0x000" size="4" name="CR" access="Read/Write" description="A/D Control Register. The ADCR register must be written to select the operating mode before A/D conversion can occur." reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="8" name="SEL" description="Selects which of the AD0[7:0] pins is (are) to be sampled and converted. For AD0, bit 0 selects Pin AD0[0], and bit 7 selects pin AD0[7]. In software-controlled mode, only one of these bits should be 1. In hardware scan mode, any value containing 1 to 8 ones is allowed. All zeroes is equivalent to 0x01." /> + <BitField start="8" size="8" name="CLKDIV" description="The APB clock (PCLK) is divided by (this value plus one) to produce the clock for the A/D converter, which should be less than or equal to 12.4 MHz. Typically, software should program the smallest value in this field that yields a clock of 12.4 MHz or slightly less, but in certain cases (such as a high-impedance analog source) a slower clock may be desirable." /> + <BitField start="16" size="1" name="BURST" description="Burst mode"> + <Enum name="BURST" start="1" description="The AD converter does repeated conversions at up to 400 kHz, scanning (if necessary) through the pins selected by bits set to ones in the SEL field. The first conversion after the start corresponds to the least-significant 1 in the SEL field, then higher numbered 1-bits (pins) if applicable. Repeated conversions can be terminated by clearing this bit, but the conversion that's in progress when this bit is cleared will be completed. START bits must be 000 when BURST = 1 or conversions will not start." /> + <Enum name="SW" start="0" description="Conversions are software controlled and require 31 clocks." /> + </BitField> + <BitField start="17" size="4" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="21" size="1" name="PDN" description="Power down mode"> + <Enum name="POWERED" start="1" description="The A/D converter is operational." /> + <Enum name="POWERDOWN" start="0" description="The A/D converter is in power-down mode." /> + </BitField> + <BitField start="22" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="24" size="3" name="START" description="When the BURST bit is 0, these bits control whether and when an A/D conversion is started:"> + <Enum name="NO_START_THIS_VALUE" start="0x0" description="No start (this value should be used when clearing PDN to 0)." /> + <Enum name="START_CONVERSION_NOW" start="0x1" description="Start conversion now." /> + <Enum name="P2_10" start="0x2" description="Start conversion when the edge selected by bit 27 occurs on the P2[10] pin." /> + <Enum name="P1_27" start="0x3" description="Start conversion when the edge selected by bit 27 occurs on the P1[27] pin." /> + <Enum name="MAT0_1" start="0x4" description="Start conversion when the edge selected by bit 27 occurs on MAT0.1. Note that this does not require that the MAT0.1 function appear on a device pin." /> + <Enum name="MAT0_3" start="0x5" description="Start conversion when the edge selected by bit 27 occurs on MAT0.3. Note that it is not possible to cause the MAT0.3 function to appear on a device pin." /> + <Enum name="MAT1_0" start="0x6" description="Start conversion when the edge selected by bit 27 occurs on MAT1.0. Note that this does not require that the MAT1.0 function appear on a device pin." /> + <Enum name="MAT1_1" start="0x7" description="Start conversion when the edge selected by bit 27 occurs on MAT1.1. Note that this does not require that the MAT1.1 function appear on a device pin." /> + </BitField> + <BitField start="27" size="1" name="EDGE" description="This bit is significant only when the START field contains 010-111. In these cases:"> + <Enum name="FALLLING" start="1" description="Start conversion on a falling edge on the selected CAP/MAT signal." /> + <Enum name="RISING" start="0" description="Start conversion on a rising edge on the selected CAP/MAT signal." /> + </BitField> + <BitField start="28" size="4" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x004" size="4" name="GDR" access="Read/Write" description="A/D Global Data Register. This register contains the ADC's DONE bit and the result of the most recent A/D conversion." reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="4" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="4" size="12" name="RESULT" description="When DONE is 1, this field contains a binary fraction representing the voltage on the AD0[n] pin selected by the SEL field, as it falls within the range of VREFP to VSS. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VSS, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP." /> + <BitField start="16" size="8" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="24" size="3" name="CHN" description="These bits contain the channel from which the RESULT bits were converted (e.g. 000 identifies channel 0, 001 channel 1...)." /> + <BitField start="27" size="3" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the RESULT bits. This bit is cleared by reading this register." /> + <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read and when the ADCR is written. If the ADCR is written while a conversion is still in progress, this bit is set and a new conversion is started." /> + </Register> + <Register start="+0x00C" size="4" name="INTEN" access="Read/Write" description="A/D Interrupt Enable Register. This register contains enable bits that allow the DONE flag of each A/D channel to be included or excluded from contributing to the generation of an A/D interrupt." reset_value="0x100" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="ADINTEN0" description="Interrupt enable"> + <Enum name="DISABLE" start="0" description="Completion of a conversion on ADC channel 0 will not generate an interrupt." /> + <Enum name="ENABLE" start="1" description="Completion of a conversion on ADC channel 0 will generate an interrupt." /> + </BitField> + <BitField start="1" size="1" name="ADINTEN1" description="Interrupt enable"> + <Enum name="DISABLE" start="0" description="Completion of a conversion on ADC channel 1 will not generate an interrupt." /> + <Enum name="ENABLE" start="1" description="Completion of a conversion on ADC channel 1 will generate an interrupt." /> + </BitField> + <BitField start="2" size="1" name="ADINTEN2" description="Interrupt enable"> + <Enum name="DISABLE" start="0" description="Completion of a conversion on ADC channel 2 will not generate an interrupt." /> + <Enum name="ENABLE" start="1" description="Completion of a conversion on ADC channel 2 will generate an interrupt." /> + </BitField> + <BitField start="3" size="1" name="ADINTEN3" description="Interrupt enable"> + <Enum name="DISABLE" start="0" description="Completion of a conversion on ADC channel 3 will not generate an interrupt." /> + <Enum name="ENABLE" start="1" description="Completion of a conversion on ADC channel 3 will generate an interrupt." /> + </BitField> + <BitField start="4" size="1" name="ADINTEN4" description="Interrupt enable"> + <Enum name="DISABLE" start="0" description="Completion of a conversion on ADC channel 4 will not generate an interrupt." /> + <Enum name="ENABLE" start="1" description="Completion of a conversion on ADC channel 4 will generate an interrupt." /> + </BitField> + <BitField start="5" size="1" name="ADINTEN5" description="Interrupt enable"> + <Enum name="DISABLE" start="0" description="Completion of a conversion on ADC channel 5 will not generate an interrupt." /> + <Enum name="ENABLE" start="1" description="Completion of a conversion on ADC channel 5 will generate an interrupt." /> + </BitField> + <BitField start="6" size="1" name="ADINTEN6" description="Interrupt enable"> + <Enum name="DISABLE" start="0" description="Completion of a conversion on ADC channel 6 will not generate an interrupt." /> + <Enum name="ENABLE" start="1" description="Completion of a conversion on ADC channel 6 will generate an interrupt." /> + </BitField> + <BitField start="7" size="1" name="ADINTEN7" description="Interrupt enable"> + <Enum name="DISABLE" start="0" description="Completion of a conversion on ADC channel 7 will not generate an interrupt." /> + <Enum name="ENABLE" start="1" description="Completion of a conversion on ADC channel 7 will generate an interrupt." /> + </BitField> + <BitField start="8" size="1" name="ADGINTEN" description="Interrupt enable"> + <Enum name="CHANNELS" start="0" description="Only the individual ADC channels enabled by ADINTEN7:0 will generate interrupts." /> + <Enum name="GLOBAL" start="1" description="The global DONE flag in ADDR is enabled to generate an interrupt in addition to any individual ADC channels that are enabled to generate interrupts." /> + </BitField> + <BitField start="9" size="23" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x010+0" size="4" name="DR[0]" access="ReadOnly" description="A/D Channel 0 Data Register. This register contains the result of the most recent conversion completed on channel 0." reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="4" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="4" size="12" name="RESULT" description="When DONE is 1, this field contains a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to V SS. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VSS, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP." /> + <BitField start="16" size="14" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the RESULT bits.This bit is cleared by reading this register." /> + <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." /> + </Register> + <Register start="+0x010+4" size="4" name="DR[1]" access="ReadOnly" description="A/D Channel 0 Data Register. This register contains the result of the most recent conversion completed on channel 0." reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="4" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="4" size="12" name="RESULT" description="When DONE is 1, this field contains a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to V SS. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VSS, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP." /> + <BitField start="16" size="14" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the RESULT bits.This bit is cleared by reading this register." /> + <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." /> + </Register> + <Register start="+0x010+8" size="4" name="DR[2]" access="ReadOnly" description="A/D Channel 0 Data Register. This register contains the result of the most recent conversion completed on channel 0." reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="4" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="4" size="12" name="RESULT" description="When DONE is 1, this field contains a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to V SS. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VSS, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP." /> + <BitField start="16" size="14" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the RESULT bits.This bit is cleared by reading this register." /> + <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." /> + </Register> + <Register start="+0x010+12" size="4" name="DR[3]" access="ReadOnly" description="A/D Channel 0 Data Register. This register contains the result of the most recent conversion completed on channel 0." reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="4" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="4" size="12" name="RESULT" description="When DONE is 1, this field contains a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to V SS. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VSS, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP." /> + <BitField start="16" size="14" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the RESULT bits.This bit is cleared by reading this register." /> + <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." /> + </Register> + <Register start="+0x010+16" size="4" name="DR[4]" access="ReadOnly" description="A/D Channel 0 Data Register. This register contains the result of the most recent conversion completed on channel 0." reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="4" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="4" size="12" name="RESULT" description="When DONE is 1, this field contains a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to V SS. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VSS, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP." /> + <BitField start="16" size="14" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the RESULT bits.This bit is cleared by reading this register." /> + <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." /> + </Register> + <Register start="+0x010+20" size="4" name="DR[5]" access="ReadOnly" description="A/D Channel 0 Data Register. This register contains the result of the most recent conversion completed on channel 0." reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="4" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="4" size="12" name="RESULT" description="When DONE is 1, this field contains a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to V SS. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VSS, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP." /> + <BitField start="16" size="14" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the RESULT bits.This bit is cleared by reading this register." /> + <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." /> + </Register> + <Register start="+0x010+24" size="4" name="DR[6]" access="ReadOnly" description="A/D Channel 0 Data Register. This register contains the result of the most recent conversion completed on channel 0." reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="4" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="4" size="12" name="RESULT" description="When DONE is 1, this field contains a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to V SS. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VSS, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP." /> + <BitField start="16" size="14" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the RESULT bits.This bit is cleared by reading this register." /> + <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." /> + </Register> + <Register start="+0x010+28" size="4" name="DR[7]" access="ReadOnly" description="A/D Channel 0 Data Register. This register contains the result of the most recent conversion completed on channel 0." reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="4" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="4" size="12" name="RESULT" description="When DONE is 1, this field contains a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to V SS. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VSS, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP." /> + <BitField start="16" size="14" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the RESULT bits.This bit is cleared by reading this register." /> + <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." /> + </Register> + <Register start="+0x030" size="4" name="STAT" access="ReadOnly" description="A/D Status Register. This register contains DONE and OVERRUN flags for all of the A/D channels, as well as the A/D interrupt/DMA flag." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="DONE0" description="This bit mirrors the DONE status flag from the result register for A/D channel 0." /> + <BitField start="1" size="1" name="DONE1" description="This bit mirrors the DONE status flag from the result register for A/D channel 1." /> + <BitField start="2" size="1" name="DONE2" description="This bit mirrors the DONE status flag from the result register for A/D channel 2." /> + <BitField start="3" size="1" name="DONE3" description="This bit mirrors the DONE status flag from the result register for A/D channel 3." /> + <BitField start="4" size="1" name="DONE4" description="This bit mirrors the DONE status flag from the result register for A/D channel 4." /> + <BitField start="5" size="1" name="DONE5" description="This bit mirrors the DONE status flag from the result register for A/D channel 5." /> + <BitField start="6" size="1" name="DONE6" description="This bit mirrors the DONE status flag from the result register for A/D channel 6." /> + <BitField start="7" size="1" name="DONE7" description="This bit mirrors the DONE status flag from the result register for A/D channel 7." /> + <BitField start="8" size="1" name="OVERRUN0" description="This bit mirrors the OVERRRUN status flag from the result register for A/D channel 0." /> + <BitField start="9" size="1" name="OVERRUN1" description="This bit mirrors the OVERRRUN status flag from the result register for A/D channel 1." /> + <BitField start="10" size="1" name="OVERRUN2" description="This bit mirrors the OVERRRUN status flag from the result register for A/D channel 2." /> + <BitField start="11" size="1" name="OVERRUN3" description="This bit mirrors the OVERRRUN status flag from the result register for A/D channel 3." /> + <BitField start="12" size="1" name="OVERRUN4" description="This bit mirrors the OVERRRUN status flag from the result register for A/D channel 4." /> + <BitField start="13" size="1" name="OVERRUN5" description="This bit mirrors the OVERRRUN status flag from the result register for A/D channel 5." /> + <BitField start="14" size="1" name="OVERRUN6" description="This bit mirrors the OVERRRUN status flag from the result register for A/D channel 6." /> + <BitField start="15" size="1" name="OVERRUN7" description="This bit mirrors the OVERRRUN status flag from the result register for A/D channel 7." /> + <BitField start="16" size="1" name="ADINT" description="This bit is the A/D interrupt flag. It is one when any of the individual A/D channel Done flags is asserted and enabled to contribute to the A/D interrupt via the ADINTEN register." /> + <BitField start="17" size="15" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x034" size="4" name="TRM" access="Read/Write" description="ADC trim register." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="4" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="4" size="4" name="ADCOFFS" description="Offset trim bits for ADC operation. Initialized by the boot code. Can be overwritten by the user." /> + <BitField start="8" size="4" name="TRIM" description="written-to by boot code. Can not be overwritten by the user. These bits are locked after boot code write." /> + <BitField start="12" size="20" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + </RegisterGroup> + <RegisterGroup name="CANAFRAM" start="0x40038000" description="CAN acceptance filter RAM"> + <Register start="+0x000+0" size="4" name="MASK[0]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+4" size="4" name="MASK[1]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+8" size="4" name="MASK[2]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+12" size="4" name="MASK[3]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+16" size="4" name="MASK[4]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+20" size="4" name="MASK[5]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+24" size="4" name="MASK[6]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+28" size="4" name="MASK[7]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+32" size="4" name="MASK[8]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+36" size="4" name="MASK[9]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+40" size="4" name="MASK[10]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+44" size="4" name="MASK[11]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+48" size="4" name="MASK[12]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+52" size="4" name="MASK[13]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+56" size="4" name="MASK[14]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+60" size="4" name="MASK[15]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+64" size="4" name="MASK[16]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+68" size="4" name="MASK[17]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+72" size="4" name="MASK[18]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+76" size="4" name="MASK[19]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+80" size="4" name="MASK[20]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+84" size="4" name="MASK[21]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+88" size="4" name="MASK[22]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+92" size="4" name="MASK[23]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+96" size="4" name="MASK[24]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+100" size="4" name="MASK[25]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+104" size="4" name="MASK[26]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+108" size="4" name="MASK[27]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+112" size="4" name="MASK[28]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+116" size="4" name="MASK[29]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+120" size="4" name="MASK[30]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+124" size="4" name="MASK[31]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+128" size="4" name="MASK[32]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+132" size="4" name="MASK[33]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+136" size="4" name="MASK[34]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+140" size="4" name="MASK[35]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+144" size="4" name="MASK[36]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+148" size="4" name="MASK[37]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+152" size="4" name="MASK[38]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+156" size="4" name="MASK[39]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+160" size="4" name="MASK[40]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+164" size="4" name="MASK[41]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+168" size="4" name="MASK[42]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+172" size="4" name="MASK[43]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+176" size="4" name="MASK[44]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+180" size="4" name="MASK[45]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+184" size="4" name="MASK[46]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+188" size="4" name="MASK[47]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+192" size="4" name="MASK[48]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+196" size="4" name="MASK[49]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+200" size="4" name="MASK[50]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+204" size="4" name="MASK[51]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+208" size="4" name="MASK[52]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+212" size="4" name="MASK[53]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+216" size="4" name="MASK[54]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+220" size="4" name="MASK[55]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+224" size="4" name="MASK[56]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+228" size="4" name="MASK[57]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+232" size="4" name="MASK[58]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+236" size="4" name="MASK[59]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+240" size="4" name="MASK[60]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+244" size="4" name="MASK[61]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+248" size="4" name="MASK[62]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+252" size="4" name="MASK[63]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+256" size="4" name="MASK[64]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+260" size="4" name="MASK[65]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+264" size="4" name="MASK[66]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+268" size="4" name="MASK[67]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+272" size="4" name="MASK[68]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+276" size="4" name="MASK[69]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+280" size="4" name="MASK[70]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+284" size="4" name="MASK[71]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+288" size="4" name="MASK[72]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+292" size="4" name="MASK[73]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+296" size="4" name="MASK[74]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+300" size="4" name="MASK[75]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+304" size="4" name="MASK[76]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+308" size="4" name="MASK[77]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+312" size="4" name="MASK[78]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+316" size="4" name="MASK[79]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+320" size="4" name="MASK[80]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+324" size="4" name="MASK[81]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+328" size="4" name="MASK[82]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+332" size="4" name="MASK[83]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+336" size="4" name="MASK[84]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+340" size="4" name="MASK[85]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+344" size="4" name="MASK[86]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+348" size="4" name="MASK[87]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+352" size="4" name="MASK[88]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+356" size="4" name="MASK[89]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+360" size="4" name="MASK[90]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+364" size="4" name="MASK[91]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+368" size="4" name="MASK[92]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+372" size="4" name="MASK[93]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+376" size="4" name="MASK[94]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+380" size="4" name="MASK[95]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+384" size="4" name="MASK[96]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+388" size="4" name="MASK[97]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+392" size="4" name="MASK[98]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+396" size="4" name="MASK[99]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+400" size="4" name="MASK[100]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+404" size="4" name="MASK[101]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+408" size="4" name="MASK[102]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+412" size="4" name="MASK[103]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+416" size="4" name="MASK[104]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+420" size="4" name="MASK[105]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+424" size="4" name="MASK[106]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+428" size="4" name="MASK[107]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+432" size="4" name="MASK[108]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+436" size="4" name="MASK[109]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+440" size="4" name="MASK[110]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+444" size="4" name="MASK[111]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+448" size="4" name="MASK[112]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+452" size="4" name="MASK[113]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+456" size="4" name="MASK[114]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+460" size="4" name="MASK[115]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+464" size="4" name="MASK[116]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+468" size="4" name="MASK[117]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+472" size="4" name="MASK[118]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+476" size="4" name="MASK[119]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+480" size="4" name="MASK[120]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+484" size="4" name="MASK[121]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+488" size="4" name="MASK[122]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+492" size="4" name="MASK[123]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+496" size="4" name="MASK[124]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+500" size="4" name="MASK[125]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+504" size="4" name="MASK[126]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+508" size="4" name="MASK[127]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+512" size="4" name="MASK[128]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+516" size="4" name="MASK[129]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+520" size="4" name="MASK[130]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+524" size="4" name="MASK[131]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+528" size="4" name="MASK[132]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+532" size="4" name="MASK[133]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+536" size="4" name="MASK[134]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+540" size="4" name="MASK[135]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+544" size="4" name="MASK[136]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+548" size="4" name="MASK[137]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+552" size="4" name="MASK[138]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+556" size="4" name="MASK[139]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+560" size="4" name="MASK[140]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+564" size="4" name="MASK[141]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+568" size="4" name="MASK[142]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+572" size="4" name="MASK[143]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+576" size="4" name="MASK[144]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+580" size="4" name="MASK[145]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+584" size="4" name="MASK[146]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+588" size="4" name="MASK[147]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+592" size="4" name="MASK[148]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+596" size="4" name="MASK[149]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+600" size="4" name="MASK[150]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+604" size="4" name="MASK[151]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+608" size="4" name="MASK[152]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+612" size="4" name="MASK[153]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+616" size="4" name="MASK[154]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+620" size="4" name="MASK[155]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+624" size="4" name="MASK[156]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+628" size="4" name="MASK[157]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+632" size="4" name="MASK[158]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+636" size="4" name="MASK[159]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+640" size="4" name="MASK[160]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+644" size="4" name="MASK[161]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+648" size="4" name="MASK[162]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+652" size="4" name="MASK[163]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+656" size="4" name="MASK[164]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+660" size="4" name="MASK[165]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+664" size="4" name="MASK[166]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+668" size="4" name="MASK[167]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+672" size="4" name="MASK[168]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+676" size="4" name="MASK[169]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+680" size="4" name="MASK[170]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+684" size="4" name="MASK[171]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+688" size="4" name="MASK[172]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+692" size="4" name="MASK[173]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+696" size="4" name="MASK[174]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+700" size="4" name="MASK[175]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+704" size="4" name="MASK[176]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+708" size="4" name="MASK[177]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+712" size="4" name="MASK[178]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+716" size="4" name="MASK[179]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+720" size="4" name="MASK[180]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+724" size="4" name="MASK[181]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+728" size="4" name="MASK[182]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+732" size="4" name="MASK[183]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+736" size="4" name="MASK[184]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+740" size="4" name="MASK[185]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+744" size="4" name="MASK[186]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+748" size="4" name="MASK[187]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+752" size="4" name="MASK[188]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+756" size="4" name="MASK[189]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+760" size="4" name="MASK[190]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+764" size="4" name="MASK[191]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+768" size="4" name="MASK[192]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+772" size="4" name="MASK[193]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+776" size="4" name="MASK[194]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+780" size="4" name="MASK[195]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+784" size="4" name="MASK[196]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+788" size="4" name="MASK[197]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+792" size="4" name="MASK[198]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+796" size="4" name="MASK[199]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+800" size="4" name="MASK[200]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+804" size="4" name="MASK[201]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+808" size="4" name="MASK[202]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+812" size="4" name="MASK[203]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+816" size="4" name="MASK[204]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+820" size="4" name="MASK[205]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+824" size="4" name="MASK[206]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+828" size="4" name="MASK[207]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+832" size="4" name="MASK[208]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+836" size="4" name="MASK[209]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+840" size="4" name="MASK[210]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+844" size="4" name="MASK[211]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+848" size="4" name="MASK[212]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+852" size="4" name="MASK[213]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+856" size="4" name="MASK[214]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+860" size="4" name="MASK[215]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+864" size="4" name="MASK[216]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+868" size="4" name="MASK[217]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+872" size="4" name="MASK[218]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+876" size="4" name="MASK[219]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+880" size="4" name="MASK[220]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+884" size="4" name="MASK[221]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+888" size="4" name="MASK[222]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+892" size="4" name="MASK[223]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+896" size="4" name="MASK[224]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+900" size="4" name="MASK[225]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+904" size="4" name="MASK[226]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+908" size="4" name="MASK[227]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+912" size="4" name="MASK[228]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+916" size="4" name="MASK[229]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+920" size="4" name="MASK[230]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+924" size="4" name="MASK[231]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+928" size="4" name="MASK[232]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+932" size="4" name="MASK[233]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+936" size="4" name="MASK[234]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+940" size="4" name="MASK[235]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+944" size="4" name="MASK[236]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+948" size="4" name="MASK[237]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+952" size="4" name="MASK[238]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+956" size="4" name="MASK[239]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+960" size="4" name="MASK[240]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+964" size="4" name="MASK[241]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+968" size="4" name="MASK[242]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+972" size="4" name="MASK[243]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+976" size="4" name="MASK[244]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+980" size="4" name="MASK[245]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+984" size="4" name="MASK[246]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+988" size="4" name="MASK[247]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+992" size="4" name="MASK[248]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+996" size="4" name="MASK[249]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1000" size="4" name="MASK[250]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1004" size="4" name="MASK[251]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1008" size="4" name="MASK[252]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1012" size="4" name="MASK[253]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1016" size="4" name="MASK[254]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1020" size="4" name="MASK[255]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1024" size="4" name="MASK[256]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1028" size="4" name="MASK[257]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1032" size="4" name="MASK[258]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1036" size="4" name="MASK[259]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1040" size="4" name="MASK[260]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1044" size="4" name="MASK[261]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1048" size="4" name="MASK[262]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1052" size="4" name="MASK[263]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1056" size="4" name="MASK[264]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1060" size="4" name="MASK[265]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1064" size="4" name="MASK[266]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1068" size="4" name="MASK[267]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1072" size="4" name="MASK[268]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1076" size="4" name="MASK[269]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1080" size="4" name="MASK[270]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1084" size="4" name="MASK[271]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1088" size="4" name="MASK[272]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1092" size="4" name="MASK[273]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1096" size="4" name="MASK[274]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1100" size="4" name="MASK[275]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1104" size="4" name="MASK[276]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1108" size="4" name="MASK[277]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1112" size="4" name="MASK[278]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1116" size="4" name="MASK[279]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1120" size="4" name="MASK[280]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1124" size="4" name="MASK[281]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1128" size="4" name="MASK[282]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1132" size="4" name="MASK[283]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1136" size="4" name="MASK[284]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1140" size="4" name="MASK[285]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1144" size="4" name="MASK[286]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1148" size="4" name="MASK[287]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1152" size="4" name="MASK[288]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1156" size="4" name="MASK[289]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1160" size="4" name="MASK[290]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1164" size="4" name="MASK[291]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1168" size="4" name="MASK[292]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1172" size="4" name="MASK[293]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1176" size="4" name="MASK[294]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1180" size="4" name="MASK[295]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1184" size="4" name="MASK[296]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1188" size="4" name="MASK[297]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1192" size="4" name="MASK[298]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1196" size="4" name="MASK[299]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1200" size="4" name="MASK[300]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1204" size="4" name="MASK[301]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1208" size="4" name="MASK[302]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1212" size="4" name="MASK[303]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1216" size="4" name="MASK[304]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1220" size="4" name="MASK[305]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1224" size="4" name="MASK[306]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1228" size="4" name="MASK[307]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1232" size="4" name="MASK[308]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1236" size="4" name="MASK[309]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1240" size="4" name="MASK[310]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1244" size="4" name="MASK[311]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1248" size="4" name="MASK[312]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1252" size="4" name="MASK[313]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1256" size="4" name="MASK[314]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1260" size="4" name="MASK[315]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1264" size="4" name="MASK[316]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1268" size="4" name="MASK[317]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1272" size="4" name="MASK[318]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1276" size="4" name="MASK[319]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1280" size="4" name="MASK[320]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1284" size="4" name="MASK[321]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1288" size="4" name="MASK[322]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1292" size="4" name="MASK[323]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1296" size="4" name="MASK[324]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1300" size="4" name="MASK[325]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1304" size="4" name="MASK[326]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1308" size="4" name="MASK[327]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1312" size="4" name="MASK[328]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1316" size="4" name="MASK[329]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1320" size="4" name="MASK[330]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1324" size="4" name="MASK[331]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1328" size="4" name="MASK[332]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1332" size="4" name="MASK[333]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1336" size="4" name="MASK[334]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1340" size="4" name="MASK[335]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1344" size="4" name="MASK[336]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1348" size="4" name="MASK[337]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1352" size="4" name="MASK[338]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1356" size="4" name="MASK[339]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1360" size="4" name="MASK[340]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1364" size="4" name="MASK[341]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1368" size="4" name="MASK[342]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1372" size="4" name="MASK[343]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1376" size="4" name="MASK[344]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1380" size="4" name="MASK[345]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1384" size="4" name="MASK[346]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1388" size="4" name="MASK[347]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1392" size="4" name="MASK[348]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1396" size="4" name="MASK[349]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1400" size="4" name="MASK[350]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1404" size="4" name="MASK[351]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1408" size="4" name="MASK[352]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1412" size="4" name="MASK[353]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1416" size="4" name="MASK[354]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1420" size="4" name="MASK[355]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1424" size="4" name="MASK[356]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1428" size="4" name="MASK[357]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1432" size="4" name="MASK[358]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1436" size="4" name="MASK[359]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1440" size="4" name="MASK[360]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1444" size="4" name="MASK[361]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1448" size="4" name="MASK[362]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1452" size="4" name="MASK[363]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1456" size="4" name="MASK[364]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1460" size="4" name="MASK[365]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1464" size="4" name="MASK[366]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1468" size="4" name="MASK[367]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1472" size="4" name="MASK[368]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1476" size="4" name="MASK[369]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1480" size="4" name="MASK[370]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1484" size="4" name="MASK[371]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1488" size="4" name="MASK[372]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1492" size="4" name="MASK[373]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1496" size="4" name="MASK[374]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1500" size="4" name="MASK[375]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1504" size="4" name="MASK[376]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1508" size="4" name="MASK[377]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1512" size="4" name="MASK[378]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1516" size="4" name="MASK[379]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1520" size="4" name="MASK[380]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1524" size="4" name="MASK[381]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1528" size="4" name="MASK[382]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1532" size="4" name="MASK[383]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1536" size="4" name="MASK[384]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1540" size="4" name="MASK[385]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1544" size="4" name="MASK[386]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1548" size="4" name="MASK[387]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1552" size="4" name="MASK[388]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1556" size="4" name="MASK[389]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1560" size="4" name="MASK[390]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1564" size="4" name="MASK[391]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1568" size="4" name="MASK[392]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1572" size="4" name="MASK[393]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1576" size="4" name="MASK[394]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1580" size="4" name="MASK[395]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1584" size="4" name="MASK[396]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1588" size="4" name="MASK[397]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1592" size="4" name="MASK[398]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1596" size="4" name="MASK[399]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1600" size="4" name="MASK[400]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1604" size="4" name="MASK[401]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1608" size="4" name="MASK[402]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1612" size="4" name="MASK[403]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1616" size="4" name="MASK[404]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1620" size="4" name="MASK[405]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1624" size="4" name="MASK[406]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1628" size="4" name="MASK[407]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1632" size="4" name="MASK[408]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1636" size="4" name="MASK[409]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1640" size="4" name="MASK[410]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1644" size="4" name="MASK[411]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1648" size="4" name="MASK[412]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1652" size="4" name="MASK[413]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1656" size="4" name="MASK[414]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1660" size="4" name="MASK[415]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1664" size="4" name="MASK[416]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1668" size="4" name="MASK[417]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1672" size="4" name="MASK[418]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1676" size="4" name="MASK[419]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1680" size="4" name="MASK[420]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1684" size="4" name="MASK[421]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1688" size="4" name="MASK[422]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1692" size="4" name="MASK[423]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1696" size="4" name="MASK[424]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1700" size="4" name="MASK[425]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1704" size="4" name="MASK[426]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1708" size="4" name="MASK[427]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1712" size="4" name="MASK[428]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1716" size="4" name="MASK[429]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1720" size="4" name="MASK[430]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1724" size="4" name="MASK[431]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1728" size="4" name="MASK[432]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1732" size="4" name="MASK[433]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1736" size="4" name="MASK[434]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1740" size="4" name="MASK[435]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1744" size="4" name="MASK[436]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1748" size="4" name="MASK[437]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1752" size="4" name="MASK[438]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1756" size="4" name="MASK[439]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1760" size="4" name="MASK[440]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1764" size="4" name="MASK[441]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1768" size="4" name="MASK[442]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1772" size="4" name="MASK[443]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1776" size="4" name="MASK[444]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1780" size="4" name="MASK[445]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1784" size="4" name="MASK[446]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1788" size="4" name="MASK[447]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1792" size="4" name="MASK[448]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1796" size="4" name="MASK[449]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1800" size="4" name="MASK[450]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1804" size="4" name="MASK[451]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1808" size="4" name="MASK[452]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1812" size="4" name="MASK[453]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1816" size="4" name="MASK[454]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1820" size="4" name="MASK[455]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1824" size="4" name="MASK[456]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1828" size="4" name="MASK[457]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1832" size="4" name="MASK[458]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1836" size="4" name="MASK[459]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1840" size="4" name="MASK[460]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1844" size="4" name="MASK[461]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1848" size="4" name="MASK[462]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1852" size="4" name="MASK[463]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1856" size="4" name="MASK[464]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1860" size="4" name="MASK[465]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1864" size="4" name="MASK[466]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1868" size="4" name="MASK[467]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1872" size="4" name="MASK[468]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1876" size="4" name="MASK[469]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1880" size="4" name="MASK[470]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1884" size="4" name="MASK[471]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1888" size="4" name="MASK[472]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1892" size="4" name="MASK[473]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1896" size="4" name="MASK[474]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1900" size="4" name="MASK[475]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1904" size="4" name="MASK[476]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1908" size="4" name="MASK[477]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1912" size="4" name="MASK[478]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1916" size="4" name="MASK[479]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1920" size="4" name="MASK[480]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1924" size="4" name="MASK[481]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1928" size="4" name="MASK[482]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1932" size="4" name="MASK[483]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1936" size="4" name="MASK[484]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1940" size="4" name="MASK[485]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1944" size="4" name="MASK[486]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1948" size="4" name="MASK[487]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1952" size="4" name="MASK[488]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1956" size="4" name="MASK[489]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1960" size="4" name="MASK[490]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1964" size="4" name="MASK[491]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1968" size="4" name="MASK[492]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1972" size="4" name="MASK[493]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1976" size="4" name="MASK[494]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1980" size="4" name="MASK[495]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1984" size="4" name="MASK[496]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1988" size="4" name="MASK[497]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1992" size="4" name="MASK[498]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1996" size="4" name="MASK[499]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+2000" size="4" name="MASK[500]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+2004" size="4" name="MASK[501]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+2008" size="4" name="MASK[502]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+2012" size="4" name="MASK[503]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+2016" size="4" name="MASK[504]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+2020" size="4" name="MASK[505]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+2024" size="4" name="MASK[506]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+2028" size="4" name="MASK[507]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+2032" size="4" name="MASK[508]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+2036" size="4" name="MASK[509]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+2040" size="4" name="MASK[510]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+2044" size="4" name="MASK[511]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + </RegisterGroup> + <RegisterGroup name="CANAF" start="0x4003C000" description=" CAN controller acceptance filter "> + <Register start="+0x000" size="4" name="AFMR" access="Read/Write" description="Acceptance Filter Register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="ACCOFF" description="if AccBP is 0, the Acceptance Filter is not operational. All Rx messages on all CAN buses are ignored." /> + <BitField start="1" size="1" name="ACCBP" description="All Rx messages are accepted on enabled CAN controllers. Software must set this bit before modifying the contents of any of the registers described below, and before modifying the contents of Lookup Table RAM in any way other than setting or clearing Disable bits in Standard Identifier entries. When both this bit and AccOff are 0, the Acceptance filter operates to screen received CAN Identifiers." /> + <BitField start="2" size="1" name="EFCAN" description="FullCAN mode"> + <Enum name="SOFTWARE_MUST_READ_A" start="0" description="Software must read all messages for all enabled IDs on all enabled CAN buses, from the receiving CAN controllers." /> + <Enum name="THE_ACCEPTANCE_FILTE" start="1" description="The Acceptance Filter itself will take care of receiving and storing messages for selected Standard ID values on selected CAN buses. See Section 21.16 FullCAN mode on page 576." /> + </BitField> + <BitField start="3" size="29" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x004" size="4" name="SFF_SA" access="Read/Write" description="Standard Frame Individual Start Address Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="2" size="9" name="SFF_SA" description="The start address of the table of individual Standard Identifiers in AF Lookup RAM. If the table is empty, write the same value in this register and the SFF_GRP_sa register described below. For compatibility with possible future devices, write zeroes in bits 31:11 and 1:0 of this register. If the eFCAN bit in the AFMR is 1, this value also indicates the size of the table of Standard IDs which the Acceptance Filter will search and (if found) automatically store received messages in Acceptance Filter RAM." /> + <BitField start="11" size="21" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x008" size="4" name="SFF_GRP_SA" access="Read/Write" description="Standard Frame Group Start Address Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="2" size="10" name="SFF_GRP_SA" description="The start address of the table of grouped Standard Identifiers in AF Lookup RAM. If the table is empty, write the same value in this register and the EFF_sa register described below. The largest value that should be written to this register is 0x800, when only the Standard Individual table is used, and the last word (address 0x7FC) in AF Lookup Table RAM is used. For compatibility with possible future devices, please write zeroes in bits 31:12 and 1:0 of this register." /> + <BitField start="12" size="20" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x00C" size="4" name="EFF_SA" access="Read/Write" description="Extended Frame Start Address Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="2" size="9" name="EFF_SA" description="The start address of the table of individual Extended Identifiers in AF Lookup RAM. If the table is empty, write the same value in this register and the EFF_GRP_sa register described below. The largest value that should be written to this register is 0x800, when both Extended Tables are empty and the last word (address 0x7FC) in AF Lookup Table RAM is used. For compatibility with possible future devices, please write zeroes in bits 31:11 and 1:0 of this register." /> + <BitField start="11" size="21" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x010" size="4" name="EFF_GRP_SA" access="Read/Write" description="Extended Frame Group Start Address Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="2" size="10" name="EFF_GRP_SA" description="The start address of the table of grouped Extended Identifiers in AF Lookup RAM. If the table is empty, write the same value in this register and the ENDofTable register described below. The largest value that should be written to this register is 0x800, when this table is empty and the last word (address 0x7FC) in AF Lookup Table RAM is used. For compatibility with possible future devices, please write zeroes in bits 31:12 and 1:0 of this register." /> + <BitField start="12" size="20" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x014" size="4" name="ENDOFTABLE" access="Read/Write" description="End of AF Tables register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="2" size="10" name="ENDOFTABLE" description="The address above the last active address in the last active AF table. For compatibility with possible future devices, please write zeroes in bits 31:12 and 1:0 of this register. If the eFCAN bit in the AFMR is 0, the largest value that should be written to this register is 0x800, which allows the last word (address 0x7FC) in AF Lookup Table RAM to be used. If the eFCAN bit in the AFMR is 1, this value marks the start of the area of Acceptance Filter RAM, into which the Acceptance Filter will automatically receive messages for selected IDs on selected CAN buses. In this case, the maximum value that should be written to this register is 0x800 minus 6 times the value in SFF_sa. This allows 12 bytes of message storage between this address and the end of Acceptance Filter RAM, for each Standard ID that is specified between the start of Acceptance Filter RAM, and the next active AF table." /> + <BitField start="12" size="20" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x018" size="4" name="LUTERRAD" access="ReadOnly" description="LUT Error Address register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="2" size="9" name="LUTERRAD" description="It the LUT Error bit (below) is 1, this read-only field contains the address in AF Lookup Table RAM, at which the Acceptance Filter encountered an error in the content of the tables." /> + <BitField start="11" size="21" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x01C" size="4" name="LUTERR" access="ReadOnly" description="LUT Error Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="LUTERR" description="This read-only bit is set to 1 if the Acceptance Filter encounters an error in the content of the tables in AF RAM. It is cleared when software reads the LUTerrAd register. This condition is ORed with the other CAN interrupts from the CAN controllers, to produce the request that is connected to the NVIC." /> + <BitField start="1" size="31" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x020" size="4" name="FCANIE" access="Read/Write" description="FullCAN interrupt enable register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="FCANIE" description="Global FullCAN Interrupt Enable. When 1, this interrupt is enabled." /> + <BitField start="1" size="31" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x024" size="4" name="FCANIC0" access="Read/Write" description="FullCAN interrupt and capture register0" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="INTPND" description="FullCan Interrupt Pending 0 = FullCan Interrupt Pending bit 0. 1 = FullCan Interrupt Pending bit 1. ... 31 = FullCan Interrupt Pending bit 31." /> + </Register> + <Register start="+0x028" size="4" name="FCANIC1" access="Read/Write" description="FullCAN interrupt and capture register1" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="IntPnd32" description="FullCan Interrupt Pending bit 32. 0 = FullCan Interrupt Pending bit 32. 1 = FullCan Interrupt Pending bit 33. ... 31 = FullCan Interrupt Pending bit 63." /> + </Register> + </RegisterGroup> + <RegisterGroup name="CCAN" start="0x40040000" description="Central CAN controller "> + <Register start="+0x000" size="4" name="TXSR" access="ReadOnly" description="CAN Central Transmit Status Register" reset_value="0x00030300" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="TS1" description="When 1, the CAN controller 1 is sending a message (same as TS in the CAN1GSR)." /> + <BitField start="1" size="1" name="TS2" description="When 1, the CAN controller 2 is sending a message (same as TS in the CAN2GSR)" /> + <BitField start="2" size="6" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." /> + <BitField start="8" size="1" name="TBS1" description="When 1, all 3 Tx Buffers of the CAN1 controller are available to the CPU (same as TBS in CAN1GSR)." /> + <BitField start="9" size="1" name="TBS2" description="When 1, all 3 Tx Buffers of the CAN2 controller are available to the CPU (same as TBS in CAN2GSR)." /> + <BitField start="10" size="6" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." /> + <BitField start="16" size="1" name="TCS1" description="When 1, all requested transmissions have been completed successfully by the CAN1 controller (same as TCS in CAN1GSR)." /> + <BitField start="17" size="1" name="TCS2" description="When 1, all requested transmissions have been completed successfully by the CAN2 controller (same as TCS in CAN2GSR)." /> + <BitField start="18" size="14" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x004" size="4" name="RXSR" access="ReadOnly" description="CAN Central Receive Status Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RS1" description="When 1, CAN1 is receiving a message (same as RS in CAN1GSR)." /> + <BitField start="1" size="1" name="RS2" description="When 1, CAN2 is receiving a message (same as RS in CAN2GSR)." /> + <BitField start="2" size="6" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." /> + <BitField start="8" size="1" name="RB1" description="When 1, a received message is available in the CAN1 controller (same as RBS in CAN1GSR)." /> + <BitField start="9" size="1" name="RB2" description="When 1, a received message is available in the CAN2 controller (same as RBS in CAN2GSR)." /> + <BitField start="10" size="6" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." /> + <BitField start="16" size="1" name="DOS1" description="When 1, a message was lost because the preceding message to CAN1 controller was not read out quickly enough (same as DOS in CAN1GSR)." /> + <BitField start="17" size="1" name="DOS2" description="When 1, a message was lost because the preceding message to CAN2 controller was not read out quickly enough (same as DOS in CAN2GSR)." /> + <BitField start="18" size="14" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x008" size="4" name="MSR" access="ReadOnly" description="CAN Central Miscellaneous Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="E1" description="When 1, one or both of the CAN1 Tx and Rx Error Counters has reached the limit set in the CAN1EWL register (same as ES in CAN1GSR)" /> + <BitField start="1" size="1" name="E2" description="When 1, one or both of the CAN2 Tx and Rx Error Counters has reached the limit set in the CAN2EWL register (same as ES in CAN2GSR)" /> + <BitField start="2" size="6" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." /> + <BitField start="8" size="1" name="BS1" description="When 1, the CAN1 controller is currently involved in bus activities (same as BS in CAN1GSR)." /> + <BitField start="9" size="1" name="BS2" description="When 1, the CAN2 controller is currently involved in bus activities (same as BS in CAN2GSR)." /> + <BitField start="10" size="22" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." /> + </Register> + </RegisterGroup> + <RegisterGroup name="CAN1" start="0x40044000" description="CAN1 controller "> + <Register start="+0x000" size="4" name="MOD" access="Read/Write" description="Controls the operating mode of the CAN Controller." reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="RM" description="Reset Mode."> + <Enum name="NORMAL_THE_CAN_CONTR" start="0" description="Normal.The CAN Controller is in the Operating Mode, and certain registers can not be written." /> + <Enum name="RESET_CAN_OPERATION" start="1" description="Reset. CAN operation is disabled, writable registers can be written and the current transmission/reception of a message is aborted." /> + </BitField> + <BitField start="1" size="1" name="LOM" description="Listen Only Mode."> + <Enum name="NORMAL_THE_CAN_CONT" start="0" description="Normal. The CAN controller acknowledges a successfully received message on the CAN bus. The error counters are stopped at the current value." /> + <Enum name="LISTEN_ONLY_THE_CON" start="1" description="Listen only. The controller gives no acknowledgment, even if a message is successfully received. Messages cannot be sent, and the controller operates in error passive mode. This mode is intended for software bit rate detection and hot plugging." /> + </BitField> + <BitField start="2" size="1" name="STM" description="Self Test Mode."> + <Enum name="NORMAL_A_TRANSMITTE" start="0" description="Normal. A transmitted message must be acknowledged to be considered successful." /> + <Enum name="SELF_TEST_THE_CONTR" start="1" description="Self test. The controller will consider a Tx message successful even if there is no acknowledgment received. In this mode a full node test is possible without any other active node on the bus using the SRR bit in CANxCMR." /> + </BitField> + <BitField start="3" size="1" name="TPM" description="Transmit Priority Mode."> + <Enum name="CAN_ID_THE_TRANSMIT" start="0" description="CAN ID. The transmit priority for 3 Transmit Buffers depends on the CAN Identifier." /> + <Enum name="LOCAL_PRIORITY_THE_" start="1" description="Local priority. The transmit priority for 3 Transmit Buffers depends on the contents of the Tx Priority register within the Transmit Buffer." /> + </BitField> + <BitField start="4" size="1" name="SM" description="Sleep Mode."> + <Enum name="WAKE_UP_NORMAL_OPER" start="0" description="Wake-up. Normal operation." /> + <Enum name="SLEEP_THE_CAN_CONTR" start="1" description="Sleep. The CAN controller enters Sleep Mode if no CAN interrupt is pending and there is no bus activity. See the Sleep Mode description Section 21.8.2 on page 565." /> + </BitField> + <BitField start="5" size="1" name="RPM" description="Receive Polarity Mode."> + <Enum name="LOW_ACTIVE_RD_INPUT" start="0" description="Low active. RD input is active Low (dominant bit = 0)." /> + <Enum name="HIGH_ACTIVE_RD_INPU" start="1" description="High active. RD input is active High (dominant bit = 1) -- reverse polarity." /> + </BitField> + <BitField start="6" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="7" size="1" name="TM" description="Test Mode."> + <Enum name="DISABLED_NORMAL_OPE" start="0" description="Disabled. Normal operation." /> + <Enum name="ENABLED_THE_TD_PIN_" start="1" description="Enabled. The TD pin will reflect the bit, detected on RD pin, with the next positive edge of the system clock." /> + </BitField> + <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x004" size="4" name="CMR" access="WriteOnly" description="Command bits that affect the state of the CAN Controller" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="TR" description="Transmission Request."> + <Enum name="ABSENT_NO_TRANSMISSI" start="0" description="Absent.No transmission request." /> + <Enum name="PRESENT_THE_MESSAGE" start="1" description="Present. The message, previously written to the CANxTFI, CANxTID, and optionally the CANxTDA and CANxTDB registers, is queued for transmission from the selected Transmit Buffer. If at two or all three of STB1, STB2 and STB3 bits are selected when TR=1 is written, Transmit Buffer will be selected based on the chosen priority scheme (for details see Section 21.5.3 Transmit Buffers (TXB))" /> + </BitField> + <BitField start="1" size="1" name="AT" description="Abort Transmission."> + <Enum name="NO_ACTION_DO_NOT_AB" start="0" description="No action. Do not abort the transmission." /> + <Enum name="PRESENT_IF_NOT_ALRE" start="1" description="Present. if not already in progress, a pending Transmission Request for the selected Transmit Buffer is cancelled." /> + </BitField> + <BitField start="2" size="1" name="RRB" description="Release Receive Buffer."> + <Enum name="NO_ACTION_DO_NOT_RE" start="0" description="No action. Do not release the receive buffer." /> + <Enum name="RELEASED_THE_INFORM" start="1" description="Released. The information in the Receive Buffer (consisting of CANxRFS, CANxRID, and if applicable the CANxRDA and CANxRDB registers) is released, and becomes eligible for replacement by the next received frame. If the next received frame is not available, writing this command clears the RBS bit in the Status Register(s)." /> + </BitField> + <BitField start="3" size="1" name="CDO" description="Clear Data Overrun."> + <Enum name="NO_ACTION_DO_NOT_CL" start="0" description="No action. Do not clear the data overrun bit." /> + <Enum name="CLEAR_THE_DATA_OVER" start="1" description="Clear. The Data Overrun bit in Status Register(s) is cleared." /> + </BitField> + <BitField start="4" size="1" name="SRR" description="Self Reception Request."> + <Enum name="ABSENT_NO_SELF_RECE" start="0" description="Absent. No self reception request." /> + <Enum name="PRESENT_THE_MESSAGE" start="1" description="Present. The message, previously written to the CANxTFS, CANxTID, and optionally the CANxTDA and CANxTDB registers, is queued for transmission from the selected Transmit Buffer and received simultaneously. This differs from the TR bit above in that the receiver is not disabled during the transmission, so that it receives the message if its Identifier is recognized by the Acceptance Filter." /> + </BitField> + <BitField start="5" size="1" name="STB1" description="Select Tx Buffer 1."> + <Enum name="NOT_SELECTED_TX_BUF" start="0" description="Not selected. Tx Buffer 1 is not selected for transmission." /> + <Enum name="SELECTED_TX_BUFFER_" start="1" description="Selected. Tx Buffer 1 is selected for transmission." /> + </BitField> + <BitField start="6" size="1" name="STB2" description="Select Tx Buffer 2."> + <Enum name="NOT_SELECTED_TX_BUF" start="0" description="Not selected. Tx Buffer 2 is not selected for transmission." /> + <Enum name="SELECTED_TX_BUFFER_" start="1" description="Selected. Tx Buffer 2 is selected for transmission." /> + </BitField> + <BitField start="7" size="1" name="STB3" description="Select Tx Buffer 3."> + <Enum name="NOT_SELECTED_TX_BUF" start="0" description="Not selected. Tx Buffer 3 is not selected for transmission." /> + <Enum name="SELECTED_TX_BUFFER_" start="1" description="Selected. Tx Buffer 3 is selected for transmission." /> + </BitField> + <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x008" size="4" name="GSR" access="ReadOnly" description="Global Controller Status and Error Counters. The error counters can only be written when RM in CANMOD is 1." reset_value="0x3C" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RBS" description="Receive Buffer Status. After reading all messages and releasing their memory space with the command 'Release Receive Buffer,' this bit is cleared."> + <Enum name="EMPTY_NO_MESSAGE_IS" start="0" description="Empty. No message is available." /> + <Enum name="FULL_AT_LEAST_ONE_C" start="1" description="Full. At least one complete message is received by the Double Receive Buffer and available in the CANxRFS, CANxRID, and if applicable the CANxRDA and CANxRDB registers. This bit is cleared by the Release Receive Buffer command in CANxCMR, if no subsequent received message is available." /> + </BitField> + <BitField start="1" size="1" name="DOS" description="Data Overrun Status. If there is not enough space to store the message within the Receive Buffer, that message is dropped and the Data Overrun condition is signalled to the CPU in the moment this message becomes valid. If this message is not completed successfully (e.g. because of an error), no overrun condition is signalled."> + <Enum name="ABSENT_NO_DATA_OVER" start="0" description="Absent. No data overrun has occurred since the last Clear Data Overrun command was given/written to CANxCMR (or since Reset)." /> + <Enum name="OVERRUN_A_MESSAGE_W" start="1" description="Overrun. A message was lost because the preceding message to this CAN controller was not read and released quickly enough (there was not enough space for a new message in the Double Receive Buffer)." /> + </BitField> + <BitField start="2" size="1" name="TBS" description="Transmit Buffer Status."> + <Enum name="LOCKED_AT_LEAST_ONE" start="0" description="Locked. At least one of the Transmit Buffers is not available for the CPU, i.e. at least one previously queued message for this CAN controller has not yet been sent, and therefore software should not write to the CANxTFI, CANxTID, CANxTDA, nor CANxTDB registers of that (those) Tx buffer(s)." /> + <Enum name="RELEASED_ALL_THREE_" start="1" description="Released. All three Transmit Buffers are available for the CPU. No transmit message is pending for this CAN controller (in any of the 3 Tx buffers), and software may write to any of the CANxTFI, CANxTID, CANxTDA, and CANxTDB registers." /> + </BitField> + <BitField start="3" size="1" name="TCS" description="Transmit Complete Status. The Transmission Complete Status bit is set '0' (incomplete) whenever the Transmission Request bit or the Self Reception Request bit is set '1' at least for one of the three Transmit Buffers. The Transmission Complete Status bit will remain '0' until all messages are transmitted successfully."> + <Enum name="INCOMPLETE_AT_LEAST" start="0" description="Incomplete. At least one requested transmission has not been successfully completed yet." /> + <Enum name="COMPLETE_ALL_REQUES" start="1" description="Complete. All requested transmission(s) has (have) been successfully completed." /> + </BitField> + <BitField start="4" size="1" name="RS" description="Receive Status. If both the Receive Status and the Transmit Status bits are '0' (idle), the CAN-Bus is idle. If both bits are set, the controller is waiting to become idle again. After hardware reset 11 consecutive recessive bits have to be detected until idle status is reached. After Bus-off this will take 128 times of 11 consecutive recessive bits."> + <Enum name="IDLE_THE_CAN_CONTRO" start="0" description="Idle. The CAN controller is idle." /> + <Enum name="RECEIVE_THE_CAN_CON" start="1" description="Receive. The CAN controller is receiving a message." /> + </BitField> + <BitField start="5" size="1" name="TS" description="Transmit Status. If both the Receive Status and the Transmit Status bits are '0' (idle), the CAN-Bus is idle. If both bits are set, the controller is waiting to become idle again. After hardware reset 11 consecutive recessive bits have to be detected until idle status is reached. After Bus-off this will take 128 times of 11 consecutive recessive bits."> + <Enum name="IDLE_THE_CAN_CONTRO" start="0" description="Idle. The CAN controller is idle." /> + <Enum name="TRANSMIT_THE_CAN_CO" start="1" description="Transmit. The CAN controller is sending a message." /> + </BitField> + <BitField start="6" size="1" name="ES" description="Error Status. Errors detected during reception or transmission will effect the error counters according to the CAN specification. The Error Status bit is set when at least one of the error counters has reached or exceeded the Error Warning Limit. An Error Warning Interrupt is generated, if enabled. The default value of the Error Warning Limit after hardware reset is 96 decimal, see also Section 21.7.7 CAN Error Warning Limit register (CAN1EWL - 0x4004 4018, CAN2EWL - 0x4004 8018)."> + <Enum name="OK_BOTH_ERROR_COUNT" start="0" description="OK. Both error counters are below the Error Warning Limit." /> + <Enum name="ERROR_ONE_OR_BOTH_O" start="1" description="Error. One or both of the Transmit and Receive Error Counters has reached the limit set in the Error Warning Limit register." /> + </BitField> + <BitField start="7" size="1" name="BS" description="Bus Status. Mode bit '1' (present) and an Error Warning Interrupt is generated, if enabled. Afterwards the Transmit Error Counter is set to '127', and the Receive Error Counter is cleared. It will stay in this mode until the CPU clears the Reset Mode bit. Once this is completed the CAN Controller will wait the minimum protocol-defined time (128 occurrences of the Bus-Free signal) counting down the Transmit Error Counter. After that, the Bus Status bit is cleared (Bus-On), the Error Status bit is set '0' (ok), the Error Counters are reset, and an Error Warning Interrupt is generated, if enabled. Reading the TX Error Counter during this time gives information about the status of the Bus-Off recovery."> + <Enum name="BUS_ON_THE_CAN_CONT" start="0" description="Bus-on. The CAN Controller is involved in bus activities" /> + <Enum name="BUS_OFF_THE_CAN_CON" start="1" description="Bus-off. The CAN controller is currently not involved/prohibited from bus activity because the Transmit Error Counter reached its limiting value of 255." /> + </BitField> + <BitField start="8" size="8" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="16" size="8" name="RXERR" description="The current value of the Rx Error Counter (an 8-bit value)." /> + <BitField start="24" size="8" name="TXERR" description="The current value of the Tx Error Counter (an 8-bit value)." /> + </Register> + <Register start="+0x00C" size="4" name="ICR" access="ReadOnly" description="Interrupt status, Arbitration Lost Capture, Error Code Capture" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RI" description="Receive Interrupt. This bit is set whenever the RBS bit in CANxSR and the RIE bit in CANxIER are both 1, indicating that a new message was received and stored in the Receive Buffer. The Receive Interrupt Bit is not cleared upon a read access to the Interrupt Register. Giving the Command Release Receive Buffer will clear RI temporarily. If there is another message available within the Receive Buffer after the release command, RI is set again. Otherwise RI remains cleared."> + <Enum name="RESET" start="0" description="Reset" /> + <Enum name="SET" start="1" description="Set" /> + </BitField> + <BitField start="1" size="1" name="TI1" description="Transmit Interrupt 1. This bit is set when the TBS1 bit in CANxSR goes from 0 to 1 (whenever a message out of TXB1 was successfully transmitted or aborted), indicating that Transmit buffer 1 is available, and the TIE1 bit in CANxIER is 1."> + <Enum name="RESET" start="0" description="Reset" /> + <Enum name="SET" start="1" description="Set" /> + </BitField> + <BitField start="2" size="1" name="EI" description="Error Warning Interrupt. This bit is set on every change (set or clear) of either the Error Status or Bus Status bit in CANxSR and the EIE bit bit is set within the Interrupt Enable Register at the time of the change."> + <Enum name="RESET" start="0" description="Reset" /> + <Enum name="SET" start="1" description="Set" /> + </BitField> + <BitField start="3" size="1" name="DOI" description="Data Overrun Interrupt. This bit is set when the DOS bit in CANxSR goes from 0 to 1 and the DOIE bit in CANxIER is 1."> + <Enum name="RESET" start="0" description="Reset" /> + <Enum name="SET" start="1" description="Set" /> + </BitField> + <BitField start="4" size="1" name="WUI" description="Wake-Up Interrupt. This bit is set if the CAN controller is sleeping and bus activity is detected and the WUIE bit in CANxIER is 1. A Wake-Up Interrupt is also generated if the CPU tries to set the Sleep bit while the CAN controller is involved in bus activities or a CAN Interrupt is pending. The WUI flag can also get asserted when the according enable bit WUIE is not set. In this case a Wake-Up Interrupt does not get asserted."> + <Enum name="RESET" start="0" description="Reset" /> + <Enum name="SET" start="1" description="Set" /> + </BitField> + <BitField start="5" size="1" name="EPI" description="Error Passive Interrupt. This bit is set if the EPIE bit in CANxIER is 1, and the CAN controller switches between Error Passive and Error Active mode in either direction. This is the case when the CAN Controller has reached the Error Passive Status (at least one error counter exceeds the CAN protocol defined level of 127) or if the CAN Controller is in Error Passive Status and enters the Error Active Status again."> + <Enum name="RESET" start="0" description="Reset" /> + <Enum name="SET" start="1" description="Set" /> + </BitField> + <BitField start="6" size="1" name="ALI" description="Arbitration Lost Interrupt. This bit is set if the ALIE bit in CANxIER is 1, and the CAN controller loses arbitration while attempting to transmit. In this case the CAN node becomes a receiver."> + <Enum name="RESET" start="0" description="Reset" /> + <Enum name="SET" start="1" description="Set" /> + </BitField> + <BitField start="7" size="1" name="BEI" description="Bus Error Interrupt -- this bit is set if the BEIE bit in CANxIER is 1, and the CAN controller detects an error on the bus."> + <Enum name="RESET" start="0" description="Reset" /> + <Enum name="SET" start="1" description="Set" /> + </BitField> + <BitField start="8" size="1" name="IDI" description="ID Ready Interrupt -- this bit is set if the IDIE bit in CANxIER is 1, and a CAN Identifier has been received (a message was successfully transmitted or aborted). This bit is set whenever a message was successfully transmitted or aborted and the IDIE bit is set in the IER register."> + <Enum name="RESET" start="0" description="Reset" /> + <Enum name="SET" start="1" description="Set" /> + </BitField> + <BitField start="9" size="1" name="TI2" description="Transmit Interrupt 2. This bit is set when the TBS2 bit in CANxSR goes from 0 to 1 (whenever a message out of TXB2 was successfully transmitted or aborted), indicating that Transmit buffer 2 is available, and the TIE2 bit in CANxIER is 1."> + <Enum name="RESET" start="0" description="Reset" /> + <Enum name="SET" start="1" description="Set" /> + </BitField> + <BitField start="10" size="1" name="TI3" description="Transmit Interrupt 3. This bit is set when the TBS3 bit in CANxSR goes from 0 to 1 (whenever a message out of TXB3 was successfully transmitted or aborted), indicating that Transmit buffer 3 is available, and the TIE3 bit in CANxIER is 1."> + <Enum name="RESET" start="0" description="Reset" /> + <Enum name="SET" start="1" description="Set" /> + </BitField> + <BitField start="11" size="5" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + <BitField start="16" size="5" name="ERRBIT4_0" description="Error Code Capture: when the CAN controller detects a bus error, the location of the error within the frame is captured in this field. The value reflects an internal state variable, and as a result is not very linear: 00011 = Start of Frame 00010 = ID28 ... ID21 00110 = ID20 ... ID18 00100 = SRTR Bit 00101 = IDE bit 00111 = ID17 ... 13 01111 = ID12 ... ID5 01110 = ID4 ... ID0 01100 = RTR Bit 01101 = Reserved Bit 1 01001 = Reserved Bit 0 01011 = Data Length Code 01010 = Data Field 01000 = CRC Sequence 11000 = CRC Delimiter 11001 = Acknowledge Slot 11011 = Acknowledge Delimiter 11010 = End of Frame 10010 = Intermission Whenever a bus error occurs, the corresponding bus error interrupt is forced, if enabled. At the same time, the current position of the Bit Stream Processor is captured into the Error Code Capture Register. The content within this register is fixed until the user software has read out its content once. From now on, the capture mechanism is activated again, i.e. reading the CANxICR enables another Bus Error Interrupt." /> + <BitField start="21" size="1" name="ERRDIR" description="When the CAN controller detects a bus error, the direction of the current bit is captured in this bit."> + <Enum name="ERROR_OCCURRED_DURIN" start="0" description="Error occurred during transmitting." /> + <Enum name="ERROR_OCCURRED_DURIN" start="1" description="Error occurred during receiving." /> + </BitField> + <BitField start="22" size="2" name="ERRC1_0" description="When the CAN controller detects a bus error, the type of error is captured in this field:"> + <Enum name="BIT_ERROR" start="0x0" description="Bit error" /> + <Enum name="FORM_ERROR" start="0x1" description="Form error" /> + <Enum name="STUFF_ERROR" start="0x2" description="Stuff error" /> + <Enum name="OTHER_ERROR" start="0x3" description="Other error" /> + </BitField> + <BitField start="24" size="8" name="ALCBIT" description="Each time arbitration is lost while trying to send on the CAN, the bit number within the frame is captured into this field. After the content of ALCBIT is read, the ALI bit is cleared and a new Arbitration Lost interrupt can occur. 00 = arbitration lost in the first bit (MS) of identifier ... 11 = arbitration lost in SRTS bit (RTR bit for standard frame messages) 12 = arbitration lost in IDE bit 13 = arbitration lost in 12th bit of identifier (extended frame only) ... 30 = arbitration lost in last bit of identifier (extended frame only) 31 = arbitration lost in RTR bit (extended frame only) On arbitration lost, the corresponding arbitration lost interrupt is forced, if enabled. At that time, the current bit position of the Bit Stream Processor is captured into the Arbitration Lost Capture Register. The content within this register is fixed until the user application has read out its contents once. From now on, the capture mechanism is activated again." /> + </Register> + <Register start="+0x010" size="4" name="IER" access="Read/Write" description="Interrupt Enable" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RIE" description="Receiver Interrupt Enable. When the Receive Buffer Status is 'full', the CAN Controller requests the respective interrupt." /> + <BitField start="1" size="1" name="TIE1" description="Transmit Interrupt Enable for Buffer1. When a message has been successfully transmitted out of TXB1 or Transmit Buffer 1 is accessible again (e.g. after an Abort Transmission command), the CAN Controller requests the respective interrupt." /> + <BitField start="2" size="1" name="EIE" description="Error Warning Interrupt Enable. If the Error or Bus Status change (see Status Register), the CAN Controller requests the respective interrupt." /> + <BitField start="3" size="1" name="DOIE" description="Data Overrun Interrupt Enable. If the Data Overrun Status bit is set (see Status Register), the CAN Controller requests the respective interrupt." /> + <BitField start="4" size="1" name="WUIE" description="Wake-Up Interrupt Enable. If the sleeping CAN controller wakes up, the respective interrupt is requested." /> + <BitField start="5" size="1" name="EPIE" description="Error Passive Interrupt Enable. If the error status of the CAN Controller changes from error active to error passive or vice versa, the respective interrupt is requested." /> + <BitField start="6" size="1" name="ALIE" description="Arbitration Lost Interrupt Enable. If the CAN Controller has lost arbitration, the respective interrupt is requested." /> + <BitField start="7" size="1" name="BEIE" description="Bus Error Interrupt Enable. If a bus error has been detected, the CAN Controller requests the respective interrupt." /> + <BitField start="8" size="1" name="IDIE" description="ID Ready Interrupt Enable. When a CAN identifier has been received, the CAN Controller requests the respective interrupt." /> + <BitField start="9" size="1" name="TIE2" description="Transmit Interrupt Enable for Buffer2. When a message has been successfully transmitted out of TXB2 or Transmit Buffer 2 is accessible again (e.g. after an Abort Transmission command), the CAN Controller requests the respective interrupt." /> + <BitField start="10" size="1" name="TIE3" description="Transmit Interrupt Enable for Buffer3. When a message has been successfully transmitted out of TXB3 or Transmit Buffer 3 is accessible again (e.g. after an Abort Transmission command), the CAN Controller requests the respective interrupt." /> + <BitField start="11" size="21" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x014" size="4" name="BTR" access="Read/Write" description="Bus Timing. Can only be written when RM in CANMOD is 1." reset_value="0x1C0000" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="10" name="BRP" description="Baud Rate Prescaler. The APB clock is divided by (this value plus one) to produce the CAN clock." /> + <BitField start="10" size="4" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="14" size="2" name="SJW" description="The Synchronization Jump Width is (this value plus one) CAN clocks." /> + <BitField start="16" size="4" name="TESG1" description="The delay from the nominal Sync point to the sample point is (this value plus one) CAN clocks." /> + <BitField start="20" size="3" name="TESG2" description="The delay from the sample point to the next nominal sync point is (this value plus one) CAN clocks. The nominal CAN bit time is (this value plus the value in TSEG1 plus 3) CAN clocks." /> + <BitField start="23" size="1" name="SAM" description="Sampling"> + <Enum name="THE_BUS_IS_SAMPLED_O" start="0" description="The bus is sampled once (recommended for high speed buses)" /> + <Enum name="THE_BUS_IS_SAMPLED_3" start="1" description="The bus is sampled 3 times (recommended for low to medium speed buses to filter spikes on the bus-line)" /> + </BitField> + <BitField start="24" size="8" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x018" size="4" name="EWL" access="Read/Write" description="Error Warning Limit. Can only be written when RM in CANMOD is 1." reset_value="0x60" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="EWL" description="During CAN operation, this value is compared to both the Tx and Rx Error Counters. If either of these counter matches this value, the Error Status (ES) bit in CANSR is set." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x01C" size="4" name="SR" access="ReadOnly" description="Status Register" reset_value="0x3C3C3C" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RBS_1" description="Receive Buffer Status. This bit is identical to the RBS bit in the CANxGSR." /> + <BitField start="1" size="1" name="DOS_1" description="Data Overrun Status. This bit is identical to the DOS bit in the CANxGSR." /> + <BitField start="2" size="1" name="TBS1_1" description="Transmit Buffer Status 1."> + <Enum name="LOCKED_SOFTWARE_CAN" start="0" description="Locked. Software cannot access the Tx Buffer 1 nor write to the corresponding CANxTFI, CANxTID, CANxTDA, and CANxTDB registers because a message is either waiting for transmission or is in transmitting process." /> + <Enum name="RELEASED_SOFTWARE_M" start="1" description="Released. Software may write a message into the Transmit Buffer 1 and its CANxTFI, CANxTID, CANxTDA, and CANxTDB registers." /> + </BitField> + <BitField start="3" size="1" name="TCS1_1" description="Transmission Complete Status."> + <Enum name="INCOMPLETE_THE_PREV" start="0" description="Incomplete. The previously requested transmission for Tx Buffer 1 is not complete." /> + <Enum name="COMPLETE_THE_PREVIO" start="1" description="Complete. The previously requested transmission for Tx Buffer 1 has been successfully completed." /> + </BitField> + <BitField start="4" size="1" name="RS_1" description="Receive Status. This bit is identical to the RS bit in the GSR." /> + <BitField start="5" size="1" name="TS1_1" description="Transmit Status 1."> + <Enum name="IDLE_THERE_IS_NO_TR" start="0" description="Idle. There is no transmission from Tx Buffer 1." /> + <Enum name="TRANSMIT_THE_CAN_CO" start="1" description="Transmit. The CAN Controller is transmitting a message from Tx Buffer 1." /> + </BitField> + <BitField start="6" size="1" name="ES_1" description="Error Status. This bit is identical to the ES bit in the CANxGSR." /> + <BitField start="7" size="1" name="BS_1" description="Bus Status. This bit is identical to the BS bit in the CANxGSR." /> + <BitField start="8" size="1" name="RBS_2" description="Receive Buffer Status. This bit is identical to the RBS bit in the CANxGSR." /> + <BitField start="9" size="1" name="DOS_2" description="Data Overrun Status. This bit is identical to the DOS bit in the CANxGSR." /> + <BitField start="10" size="1" name="TBS2_2" description="Transmit Buffer Status 2."> + <Enum name="LOCKED_SOFTWARE_CAN" start="0" description="Locked. Software cannot access the Tx Buffer 2 nor write to the corresponding CANxTFI, CANxTID, CANxTDA, and CANxTDB registers because a message is either waiting for transmission or is in transmitting process." /> + <Enum name="RELEASED_SOFTWARE_M" start="1" description="Released. Software may write a message into the Transmit Buffer 2 and its CANxTFI, CANxTID, CANxTDA, and CANxTDB registers." /> + </BitField> + <BitField start="11" size="1" name="TCS2_2" description="Transmission Complete Status."> + <Enum name="INCOMPLETE_THE_PREV" start="0" description="Incomplete. The previously requested transmission for Tx Buffer 2 is not complete." /> + <Enum name="COMPLETE_THE_PREVIO" start="1" description="Complete. The previously requested transmission for Tx Buffer 2 has been successfully completed." /> + </BitField> + <BitField start="12" size="1" name="RS_2" description="Receive Status. This bit is identical to the RS bit in the GSR." /> + <BitField start="13" size="1" name="TS2_2" description="Transmit Status 2."> + <Enum name="IDLE_THERE_IS_NO_TR" start="0" description="Idle. There is no transmission from Tx Buffer 2." /> + <Enum name="TRANSMIT_THE_CAN_CO" start="1" description="Transmit. The CAN Controller is transmitting a message from Tx Buffer 2." /> + </BitField> + <BitField start="14" size="1" name="ES_2" description="Error Status. This bit is identical to the ES bit in the CANxGSR." /> + <BitField start="15" size="1" name="BS_2" description="Bus Status. This bit is identical to the BS bit in the CANxGSR." /> + <BitField start="16" size="1" name="RBS_3" description="Receive Buffer Status. This bit is identical to the RBS bit in the CANxGSR." /> + <BitField start="17" size="1" name="DOS_3" description="Data Overrun Status. This bit is identical to the DOS bit in the CANxGSR." /> + <BitField start="18" size="1" name="TBS3_3" description="Transmit Buffer Status 3."> + <Enum name="LOCKED_SOFTWARE_CAN" start="0" description="Locked. Software cannot access the Tx Buffer 3 nor write to the corresponding CANxTFI, CANxTID, CANxTDA, and CANxTDB registers because a message is either waiting for transmission or is in transmitting process." /> + <Enum name="RELEASED_SOFTWARE_M" start="1" description="Released. Software may write a message into the Transmit Buffer 3 and its CANxTFI, CANxTID, CANxTDA, and CANxTDB registers." /> + </BitField> + <BitField start="19" size="1" name="TCS3_3" description="Transmission Complete Status."> + <Enum name="INCOMPLETE_THE_PREV" start="0" description="Incomplete. The previously requested transmission for Tx Buffer 3 is not complete." /> + <Enum name="COMPLETE_THE_PREVIO" start="1" description="Complete. The previously requested transmission for Tx Buffer 3 has been successfully completed." /> + </BitField> + <BitField start="20" size="1" name="RS_3" description="Receive Status. This bit is identical to the RS bit in the GSR." /> + <BitField start="21" size="1" name="TS3_3" description="Transmit Status 3."> + <Enum name="IDLE_THERE_IS_NO_TR" start="0" description="Idle. There is no transmission from Tx Buffer 3." /> + <Enum name="TRANSMIT_THE_CAN_CO" start="1" description="Transmit. The CAN Controller is transmitting a message from Tx Buffer 3." /> + </BitField> + <BitField start="22" size="1" name="ES_3" description="Error Status. This bit is identical to the ES bit in the CANxGSR." /> + <BitField start="23" size="1" name="BS_3" description="Bus Status. This bit is identical to the BS bit in the CANxGSR." /> + <BitField start="24" size="8" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x020" size="4" name="RFS" access="Read/Write" description="Receive frame status. Can only be written when RM in CANMOD is 1." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="10" name="IDINDEX" description="ID Index. If the BP bit (below) is 0, this value is the zero-based number of the Lookup Table RAM entry at which the Acceptance Filter matched the received Identifier. Disabled entries in the Standard tables are included in this numbering, but will not be matched. See Section 21.17 Examples of acceptance filter tables and ID index values on page 587 for examples of ID Index values." /> + <BitField start="10" size="1" name="BP" description="If this bit is 1, the current message was received in AF Bypass mode, and the ID Index field (above) is meaningless." /> + <BitField start="11" size="5" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + <BitField start="16" size="4" name="DLC" description="The field contains the Data Length Code (DLC) field of the current received message. When RTR = 0, this is related to the number of data bytes available in the CANRDA and CANRDB registers as follows: 0000-0111 = 0 to 7 bytes1000-1111 = 8 bytes With RTR = 1, this value indicates the number of data bytes requested to be sent back, with the same encoding." /> + <BitField start="20" size="10" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="30" size="1" name="RTR" description="This bit contains the Remote Transmission Request bit of the current received message. 0 indicates a Data Frame, in which (if DLC is non-zero) data can be read from the CANRDA and possibly the CANRDB registers. 1 indicates a Remote frame, in which case the DLC value identifies the number of data bytes requested to be sent using the same Identifier." /> + <BitField start="31" size="1" name="FF" description="A 0 in this bit indicates that the current received message included an 11-bit Identifier, while a 1 indicates a 29-bit Identifier. This affects the contents of the CANid register described below." /> + </Register> + <Register start="+0x024" size="4" name="RID" access="Read/Write" description="Received Identifier. Can only be written when RM in CANMOD is 1." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="11" name="ID" description="The 11-bit Identifier field of the current received message. In CAN 2.0A, these bits are called ID10-0, while in CAN 2.0B they're called ID29-18." /> + <BitField start="11" size="21" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x028" size="4" name="RDA" access="Read/Write" description="Received data bytes 1-4. Can only be written when RM in CANMOD is 1." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="DATA1" description="Data 1. If the DLC field in CANRFS >= 0001, this contains the first Data byte of the current received message." /> + <BitField start="8" size="8" name="DATA2" description="Data 2. If the DLC field in CANRFS >= 0010, this contains the first Data byte of the current received message." /> + <BitField start="16" size="8" name="DATA3" description="Data 3. If the DLC field in CANRFS >= 0011, this contains the first Data byte of the current received message." /> + <BitField start="24" size="8" name="DATA4" description="Data 4. If the DLC field in CANRFS >= 0100, this contains the first Data byte of the current received message." /> + </Register> + <Register start="+0x02C" size="4" name="RDB" access="Read/Write" description="Received data bytes 5-8. Can only be written when RM in CANMOD is 1." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="DATA5" description="Data 5. If the DLC field in CANRFS >= 0101, this contains the first Data byte of the current received message." /> + <BitField start="8" size="8" name="DATA6" description="Data 6. If the DLC field in CANRFS >= 0110, this contains the first Data byte of the current received message." /> + <BitField start="16" size="8" name="DATA7" description="Data 7. If the DLC field in CANRFS >= 0111, this contains the first Data byte of the current received message." /> + <BitField start="24" size="8" name="DATA8" description="Data 8. If the DLC field in CANRFS >= 1000, this contains the first Data byte of the current received message." /> + </Register> + <Register start="+0x030+0" size="4" name="TFI1" access="Read/Write" description="Transmit
frame info (Tx Buffer )" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="PRIO" description="If the TPM (Transmit Priority Mode) bit in the CANxMOD register is set to 1, enabled Tx Buffers contend for the right to send their messages based on this field. The buffer with the lowest TX Priority value wins the prioritization and is sent first." /> + <BitField start="8" size="8" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="16" size="4" name="DLC" description="Data Length Code. This value is sent in the DLC field of the next transmit message. In addition, if RTR = 0, this value controls the number of Data bytes sent in the next transmit message, from the CANxTDA and CANxTDB registers: 0000-0111 = 0-7 bytes 1xxx = 8 bytes" /> + <BitField start="20" size="10" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="30" size="1" name="RTR" description="This value is sent in the RTR bit of the next transmit message. If this bit is 0, the number of data bytes called out by the DLC field are sent from the CANxTDA and CANxTDB registers. If this bit is 1, a Remote Frame is sent, containing a request for that number of bytes." /> + <BitField start="31" size="1" name="FF" description="If this bit is 0, the next transmit message will be sent with an 11-bit Identifier (standard frame format), while if it's 1, the message will be sent with a 29-bit Identifier (extended frame format)." /> + </Register> + <Register start="+0x030+16" size="4" name="TFI2" access="Read/Write" description="Transmit
frame info (Tx Buffer )" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="PRIO" description="If the TPM (Transmit Priority Mode) bit in the CANxMOD register is set to 1, enabled Tx Buffers contend for the right to send their messages based on this field. The buffer with the lowest TX Priority value wins the prioritization and is sent first." /> + <BitField start="8" size="8" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="16" size="4" name="DLC" description="Data Length Code. This value is sent in the DLC field of the next transmit message. In addition, if RTR = 0, this value controls the number of Data bytes sent in the next transmit message, from the CANxTDA and CANxTDB registers: 0000-0111 = 0-7 bytes 1xxx = 8 bytes" /> + <BitField start="20" size="10" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="30" size="1" name="RTR" description="This value is sent in the RTR bit of the next transmit message. If this bit is 0, the number of data bytes called out by the DLC field are sent from the CANxTDA and CANxTDB registers. If this bit is 1, a Remote Frame is sent, containing a request for that number of bytes." /> + <BitField start="31" size="1" name="FF" description="If this bit is 0, the next transmit message will be sent with an 11-bit Identifier (standard frame format), while if it's 1, the message will be sent with a 29-bit Identifier (extended frame format)." /> + </Register> + <Register start="+0x030+32" size="4" name="TFI3" access="Read/Write" description="Transmit
frame info (Tx Buffer )" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="PRIO" description="If the TPM (Transmit Priority Mode) bit in the CANxMOD register is set to 1, enabled Tx Buffers contend for the right to send their messages based on this field. The buffer with the lowest TX Priority value wins the prioritization and is sent first." /> + <BitField start="8" size="8" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="16" size="4" name="DLC" description="Data Length Code. This value is sent in the DLC field of the next transmit message. In addition, if RTR = 0, this value controls the number of Data bytes sent in the next transmit message, from the CANxTDA and CANxTDB registers: 0000-0111 = 0-7 bytes 1xxx = 8 bytes" /> + <BitField start="20" size="10" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="30" size="1" name="RTR" description="This value is sent in the RTR bit of the next transmit message. If this bit is 0, the number of data bytes called out by the DLC field are sent from the CANxTDA and CANxTDB registers. If this bit is 1, a Remote Frame is sent, containing a request for that number of bytes." /> + <BitField start="31" size="1" name="FF" description="If this bit is 0, the next transmit message will be sent with an 11-bit Identifier (standard frame format), while if it's 1, the message will be sent with a 29-bit Identifier (extended frame format)." /> + </Register> + <Register start="+0x034+0" size="4" name="TID1" access="Read/Write" description="Transmit
Identifier (Tx Buffer)" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="11" name="ID" description="The 11-bit Identifier to be sent in the next transmit message." /> + <BitField start="11" size="21" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x034+16" size="4" name="TID2" access="Read/Write" description="Transmit
Identifier (Tx Buffer)" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="11" name="ID" description="The 11-bit Identifier to be sent in the next transmit message." /> + <BitField start="11" size="21" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x034+32" size="4" name="TID3" access="Read/Write" description="Transmit
Identifier (Tx Buffer)" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="11" name="ID" description="The 11-bit Identifier to be sent in the next transmit message." /> + <BitField start="11" size="21" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x038+0" size="4" name="TDA1" access="Read/Write" description="Transmit
data bytes 1-4 (Tx Buffer)" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="8" name="DATA1" description="Data 1. If RTR = 0 and DLC >= 0001 in the corresponding CANxTFI, this byte is sent as the first Data byte of the next transmit message." /> + <BitField start="8" size="8" name="DATA2" description="Data 2. If RTR = 0 and DLC >= 0010 in the corresponding CANxTFI, this byte is sent as the 2nd Data byte of the next transmit message." /> + <BitField start="16" size="8" name="DATA3" description="Data 3. If RTR = 0 and DLC >= 0011 in the corresponding CANxTFI, this byte is sent as the 3rd Data byte of the next transmit message." /> + <BitField start="24" size="8" name="DATA4" description="Data 4. If RTR = 0 and DLC >= 0100 in the corresponding CANxTFI, this byte is sent as the 4th Data byte of the next transmit message." /> + </Register> + <Register start="+0x038+16" size="4" name="TDA2" access="Read/Write" description="Transmit
data bytes 1-4 (Tx Buffer)" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="8" name="DATA1" description="Data 1. If RTR = 0 and DLC >= 0001 in the corresponding CANxTFI, this byte is sent as the first Data byte of the next transmit message." /> + <BitField start="8" size="8" name="DATA2" description="Data 2. If RTR = 0 and DLC >= 0010 in the corresponding CANxTFI, this byte is sent as the 2nd Data byte of the next transmit message." /> + <BitField start="16" size="8" name="DATA3" description="Data 3. If RTR = 0 and DLC >= 0011 in the corresponding CANxTFI, this byte is sent as the 3rd Data byte of the next transmit message." /> + <BitField start="24" size="8" name="DATA4" description="Data 4. If RTR = 0 and DLC >= 0100 in the corresponding CANxTFI, this byte is sent as the 4th Data byte of the next transmit message." /> + </Register> + <Register start="+0x038+32" size="4" name="TDA3" access="Read/Write" description="Transmit
data bytes 1-4 (Tx Buffer)" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="8" name="DATA1" description="Data 1. If RTR = 0 and DLC >= 0001 in the corresponding CANxTFI, this byte is sent as the first Data byte of the next transmit message." /> + <BitField start="8" size="8" name="DATA2" description="Data 2. If RTR = 0 and DLC >= 0010 in the corresponding CANxTFI, this byte is sent as the 2nd Data byte of the next transmit message." /> + <BitField start="16" size="8" name="DATA3" description="Data 3. If RTR = 0 and DLC >= 0011 in the corresponding CANxTFI, this byte is sent as the 3rd Data byte of the next transmit message." /> + <BitField start="24" size="8" name="DATA4" description="Data 4. If RTR = 0 and DLC >= 0100 in the corresponding CANxTFI, this byte is sent as the 4th Data byte of the next transmit message." /> + </Register> + <Register start="+0x03C+0" size="4" name="TDB1" access="Read/Write" description="Transmit
data bytes 5-8 (Tx Buffer )" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="8" name="DATA5" description="Data 5. If RTR = 0 and DLC >= 0101 in the corresponding CANTFI, this byte is sent as the 5th Data byte of the next transmit message." /> + <BitField start="8" size="8" name="DATA6" description="Data 6. If RTR = 0 and DLC >= 0110 in the corresponding CANTFI, this byte is sent as the 6th Data byte of the next transmit message." /> + <BitField start="16" size="8" name="DATA7" description="Data 7. If RTR = 0 and DLC >= 0111 in the corresponding CANTFI, this byte is sent as the 7th Data byte of the next transmit message." /> + <BitField start="24" size="8" name="DATA8" description="Data 8. If RTR = 0 and DLC >= 1000 in the corresponding CANTFI, this byte is sent as the 8th Data byte of the next transmit message." /> + </Register> + <Register start="+0x03C+16" size="4" name="TDB2" access="Read/Write" description="Transmit
data bytes 5-8 (Tx Buffer )" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="8" name="DATA5" description="Data 5. If RTR = 0 and DLC >= 0101 in the corresponding CANTFI, this byte is sent as the 5th Data byte of the next transmit message." /> + <BitField start="8" size="8" name="DATA6" description="Data 6. If RTR = 0 and DLC >= 0110 in the corresponding CANTFI, this byte is sent as the 6th Data byte of the next transmit message." /> + <BitField start="16" size="8" name="DATA7" description="Data 7. If RTR = 0 and DLC >= 0111 in the corresponding CANTFI, this byte is sent as the 7th Data byte of the next transmit message." /> + <BitField start="24" size="8" name="DATA8" description="Data 8. If RTR = 0 and DLC >= 1000 in the corresponding CANTFI, this byte is sent as the 8th Data byte of the next transmit message." /> + </Register> + <Register start="+0x03C+32" size="4" name="TDB3" access="Read/Write" description="Transmit
data bytes 5-8 (Tx Buffer )" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="8" name="DATA5" description="Data 5. If RTR = 0 and DLC >= 0101 in the corresponding CANTFI, this byte is sent as the 5th Data byte of the next transmit message." /> + <BitField start="8" size="8" name="DATA6" description="Data 6. If RTR = 0 and DLC >= 0110 in the corresponding CANTFI, this byte is sent as the 6th Data byte of the next transmit message." /> + <BitField start="16" size="8" name="DATA7" description="Data 7. If RTR = 0 and DLC >= 0111 in the corresponding CANTFI, this byte is sent as the 7th Data byte of the next transmit message." /> + <BitField start="24" size="8" name="DATA8" description="Data 8. If RTR = 0 and DLC >= 1000 in the corresponding CANTFI, this byte is sent as the 8th Data byte of the next transmit message." /> + </Register> + </RegisterGroup> + <RegisterGroup name="CAN2" start="0x40048000" description="CAN1 controller "> + <Register start="+0x000" size="4" name="MOD" access="Read/Write" description="Controls the operating mode of the CAN Controller." reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="RM" description="Reset Mode."> + <Enum name="NORMAL_THE_CAN_CONTR" start="0" description="Normal.The CAN Controller is in the Operating Mode, and certain registers can not be written." /> + <Enum name="RESET_CAN_OPERATION" start="1" description="Reset. CAN operation is disabled, writable registers can be written and the current transmission/reception of a message is aborted." /> + </BitField> + <BitField start="1" size="1" name="LOM" description="Listen Only Mode."> + <Enum name="NORMAL_THE_CAN_CONT" start="0" description="Normal. The CAN controller acknowledges a successfully received message on the CAN bus. The error counters are stopped at the current value." /> + <Enum name="LISTEN_ONLY_THE_CON" start="1" description="Listen only. The controller gives no acknowledgment, even if a message is successfully received. Messages cannot be sent, and the controller operates in error passive mode. This mode is intended for software bit rate detection and hot plugging." /> + </BitField> + <BitField start="2" size="1" name="STM" description="Self Test Mode."> + <Enum name="NORMAL_A_TRANSMITTE" start="0" description="Normal. A transmitted message must be acknowledged to be considered successful." /> + <Enum name="SELF_TEST_THE_CONTR" start="1" description="Self test. The controller will consider a Tx message successful even if there is no acknowledgment received. In this mode a full node test is possible without any other active node on the bus using the SRR bit in CANxCMR." /> + </BitField> + <BitField start="3" size="1" name="TPM" description="Transmit Priority Mode."> + <Enum name="CAN_ID_THE_TRANSMIT" start="0" description="CAN ID. The transmit priority for 3 Transmit Buffers depends on the CAN Identifier." /> + <Enum name="LOCAL_PRIORITY_THE_" start="1" description="Local priority. The transmit priority for 3 Transmit Buffers depends on the contents of the Tx Priority register within the Transmit Buffer." /> + </BitField> + <BitField start="4" size="1" name="SM" description="Sleep Mode."> + <Enum name="WAKE_UP_NORMAL_OPER" start="0" description="Wake-up. Normal operation." /> + <Enum name="SLEEP_THE_CAN_CONTR" start="1" description="Sleep. The CAN controller enters Sleep Mode if no CAN interrupt is pending and there is no bus activity. See the Sleep Mode description Section 21.8.2 on page 565." /> + </BitField> + <BitField start="5" size="1" name="RPM" description="Receive Polarity Mode."> + <Enum name="LOW_ACTIVE_RD_INPUT" start="0" description="Low active. RD input is active Low (dominant bit = 0)." /> + <Enum name="HIGH_ACTIVE_RD_INPU" start="1" description="High active. RD input is active High (dominant bit = 1) -- reverse polarity." /> + </BitField> + <BitField start="6" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="7" size="1" name="TM" description="Test Mode."> + <Enum name="DISABLED_NORMAL_OPE" start="0" description="Disabled. Normal operation." /> + <Enum name="ENABLED_THE_TD_PIN_" start="1" description="Enabled. The TD pin will reflect the bit, detected on RD pin, with the next positive edge of the system clock." /> + </BitField> + <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x004" size="4" name="CMR" access="WriteOnly" description="Command bits that affect the state of the CAN Controller" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="TR" description="Transmission Request."> + <Enum name="ABSENT_NO_TRANSMISSI" start="0" description="Absent.No transmission request." /> + <Enum name="PRESENT_THE_MESSAGE" start="1" description="Present. The message, previously written to the CANxTFI, CANxTID, and optionally the CANxTDA and CANxTDB registers, is queued for transmission from the selected Transmit Buffer. If at two or all three of STB1, STB2 and STB3 bits are selected when TR=1 is written, Transmit Buffer will be selected based on the chosen priority scheme (for details see Section 21.5.3 Transmit Buffers (TXB))" /> + </BitField> + <BitField start="1" size="1" name="AT" description="Abort Transmission."> + <Enum name="NO_ACTION_DO_NOT_AB" start="0" description="No action. Do not abort the transmission." /> + <Enum name="PRESENT_IF_NOT_ALRE" start="1" description="Present. if not already in progress, a pending Transmission Request for the selected Transmit Buffer is cancelled." /> + </BitField> + <BitField start="2" size="1" name="RRB" description="Release Receive Buffer."> + <Enum name="NO_ACTION_DO_NOT_RE" start="0" description="No action. Do not release the receive buffer." /> + <Enum name="RELEASED_THE_INFORM" start="1" description="Released. The information in the Receive Buffer (consisting of CANxRFS, CANxRID, and if applicable the CANxRDA and CANxRDB registers) is released, and becomes eligible for replacement by the next received frame. If the next received frame is not available, writing this command clears the RBS bit in the Status Register(s)." /> + </BitField> + <BitField start="3" size="1" name="CDO" description="Clear Data Overrun."> + <Enum name="NO_ACTION_DO_NOT_CL" start="0" description="No action. Do not clear the data overrun bit." /> + <Enum name="CLEAR_THE_DATA_OVER" start="1" description="Clear. The Data Overrun bit in Status Register(s) is cleared." /> + </BitField> + <BitField start="4" size="1" name="SRR" description="Self Reception Request."> + <Enum name="ABSENT_NO_SELF_RECE" start="0" description="Absent. No self reception request." /> + <Enum name="PRESENT_THE_MESSAGE" start="1" description="Present. The message, previously written to the CANxTFS, CANxTID, and optionally the CANxTDA and CANxTDB registers, is queued for transmission from the selected Transmit Buffer and received simultaneously. This differs from the TR bit above in that the receiver is not disabled during the transmission, so that it receives the message if its Identifier is recognized by the Acceptance Filter." /> + </BitField> + <BitField start="5" size="1" name="STB1" description="Select Tx Buffer 1."> + <Enum name="NOT_SELECTED_TX_BUF" start="0" description="Not selected. Tx Buffer 1 is not selected for transmission." /> + <Enum name="SELECTED_TX_BUFFER_" start="1" description="Selected. Tx Buffer 1 is selected for transmission." /> + </BitField> + <BitField start="6" size="1" name="STB2" description="Select Tx Buffer 2."> + <Enum name="NOT_SELECTED_TX_BUF" start="0" description="Not selected. Tx Buffer 2 is not selected for transmission." /> + <Enum name="SELECTED_TX_BUFFER_" start="1" description="Selected. Tx Buffer 2 is selected for transmission." /> + </BitField> + <BitField start="7" size="1" name="STB3" description="Select Tx Buffer 3."> + <Enum name="NOT_SELECTED_TX_BUF" start="0" description="Not selected. Tx Buffer 3 is not selected for transmission." /> + <Enum name="SELECTED_TX_BUFFER_" start="1" description="Selected. Tx Buffer 3 is selected for transmission." /> + </BitField> + <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x008" size="4" name="GSR" access="ReadOnly" description="Global Controller Status and Error Counters. The error counters can only be written when RM in CANMOD is 1." reset_value="0x3C" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RBS" description="Receive Buffer Status. After reading all messages and releasing their memory space with the command 'Release Receive Buffer,' this bit is cleared."> + <Enum name="EMPTY_NO_MESSAGE_IS" start="0" description="Empty. No message is available." /> + <Enum name="FULL_AT_LEAST_ONE_C" start="1" description="Full. At least one complete message is received by the Double Receive Buffer and available in the CANxRFS, CANxRID, and if applicable the CANxRDA and CANxRDB registers. This bit is cleared by the Release Receive Buffer command in CANxCMR, if no subsequent received message is available." /> + </BitField> + <BitField start="1" size="1" name="DOS" description="Data Overrun Status. If there is not enough space to store the message within the Receive Buffer, that message is dropped and the Data Overrun condition is signalled to the CPU in the moment this message becomes valid. If this message is not completed successfully (e.g. because of an error), no overrun condition is signalled."> + <Enum name="ABSENT_NO_DATA_OVER" start="0" description="Absent. No data overrun has occurred since the last Clear Data Overrun command was given/written to CANxCMR (or since Reset)." /> + <Enum name="OVERRUN_A_MESSAGE_W" start="1" description="Overrun. A message was lost because the preceding message to this CAN controller was not read and released quickly enough (there was not enough space for a new message in the Double Receive Buffer)." /> + </BitField> + <BitField start="2" size="1" name="TBS" description="Transmit Buffer Status."> + <Enum name="LOCKED_AT_LEAST_ONE" start="0" description="Locked. At least one of the Transmit Buffers is not available for the CPU, i.e. at least one previously queued message for this CAN controller has not yet been sent, and therefore software should not write to the CANxTFI, CANxTID, CANxTDA, nor CANxTDB registers of that (those) Tx buffer(s)." /> + <Enum name="RELEASED_ALL_THREE_" start="1" description="Released. All three Transmit Buffers are available for the CPU. No transmit message is pending for this CAN controller (in any of the 3 Tx buffers), and software may write to any of the CANxTFI, CANxTID, CANxTDA, and CANxTDB registers." /> + </BitField> + <BitField start="3" size="1" name="TCS" description="Transmit Complete Status. The Transmission Complete Status bit is set '0' (incomplete) whenever the Transmission Request bit or the Self Reception Request bit is set '1' at least for one of the three Transmit Buffers. The Transmission Complete Status bit will remain '0' until all messages are transmitted successfully."> + <Enum name="INCOMPLETE_AT_LEAST" start="0" description="Incomplete. At least one requested transmission has not been successfully completed yet." /> + <Enum name="COMPLETE_ALL_REQUES" start="1" description="Complete. All requested transmission(s) has (have) been successfully completed." /> + </BitField> + <BitField start="4" size="1" name="RS" description="Receive Status. If both the Receive Status and the Transmit Status bits are '0' (idle), the CAN-Bus is idle. If both bits are set, the controller is waiting to become idle again. After hardware reset 11 consecutive recessive bits have to be detected until idle status is reached. After Bus-off this will take 128 times of 11 consecutive recessive bits."> + <Enum name="IDLE_THE_CAN_CONTRO" start="0" description="Idle. The CAN controller is idle." /> + <Enum name="RECEIVE_THE_CAN_CON" start="1" description="Receive. The CAN controller is receiving a message." /> + </BitField> + <BitField start="5" size="1" name="TS" description="Transmit Status. If both the Receive Status and the Transmit Status bits are '0' (idle), the CAN-Bus is idle. If both bits are set, the controller is waiting to become idle again. After hardware reset 11 consecutive recessive bits have to be detected until idle status is reached. After Bus-off this will take 128 times of 11 consecutive recessive bits."> + <Enum name="IDLE_THE_CAN_CONTRO" start="0" description="Idle. The CAN controller is idle." /> + <Enum name="TRANSMIT_THE_CAN_CO" start="1" description="Transmit. The CAN controller is sending a message." /> + </BitField> + <BitField start="6" size="1" name="ES" description="Error Status. Errors detected during reception or transmission will effect the error counters according to the CAN specification. The Error Status bit is set when at least one of the error counters has reached or exceeded the Error Warning Limit. An Error Warning Interrupt is generated, if enabled. The default value of the Error Warning Limit after hardware reset is 96 decimal, see also Section 21.7.7 CAN Error Warning Limit register (CAN1EWL - 0x4004 4018, CAN2EWL - 0x4004 8018)."> + <Enum name="OK_BOTH_ERROR_COUNT" start="0" description="OK. Both error counters are below the Error Warning Limit." /> + <Enum name="ERROR_ONE_OR_BOTH_O" start="1" description="Error. One or both of the Transmit and Receive Error Counters has reached the limit set in the Error Warning Limit register." /> + </BitField> + <BitField start="7" size="1" name="BS" description="Bus Status. Mode bit '1' (present) and an Error Warning Interrupt is generated, if enabled. Afterwards the Transmit Error Counter is set to '127', and the Receive Error Counter is cleared. It will stay in this mode until the CPU clears the Reset Mode bit. Once this is completed the CAN Controller will wait the minimum protocol-defined time (128 occurrences of the Bus-Free signal) counting down the Transmit Error Counter. After that, the Bus Status bit is cleared (Bus-On), the Error Status bit is set '0' (ok), the Error Counters are reset, and an Error Warning Interrupt is generated, if enabled. Reading the TX Error Counter during this time gives information about the status of the Bus-Off recovery."> + <Enum name="BUS_ON_THE_CAN_CONT" start="0" description="Bus-on. The CAN Controller is involved in bus activities" /> + <Enum name="BUS_OFF_THE_CAN_CON" start="1" description="Bus-off. The CAN controller is currently not involved/prohibited from bus activity because the Transmit Error Counter reached its limiting value of 255." /> + </BitField> + <BitField start="8" size="8" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="16" size="8" name="RXERR" description="The current value of the Rx Error Counter (an 8-bit value)." /> + <BitField start="24" size="8" name="TXERR" description="The current value of the Tx Error Counter (an 8-bit value)." /> + </Register> + <Register start="+0x00C" size="4" name="ICR" access="ReadOnly" description="Interrupt status, Arbitration Lost Capture, Error Code Capture" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RI" description="Receive Interrupt. This bit is set whenever the RBS bit in CANxSR and the RIE bit in CANxIER are both 1, indicating that a new message was received and stored in the Receive Buffer. The Receive Interrupt Bit is not cleared upon a read access to the Interrupt Register. Giving the Command Release Receive Buffer will clear RI temporarily. If there is another message available within the Receive Buffer after the release command, RI is set again. Otherwise RI remains cleared."> + <Enum name="RESET" start="0" description="Reset" /> + <Enum name="SET" start="1" description="Set" /> + </BitField> + <BitField start="1" size="1" name="TI1" description="Transmit Interrupt 1. This bit is set when the TBS1 bit in CANxSR goes from 0 to 1 (whenever a message out of TXB1 was successfully transmitted or aborted), indicating that Transmit buffer 1 is available, and the TIE1 bit in CANxIER is 1."> + <Enum name="RESET" start="0" description="Reset" /> + <Enum name="SET" start="1" description="Set" /> + </BitField> + <BitField start="2" size="1" name="EI" description="Error Warning Interrupt. This bit is set on every change (set or clear) of either the Error Status or Bus Status bit in CANxSR and the EIE bit bit is set within the Interrupt Enable Register at the time of the change."> + <Enum name="RESET" start="0" description="Reset" /> + <Enum name="SET" start="1" description="Set" /> + </BitField> + <BitField start="3" size="1" name="DOI" description="Data Overrun Interrupt. This bit is set when the DOS bit in CANxSR goes from 0 to 1 and the DOIE bit in CANxIER is 1."> + <Enum name="RESET" start="0" description="Reset" /> + <Enum name="SET" start="1" description="Set" /> + </BitField> + <BitField start="4" size="1" name="WUI" description="Wake-Up Interrupt. This bit is set if the CAN controller is sleeping and bus activity is detected and the WUIE bit in CANxIER is 1. A Wake-Up Interrupt is also generated if the CPU tries to set the Sleep bit while the CAN controller is involved in bus activities or a CAN Interrupt is pending. The WUI flag can also get asserted when the according enable bit WUIE is not set. In this case a Wake-Up Interrupt does not get asserted."> + <Enum name="RESET" start="0" description="Reset" /> + <Enum name="SET" start="1" description="Set" /> + </BitField> + <BitField start="5" size="1" name="EPI" description="Error Passive Interrupt. This bit is set if the EPIE bit in CANxIER is 1, and the CAN controller switches between Error Passive and Error Active mode in either direction. This is the case when the CAN Controller has reached the Error Passive Status (at least one error counter exceeds the CAN protocol defined level of 127) or if the CAN Controller is in Error Passive Status and enters the Error Active Status again."> + <Enum name="RESET" start="0" description="Reset" /> + <Enum name="SET" start="1" description="Set" /> + </BitField> + <BitField start="6" size="1" name="ALI" description="Arbitration Lost Interrupt. This bit is set if the ALIE bit in CANxIER is 1, and the CAN controller loses arbitration while attempting to transmit. In this case the CAN node becomes a receiver."> + <Enum name="RESET" start="0" description="Reset" /> + <Enum name="SET" start="1" description="Set" /> + </BitField> + <BitField start="7" size="1" name="BEI" description="Bus Error Interrupt -- this bit is set if the BEIE bit in CANxIER is 1, and the CAN controller detects an error on the bus."> + <Enum name="RESET" start="0" description="Reset" /> + <Enum name="SET" start="1" description="Set" /> + </BitField> + <BitField start="8" size="1" name="IDI" description="ID Ready Interrupt -- this bit is set if the IDIE bit in CANxIER is 1, and a CAN Identifier has been received (a message was successfully transmitted or aborted). This bit is set whenever a message was successfully transmitted or aborted and the IDIE bit is set in the IER register."> + <Enum name="RESET" start="0" description="Reset" /> + <Enum name="SET" start="1" description="Set" /> + </BitField> + <BitField start="9" size="1" name="TI2" description="Transmit Interrupt 2. This bit is set when the TBS2 bit in CANxSR goes from 0 to 1 (whenever a message out of TXB2 was successfully transmitted or aborted), indicating that Transmit buffer 2 is available, and the TIE2 bit in CANxIER is 1."> + <Enum name="RESET" start="0" description="Reset" /> + <Enum name="SET" start="1" description="Set" /> + </BitField> + <BitField start="10" size="1" name="TI3" description="Transmit Interrupt 3. This bit is set when the TBS3 bit in CANxSR goes from 0 to 1 (whenever a message out of TXB3 was successfully transmitted or aborted), indicating that Transmit buffer 3 is available, and the TIE3 bit in CANxIER is 1."> + <Enum name="RESET" start="0" description="Reset" /> + <Enum name="SET" start="1" description="Set" /> + </BitField> + <BitField start="11" size="5" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + <BitField start="16" size="5" name="ERRBIT4_0" description="Error Code Capture: when the CAN controller detects a bus error, the location of the error within the frame is captured in this field. The value reflects an internal state variable, and as a result is not very linear: 00011 = Start of Frame 00010 = ID28 ... ID21 00110 = ID20 ... ID18 00100 = SRTR Bit 00101 = IDE bit 00111 = ID17 ... 13 01111 = ID12 ... ID5 01110 = ID4 ... ID0 01100 = RTR Bit 01101 = Reserved Bit 1 01001 = Reserved Bit 0 01011 = Data Length Code 01010 = Data Field 01000 = CRC Sequence 11000 = CRC Delimiter 11001 = Acknowledge Slot 11011 = Acknowledge Delimiter 11010 = End of Frame 10010 = Intermission Whenever a bus error occurs, the corresponding bus error interrupt is forced, if enabled. At the same time, the current position of the Bit Stream Processor is captured into the Error Code Capture Register. The content within this register is fixed until the user software has read out its content once. From now on, the capture mechanism is activated again, i.e. reading the CANxICR enables another Bus Error Interrupt." /> + <BitField start="21" size="1" name="ERRDIR" description="When the CAN controller detects a bus error, the direction of the current bit is captured in this bit."> + <Enum name="ERROR_OCCURRED_DURIN" start="0" description="Error occurred during transmitting." /> + <Enum name="ERROR_OCCURRED_DURIN" start="1" description="Error occurred during receiving." /> + </BitField> + <BitField start="22" size="2" name="ERRC1_0" description="When the CAN controller detects a bus error, the type of error is captured in this field:"> + <Enum name="BIT_ERROR" start="0x0" description="Bit error" /> + <Enum name="FORM_ERROR" start="0x1" description="Form error" /> + <Enum name="STUFF_ERROR" start="0x2" description="Stuff error" /> + <Enum name="OTHER_ERROR" start="0x3" description="Other error" /> + </BitField> + <BitField start="24" size="8" name="ALCBIT" description="Each time arbitration is lost while trying to send on the CAN, the bit number within the frame is captured into this field. After the content of ALCBIT is read, the ALI bit is cleared and a new Arbitration Lost interrupt can occur. 00 = arbitration lost in the first bit (MS) of identifier ... 11 = arbitration lost in SRTS bit (RTR bit for standard frame messages) 12 = arbitration lost in IDE bit 13 = arbitration lost in 12th bit of identifier (extended frame only) ... 30 = arbitration lost in last bit of identifier (extended frame only) 31 = arbitration lost in RTR bit (extended frame only) On arbitration lost, the corresponding arbitration lost interrupt is forced, if enabled. At that time, the current bit position of the Bit Stream Processor is captured into the Arbitration Lost Capture Register. The content within this register is fixed until the user application has read out its contents once. From now on, the capture mechanism is activated again." /> + </Register> + <Register start="+0x010" size="4" name="IER" access="Read/Write" description="Interrupt Enable" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RIE" description="Receiver Interrupt Enable. When the Receive Buffer Status is 'full', the CAN Controller requests the respective interrupt." /> + <BitField start="1" size="1" name="TIE1" description="Transmit Interrupt Enable for Buffer1. When a message has been successfully transmitted out of TXB1 or Transmit Buffer 1 is accessible again (e.g. after an Abort Transmission command), the CAN Controller requests the respective interrupt." /> + <BitField start="2" size="1" name="EIE" description="Error Warning Interrupt Enable. If the Error or Bus Status change (see Status Register), the CAN Controller requests the respective interrupt." /> + <BitField start="3" size="1" name="DOIE" description="Data Overrun Interrupt Enable. If the Data Overrun Status bit is set (see Status Register), the CAN Controller requests the respective interrupt." /> + <BitField start="4" size="1" name="WUIE" description="Wake-Up Interrupt Enable. If the sleeping CAN controller wakes up, the respective interrupt is requested." /> + <BitField start="5" size="1" name="EPIE" description="Error Passive Interrupt Enable. If the error status of the CAN Controller changes from error active to error passive or vice versa, the respective interrupt is requested." /> + <BitField start="6" size="1" name="ALIE" description="Arbitration Lost Interrupt Enable. If the CAN Controller has lost arbitration, the respective interrupt is requested." /> + <BitField start="7" size="1" name="BEIE" description="Bus Error Interrupt Enable. If a bus error has been detected, the CAN Controller requests the respective interrupt." /> + <BitField start="8" size="1" name="IDIE" description="ID Ready Interrupt Enable. When a CAN identifier has been received, the CAN Controller requests the respective interrupt." /> + <BitField start="9" size="1" name="TIE2" description="Transmit Interrupt Enable for Buffer2. When a message has been successfully transmitted out of TXB2 or Transmit Buffer 2 is accessible again (e.g. after an Abort Transmission command), the CAN Controller requests the respective interrupt." /> + <BitField start="10" size="1" name="TIE3" description="Transmit Interrupt Enable for Buffer3. When a message has been successfully transmitted out of TXB3 or Transmit Buffer 3 is accessible again (e.g. after an Abort Transmission command), the CAN Controller requests the respective interrupt." /> + <BitField start="11" size="21" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x014" size="4" name="BTR" access="Read/Write" description="Bus Timing. Can only be written when RM in CANMOD is 1." reset_value="0x1C0000" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="10" name="BRP" description="Baud Rate Prescaler. The APB clock is divided by (this value plus one) to produce the CAN clock." /> + <BitField start="10" size="4" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="14" size="2" name="SJW" description="The Synchronization Jump Width is (this value plus one) CAN clocks." /> + <BitField start="16" size="4" name="TESG1" description="The delay from the nominal Sync point to the sample point is (this value plus one) CAN clocks." /> + <BitField start="20" size="3" name="TESG2" description="The delay from the sample point to the next nominal sync point is (this value plus one) CAN clocks. The nominal CAN bit time is (this value plus the value in TSEG1 plus 3) CAN clocks." /> + <BitField start="23" size="1" name="SAM" description="Sampling"> + <Enum name="THE_BUS_IS_SAMPLED_O" start="0" description="The bus is sampled once (recommended for high speed buses)" /> + <Enum name="THE_BUS_IS_SAMPLED_3" start="1" description="The bus is sampled 3 times (recommended for low to medium speed buses to filter spikes on the bus-line)" /> + </BitField> + <BitField start="24" size="8" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x018" size="4" name="EWL" access="Read/Write" description="Error Warning Limit. Can only be written when RM in CANMOD is 1." reset_value="0x60" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="EWL" description="During CAN operation, this value is compared to both the Tx and Rx Error Counters. If either of these counter matches this value, the Error Status (ES) bit in CANSR is set." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x01C" size="4" name="SR" access="ReadOnly" description="Status Register" reset_value="0x3C3C3C" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RBS_1" description="Receive Buffer Status. This bit is identical to the RBS bit in the CANxGSR." /> + <BitField start="1" size="1" name="DOS_1" description="Data Overrun Status. This bit is identical to the DOS bit in the CANxGSR." /> + <BitField start="2" size="1" name="TBS1_1" description="Transmit Buffer Status 1."> + <Enum name="LOCKED_SOFTWARE_CAN" start="0" description="Locked. Software cannot access the Tx Buffer 1 nor write to the corresponding CANxTFI, CANxTID, CANxTDA, and CANxTDB registers because a message is either waiting for transmission or is in transmitting process." /> + <Enum name="RELEASED_SOFTWARE_M" start="1" description="Released. Software may write a message into the Transmit Buffer 1 and its CANxTFI, CANxTID, CANxTDA, and CANxTDB registers." /> + </BitField> + <BitField start="3" size="1" name="TCS1_1" description="Transmission Complete Status."> + <Enum name="INCOMPLETE_THE_PREV" start="0" description="Incomplete. The previously requested transmission for Tx Buffer 1 is not complete." /> + <Enum name="COMPLETE_THE_PREVIO" start="1" description="Complete. The previously requested transmission for Tx Buffer 1 has been successfully completed." /> + </BitField> + <BitField start="4" size="1" name="RS_1" description="Receive Status. This bit is identical to the RS bit in the GSR." /> + <BitField start="5" size="1" name="TS1_1" description="Transmit Status 1."> + <Enum name="IDLE_THERE_IS_NO_TR" start="0" description="Idle. There is no transmission from Tx Buffer 1." /> + <Enum name="TRANSMIT_THE_CAN_CO" start="1" description="Transmit. The CAN Controller is transmitting a message from Tx Buffer 1." /> + </BitField> + <BitField start="6" size="1" name="ES_1" description="Error Status. This bit is identical to the ES bit in the CANxGSR." /> + <BitField start="7" size="1" name="BS_1" description="Bus Status. This bit is identical to the BS bit in the CANxGSR." /> + <BitField start="8" size="1" name="RBS_2" description="Receive Buffer Status. This bit is identical to the RBS bit in the CANxGSR." /> + <BitField start="9" size="1" name="DOS_2" description="Data Overrun Status. This bit is identical to the DOS bit in the CANxGSR." /> + <BitField start="10" size="1" name="TBS2_2" description="Transmit Buffer Status 2."> + <Enum name="LOCKED_SOFTWARE_CAN" start="0" description="Locked. Software cannot access the Tx Buffer 2 nor write to the corresponding CANxTFI, CANxTID, CANxTDA, and CANxTDB registers because a message is either waiting for transmission or is in transmitting process." /> + <Enum name="RELEASED_SOFTWARE_M" start="1" description="Released. Software may write a message into the Transmit Buffer 2 and its CANxTFI, CANxTID, CANxTDA, and CANxTDB registers." /> + </BitField> + <BitField start="11" size="1" name="TCS2_2" description="Transmission Complete Status."> + <Enum name="INCOMPLETE_THE_PREV" start="0" description="Incomplete. The previously requested transmission for Tx Buffer 2 is not complete." /> + <Enum name="COMPLETE_THE_PREVIO" start="1" description="Complete. The previously requested transmission for Tx Buffer 2 has been successfully completed." /> + </BitField> + <BitField start="12" size="1" name="RS_2" description="Receive Status. This bit is identical to the RS bit in the GSR." /> + <BitField start="13" size="1" name="TS2_2" description="Transmit Status 2."> + <Enum name="IDLE_THERE_IS_NO_TR" start="0" description="Idle. There is no transmission from Tx Buffer 2." /> + <Enum name="TRANSMIT_THE_CAN_CO" start="1" description="Transmit. The CAN Controller is transmitting a message from Tx Buffer 2." /> + </BitField> + <BitField start="14" size="1" name="ES_2" description="Error Status. This bit is identical to the ES bit in the CANxGSR." /> + <BitField start="15" size="1" name="BS_2" description="Bus Status. This bit is identical to the BS bit in the CANxGSR." /> + <BitField start="16" size="1" name="RBS_3" description="Receive Buffer Status. This bit is identical to the RBS bit in the CANxGSR." /> + <BitField start="17" size="1" name="DOS_3" description="Data Overrun Status. This bit is identical to the DOS bit in the CANxGSR." /> + <BitField start="18" size="1" name="TBS3_3" description="Transmit Buffer Status 3."> + <Enum name="LOCKED_SOFTWARE_CAN" start="0" description="Locked. Software cannot access the Tx Buffer 3 nor write to the corresponding CANxTFI, CANxTID, CANxTDA, and CANxTDB registers because a message is either waiting for transmission or is in transmitting process." /> + <Enum name="RELEASED_SOFTWARE_M" start="1" description="Released. Software may write a message into the Transmit Buffer 3 and its CANxTFI, CANxTID, CANxTDA, and CANxTDB registers." /> + </BitField> + <BitField start="19" size="1" name="TCS3_3" description="Transmission Complete Status."> + <Enum name="INCOMPLETE_THE_PREV" start="0" description="Incomplete. The previously requested transmission for Tx Buffer 3 is not complete." /> + <Enum name="COMPLETE_THE_PREVIO" start="1" description="Complete. The previously requested transmission for Tx Buffer 3 has been successfully completed." /> + </BitField> + <BitField start="20" size="1" name="RS_3" description="Receive Status. This bit is identical to the RS bit in the GSR." /> + <BitField start="21" size="1" name="TS3_3" description="Transmit Status 3."> + <Enum name="IDLE_THERE_IS_NO_TR" start="0" description="Idle. There is no transmission from Tx Buffer 3." /> + <Enum name="TRANSMIT_THE_CAN_CO" start="1" description="Transmit. The CAN Controller is transmitting a message from Tx Buffer 3." /> + </BitField> + <BitField start="22" size="1" name="ES_3" description="Error Status. This bit is identical to the ES bit in the CANxGSR." /> + <BitField start="23" size="1" name="BS_3" description="Bus Status. This bit is identical to the BS bit in the CANxGSR." /> + <BitField start="24" size="8" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x020" size="4" name="RFS" access="Read/Write" description="Receive frame status. Can only be written when RM in CANMOD is 1." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="10" name="IDINDEX" description="ID Index. If the BP bit (below) is 0, this value is the zero-based number of the Lookup Table RAM entry at which the Acceptance Filter matched the received Identifier. Disabled entries in the Standard tables are included in this numbering, but will not be matched. See Section 21.17 Examples of acceptance filter tables and ID index values on page 587 for examples of ID Index values." /> + <BitField start="10" size="1" name="BP" description="If this bit is 1, the current message was received in AF Bypass mode, and the ID Index field (above) is meaningless." /> + <BitField start="11" size="5" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + <BitField start="16" size="4" name="DLC" description="The field contains the Data Length Code (DLC) field of the current received message. When RTR = 0, this is related to the number of data bytes available in the CANRDA and CANRDB registers as follows: 0000-0111 = 0 to 7 bytes1000-1111 = 8 bytes With RTR = 1, this value indicates the number of data bytes requested to be sent back, with the same encoding." /> + <BitField start="20" size="10" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="30" size="1" name="RTR" description="This bit contains the Remote Transmission Request bit of the current received message. 0 indicates a Data Frame, in which (if DLC is non-zero) data can be read from the CANRDA and possibly the CANRDB registers. 1 indicates a Remote frame, in which case the DLC value identifies the number of data bytes requested to be sent using the same Identifier." /> + <BitField start="31" size="1" name="FF" description="A 0 in this bit indicates that the current received message included an 11-bit Identifier, while a 1 indicates a 29-bit Identifier. This affects the contents of the CANid register described below." /> + </Register> + <Register start="+0x024" size="4" name="RID" access="Read/Write" description="Received Identifier. Can only be written when RM in CANMOD is 1." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="11" name="ID" description="The 11-bit Identifier field of the current received message. In CAN 2.0A, these bits are called ID10-0, while in CAN 2.0B they're called ID29-18." /> + <BitField start="11" size="21" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x028" size="4" name="RDA" access="Read/Write" description="Received data bytes 1-4. Can only be written when RM in CANMOD is 1." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="DATA1" description="Data 1. If the DLC field in CANRFS >= 0001, this contains the first Data byte of the current received message." /> + <BitField start="8" size="8" name="DATA2" description="Data 2. If the DLC field in CANRFS >= 0010, this contains the first Data byte of the current received message." /> + <BitField start="16" size="8" name="DATA3" description="Data 3. If the DLC field in CANRFS >= 0011, this contains the first Data byte of the current received message." /> + <BitField start="24" size="8" name="DATA4" description="Data 4. If the DLC field in CANRFS >= 0100, this contains the first Data byte of the current received message." /> + </Register> + <Register start="+0x02C" size="4" name="RDB" access="Read/Write" description="Received data bytes 5-8. Can only be written when RM in CANMOD is 1." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="DATA5" description="Data 5. If the DLC field in CANRFS >= 0101, this contains the first Data byte of the current received message." /> + <BitField start="8" size="8" name="DATA6" description="Data 6. If the DLC field in CANRFS >= 0110, this contains the first Data byte of the current received message." /> + <BitField start="16" size="8" name="DATA7" description="Data 7. If the DLC field in CANRFS >= 0111, this contains the first Data byte of the current received message." /> + <BitField start="24" size="8" name="DATA8" description="Data 8. If the DLC field in CANRFS >= 1000, this contains the first Data byte of the current received message." /> + </Register> + <Register start="+0x030+0" size="4" name="TFI1" access="Read/Write" description="Transmit
frame info (Tx Buffer )" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="PRIO" description="If the TPM (Transmit Priority Mode) bit in the CANxMOD register is set to 1, enabled Tx Buffers contend for the right to send their messages based on this field. The buffer with the lowest TX Priority value wins the prioritization and is sent first." /> + <BitField start="8" size="8" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="16" size="4" name="DLC" description="Data Length Code. This value is sent in the DLC field of the next transmit message. In addition, if RTR = 0, this value controls the number of Data bytes sent in the next transmit message, from the CANxTDA and CANxTDB registers: 0000-0111 = 0-7 bytes 1xxx = 8 bytes" /> + <BitField start="20" size="10" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="30" size="1" name="RTR" description="This value is sent in the RTR bit of the next transmit message. If this bit is 0, the number of data bytes called out by the DLC field are sent from the CANxTDA and CANxTDB registers. If this bit is 1, a Remote Frame is sent, containing a request for that number of bytes." /> + <BitField start="31" size="1" name="FF" description="If this bit is 0, the next transmit message will be sent with an 11-bit Identifier (standard frame format), while if it's 1, the message will be sent with a 29-bit Identifier (extended frame format)." /> + </Register> + <Register start="+0x030+16" size="4" name="TFI2" access="Read/Write" description="Transmit
frame info (Tx Buffer )" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="PRIO" description="If the TPM (Transmit Priority Mode) bit in the CANxMOD register is set to 1, enabled Tx Buffers contend for the right to send their messages based on this field. The buffer with the lowest TX Priority value wins the prioritization and is sent first." /> + <BitField start="8" size="8" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="16" size="4" name="DLC" description="Data Length Code. This value is sent in the DLC field of the next transmit message. In addition, if RTR = 0, this value controls the number of Data bytes sent in the next transmit message, from the CANxTDA and CANxTDB registers: 0000-0111 = 0-7 bytes 1xxx = 8 bytes" /> + <BitField start="20" size="10" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="30" size="1" name="RTR" description="This value is sent in the RTR bit of the next transmit message. If this bit is 0, the number of data bytes called out by the DLC field are sent from the CANxTDA and CANxTDB registers. If this bit is 1, a Remote Frame is sent, containing a request for that number of bytes." /> + <BitField start="31" size="1" name="FF" description="If this bit is 0, the next transmit message will be sent with an 11-bit Identifier (standard frame format), while if it's 1, the message will be sent with a 29-bit Identifier (extended frame format)." /> + </Register> + <Register start="+0x030+32" size="4" name="TFI3" access="Read/Write" description="Transmit
frame info (Tx Buffer )" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="PRIO" description="If the TPM (Transmit Priority Mode) bit in the CANxMOD register is set to 1, enabled Tx Buffers contend for the right to send their messages based on this field. The buffer with the lowest TX Priority value wins the prioritization and is sent first." /> + <BitField start="8" size="8" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="16" size="4" name="DLC" description="Data Length Code. This value is sent in the DLC field of the next transmit message. In addition, if RTR = 0, this value controls the number of Data bytes sent in the next transmit message, from the CANxTDA and CANxTDB registers: 0000-0111 = 0-7 bytes 1xxx = 8 bytes" /> + <BitField start="20" size="10" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="30" size="1" name="RTR" description="This value is sent in the RTR bit of the next transmit message. If this bit is 0, the number of data bytes called out by the DLC field are sent from the CANxTDA and CANxTDB registers. If this bit is 1, a Remote Frame is sent, containing a request for that number of bytes." /> + <BitField start="31" size="1" name="FF" description="If this bit is 0, the next transmit message will be sent with an 11-bit Identifier (standard frame format), while if it's 1, the message will be sent with a 29-bit Identifier (extended frame format)." /> + </Register> + <Register start="+0x034+0" size="4" name="TID1" access="Read/Write" description="Transmit
Identifier (Tx Buffer)" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="11" name="ID" description="The 11-bit Identifier to be sent in the next transmit message." /> + <BitField start="11" size="21" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x034+16" size="4" name="TID2" access="Read/Write" description="Transmit
Identifier (Tx Buffer)" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="11" name="ID" description="The 11-bit Identifier to be sent in the next transmit message." /> + <BitField start="11" size="21" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x034+32" size="4" name="TID3" access="Read/Write" description="Transmit
Identifier (Tx Buffer)" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="11" name="ID" description="The 11-bit Identifier to be sent in the next transmit message." /> + <BitField start="11" size="21" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x038+0" size="4" name="TDA1" access="Read/Write" description="Transmit
data bytes 1-4 (Tx Buffer)" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="8" name="DATA1" description="Data 1. If RTR = 0 and DLC >= 0001 in the corresponding CANxTFI, this byte is sent as the first Data byte of the next transmit message." /> + <BitField start="8" size="8" name="DATA2" description="Data 2. If RTR = 0 and DLC >= 0010 in the corresponding CANxTFI, this byte is sent as the 2nd Data byte of the next transmit message." /> + <BitField start="16" size="8" name="DATA3" description="Data 3. If RTR = 0 and DLC >= 0011 in the corresponding CANxTFI, this byte is sent as the 3rd Data byte of the next transmit message." /> + <BitField start="24" size="8" name="DATA4" description="Data 4. If RTR = 0 and DLC >= 0100 in the corresponding CANxTFI, this byte is sent as the 4th Data byte of the next transmit message." /> + </Register> + <Register start="+0x038+16" size="4" name="TDA2" access="Read/Write" description="Transmit
data bytes 1-4 (Tx Buffer)" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="8" name="DATA1" description="Data 1. If RTR = 0 and DLC >= 0001 in the corresponding CANxTFI, this byte is sent as the first Data byte of the next transmit message." /> + <BitField start="8" size="8" name="DATA2" description="Data 2. If RTR = 0 and DLC >= 0010 in the corresponding CANxTFI, this byte is sent as the 2nd Data byte of the next transmit message." /> + <BitField start="16" size="8" name="DATA3" description="Data 3. If RTR = 0 and DLC >= 0011 in the corresponding CANxTFI, this byte is sent as the 3rd Data byte of the next transmit message." /> + <BitField start="24" size="8" name="DATA4" description="Data 4. If RTR = 0 and DLC >= 0100 in the corresponding CANxTFI, this byte is sent as the 4th Data byte of the next transmit message." /> + </Register> + <Register start="+0x038+32" size="4" name="TDA3" access="Read/Write" description="Transmit
data bytes 1-4 (Tx Buffer)" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="8" name="DATA1" description="Data 1. If RTR = 0 and DLC >= 0001 in the corresponding CANxTFI, this byte is sent as the first Data byte of the next transmit message." /> + <BitField start="8" size="8" name="DATA2" description="Data 2. If RTR = 0 and DLC >= 0010 in the corresponding CANxTFI, this byte is sent as the 2nd Data byte of the next transmit message." /> + <BitField start="16" size="8" name="DATA3" description="Data 3. If RTR = 0 and DLC >= 0011 in the corresponding CANxTFI, this byte is sent as the 3rd Data byte of the next transmit message." /> + <BitField start="24" size="8" name="DATA4" description="Data 4. If RTR = 0 and DLC >= 0100 in the corresponding CANxTFI, this byte is sent as the 4th Data byte of the next transmit message." /> + </Register> + <Register start="+0x03C+0" size="4" name="TDB1" access="Read/Write" description="Transmit
data bytes 5-8 (Tx Buffer )" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="8" name="DATA5" description="Data 5. If RTR = 0 and DLC >= 0101 in the corresponding CANTFI, this byte is sent as the 5th Data byte of the next transmit message." /> + <BitField start="8" size="8" name="DATA6" description="Data 6. If RTR = 0 and DLC >= 0110 in the corresponding CANTFI, this byte is sent as the 6th Data byte of the next transmit message." /> + <BitField start="16" size="8" name="DATA7" description="Data 7. If RTR = 0 and DLC >= 0111 in the corresponding CANTFI, this byte is sent as the 7th Data byte of the next transmit message." /> + <BitField start="24" size="8" name="DATA8" description="Data 8. If RTR = 0 and DLC >= 1000 in the corresponding CANTFI, this byte is sent as the 8th Data byte of the next transmit message." /> + </Register> + <Register start="+0x03C+16" size="4" name="TDB2" access="Read/Write" description="Transmit
data bytes 5-8 (Tx Buffer )" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="8" name="DATA5" description="Data 5. If RTR = 0 and DLC >= 0101 in the corresponding CANTFI, this byte is sent as the 5th Data byte of the next transmit message." /> + <BitField start="8" size="8" name="DATA6" description="Data 6. If RTR = 0 and DLC >= 0110 in the corresponding CANTFI, this byte is sent as the 6th Data byte of the next transmit message." /> + <BitField start="16" size="8" name="DATA7" description="Data 7. If RTR = 0 and DLC >= 0111 in the corresponding CANTFI, this byte is sent as the 7th Data byte of the next transmit message." /> + <BitField start="24" size="8" name="DATA8" description="Data 8. If RTR = 0 and DLC >= 1000 in the corresponding CANTFI, this byte is sent as the 8th Data byte of the next transmit message." /> + </Register> + <Register start="+0x03C+32" size="4" name="TDB3" access="Read/Write" description="Transmit
data bytes 5-8 (Tx Buffer )" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="8" name="DATA5" description="Data 5. If RTR = 0 and DLC >= 0101 in the corresponding CANTFI, this byte is sent as the 5th Data byte of the next transmit message." /> + <BitField start="8" size="8" name="DATA6" description="Data 6. If RTR = 0 and DLC >= 0110 in the corresponding CANTFI, this byte is sent as the 6th Data byte of the next transmit message." /> + <BitField start="16" size="8" name="DATA7" description="Data 7. If RTR = 0 and DLC >= 0111 in the corresponding CANTFI, this byte is sent as the 7th Data byte of the next transmit message." /> + <BitField start="24" size="8" name="DATA8" description="Data 8. If RTR = 0 and DLC >= 1000 in the corresponding CANTFI, this byte is sent as the 8th Data byte of the next transmit message." /> + </Register> + </RegisterGroup> + <RegisterGroup name="I2C1" start="0x4005C000" description="I2C bus interface"> + <Register start="+0x000" size="4" name="CONSET" access="Read/Write" description="I2C Control Set Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is set. Writing a zero has no effect on the corresponding bit in the I2C control register." reset_value="0x00" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + <BitField start="2" size="1" name="AA" description="Assert acknowledge flag." /> + <BitField start="3" size="1" name="SI" description="I2C interrupt flag." /> + <BitField start="4" size="1" name="STO" description="STOP flag." /> + <BitField start="5" size="1" name="STA" description="START flag." /> + <BitField start="6" size="1" name="I2EN" description="I2C interface enable." /> + <BitField start="7" size="25" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x004" size="4" name="STAT" access="ReadOnly" description="I2C Status Register. During I2C operation, this register provides detailed status codes that allow software to determine the next action needed." reset_value="0xF8" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="RESERVED" description="These bits are unused and are always 0." /> + <BitField start="3" size="5" name="Status" description="These bits give the actual status information about the I 2C interface." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x008" size="4" name="DAT" access="Read/Write" description="I2C Data Register. During master or slave transmit mode, data to be transmitted is written to this register. During master or slave receive mode, data that has been received may be read from this register." reset_value="0x00" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="Data" description="This register holds data values that have been received or are to be transmitted." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x00C" size="4" name="ADR0" access="Read/Write" description="I2C Slave Address Register 0. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="GC" description="General Call enable bit." /> + <BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x010" size="4" name="SCLH" access="Read/Write" description="SCH Duty Cycle Register High Half Word. Determines the high time of the I2C clock." reset_value="0x04" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="16" name="SCLH" description="Count for SCL HIGH time period selection." /> + <BitField start="16" size="16" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x014" size="4" name="SCLL" access="Read/Write" description="SCL Duty Cycle Register Low Half Word. Determines the low time of the I2C clock. SCLL and SCLH together determine the clock frequency generated by an I2C master and certain times used in slave mode." reset_value="0x04" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="16" name="SCLL" description="Count for SCL low time period selection." /> + <BitField start="16" size="16" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x018" size="4" name="CONCLR" access="WriteOnly" description="I2C Control Clear Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is cleared. Writing a zero has no effect on the corresponding bit in the I2C control register." reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="2" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + <BitField start="2" size="1" name="AAC" description="Assert acknowledge Clear bit." /> + <BitField start="3" size="1" name="SIC" description="I2C interrupt Clear bit." /> + <BitField start="4" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + <BitField start="5" size="1" name="STAC" description="START flag Clear bit." /> + <BitField start="6" size="1" name="I2ENC" description="I2C interface Disable bit." /> + <BitField start="7" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x01C" size="4" name="MMCTRL" access="Read/Write" description="Monitor mode control register." reset_value="0x00" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="MM_ENA" description="Monitor mode enable."> + <Enum name="MONITOR_MODE_DISABLE" start="0" description="Monitor mode disabled." /> + <Enum name="THE_I_2C_MODULE_WILL" start="1" description="The I 2C module will enter monitor mode. In this mode the SDA output will be forced high. This will prevent the I2C module from outputting data of any kind (including ACK) onto the I2C data bus. Depending on the state of the ENA_SCL bit, the output may be also forced high, preventing the module from having control over the I2C clock line." /> + </BitField> + <BitField start="1" size="1" name="ENA_SCL" description="SCL output enable."> + <Enum name="WHEN_THIS_BIT_IS_CLE" start="0" description="When this bit is cleared to 0, the SCL output will be forced high when the module is in monitor mode. As described above, this will prevent the module from having any control over the I2C clock line." /> + <Enum name="WHEN_THIS_BIT_IS_SET" start="1" description="When this bit is set, the I2C module may exercise the same control over the clock line that it would in normal operation. This means that, acting as a slave peripheral, the I2C module can stretch the clock line (hold it low) until it has had time to respond to an I2C interrupt.[1]" /> + </BitField> + <BitField start="2" size="1" name="MATCH_ALL" description="Select interrupt register match."> + <Enum name="WHEN_THIS_BIT_IS_CLE" start="0" description="When this bit is cleared, an interrupt will only be generated when a match occurs to one of the (up-to) four address registers described above. That is, the module will respond as a normal slave as far as address-recognition is concerned." /> + <Enum name="WHEN_THIS_BIT_IS_SET" start="1" description="When this bit is set to 1 and the I2C is in monitor mode, an interrupt will be generated on ANY address received. This will enable the part to monitor all traffic on the bus." /> + </BitField> + <BitField start="3" size="29" name="RESERVED" description="Reserved. The value read from reserved bits is not defined." /> + </Register> + <Register start="+0x020+0" size="4" name="ADR1" access="Read/Write" description="I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="GC" description="General Call enable bit." /> + <BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x020+4" size="4" name="ADR2" access="Read/Write" description="I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="GC" description="General Call enable bit." /> + <BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x020+8" size="4" name="ADR3" access="Read/Write" description="I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="GC" description="General Call enable bit." /> + <BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x02C" size="4" name="DATA_BUFFER" access="ReadOnly" description="Data buffer register. The contents of the 8 MSBs of the DAT shift register will be transferred to the DATA_BUFFER automatically after every nine bits (8 bits of data plus ACK or NACK) has been received on the bus." reset_value="0x00" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="Data" description="This register holds contents of the 8 MSBs of the DAT shift register." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x030+0" size="4" name="MASK[0]" access="Read/Write" description="I2C Slave address mask register" reset_value="0x00" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." /> + <BitField start="1" size="7" name="MASK" description="Mask bits." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x030+4" size="4" name="MASK[1]" access="Read/Write" description="I2C Slave address mask register" reset_value="0x00" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." /> + <BitField start="1" size="7" name="MASK" description="Mask bits." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x030+8" size="4" name="MASK[2]" access="Read/Write" description="I2C Slave address mask register" reset_value="0x00" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." /> + <BitField start="1" size="7" name="MASK" description="Mask bits." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x030+12" size="4" name="MASK[3]" access="Read/Write" description="I2C Slave address mask register" reset_value="0x00" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." /> + <BitField start="1" size="7" name="MASK" description="Mask bits." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + </RegisterGroup> + <RegisterGroup name="SSP0" start="0x40088000" description="SSP controller"> + <Register start="+0x000" size="4" name="CR0" access="Read/Write" description="Control Register 0. Selects the serial clock rate, bus type, and data size." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="4" name="DSS" description="Data Size Select. This field controls the number of bits transferred in each frame. Values 0000-0010 are not supported and should not be used."> + <Enum name="4_BIT_TRANSFER" start="0x3" description="4-bit transfer" /> + <Enum name="5_BIT_TRANSFER" start="0x4" description="5-bit transfer" /> + <Enum name="6_BIT_TRANSFER" start="0x5" description="6-bit transfer" /> + <Enum name="7_BIT_TRANSFER" start="0x6" description="7-bit transfer" /> + <Enum name="8_BIT_TRANSFER" start="0x7" description="8-bit transfer" /> + <Enum name="9_BIT_TRANSFER" start="0x8" description="9-bit transfer" /> + <Enum name="10_BIT_TRANSFER" start="0x9" description="10-bit transfer" /> + <Enum name="11_BIT_TRANSFER" start="0xA" description="11-bit transfer" /> + <Enum name="12_BIT_TRANSFER" start="0xB" description="12-bit transfer" /> + <Enum name="13_BIT_TRANSFER" start="0xC" description="13-bit transfer" /> + <Enum name="14_BIT_TRANSFER" start="0xD" description="14-bit transfer" /> + <Enum name="15_BIT_TRANSFER" start="0xE" description="15-bit transfer" /> + <Enum name="16_BIT_TRANSFER" start="0xF" description="16-bit transfer" /> + </BitField> + <BitField start="4" size="2" name="FRF" description="Frame Format."> + <Enum name="SPI" start="0x0" description="SPI" /> + <Enum name="TI" start="0x1" description="TI" /> + <Enum name="MICROWIRE" start="0x2" description="Microwire" /> + <Enum name="THIS_COMBINATION_IS_" start="0x3" description="This combination is not supported and should not be used." /> + </BitField> + <BitField start="6" size="1" name="CPOL" description="Clock Out Polarity. This bit is only used in SPI mode."> + <Enum name="BUS_LOW" start="0" description="SSP controller maintains the bus clock low between frames." /> + <Enum name="BUS_HIGH" start="1" description="SSP controller maintains the bus clock high between frames." /> + </BitField> + <BitField start="7" size="1" name="CPHA" description="Clock Out Phase. This bit is only used in SPI mode."> + <Enum name="FIRST_CLOCK" start="0" description="SSP controller captures serial data on the first clock transition of the frame, that is, the transition away from the inter-frame state of the clock line." /> + <Enum name="SECOND_CLOCK" start="1" description="SSP controller captures serial data on the second clock transition of the frame, that is, the transition back to the inter-frame state of the clock line." /> + </BitField> + <BitField start="8" size="8" name="SCR" description="Serial Clock Rate. The number of prescaler-output clocks per bit on the bus, minus one. Given that CPSDVSR is the prescale divider, and the APB clock PCLK clocks the prescaler, the bit frequency is PCLK / (CPSDVSR X [SCR+1])." /> + <BitField start="16" size="16" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x004" size="4" name="CR1" access="Read/Write" description="Control Register 1. Selects master/slave and other modes." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="LBM" description="Loop Back Mode."> + <Enum name="NORMAL" start="0" description="During normal operation." /> + <Enum name="OUPTU" start="1" description="Serial input is taken from the serial output (MOSI or MISO) rather than the serial input pin (MISO or MOSI respectively)." /> + </BitField> + <BitField start="1" size="1" name="SSE" description="SSP Enable."> + <Enum name="DISABLED" start="0" description="The SSP controller is disabled." /> + <Enum name="ENABLED" start="1" description="The SSP controller will interact with other devices on the serial bus. Software should write the appropriate control information to the other SSP registers and interrupt controller registers, before setting this bit." /> + </BitField> + <BitField start="2" size="1" name="MS" description="Master/Slave Mode.This bit can only be written when the SSE bit is 0."> + <Enum name="MASTER" start="0" description="The SSP controller acts as a master on the bus, driving the SCLK, MOSI, and SSEL lines and receiving the MISO line." /> + <Enum name="SLAVE" start="1" description="The SSP controller acts as a slave on the bus, driving MISO line and receiving SCLK, MOSI, and SSEL lines." /> + </BitField> + <BitField start="3" size="1" name="SOD" description="Slave Output Disable. This bit is relevant only in slave mode (MS = 1). If it is 1, this blocks this SSP controller from driving the transmit data line (MISO)." /> + <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x008" size="4" name="DR" access="None" description="Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="16" name="DATA" description="Write: software can write data to be sent in a future frame to this register whenever the TNF bit in the Status register is 1, indicating that the Tx FIFO is not full. If the Tx FIFO was previously empty and the SSP controller is not busy on the bus, transmission of the data will begin immediately. Otherwise the data written to this register will be sent as soon as all previous data has been sent (and received). If the data length is less than 16 bits, software must right-justify the data written to this register. Read: software can read data from this register whenever the RNE bit in the Status register is 1, indicating that the Rx FIFO is not empty. When software reads this register, the SSP controller returns data from the least recent frame in the Rx FIFO. If the data length is less than 16 bits, the data is right-justified in this field with higher order bits filled with 0s." /> + <BitField start="16" size="16" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x00C" size="4" name="SR" access="ReadOnly" description="Status Register" reset_value="0x00000003" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="TFE" description="Transmit FIFO Empty. This bit is 1 is the Transmit FIFO is empty, 0 if not." /> + <BitField start="1" size="1" name="TNF" description="Transmit FIFO Not Full. This bit is 0 if the Tx FIFO is full, 1 if not." /> + <BitField start="2" size="1" name="RNE" description="Receive FIFO Not Empty. This bit is 0 if the Receive FIFO is empty, 1 if not." /> + <BitField start="3" size="1" name="RFF" description="Receive FIFO Full. This bit is 1 if the Receive FIFO is full, 0 if not." /> + <BitField start="4" size="1" name="BSY" description="Busy. This bit is 0 if the SSPn controller is idle, or 1 if it is currently sending/receiving a frame and/or the Tx FIFO is not empty." /> + <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x010" size="4" name="CPSR" access="Read/Write" description="Clock Prescale Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="CPSDVSR" description="This even value between 2 and 254, by which PCLK is divided to yield the prescaler output clock. Bit 0 always reads as 0." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x014" size="4" name="IMSC" access="Read/Write" description="Interrupt Mask Set and Clear Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RORIM" description="Software should set this bit to enable interrupt when a Receive Overrun occurs, that is, when the Rx FIFO is full and another frame is completely received. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs." /> + <BitField start="1" size="1" name="RTIM" description="Software should set this bit to enable interrupt when a Receive Time-out condition occurs. A Receive Time-out occurs when the Rx FIFO is not empty, and no has not been read for a time-out period. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1])." /> + <BitField start="2" size="1" name="RXIM" description="Software should set this bit to enable interrupt when the Rx FIFO is at least half full." /> + <BitField start="3" size="1" name="TXIM" description="Software should set this bit to enable interrupt when the Tx FIFO is at least half empty." /> + <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x018" size="4" name="RIS" access="ReadOnly" description="Raw Interrupt Status Register" reset_value="0x00000008" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RORRIS" description="This bit is 1 if another frame was completely received while the RxFIFO was full. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs." /> + <BitField start="1" size="1" name="RTRIS" description="This bit is 1 if the Rx FIFO is not empty, and has not been read for a time-out period. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1])." /> + <BitField start="2" size="1" name="RXRIS" description="This bit is 1 if the Rx FIFO is at least half full." /> + <BitField start="3" size="1" name="TXRIS" description="This bit is 1 if the Tx FIFO is at least half empty." /> + <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x01C" size="4" name="MIS" access="ReadOnly" description="Masked Interrupt Status Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RORMIS" description="This bit is 1 if another frame was completely received while the RxFIFO was full, and this interrupt is enabled." /> + <BitField start="1" size="1" name="RTMIS" description="This bit is 1 if the Rx FIFO is not empty, has not been read for a time-out period, and this interrupt is enabled. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1])." /> + <BitField start="2" size="1" name="RXMIS" description="This bit is 1 if the Rx FIFO is at least half full, and this interrupt is enabled." /> + <BitField start="3" size="1" name="TXMIS" description="This bit is 1 if the Tx FIFO is at least half empty, and this interrupt is enabled." /> + <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x020" size="4" name="ICR" access="WriteOnly" description="SSPICR Interrupt Clear Register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="RORIC" description="Writing a 1 to this bit clears the frame was received when RxFIFO was full interrupt." /> + <BitField start="1" size="1" name="RTIC" description="Writing a 1 to this bit clears the Rx FIFO was not empty and has not been read for a time-out period interrupt. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR / [SCR+1])." /> + <BitField start="2" size="30" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x024" size="4" name="DMACR" access="Read/Write" description="SSP0 DMA control register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RXDMAE" description="Receive DMA Enable. When this bit is set to one 1, DMA for the receive FIFO is enabled, otherwise receive DMA is disabled." /> + <BitField start="1" size="1" name="TXDMAE" description="Transmit DMA Enable. When this bit is set to one 1, DMA for the transmit FIFO is enabled, otherwise transmit DMA is disabled" /> + <BitField start="2" size="30" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + </RegisterGroup> + <RegisterGroup name="DAC" start="0x4008C000" description=" Digital-to-Analog Converter (DAC) "> + <Register start="+0x000" size="4" name="CR" access="Read/Write" description="D/A Converter Register. This register contains the digital value to be converted to analog and a power control bit." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="6" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="6" size="10" name="VALUE" description="After the selected settling time after this field is written with a new VALUE, the voltage on the DAC_OUT pin (with respect to VSSA) is VALUE x ((VREFP - V REFN)/1024) + VREFN." /> + <BitField start="16" size="1" name="BIAS" description="Settling time The settling times noted in the description of the BIAS bit are valid for a capacitance load on the DAC_OUT pin not exceeding 100 pF. A load impedance value greater than that value will cause settling time longer than the specified time. One or more graphs of load impedance vs. settling time will be included in the final data sheet."> + <Enum name="FAST" start="0" description="The settling time of the DAC is 1 us max, and the maximum current is 700 uA. This allows a maximum update rate of 1 MHz." /> + <Enum name="SLOW" start="1" description="The settling time of the DAC is 2.5 us and the maximum current is 350 uA. This allows a maximum update rate of 400 kHz." /> + </BitField> + <BitField start="17" size="15" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x004" size="4" name="CTRL" access="Read/Write" description="DAC Control register. This register controls DMA and timer operation." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="INT_DMA_REQ" description="DMA interrupt request"> + <Enum name="CLEAR_ON_ANY_WRITE_T" start="0" description="Clear on any write to the DACR register." /> + <Enum name="SET_BY_HARDWARE_WHEN" start="1" description="Set by hardware when the timer times out." /> + </BitField> + <BitField start="1" size="1" name="DBLBUF_ENA" description="Double buffering"> + <Enum name="DISABLE" start="0" description="Disable" /> + <Enum name="ENABLE_WHEN_THIS_BI" start="1" description="Enable. When this bit and the CNT_ENA bit are both set, the double-buffering feature in the DACR register will be enabled. Writes to the DACR register are written to a pre-buffer and then transferred to the DACR on the next time-out of the counter." /> + </BitField> + <BitField start="2" size="1" name="CNT_ENA" description="Time-out counter operation"> + <Enum name="DISABLE" start="0" description="Disable" /> + <Enum name="ENABLE" start="1" description="Enable" /> + </BitField> + <BitField start="3" size="1" name="DMA_ENA" description="DMA access"> + <Enum name="DISABLE" start="0" description="Disable" /> + <Enum name="ENABLE_DMA_BURST_RE" start="1" description="Enable. DMA Burst Request Input 7 is enabled for the DAC (see Table 672)." /> + </BitField> + <BitField start="4" size="28" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x008" size="4" name="CNTVAL" access="Read/Write" description="DAC Counter Value register. This register contains the reload value for the DAC DMA/Interrupt timer." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="16" name="VALUE" description="16-bit reload value for the DAC interrupt/DMA timer." /> + <BitField start="16" size="16" name="RESERVED" description="Reserved" /> + </Register> + </RegisterGroup> + <RegisterGroup name="TIMER2" start="0x40090000" description="Timer0/1/2/3 "> + <Register start="+0x000" size="4" name="IR" access="Read/Write" description="Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="MR0INT" description="Interrupt flag for match channel 0." /> + <BitField start="1" size="1" name="MR1INT" description="Interrupt flag for match channel 1." /> + <BitField start="2" size="1" name="MR2INT" description="Interrupt flag for match channel 2." /> + <BitField start="3" size="1" name="MR3INT" description="Interrupt flag for match channel 3." /> + <BitField start="4" size="1" name="CR0INT" description="Interrupt flag for capture channel 0 event." /> + <BitField start="5" size="1" name="CR1INT" description="Interrupt flag for capture channel 1 event." /> + <BitField start="6" size="26" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x004" size="4" name="TCR" access="Read/Write" description="Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="CEN" description="When one, the Timer Counter and Prescale Counter are enabled for counting. When zero, the counters are disabled." /> + <BitField start="1" size="1" name="CRST" description="When one, the Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero." /> + <BitField start="2" size="30" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x008" size="4" name="TC" access="Read/Write" description="Timer Counter. The 32 bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="TC" description="Timer counter value." /> + </Register> + <Register start="+0x00C" size="4" name="PR" access="Read/Write" description="Prescale Register. When the Prescale Counter (PC) is equal to this value, the next clock increments the TC and clears the PC." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="PM" description="Prescale counter maximum value." /> + </Register> + <Register start="+0x010" size="4" name="PC" access="Read/Write" description="Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="PC" description="Prescale counter value." /> + </Register> + <Register start="+0x014" size="4" name="MCR" access="Read/Write" description="Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="MR0I" description="Interrupt on MR0"> + <Enum name="INTERRUPT_IS_GENERAT" start="1" description="Interrupt is generated when MR0 matches the value in the TC." /> + <Enum name="INTERRUPT_IS_DISABLE" start="0" description="Interrupt is disabled" /> + </BitField> + <BitField start="1" size="1" name="MR0R" description="Reset on MR0"> + <Enum name="TC_WILL_BE_RESET_IF_" start="1" description="TC will be reset if MR0 matches it." /> + <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." /> + </BitField> + <BitField start="2" size="1" name="MR0S" description="Stop on MR0"> + <Enum name="TC_AND_PC_WILL_BE_ST" start="1" description="TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC." /> + <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." /> + </BitField> + <BitField start="3" size="1" name="MR1I" description="Interrupt on MR1"> + <Enum name="INTERRUPT_IS_GENERAT" start="1" description="Interrupt is generated when MR1 matches the value in the TC." /> + <Enum name="INTERRUPT_IS_DISABLE" start="0" description="Interrupt is disabled." /> + </BitField> + <BitField start="4" size="1" name="MR1R" description="Reset on MR1"> + <Enum name="TC_WILL_BE_RESET_IF_" start="1" description="TC will be reset if MR1 matches it." /> + <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." /> + </BitField> + <BitField start="5" size="1" name="MR1S" description="Stop on MR1"> + <Enum name="TC_AND_PC_WILL_BE_ST" start="1" description="TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC." /> + <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." /> + </BitField> + <BitField start="6" size="1" name="MR2I" description="Interrupt on MR2"> + <Enum name="INTERRUPT_IS_GENERAT" start="1" description="Interrupt is generated when MR2 matches the value in the TC." /> + <Enum name="INTERRUPT_IS_DISABLE" start="0" description="Interrupt is disabled" /> + </BitField> + <BitField start="7" size="1" name="MR2R" description="Reset on MR2"> + <Enum name="TC_WILL_BE_RESET_IF_" start="1" description="TC will be reset if MR2 matches it." /> + <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." /> + </BitField> + <BitField start="8" size="1" name="MR2S" description="Stop on MR2."> + <Enum name="TC_AND_PC_WILL_BE_ST" start="1" description="TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC" /> + <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." /> + </BitField> + <BitField start="9" size="1" name="MR3I" description="Interrupt on MR3"> + <Enum name="INTERRUPT_IS_GENERAT" start="1" description="Interrupt is generated when MR3 matches the value in the TC." /> + <Enum name="THIS_INTERRUPT_IS_DI" start="0" description="This interrupt is disabled" /> + </BitField> + <BitField start="10" size="1" name="MR3R" description="Reset on MR3"> + <Enum name="TC_WILL_BE_RESET_IF_" start="1" description="TC will be reset if MR3 matches it." /> + <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." /> + </BitField> + <BitField start="11" size="1" name="MR3S" description="Stop on MR3"> + <Enum name="TC_AND_PC_WILL_BE_ST" start="1" description="TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC." /> + <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." /> + </BitField> + <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x018+0" size="4" name="MR[0]" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="MATCH" description="Timer counter match value." /> + </Register> + <Register start="+0x018+4" size="4" name="MR[1]" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="MATCH" description="Timer counter match value." /> + </Register> + <Register start="+0x018+8" size="4" name="MR[2]" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="MATCH" description="Timer counter match value." /> + </Register> + <Register start="+0x018+12" size="4" name="MR[3]" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="MATCH" description="Timer counter match value." /> + </Register> + <Register start="+0x028" size="4" name="CCR" access="Read/Write" description="Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="CAP0RE" description="Capture on CAPn.0 rising edge"> + <Enum name="ENABLE" start="1" description="A sequence of 0 then 1 on CAPn.0 will cause CR0 to be loaded with the contents of TC." /> + <Enum name="DISABLE" start="0" description="This feature is disabled." /> + </BitField> + <BitField start="1" size="1" name="CAP0FE" description="Capture on CAPn.0 falling edge"> + <Enum name="ENABLE" start="1" description="A sequence of 1 then 0 on CAPn.0 will cause CR0 to be loaded with the contents of TC." /> + <Enum name="DISABLE" start="0" description="This feature is disabled." /> + </BitField> + <BitField start="2" size="1" name="CAP0I" description="Interrupt on CAPn.0 event"> + <Enum name="ENABLE" start="1" description="A CR0 load due to a CAPn.0 event will generate an interrupt." /> + <Enum name="DISABLE" start="0" description="This feature is disabled." /> + </BitField> + <BitField start="3" size="1" name="CAP1RE" description="Capture on CAPn.1 rising edge"> + <Enum name="ENABLE" start="1" description="A sequence of 0 then 1 on CAPn.1 will cause CR1 to be loaded with the contents of TC." /> + <Enum name="DISABLE" start="0" description="This feature is disabled." /> + </BitField> + <BitField start="4" size="1" name="CAP1FE" description="Capture on CAPn.1 falling edge"> + <Enum name="ENABLE" start="1" description="A sequence of 1 then 0 on CAPn.1 will cause CR1 to be loaded with the contents of TC." /> + <Enum name="DISABLE" start="0" description="This feature is disabled." /> + </BitField> + <BitField start="5" size="1" name="CAP1I" description="Interrupt on CAPn.1 event"> + <Enum name="ENABLE" start="1" description="A CR1 load due to a CAPn.1 event will generate an interrupt." /> + <Enum name="DISABLE" start="0" description="This feature is disabled." /> + </BitField> + <BitField start="6" size="26" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x02C+0" size="4" name="CR[0]" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CAP" description="Timer counter capture value." /> + </Register> + <Register start="+0x02C+4" size="4" name="CR[1]" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CAP" description="Timer counter capture value." /> + </Register> + <Register start="+0x03C" size="4" name="EMR" access="Read/Write" description="External Match Register. The EMR controls the external match pins." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="EM0" description="External Match 0. When a match occurs between the TC and MR0, this bit can either toggle, go low, go high, or do nothing, depending on bits 5:4 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." /> + <BitField start="1" size="1" name="EM1" description="External Match 1. When a match occurs between the TC and MR1, this bit can either toggle, go low, go high, or do nothing, depending on bits 7:6 of this register. This bit can be driven onto a MATn.1 pin, in a positive-logic manner (0 = low, 1 = high)." /> + <BitField start="2" size="1" name="EM2" description="External Match 2. When a match occurs between the TC and MR2, this bit can either toggle, go low, go high, or do nothing, depending on bits 9:8 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." /> + <BitField start="3" size="1" name="EM3" description="External Match 3. When a match occurs between the TC and MR3, this bit can either toggle, go low, go high, or do nothing, depending on bits 11:10 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." /> + <BitField start="4" size="2" name="EMC0" description="External Match Control 0. Determines the functionality of External Match 0."> + <Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." /> + <Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." /> + <Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." /> + <Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." /> + </BitField> + <BitField start="6" size="2" name="EMC1" description="External Match Control 1. Determines the functionality of External Match 1."> + <Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." /> + <Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." /> + <Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." /> + <Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." /> + </BitField> + <BitField start="8" size="2" name="EMC2" description="External Match Control 2. Determines the functionality of External Match 2."> + <Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." /> + <Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." /> + <Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." /> + <Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." /> + </BitField> + <BitField start="10" size="2" name="EMC3" description="External Match Control 3. Determines the functionality of External Match 3."> + <Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." /> + <Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." /> + <Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." /> + <Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." /> + </BitField> + <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x070" size="4" name="CTCR" access="Read/Write" description="Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="CTMODE" description="Counter/Timer Mode This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale Register."> + <Enum name="TIMER_MODE_EVERY_RI" start="0x0" description="Timer Mode: every rising PCLK edge" /> + <Enum name="RISING" start="0x1" description="Counter Mode: TC is incremented on rising edges on the CAP input selected by bits 3:2." /> + <Enum name="FALLING" start="0x2" description="Counter Mode: TC is incremented on falling edges on the CAP input selected by bits 3:2." /> + <Enum name="DUALEDGE" start="0x3" description="Counter Mode: TC is incremented on both edges on the CAP input selected by bits 3:2." /> + </BitField> + <BitField start="2" size="2" name="CINSEL" description="Count Input Select When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the TnCTCR, the 3 bits for that input in the Capture Control Register (TnCCR) must be programmed as 000. However, capture and/or interrupt can be selected for the other 3 CAPn inputs in the same timer."> + <Enum name="CAPN_0_FOR_TIMERN" start="0x0" description="CAPn.0 for TIMERn" /> + <Enum name="CAPN_1_FOR_TIMERN" start="0x1" description="CAPn.1 for TIMERn" /> + </BitField> + <BitField start="4" size="28" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + </RegisterGroup> + <RegisterGroup name="TIMER3" start="0x40094000" description="Timer0/1/2/3 "> + <Register start="+0x000" size="4" name="IR" access="Read/Write" description="Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="MR0INT" description="Interrupt flag for match channel 0." /> + <BitField start="1" size="1" name="MR1INT" description="Interrupt flag for match channel 1." /> + <BitField start="2" size="1" name="MR2INT" description="Interrupt flag for match channel 2." /> + <BitField start="3" size="1" name="MR3INT" description="Interrupt flag for match channel 3." /> + <BitField start="4" size="1" name="CR0INT" description="Interrupt flag for capture channel 0 event." /> + <BitField start="5" size="1" name="CR1INT" description="Interrupt flag for capture channel 1 event." /> + <BitField start="6" size="26" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x004" size="4" name="TCR" access="Read/Write" description="Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="CEN" description="When one, the Timer Counter and Prescale Counter are enabled for counting. When zero, the counters are disabled." /> + <BitField start="1" size="1" name="CRST" description="When one, the Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero." /> + <BitField start="2" size="30" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x008" size="4" name="TC" access="Read/Write" description="Timer Counter. The 32 bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="TC" description="Timer counter value." /> + </Register> + <Register start="+0x00C" size="4" name="PR" access="Read/Write" description="Prescale Register. When the Prescale Counter (PC) is equal to this value, the next clock increments the TC and clears the PC." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="PM" description="Prescale counter maximum value." /> + </Register> + <Register start="+0x010" size="4" name="PC" access="Read/Write" description="Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="PC" description="Prescale counter value." /> + </Register> + <Register start="+0x014" size="4" name="MCR" access="Read/Write" description="Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="MR0I" description="Interrupt on MR0"> + <Enum name="INTERRUPT_IS_GENERAT" start="1" description="Interrupt is generated when MR0 matches the value in the TC." /> + <Enum name="INTERRUPT_IS_DISABLE" start="0" description="Interrupt is disabled" /> + </BitField> + <BitField start="1" size="1" name="MR0R" description="Reset on MR0"> + <Enum name="TC_WILL_BE_RESET_IF_" start="1" description="TC will be reset if MR0 matches it." /> + <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." /> + </BitField> + <BitField start="2" size="1" name="MR0S" description="Stop on MR0"> + <Enum name="TC_AND_PC_WILL_BE_ST" start="1" description="TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC." /> + <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." /> + </BitField> + <BitField start="3" size="1" name="MR1I" description="Interrupt on MR1"> + <Enum name="INTERRUPT_IS_GENERAT" start="1" description="Interrupt is generated when MR1 matches the value in the TC." /> + <Enum name="INTERRUPT_IS_DISABLE" start="0" description="Interrupt is disabled." /> + </BitField> + <BitField start="4" size="1" name="MR1R" description="Reset on MR1"> + <Enum name="TC_WILL_BE_RESET_IF_" start="1" description="TC will be reset if MR1 matches it." /> + <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." /> + </BitField> + <BitField start="5" size="1" name="MR1S" description="Stop on MR1"> + <Enum name="TC_AND_PC_WILL_BE_ST" start="1" description="TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC." /> + <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." /> + </BitField> + <BitField start="6" size="1" name="MR2I" description="Interrupt on MR2"> + <Enum name="INTERRUPT_IS_GENERAT" start="1" description="Interrupt is generated when MR2 matches the value in the TC." /> + <Enum name="INTERRUPT_IS_DISABLE" start="0" description="Interrupt is disabled" /> + </BitField> + <BitField start="7" size="1" name="MR2R" description="Reset on MR2"> + <Enum name="TC_WILL_BE_RESET_IF_" start="1" description="TC will be reset if MR2 matches it." /> + <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." /> + </BitField> + <BitField start="8" size="1" name="MR2S" description="Stop on MR2."> + <Enum name="TC_AND_PC_WILL_BE_ST" start="1" description="TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC" /> + <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." /> + </BitField> + <BitField start="9" size="1" name="MR3I" description="Interrupt on MR3"> + <Enum name="INTERRUPT_IS_GENERAT" start="1" description="Interrupt is generated when MR3 matches the value in the TC." /> + <Enum name="THIS_INTERRUPT_IS_DI" start="0" description="This interrupt is disabled" /> + </BitField> + <BitField start="10" size="1" name="MR3R" description="Reset on MR3"> + <Enum name="TC_WILL_BE_RESET_IF_" start="1" description="TC will be reset if MR3 matches it." /> + <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." /> + </BitField> + <BitField start="11" size="1" name="MR3S" description="Stop on MR3"> + <Enum name="TC_AND_PC_WILL_BE_ST" start="1" description="TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC." /> + <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." /> + </BitField> + <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x018+0" size="4" name="MR[0]" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="MATCH" description="Timer counter match value." /> + </Register> + <Register start="+0x018+4" size="4" name="MR[1]" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="MATCH" description="Timer counter match value." /> + </Register> + <Register start="+0x018+8" size="4" name="MR[2]" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="MATCH" description="Timer counter match value." /> + </Register> + <Register start="+0x018+12" size="4" name="MR[3]" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="MATCH" description="Timer counter match value." /> + </Register> + <Register start="+0x028" size="4" name="CCR" access="Read/Write" description="Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="CAP0RE" description="Capture on CAPn.0 rising edge"> + <Enum name="ENABLE" start="1" description="A sequence of 0 then 1 on CAPn.0 will cause CR0 to be loaded with the contents of TC." /> + <Enum name="DISABLE" start="0" description="This feature is disabled." /> + </BitField> + <BitField start="1" size="1" name="CAP0FE" description="Capture on CAPn.0 falling edge"> + <Enum name="ENABLE" start="1" description="A sequence of 1 then 0 on CAPn.0 will cause CR0 to be loaded with the contents of TC." /> + <Enum name="DISABLE" start="0" description="This feature is disabled." /> + </BitField> + <BitField start="2" size="1" name="CAP0I" description="Interrupt on CAPn.0 event"> + <Enum name="ENABLE" start="1" description="A CR0 load due to a CAPn.0 event will generate an interrupt." /> + <Enum name="DISABLE" start="0" description="This feature is disabled." /> + </BitField> + <BitField start="3" size="1" name="CAP1RE" description="Capture on CAPn.1 rising edge"> + <Enum name="ENABLE" start="1" description="A sequence of 0 then 1 on CAPn.1 will cause CR1 to be loaded with the contents of TC." /> + <Enum name="DISABLE" start="0" description="This feature is disabled." /> + </BitField> + <BitField start="4" size="1" name="CAP1FE" description="Capture on CAPn.1 falling edge"> + <Enum name="ENABLE" start="1" description="A sequence of 1 then 0 on CAPn.1 will cause CR1 to be loaded with the contents of TC." /> + <Enum name="DISABLE" start="0" description="This feature is disabled." /> + </BitField> + <BitField start="5" size="1" name="CAP1I" description="Interrupt on CAPn.1 event"> + <Enum name="ENABLE" start="1" description="A CR1 load due to a CAPn.1 event will generate an interrupt." /> + <Enum name="DISABLE" start="0" description="This feature is disabled." /> + </BitField> + <BitField start="6" size="26" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x02C+0" size="4" name="CR[0]" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CAP" description="Timer counter capture value." /> + </Register> + <Register start="+0x02C+4" size="4" name="CR[1]" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CAP" description="Timer counter capture value." /> + </Register> + <Register start="+0x03C" size="4" name="EMR" access="Read/Write" description="External Match Register. The EMR controls the external match pins." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="EM0" description="External Match 0. When a match occurs between the TC and MR0, this bit can either toggle, go low, go high, or do nothing, depending on bits 5:4 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." /> + <BitField start="1" size="1" name="EM1" description="External Match 1. When a match occurs between the TC and MR1, this bit can either toggle, go low, go high, or do nothing, depending on bits 7:6 of this register. This bit can be driven onto a MATn.1 pin, in a positive-logic manner (0 = low, 1 = high)." /> + <BitField start="2" size="1" name="EM2" description="External Match 2. When a match occurs between the TC and MR2, this bit can either toggle, go low, go high, or do nothing, depending on bits 9:8 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." /> + <BitField start="3" size="1" name="EM3" description="External Match 3. When a match occurs between the TC and MR3, this bit can either toggle, go low, go high, or do nothing, depending on bits 11:10 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." /> + <BitField start="4" size="2" name="EMC0" description="External Match Control 0. Determines the functionality of External Match 0."> + <Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." /> + <Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." /> + <Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." /> + <Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." /> + </BitField> + <BitField start="6" size="2" name="EMC1" description="External Match Control 1. Determines the functionality of External Match 1."> + <Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." /> + <Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." /> + <Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." /> + <Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." /> + </BitField> + <BitField start="8" size="2" name="EMC2" description="External Match Control 2. Determines the functionality of External Match 2."> + <Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." /> + <Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." /> + <Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." /> + <Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." /> + </BitField> + <BitField start="10" size="2" name="EMC3" description="External Match Control 3. Determines the functionality of External Match 3."> + <Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." /> + <Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." /> + <Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." /> + <Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." /> + </BitField> + <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x070" size="4" name="CTCR" access="Read/Write" description="Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="CTMODE" description="Counter/Timer Mode This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale Register."> + <Enum name="TIMER_MODE_EVERY_RI" start="0x0" description="Timer Mode: every rising PCLK edge" /> + <Enum name="RISING" start="0x1" description="Counter Mode: TC is incremented on rising edges on the CAP input selected by bits 3:2." /> + <Enum name="FALLING" start="0x2" description="Counter Mode: TC is incremented on falling edges on the CAP input selected by bits 3:2." /> + <Enum name="DUALEDGE" start="0x3" description="Counter Mode: TC is incremented on both edges on the CAP input selected by bits 3:2." /> + </BitField> + <BitField start="2" size="2" name="CINSEL" description="Count Input Select When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the TnCTCR, the 3 bits for that input in the Capture Control Register (TnCCR) must be programmed as 000. However, capture and/or interrupt can be selected for the other 3 CAPn inputs in the same timer."> + <Enum name="CAPN_0_FOR_TIMERN" start="0x0" description="CAPn.0 for TIMERn" /> + <Enum name="CAPN_1_FOR_TIMERN" start="0x1" description="CAPn.1 for TIMERn" /> + </BitField> + <BitField start="4" size="28" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + </RegisterGroup> + <RegisterGroup name="UART2" start="0x40098000" description="UART0/2/3 "> + <Register start="+0x000" size="4" name="RBR" access="None" description="Receiver Buffer Register. Contains the next received character to be read (DLAB =0)." reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="8" name="RBR" description="The UARTn Receiver Buffer Register contains the oldest received byte in the UARTn Rx FIFO." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x000" size="4" name="THR" access="WriteOnly" description="Transmit Holding Regiter. The next character to be transmitted is written here (DLAB =0)." reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="8" name="THR" description="Writing to the UARTn Transmit Holding Register causes the data to be stored in the UARTn transmit FIFO. The byte will be sent when it reaches the bottom of the FIFO and the transmitter is available." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x000" size="4" name="DLL" access="Read/Write" description="Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB =1)." reset_value="0x01" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="DLLSB" description="The UARTn Divisor Latch LSB Register, along with the UnDLM register, determines the baud rate of the UARTn." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x004" size="4" name="DLM" access="Read/Write" description="Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB =1)." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="DLMSB" description="The UARTn Divisor Latch MSB Register, along with the U0DLL register, determines the baud rate of the UARTn." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x004" size="4" name="IER" access="Read/Write" description="Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential UART interrupts (DLAB =0)." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RBRIE" description="RBR Interrupt Enable. Enables the Receive Data Available interrupt for UARTn. It also controls the Character Receive Time-out interrupt."> + <Enum name="DISABLE_THE_RDA_INTE" start="0" description="Disable the RDA interrupts." /> + <Enum name="ENABLE_THE_RDA_INTER" start="1" description="Enable the RDA interrupts." /> + </BitField> + <BitField start="1" size="1" name="THREIE" description="THRE Interrupt Enable. Enables the THRE interrupt for UARTn. The status of this can be read from UnLSR[5]."> + <Enum name="DISABLE_THE_THRE_INT" start="0" description="Disable the THRE interrupts." /> + <Enum name="ENABLE_THE_THRE_INTE" start="1" description="Enable the THRE interrupts." /> + </BitField> + <BitField start="2" size="1" name="RXIE" description="RX Line Status Interrupt Enable. Enables the UARTn RX line status interrupts. The status of this interrupt can be read from UnLSR[4:1]."> + <Enum name="DISABLE_THE_RX_LINE_" start="0" description="Disable the RX line status interrupts." /> + <Enum name="ENABLE_THE_RX_LINE_S" start="1" description="Enable the RX line status interrupts." /> + </BitField> + <BitField start="3" size="5" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="8" size="1" name="ABEOINTEN" description="Enables the end of auto-baud interrupt."> + <Enum name="DISABLE_END_OF_AUTO_" start="0" description="Disable end of auto-baud Interrupt." /> + <Enum name="ENABLE_END_OF_AUTO_B" start="1" description="Enable end of auto-baud Interrupt." /> + </BitField> + <BitField start="9" size="1" name="ABTOINTEN" description="Enables the auto-baud time-out interrupt."> + <Enum name="DISABLE_AUTO_BAUD_TI" start="0" description="Disable auto-baud time-out Interrupt." /> + <Enum name="ENABLE_AUTO_BAUD_TIM" start="1" description="Enable auto-baud time-out Interrupt." /> + </BitField> + <BitField start="10" size="22" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x008" size="4" name="IIR" access="ReadOnly" description="Interrupt ID Register. Identifies which interrupt(s) are pending." reset_value="0x01" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="INTSTATUS" description="Interrupt status. Note that UnIIR[0] is active low. The pending interrupt can be determined by evaluating UnIIR[3:1]."> + <Enum name="AT_LEAST_ONE_INTERRU" start="0" description="At least one interrupt is pending." /> + <Enum name="NO_INTERRUPT_IS_PEND" start="1" description="No interrupt is pending." /> + </BitField> + <BitField start="1" size="3" name="INTID" description="Interrupt identification. UnIER[3:1] identifies an interrupt corresponding to the UARTn Rx or TX FIFO. All other combinations of UnIER[3:1] not listed below are reserved (000,100,101,111)."> + <Enum name="1_RECEIVE_LINE_S" start="0x3" description="1 - Receive Line Status (RLS)." /> + <Enum name="2A__RECEIVE_DATA_AV" start="0x2" description="2a - Receive Data Available (RDA)." /> + <Enum name="2B__CHARACTER_TIME_" start="0x6" description="2b - Character Time-out Indicator (CTI)." /> + <Enum name="3_THRE_INTERRUPT" start="0x1" description="3 - THRE Interrupt" /> + </BitField> + <BitField start="4" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="6" size="2" name="FIFOENABLE" description="Copies of UnFCR[0]." /> + <BitField start="8" size="1" name="ABEOINT" description="End of auto-baud interrupt. True if auto-baud has finished successfully and interrupt is enabled." /> + <BitField start="9" size="1" name="ABTOINT" description="Auto-baud time-out interrupt. True if auto-baud has timed out and interrupt is enabled." /> + <BitField start="10" size="22" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x008" size="4" name="FCR" access="WriteOnly" description="FIFO Control Register. Controls UART FIFO usage and modes." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="FIFOEN" description="FIFO Enable."> + <Enum name="UARTN_FIFOS_ARE_DISA" start="0" description="UARTn FIFOs are disabled. Must not be used in the application." /> + <Enum name="ACTIVE_HIGH_ENABLE_F" start="1" description="Active high enable for both UARTn Rx and TX FIFOs and UnFCR[7:1] access. This bit must be set for proper UART operation. Any transition on this bit will automatically clear the related UART FIFOs." /> + </BitField> + <BitField start="1" size="1" name="RXFIFORES" description="RX FIFO Reset."> + <Enum name="NO_IMPACT_ON_EITHER_" start="0" description="No impact on either of UARTn FIFOs." /> + <Enum name="WRITING_A_LOGIC_1_TO" start="1" description="Writing a logic 1 to UnFCR[1] will clear all bytes in UARTn Rx FIFO, reset the pointer logic. This bit is self-clearing." /> + </BitField> + <BitField start="2" size="1" name="TXFIFORES" description="TX FIFO Reset."> + <Enum name="NO_IMPACT_ON_EITHER_" start="0" description="No impact on either of UARTn FIFOs." /> + <Enum name="WRITING_A_LOGIC_1_TO" start="1" description="Writing a logic 1 to UnFCR[2] will clear all bytes in UARTn TX FIFO, reset the pointer logic. This bit is self-clearing." /> + </BitField> + <BitField start="3" size="1" name="DMAMODE" description="DMA Mode Select. When the FIFO enable (bit 0 of this register) is set, this bit selects the DMA mode. See Section 18.6.6.1." /> + <BitField start="4" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="6" size="2" name="RXTRIGLVL" description="RX Trigger Level. These two bits determine how many receiver UARTn FIFO characters must be written before an interrupt or DMA request is activated."> + <Enum name="TRIGGER_LEVEL_0_1_C" start="0x0" description="Trigger level 0 (1 character or 0x01)." /> + <Enum name="TRIGGER_LEVEL_1_4_C" start="0x1" description="Trigger level 1 (4 characters or 0x04)." /> + <Enum name="TRIGGER_LEVEL_2_8_C" start="0x2" description="Trigger level 2 (8 characters or 0x08)." /> + <Enum name="TRIGGER_LEVEL_3_14_" start="0x3" description="Trigger level 3 (14 characters or 0x0E)." /> + </BitField> + <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x00C" size="4" name="LCR" access="Read/Write" description="Line Control Register. Contains controls for frame formatting and break generation." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="WLS" description="Word Length Select."> + <Enum name="5_BIT_CHARACTER_LENG" start="0x0" description="5-bit character length" /> + <Enum name="6_BIT_CHARACTER_LENG" start="0x1" description="6-bit character length" /> + <Enum name="7_BIT_CHARACTER_LENG" start="0x2" description="7-bit character length" /> + <Enum name="8_BIT_CHARACTER_LENG" start="0x3" description="8-bit character length" /> + </BitField> + <BitField start="2" size="1" name="SBS" description="Stop Bit Select"> + <Enum name="1_STOP_BIT_" start="0" description="1 stop bit." /> + <Enum name="2_STOP_BITS_1_5_IF_" start="1" description="2 stop bits (1.5 if UnLCR[1:0]=00)." /> + </BitField> + <BitField start="3" size="1" name="PE" description="Parity Enable."> + <Enum name="DISABLE_PARITY_GENER" start="0" description="Disable parity generation and checking." /> + <Enum name="ENABLE_PARITY_GENERA" start="1" description="Enable parity generation and checking." /> + </BitField> + <BitField start="4" size="2" name="PS" description="Parity Select"> + <Enum name="ODD_PARITY_NUMBER_O" start="0x0" description="Odd parity. Number of 1s in the transmitted character and the attached parity bit will be odd." /> + <Enum name="EVEN_PARITY_NUMBER_" start="0x1" description="Even Parity. Number of 1s in the transmitted character and the attached parity bit will be even." /> + <Enum name="FORCED_1_STICK_PARIT" start="0x2" description="Forced 1 stick parity." /> + <Enum name="FORCED_0_STICK_PARIT" start="0x3" description="Forced 0 stick parity." /> + </BitField> + <BitField start="6" size="1" name="BC" description="Break Control"> + <Enum name="DISABLE_BREAK_TRANSM" start="0" description="Disable break transmission." /> + <Enum name="ENABLE_BREAK_TRANSMI" start="1" description="Enable break transmission. Output pin UARTn TXD is forced to logic 0 when UnLCR[6] is active high." /> + </BitField> + <BitField start="7" size="1" name="DLAB" description="Divisor Latch Access Bit"> + <Enum name="DISABLE_ACCESS_TO_DI" start="0" description="Disable access to Divisor Latches." /> + <Enum name="ENABLE_ACCESS_TO_DIV" start="1" description="Enable access to Divisor Latches." /> + </BitField> + <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x014" size="4" name="LSR" access="None" description="Line Status Register. Contains flags for transmit and receive status, including line errors." reset_value="0x60" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RDR" description="Receiver Data Ready. UnLSR[0] is set when the UnRBR holds an unread character and is cleared when the UARTn RBR FIFO is empty."> + <Enum name="EMPTY" start="0" description="The UARTn receiver FIFO is empty." /> + <Enum name="NOTEMPTY" start="1" description="The UARTn receiver FIFO is not empty." /> + </BitField> + <BitField start="1" size="1" name="OE" description="Overrun Error. The overrun error condition is set as soon as it occurs. An UnLSR read clears UnLSR[1]. UnLSR[1] is set when UARTn RSR has a new character assembled and the UARTn RBR FIFO is full. In this case, the UARTn RBR FIFO will not be overwritten and the character in the UARTn RSR will be lost."> + <Enum name="INACTIVE" start="0" description="Overrun error status is inactive." /> + <Enum name="ACTIVE" start="1" description="Overrun error status is active." /> + </BitField> + <BitField start="2" size="1" name="PE" description="Parity Error. When the parity bit of a received character is in the wrong state, a parity error occurs. An UnLSR read clears UnLSR[2]. Time of parity error detection is dependent on UnFCR[0]. Note: A parity error is associated with the character at the top of the UARTn RBR FIFO."> + <Enum name="INACTIVE" start="0" description="Parity error status is inactive." /> + <Enum name="ACTIVE" start="1" description="Parity error status is active." /> + </BitField> + <BitField start="3" size="1" name="FE" description="Framing Error. When the stop bit of a received character is a logic 0, a framing error occurs. An UnLSR read clears UnLSR[3]. The time of the framing error detection is dependent on UnFCR[0]. Upon detection of a framing error, the Rx will attempt to resynchronize to the data and assume that the bad stop bit is actually an early start bit. However, it cannot be assumed that the next received byte will be correct even if there is no Framing Error. Note: A framing error is associated with the character at the top of the UARTn RBR FIFO."> + <Enum name="INACTIVE" start="0" description="Framing error status is inactive." /> + <Enum name="ACTIVE" start="1" description="Framing error status is active." /> + </BitField> + <BitField start="4" size="1" name="BI" description="Break Interrupt. When RXDn is held in the spacing state (all zeroes) for one full character transmission (start, data, parity, stop), a break interrupt occurs. Once the break condition has been detected, the receiver goes idle until RXDn goes to marking state (all ones). An UnLSR read clears this status bit. The time of break detection is dependent on UnFCR[0]. Note: The break interrupt is associated with the character at the top of the UARTn RBR FIFO."> + <Enum name="INACTIVE" start="0" description="Break interrupt status is inactive." /> + <Enum name="ACTIVE" start="1" description="Break interrupt status is active." /> + </BitField> + <BitField start="5" size="1" name="THRE" description="Transmitter Holding Register Empty. THRE is set immediately upon detection of an empty UARTn THR and is cleared on a UnTHR write."> + <Enum name="VALIDDATA" start="0" description="UnTHR contains valid data." /> + <Enum name="EMPTY" start="1" description="UnTHR is empty." /> + </BitField> + <BitField start="6" size="1" name="TEMT" description="Transmitter Empty. TEMT is set when both UnTHR and UnTSR are empty; TEMT is cleared when either the UnTSR or the UnTHR contain valid data."> + <Enum name="VALIDDATA" start="0" description="UnTHR and/or the UnTSR contains valid data." /> + <Enum name="EMPTY" start="1" description="UnTHR and the UnTSR are empty." /> + </BitField> + <BitField start="7" size="1" name="RXFE" description="Error in RX FIFO . UnLSR[7] is set when a character with a Rx error such as framing error, parity error or break interrupt, is loaded into the UnRBR. This bit is cleared when the UnLSR register is read and there are no subsequent errors in the UARTn FIFO."> + <Enum name="NOERROR" start="0" description="UnRBR contains no UARTn RX errors or UnFCR[0]=0." /> + <Enum name="ERRORS" start="1" description="UARTn RBR contains at least one UARTn RX error." /> + </BitField> + <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x01C" size="4" name="SCR" access="Read/Write" description="Scratch Pad Register. 8-bit temporary storage for software." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="PAD" description="A readable, writable byte." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x020" size="4" name="ACR" access="Read/Write" description="Auto-baud Control Register. Contains controls for the auto-baud feature." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="START" description="Start bit. This bit is automatically cleared after auto-baud completion."> + <Enum name="AUTO_BAUD_STOP_AUTO" start="0" description="Auto-baud stop (auto-baud is not running)." /> + <Enum name="AUTO_BAUD_START_AUT" start="1" description="Auto-baud start (auto-baud is running). Auto-baud run bit. This bit is automatically cleared after auto-baud completion." /> + </BitField> + <BitField start="1" size="1" name="MODE" description="Auto-baud mode select bit."> + <Enum name="MODE_0_" start="0" description="Mode 0." /> + <Enum name="MODE_1_" start="1" description="Mode 1." /> + </BitField> + <BitField start="2" size="1" name="AUTORESTART" description="Restart bit."> + <Enum name="NO_RESTART_" start="0" description="No restart." /> + <Enum name="RESTART_IN_CASE_OF_T" start="1" description="Restart in case of time-out (counter restarts at next UARTn Rx falling edge)" /> + </BitField> + <BitField start="3" size="5" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="8" size="1" name="ABEOINTCLR" description="End of auto-baud interrupt clear bit (write-only accessible). Writing a 1 will clear the corresponding interrupt in the UnIIR. Writing a 0 has no impact."> + <Enum name="NO_IMPACT_" start="0" description="No impact." /> + <Enum name="CLEAR_THE_CORRESPOND" start="1" description="Clear the corresponding interrupt in the IIR." /> + </BitField> + <BitField start="9" size="1" name="ABTOINTCLR" description="Auto-baud time-out interrupt clear bit (write-only accessible). Writing a 1 will clear the corresponding interrupt in the UnIIR. Writing a 0 has no impact."> + <Enum name="NO_IMPACT_" start="0" description="No impact." /> + <Enum name="CLEAR_THE_CORRESPOND" start="1" description="Clear the corresponding interrupt in the IIR." /> + </BitField> + <BitField start="10" size="22" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x028" size="4" name="FDR" access="Read/Write" description="Fractional Divider Register. Generates a clock input for the baud rate divider." reset_value="0x10" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="4" name="DIVADDVAL" description="Baud-rate generation pre-scaler divisor value. If this field is 0, fractional baud-rate generator will not impact the UARTn baudrate." /> + <BitField start="4" size="4" name="MULVAL" description="Baud-rate pre-scaler multiplier value. This field must be greater or equal 1 for UARTn to operate properly, regardless of whether the fractional baud-rate generator is used or not." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x030" size="4" name="TER" access="Read/Write" description="Transmit Enable Register. Turns off UART transmitter for use with software flow control." reset_value="0x80" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="7" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="7" size="1" name="TXEN" description="When this bit is 1, as it is after a Reset, data written to the THR is output on the TXD pin as soon as any preceding data has been sent. If this bit is cleared to 0 while a character is being sent, the transmission of that character is completed, but no further characters are sent until this bit is set again. In other words, a 0 in this bit blocks the transfer of characters from the THR or TX FIFO into the transmit shift register. Software implementing software-handshaking can clear this bit when it receives an XOFF character (DC3). Software can set this bit again when it receives an XON (DC1) character." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x04C" size="4" name="RS485CTRL" access="Read/Write" description="RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="NMMEN" description="NMM enable."> + <Enum name="DISABLED" start="0" description="RS-485/EIA-485 Normal Multidrop Mode (NMM) is disabled." /> + <Enum name="ENABLED" start="1" description="RS-485/EIA-485 Normal Multidrop Mode (NMM) is enabled. In this mode, an address is detected when a received byte has the parity bit = 1, generating a received data interrupt. See Section 18.6.16 RS-485/EIA-485 modes of operation." /> + </BitField> + <BitField start="1" size="1" name="RXDIS" description="Receiver enable."> + <Enum name="ENABLED" start="0" description="The receiver is enabled." /> + <Enum name="DISABLED" start="1" description="The receiver is disabled." /> + </BitField> + <BitField start="2" size="1" name="AADEN" description="AAD enable."> + <Enum name="DISABLED" start="0" description="Auto Address Detect (AAD) is disabled." /> + <Enum name="ENABLED" start="1" description="Auto Address Detect (AAD) is enabled." /> + </BitField> + <BitField start="3" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="4" size="1" name="DCTRL" description="Direction control enable."> + <Enum name="DISABLE_AUTO_DIRECTI" start="0" description="Disable Auto Direction Control." /> + <Enum name="ENABLE_AUTO_DIRECTIO" start="1" description="Enable Auto Direction Control." /> + </BitField> + <BitField start="5" size="1" name="OINV" description="Direction control pin polarity. This bit reverses the polarity of the direction control signal on the Un_OE pin."> + <Enum name="DIRLOW" start="0" description="The direction control pin will be driven to logic 0 when the transmitter has data to be sent. It will be driven to logic 1 after the last bit of data has been transmitted." /> + <Enum name="DIRHIGH" start="1" description="The direction control pin will be driven to logic 1 when the transmitter has data to be sent. It will be driven to logic 0 after the last bit of data has been transmitted." /> + </BitField> + <BitField start="6" size="26" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x050" size="4" name="RS485ADRMATCH" access="Read/Write" description="RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="ADRMATCH" description="Contains the address match value." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x054" size="4" name="RS485DLY" access="Read/Write" description="RS-485/EIA-485 direction control delay." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="DLY" description="Contains the direction control (UnOE) delay value. This register works in conjunction with an 8-bit counter." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + </RegisterGroup> + <RegisterGroup name="UART3" start="0x4009C000" description="UART0/2/3 "> + <Register start="+0x000" size="4" name="RBR" access="None" description="Receiver Buffer Register. Contains the next received character to be read (DLAB =0)." reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="8" name="RBR" description="The UARTn Receiver Buffer Register contains the oldest received byte in the UARTn Rx FIFO." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x000" size="4" name="THR" access="WriteOnly" description="Transmit Holding Regiter. The next character to be transmitted is written here (DLAB =0)." reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="8" name="THR" description="Writing to the UARTn Transmit Holding Register causes the data to be stored in the UARTn transmit FIFO. The byte will be sent when it reaches the bottom of the FIFO and the transmitter is available." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x000" size="4" name="DLL" access="Read/Write" description="Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB =1)." reset_value="0x01" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="DLLSB" description="The UARTn Divisor Latch LSB Register, along with the UnDLM register, determines the baud rate of the UARTn." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x004" size="4" name="DLM" access="Read/Write" description="Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB =1)." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="DLMSB" description="The UARTn Divisor Latch MSB Register, along with the U0DLL register, determines the baud rate of the UARTn." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x004" size="4" name="IER" access="Read/Write" description="Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential UART interrupts (DLAB =0)." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RBRIE" description="RBR Interrupt Enable. Enables the Receive Data Available interrupt for UARTn. It also controls the Character Receive Time-out interrupt."> + <Enum name="DISABLE_THE_RDA_INTE" start="0" description="Disable the RDA interrupts." /> + <Enum name="ENABLE_THE_RDA_INTER" start="1" description="Enable the RDA interrupts." /> + </BitField> + <BitField start="1" size="1" name="THREIE" description="THRE Interrupt Enable. Enables the THRE interrupt for UARTn. The status of this can be read from UnLSR[5]."> + <Enum name="DISABLE_THE_THRE_INT" start="0" description="Disable the THRE interrupts." /> + <Enum name="ENABLE_THE_THRE_INTE" start="1" description="Enable the THRE interrupts." /> + </BitField> + <BitField start="2" size="1" name="RXIE" description="RX Line Status Interrupt Enable. Enables the UARTn RX line status interrupts. The status of this interrupt can be read from UnLSR[4:1]."> + <Enum name="DISABLE_THE_RX_LINE_" start="0" description="Disable the RX line status interrupts." /> + <Enum name="ENABLE_THE_RX_LINE_S" start="1" description="Enable the RX line status interrupts." /> + </BitField> + <BitField start="3" size="5" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="8" size="1" name="ABEOINTEN" description="Enables the end of auto-baud interrupt."> + <Enum name="DISABLE_END_OF_AUTO_" start="0" description="Disable end of auto-baud Interrupt." /> + <Enum name="ENABLE_END_OF_AUTO_B" start="1" description="Enable end of auto-baud Interrupt." /> + </BitField> + <BitField start="9" size="1" name="ABTOINTEN" description="Enables the auto-baud time-out interrupt."> + <Enum name="DISABLE_AUTO_BAUD_TI" start="0" description="Disable auto-baud time-out Interrupt." /> + <Enum name="ENABLE_AUTO_BAUD_TIM" start="1" description="Enable auto-baud time-out Interrupt." /> + </BitField> + <BitField start="10" size="22" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x008" size="4" name="IIR" access="ReadOnly" description="Interrupt ID Register. Identifies which interrupt(s) are pending." reset_value="0x01" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="INTSTATUS" description="Interrupt status. Note that UnIIR[0] is active low. The pending interrupt can be determined by evaluating UnIIR[3:1]."> + <Enum name="AT_LEAST_ONE_INTERRU" start="0" description="At least one interrupt is pending." /> + <Enum name="NO_INTERRUPT_IS_PEND" start="1" description="No interrupt is pending." /> + </BitField> + <BitField start="1" size="3" name="INTID" description="Interrupt identification. UnIER[3:1] identifies an interrupt corresponding to the UARTn Rx or TX FIFO. All other combinations of UnIER[3:1] not listed below are reserved (000,100,101,111)."> + <Enum name="1_RECEIVE_LINE_S" start="0x3" description="1 - Receive Line Status (RLS)." /> + <Enum name="2A__RECEIVE_DATA_AV" start="0x2" description="2a - Receive Data Available (RDA)." /> + <Enum name="2B__CHARACTER_TIME_" start="0x6" description="2b - Character Time-out Indicator (CTI)." /> + <Enum name="3_THRE_INTERRUPT" start="0x1" description="3 - THRE Interrupt" /> + </BitField> + <BitField start="4" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="6" size="2" name="FIFOENABLE" description="Copies of UnFCR[0]." /> + <BitField start="8" size="1" name="ABEOINT" description="End of auto-baud interrupt. True if auto-baud has finished successfully and interrupt is enabled." /> + <BitField start="9" size="1" name="ABTOINT" description="Auto-baud time-out interrupt. True if auto-baud has timed out and interrupt is enabled." /> + <BitField start="10" size="22" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x008" size="4" name="FCR" access="WriteOnly" description="FIFO Control Register. Controls UART FIFO usage and modes." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="FIFOEN" description="FIFO Enable."> + <Enum name="UARTN_FIFOS_ARE_DISA" start="0" description="UARTn FIFOs are disabled. Must not be used in the application." /> + <Enum name="ACTIVE_HIGH_ENABLE_F" start="1" description="Active high enable for both UARTn Rx and TX FIFOs and UnFCR[7:1] access. This bit must be set for proper UART operation. Any transition on this bit will automatically clear the related UART FIFOs." /> + </BitField> + <BitField start="1" size="1" name="RXFIFORES" description="RX FIFO Reset."> + <Enum name="NO_IMPACT_ON_EITHER_" start="0" description="No impact on either of UARTn FIFOs." /> + <Enum name="WRITING_A_LOGIC_1_TO" start="1" description="Writing a logic 1 to UnFCR[1] will clear all bytes in UARTn Rx FIFO, reset the pointer logic. This bit is self-clearing." /> + </BitField> + <BitField start="2" size="1" name="TXFIFORES" description="TX FIFO Reset."> + <Enum name="NO_IMPACT_ON_EITHER_" start="0" description="No impact on either of UARTn FIFOs." /> + <Enum name="WRITING_A_LOGIC_1_TO" start="1" description="Writing a logic 1 to UnFCR[2] will clear all bytes in UARTn TX FIFO, reset the pointer logic. This bit is self-clearing." /> + </BitField> + <BitField start="3" size="1" name="DMAMODE" description="DMA Mode Select. When the FIFO enable (bit 0 of this register) is set, this bit selects the DMA mode. See Section 18.6.6.1." /> + <BitField start="4" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="6" size="2" name="RXTRIGLVL" description="RX Trigger Level. These two bits determine how many receiver UARTn FIFO characters must be written before an interrupt or DMA request is activated."> + <Enum name="TRIGGER_LEVEL_0_1_C" start="0x0" description="Trigger level 0 (1 character or 0x01)." /> + <Enum name="TRIGGER_LEVEL_1_4_C" start="0x1" description="Trigger level 1 (4 characters or 0x04)." /> + <Enum name="TRIGGER_LEVEL_2_8_C" start="0x2" description="Trigger level 2 (8 characters or 0x08)." /> + <Enum name="TRIGGER_LEVEL_3_14_" start="0x3" description="Trigger level 3 (14 characters or 0x0E)." /> + </BitField> + <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x00C" size="4" name="LCR" access="Read/Write" description="Line Control Register. Contains controls for frame formatting and break generation." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="WLS" description="Word Length Select."> + <Enum name="5_BIT_CHARACTER_LENG" start="0x0" description="5-bit character length" /> + <Enum name="6_BIT_CHARACTER_LENG" start="0x1" description="6-bit character length" /> + <Enum name="7_BIT_CHARACTER_LENG" start="0x2" description="7-bit character length" /> + <Enum name="8_BIT_CHARACTER_LENG" start="0x3" description="8-bit character length" /> + </BitField> + <BitField start="2" size="1" name="SBS" description="Stop Bit Select"> + <Enum name="1_STOP_BIT_" start="0" description="1 stop bit." /> + <Enum name="2_STOP_BITS_1_5_IF_" start="1" description="2 stop bits (1.5 if UnLCR[1:0]=00)." /> + </BitField> + <BitField start="3" size="1" name="PE" description="Parity Enable."> + <Enum name="DISABLE_PARITY_GENER" start="0" description="Disable parity generation and checking." /> + <Enum name="ENABLE_PARITY_GENERA" start="1" description="Enable parity generation and checking." /> + </BitField> + <BitField start="4" size="2" name="PS" description="Parity Select"> + <Enum name="ODD_PARITY_NUMBER_O" start="0x0" description="Odd parity. Number of 1s in the transmitted character and the attached parity bit will be odd." /> + <Enum name="EVEN_PARITY_NUMBER_" start="0x1" description="Even Parity. Number of 1s in the transmitted character and the attached parity bit will be even." /> + <Enum name="FORCED_1_STICK_PARIT" start="0x2" description="Forced 1 stick parity." /> + <Enum name="FORCED_0_STICK_PARIT" start="0x3" description="Forced 0 stick parity." /> + </BitField> + <BitField start="6" size="1" name="BC" description="Break Control"> + <Enum name="DISABLE_BREAK_TRANSM" start="0" description="Disable break transmission." /> + <Enum name="ENABLE_BREAK_TRANSMI" start="1" description="Enable break transmission. Output pin UARTn TXD is forced to logic 0 when UnLCR[6] is active high." /> + </BitField> + <BitField start="7" size="1" name="DLAB" description="Divisor Latch Access Bit"> + <Enum name="DISABLE_ACCESS_TO_DI" start="0" description="Disable access to Divisor Latches." /> + <Enum name="ENABLE_ACCESS_TO_DIV" start="1" description="Enable access to Divisor Latches." /> + </BitField> + <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x014" size="4" name="LSR" access="None" description="Line Status Register. Contains flags for transmit and receive status, including line errors." reset_value="0x60" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RDR" description="Receiver Data Ready. UnLSR[0] is set when the UnRBR holds an unread character and is cleared when the UARTn RBR FIFO is empty."> + <Enum name="EMPTY" start="0" description="The UARTn receiver FIFO is empty." /> + <Enum name="NOTEMPTY" start="1" description="The UARTn receiver FIFO is not empty." /> + </BitField> + <BitField start="1" size="1" name="OE" description="Overrun Error. The overrun error condition is set as soon as it occurs. An UnLSR read clears UnLSR[1]. UnLSR[1] is set when UARTn RSR has a new character assembled and the UARTn RBR FIFO is full. In this case, the UARTn RBR FIFO will not be overwritten and the character in the UARTn RSR will be lost."> + <Enum name="INACTIVE" start="0" description="Overrun error status is inactive." /> + <Enum name="ACTIVE" start="1" description="Overrun error status is active." /> + </BitField> + <BitField start="2" size="1" name="PE" description="Parity Error. When the parity bit of a received character is in the wrong state, a parity error occurs. An UnLSR read clears UnLSR[2]. Time of parity error detection is dependent on UnFCR[0]. Note: A parity error is associated with the character at the top of the UARTn RBR FIFO."> + <Enum name="INACTIVE" start="0" description="Parity error status is inactive." /> + <Enum name="ACTIVE" start="1" description="Parity error status is active." /> + </BitField> + <BitField start="3" size="1" name="FE" description="Framing Error. When the stop bit of a received character is a logic 0, a framing error occurs. An UnLSR read clears UnLSR[3]. The time of the framing error detection is dependent on UnFCR[0]. Upon detection of a framing error, the Rx will attempt to resynchronize to the data and assume that the bad stop bit is actually an early start bit. However, it cannot be assumed that the next received byte will be correct even if there is no Framing Error. Note: A framing error is associated with the character at the top of the UARTn RBR FIFO."> + <Enum name="INACTIVE" start="0" description="Framing error status is inactive." /> + <Enum name="ACTIVE" start="1" description="Framing error status is active." /> + </BitField> + <BitField start="4" size="1" name="BI" description="Break Interrupt. When RXDn is held in the spacing state (all zeroes) for one full character transmission (start, data, parity, stop), a break interrupt occurs. Once the break condition has been detected, the receiver goes idle until RXDn goes to marking state (all ones). An UnLSR read clears this status bit. The time of break detection is dependent on UnFCR[0]. Note: The break interrupt is associated with the character at the top of the UARTn RBR FIFO."> + <Enum name="INACTIVE" start="0" description="Break interrupt status is inactive." /> + <Enum name="ACTIVE" start="1" description="Break interrupt status is active." /> + </BitField> + <BitField start="5" size="1" name="THRE" description="Transmitter Holding Register Empty. THRE is set immediately upon detection of an empty UARTn THR and is cleared on a UnTHR write."> + <Enum name="VALIDDATA" start="0" description="UnTHR contains valid data." /> + <Enum name="EMPTY" start="1" description="UnTHR is empty." /> + </BitField> + <BitField start="6" size="1" name="TEMT" description="Transmitter Empty. TEMT is set when both UnTHR and UnTSR are empty; TEMT is cleared when either the UnTSR or the UnTHR contain valid data."> + <Enum name="VALIDDATA" start="0" description="UnTHR and/or the UnTSR contains valid data." /> + <Enum name="EMPTY" start="1" description="UnTHR and the UnTSR are empty." /> + </BitField> + <BitField start="7" size="1" name="RXFE" description="Error in RX FIFO . UnLSR[7] is set when a character with a Rx error such as framing error, parity error or break interrupt, is loaded into the UnRBR. This bit is cleared when the UnLSR register is read and there are no subsequent errors in the UARTn FIFO."> + <Enum name="NOERROR" start="0" description="UnRBR contains no UARTn RX errors or UnFCR[0]=0." /> + <Enum name="ERRORS" start="1" description="UARTn RBR contains at least one UARTn RX error." /> + </BitField> + <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x01C" size="4" name="SCR" access="Read/Write" description="Scratch Pad Register. 8-bit temporary storage for software." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="PAD" description="A readable, writable byte." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x020" size="4" name="ACR" access="Read/Write" description="Auto-baud Control Register. Contains controls for the auto-baud feature." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="START" description="Start bit. This bit is automatically cleared after auto-baud completion."> + <Enum name="AUTO_BAUD_STOP_AUTO" start="0" description="Auto-baud stop (auto-baud is not running)." /> + <Enum name="AUTO_BAUD_START_AUT" start="1" description="Auto-baud start (auto-baud is running). Auto-baud run bit. This bit is automatically cleared after auto-baud completion." /> + </BitField> + <BitField start="1" size="1" name="MODE" description="Auto-baud mode select bit."> + <Enum name="MODE_0_" start="0" description="Mode 0." /> + <Enum name="MODE_1_" start="1" description="Mode 1." /> + </BitField> + <BitField start="2" size="1" name="AUTORESTART" description="Restart bit."> + <Enum name="NO_RESTART_" start="0" description="No restart." /> + <Enum name="RESTART_IN_CASE_OF_T" start="1" description="Restart in case of time-out (counter restarts at next UARTn Rx falling edge)" /> + </BitField> + <BitField start="3" size="5" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="8" size="1" name="ABEOINTCLR" description="End of auto-baud interrupt clear bit (write-only accessible). Writing a 1 will clear the corresponding interrupt in the UnIIR. Writing a 0 has no impact."> + <Enum name="NO_IMPACT_" start="0" description="No impact." /> + <Enum name="CLEAR_THE_CORRESPOND" start="1" description="Clear the corresponding interrupt in the IIR." /> + </BitField> + <BitField start="9" size="1" name="ABTOINTCLR" description="Auto-baud time-out interrupt clear bit (write-only accessible). Writing a 1 will clear the corresponding interrupt in the UnIIR. Writing a 0 has no impact."> + <Enum name="NO_IMPACT_" start="0" description="No impact." /> + <Enum name="CLEAR_THE_CORRESPOND" start="1" description="Clear the corresponding interrupt in the IIR." /> + </BitField> + <BitField start="10" size="22" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x028" size="4" name="FDR" access="Read/Write" description="Fractional Divider Register. Generates a clock input for the baud rate divider." reset_value="0x10" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="4" name="DIVADDVAL" description="Baud-rate generation pre-scaler divisor value. If this field is 0, fractional baud-rate generator will not impact the UARTn baudrate." /> + <BitField start="4" size="4" name="MULVAL" description="Baud-rate pre-scaler multiplier value. This field must be greater or equal 1 for UARTn to operate properly, regardless of whether the fractional baud-rate generator is used or not." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x030" size="4" name="TER" access="Read/Write" description="Transmit Enable Register. Turns off UART transmitter for use with software flow control." reset_value="0x80" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="7" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="7" size="1" name="TXEN" description="When this bit is 1, as it is after a Reset, data written to the THR is output on the TXD pin as soon as any preceding data has been sent. If this bit is cleared to 0 while a character is being sent, the transmission of that character is completed, but no further characters are sent until this bit is set again. In other words, a 0 in this bit blocks the transfer of characters from the THR or TX FIFO into the transmit shift register. Software implementing software-handshaking can clear this bit when it receives an XOFF character (DC3). Software can set this bit again when it receives an XON (DC1) character." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x04C" size="4" name="RS485CTRL" access="Read/Write" description="RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="NMMEN" description="NMM enable."> + <Enum name="DISABLED" start="0" description="RS-485/EIA-485 Normal Multidrop Mode (NMM) is disabled." /> + <Enum name="ENABLED" start="1" description="RS-485/EIA-485 Normal Multidrop Mode (NMM) is enabled. In this mode, an address is detected when a received byte has the parity bit = 1, generating a received data interrupt. See Section 18.6.16 RS-485/EIA-485 modes of operation." /> + </BitField> + <BitField start="1" size="1" name="RXDIS" description="Receiver enable."> + <Enum name="ENABLED" start="0" description="The receiver is enabled." /> + <Enum name="DISABLED" start="1" description="The receiver is disabled." /> + </BitField> + <BitField start="2" size="1" name="AADEN" description="AAD enable."> + <Enum name="DISABLED" start="0" description="Auto Address Detect (AAD) is disabled." /> + <Enum name="ENABLED" start="1" description="Auto Address Detect (AAD) is enabled." /> + </BitField> + <BitField start="3" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="4" size="1" name="DCTRL" description="Direction control enable."> + <Enum name="DISABLE_AUTO_DIRECTI" start="0" description="Disable Auto Direction Control." /> + <Enum name="ENABLE_AUTO_DIRECTIO" start="1" description="Enable Auto Direction Control." /> + </BitField> + <BitField start="5" size="1" name="OINV" description="Direction control pin polarity. This bit reverses the polarity of the direction control signal on the Un_OE pin."> + <Enum name="DIRLOW" start="0" description="The direction control pin will be driven to logic 0 when the transmitter has data to be sent. It will be driven to logic 1 after the last bit of data has been transmitted." /> + <Enum name="DIRHIGH" start="1" description="The direction control pin will be driven to logic 1 when the transmitter has data to be sent. It will be driven to logic 0 after the last bit of data has been transmitted." /> + </BitField> + <BitField start="6" size="26" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x050" size="4" name="RS485ADRMATCH" access="Read/Write" description="RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="ADRMATCH" description="Contains the address match value." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x054" size="4" name="RS485DLY" access="Read/Write" description="RS-485/EIA-485 direction control delay." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="DLY" description="Contains the direction control (UnOE) delay value. This register works in conjunction with an 8-bit counter." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + </RegisterGroup> + <RegisterGroup name="I2C2" start="0x400A0000" description="I2C bus interface"> + <Register start="+0x000" size="4" name="CONSET" access="Read/Write" description="I2C Control Set Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is set. Writing a zero has no effect on the corresponding bit in the I2C control register." reset_value="0x00" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + <BitField start="2" size="1" name="AA" description="Assert acknowledge flag." /> + <BitField start="3" size="1" name="SI" description="I2C interrupt flag." /> + <BitField start="4" size="1" name="STO" description="STOP flag." /> + <BitField start="5" size="1" name="STA" description="START flag." /> + <BitField start="6" size="1" name="I2EN" description="I2C interface enable." /> + <BitField start="7" size="25" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x004" size="4" name="STAT" access="ReadOnly" description="I2C Status Register. During I2C operation, this register provides detailed status codes that allow software to determine the next action needed." reset_value="0xF8" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="RESERVED" description="These bits are unused and are always 0." /> + <BitField start="3" size="5" name="Status" description="These bits give the actual status information about the I 2C interface." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x008" size="4" name="DAT" access="Read/Write" description="I2C Data Register. During master or slave transmit mode, data to be transmitted is written to this register. During master or slave receive mode, data that has been received may be read from this register." reset_value="0x00" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="Data" description="This register holds data values that have been received or are to be transmitted." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x00C" size="4" name="ADR0" access="Read/Write" description="I2C Slave Address Register 0. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="GC" description="General Call enable bit." /> + <BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x010" size="4" name="SCLH" access="Read/Write" description="SCH Duty Cycle Register High Half Word. Determines the high time of the I2C clock." reset_value="0x04" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="16" name="SCLH" description="Count for SCL HIGH time period selection." /> + <BitField start="16" size="16" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x014" size="4" name="SCLL" access="Read/Write" description="SCL Duty Cycle Register Low Half Word. Determines the low time of the I2C clock. SCLL and SCLH together determine the clock frequency generated by an I2C master and certain times used in slave mode." reset_value="0x04" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="16" name="SCLL" description="Count for SCL low time period selection." /> + <BitField start="16" size="16" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x018" size="4" name="CONCLR" access="WriteOnly" description="I2C Control Clear Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is cleared. Writing a zero has no effect on the corresponding bit in the I2C control register." reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="2" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + <BitField start="2" size="1" name="AAC" description="Assert acknowledge Clear bit." /> + <BitField start="3" size="1" name="SIC" description="I2C interrupt Clear bit." /> + <BitField start="4" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + <BitField start="5" size="1" name="STAC" description="START flag Clear bit." /> + <BitField start="6" size="1" name="I2ENC" description="I2C interface Disable bit." /> + <BitField start="7" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x01C" size="4" name="MMCTRL" access="Read/Write" description="Monitor mode control register." reset_value="0x00" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="MM_ENA" description="Monitor mode enable."> + <Enum name="MONITOR_MODE_DISABLE" start="0" description="Monitor mode disabled." /> + <Enum name="THE_I_2C_MODULE_WILL" start="1" description="The I 2C module will enter monitor mode. In this mode the SDA output will be forced high. This will prevent the I2C module from outputting data of any kind (including ACK) onto the I2C data bus. Depending on the state of the ENA_SCL bit, the output may be also forced high, preventing the module from having control over the I2C clock line." /> + </BitField> + <BitField start="1" size="1" name="ENA_SCL" description="SCL output enable."> + <Enum name="WHEN_THIS_BIT_IS_CLE" start="0" description="When this bit is cleared to 0, the SCL output will be forced high when the module is in monitor mode. As described above, this will prevent the module from having any control over the I2C clock line." /> + <Enum name="WHEN_THIS_BIT_IS_SET" start="1" description="When this bit is set, the I2C module may exercise the same control over the clock line that it would in normal operation. This means that, acting as a slave peripheral, the I2C module can stretch the clock line (hold it low) until it has had time to respond to an I2C interrupt.[1]" /> + </BitField> + <BitField start="2" size="1" name="MATCH_ALL" description="Select interrupt register match."> + <Enum name="WHEN_THIS_BIT_IS_CLE" start="0" description="When this bit is cleared, an interrupt will only be generated when a match occurs to one of the (up-to) four address registers described above. That is, the module will respond as a normal slave as far as address-recognition is concerned." /> + <Enum name="WHEN_THIS_BIT_IS_SET" start="1" description="When this bit is set to 1 and the I2C is in monitor mode, an interrupt will be generated on ANY address received. This will enable the part to monitor all traffic on the bus." /> + </BitField> + <BitField start="3" size="29" name="RESERVED" description="Reserved. The value read from reserved bits is not defined." /> + </Register> + <Register start="+0x020+0" size="4" name="ADR1" access="Read/Write" description="I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="GC" description="General Call enable bit." /> + <BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x020+4" size="4" name="ADR2" access="Read/Write" description="I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="GC" description="General Call enable bit." /> + <BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x020+8" size="4" name="ADR3" access="Read/Write" description="I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="GC" description="General Call enable bit." /> + <BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x02C" size="4" name="DATA_BUFFER" access="ReadOnly" description="Data buffer register. The contents of the 8 MSBs of the DAT shift register will be transferred to the DATA_BUFFER automatically after every nine bits (8 bits of data plus ACK or NACK) has been received on the bus." reset_value="0x00" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="Data" description="This register holds contents of the 8 MSBs of the DAT shift register." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x030+0" size="4" name="MASK[0]" access="Read/Write" description="I2C Slave address mask register" reset_value="0x00" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." /> + <BitField start="1" size="7" name="MASK" description="Mask bits." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x030+4" size="4" name="MASK[1]" access="Read/Write" description="I2C Slave address mask register" reset_value="0x00" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." /> + <BitField start="1" size="7" name="MASK" description="Mask bits." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x030+8" size="4" name="MASK[2]" access="Read/Write" description="I2C Slave address mask register" reset_value="0x00" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." /> + <BitField start="1" size="7" name="MASK" description="Mask bits." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x030+12" size="4" name="MASK[3]" access="Read/Write" description="I2C Slave address mask register" reset_value="0x00" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." /> + <BitField start="1" size="7" name="MASK" description="Mask bits." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + </RegisterGroup> + <RegisterGroup name="I2S" start="0x400A8000" description="I2S interface"> + <Register start="+0x000" size="4" name="DAO" access="Read/Write" description="I2S Digital Audio Output Register. Contains control bits for the I2S transmit channel." reset_value="0x87E1" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="WORDWIDTH" description="Selects the number of bytes in data as follows:"> + <Enum name="8_BIT_DATA" start="0x0" description="8-bit data" /> + <Enum name="16_BIT_DATA" start="0x1" description="16-bit data" /> + <Enum name="32_BIT_DATA" start="0x3" description="32-bit data" /> + </BitField> + <BitField start="2" size="1" name="MONO" description="When 1, data is of monaural format. When 0, the data is in stereo format." /> + <BitField start="3" size="1" name="STOP" description="When 1, disables accesses on FIFOs, places the transmit channel in mute mode." /> + <BitField start="4" size="1" name="RESET" description="When 1, asynchronously resets the transmit channel and FIFO." /> + <BitField start="5" size="1" name="WS_SEL" description="When 0, the interface is in master mode. When 1, the interface is in slave mode. See Section 34.7.2 for a summary of useful combinations for this bit with TXMODE." /> + <BitField start="6" size="9" name="WS_HALFPERIOD" description="Word select half period minus 1, i.e. WS 64clk period -> ws_halfperiod = 31." /> + <BitField start="15" size="1" name="MUTE" description="When 1, the transmit channel sends only zeroes." /> + <BitField start="16" size="16" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x004" size="4" name="DAI" access="Read/Write" description="I2S Digital Audio Input Register. Contains control bits for the I2S receive channel." reset_value="0x07E1" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="WORDWIDTH" description="Selects the number of bytes in data as follows:"> + <Enum name="8_BIT_DATA" start="0x0" description="8-bit data" /> + <Enum name="16_BIT_DATA" start="0x1" description="16-bit data" /> + <Enum name="32_BIT_DATA" start="0x3" description="32-bit data" /> + </BitField> + <BitField start="2" size="1" name="MONO" description="When 1, data is of monaural format. When 0, the data is in stereo format." /> + <BitField start="3" size="1" name="STOP" description="When 1, disables accesses on FIFOs, places the transmit channel in mute mode." /> + <BitField start="4" size="1" name="RESET" description="When 1, asynchronously reset the transmit channel and FIFO." /> + <BitField start="5" size="1" name="WS_SEL" description="When 0, the interface is in master mode. When 1, the interface is in slave mode. See Section 34.7.2 for a summary of useful combinations for this bit with RXMODE." /> + <BitField start="6" size="9" name="WS_HALFPERIOD" description="Word select half period minus 1, i.e. WS 64clk period -> ws_halfperiod = 31." /> + <BitField start="15" size="17" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x008" size="4" name="TXFIFO" access="WriteOnly" description="I2S Transmit FIFO. Access register for the 8 x 32-bit transmitter FIFO." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="I2STXFIFO" description="8 x 32-bit transmit FIFO." /> + </Register> + <Register start="+0x00C" size="4" name="RXFIFO" access="None" description="I2S Receive FIFO. Access register for the 8 x 32-bit receiver FIFO." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="I2SRXFIFO" description="8 x 32-bit transmit FIFO." /> + </Register> + <Register start="+0x010" size="4" name="STATE" access="ReadOnly" description="I2S Status Feedback Register. Contains status information about the I2S interface." reset_value="0x7" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="IRQ" description="This bit reflects the presence of Receive Interrupt or Transmit Interrupt. This is determined by comparing the current FIFO levels to the rx_depth_irq and tx_depth_irq fields in the IRQ register." /> + <BitField start="1" size="1" name="DMAREQ1" description="This bit reflects the presence of Receive or Transmit DMA Request 1. This is determined by comparing the current FIFO levels to the rx_depth_dma1 and tx_depth_dma1 fields in the DMA1 register." /> + <BitField start="2" size="1" name="DMAREQ2" description="This bit reflects the presence of Receive or Transmit DMA Request 2. This is determined by comparing the current FIFO levels to the rx_depth_dma2 and tx_depth_dma2 fields in the DMA2 register." /> + <BitField start="3" size="5" name="RESERVED" description="Reserved." /> + <BitField start="8" size="4" name="RX_LEVEL" description="Reflects the current level of the Receive FIFO." /> + <BitField start="12" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + <BitField start="16" size="4" name="TX_LEVEL" description="Reflects the current level of the Transmit FIFO." /> + <BitField start="20" size="12" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x014" size="4" name="DMA1" access="Read/Write" description="I2S DMA Configuration Register 1. Contains control information for DMA request 1." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RX_DMA1_ENABLE" description="When 1, enables DMA1 for I2S receive." /> + <BitField start="1" size="1" name="TX_DMA1_ENABLE" description="When 1, enables DMA1 for I2S transmit." /> + <BitField start="2" size="6" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + <BitField start="8" size="4" name="RX_DEPTH_DMA1" description="Set the FIFO level that triggers a receive DMA request on DMA1." /> + <BitField start="12" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + <BitField start="16" size="4" name="TX_DEPTH_DMA1" description="Set the FIFO level that triggers a transmit DMA request on DMA1." /> + <BitField start="20" size="12" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x018" size="4" name="DMA2" access="Read/Write" description="I2S DMA Configuration Register 2. Contains control information for DMA request 2." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RX_DMA2_ENABLE" description="When 1, enables DMA1 for I2S receive." /> + <BitField start="1" size="1" name="TX_DMA2_ENABLE" description="When 1, enables DMA1 for I2S transmit." /> + <BitField start="2" size="6" name="RESERVED" description="Reserved." /> + <BitField start="8" size="4" name="RX_DEPTH_DMA2" description="Set the FIFO level that triggers a receive DMA request on DMA2." /> + <BitField start="12" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + <BitField start="16" size="4" name="TX_DEPTH_DMA2" description="Set the FIFO level that triggers a transmit DMA request on DMA2." /> + <BitField start="20" size="12" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x01C" size="4" name="IRQ" access="Read/Write" description="I2S Interrupt Request Control Register. Contains bits that control how the I2S interrupt request is generated." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RX_IRQ_ENABLE" description="When 1, enables I2S receive interrupt." /> + <BitField start="1" size="1" name="TX_IRQ_ENABLE" description="When 1, enables I2S transmit interrupt." /> + <BitField start="2" size="6" name="RESERVED" description="Reserved." /> + <BitField start="8" size="4" name="RX_DEPTH_IRQ" description="Set the FIFO level on which to create an irq request." /> + <BitField start="12" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + <BitField start="16" size="4" name="TX_DEPTH_IRQ" description="Set the FIFO level on which to create an irq request." /> + <BitField start="20" size="12" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x020" size="4" name="TXRATE" access="Read/Write" description="I2S Transmit MCLK divider. This register determines the I2S TX MCLK rate by specifying the value to divide PCLK by in order to produce MCLK." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="Y_DIVIDER" description="I2S transmit MCLK rate denominator. This value is used to divide PCLK to produce the transmit MCLK. Eight bits of fractional divide supports a wide range of possibilities. A value of 0 stops the clock." /> + <BitField start="8" size="8" name="X_DIVIDER" description="I2S transmit MCLK rate numerator. This value is used to multiply PCLK by to produce the transmit MCLK. A value of 0 stops the clock. Eight bits of fractional divide supports a wide range of possibilities. Note: the resulting ratio X/Y is divided by 2." /> + <BitField start="16" size="16" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x024" size="4" name="RXRATE" access="Read/Write" description="I2S Receive MCLK divider. This register determines the I2S RX MCLK rate by specifying the value to divide PCLK by in order to produce MCLK." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="Y_DIVIDER" description="I2S receive MCLK rate denominator. This value is used to divide PCLK to produce the receive MCLK. Eight bits of fractional divide supports a wide range of possibilities. A value of 0 stops the clock." /> + <BitField start="8" size="8" name="X_DIVIDER" description="I2S receive MCLK rate numerator. This value is used to multiply PCLK by to produce the receive MCLK. A value of 0 stops the clock. Eight bits of fractional divide supports a wide range of possibilities. Note: the resulting ratio X/Y is divided by 2." /> + <BitField start="16" size="16" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x028" size="4" name="TXBITRATE" access="Read/Write" description="I2S Transmit bit rate divider. This register determines the I2S transmit bit rate by specifying the value to divide TX_MCLK by in order to produce the transmit bit clock." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="6" name="TX_BITRATE" description="I2S transmit bit rate. This value plus one is used to divide TX_MCLK to produce the transmit bit clock." /> + <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x02C" size="4" name="RXBITRATE" access="Read/Write" description="I2S Receive bit rate divider. This register determines the I2S receive bit rate by specifying the value to divide RX_MCLK by in order to produce the receive bit clock." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="6" name="RX_BITRATE" description="I2S receive bit rate. This value plus one is used to divide RX_MCLK to produce the receive bit clock." /> + <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x030" size="4" name="TXMODE" access="Read/Write" description="I2S Transmit mode control." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="TXCLKSEL" description="Clock source selection for the transmit bit clock divider."> + <Enum name="SELECT_THE_TX_FRACTI" start="0x0" description="Select the TX fractional rate divider clock output as the source" /> + <Enum name="SELECT_THE_RX_MCLK_S" start="0x2" description="Select the RX_MCLK signal as the TX_MCLK clock source" /> + </BitField> + <BitField start="2" size="1" name="TX4PIN" description="Transmit 4-pin mode selection. When 1, enables 4-pin mode." /> + <BitField start="3" size="1" name="TXMCENA" description="Enable for the TX_MCLK output. When 0, output of TX_MCLK is not enabled. When 1, output of TX_MCLK is enabled." /> + <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x034" size="4" name="RXMODE" access="Read/Write" description="I2S Receive mode control." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="RXCLKSEL" description="Clock source selection for the receive bit clock divider."> + <Enum name="SELECT_THE_RX_FRACTI" start="0x0" description="Select the RX fractional rate divider clock output as the source" /> + <Enum name="SELECT_THE_TX_MCLK_S" start="0x2" description="Select the TX_MCLK signal as the RX_MCLK clock source" /> + </BitField> + <BitField start="2" size="1" name="RX4PIN" description="Receive 4-pin mode selection. When 1, enables 4-pin mode." /> + <BitField start="3" size="1" name="RXMCENA" description="Enable for the RX_MCLK output. When 0, output of RX_MCLK is not enabled. When 1, output of RX_MCLK is enabled." /> + <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + </RegisterGroup> + <RegisterGroup name="RITIMER" start="0x400B0000" description="Repetitive Interrupt Timer (RIT) "> + <Register start="+0x000" size="4" name="COMPVAL" access="Read/Write" description="Compare register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="RICOMP" description="Compare register. Holds the compare value which is compared to the counter." /> + </Register> + <Register start="+0x004" size="4" name="MASK" access="Read/Write" description="Mask register. This register holds the 32-bit mask value. A 1 written to any bit will force a compare on the corresponding bit of the counter and compare register." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="RIMASK" description="Mask register. This register holds the 32-bit mask value. A one written to any bit overrides the result of the comparison for the corresponding bit of the counter and compare register (causes the comparison of the register bits to be always true)." /> + </Register> + <Register start="+0x008" size="4" name="CTRL" access="Read/Write" description="Control register." reset_value="0xC" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RITINT" description="Interrupt flag"> + <Enum name="THIS_BIT_IS_SET_TO_1" start="1" description="This bit is set to 1 by hardware whenever the counter value equals the masked compare value specified by the contents of RICOMPVAL and RIMASK registers. Writing a 1 to this bit will clear it to 0. Writing a 0 has no effect." /> + <Enum name="THE_COUNTER_VALUE_DO" start="0" description="The counter value does not equal the masked compare value." /> + </BitField> + <BitField start="1" size="1" name="RITENCLR" description="Timer enable clear"> + <Enum name="THE_TIMER_WILL_BE_CL" start="1" description="The timer will be cleared to 0 whenever the counter value equals the masked compare value specified by the contents of RICOMPVAL and RIMASK registers. This will occur on the same clock that sets the interrupt flag." /> + <Enum name="THE_TIMER_WILL_NOT_B" start="0" description="The timer will not be cleared to 0." /> + </BitField> + <BitField start="2" size="1" name="RITENBR" description="Timer enable for debug"> + <Enum name="THE_TIMER_IS_HALTED_" start="1" description="The timer is halted when the processor is halted for debugging." /> + <Enum name="DEBUG_HAS_NO_EFFECT_" start="0" description="Debug has no effect on the timer operation." /> + </BitField> + <BitField start="3" size="1" name="RITEN" description="Timer enable."> + <Enum name="TIMER_ENABLED_THIS_" start="1" description="Timer enabled. This can be overruled by a debug halt if enabled in bit 2." /> + <Enum name="TIMER_DISABLED_" start="0" description="Timer disabled." /> + </BitField> + <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x00C" size="4" name="COUNTER" access="Read/Write" description="32-bit counter" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="RICOUNTER" description="32-bit up counter. Counts continuously unless RITEN bit in RICTRL register is cleared or debug mode is entered (if enabled by the RITNEBR bit in RICTRL). Can be loaded to any value in software." /> + </Register> + </RegisterGroup> + <RegisterGroup name="MCPWM" start="0x400B8000" description="Motor Control PWM"> + <Register start="+0x000" size="4" name="CON" access="ReadOnly" description="PWM Control read address" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RUN0" description="Stops/starts timer channel 0."> + <Enum name="STOP_" start="0" description="Stop." /> + <Enum name="RUN_" start="1" description="Run." /> + </BitField> + <BitField start="1" size="1" name="CENTER0" description="Edge/center aligned operation for channel 0."> + <Enum name="EDGE_ALIGNED_" start="0" description="Edge-aligned." /> + <Enum name="CENTER_ALIGNED_" start="1" description="Center-aligned." /> + </BitField> + <BitField start="2" size="1" name="POLA0" description="Selects polarity of the MCOA0 and MCOB0 pins."> + <Enum name="PASSIVE_STATE_IS_LOW" start="0" description="Passive state is LOW, active state is HIGH." /> + <Enum name="PASSIVE_STATE_IS_HIG" start="1" description="Passive state is HIGH, active state is LOW." /> + </BitField> + <BitField start="3" size="1" name="DTE0" description="Controls the dead-time feature for channel 0."> + <Enum name="DEAD_TIME_DISABLED_" start="0" description="Dead-time disabled." /> + <Enum name="DEAD_TIME_ENABLED_" start="1" description="Dead-time enabled." /> + </BitField> + <BitField start="4" size="1" name="DISUP0" description="Enable/disable updates of functional registers for channel 0 (see Section 24.8.2)."> + <Enum name="UPDATE" start="0" description="Functional registers are updated from the write registers at the end of each PWM cycle." /> + <Enum name="NOUPDATE" start="1" description="Functional registers remain the same as long as the timer is running." /> + </BitField> + <BitField start="5" size="3" name="RESERVED" description="Reserved." /> + <BitField start="8" size="1" name="RUN1" description="Stops/starts timer channel 1."> + <Enum name="STOP_" start="0" description="Stop." /> + <Enum name="RUN_" start="1" description="Run." /> + </BitField> + <BitField start="9" size="1" name="CENTER1" description="Edge/center aligned operation for channel 1."> + <Enum name="EDGE_ALIGNED_" start="0" description="Edge-aligned." /> + <Enum name="CENTER_ALIGNED_" start="1" description="Center-aligned." /> + </BitField> + <BitField start="10" size="1" name="POLA1" description="Selects polarity of the MCOA1 and MCOB1 pins."> + <Enum name="PASSIVE_STATE_IS_LOW" start="0" description="Passive state is LOW, active state is HIGH." /> + <Enum name="PASSIVE_STATE_IS_HIG" start="1" description="Passive state is HIGH, active state is LOW." /> + </BitField> + <BitField start="11" size="1" name="DTE1" description="Controls the dead-time feature for channel 1."> + <Enum name="DEAD_TIME_DISABLED_" start="0" description="Dead-time disabled." /> + <Enum name="DEAD_TIME_ENABLED_" start="1" description="Dead-time enabled." /> + </BitField> + <BitField start="12" size="1" name="DISUP1" description="Enable/disable updates of functional registers for channel 1 (see Section 24.8.2)."> + <Enum name="UPDATE" start="0" description="Functional registers are updated from the write registers at the end of each PWM cycle." /> + <Enum name="NOUPDATE" start="1" description="Functional registers remain the same as long as the timer is running." /> + </BitField> + <BitField start="13" size="3" name="RESERVED" description="Reserved." /> + <BitField start="16" size="1" name="RUN2" description="Stops/starts timer channel 2."> + <Enum name="STOP_" start="0" description="Stop." /> + <Enum name="RUN_" start="1" description="Run." /> + </BitField> + <BitField start="17" size="1" name="CENTER2" description="Edge/center aligned operation for channel 2."> + <Enum name="EDGE_ALIGNED_" start="0" description="Edge-aligned." /> + <Enum name="CENTER_ALIGNED_" start="1" description="Center-aligned." /> + </BitField> + <BitField start="18" size="1" name="POLA2" description="Selects polarity of the MCOA2 and MCOB2 pins."> + <Enum name="PASSIVE_STATE_IS_LOW" start="0" description="Passive state is LOW, active state is HIGH." /> + <Enum name="PASSIVE_STATE_IS_HIG" start="1" description="Passive state is HIGH, active state is LOW." /> + </BitField> + <BitField start="19" size="1" name="DTE2" description="Controls the dead-time feature for channel 1."> + <Enum name="DEAD_TIME_DISABLED_" start="0" description="Dead-time disabled." /> + <Enum name="DEAD_TIME_ENABLED_" start="1" description="Dead-time enabled." /> + </BitField> + <BitField start="20" size="1" name="DISUP2" description="Enable/disable updates of functional registers for channel 2 (see Section 24.8.2)."> + <Enum name="UPDATE" start="0" description="Functional registers are updated from the write registers at the end of each PWM cycle." /> + <Enum name="NOUPDATE" start="1" description="Functional registers remain the same as long as the timer is running." /> + </BitField> + <BitField start="21" size="8" name="RESERVED" description="Reserved." /> + <BitField start="29" size="1" name="INVBDC" description="Controls the polarity of the MCOB outputs for all 3 channels. This bit is typically set to 1 only in 3-phase DC mode."> + <Enum name="OPPOSITE" start="0" description="The MCOB outputs have opposite polarity from the MCOA outputs (aside from dead time)." /> + <Enum name="SAME" start="1" description="The MCOB outputs have the same basic polarity as the MCOA outputs. (see Section 24.8.6)" /> + </BitField> + <BitField start="30" size="1" name="ACMODE" description="3-phase AC mode select (see Section 24.8.7)."> + <Enum name="3_PHASE_AC_MODE_OFF" start="0" description="3-phase AC-mode off: Each PWM channel uses its own timer-counter and period register." /> + <Enum name="3_PHASE_AC_MODE_ON_" start="1" description="3-phase AC-mode on: All PWM channels use the timer-counter and period register of channel 0." /> + </BitField> + <BitField start="31" size="1" name="DCMODE" description="3-phase DC mode select (see Section 24.8.6)."> + <Enum name="3_PHASE_DC_MODE_OFF" start="0" description="3-phase DC mode off: PWM channels are independent (unless bit ACMODE = 1)" /> + <Enum name="3_PHASE_DC_MODE_ON_" start="1" description="3-phase DC mode on: The internal MCOA0 output is routed through the CP register (i.e. a mask) register to all six PWM outputs." /> + </BitField> + </Register> + <Register start="+0x004" size="4" name="CON_SET" access="WriteOnly" description="PWM Control set address" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="RUN0_SET" description="Writing a one sets the corresponding bit in the CON register." /> + <BitField start="1" size="1" name="CENTER0_SET" description="Writing a one sets the corresponding bit in the CON register." /> + <BitField start="2" size="1" name="POLA0_SET" description="Writing a one sets the corresponding bit in the CON register." /> + <BitField start="3" size="1" name="DTE0_SET" description="Writing a one sets the corresponding bit in the CON register." /> + <BitField start="4" size="1" name="DISUP0_SET" description="Writing a one sets the corresponding bit in the CON register." /> + <BitField start="5" size="3" name="RESERVED" description="Writing a one sets the corresponding bit in the CON register." /> + <BitField start="8" size="1" name="RUN1_SET" description="Writing a one sets the corresponding bit in the CON register." /> + <BitField start="9" size="1" name="CENTER1_SET" description="Writing a one sets the corresponding bit in the CON register." /> + <BitField start="10" size="1" name="POLA1_SET" description="Writing a one sets the corresponding bit in the CON register." /> + <BitField start="11" size="1" name="DTE1_SET" description="Writing a one sets the corresponding bit in the CON register." /> + <BitField start="12" size="1" name="DISUP1_SET" description="Writing a one sets the corresponding bit in the CON register." /> + <BitField start="13" size="3" name="RESERVED" description="Writing a one sets the corresponding bit in the CON register." /> + <BitField start="16" size="1" name="RUN2_SET" description="Writing a one sets the corresponding bit in the CON register." /> + <BitField start="17" size="1" name="CENTER2_SET" description="Writing a one sets the corresponding bit in the CON register." /> + <BitField start="18" size="1" name="POLA2_SET" description="Writing a one sets the corresponding bit in the CON register." /> + <BitField start="19" size="1" name="DTE2_SET" description="Writing a one sets the corresponding bit in the CON register." /> + <BitField start="20" size="1" name="DISUP2_SET" description="Writing a one sets the corresponding bit in the CON register." /> + <BitField start="21" size="8" name="RESERVED" description="Writing a one sets the corresponding bit in the CON register." /> + <BitField start="29" size="1" name="INVBDC_SET" description="Writing a one sets the corresponding bit in the CON register." /> + <BitField start="30" size="1" name="ACMODE_SET" description="Writing a one sets the corresponding bit in the CON register." /> + <BitField start="31" size="1" name="DCMODE_SET" description="Writing a one sets the corresponding bit in the CON register." /> + </Register> + <Register start="+0x008" size="4" name="CON_CLR" access="WriteOnly" description="PWM Control clear address" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="RUN0_CLR" description="Writing a one clears the corresponding bit in the CON register." /> + <BitField start="1" size="1" name="CENTER0_CLR" description="Writing a one clears the corresponding bit in the CON register." /> + <BitField start="2" size="1" name="POLA0_CLR" description="Writing a one clears the corresponding bit in the CON register." /> + <BitField start="3" size="1" name="DTE0_CLR" description="Writing a one clears the corresponding bit in the CON register." /> + <BitField start="4" size="1" name="DISUP0_CLR" description="Writing a one clears the corresponding bit in the CON register." /> + <BitField start="5" size="3" name="RESERVED" description="Writing a one clears the corresponding bit in the CON register." /> + <BitField start="8" size="1" name="RUN1_CLR" description="Writing a one clears the corresponding bit in the CON register." /> + <BitField start="9" size="1" name="CENTER1_CLR" description="Writing a one clears the corresponding bit in the CON register." /> + <BitField start="10" size="1" name="POLA1_CLR" description="Writing a one clears the corresponding bit in the CON register." /> + <BitField start="11" size="1" name="DTE1_CLR" description="Writing a one clears the corresponding bit in the CON register." /> + <BitField start="12" size="1" name="DISUP1_CLR" description="Writing a one clears the corresponding bit in the CON register." /> + <BitField start="13" size="3" name="RESERVED" description="Writing a one clears the corresponding bit in the CON register." /> + <BitField start="16" size="1" name="RUN2_CLR" description="Writing a one clears the corresponding bit in the CON register." /> + <BitField start="17" size="1" name="CENTER2_CLR" description="Writing a one clears the corresponding bit in the CON register." /> + <BitField start="18" size="1" name="POLA2_CLR" description="Writing a one clears the corresponding bit in the CON register." /> + <BitField start="19" size="1" name="DTE2_CLR" description="Writing a one clears the corresponding bit in the CON register." /> + <BitField start="20" size="1" name="DISUP2_CLR" description="Writing a one clears the corresponding bit in the CON register." /> + <BitField start="21" size="8" name="RESERVED" description="Writing a one clears the corresponding bit in the CON register." /> + <BitField start="29" size="1" name="INVBDC_CLR" description="Writing a one clears the corresponding bit in the CON register." /> + <BitField start="30" size="1" name="ACMOD_CLR" description="Writing a one clears the corresponding bit in the CON register." /> + <BitField start="31" size="1" name="DCMODE_CLR" description="Writing a one clears the corresponding bit in the CON register." /> + </Register> + <Register start="+0x00C" size="4" name="CAPCON" access="ReadOnly" description="Capture Control read address" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="CAP0MCI0_RE" description="A 1 in this bit enables a channel 0 capture event on a rising edge on MCI0." /> + <BitField start="1" size="1" name="CAP0MCI0_FE" description="A 1 in this bit enables a channel 0 capture event on a falling edge on MCI0." /> + <BitField start="2" size="1" name="CAP0MCI1_RE" description="A 1 in this bit enables a channel 0 capture event on a rising edge on MCI1." /> + <BitField start="3" size="1" name="CAP0MCI1_FE" description="A 1 in this bit enables a channel 0 capture event on a falling edge on MCI1." /> + <BitField start="4" size="1" name="CAP0MCI2_RE" description="A 1 in this bit enables a channel 0 capture event on a rising edge on MCI2." /> + <BitField start="5" size="1" name="CAP0MCI2_FE" description="A 1 in this bit enables a channel 0 capture event on a falling edge on MCI2." /> + <BitField start="6" size="1" name="CAP1MCI0_RE" description="A 1 in this bit enables a channel 1 capture event on a rising edge on MCI0." /> + <BitField start="7" size="1" name="CAP1MCI0_FE" description="A 1 in this bit enables a channel 1 capture event on a falling edge on MCI0." /> + <BitField start="8" size="1" name="CAP1MCI1_RE" description="A 1 in this bit enables a channel 1 capture event on a rising edge on MCI1." /> + <BitField start="9" size="1" name="CAP1MCI1_FE" description="A 1 in this bit enables a channel 1 capture event on a falling edge on MCI1." /> + <BitField start="10" size="1" name="CAP1MCI2_RE" description="A 1 in this bit enables a channel 1 capture event on a rising edge on MCI2." /> + <BitField start="11" size="1" name="CAP1MCI2_FE" description="A 1 in this bit enables a channel 1 capture event on a falling edge on MCI2." /> + <BitField start="12" size="1" name="CAP2MCI0_RE" description="A 1 in this bit enables a channel 2 capture event on a rising edge on MCI0." /> + <BitField start="13" size="1" name="CAP2MCI0_FE" description="A 1 in this bit enables a channel 2 capture event on a falling edge on MCI0." /> + <BitField start="14" size="1" name="CAP2MCI1_RE" description="A 1 in this bit enables a channel 2 capture event on a rising edge on MCI1." /> + <BitField start="15" size="1" name="CAP2MCI1_FE" description="A 1 in this bit enables a channel 2 capture event on a falling edge on MCI1." /> + <BitField start="16" size="1" name="CAP2MCI2_RE" description="A 1 in this bit enables a channel 2 capture event on a rising edge on MCI2." /> + <BitField start="17" size="1" name="CAP2MCI2_FE" description="A 1 in this bit enables a channel 2 capture event on a falling edge on MCI2." /> + <BitField start="18" size="1" name="RT0" description="If this bit is 1, TC0 is reset by a channel 0 capture event." /> + <BitField start="19" size="1" name="RT1" description="If this bit is 1, TC1 is reset by a channel 1 capture event." /> + <BitField start="20" size="1" name="RT2" description="If this bit is 1, TC2 is reset by a channel 2 capture event." /> + <BitField start="21" size="11" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x010" size="4" name="CAPCON_SET" access="WriteOnly" description="Capture Control set address" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="CAP0MCI0_RE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." /> + <BitField start="1" size="1" name="CAP0MCI0_FE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." /> + <BitField start="2" size="1" name="CAP0MCI1_RE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." /> + <BitField start="3" size="1" name="CAP0MCI1_FE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." /> + <BitField start="4" size="1" name="CAP0MCI2_RE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." /> + <BitField start="5" size="1" name="CAP0MCI2_FE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." /> + <BitField start="6" size="1" name="CAP1MCI0_RE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." /> + <BitField start="7" size="1" name="CAP1MCI0_FE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." /> + <BitField start="8" size="1" name="CAP1MCI1_RE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." /> + <BitField start="9" size="1" name="CAP1MCI1_FE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." /> + <BitField start="10" size="1" name="CAP1MCI2_RE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." /> + <BitField start="11" size="1" name="CAP1MCI2_FE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." /> + <BitField start="12" size="1" name="CAP2MCI0_RE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." /> + <BitField start="13" size="1" name="CAP2MCI0_FE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." /> + <BitField start="14" size="1" name="CAP2MCI1_RE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." /> + <BitField start="15" size="1" name="CAP2MCI1_FE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." /> + <BitField start="16" size="1" name="CAP2MCI2_RE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." /> + <BitField start="17" size="1" name="CAP2MCI2_FE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." /> + <BitField start="18" size="1" name="RT0_SET" description="Writing a one sets the corresponding bits in the CAPCON register." /> + <BitField start="19" size="1" name="RT1_SET" description="Writing a one sets the corresponding bits in the CAPCON register." /> + <BitField start="20" size="1" name="RT2_SET" description="Writing a one sets the corresponding bits in the CAPCON register." /> + <BitField start="21" size="11" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x014" size="4" name="CAPCON_CLR" access="WriteOnly" description="Event Control clear address" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="CAP0MCI0_RE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." /> + <BitField start="1" size="1" name="CAP0MCI0_FE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." /> + <BitField start="2" size="1" name="CAP0MCI1_RE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." /> + <BitField start="3" size="1" name="CAP0MCI1_FE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." /> + <BitField start="4" size="1" name="CAP0MCI2_RE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." /> + <BitField start="5" size="1" name="CAP0MCI2_FE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." /> + <BitField start="6" size="1" name="CAP1MCI0_RE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." /> + <BitField start="7" size="1" name="CAP1MCI0_FE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." /> + <BitField start="8" size="1" name="CAP1MCI1_RE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." /> + <BitField start="9" size="1" name="CAP1MCI1_FE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." /> + <BitField start="10" size="1" name="CAP1MCI2_RE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." /> + <BitField start="11" size="1" name="CAP1MCI2_FE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." /> + <BitField start="12" size="1" name="CAP2MCI0_RE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." /> + <BitField start="13" size="1" name="CAP2MCI0_FE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." /> + <BitField start="14" size="1" name="CAP2MCI1_RE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." /> + <BitField start="15" size="1" name="CAP2MCI1_FE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." /> + <BitField start="16" size="1" name="CAP2MCI2_RE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." /> + <BitField start="17" size="1" name="CAP2MCI2_FE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." /> + <BitField start="18" size="1" name="RT0_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." /> + <BitField start="19" size="1" name="RT1_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." /> + <BitField start="20" size="1" name="RT2_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." /> + <BitField start="21" size="11" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x018+0" size="4" name="TC[0]" access="Read/Write" description="Timer Counter register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="MCTC" description="Timer/Counter value." /> + </Register> + <Register start="+0x018+4" size="4" name="TC[1]" access="Read/Write" description="Timer Counter register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="MCTC" description="Timer/Counter value." /> + </Register> + <Register start="+0x018+8" size="4" name="TC[2]" access="Read/Write" description="Timer Counter register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="MCTC" description="Timer/Counter value." /> + </Register> + <Register start="+0x024+0" size="4" name="LIM[0]" access="Read/Write" description="Limit register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="MCLIM" description="Limit value." /> + </Register> + <Register start="+0x024+4" size="4" name="LIM[1]" access="Read/Write" description="Limit register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="MCLIM" description="Limit value." /> + </Register> + <Register start="+0x024+8" size="4" name="LIM[2]" access="Read/Write" description="Limit register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="MCLIM" description="Limit value." /> + </Register> + <Register start="+0x030+0" size="4" name="MAT[0]" access="Read/Write" description="Match register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="MCMAT" description="Match value." /> + </Register> + <Register start="+0x030+4" size="4" name="MAT[1]" access="Read/Write" description="Match register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="MCMAT" description="Match value." /> + </Register> + <Register start="+0x030+8" size="4" name="MAT[2]" access="Read/Write" description="Match register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="MCMAT" description="Match value." /> + </Register> + <Register start="+0x03C" size="4" name="DT" access="Read/Write" description="Dead time register" reset_value="0x3FFFFFFF" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="10" name="DT0" description="Dead time for channel 0.[1]" /> + <BitField start="10" size="10" name="DT1" description="Dead time for channel 1.[2]" /> + <BitField start="20" size="10" name="DT2" description="Dead time for channel 2.[2]" /> + <BitField start="30" size="2" name="RESERVED" description="reserved" /> + </Register> + <Register start="+0x040" size="4" name="CP" access="Read/Write" description="Communication Pattern register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="CCPA0" description="Communication pattern output A, channel 0."> + <Enum name="MCOA0_PASSIVE_" start="0" description="MCOA0 passive." /> + <Enum name="INTERNAL_MCOA0_" start="1" description="internal MCOA0." /> + </BitField> + <BitField start="1" size="1" name="CCPB0" description="Communication pattern output B, channel 0."> + <Enum name="MCOB0_PASSIVE_" start="0" description="MCOB0 passive." /> + <Enum name="MCOB0_TRACKS_INTERNA" start="1" description="MCOB0 tracks internal MCOA0." /> + </BitField> + <BitField start="2" size="1" name="CCPA1" description="Communication pattern output A, channel 1."> + <Enum name="MCOA1_PASSIVE_" start="0" description="MCOA1 passive." /> + <Enum name="MCOA1_TRACKS_INTERNA" start="1" description="MCOA1 tracks internal MCOA0." /> + </BitField> + <BitField start="3" size="1" name="CCPB1" description="Communication pattern output B, channel 1."> + <Enum name="MCOB1_PASSIVE_" start="0" description="MCOB1 passive." /> + <Enum name="MCOB1_TRACKS_INTERNA" start="1" description="MCOB1 tracks internal MCOA0." /> + </BitField> + <BitField start="4" size="1" name="CCPA2" description="Communication pattern output A, channel 2."> + <Enum name="MCOA2_PASSIVE_" start="0" description="MCOA2 passive." /> + <Enum name="MCOA2_TRACKS_INTERNA" start="1" description="MCOA2 tracks internal MCOA0." /> + </BitField> + <BitField start="5" size="1" name="CCPB2" description="Communication pattern output B, channel 2."> + <Enum name="MCOB2_PASSIVE_" start="0" description="MCOB2 passive." /> + <Enum name="MCOB2_TRACKS_INTERNA" start="1" description="MCOB2 tracks internal MCOA0." /> + </BitField> + <BitField start="6" size="26" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x044+0" size="4" name="CAP[0]" access="ReadOnly" description="Capture register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CAP" description="Current TC value at a capture event." /> + </Register> + <Register start="+0x044+4" size="4" name="CAP[1]" access="ReadOnly" description="Capture register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CAP" description="Current TC value at a capture event." /> + </Register> + <Register start="+0x044+8" size="4" name="CAP[2]" access="ReadOnly" description="Capture register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CAP" description="Current TC value at a capture event." /> + </Register> + <Register start="+0x050" size="4" name="INTEN" access="ReadOnly" description="Interrupt Enable read address" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="ILIM0" description="Limit interrupt for channel 0."> + <Enum name="INTERRUPT_DISABLED_" start="0" description="Interrupt disabled." /> + <Enum name="INTERRUPT_ENABLED_" start="1" description="Interrupt enabled." /> + </BitField> + <BitField start="1" size="1" name="IMAT0" description="Match interrupt for channel 0."> + <Enum name="INTERRUPT_DISABLED_" start="0" description="Interrupt disabled." /> + <Enum name="INTERRUPT_ENABLED_" start="1" description="Interrupt enabled." /> + </BitField> + <BitField start="2" size="1" name="ICAP0" description="Capture interrupt for channel 0."> + <Enum name="INTERRUPT_DISABLED_" start="0" description="Interrupt disabled." /> + <Enum name="INTERRUPT_ENABLED_" start="1" description="Interrupt enabled." /> + </BitField> + <BitField start="3" size="1" name="RESERVED" description="Reserved." /> + <BitField start="4" size="1" name="ILIM1" description="Limit interrupt for channel 1."> + <Enum name="INTERRUPT_DISABLED_" start="0" description="Interrupt disabled." /> + <Enum name="INTERRUPT_ENABLED_" start="1" description="Interrupt enabled." /> + </BitField> + <BitField start="5" size="1" name="IMAT1" description="Match interrupt for channel 1."> + <Enum name="INTERRUPT_DISABLED_" start="0" description="Interrupt disabled." /> + <Enum name="INTERRUPT_ENABLED_" start="1" description="Interrupt enabled." /> + </BitField> + <BitField start="6" size="1" name="ICAP1" description="Capture interrupt for channel 1."> + <Enum name="INTERRUPT_DISABLED_" start="0" description="Interrupt disabled." /> + <Enum name="INTERRUPT_ENABLED_" start="1" description="Interrupt enabled." /> + </BitField> + <BitField start="7" size="1" name="RESERVED" description="Reserved." /> + <BitField start="8" size="1" name="ILIM2" description="Limit interrupt for channel 2."> + <Enum name="INTERRUPT_DISABLED_" start="0" description="Interrupt disabled." /> + <Enum name="INTERRUPT_ENABLED_" start="1" description="Interrupt enabled." /> + </BitField> + <BitField start="9" size="1" name="IMAT2" description="Match interrupt for channel 2."> + <Enum name="INTERRUPT_DISABLED_" start="0" description="Interrupt disabled." /> + <Enum name="INTERRUPT_ENABLED_" start="1" description="Interrupt enabled." /> + </BitField> + <BitField start="10" size="1" name="ICAP2" description="Capture interrupt for channel 2."> + <Enum name="INTERRUPT_DISABLED_" start="0" description="Interrupt disabled." /> + <Enum name="INTERRUPT_ENABLED_" start="1" description="Interrupt enabled." /> + </BitField> + <BitField start="11" size="4" name="RESERVED" description="Reserved." /> + <BitField start="15" size="1" name="ABORT" description="Fast abort interrupt."> + <Enum name="INTERRUPT_DISABLED_" start="0" description="Interrupt disabled." /> + <Enum name="INTERRUPT_ENABLED_" start="1" description="Interrupt enabled." /> + </BitField> + <BitField start="16" size="16" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x054" size="4" name="INTEN_SET" access="WriteOnly" description="Interrupt Enable set address" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="ILIM0_SET" description="Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt." /> + <BitField start="1" size="1" name="IMAT0_SET" description="Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt." /> + <BitField start="2" size="1" name="ICAP0_SET" description="Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt." /> + <BitField start="3" size="1" name="RESERVED" description="Reserved." /> + <BitField start="4" size="1" name="ILIM1_SET" description="Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt." /> + <BitField start="5" size="1" name="IMAT1_SET" description="Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt." /> + <BitField start="6" size="1" name="ICAP1_SET" description="Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt." /> + <BitField start="7" size="1" name="RESERVED" description="Reserved." /> + <BitField start="9" size="1" name="ILIM2_SET" description="Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt." /> + <BitField start="10" size="1" name="IMAT2_SET" description="Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt." /> + <BitField start="11" size="1" name="ICAP2_SET" description="Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt." /> + <BitField start="12" size="3" name="RESERVED" description="Reserved." /> + <BitField start="15" size="1" name="ABORT_SET" description="Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt." /> + <BitField start="16" size="16" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x058" size="4" name="INTEN_CLR" access="WriteOnly" description="Interrupt Enable clear address" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="ILIM0_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." /> + <BitField start="1" size="1" name="IMAT0_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." /> + <BitField start="2" size="1" name="ICAP0_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." /> + <BitField start="3" size="1" name="RESERVED" description="Reserved." /> + <BitField start="4" size="1" name="ILIM1_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." /> + <BitField start="5" size="1" name="IMAT1_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." /> + <BitField start="6" size="1" name="ICAP1_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." /> + <BitField start="7" size="1" name="RESERVED" description="Reserved." /> + <BitField start="8" size="1" name="ILIM2_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." /> + <BitField start="9" size="1" name="IMAT2_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." /> + <BitField start="10" size="1" name="ICAP2_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." /> + <BitField start="11" size="4" name="RESERVED" description="Reserved." /> + <BitField start="15" size="1" name="ABORT_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." /> + <BitField start="16" size="16" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x068" size="4" name="INTF" access="ReadOnly" description="Interrupt flags read address" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="ILIM0_F" description="Limit interrupt flag for channel 0."> + <Enum name="THIS_INTERRUPT_SOURC" start="0" description="This interrupt source is not contributing to the MCPWM interrupt request." /> + <Enum name="IF_THE_CORRESPONDING" start="1" description="If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller." /> + </BitField> + <BitField start="1" size="1" name="IMAT0_F" description="Match interrupt flag for channel 0."> + <Enum name="THIS_INTERRUPT_SOURC" start="0" description="This interrupt source is not contributing to the MCPWM interrupt request." /> + <Enum name="IF_THE_CORRESPONDING" start="1" description="If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller." /> + </BitField> + <BitField start="2" size="1" name="ICAP0_F" description="Capture interrupt flag for channel 0."> + <Enum name="THIS_INTERRUPT_SOURC" start="0" description="This interrupt source is not contributing to the MCPWM interrupt request." /> + <Enum name="IF_THE_CORRESPONDING" start="1" description="If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller." /> + </BitField> + <BitField start="3" size="1" name="RESERVED" description="Reserved." /> + <BitField start="4" size="1" name="ILIM1_F" description="Limit interrupt flag for channel 1."> + <Enum name="THIS_INTERRUPT_SOURC" start="0" description="This interrupt source is not contributing to the MCPWM interrupt request." /> + <Enum name="IF_THE_CORRESPONDING" start="1" description="If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller." /> + </BitField> + <BitField start="5" size="1" name="IMAT1_F" description="Match interrupt flag for channel 1."> + <Enum name="THIS_INTERRUPT_SOURC" start="0" description="This interrupt source is not contributing to the MCPWM interrupt request." /> + <Enum name="IF_THE_CORRESPONDING" start="1" description="If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller." /> + </BitField> + <BitField start="6" size="1" name="ICAP1_F" description="Capture interrupt flag for channel 1."> + <Enum name="THIS_INTERRUPT_SOURC" start="0" description="This interrupt source is not contributing to the MCPWM interrupt request." /> + <Enum name="IF_THE_CORRESPONDING" start="1" description="If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller." /> + </BitField> + <BitField start="7" size="1" name="RESERVED" description="Reserved." /> + <BitField start="8" size="1" name="ILIM2_F" description="Limit interrupt flag for channel 2."> + <Enum name="THIS_INTERRUPT_SOURC" start="0" description="This interrupt source is not contributing to the MCPWM interrupt request." /> + <Enum name="IF_THE_CORRESPONDING" start="1" description="If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller." /> + </BitField> + <BitField start="9" size="1" name="IMAT2_F" description="Match interrupt flag for channel 2."> + <Enum name="THIS_INTERRUPT_SOURC" start="0" description="This interrupt source is not contributing to the MCPWM interrupt request." /> + <Enum name="IF_THE_CORRESPONDING" start="1" description="If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller." /> + </BitField> + <BitField start="10" size="1" name="ICAP2_F" description="Capture interrupt flag for channel 2."> + <Enum name="THIS_INTERRUPT_SOURC" start="0" description="This interrupt source is not contributing to the MCPWM interrupt request." /> + <Enum name="IF_THE_CORRESPONDING" start="1" description="If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller." /> + </BitField> + <BitField start="11" size="4" name="RESERVED" description="Reserved." /> + <BitField start="15" size="1" name="ABORT_F" description="Fast abort interrupt flag."> + <Enum name="THIS_INTERRUPT_SOURC" start="0" description="This interrupt source is not contributing to the MCPWM interrupt request." /> + <Enum name="IF_THE_CORRESPONDING" start="1" description="If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller." /> + </BitField> + <BitField start="16" size="16" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x06C" size="4" name="INTF_SET" access="WriteOnly" description="Interrupt flags set address" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="ILIM0_F_SET" description="Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt." /> + <BitField start="1" size="1" name="IMAT0_F_SET" description="Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt." /> + <BitField start="2" size="1" name="ICAP0_F_SET" description="Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt." /> + <BitField start="3" size="1" name="RESERVED" description="Reserved." /> + <BitField start="4" size="1" name="ILIM1_F_SET" description="Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt." /> + <BitField start="5" size="1" name="IMAT1_F_SET" description="Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt." /> + <BitField start="6" size="1" name="ICAP1_F_SET" description="Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt." /> + <BitField start="7" size="1" name="RESERVED" description="Reserved." /> + <BitField start="8" size="1" name="ILIM2_F_SET" description="Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt." /> + <BitField start="9" size="1" name="IMAT2_F_SET" description="Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt." /> + <BitField start="10" size="1" name="ICAP2_F_SET" description="Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt." /> + <BitField start="11" size="4" name="RESERVED" description="Reserved." /> + <BitField start="15" size="1" name="ABORT_F_SET" description="Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt." /> + <BitField start="16" size="16" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x070" size="4" name="INTF_CLR" access="WriteOnly" description="Interrupt flags clear address" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="ILIM0_F_CLR" description="Writing a one clears the corresponding bit in the INTF register, thus clearing the corresponding interrupt request." /> + <BitField start="1" size="1" name="IMAT0_F_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." /> + <BitField start="2" size="1" name="ICAP0_F_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." /> + <BitField start="3" size="1" name="RESERVED" description="Reserved." /> + <BitField start="4" size="1" name="ILIM1_F_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." /> + <BitField start="5" size="1" name="IMAT1_F_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." /> + <BitField start="6" size="1" name="ICAP1_F_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." /> + <BitField start="7" size="1" name="RESERVED" description="Reserved." /> + <BitField start="8" size="1" name="ILIM2_F_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." /> + <BitField start="9" size="1" name="IMAT2_F_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." /> + <BitField start="10" size="1" name="ICAP2_F_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." /> + <BitField start="11" size="4" name="RESERVED" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." /> + <BitField start="15" size="1" name="ABORT_F_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." /> + <BitField start="16" size="16" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x05C" size="4" name="CNTCON" access="ReadOnly" description="Count Control read address" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="TC0MCI0_RE" description="Counter 0 rising edge mode, channel 0."> + <Enum name="A_RISING_EDGE_ON_MCI" start="0" description="A rising edge on MCI0 does not affect counter 0." /> + <Enum name="RISING" start="1" description="If MODE0 is 1, counter 0 advances on a rising edge on MCI0." /> + </BitField> + <BitField start="1" size="1" name="TC0MCI0_FE" description="Counter 0 falling edge mode, channel 0."> + <Enum name="A_FALLING_EDGE_ON_MC" start="0" description="A falling edge on MCI0 does not affect counter 0." /> + <Enum name="FALLING" start="1" description="If MODE0 is 1, counter 0 advances on a falling edge on MCI0." /> + </BitField> + <BitField start="2" size="1" name="TC0MCI1_RE" description="Counter 0 rising edge mode, channel 1."> + <Enum name="A_RISING_EDGE_ON_MCI" start="0" description="A rising edge on MCI1 does not affect counter 0." /> + <Enum name="RISING" start="1" description="If MODE0 is 1, counter 0 advances on a rising edge on MCI1." /> + </BitField> + <BitField start="3" size="1" name="TC0MCI1_FE" description="Counter 0 falling edge mode, channel 1."> + <Enum name="A_FALLING_EDGE_ON_MC" start="0" description="A falling edge on MCI1 does not affect counter 0." /> + <Enum name="FALLING" start="1" description="If MODE0 is 1, counter 0 advances on a falling edge on MCI1." /> + </BitField> + <BitField start="4" size="1" name="TC0MCI2_RE" description="Counter 0 rising edge mode, channel 2."> + <Enum name="A_RISING_EDGE_ON_MCI" start="0" description="A rising edge on MCI0 does not affect counter 0." /> + <Enum name="RISING" start="1" description="If MODE0 is 1, counter 0 advances on a rising edge on MCI2." /> + </BitField> + <BitField start="5" size="1" name="TC0MCI2_FE" description="Counter 0 falling edge mode, channel 2."> + <Enum name="A_FALLING_EDGE_ON_MC" start="0" description="A falling edge on MCI0 does not affect counter 0." /> + <Enum name="FALLLING" start="1" description="If MODE0 is 1, counter 0 advances on a falling edge on MCI2." /> + </BitField> + <BitField start="6" size="1" name="TC1MCI0_RE" description="Counter 1 rising edge mode, channel 0."> + <Enum name="A_RISING_EDGE_ON_MCI" start="0" description="A rising edge on MCI0 does not affect counter 1." /> + <Enum name="RISING" start="1" description="If MODE1 is 1, counter 1 advances on a rising edge on MCI0." /> + </BitField> + <BitField start="7" size="1" name="TC1MCI0_FE" description="Counter 1 falling edge mode, channel 0."> + <Enum name="A_FALLING_EDGE_ON_MC" start="0" description="A falling edge on MCI0 does not affect counter 1." /> + <Enum name="FALLING" start="1" description="If MODE1 is 1, counter 1 advances on a falling edge on MCI0." /> + </BitField> + <BitField start="8" size="1" name="TC1MCI1_RE" description="Counter 1 rising edge mode, channel 1."> + <Enum name="A_RISING_EDGE_ON_MCI" start="0" description="A rising edge on MCI1 does not affect counter 1." /> + <Enum name="RISING" start="1" description="If MODE1 is 1, counter 1 advances on a rising edge on MCI1." /> + </BitField> + <BitField start="9" size="1" name="TC1MCI1_FE" description="Counter 1 falling edge mode, channel 1."> + <Enum name="A_FALLING_EDGE_ON_MC" start="0" description="A falling edge on MCI0 does not affect counter 1." /> + <Enum name="FALLING" start="1" description="If MODE1 is 1, counter 1 advances on a falling edge on MCI1." /> + </BitField> + <BitField start="10" size="1" name="TC1MCI2_RE" description="Counter 1 rising edge mode, channel 2."> + <Enum name="A_RISING_EDGE_ON_MCI" start="0" description="A rising edge on MCI2 does not affect counter 1." /> + <Enum name="RISING" start="1" description="If MODE1 is 1, counter 1 advances on a rising edge on MCI2." /> + </BitField> + <BitField start="11" size="1" name="TC1MCI2_FE" description="Counter 1 falling edge mode, channel 2."> + <Enum name="A_FALLING_EDGE_ON_MC" start="0" description="A falling edge on MCI2 does not affect counter 1." /> + <Enum name="FALLING" start="1" description="If MODE1 is 1, counter 1 advances on a falling edge on MCI2." /> + </BitField> + <BitField start="12" size="1" name="TC2MCI0_RE" description="Counter 2 rising edge mode, channel 0."> + <Enum name="A_RISING_EDGE_ON_MCI" start="0" description="A rising edge on MCI0 does not affect counter 2." /> + <Enum name="RISING" start="1" description="If MODE2 is 1, counter 2 advances on a rising edge on MCI0." /> + </BitField> + <BitField start="13" size="1" name="TC2MCI0_FE" description="Counter 2 falling edge mode, channel 0."> + <Enum name="A_FALLING_EDGE_ON_MC" start="0" description="A falling edge on MCI0 does not affect counter 2." /> + <Enum name="FALLING" start="1" description="If MODE2 is 1, counter 2 advances on a falling edge on MCI0." /> + </BitField> + <BitField start="14" size="1" name="TC2MCI1_RE" description="Counter 2 rising edge mode, channel 1."> + <Enum name="A_RISING_EDGE_ON_MCI" start="0" description="A rising edge on MCI1 does not affect counter 2." /> + <Enum name="RISING" start="1" description="If MODE2 is 1, counter 2 advances on a rising edge on MCI1." /> + </BitField> + <BitField start="15" size="1" name="TC2MCI1_FE" description="Counter 2 falling edge mode, channel 1."> + <Enum name="A_FALLING_EDGE_ON_MC" start="0" description="A falling edge on MCI1 does not affect counter 2." /> + <Enum name="FALLING" start="1" description="If MODE2 is 1, counter 2 advances on a falling edge on MCI1." /> + </BitField> + <BitField start="16" size="1" name="TC2MCI2_RE" description="Counter 2 rising edge mode, channel 2."> + <Enum name="A_RISING_EDGE_ON_MCI" start="0" description="A rising edge on MCI2 does not affect counter 2." /> + <Enum name="RISIING" start="1" description="If MODE2 is 1, counter 2 advances on a rising edge on MCI2." /> + </BitField> + <BitField start="17" size="1" name="TC2MCI2_FE" description="Counter 2 falling edge mode, channel 2."> + <Enum name="A_FALLING_EDGE_ON_MC" start="0" description="A falling edge on MCI2 does not affect counter 2." /> + <Enum name="FALLING" start="1" description="If MODE2 is 1, counter 2 advances on a falling edge on MCI2." /> + </BitField> + <BitField start="18" size="11" name="RESERVED" description="Reserved." /> + <BitField start="29" size="1" name="CNTR0" description="Channel 0 counter/timer mode."> + <Enum name="CHANNEL_0_IS_IN_TIME" start="0" description="Channel 0 is in timer mode." /> + <Enum name="CHANNEL_0_IS_IN_COUN" start="1" description="Channel 0 is in counter mode." /> + </BitField> + <BitField start="30" size="1" name="CNTR1" description="Channel 1 counter/timer mode."> + <Enum name="CHANNEL_1_IS_IN_TIME" start="0" description="Channel 1 is in timer mode." /> + <Enum name="CHANNEL_1_IS_IN_COUN" start="1" description="Channel 1 is in counter mode." /> + </BitField> + <BitField start="31" size="1" name="CNTR2" description="Channel 2 counter/timer mode."> + <Enum name="CHANNEL_2_IS_IN_TIME" start="0" description="Channel 2 is in timer mode." /> + <Enum name="CHANNEL_2_IS_IN_COUN" start="1" description="Channel 2 is in counter mode." /> + </BitField> + </Register> + <Register start="+0x060" size="4" name="CNTCON_SET" access="WriteOnly" description="Count Control set address" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="TC0MCI0_RE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." /> + <BitField start="1" size="1" name="TC0MCI0_FE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." /> + <BitField start="2" size="1" name="TC0MCI1_RE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." /> + <BitField start="3" size="1" name="TC0MCI1_FE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." /> + <BitField start="4" size="1" name="TC0MCI2_RE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." /> + <BitField start="5" size="1" name="TC0MCI2_FE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." /> + <BitField start="6" size="1" name="TC1MCI0_RE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." /> + <BitField start="7" size="1" name="TC1MCI0_FE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." /> + <BitField start="8" size="1" name="TC1MCI1_RE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." /> + <BitField start="9" size="1" name="TC1MCI1_FE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." /> + <BitField start="10" size="1" name="TC1MCI2_RE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." /> + <BitField start="11" size="1" name="TC1MCI2_FE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." /> + <BitField start="12" size="1" name="TC2MCI0_RE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." /> + <BitField start="13" size="1" name="TC2MCI0_FE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." /> + <BitField start="14" size="1" name="TC2MCI1_RE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." /> + <BitField start="15" size="1" name="TC2MCI1_FE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." /> + <BitField start="16" size="1" name="TC2MCI2_RE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." /> + <BitField start="17" size="1" name="TC2MCI2_FE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." /> + <BitField start="18" size="11" name="RESERVED" description="Reserved." /> + <BitField start="29" size="1" name="CNTR0_SET" description="Writing a one sets the corresponding bit in the CNTCON register." /> + <BitField start="30" size="1" name="CNTR1_SET" description="Writing a one sets the corresponding bit in the CNTCON register." /> + <BitField start="31" size="1" name="CNTR2_SET" description="Writing a one sets the corresponding bit in the CNTCON register." /> + </Register> + <Register start="+0x064" size="4" name="CNTCON_CLR" access="WriteOnly" description="Count Control clear address" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="TC0MCI0_RE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." /> + <BitField start="1" size="1" name="TC0MCI0_FE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." /> + <BitField start="2" size="1" name="TC0MCI1_RE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." /> + <BitField start="3" size="1" name="TC0MCI1_FE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." /> + <BitField start="4" size="1" name="TC0MCI2_RE" description="Writing a one clears the corresponding bit in the CNTCON register." /> + <BitField start="5" size="1" name="TC0MCI2_FE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." /> + <BitField start="6" size="1" name="TC1MCI0_RE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." /> + <BitField start="7" size="1" name="TC1MCI0_FE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." /> + <BitField start="8" size="1" name="TC1MCI1_RE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." /> + <BitField start="9" size="1" name="TC1MCI1_FE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." /> + <BitField start="10" size="1" name="TC1MCI2_RE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." /> + <BitField start="11" size="1" name="TC1MCI2_FE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." /> + <BitField start="12" size="1" name="TC2MCI0_RE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." /> + <BitField start="13" size="1" name="TC2MCI0_FE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." /> + <BitField start="14" size="1" name="TC2MCI1_RE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." /> + <BitField start="15" size="1" name="TC2MCI1_FE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." /> + <BitField start="16" size="1" name="TC2MCI2_RE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." /> + <BitField start="17" size="1" name="TC2MCI2_FE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." /> + <BitField start="18" size="11" name="RESERVED" description="Reserved." /> + <BitField start="29" size="1" name="CNTR0_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." /> + <BitField start="30" size="1" name="CNTR1_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." /> + <BitField start="31" size="1" name="CNTR2_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." /> + </Register> + <Register start="+0x074" size="4" name="CAP_CLR" access="WriteOnly" description="Capture clear address" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="CAP_CLR0" description="Writing a 1 to this bit clears the CAP0 register." /> + <BitField start="1" size="1" name="CAP_CLR1" description="Writing a 1 to this bit clears the CAP1 register." /> + <BitField start="2" size="1" name="CAP_CLR2" description="Writing a 1 to this bit clears the CAP2 register." /> + <BitField start="3" size="29" name="RESERVED" description="Reserved" /> + </Register> + </RegisterGroup> + <RegisterGroup name="QEI" start="0x400BC000" description="Quadrature Encoder Interface (QEI) "> + <Register start="+0x000" size="4" name="CON" access="WriteOnly" description="Control register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="RESP" description="Reset position counter. When set = 1, resets the position counter to all zeros. Autoclears when the position counter is cleared." /> + <BitField start="1" size="1" name="RESPI" description="Reset position counter on index. When set = 1, resets the position counter to all zeros once only the first time an index pulse occurs. Autoclears when the position counter is cleared." /> + <BitField start="2" size="1" name="RESV" description="Reset velocity. When set = 1, resets the velocity counter to all zeros, reloads the velocity timer, and presets the velocity compare register. Autoclears when the velocity counter is cleared." /> + <BitField start="3" size="1" name="RESI" description="Reset index counter. When set = 1, resets the index counter to all zeros. Autoclears when the index counter is cleared." /> + <BitField start="4" size="28" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x008" size="4" name="CONF" access="Read/Write" description="Configuration register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="DIRINV" description="Direction invert. When 1, complements the DIR bit." /> + <BitField start="1" size="1" name="SIGMODE" description="Signal Mode. When 0, PhA and PhB function as quadrature encoder inputs. When 1, PhA functions as the direction signal and PhB functions as the clock signal." /> + <BitField start="2" size="1" name="CAPMODE" description="Capture Mode. When 0, only PhA edges are counted (2X). When 1, BOTH PhA and PhB edges are counted (4X), increasing resolution but decreasing range." /> + <BitField start="3" size="1" name="INVINX" description="Invert Index. When 1, inverts the sense of the index input." /> + <BitField start="4" size="1" name="CRESPI" description="Continuously reset the position counter on index. When 1, resets the position counter to all zeros whenever an index pulse occurs after the next position increase (recalibration)." /> + <BitField start="5" size="11" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="16" size="4" name="INXGATE" description="Index gating configuration: When INXGATE[16] = 1, pass the index when PHA = 1 and PHB = 0, otherwise block index. When INXGATE[17] = 1, pass the index when PHA = 1 and PHB = 1, otherwise block index. When INXGATE[18] = 1, pass the index when PHA = 0 and PHB = 1, otherwise block index. When INXGATE[19] = 1, pass the index when PHA = 0 and PHB = 0, otherwise block index." /> + <BitField start="20" size="12" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x004" size="4" name="STAT" access="ReadOnly" description="Status register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="DIR" description="Direction bit. In combination with DIRINV bit indicates forward or reverse direction. See Table 597." /> + <BitField start="1" size="31" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x00C" size="4" name="POS" access="ReadOnly" description="Position register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="POS" description="Current position value." /> + </Register> + <Register start="+0x010" size="4" name="MAXPOS" access="Read/Write" description="Maximum position register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="MAXPOS" description="Current maximum position value." /> + </Register> + <Register start="+0x014" size="4" name="CMPOS0" access="Read/Write" description="Position compare register 0" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="PCMP0" description="Position compare value 0." /> + </Register> + <Register start="+0x018" size="4" name="CMPOS1" access="Read/Write" description="Position compare register 1" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="PCMP1" description="Position compare value 1." /> + </Register> + <Register start="+0x01C" size="4" name="CMPOS2" access="Read/Write" description="Position compare register 2" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="PCMP2" description="Position compare value 2." /> + </Register> + <Register start="+0x020" size="4" name="INXCNT" access="ReadOnly" description="Index count register 0" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="ENCPOS" description="Current index counter value." /> + </Register> + <Register start="+0x024" size="4" name="INXCMP0" access="Read/Write" description="Index compare register 0" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="ICMP0" description="Index compare value 0." /> + </Register> + <Register start="+0x028" size="4" name="LOAD" access="Read/Write" description="Velocity timer reload register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="VELLOAD" description="Current velocity timer load value." /> + </Register> + <Register start="+0x02C" size="4" name="TIME" access="ReadOnly" description="Velocity timer register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="VELVAL" description="Current velocity timer value." /> + </Register> + <Register start="+0x030" size="4" name="VEL" access="ReadOnly" description="Velocity counter register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="VELPC" description="Current velocity pulse count." /> + </Register> + <Register start="+0x034" size="4" name="CAP" access="ReadOnly" description="Velocity capture register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="VELCAP" description="Last velocity capture." /> + </Register> + <Register start="+0x038" size="4" name="VELCOMP" access="Read/Write" description="Velocity compare register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="VELPC" description="Compare velocity pulse count." /> + </Register> + <Register start="+0x03C" size="4" name="FILTER" access="Read/Write" description="Digital filter register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="FILTA" description="Digital filter sampling delay." /> + </Register> + <Register start="+0xFE0" size="4" name="INTSTAT" access="ReadOnly" description="Interrupt status register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="INX_INT" description="Indicates that an index pulse was detected." /> + <BitField start="1" size="1" name="TIM_INT" description="Indicates that a velocity timer overflow occurred" /> + <BitField start="2" size="1" name="VELC_INT" description="Indicates that captured velocity is less than compare velocity." /> + <BitField start="3" size="1" name="DIR_INT" description="Indicates that a change of direction was detected." /> + <BitField start="4" size="1" name="ERR_INT" description="Indicates that an encoder phase error was detected." /> + <BitField start="5" size="1" name="ENCLK_INT" description="Indicates that and encoder clock pulse was detected." /> + <BitField start="6" size="1" name="POS0_INT" description="Indicates that the position 0 compare value is equal to the current position." /> + <BitField start="7" size="1" name="POS1_INT" description="Indicates that the position 1compare value is equal to the current position." /> + <BitField start="8" size="1" name="POS2_INT" description="Indicates that the position 2 compare value is equal to the current position." /> + <BitField start="9" size="1" name="REV0_INT" description="Indicates that the index compare 0 value is equal to the current index count." /> + <BitField start="10" size="1" name="POS0REV_INT" description="Combined position 0 and revolution count interrupt. Set when both the POS0_Int bit is set and the REV0_Int is set." /> + <BitField start="11" size="1" name="POS1REV_INT" description="Combined position 1 and revolution count interrupt. Set when both the POS1_Int bit is set and the REV1_Int is set." /> + <BitField start="12" size="1" name="POS2REV_INT" description="Combined position 2 and revolution count interrupt. Set when both the POS2_Int bit is set and the REV2_Int is set." /> + <BitField start="13" size="1" name="REV1_INT" description="Indicates that the index compare 1value is equal to the current index count." /> + <BitField start="14" size="1" name="REV2_INT" description="Indicates that the index compare 2 value is equal to the current index count." /> + <BitField start="15" size="1" name="MAXPOS_INT" description="Indicates that the current position count goes through the MAXPOS value to zero in the forward direction, or through zero to MAXPOS in the reverse direction." /> + <BitField start="16" size="16" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0xFEC" size="4" name="SET" access="WriteOnly" description="Interrupt status set register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="INX_INT" description="Writing a 1 sets the INX_Int bit in QEIINTSTAT." /> + <BitField start="1" size="1" name="TIM_INT" description="Writing a 1 sets the TIN_Int bit in QEIINTSTAT." /> + <BitField start="2" size="1" name="VELC_INT" description="Writing a 1 sets the VELC_Int bit in QEIINTSTAT." /> + <BitField start="3" size="1" name="DIR_INT" description="Writing a 1 sets the DIR_Int bit in QEIINTSTAT." /> + <BitField start="4" size="1" name="ERR_INT" description="Writing a 1 sets the ERR_Int bit in QEIINTSTAT." /> + <BitField start="5" size="1" name="ENCLK_INT" description="Writing a 1 sets the ENCLK_Int bit in QEIINTSTAT." /> + <BitField start="6" size="1" name="POS0_INT" description="Writing a 1 sets the POS0_Int bit in QEIINTSTAT." /> + <BitField start="7" size="1" name="POS1_INT" description="Writing a 1 sets the POS1_Int bit in QEIINTSTAT." /> + <BitField start="8" size="1" name="POS2_INT" description="Writing a 1 sets the POS2_Int bit in QEIINTSTAT." /> + <BitField start="9" size="1" name="REV0_INT" description="Writing a 1 sets the REV0_Int bit in QEIINTSTAT." /> + <BitField start="10" size="1" name="POS0REV_INT" description="Writing a 1 sets the POS0REV_Int bit in QEIINTSTAT." /> + <BitField start="11" size="1" name="POS1REV_INT" description="Writing a 1 sets the POS1REV_Int bit in QEIINTSTAT." /> + <BitField start="12" size="1" name="POS2REV_INT" description="Writing a 1 sets the POS2REV_Int bit in QEIINTSTAT." /> + <BitField start="13" size="1" name="REV1_INT" description="Writing a 1 sets the REV1_Int bit in QEIINTSTAT." /> + <BitField start="14" size="1" name="REV2_INT" description="Writing a 1 sets the REV2_Int bit in QEIINTSTAT." /> + <BitField start="15" size="1" name="MAXPOS_INT" description="Writing a 1 sets the MAXPOS_Int bit in QEIINTSTAT." /> + <BitField start="16" size="16" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0xFE8" size="4" name="CLR" access="WriteOnly" description="Interrupt status clear register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="INX_INT" description="Writing a 1 clears the INX_Int bit in QEIINTSTAT." /> + <BitField start="1" size="1" name="TIM_INT" description="Writing a 1 clears the TIN_Int bit in QEIINTSTAT." /> + <BitField start="2" size="1" name="VELC_INT" description="Writing a 1 clears the VELC_Int bit in QEIINTSTAT." /> + <BitField start="3" size="1" name="DIR_INT" description="Writing a 1 clears the DIR_Int bit in QEIINTSTAT." /> + <BitField start="4" size="1" name="ERR_INT" description="Writing a 1 clears the ERR_Int bit in QEIINTSTAT." /> + <BitField start="5" size="1" name="ENCLK_INT" description="Writing a 1 clears the ENCLK_Int bit in QEIINTSTAT." /> + <BitField start="6" size="1" name="POS0_INT" description="Writing a 1 clears the POS0_Int bit in QEIINTSTAT." /> + <BitField start="7" size="1" name="POS1_INT" description="Writing a 1 clears the POS1_Int bit in QEIINTSTAT." /> + <BitField start="8" size="1" name="POS2_INT" description="Writing a 1 clears the POS2_Int bit in QEIINTSTAT." /> + <BitField start="9" size="1" name="REV0_INT" description="Writing a 1 clears the REV0_Int bit in QEIINTSTAT." /> + <BitField start="10" size="1" name="POS0REV_INT" description="Writing a 1 clears the POS0REV_Int bit in QEIINTSTAT." /> + <BitField start="11" size="1" name="POS1REV_INT" description="Writing a 1 clears the POS1REV_Int bit in QEIINTSTAT." /> + <BitField start="12" size="1" name="POS2REV_INT" description="Writing a 1 clears the POS2REV_Int bit in QEIINTSTAT." /> + <BitField start="13" size="1" name="REV1_INT" description="Writing a 1 clears the REV1_Int bit in QEIINTSTAT." /> + <BitField start="14" size="1" name="REV2_INT" description="Writing a 1 clears the REV2_Int bit in QEIINTSTAT." /> + <BitField start="15" size="1" name="MAXPOS_INT" description="Writing a 1 clears the MAXPOS_Int bit in QEIINTSTAT." /> + <BitField start="16" size="16" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0xFE4" size="4" name="IE" access="ReadOnly" description="Interrupt enable register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="INX_INT" description="When 1, the INX_Int interrupt is enabled." /> + <BitField start="1" size="1" name="TIM_INT" description="When 1, the TIN_Int interrupt is enabled." /> + <BitField start="2" size="1" name="VELC_INT" description="When 1, the VELC_Int interrupt is enabled." /> + <BitField start="3" size="1" name="DIR_INT" description="When 1, the DIR_Int interrupt is enabled." /> + <BitField start="4" size="1" name="ERR_INT" description="When 1, the ERR_Int interrupt is enabled." /> + <BitField start="5" size="1" name="ENCLK_INT" description="When 1, the ENCLK_Int interrupt is enabled." /> + <BitField start="6" size="1" name="POS0_INT" description="When 1, the POS0_Int interrupt is enabled." /> + <BitField start="7" size="1" name="POS1_INT" description="When 1, the POS1_Int interrupt is enabled." /> + <BitField start="8" size="1" name="POS2_INT" description="When 1, the POS2_Int interrupt is enabled." /> + <BitField start="9" size="1" name="REV0_INT" description="When 1, the REV0_Int interrupt is enabled." /> + <BitField start="10" size="1" name="POS0REV_INT" description="When 1, the POS0REV_Int interrupt is enabled." /> + <BitField start="11" size="1" name="POS1REV_INT" description="When 1, the POS1REV_Int interrupt is enabled." /> + <BitField start="12" size="1" name="POS2REV_INT" description="When 1, the POS2REV_Int interrupt is enabled." /> + <BitField start="13" size="1" name="REV1_INT" description="When 1, the REV1_Int interrupt is enabled." /> + <BitField start="14" size="1" name="REV2_INT" description="When 1, the REV2_Int interrupt is enabled." /> + <BitField start="15" size="1" name="MAXPOS_INT" description="When 1, the MAXPOS_Int interrupt is enabled." /> + <BitField start="16" size="16" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0xFDC" size="4" name="IES" access="WriteOnly" description="Interrupt enable set register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="INX_INT" description="Writing a 1 enables the INX_Int interrupt in the QEIIE register." /> + <BitField start="1" size="1" name="TIM_INT" description="Writing a 1 enables the TIN_Int interrupt in the QEIIE register." /> + <BitField start="2" size="1" name="VELC_INT" description="Writing a 1 enables the VELC_Int interrupt in the QEIIE register." /> + <BitField start="3" size="1" name="DIR_INT" description="Writing a 1 enables the DIR_Int interrupt in the QEIIE register." /> + <BitField start="4" size="1" name="ERR_INT" description="Writing a 1 enables the ERR_Int interrupt in the QEIIE register." /> + <BitField start="5" size="1" name="ENCLK_INT" description="Writing a 1 enables the ENCLK_Int interrupt in the QEIIE register." /> + <BitField start="6" size="1" name="POS0_INT" description="Writing a 1 enables the POS0_Int interrupt in the QEIIE register." /> + <BitField start="7" size="1" name="POS1_INT" description="Writing a 1 enables the POS1_Int interrupt in the QEIIE register." /> + <BitField start="8" size="1" name="POS2_INT" description="Writing a 1 enables the POS2_Int interrupt in the QEIIE register." /> + <BitField start="9" size="1" name="REV0_INT" description="Writing a 1 enables the REV0_Int interrupt in the QEIIE register." /> + <BitField start="10" size="1" name="POS0REV_INT" description="Writing a 1 enables the POS0REV_Int interrupt in the QEIIE register." /> + <BitField start="11" size="1" name="POS1REV_INT" description="Writing a 1 enables the POS1REV_Int interrupt in the QEIIE register." /> + <BitField start="12" size="1" name="POS2REV_INT" description="Writing a 1 enables the POS2REV_Int interrupt in the QEIIE register." /> + <BitField start="13" size="1" name="REV1_INT" description="Writing a 1 enables the REV1_Int interrupt in the QEIIE register." /> + <BitField start="14" size="1" name="REV2_INT" description="Writing a 1 enables the REV2_Int interrupt in the QEIIE register." /> + <BitField start="15" size="1" name="MAXPOS_INT" description="Writing a 1 enables the MAXPOS_Int interrupt in the QEIIE register." /> + <BitField start="16" size="16" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0xFD8" size="4" name="IEC" access="WriteOnly" description="Interrupt enable clear register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="INX_INT" description="Writing a 1 disables the INX_Int interrupt in the QEIIE register." /> + <BitField start="1" size="1" name="TIM_INT" description="Writing a 1 disables the TIN_Int interrupt in the QEIIE register." /> + <BitField start="2" size="1" name="VELC_INT" description="Writing a 1 disables the VELC_Int interrupt in the QEIIE register." /> + <BitField start="3" size="1" name="DIR_INT" description="Writing a 1 disables the DIR_Int interrupt in the QEIIE register." /> + <BitField start="4" size="1" name="ERR_INT" description="Writing a 1 disables the ERR_Int interrupt in the QEIIE register." /> + <BitField start="5" size="1" name="ENCLK_INT" description="Writing a 1 disables the ENCLK_Int interrupt in the QEIIE register." /> + <BitField start="6" size="1" name="POS0_INT" description="Writing a 1 disables the POS0_Int interrupt in the QEIIE register." /> + <BitField start="7" size="1" name="POS1_INT" description="Writing a 1 disables the POS1_Int interrupt in the QEIIE register." /> + <BitField start="8" size="1" name="POS2_INT" description="Writing a 1 disables the POS2_Int interrupt in the QEIIE register." /> + <BitField start="9" size="1" name="REV0_INT" description="Writing a 1 disables the REV0_Int interrupt in the QEIIE register." /> + <BitField start="10" size="1" name="POS0REV_INT" description="Writing a 1 disables the POS0REV_Int interrupt in the QEIIE register." /> + <BitField start="11" size="1" name="POS1REV_INT" description="Writing a 1 disables the POS1REV_Int interrupt in the QEIIE register." /> + <BitField start="12" size="1" name="POS2REV_INT" description="Writing a 1 disables the POS2REV_Int interrupt in the QEIIE register." /> + <BitField start="13" size="1" name="REV1_INT" description="Writing a 1 disables the REV1_Int interrupt in the QEIIE register." /> + <BitField start="14" size="1" name="REV2_INT" description="Writing a 1 disables the REV2_Int interrupt in the QEIIE register." /> + <BitField start="15" size="1" name="MAXPOS_INT" description="Writing a 1 disables the MAXPOS_Int interrupt in the QEIIE register." /> + <BitField start="16" size="16" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + </RegisterGroup> + <RegisterGroup name="SYSCON" start="0x400FC000" description="System and clock control"> + <Register start="+0x000" size="4" name="FLASHCFG" access="Read/Write" description="Flash Accelerator Configuration Register. Controls flash access timing." reset_value="0x303A" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="12" name="RESERVED" description="Reserved, user software should not change these bits from the reset value." /> + <BitField start="12" size="4" name="FLASHTIM" description="Flash access time. The value of this field plus 1 gives the number of CPU clocks used for a flash access. Warning: improper setting of this value may result in incorrect operation of the device. Other values are reserved."> + <Enum name="1CLK" start="0x0" description="Flash accesses use 1 CPU clock. Use for up to 20 MHz CPU clock." /> + <Enum name="2CLK" start="0x1" description="Flash accesses use 2 CPU clocks. Use for up to 40 MHz CPU clock." /> + <Enum name="3CLK" start="0x2" description="Flash accesses use 3 CPU clocks. Use for up to 60 MHz CPU clock." /> + <Enum name="4CLK" start="0x3" description="Flash accesses use 4 CPU clocks. Use for up to 80 MHz CPU clock." /> + <Enum name="5CLK" start="0x4" description="Flash accesses use 5 CPU clocks. Use for up to 100 MHz CPU clock. Use for up to 120 Mhz for LPC1759 and LPC1769 only." /> + <Enum name="6CLK" start="0x5" description="Flash accesses use 6 CPU clocks. This safe setting will work under any conditions." /> + </BitField> + <BitField start="16" size="16" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x080" size="4" name="PLL0CON" access="Read/Write" description="PLL0 Control Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="PLLE0" description="PLL0 Enable. When one, and after a valid PLL0 feed, this bit will activate PLL0 and allow it to lock to the requested frequency. See PLL0STAT register." /> + <BitField start="1" size="1" name="PLLC0" description="PLL0 Connect. Setting PLLC0 to one after PLL0 has been enabled and locked, then followed by a valid PLL0 feed sequence causes PLL0 to become the clock source for the CPU, AHB peripherals, and used to derive the clocks for APB peripherals. The PLL0 output may potentially be used to clock the USB subsystem if the frequency is 48 MHz. See PLL0STAT register." /> + <BitField start="2" size="30" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x084" size="4" name="PLL0CFG" access="Read/Write" description="PLL0 Configuration Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="15" name="MSEL0" description="PLL0 Multiplier value. Supplies the value M in PLL0 frequency calculations. The value stored here is M - 1. Note: Not all values of M are needed, and therefore some are not supported by hardware." /> + <BitField start="15" size="1" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + <BitField start="16" size="8" name="NSEL0" description="PLL0 Pre-Divider value. Supplies the value N in PLL0 frequency calculations. The value stored here is N - 1. Supported values for N are 1 through 32." /> + <BitField start="24" size="8" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x088" size="4" name="PLL0STAT" access="ReadOnly" description="PLL0 Status Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="15" name="MSEL0" description="Read-back for the PLL0 Multiplier value. This is the value currently used by PLL0, and is one less than the actual multiplier." /> + <BitField start="15" size="1" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + <BitField start="16" size="8" name="NSEL0" description="Read-back for the PLL0 Pre-Divider value. This is the value currently used by PLL0, and is one less than the actual divider." /> + <BitField start="24" size="1" name="PLLE0_STAT" description="Read-back for the PLL0 Enable bit. This bit reflects the state of the PLEC0 bit in PLL0CON after a valid PLL0 feed. When one, PLL0 is currently enabled. When zero, PLL0 is turned off. This bit is automatically cleared when Power-down mode is entered." /> + <BitField start="25" size="1" name="PLLC0_STAT" description="Read-back for the PLL0 Connect bit. This bit reflects the state of the PLLC0 bit in PLL0CON after a valid PLL0 feed. When PLLC0 and PLLE0 are both one, PLL0 is connected as the clock source for the CPU. When either PLLC0 or PLLE0 is zero, PLL0 is bypassed. This bit is automatically cleared when Power-down mode is entered." /> + <BitField start="26" size="1" name="PLOCK0" description="Reflects the PLL0 Lock status. When zero, PLL0 is not locked. When one, PLL0 is locked onto the requested frequency. See text for details." /> + <BitField start="27" size="5" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x08C" size="4" name="PLL0FEED" access="WriteOnly" description="PLL0 Feed Register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="8" name="PLL0FEED" description="The PLL0 feed sequence must be written to this register in order for PLL0 configuration and control register changes to take effect." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x0A0" size="4" name="PLL1CON" access="Read/Write" description="PLL1 Control Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="PLLE1" description="PLL1 Enable. When one, and after a valid PLL1 feed, this bit will activate PLL1 and allow it to lock to the requested frequency." /> + <BitField start="1" size="1" name="PLLC1" description="PLL1 Connect. Setting PLLC to one after PLL1 has been enabled and locked, then followed by a valid PLL1 feed sequence causes PLL1 to become the clock source for the USB subsystem via the USB clock divider. See PLL1STAT register." /> + <BitField start="2" size="30" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x0A4" size="4" name="PLL1CFG" access="Read/Write" description="PLL1 Configuration Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="MSEL1" description="PLL1 Multiplier value. Supplies the value M in the PLL1 frequency calculations." /> + <BitField start="5" size="2" name="PSEL1" description="PLL1 Divider value. Supplies the value P in the PLL1 frequency calculations." /> + <BitField start="7" size="25" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x0A8" size="4" name="PLL1STAT" access="ReadOnly" description="PLL1 Status Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="MSEL1" description="Read-back for the PLL1 Multiplier value. This is the value currently used by PLL1." /> + <BitField start="5" size="2" name="PSEL1" description="Read-back for the PLL1 Divider value. This is the value currently used by PLL1." /> + <BitField start="7" size="1" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + <BitField start="8" size="1" name="PLLE1_STAT" description="Read-back for the PLL1 Enable bit. When one, PLL1 is currently activated. When zero, PLL1 is turned off. This bit is automatically cleared when Power-down mode is activated." /> + <BitField start="9" size="1" name="PLLC1_STAT" description="Read-back for the PLL1 Connect bit. When PLLC and PLLE are both one, PLL1 is connected as the clock source for the microcontroller. When either PLLC or PLLE is zero, PLL1 is bypassed and the oscillator clock is used directly by the microcontroller. This bit is automatically cleared when Power-down mode is activated." /> + <BitField start="10" size="1" name="PLOCK1" description="Reflects the PLL1 Lock status. When zero, PLL1 is not locked. When one, PLL1 is locked onto the requested frequency." /> + <BitField start="11" size="21" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x0AC" size="4" name="PLL1FEED" access="WriteOnly" description="PLL1 Feed Register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="8" name="PLL1FEED" description="The PLL1 feed sequence must be written to this register in order for PLL1 configuration and control register changes to take effect." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x0C0" size="4" name="PCON" access="Read/Write" description="Power Control Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="PM0" description="Power mode control bit 0. This bit controls entry to the Power-down mode." /> + <BitField start="1" size="1" name="PM1" description="Power mode control bit 1. This bit controls entry to the Deep Power-down mode." /> + <BitField start="2" size="1" name="BODRPM" description="Brown-Out Reduced Power Mode. When BODRPM is 1, the Brown-Out Detect circuitry will be turned off when chip Power-down mode or Deep Sleep mode is entered, resulting in a further reduction in power usage. However, the possibility of using Brown-Out Detect as a wake-up source from the reduced power mode will be lost. When 0, the Brown-Out Detect function remains active during Power-down and Deep Sleep modes. See the System Control Block chapter for details of Brown-Out detection." /> + <BitField start="3" size="1" name="BOGD" description="Brown-Out Global Disable. When BOGD is 1, the Brown-Out Detect circuitry is fully disabled at all times, and does not consume power. When 0, the Brown-Out Detect circuitry is enabled. See the System Control Block chapter for details of Brown-Out detection. Note: the Brown-Out Reset Disable (BORD, in this register) and the Brown-Out Interrupt (xx) must be disabled when software changes the value of this bit." /> + <BitField start="4" size="1" name="BORD" description="Brown-Out Reset Disable. When BORD is 1, the BOD will not reset the device when the VDD(REG)(3V3) voltage dips goes below the BOD reset trip level. The Brown-Out interrupt is not affected. When BORD is 0, the BOD reset is enabled." /> + <BitField start="3" size="5" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + <BitField start="8" size="1" name="SMFLAG" description="Sleep Mode entry flag. Set when the Sleep mode is successfully entered. Cleared by software writing a one to this bit." /> + <BitField start="9" size="1" name="DSFLAG" description="Deep Sleep entry flag. Set when the Deep Sleep mode is successfully entered. Cleared by software writing a one to this bit." /> + <BitField start="10" size="1" name="PDFLAG" description="Power-down entry flag. Set when the Power-down mode is successfully entered. Cleared by software writing a one to this bit." /> + <BitField start="11" size="1" name="DPDFLAG" description="Deep Power-down entry flag. Set when the Deep Power-down mode is successfully entered. Cleared by software writing a one to this bit." /> + <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x0C4" size="4" name="PCONP" access="Read/Write" description="Power Control for Peripherals Register" reset_value="0x03BE" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RESERVED" description="Reserved." /> + <BitField start="1" size="1" name="PCTIM0" description="Timer/Counter 0 power/clock control bit." /> + <BitField start="2" size="1" name="PCTIM1" description="Timer/Counter 1 power/clock control bit." /> + <BitField start="3" size="1" name="PCUART0" description="UART0 power/clock control bit." /> + <BitField start="4" size="1" name="PCUART1" description="UART1 power/clock control bit." /> + <BitField start="5" size="1" name="RESERVED" description="Reserved." /> + <BitField start="6" size="1" name="PCPWM1" description="PWM1 power/clock control bit." /> + <BitField start="7" size="1" name="PCI2C0" description="The I2C0 interface power/clock control bit." /> + <BitField start="8" size="1" name="PCSPI" description="The SPI interface power/clock control bit." /> + <BitField start="9" size="1" name="PCRTC" description="The RTC power/clock control bit." /> + <BitField start="10" size="1" name="PCSSP1" description="The SSP 1 interface power/clock control bit." /> + <BitField start="11" size="1" name="RESERVED" description="Reserved." /> + <BitField start="12" size="1" name="PCADC" description="A/D converter (ADC) power/clock control bit. Note: Clear the PDN bit in the AD0CR before clearing this bit, and set this bit before setting PDN." /> + <BitField start="13" size="1" name="PCCAN1" description="CAN Controller 1 power/clock control bit." /> + <BitField start="14" size="1" name="PCCAN2" description="CAN Controller 2 power/clock control bit." /> + <BitField start="15" size="1" name="PCGPIO" description="Power/clock control bit for IOCON, GPIO, and GPIO interrupts." /> + <BitField start="16" size="1" name="PCRIT" description="Repetitive Interrupt Timer power/clock control bit." /> + <BitField start="17" size="1" name="PCMCPWM" description="Motor Control PWM" /> + <BitField start="18" size="1" name="PCQEI" description="Quadrature Encoder Interface power/clock control bit." /> + <BitField start="19" size="1" name="PCI2C1" description="The I2C1 interface power/clock control bit." /> + <BitField start="20" size="1" name="RESERVED" description="Reserved." /> + <BitField start="21" size="1" name="PCSSP0" description="The SSP0 interface power/clock control bit." /> + <BitField start="22" size="1" name="PCTIM2" description="Timer 2 power/clock control bit." /> + <BitField start="23" size="1" name="PCTIM3" description="Timer 3 power/clock control bit." /> + <BitField start="24" size="1" name="PCUART2" description="UART 2 power/clock control bit." /> + <BitField start="25" size="1" name="PCUART3" description="UART 3 power/clock control bit." /> + <BitField start="26" size="1" name="PCI2C2" description="I2C interface 2 power/clock control bit." /> + <BitField start="27" size="1" name="PCI2S" description="I2S interface power/clock control bit." /> + <BitField start="28" size="1" name="RESERVED" description="Reserved." /> + <BitField start="29" size="1" name="PCGPDMA" description="GPDMA function power/clock control bit." /> + <BitField start="30" size="1" name="PCENET" description="Ethernet block power/clock control bit." /> + <BitField start="31" size="1" name="PCUSB" description="USB interface power/clock control bit." /> + </Register> + <Register start="+0x104" size="4" name="CCLKCFG" access="Read/Write" description="CPU Clock Configuration Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="CCLKSEL" description="Selects the divide value for creating the CPU clock (CCLK) from the PLL0 output. 0 = pllclk is divided by 1 to produce the CPU clock. This setting is not allowed when the PLL0 is connected, because the rate would always be greater than the maximum allowed CPU clock. 1 = pllclk is divided by 2 to produce the CPU clock. This setting is not allowed when the PLL0 is connected, because the rate would always be greater than the maximum allowed CPU clock. 2 = pllclk is divided by 3 to produce the CPU clock. 3 = pllclk is divided by 4 to produce the CPU clock. ... 255 = pllclk is divided by 256 to produce the CPU clock." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x108" size="4" name="USBCLKCFG" access="Read/Write" description="USB Clock Configuration Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="4" name="USBSEL" description="Selects the divide value for creating the USB clock from the PLL0 output. Only the values shown below can produce even number multiples of 48 MHz from the PLL0 output. Warning: Improper setting of this value will result in incorrect operation of the USB interface. 5 = PLL0 output is divided by 6. PLL0 output must be 288 MHz. 7 = PLL0 output is divided by 8. PLL0 output must be 384 MHz. 9 = PLL0 output is divided by 10. PLL0 output must be 480 MHz." /> + <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x10C" size="4" name="CLKSRCSEL" access="Read/Write" description="Clock Source Select Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="CLKSRC" description="Selects the clock source for PLL0 as follows. Warning: Improper setting of this value, or an incorrect sequence of changing this value may result in incorrect operation of the device."> + <Enum name="SELECTS_THE_INTERNAL" start="0x0" description="Selects the Internal RC oscillator as the PLL0 clock source (default)." /> + <Enum name="SELECTS_THE_MAIN_OSC" start="0x1" description="Selects the main oscillator as the PLL0 clock source. Select the main oscillator as PLL0 clock source if the PLL0 clock output is used for USB or for CAN with baudrates > 100 kBit/s." /> + <Enum name="SELECTS_THE_RTC_OSCI" start="0x2" description="Selects the RTC oscillator as the PLL0 clock source." /> + <Enum name="RESERVED" start="0x3" description="Reserved, do not use this setting." /> + </BitField> + <BitField start="2" size="30" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x110" size="4" name="CANSLEEPCLR" access="Read/Write" description="Allows clearing the current CAN channel sleep state as well as reading that state." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="1" size="1" name="CAN1SLEEP" description="Sleep status and control for CAN channel 1. Read: when 1, indicates that CAN channel 1 is in the sleep mode. Write: writing a 1 causes clocks to be restored to CAN channel 1." /> + <BitField start="2" size="1" name="CAN2SLEEP" description="Sleep status and control for CAN channel 2. Read: when 1, indicates that CAN channel 2 is in the sleep mode. Write: writing a 1 causes clocks to be restored to CAN channel 2." /> + <BitField start="3" size="29" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x114" size="4" name="CANWAKEFLAGS" access="Read/Write" description="Allows reading the wake-up state of the CAN channels." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="1" size="1" name="CAN1WAKE" description="Wake-up status for CAN channel 1. Read: when 1, indicates that a falling edge has occurred on the receive data line of CAN channel 1. Write: writing a 1 clears this bit." /> + <BitField start="2" size="1" name="CAN2WAKE" description="Wake-up status for CAN channel 2. Read: when 1, indicates that a falling edge has occurred on the receive data line of CAN channel 2. Write: writing a 1 clears this bit." /> + <BitField start="3" size="29" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x140" size="4" name="EXTINT" access="Read/Write" description="External Interrupt Flag Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="EINT0" description="In level-sensitive mode, this bit is set if the EINT0 function is selected for its pin, and the pin is in its active state. In edge-sensitive mode, this bit is set if the EINT0 function is selected for its pin, and the selected edge occurs on the pin. This bit is cleared by writing a one to it, except in level sensitive mode when the pin is in its active state." /> + <BitField start="1" size="1" name="EINT1" description="In level-sensitive mode, this bit is set if the EINT1 function is selected for its pin, and the pin is in its active state. In edge-sensitive mode, this bit is set if the EINT1 function is selected for its pin, and the selected edge occurs on the pin. This bit is cleared by writing a one to it, except in level sensitive mode when the pin is in its active state." /> + <BitField start="2" size="1" name="EINT2" description="In level-sensitive mode, this bit is set if the EINT2 function is selected for its pin, and the pin is in its active state. In edge-sensitive mode, this bit is set if the EINT2 function is selected for its pin, and the selected edge occurs on the pin. This bit is cleared by writing a one to it, except in level sensitive mode when the pin is in its active state." /> + <BitField start="3" size="1" name="EINT3" description="In level-sensitive mode, this bit is set if the EINT3 function is selected for its pin, and the pin is in its active state. In edge-sensitive mode, this bit is set if the EINT3 function is selected for its pin, and the selected edge occurs on the pin. This bit is cleared by writing a one to it, except in level sensitive mode when the pin is in its active state." /> + <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x148" size="4" name="EXTMODE" access="Read/Write" description="External Interrupt Mode register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="EXTMODE0" description="External interrupt 0 EINT0 mode."> + <Enum name="LEVEL_SENSITIVE" start="0" description="Level-sensitive. Level-sensitivity is selected for EINT0." /> + <Enum name="EDGE_SENSITIVE" start="1" description="Edge-sensitive. EINT0 is edge sensitive." /> + </BitField> + <BitField start="1" size="1" name="EXTMODE1" description="External interrupt 1 EINT1 mode."> + <Enum name="LEVEL_SENSITIVE" start="0" description="Level-sensitive. Level-sensitivity is selected for EINT1." /> + <Enum name="EDGE_SENSITIVE" start="1" description="Edge-sensitive. EINT1 is edge sensitive." /> + </BitField> + <BitField start="2" size="1" name="EXTMODE2" description="External interrupt 2 EINT2 mode."> + <Enum name="LEVEL_SENSITIVE" start="0" description="Level-sensitive. Level-sensitivity is selected for EINT2." /> + <Enum name="EDGE_SENSITIVE" start="1" description="Edge-sensitive. EINT2 is edge sensitive." /> + </BitField> + <BitField start="3" size="1" name="EXTMODE3" description="External interrupt 3 EINT3 mode."> + <Enum name="LEVEL_SENSITIVE" start="0" description="Level-sensitive. Level-sensitivity is selected for EINT3." /> + <Enum name="EDGE_SENSITIVE" start="1" description="Edge-sensitive. EINT3 is edge sensitive." /> + </BitField> + <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x14C" size="4" name="EXTPOLAR" access="Read/Write" description="External Interrupt Polarity Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="EXTPOLAR0" description="External interrupt 0 EINT0 polarity."> + <Enum name="FALLING_EDGE" start="0" description="Falling edge. EINT0 is low-active or falling-edge sensitive (depending on EXTMODE0)." /> + <Enum name="RISING_EDGE" start="1" description="Rising edge. EINT0 is high-active or rising-edge sensitive (depending on EXTMODE0)." /> + </BitField> + <BitField start="1" size="1" name="EXTPOLAR1" description="External interrupt 1 EINT1 polarity."> + <Enum name="FALLING_EDGE" start="0" description="Falling edge. EINT1 is low-active or falling-edge sensitive (depending on EXTMODE1)." /> + <Enum name="RISING_EDGE" start="1" description="Rising edge. EINT1 is high-active or rising-edge sensitive (depending on EXTMODE1)." /> + </BitField> + <BitField start="2" size="1" name="EXTPOLAR2" description="External interrupt 2 EINT2 polarity."> + <Enum name="FALLING_EDGE" start="0" description="Falling edge. EINT2 is low-active or falling-edge sensitive (depending on EXTMODE2)." /> + <Enum name="RISING_EDGE" start="1" description="Rising edge. EINT2 is high-active or rising-edge sensitive (depending on EXTMODE2)." /> + </BitField> + <BitField start="3" size="1" name="EXTPOLAR3" description="External interrupt 3 EINT3 polarity."> + <Enum name="FALLING_EDGE" start="0" description="Falling edge. EINT3 is low-active or falling-edge sensitive (depending on EXTMODE3)." /> + <Enum name="RISING_EDGE" start="1" description="Rising edge. EINT3 is high-active or rising-edge sensitive (depending on EXTMODE3)." /> + </BitField> + <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x180" size="4" name="RSID" access="Read/Write" description="Reset Source Identification Register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="POR" description="Assertion of the POR signal sets this bit, and clears all of the other bits in this register. But if another Reset signal (e.g., External Reset) remains asserted after the POR signal is negated, then its bit is set. This bit is not affected by any of the other sources of Reset." /> + <BitField start="1" size="1" name="EXTR" description="Assertion of the RESET signal sets this bit. This bit is cleared only by software or POR." /> + <BitField start="2" size="1" name="WDTR" description="This bit is set when the Watchdog Timer times out and the WDTRESET bit in the Watchdog Mode Register is 1. This bit is cleared only by software or POR." /> + <BitField start="3" size="1" name="BODR" description="This bit is set when the VDD(REG)(3V3) voltage reaches a level below the BOD reset trip level (typically 1.85 V under nominal room temperature conditions). If the VDD(REG)(3V3) voltage dips from the normal operating range to below the BOD reset trip level and recovers, the BODR bit will be set to 1. If the VDD(REG)(3V3) voltage dips from the normal operating range to below the BOD reset trip level and continues to decline to the level at which POR is asserted (nominally 1 V), the BODR bit is cleared. If the VDD(REG)(3V3) voltage rises continuously from below 1 V to a level above the BOD reset trip level, the BODR will be set to 1. This bit is cleared only by software or POR. Note: Only in the case where a reset occurs and the POR = 0, the BODR bit indicates if the VDD(REG)(3V3) voltage was below the BOD reset trip level or not." /> + <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x1A0" size="4" name="SCS" access="Read/Write" description="System control and status" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="4" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + <BitField start="4" size="1" name="OSCRANGE" description="Main oscillator range select."> + <Enum name="LOW" start="0" description="Low. The frequency range of the main oscillator is 1 MHz to 20 MHz." /> + <Enum name="HIGH" start="1" description="High. The frequency range of the main oscillator is 15 MHz to 25 MHz." /> + </BitField> + <BitField start="5" size="1" name="OSCEN" description="Main oscillator enable."> + <Enum name="DISABLED" start="0" description="Disabled. The main oscillator is disabled." /> + <Enum name="ENABLED" start="1" description="Enabled.The main oscillator is enabled, and will start up if the correct external circuitry is connected to the XTAL1 and XTAL2 pins." /> + </BitField> + <BitField start="6" size="1" name="OSCSTAT" description="Main oscillator status."> + <Enum name="NOT_READY" start="0" description="Not ready. The main oscillator is not ready to be used as a clock source." /> + <Enum name="READY" start="1" description="Ready. The main oscillator is ready to be used as a clock source. The main oscillator must be enabled via the OSCEN bit." /> + </BitField> + <BitField start="7" size="25" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x1A8" size="4" name="PCLKSEL0" access="Read/Write" description="Peripheral Clock Selection register 0." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="PCLK_WDT" description="Peripheral clock selection for WDT."> + <Enum name="CCLK_DIV_4" start="0x0" description="CCLK div 4. PCLK_peripheral = CCLK/4" /> + <Enum name="CCLK" start="0x1" description="CCLK. PCLK_peripheral = CCLK" /> + <Enum name="CCLK_DIV_2" start="0x2" description="CCLK div 2. PCLK_peripheral = CCLK/2" /> + <Enum name="CCLK_DIV_8" start="0x3" description="CCLK div 8. PCLK_peripheral = CCLK/8" /> + </BitField> + <BitField start="2" size="2" name="PCLK_TIMER0" description="Peripheral clock selection for TIMER0."> + <Enum name="CCLK_DIV_4" start="0x0" description="CCLK div 4. PCLK_peripheral = CCLK/4" /> + <Enum name="CCLK" start="0x1" description="CCLK. PCLK_peripheral = CCLK" /> + <Enum name="CCLK_DIV_2" start="0x2" description="CCLK div 2. PCLK_peripheral = CCLK/2" /> + <Enum name="CCLK_DIV_8" start="0x3" description="CCLK div 8. PCLK_peripheral = CCLK/8" /> + </BitField> + <BitField start="4" size="2" name="PCLK_TIMER1" description="Peripheral clock selection for TIMER1."> + <Enum name="CCLK_DIV_4" start="0x0" description="CCLK div 4. PCLK_peripheral = CCLK/4" /> + <Enum name="CCLK" start="0x1" description="CCLK. PCLK_peripheral = CCLK" /> + <Enum name="CCLK_DIV_2" start="0x2" description="CCLK div 2. PCLK_peripheral = CCLK/2" /> + <Enum name="CCLK_DIV_8" start="0x3" description="CCLK div 8. PCLK_peripheral = CCLK/8" /> + </BitField> + <BitField start="6" size="2" name="PCLK_UART0" description="Peripheral clock selection for UART0."> + <Enum name="CCLK_DIV_4" start="0x0" description="CCLK div 4. PCLK_peripheral = CCLK/4" /> + <Enum name="CCLK" start="0x1" description="CCLK. PCLK_peripheral = CCLK" /> + <Enum name="CCLK_DIV_2" start="0x2" description="CCLK div 2. PCLK_peripheral = CCLK/2" /> + <Enum name="CCLK_DIV_8" start="0x3" description="CCLK div 8. PCLK_peripheral = CCLK/8" /> + </BitField> + <BitField start="8" size="2" name="PCLK_UART1" description="Peripheral clock selection for UART1."> + <Enum name="CCLK_DIV_4" start="0x0" description="CCLK div 4. PCLK_peripheral = CCLK/4" /> + <Enum name="CCLK" start="0x1" description="CCLK. PCLK_peripheral = CCLK" /> + <Enum name="CCLK_DIV_2" start="0x2" description="CCLK div 2. PCLK_peripheral = CCLK/2" /> + <Enum name="CCLK_DIV_8" start="0x3" description="CCLK div 8. PCLK_peripheral = CCLK/8" /> + </BitField> + <BitField start="10" size="2" name="RESERVED" description="Reserved." /> + <BitField start="12" size="2" name="PCLK_PWM1" description="Peripheral clock selection for PWM1."> + <Enum name="CCLK_DIV_4" start="0x0" description="CCLK div 4. PCLK_peripheral = CCLK/4" /> + <Enum name="CCLK" start="0x1" description="CCLK. PCLK_peripheral = CCLK" /> + <Enum name="CCLK_DIV_2" start="0x2" description="CCLK div 2. PCLK_peripheral = CCLK/2" /> + <Enum name="CCLK_DIV_8" start="0x3" description="CCLK div 8. PCLK_peripheral = CCLK/8" /> + </BitField> + <BitField start="14" size="2" name="PCLK_I2C0" description="Peripheral clock selection for I2C0."> + <Enum name="CCLK_DIV_4" start="0x0" description="CCLK div 4. PCLK_peripheral = CCLK/4" /> + <Enum name="CCLK" start="0x1" description="CCLK. PCLK_peripheral = CCLK" /> + <Enum name="CCLK_DIV_2" start="0x2" description="CCLK div 2. PCLK_peripheral = CCLK/2" /> + <Enum name="CCLK_DIV_8" start="0x3" description="CCLK div 8. PCLK_peripheral = CCLK/8" /> + </BitField> + <BitField start="16" size="2" name="PCLK_SPI" description="Peripheral clock selection for SPI."> + <Enum name="CCLK_DIV_4" start="0x0" description="CCLK div 4. PCLK_peripheral = CCLK/4" /> + <Enum name="CCLK" start="0x1" description="CCLK. PCLK_peripheral = CCLK" /> + <Enum name="CCLK_DIV_2" start="0x2" description="CCLK div 2. PCLK_peripheral = CCLK/2" /> + <Enum name="CCLK_DIV_8" start="0x3" description="CCLK div 8. PCLK_peripheral = CCLK/8" /> + </BitField> + <BitField start="18" size="2" name="RESERVED" description="Reserved." /> + <BitField start="20" size="2" name="PCLK_SSP1" description="Peripheral clock selection for SSP1."> + <Enum name="CCLK_DIV_4" start="0x0" description="CCLK div 4. PCLK_peripheral = CCLK/4" /> + <Enum name="CCLK" start="0x1" description="CCLK. PCLK_peripheral = CCLK" /> + <Enum name="CCLK_DIV_2" start="0x2" description="CCLK div 2. PCLK_peripheral = CCLK/2" /> + <Enum name="CCLK_DIV_8" start="0x3" description="CCLK div 8. PCLK_peripheral = CCLK/8" /> + </BitField> + <BitField start="22" size="2" name="PCLK_DAC" description="Peripheral clock selection for DAC."> + <Enum name="CCLK_DIV_4" start="0x0" description="CCLK div 4. PCLK_peripheral = CCLK/4" /> + <Enum name="CCLK" start="0x1" description="CCLK. PCLK_peripheral = CCLK" /> + <Enum name="CCLK_DIV_2" start="0x2" description="CCLK div 2. PCLK_peripheral = CCLK/2" /> + <Enum name="CCLK_DIV_8" start="0x3" description="CCLK div 8. PCLK_peripheral = CCLK/8" /> + </BitField> + <BitField start="24" size="2" name="PCLK_ADC" description="Peripheral clock selection for ADC."> + <Enum name="CCLK_DIV_4" start="0x0" description="CCLK div 4. PCLK_peripheral = CCLK/4" /> + <Enum name="CCLK" start="0x1" description="CCLK. PCLK_peripheral = CCLK" /> + <Enum name="CCLK_DIV_2" start="0x2" description="CCLK div 2. PCLK_peripheral = CCLK/2" /> + <Enum name="CCLK_DIV_8" start="0x3" description="CCLK div 8. PCLK_peripheral = CCLK/8" /> + </BitField> + <BitField start="26" size="2" name="PCLK_CAN1" description="Peripheral clock selection for CAN1.PCLK_CAN1 and PCLK_CAN2 must have the same PCLK divide value when the CAN function is used."> + <Enum name="CCLK_DIV_4" start="0x0" description="CCLK div 4. PCLK_peripheral = CCLK/4" /> + <Enum name="CCLK" start="0x1" description="CCLK. PCLK_peripheral = CCLK" /> + <Enum name="CCLK_DIV_2" start="0x2" description="CCLK div 2. PCLK_peripheral = CCLK/2" /> + <Enum name="CCLK_DIV_6" start="0x3" description="CCLK div 6. PCLK_peripheral = CCLK/6." /> + </BitField> + <BitField start="28" size="2" name="PCLK_CAN2" description="Peripheral clock selection for CAN2.PCLK_CAN1 and PCLK_CAN2 must have the same PCLK divide value when the CAN function is used."> + <Enum name="CCLK_DIV_4" start="0x0" description="CCLK div 4. PCLK_peripheral = CCLK/4" /> + <Enum name="CCLK" start="0x1" description="CCLK. PCLK_peripheral = CCLK" /> + <Enum name="CCLK_DIV_2" start="0x2" description="CCLK div 2. PCLK_peripheral = CCLK/2" /> + <Enum name="CCLK_DIV_6" start="0x3" description="CCLK div 6. PCLK_peripheral = CCLK/6," /> + </BitField> + <BitField start="30" size="2" name="PCLK_ACF" description="Peripheral clock selection for CAN acceptance filtering.PCLK_CAN1 and PCLK_CAN2 must have the same PCLK divide value when the CAN function is used."> + <Enum name="CCLK_DIV_4" start="0x0" description="CCLK div 4. PCLK_peripheral = CCLK/4" /> + <Enum name="CCLK" start="0x1" description="CCLK. PCLK_peripheral = CCLK" /> + <Enum name="CCLK_DIV_2" start="0x2" description="CCLK div 2. PCLK_peripheral = CCLK/2" /> + <Enum name="CCLK_DIV_6" start="0x3" description="CCLK div 6. PCLK_peripheral = CCLK/6" /> + </BitField> + </Register> + <Register start="+0x1AC" size="4" name="PCLKSEL1" access="Read/Write" description="Peripheral Clock Selection register 1." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="PCLK_QEI" description="Peripheral clock selection for the Quadrature Encoder Interface."> + <Enum name="CCLK_DIV_4" start="0x0" description="CCLK div 4. PCLK_peripheral = CCLK/4" /> + <Enum name="CCLK" start="0x1" description="CCLK. PCLK_peripheral = CCLK" /> + <Enum name="CCLK_DIV_2" start="0x2" description="CCLK div 2. PCLK_peripheral = CCLK/2" /> + <Enum name="CCLK_DIV_8" start="0x3" description="CCLK div 8. PCLK_peripheral = CCLK/8" /> + </BitField> + <BitField start="2" size="2" name="PCLK_GPIOINT" description="Peripheral clock selection for GPIO interrupts."> + <Enum name="CCLK_DIV_4" start="0x0" description="CCLK div 4. PCLK_peripheral = CCLK/4" /> + <Enum name="CCLK" start="0x1" description="CCLK. PCLK_peripheral = CCLK" /> + <Enum name="CCLK_DIV_2" start="0x2" description="CCLK div 2. PCLK_peripheral = CCLK/2" /> + <Enum name="CCLK_DIV_8" start="0x3" description="CCLK div 8. PCLK_peripheral = CCLK/8" /> + </BitField> + <BitField start="4" size="2" name="PCLK_PCB" description="Peripheral clock selection for the Pin Connect block."> + <Enum name="CCLK_DIV_4" start="0x0" description="CCLK div 4. PCLK_peripheral = CCLK/4" /> + <Enum name="CCLK" start="0x1" description="CCLK. PCLK_peripheral = CCLK" /> + <Enum name="CCLK_DIV_2" start="0x2" description="CCLK div 2. PCLK_peripheral = CCLK/2" /> + <Enum name="CCLK_DIV_8" start="0x3" description="CCLK div 8. PCLK_peripheral = CCLK/8" /> + </BitField> + <BitField start="6" size="2" name="PCLK_I2C1" description="Peripheral clock selection for I2C1."> + <Enum name="CCLK_DIV_4" start="0x0" description="CCLK div 4. PCLK_peripheral = CCLK/4" /> + <Enum name="CCLK" start="0x1" description="CCLK. PCLK_peripheral = CCLK" /> + <Enum name="CCLK_DIV_2" start="0x2" description="CCLK div 2. PCLK_peripheral = CCLK/2" /> + <Enum name="CCLK_DIV_8" start="0x3" description="CCLK div 8. PCLK_peripheral = CCLK/8" /> + </BitField> + <BitField start="8" size="2" name="RESERVED" description="Reserved." /> + <BitField start="10" size="2" name="PCLK_SSP0" description="Peripheral clock selection for SSP0."> + <Enum name="CCLK_DIV_4" start="0x0" description="CCLK div 4. PCLK_peripheral = CCLK/4" /> + <Enum name="CCLK" start="0x1" description="CCLK. PCLK_peripheral = CCLK" /> + <Enum name="CCLK_DIV_2" start="0x2" description="CCLK div 2. PCLK_peripheral = CCLK/2" /> + <Enum name="CCLK_DIV_8" start="0x3" description="CCLK div 8. PCLK_peripheral = CCLK/8" /> + </BitField> + <BitField start="12" size="2" name="PCLK_TIMER2" description="Peripheral clock selection for TIMER2."> + <Enum name="CCLK_DIV_4" start="0x0" description="CCLK div 4. PCLK_peripheral = CCLK/4" /> + <Enum name="CCLK" start="0x1" description="CCLK. PCLK_peripheral = CCLK" /> + <Enum name="CCLK_DIV_2" start="0x2" description="CCLK div 2. PCLK_peripheral = CCLK/2" /> + <Enum name="CCLK_DIV_8" start="0x3" description="CCLK div 8. PCLK_peripheral = CCLK/8" /> + </BitField> + <BitField start="14" size="2" name="PCLK_TIMER3" description="Peripheral clock selection for TIMER3."> + <Enum name="CCLK_DIV_4" start="0x0" description="CCLK div 4. PCLK_peripheral = CCLK/4" /> + <Enum name="CCLK" start="0x1" description="CCLK. PCLK_peripheral = CCLK" /> + <Enum name="CCLK_DIV_2" start="0x2" description="CCLK div 2. PCLK_peripheral = CCLK/2" /> + <Enum name="CCLK_DIV_8" start="0x3" description="CCLK div 8. PCLK_peripheral = CCLK/8" /> + </BitField> + <BitField start="16" size="2" name="PCLK_UART2" description="Peripheral clock selection for UART2."> + <Enum name="CCLK_DIV_4" start="0x0" description="CCLK div 4. PCLK_peripheral = CCLK/4" /> + <Enum name="CCLK" start="0x1" description="CCLK. PCLK_peripheral = CCLK" /> + <Enum name="CCLK_DIV_2" start="0x2" description="CCLK div 2. PCLK_peripheral = CCLK/2" /> + <Enum name="CCLK_DIV_8" start="0x3" description="CCLK div 8. PCLK_peripheral = CCLK/8" /> + </BitField> + <BitField start="18" size="2" name="PCLK_UART3" description="Peripheral clock selection for UART3."> + <Enum name="CCLK_DIV_4" start="0x0" description="CCLK div 4. PCLK_peripheral = CCLK/4" /> + <Enum name="CCLK" start="0x1" description="CCLK. PCLK_peripheral = CCLK" /> + <Enum name="CCLK_DIV_2" start="0x2" description="CCLK div 2. PCLK_peripheral = CCLK/2" /> + <Enum name="CCLK_DIV_8" start="0x3" description="CCLK div 8. PCLK_peripheral = CCLK/8" /> + </BitField> + <BitField start="20" size="2" name="PCLK_I2C2" description="Peripheral clock selection for I2C2."> + <Enum name="CCLK_DIV_4" start="0x0" description="CCLK div 4. PCLK_peripheral = CCLK/4" /> + <Enum name="CCLK" start="0x1" description="CCLK. PCLK_peripheral = CCLK" /> + <Enum name="CCLK_DIV_2" start="0x2" description="CCLK div 2. PCLK_peripheral = CCLK/2" /> + <Enum name="CCLK_DIV_8" start="0x3" description="CCLK div 8. PCLK_peripheral = CCLK/8" /> + </BitField> + <BitField start="22" size="2" name="PCLK_I2S" description="Peripheral clock selection for I2S."> + <Enum name="CCLK_DIV_4" start="0x0" description="CCLK div 4. PCLK_peripheral = CCLK/4" /> + <Enum name="CCLK" start="0x1" description="CCLK. PCLK_peripheral = CCLK" /> + <Enum name="CCLK_DIV_2" start="0x2" description="CCLK div 2. PCLK_peripheral = CCLK/2" /> + <Enum name="CCLK_DIV_8" start="0x3" description="CCLK div 8. PCLK_peripheral = CCLK/8" /> + </BitField> + <BitField start="24" size="2" name="RESERVED" description="Reserved." /> + <BitField start="26" size="2" name="PCLK_RIT" description="Peripheral clock selection for Repetitive Interrupt Timer."> + <Enum name="CCLK_DIV_4" start="0x0" description="CCLK div 4. PCLK_peripheral = CCLK/4" /> + <Enum name="CCLK" start="0x1" description="CCLK. PCLK_peripheral = CCLK" /> + <Enum name="CCLK_DIV_2" start="0x2" description="CCLK div 2. PCLK_peripheral = CCLK/2" /> + <Enum name="CCLK_DIV_8" start="0x3" description="CCLK div 8. PCLK_peripheral = CCLK/8" /> + </BitField> + <BitField start="28" size="2" name="PCLK_SYSCON" description="Peripheral clock selection for the System Control block."> + <Enum name="CCLK_DIV_4" start="0x0" description="CCLK div 4. PCLK_peripheral = CCLK/4" /> + <Enum name="CCLK" start="0x1" description="CCLK. PCLK_peripheral = CCLK" /> + <Enum name="CCLK_DIV_2" start="0x2" description="CCLK div 2. PCLK_peripheral = CCLK/2" /> + <Enum name="CCLK_DIV_8" start="0x3" description="CCLK div 8. PCLK_peripheral = CCLK/8" /> + </BitField> + <BitField start="30" size="2" name="PCLK_MC" description="Peripheral clock selection for the Motor Control PWM."> + <Enum name="CCLK_DIV_4" start="0x0" description="CCLK div 4. PCLK_peripheral = CCLK/4" /> + <Enum name="CCLK" start="0x1" description="CCLK. PCLK_peripheral = CCLK" /> + <Enum name="CCLK_DIV_2" start="0x2" description="CCLK div 2. PCLK_peripheral = CCLK/2" /> + <Enum name="CCLK_DIV_8" start="0x3" description="CCLK div 8. PCLK_peripheral = CCLK/8" /> + </BitField> + </Register> + <Register start="+0x1C0" size="4" name="USBINTST" access="Read/Write" description="USB Interrupt Status" reset_value="0x80000000" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="USB_INT_REQ_LP" description="Low priority interrupt line status. This bit is read-only." /> + <BitField start="1" size="1" name="USB_INT_REQ_HP" description="High priority interrupt line status. This bit is read-only." /> + <BitField start="2" size="1" name="USB_INT_REQ_DMA" description="DMA interrupt line status. This bit is read-only." /> + <BitField start="3" size="1" name="USB_HOST_INT" description="USB host interrupt line status. This bit is read-only." /> + <BitField start="4" size="1" name="USB_ATX_INT" description="External ATX interrupt line status. This bit is read-only." /> + <BitField start="5" size="1" name="USB_OTG_INT" description="OTG interrupt line status. This bit is read-only." /> + <BitField start="6" size="1" name="USB_I2C_INT" description="I2C module interrupt line status. This bit is read-only." /> + <BitField start="7" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="8" size="1" name="USB_NEED_CLK" description="USB need clock indicator. This bit is read-only. This bit is set to 1 when USB activity or a change of state on the USB data pins is detected, and it indicates that a PLL supplied clock of 48 MHz is needed. Once USB_NEED_CLK becomes one, it resets to zero 5 ms after the last packet has been received/sent, or 2 ms after the Suspend Change (SUS_CH) interrupt has occurred. A change of this bit from 0 to 1 can wake up the microcontroller if activity on the USB bus is selected to wake up the part from the Power-down mode (see Section 4.7.9 Wake-up from Reduced Power Modes for details). Also see Section 4.5.8 PLLs and Power-down mode and Section 4.7.10 Power Control for Peripherals register (PCONP - 0x400F C0C4) for considerations about the PLL and invoking the Power-down mode. This bit is read-only." /> + <BitField start="9" size="22" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="31" size="1" name="EN_USB_INTS" description="Enable all USB interrupts. When this bit is cleared, the NVIC does not see the ORed output of the USB interrupt lines." /> + </Register> + <Register start="+0x1C4" size="4" name="DMACREQSEL" access="Read/Write" description="Selects between alternative requests on DMA channels 0 through 7 and 10 through 15" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="DMASEL08" description="Selects the DMA request for GPDMA input 8: 0 - uart0 tx 1 - Timer 0 match 0 is selected." /> + <BitField start="1" size="1" name="DMASEL09" description="Selects the DMA request for GPDMA input 9: 0 - uart0 rx 1 - Timer 0 match 1 is selected." /> + <BitField start="2" size="1" name="DMASEL10" description="Selects the DMA request for GPDMA input 10: 0 - uart1 tx is selected. 1 - Timer 1 match 0 is selected." /> + <BitField start="3" size="1" name="DMASEL11" description="Selects the DMA request for GPDMA input 11: 0 - uart1 rx is selected. 1 - Timer 1 match 1 is selected." /> + <BitField start="4" size="1" name="DMASEL12" description="Selects the DMA request for GPDMA input 12: 0 - uart2 tx is selected. 1 - Timer 2 match 0 is selected." /> + <BitField start="5" size="1" name="DMASEL13" description="Selects the DMA request for GPDMA input 13: 0 - uart2 rx is selected. 1 - Timer 2 match 1 is selected." /> + <BitField start="6" size="1" name="DMASEL14" description="Selects the DMA request for GPDMA input 14: 0 - uart3 tx is selected. 1 - I2S channel 0 is selected." /> + <BitField start="7" size="1" name="DMASEL15" description="Selects the DMA request for GPDMA input 15: 0 - uart3 rx is selected. 1 - I2S channel 1 is selected." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x1C8" size="4" name="CLKOUTCFG" access="Read/Write" description="Clock Output Configuration Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="4" name="CLKOUTSEL" description="Selects the clock source for the CLKOUT function. Other values are reserved. Do not use."> + <Enum name="SELECTS_THE_CPU_CLOC" start="0x0" description="Selects the CPU clock as the CLKOUT source." /> + <Enum name="SELECTS_THE_MAIN_OSC" start="0x1" description="Selects the main oscillator as the CLKOUT source." /> + <Enum name="SELECTS_THE_INTERNAL" start="0x2" description="Selects the Internal RC oscillator as the CLKOUT source." /> + <Enum name="SELECTS_THE_USB_CLOC" start="0x3" description="Selects the USB clock as the CLKOUT source." /> + <Enum name="SELECTS_THE_RTC_OSCI" start="0x4" description="Selects the RTC oscillator as the CLKOUT source." /> + </BitField> + <BitField start="4" size="4" name="CLKOUTDIV" description="Integer value to divide the output clock by, minus one. 0 = Clock is divided by 1 1 = Clock is divided by 2. 2 = Clock is divided by 3. ... 15 = Clock is divided by 16." /> + <BitField start="8" size="1" name="CLKOUT_EN" description="CLKOUT enable control, allows switching the CLKOUT source without glitches. Clear to stop CLKOUT on the next falling edge. Set to enable CLKOUT." /> + <BitField start="9" size="1" name="CLKOUT_ACT" description="CLKOUT activity indication. Reads as 1 when CLKOUT is enabled. Read as 0 when CLKOUT has been disabled via the CLKOUT_EN bit and the clock has completed being stopped." /> + <BitField start="10" size="22" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + </RegisterGroup> + <RegisterGroup name="EMAC" start="0x50000000" description="Ethernet"> + <Register start="+0x000" size="4" name="MAC1" access="Read/Write" description="MAC configuration register 1." reset_value="0x8000" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RXENABLE" description="RECEIVE ENABLE. Set this to allow receive frames to be received. Internally the MAC synchronizes this control bit to the incoming receive stream." /> + <BitField start="1" size="1" name="PARF" description="PASS ALL RECEIVE FRAMES. When enabled (set to 1), the MAC will pass all frames regardless of type (normal vs. Control). When disabled, the MAC does not pass valid Control frames." /> + <BitField start="2" size="1" name="RXFLOWCTRL" description="RX FLOW CONTROL. When enabled (set to 1), the MAC acts upon received PAUSE Flow Control frames. When disabled, received PAUSE Flow Control frames are ignored." /> + <BitField start="3" size="1" name="TXFLOWCTRL" description="TX FLOW CONTROL. When enabled (set to 1), PAUSE Flow Control frames are allowed to be transmitted. When disabled, Flow Control frames are blocked." /> + <BitField start="4" size="1" name="LOOPBACK" description="Setting this bit will cause the MAC Transmit interface to be looped back to the MAC Receive interface. Clearing this bit results in normal operation." /> + <BitField start="5" size="3" name="RESERVED" description="Unused" /> + <BitField start="8" size="1" name="RESETTX" description="Setting this bit will put the Transmit Function logic in reset." /> + <BitField start="9" size="1" name="RESETMCSTX" description="Setting this bit resets the MAC Control Sublayer / Transmit logic. The MCS logic implements flow control." /> + <BitField start="10" size="1" name="RESETRX" description="Setting this bit will put the Ethernet receive logic in reset." /> + <BitField start="11" size="1" name="RESETMCSRX" description="Setting this bit resets the MAC Control Sublayer / Receive logic. The MCS logic implements flow control." /> + <BitField start="12" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="14" size="1" name="SIMRESET" description="SIMULATION RESET. Setting this bit will cause a reset to the random number generator within the Transmit Function." /> + <BitField start="15" size="1" name="SOFTRESET" description="SOFT RESET. Setting this bit will put all modules within the MAC in reset except the Host Interface." /> + <BitField start="16" size="16" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x004" size="4" name="MAC2" access="Read/Write" description="MAC configuration register 2." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="FULLDUPLEX" description="When enabled (set to 1), the MAC operates in Full-Duplex mode. When disabled, the MAC operates in Half-Duplex mode." /> + <BitField start="1" size="1" name="FLC" description="FRAMELENGTH CHECKING. When enabled (set to 1), both transmit and receive frame lengths are compared to the Length/Type field. If the Length/Type field represents a length then the check is performed. Mismatches are reported in the StatusInfo word for each received frame." /> + <BitField start="2" size="1" name="HFEN" description="HUGE FRAME ENABLEWhen enabled (set to 1), frames of any length are transmitted and received." /> + <BitField start="3" size="1" name="DELAYEDCRC" description="DELAYED CRC. This bit determines the number of bytes, if any, of proprietary header information that exist on the front of IEEE 802.3 frames. When 1, four bytes of header (ignored by the CRC function) are added. When 0, there is no proprietary header." /> + <BitField start="4" size="1" name="CRCEN" description="CRC ENABLESet this bit to append a CRC to every frame whether padding was required or not. Must be set if PAD/CRC ENABLE is set. Clear this bit if frames presented to the MAC contain a CRC." /> + <BitField start="5" size="1" name="PADCRCEN" description="PAD CRC ENABLE. Set this bit to have the MAC pad all short frames. Clear this bit if frames presented to the MAC have a valid length. This bit is used in conjunction with AUTO PAD ENABLE and VLAN PAD ENABLE. See Table 153 - Pad Operation for details on the pad function." /> + <BitField start="6" size="1" name="VLANPADEN" description="VLAN PAD ENABLE. Set this bit to cause the MAC to pad all short frames to 64 bytes and append a valid CRC. Consult Table 153 - Pad Operation for more information on the various padding features. Note: This bit is ignored if PAD / CRC ENABLE is cleared." /> + <BitField start="7" size="1" name="AUTODETPADEN" description="AUTODETECTPAD ENABLE. Set this bit to cause the MAC to automatically detect the type of frame, either tagged or un-tagged, by comparing the two octets following the source address with 0x8100 (VLAN Protocol ID) and pad accordingly. Table 153 - Pad Operation provides a description of the pad function based on the configuration of this register. Note: This bit is ignored if PAD / CRC ENABLE is cleared." /> + <BitField start="8" size="1" name="PPENF" description="PURE PREAMBLE ENFORCEMEN. When enabled (set to 1), the MAC will verify the content of the preamble to ensure it contains 0x55 and is error-free. A packet with an incorrect preamble is discarded. When disabled, no preamble checking is performed." /> + <BitField start="9" size="1" name="LPENF" description="LONG PREAMBLE ENFORCEMENT. When enabled (set to 1), the MAC only allows receive packets which contain preamble fields less than 12 bytes in length. When disabled, the MAC allows any length preamble as per the Standard." /> + <BitField start="10" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="12" size="1" name="NOBACKOFF" description="When enabled (set to 1), the MAC will immediately retransmit following a collision rather than using the Binary Exponential Backoff algorithm as specified in the Standard." /> + <BitField start="13" size="1" name="BP_NOBACKOFF" description="BACK PRESSURE / NO BACKOFF. When enabled (set to 1), after the MAC incidentally causes a collision during back pressure, it will immediately retransmit without backoff, reducing the chance of further collisions and ensuring transmit packets get sent." /> + <BitField start="14" size="1" name="EXCESSDEFER" description="When enabled (set to 1) the MAC will defer to carrier indefinitely as per the Standard. When disabled, the MAC will abort when the excessive deferral limit is reached." /> + <BitField start="15" size="17" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x008" size="4" name="IPGT" access="Read/Write" description="Back-to-Back Inter-Packet-Gap register." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="7" name="BTOBINTEGAP" description="BACK-TO-BACK INTER-PACKET-GAP.This is a programmable field representing the nibble time offset of the minimum possible period between the end of any transmitted packet to the beginning of the next. In Full-Duplex mode, the register value should be the desired period in nibble times minus 3. In Half-Duplex mode, the register value should be the desired period in nibble times minus 6. In Full-Duplex the recommended setting is 0x15 (21d), which represents the minimum IPG of 960 ns (in 100 Mbps mode) or 9.6 us (in 10 Mbps mode). In Half-Duplex the recommended setting is 0x12 (18d), which also represents the minimum IPG of 960 ns (in 100 Mbps mode) or 9.6 us (in 10 Mbps mode)." /> + <BitField start="7" size="25" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x00C" size="4" name="IPGR" access="Read/Write" description="Non Back-to-Back Inter-Packet-Gap register." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="7" name="NBTOBINTEGAP2" description="NON-BACK-TO-BACK INTER-PACKET-GAP PART2. This is a programmable field representing the Non-Back-to-Back Inter-Packet-Gap. The recommended value is 0x12 (18d), which represents the minimum IPG of 960 ns (in 100 Mbps mode) or 9.6 us (in 10 Mbps mode)." /> + <BitField start="7" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="8" size="7" name="NBTOBINTEGAP1" description="NON-BACK-TO-BACK INTER-PACKET-GAP PART1. This is a programmable field representing the optional carrierSense window referenced in IEEE 802.3/4.2.3.2.1 'Carrier Deference'. If carrier is detected during the timing of IPGR1, the MAC defers to carrier. If, however, carrier becomes active after IPGR1, the MAC continues timing IPGR2 and transmits, knowingly causing a collision, thus ensuring fair access to medium. Its range of values is 0x0 to IPGR2. The recommended value is 0xC (12d)" /> + <BitField start="15" size="17" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x010" size="4" name="CLRT" access="Read/Write" description="Collision window / Retry register." reset_value="0x370F" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="4" name="RETRANSMAX" description="RETRANSMISSION MAXIMUM.This is a programmable field specifying the number of retransmission attempts following a collision before aborting the packet due to excessive collisions. The Standard specifies the attemptLimit to be 0xF (15d). See IEEE 802.3/4.2.3.2.5." /> + <BitField start="4" size="4" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="8" size="6" name="COLLWIN" description="COLLISION WINDOW. This is a programmable field representing the slot time or collision window during which collisions occur in properly configured networks. The default value of 0x37 (55d) represents a 56 byte window following the preamble and SFD." /> + <BitField start="14" size="18" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x014" size="4" name="MAXF" access="Read/Write" description="Maximum Frame register." reset_value="0x0600" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="16" name="MAXFLEN" description="MAXIMUM FRAME LENGTH. This field resets to the value 0x0600, which represents a maximum receive frame of 1536 octets. An untagged maximum size Ethernet frame is 1518 octets. A tagged frame adds four octets for a total of 1522 octets. If a shorter maximum length restriction is desired, program this 16-bit field." /> + <BitField start="16" size="16" name="RESERVED" description="Unused" /> + </Register> + <Register start="+0x018" size="4" name="SUPP" access="Read/Write" description="PHY Support register." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="RESERVED" description="Unused" /> + <BitField start="8" size="1" name="SPEED" description="This bit configures the Reduced MII logic for the current operating speed. When set, 100 Mbps mode is selected. When cleared, 10 Mbps mode is selected." /> + <BitField start="9" size="23" name="RESERVED" description="Unused" /> + </Register> + <Register start="+0x01C" size="4" name="TEST" access="Read/Write" description="Test register." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="SCPQ" description="SHORTCUT PAUSE QUANTA. This bit reduces the effective PAUSE quanta from 64 byte-times to 1 byte-time." /> + <BitField start="1" size="1" name="TESTPAUSE" description="This bit causes the MAC Control sublayer to inhibit transmissions, just as if a PAUSE Receive Control frame with a nonzero pause time parameter was received." /> + <BitField start="2" size="1" name="TESTBP" description="TEST BACKPRESSURE. Setting this bit will cause the MAC to assert backpressure on the link. Backpressure causes preamble to be transmitted, raising carrier sense. A transmit packet from the system will be sent during backpressure." /> + <BitField start="3" size="29" name="RESERVED" description="Unused" /> + </Register> + <Register start="+0x020" size="4" name="MCFG" access="Read/Write" description="MII Mgmt Configuration register." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="SCANINC" description="SCAN INCREMENT. Set this bit to cause the MII Management hardware to perform read cycles across a range of PHYs. When set, the MII Management hardware will perform read cycles from address 1 through the value set in PHY ADDRESS[4:0]. Clear this bit to allow continuous reads of the same PHY." /> + <BitField start="1" size="1" name="SUPPPREAMBLE" description="SUPPRESS PREAMBLE. Set this bit to cause the MII Management hardware to perform read/write cycles without the 32-bit preamble field. Clear this bit to cause normal cycles to be performed. Some PHYs support suppressed preamble." /> + <BitField start="2" size="4" name="CLOCKSEL" description="CLOCK SELECT. This field is used by the clock divide logic in creating the MII Management Clock (MDC) which IEEE 802.3u defines to be no faster than 2.5 MHz. Some PHYs support clock rates up to 12.5 MHz, however. The AHB bus clock (HCLK) is divided by the specified amount. Refer to Table 160 below for the definition of values for this field." /> + <BitField start="6" size="9" name="RESERVED" description="Unused" /> + <BitField start="15" size="1" name="RESETMIIMGMT" description="RESET MII MGMT. This bit resets the MII Management hardware." /> + <BitField start="16" size="16" name="RESERVED" description="Unused" /> + </Register> + <Register start="+0x024" size="4" name="MCMD" access="Read/Write" description="MII Mgmt Command register." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="READ" description="This bit causes the MII Management hardware to perform a single Read cycle. The Read data is returned in Register MRDD (MII Mgmt Read Data)." /> + <BitField start="1" size="1" name="SCAN" description="This bit causes the MII Management hardware to perform Read cycles continuously. This is useful for monitoring Link Fail for example." /> + <BitField start="2" size="30" name="RESERVED" description="Unused" /> + </Register> + <Register start="+0x028" size="4" name="MADR" access="Read/Write" description="MII Mgmt Address register." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="REGADDR" description="REGISTER ADDRESS. This field represents the 5-bit Register Address field of Mgmt cycles. Up to 32 registers can be accessed." /> + <BitField start="5" size="3" name="RESERVED" description="Unused" /> + <BitField start="8" size="5" name="PHYADDR" description="PHY ADDRESS. This field represents the 5-bit PHY Address field of Mgmt cycles. Up to 31 PHYs can be addressed (0 is reserved)." /> + <BitField start="13" size="19" name="RESERVED" description="Unused" /> + </Register> + <Register start="+0x02C" size="4" name="MWTD" access="WriteOnly" description="MII Mgmt Write Data register." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="16" name="WRITEDATA" description="WRITE DATA. When written, an MII Mgmt write cycle is performed using the 16-bit data and the pre-configured PHY and Register addresses from the MII Mgmt Address register (MADR)." /> + <BitField start="16" size="16" name="RESERVED" description="Unused" /> + </Register> + <Register start="+0x030" size="4" name="MRDD" access="ReadOnly" description="MII Mgmt Read Data register." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="16" name="READDATA" description="READ DATA. Following an MII Mgmt Read Cycle, the 16-bit data can be read from this location." /> + <BitField start="16" size="16" name="RESERVED" description="Unused" /> + </Register> + <Register start="+0x034" size="4" name="MIND" access="ReadOnly" description="MII Mgmt Indicators register." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="BUSY" description="When 1 is returned - indicates MII Mgmt is currently performing an MII Mgmt Read or Write cycle." /> + <BitField start="1" size="1" name="SCANNING" description="When 1 is returned - indicates a scan operation (continuous MII Mgmt Read cycles) is in progress." /> + <BitField start="2" size="1" name="NOTVALID" description="When 1 is returned - indicates MII Mgmt Read cycle has not completed and the Read Data is not yet valid." /> + <BitField start="3" size="1" name="MIILINKFAIL" description="When 1 is returned - indicates that an MII Mgmt link fail has occurred." /> + <BitField start="4" size="28" name="RESERVED" description="Unused" /> + </Register> + <Register start="+0x040" size="4" name="SA0" access="Read/Write" description="Station Address 0 register." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="SADDR2" description="STATION ADDRESS, 2nd octet. This field holds the second octet of the station address." /> + <BitField start="8" size="8" name="SADDR1" description="STATION ADDRESS, 1st octet. This field holds the first octet of the station address." /> + <BitField start="16" size="16" name="RESERVED" description="Unused" /> + </Register> + <Register start="+0x044" size="4" name="SA1" access="Read/Write" description="Station Address 1 register." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="SADDR4" description="STATION ADDRESS, 4th octet. This field holds the fourth octet of the station address." /> + <BitField start="8" size="8" name="SADDR3" description="STATION ADDRESS, 3rd octet. This field holds the third octet of the station address." /> + <BitField start="16" size="16" name="RESERVED" description="Unused" /> + </Register> + <Register start="+0x048" size="4" name="SA2" access="Read/Write" description="Station Address 2 register." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="SADDR6" description="STATION ADDRESS, 6th octet. This field holds the sixth octet of the station address." /> + <BitField start="8" size="8" name="SADDR5" description="STATION ADDRESS, 5th octet. This field holds the fifth octet of the station address." /> + <BitField start="16" size="16" name="RESERVED" description="Unused" /> + </Register> + <Register start="+0x100" size="4" name="COMMAND" access="Read/Write" description="Command register." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RXENABLE" description="Enable receive." /> + <BitField start="1" size="1" name="TXENABLE" description="Enable transmit." /> + <BitField start="2" size="1" name="RESERVED" description="Unused" /> + <BitField start="3" size="1" name="REGRESET" description="When a 1 is written, all datapaths and the host registers are reset. The MAC needs to be reset separately." /> + <BitField start="4" size="1" name="TXRESET" description="When a 1 is written, the transmit datapath is reset." /> + <BitField start="5" size="1" name="RXRESET" description="When a 1 is written, the receive datapath is reset." /> + <BitField start="6" size="1" name="PASSRUNTFRAME" description="When set to 1 , passes runt frames s1maller than 64 bytes to memory unless they have a CRC error. If 0 runt frames are filtered out." /> + <BitField start="7" size="1" name="PASSRXFILTER" description="When set to 1 , disables receive filtering i.e. all frames received are written to memory." /> + <BitField start="8" size="1" name="TXFLOWCONTROL" description="Enable IEEE 802.3 / clause 31 flow control sending pause frames in full duplex and continuous preamble in half duplex." /> + <BitField start="9" size="1" name="RMII" description="When set to 1 , RMII mode is selected; if 0, MII mode is selected." /> + <BitField start="10" size="1" name="FULLDUPLEX" description="When set to 1 , indicates full duplex operation." /> + <BitField start="11" size="21" name="RESERVED" description="Unused" /> + </Register> + <Register start="+0x104" size="4" name="STATUS" access="ReadOnly" description="Status register." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RXSTATUS" description="If 1, the receive channel is active. If 0, the receive channel is inactive." /> + <BitField start="1" size="1" name="TXSTATUS" description="If 1, the transmit channel is active. If 0, the transmit channel is inactive." /> + <BitField start="2" size="30" name="RESERVED" description="Unused" /> + </Register> + <Register start="+0x108" size="4" name="RXDESCRIPTOR" access="Read/Write" description="Receive descriptor base address register." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="RESERVED" description="Fixed to 00" /> + <BitField start="2" size="30" name="RXDESCRIPTOR" description="MSBs of receive descriptor base address." /> + </Register> + <Register start="+0x10C" size="4" name="RXSTATUS" access="Read/Write" description="Receive status base address register." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="RESERVED" description="Fixed to 000" /> + <BitField start="3" size="29" name="RXSTATUS" description="MSBs of receive status base address." /> + </Register> + <Register start="+0x110" size="4" name="RXDESCRIPTORNUMBER" access="Read/Write" description="Receive number of descriptors register." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="16" name="RXDESCRIPTORN" description="RxDescriptorNumber. Number of descriptors in the descriptor array for which RxDescriptor is the base address. The number of descriptors is minus one encoded." /> + <BitField start="16" size="16" name="RESERVED" description="Unused" /> + </Register> + <Register start="+0x114" size="4" name="RXPRODUCEINDEX" access="ReadOnly" description="Receive produce index register." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="16" name="RXPRODUCEIX" description="Index of the descriptor that is going to be filled next by the receive datapath." /> + <BitField start="16" size="16" name="RESERVED" description="Unused" /> + </Register> + <Register start="+0x118" size="4" name="RXCONSUMEINDEX" access="Read/Write" description="Receive consume index register." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="16" name="RXCONSUMEIX" description="Index of the descriptor that is going to be processed next by the receive" /> + <BitField start="16" size="16" name="RESERVED" description="Unused" /> + </Register> + <Register start="+0x11C" size="4" name="TXDESCRIPTOR" access="Read/Write" description="Transmit descriptor base address register." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="RESERVED" description="Fixed to 00" /> + <BitField start="2" size="30" name="TXD" description="TxDescriptor. MSBs of transmit descriptor base address." /> + </Register> + <Register start="+0x120" size="4" name="TXSTATUS" access="Read/Write" description="Transmit status base address register." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="RESERVED" description="Fixed to 00" /> + <BitField start="2" size="30" name="TXSTAT" description="TxStatus. MSBs of transmit status base address." /> + </Register> + <Register start="+0x124" size="4" name="TXDESCRIPTORNUMBER" access="Read/Write" description="Transmit number of descriptors register." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="16" name="TXDN" description="TxDescriptorNumber. Number of descriptors in the descriptor array for which TxDescriptor is the base address. The register is minus one encoded." /> + <BitField start="16" size="16" name="RESERVED" description="Unused" /> + </Register> + <Register start="+0x128" size="4" name="TXPRODUCEINDEX" access="Read/Write" description="Transmit produce index register." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="16" name="TXPI" description="TxProduceIndex. Index of the descriptor that is going to be filled next by the transmit software driver." /> + <BitField start="16" size="16" name="RESERVED" description="Unused" /> + </Register> + <Register start="+0x12C" size="4" name="TXCONSUMEINDEX" access="ReadOnly" description="Transmit consume index register." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="16" name="TXCI" description="TxConsumeIndex. Index of the descriptor that is going to be transmitted next by the transmit datapath." /> + <BitField start="16" size="16" name="RESERVED" description="Unused" /> + </Register> + <Register start="+0x158" size="4" name="TSV0" access="ReadOnly" description="Transmit status vector 0 register." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="CRCERR" description="CRC error. The attached CRC in the packet did not match the internally generated CRC." /> + <BitField start="1" size="1" name="LCE" description="Length check error. Indicates the frame length field does not match the actual number of data items and is not a type field." /> + <BitField start="2" size="1" name="LOR" description="Length out of range. Indicates that frame type/length field was larger than 1500 bytes. The EMAC doesn't distinguish the frame type and frame length, so, e.g. when the IP(0x8000) or ARP(0x0806) packets are received, it compares the frame type with the max length and gives the "Length out of range" error. In fact, this bit is not an error indication, but simply a statement by the chip regarding the status of the received frame." /> + <BitField start="3" size="1" name="DONE" description="Transmission of packet was completed." /> + <BitField start="4" size="1" name="MULTICAST" description="Packet's destination was a multicast address." /> + <BitField start="5" size="1" name="BROADCAST" description="Packet's destination was a broadcast address." /> + <BitField start="6" size="1" name="PACKETDEFER" description="Packet was deferred for at least one attempt, but less than an excessive defer." /> + <BitField start="7" size="1" name="EXDF" description="Excessive Defer. Packet was deferred in excess of 6071 nibble times in 100 Mbps or 24287 bit times in 10 Mbps mode." /> + <BitField start="8" size="1" name="EXCOL" description="Excessive Collision. Packet was aborted due to exceeding of maximum allowed number of collisions." /> + <BitField start="9" size="1" name="LCOL" description="Late Collision. Collision occurred beyond collision window, 512 bit times." /> + <BitField start="10" size="1" name="GIANT" description="Byte count in frame was greater than can be represented in the transmit byte count field in TSV1." /> + <BitField start="11" size="1" name="UNDERRUN" description="Host side caused buffer underrun." /> + <BitField start="12" size="16" name="TOTALBYTES" description="The total number of bytes transferred including collided attempts." /> + <BitField start="28" size="1" name="CONTROLFRAME" description="The frame was a control frame." /> + <BitField start="29" size="1" name="PAUSE" description="The frame was a control frame with a valid PAUSE opcode." /> + <BitField start="30" size="1" name="BACKPRESSURE" description="Carrier-sense method backpressure was previously applied." /> + <BitField start="31" size="1" name="VLAN" description="Frame's length/type field contained 0x8100 which is the VLAN protocol identifier." /> + </Register> + <Register start="+0x15C" size="4" name="TSV1" access="ReadOnly" description="Transmit status vector 1 register." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="16" name="TBC" description="Transmit byte count. The total number of bytes in the frame, not counting the collided bytes." /> + <BitField start="16" size="4" name="TCC" description="Transmit collision count. Number of collisions the current packet incurred during transmission attempts. The maximum number of collisions (16) cannot be represented." /> + <BitField start="20" size="12" name="RESERVED" description="Unused" /> + </Register> + <Register start="+0x160" size="4" name="RSV" access="ReadOnly" description="Receive status vector register." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="16" name="RBC" description="Received byte count. Indicates length of received frame." /> + <BitField start="16" size="1" name="PPI" description="Packet previously ignored. Indicates that a packet was dropped." /> + <BitField start="17" size="1" name="RXDVSEEN" description="RXDV event previously seen. Indicates that the last receive event seen was not long enough to be a valid packet." /> + <BitField start="18" size="1" name="CESEEN" description="Carrier event previously seen. Indicates that at some time since the last receive statistics, a carrier event was detected." /> + <BitField start="19" size="1" name="RCV" description="Receive code violation. Indicates that received PHY data does not represent a valid receive code." /> + <BitField start="20" size="1" name="CRCERR" description="CRC error. The attached CRC in the packet did not match the internally generated CRC." /> + <BitField start="21" size="1" name="LCERR" description="Length check error. Indicates the frame length field does not match the actual number of data items and is not a type field." /> + <BitField start="22" size="1" name="LOR" description="Length out of range. Indicates that frame type/length field was larger than 1518 bytes. The EMAC doesn't distinguish the frame type and frame length, so, e.g. when the IP(0x8000) or ARP(0x0806) packets are received, it compares the frame type with the max length and gives the "Length out of range" error. In fact, this bit is not an error indication, but simply a statement by the chip regarding the status of the received frame." /> + <BitField start="23" size="1" name="ROK" description="Receive OK. The packet had valid CRC and no symbol errors." /> + <BitField start="24" size="1" name="MULTICAST" description="The packet destination was a multicast address." /> + <BitField start="25" size="1" name="BROADCAST" description="The packet destination was a broadcast address." /> + <BitField start="26" size="1" name="DRIBBLENIBBLE" description="Indicates that after the end of packet another 1-7 bits were received. A single nibble, called dribble nibble, is formed but not sent out." /> + <BitField start="27" size="1" name="CONTROLFRAME" description="The frame was a control frame." /> + <BitField start="28" size="1" name="PAUSE" description="The frame was a control frame with a valid PAUSE opcode." /> + <BitField start="29" size="1" name="UO" description="Unsupported Opcode. The current frame was recognized as a Control Frame but contains an unknown opcode." /> + <BitField start="30" size="1" name="VLAN" description="Frame's length/type field contained 0x8100 which is the VLAN protocol identifier." /> + <BitField start="31" size="1" name="RESERVED" description="Unused" /> + </Register> + <Register start="+0x170" size="4" name="FLOWCONTROLCOUNTER" access="Read/Write" description="Flow control counter register." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="16" name="MC" description="MirrorCounter. In full duplex mode the MirrorCounter specifies the number of cycles before re-issuing the Pause control frame." /> + <BitField start="16" size="16" name="PT" description="PauseTimer. In full-duplex mode the PauseTimer specifies the value that is inserted into the pause timer field of a pause flow control frame. In half duplex mode the PauseTimer specifies the number of backpressure cycles." /> + </Register> + <Register start="+0x174" size="4" name="FLOWCONTROLSTATUS" access="ReadOnly" description="Flow control status register." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="16" name="MCC" description="MirrorCounterCurrent. In full duplex mode this register represents the current value of the datapath's mirror counter which counts up to the value specified by the MirrorCounter field in the FlowControlCounter register. In half duplex mode the register counts until it reaches the value of the PauseTimer bits in the FlowControlCounter register." /> + <BitField start="16" size="16" name="RESERVED" description="Unused" /> + </Register> + <Register start="+0x200" size="4" name="RXFILTERCTRL" access="Read/Write" description="Receive filter control register." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="AUE" description="AcceptUnicastEn. When set to 1, all unicast frames are accepted." /> + <BitField start="1" size="1" name="ABE" description="AcceptBroadcastEn. When set to 1, all broadcast frames are accepted." /> + <BitField start="2" size="1" name="AME" description="AcceptMulticastEn. When set to 1, all multicast frames are accepted." /> + <BitField start="3" size="1" name="AUHE" description="AcceptUnicastHashEn. When set to 1, unicast frames that pass the imperfect hash filter are accepted." /> + <BitField start="4" size="1" name="AMHE" description="AcceptMulticastHashEn. When set to 1, multicast frames that pass the imperfect hash filter are accepted." /> + <BitField start="5" size="1" name="APE" description="AcceptPerfectEn. When set to 1, the frames with a destination address identical to the station address are accepted." /> + <BitField start="6" size="6" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="12" size="1" name="MPEW" description="MagicPacketEnWoL. When set to 1, the result of the magic packet filter will generate a WoL interrupt when there is a match." /> + <BitField start="13" size="1" name="RFEW" description="RxFilterEnWoL. When set to 1, the result of the perfect address matching filter and the imperfect hash filter will generate a WoL interrupt when there is a match." /> + <BitField start="14" size="18" name="RESERVED" description="Unused" /> + </Register> + <Register start="+0x204" size="4" name="RXFILTERWOLSTATUS" access="ReadOnly" description="Receive filter WoL status register." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="AUW" description="AcceptUnicastWoL. When the value is 1, a unicast frames caused WoL." /> + <BitField start="1" size="1" name="ABW" description="AcceptBroadcastWoL. When the value is 1, a broadcast frame caused WoL." /> + <BitField start="2" size="1" name="AMW" description="AcceptMulticastWoL. When the value is 1, a multicast frame caused WoL." /> + <BitField start="3" size="1" name="AUHW" description="AcceptUnicastHashWoL. When the value is 1, a unicast frame that passes the imperfect hash filter caused WoL." /> + <BitField start="4" size="1" name="AMHW" description="AcceptMulticastHashWoL. When the value is 1, a multicast frame that passes the imperfect hash filter caused WoL." /> + <BitField start="5" size="1" name="APW" description="AcceptPerfectWoL. When the value is 1, the perfect address matching filter caused WoL." /> + <BitField start="6" size="1" name="RESERVED" description="Unused" /> + <BitField start="7" size="1" name="RFW" description="RxFilterWoL. When the value is 1, the receive filter caused WoL." /> + <BitField start="8" size="1" name="MPW" description="MagicPacketWoL. When the value is 1, the magic packet filter caused WoL." /> + <BitField start="9" size="23" name="RESERVED" description="Unused" /> + </Register> + <Register start="+0x208" size="4" name="RXFILTERWOLCLEAR" access="WriteOnly" description="Receive filter WoL clear register." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="AUWCLR" description="AcceptUnicastWoLClr. When a 1 is written, the corresponding status bit in the RxFilterWoLStatus register is cleared." /> + <BitField start="1" size="1" name="ABWCLR" description="AcceptBroadcastWoLClr. When a 1 is written, the corresponding status bit in the RxFilterWoLStatus register is cleared." /> + <BitField start="2" size="1" name="AMWCLR" description="AcceptMulticastWoLClr. When a 1 is written, the corresponding status bit in the RxFilterWoLStatus register is cleared." /> + <BitField start="3" size="1" name="AUHWCLR" description="AcceptUnicastHashWoLClr. When a 1 is written, the corresponding status bit in the RxFilterWoLStatus register is cleared." /> + <BitField start="4" size="1" name="AMHWCLR" description="AcceptMulticastHashWoLClr. When a 1 is written, the corresponding status bit in the RxFilterWoLStatus register is cleared." /> + <BitField start="5" size="1" name="APWCLR" description="AcceptPerfectWoLClr. When a 1 is written, the corresponding status bit in the RxFilterWoLStatus register is cleared." /> + <BitField start="6" size="1" name="RESERVED" description="Unused" /> + <BitField start="7" size="1" name="RFWCLR" description="RxFilterWoLClr. When a 1 is written, the corresponding status bit in the RxFilterWoLStatus register is cleared." /> + <BitField start="8" size="1" name="MPWCLR" description="MagicPacketWoLClr. When a 1 is written, the corresponding status bit in the RxFilterWoLStatus register is cleared." /> + <BitField start="9" size="23" name="RESERVED" description="Unused" /> + </Register> + <Register start="+0x210" size="4" name="HASHFILTERL" access="Read/Write" description="Hash filter table LSBs register." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="HFL" description="HashFilterL. Bits 31:0 of the imperfect filter hash table for receive filtering." /> + </Register> + <Register start="+0x214" size="4" name="HASHFILTERH" access="Read/Write" description="Hash filter table MSBs register." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="HFH" description="Bits 63:32 of the imperfect filter hash table for receive filtering." /> + </Register> + <Register start="+0xFE0" size="4" name="INTSTATUS" access="ReadOnly" description="Interrupt status register." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RXOVERRUNINT" description="Interrupt set on a fatal overrun error in the receive queue. The fatal interrupt should be resolved by a Rx soft-reset. The bit is not set when there is a nonfatal overrun error." /> + <BitField start="1" size="1" name="RXERRORINT" description="Interrupt trigger on receive errors: AlignmentError, RangeError, LengthError, SymbolError, CRCError or NoDescriptor or Overrun." /> + <BitField start="2" size="1" name="RXFINISHEDINT" description="Interrupt triggered when all receive descriptors have been processed i.e. on the transition to the situation where ProduceIndex == ConsumeIndex." /> + <BitField start="3" size="1" name="RXDONEINT" description="Interrupt triggered when a receive descriptor has been processed while the Interrupt bit in the Control field of the descriptor was set." /> + <BitField start="4" size="1" name="TXUNDERRUNINT" description="Interrupt set on a fatal underrun error in the transmit queue. The fatal interrupt should be resolved by a Tx soft-reset. The bit is not set when there is a nonfatal underrun error." /> + <BitField start="5" size="1" name="TXERRORINT" description="Interrupt trigger on transmit errors: LateCollision, ExcessiveCollision and ExcessiveDefer, NoDescriptor or Underrun." /> + <BitField start="6" size="1" name="TXFINISHEDINT" description="Interrupt triggered when all transmit descriptors have been processed i.e. on the transition to the situation where ProduceIndex == ConsumeIndex." /> + <BitField start="7" size="1" name="TXDONEINT" description="Interrupt triggered when a descriptor has been transmitted while the Interrupt bit in the Control field of the descriptor was set." /> + <BitField start="8" size="4" name="RESERVED" description="Unused" /> + <BitField start="12" size="1" name="SOFTINT" description="Interrupt triggered by software writing a 1 to the SoftIntSet bit in the IntSet register." /> + <BitField start="13" size="1" name="WAKEUPINT" description="Interrupt triggered by a Wake-up event detected by the receive filter." /> + <BitField start="14" size="18" name="RESERVED" description="Unused" /> + </Register> + <Register start="+0xFE4" size="4" name="INTENABLE" access="Read/Write" description="Interrupt enable register." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RXOVERRUNINTEN" description="Enable for interrupt trigger on receive buffer overrun or descriptor underrun situations." /> + <BitField start="1" size="1" name="RXERRORINTEN" description="Enable for interrupt trigger on receive errors." /> + <BitField start="2" size="1" name="RXFINISHEDINTEN" description="Enable for interrupt triggered when all receive descriptors have been processed i.e. on the transition to the situation where ProduceIndex == ConsumeIndex." /> + <BitField start="3" size="1" name="RXDONEINTEN" description="Enable for interrupt triggered when a receive descriptor has been processed while the Interrupt bit in the Control field of the descriptor was set." /> + <BitField start="4" size="1" name="TXUNDERRUNINTEN" description="Enable for interrupt trigger on transmit buffer or descriptor underrun situations." /> + <BitField start="5" size="1" name="TXERRORINTEN" description="Enable for interrupt trigger on transmit errors." /> + <BitField start="6" size="1" name="TXFINISHEDINTEN" description="Enable for interrupt triggered when all transmit descriptors have been processed i.e. on the transition to the situation where ProduceIndex == ConsumeIndex." /> + <BitField start="7" size="1" name="TXDONEINTEN" description="Enable for interrupt triggered when a descriptor has been transmitted while the Interrupt bit in the Control field of the descriptor was set." /> + <BitField start="8" size="4" name="RESERVED" description="Unused" /> + <BitField start="12" size="1" name="SOFTINTEN" description="Enable for interrupt triggered by the SoftInt bit in the IntStatus register, caused by software writing a 1 to the SoftIntSet bit in the IntSet register." /> + <BitField start="13" size="1" name="WAKEUPINTEN" description="Enable for interrupt triggered by a Wake-up event detected by the receive filter." /> + <BitField start="14" size="18" name="RESERVED" description="Unused" /> + </Register> + <Register start="+0xFE8" size="4" name="INTCLEAR" access="WriteOnly" description="Interrupt clear register." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RXOVERRUNINTCLR" description="Writing a 1 clears the corresponding status bit in interrupt status register IntStatus." /> + <BitField start="1" size="1" name="RXERRORINTCLR" description="Writing a 1 clears the corresponding status bit in interrupt status register IntStatus." /> + <BitField start="2" size="1" name="RXFINISHEDINTCLR" description="Writing a 1 clears the corresponding status bit in interrupt status register IntStatus." /> + <BitField start="3" size="1" name="RXDONEINTCLR" description="Writing a 1 clears the corresponding status bit in interrupt status register IntStatus." /> + <BitField start="4" size="1" name="TXUNDERRUNINTCLR" description="Writing a 1 clears the corresponding status bit in interrupt status register IntStatus." /> + <BitField start="5" size="1" name="TXERRORINTCLR" description="Writing a 1 clears the corresponding status bit in interrupt status register IntStatus." /> + <BitField start="6" size="1" name="TXFINISHEDINTCLR" description="Writing a 1 clears the corresponding status bit in interrupt status register IntStatus." /> + <BitField start="7" size="1" name="TXDONEINTCLR" description="Writing a 1 clears the corresponding status bit in interrupt status register IntStatus." /> + <BitField start="8" size="4" name="RESERVED" description="Unused" /> + <BitField start="12" size="1" name="SOFTINTCLR" description="Writing a 1 clears the corresponding status bit in interrupt status register IntStatus." /> + <BitField start="13" size="1" name="WAKEUPINTCLR" description="Writing a 1 clears the corresponding status bit in interrupt status register IntStatus." /> + <BitField start="14" size="18" name="RESERVED" description="Unused" /> + </Register> + <Register start="+0xFEC" size="4" name="INTSET" access="WriteOnly" description="Interrupt set register." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RXOVERRUNINTSET" description="Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus." /> + <BitField start="1" size="1" name="RXERRORINTSET" description="Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus." /> + <BitField start="2" size="1" name="RXFINISHEDINTSET" description="Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus." /> + <BitField start="3" size="1" name="RXDONEINTSET" description="Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus." /> + <BitField start="4" size="1" name="TXUNDERRUNINTSET" description="Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus." /> + <BitField start="5" size="1" name="TXERRORINTSET" description="Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus." /> + <BitField start="6" size="1" name="TXFINISHEDINTSET" description="Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus." /> + <BitField start="7" size="1" name="TXDONEINTSET" description="Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus." /> + <BitField start="8" size="4" name="RESERVED" description="Unused" /> + <BitField start="12" size="1" name="SOFTINTSET" description="Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus." /> + <BitField start="13" size="1" name="WAKEUPINTSET" description="Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus." /> + <BitField start="14" size="18" name="RESERVED" description="Unused" /> + </Register> + <Register start="+0xFF4" size="4" name="POWERDOWN" access="Read/Write" description="Power-down register." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="31" name="RESERVED" description="Unused" /> + <BitField start="31" size="1" name="PD" description="PowerDownMACAHB. If true, all AHB accesses will return a read/write error, except accesses to the Power-Down register." /> + </Register> + </RegisterGroup> + <RegisterGroup name="GPDMA" start="0x50004000" description="General purpose DMA controller"> + <Register start="+0x000" size="4" name="INTSTAT" access="ReadOnly" description="DMA Interrupt Status Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="INTSTAT0" description="Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request." /> + <BitField start="1" size="1" name="INTSTAT1" description="Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request." /> + <BitField start="2" size="1" name="INTSTAT2" description="Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request." /> + <BitField start="3" size="1" name="INTSTAT3" description="Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request." /> + <BitField start="4" size="1" name="INTSTAT4" description="Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request." /> + <BitField start="5" size="1" name="INTSTAT5" description="Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request." /> + <BitField start="6" size="1" name="INTSTAT6" description="Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request." /> + <BitField start="7" size="1" name="INTSTAT7" description="Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x004" size="4" name="INTTCSTAT" access="ReadOnly" description="DMA Interrupt Terminal Count Request Status Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="INTTCSTAT0" description="Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." /> + <BitField start="1" size="1" name="INTTCSTAT1" description="Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." /> + <BitField start="2" size="1" name="INTTCSTAT2" description="Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." /> + <BitField start="3" size="1" name="INTTCSTAT3" description="Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." /> + <BitField start="4" size="1" name="INTTCSTAT4" description="Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." /> + <BitField start="5" size="1" name="INTTCSTAT5" description="Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." /> + <BitField start="6" size="1" name="INTTCSTAT6" description="Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." /> + <BitField start="7" size="1" name="INTTCSTAT7" description="Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x008" size="4" name="INTTCCLEAR" access="WriteOnly" description="DMA Interrupt Terminal Count Request Clear Register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="INTTCCLEAR0" description="Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt." /> + <BitField start="1" size="1" name="INTTCCLEAR1" description="Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt." /> + <BitField start="2" size="1" name="INTTCCLEAR2" description="Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt." /> + <BitField start="3" size="1" name="INTTCCLEAR3" description="Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt." /> + <BitField start="4" size="1" name="INTTCCLEAR4" description="Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt." /> + <BitField start="5" size="1" name="INTTCCLEAR5" description="Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt." /> + <BitField start="6" size="1" name="INTTCCLEAR6" description="Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt." /> + <BitField start="7" size="1" name="INTTCCLEAR7" description="Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x00C" size="4" name="INTERRSTAT" access="ReadOnly" description="DMA Interrupt Error Status Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="INTERRSTAT0" description="Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." /> + <BitField start="1" size="1" name="INTERRSTAT1" description="Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." /> + <BitField start="2" size="1" name="INTERRSTAT2" description="Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." /> + <BitField start="3" size="1" name="INTERRSTAT3" description="Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." /> + <BitField start="4" size="1" name="INTERRSTAT4" description="Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." /> + <BitField start="5" size="1" name="INTERRSTAT5" description="Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." /> + <BitField start="6" size="1" name="INTERRSTAT6" description="Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." /> + <BitField start="7" size="1" name="INTERRSTAT7" description="Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x010" size="4" name="INTERRCLR" access="WriteOnly" description="DMA Interrupt Error Clear Register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="INTERRCLR0" description="Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt." /> + <BitField start="1" size="1" name="INTERRCLR1" description="Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt." /> + <BitField start="2" size="1" name="INTERRCLR2" description="Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt." /> + <BitField start="3" size="1" name="INTERRCLR3" description="Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt." /> + <BitField start="4" size="1" name="INTERRCLR4" description="Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt." /> + <BitField start="5" size="1" name="INTERRCLR5" description="Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt." /> + <BitField start="6" size="1" name="INTERRCLR6" description="Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt." /> + <BitField start="7" size="1" name="INTERRCLR7" description="Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x014" size="4" name="RAWINTTCSTAT" access="ReadOnly" description="DMA Raw Interrupt Terminal Count Status Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RAWINTTCSTAT0" description="Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." /> + <BitField start="1" size="1" name="RAWINTTCSTAT1" description="Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." /> + <BitField start="2" size="1" name="RAWINTTCSTAT2" description="Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." /> + <BitField start="3" size="1" name="RAWINTTCSTAT3" description="Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." /> + <BitField start="4" size="1" name="RAWINTTCSTAT4" description="Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." /> + <BitField start="5" size="1" name="RAWINTTCSTAT5" description="Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." /> + <BitField start="6" size="1" name="RAWINTTCSTAT6" description="Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." /> + <BitField start="7" size="1" name="RAWINTTCSTAT7" description="Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x018" size="4" name="RAWINTERRSTAT" access="ReadOnly" description="DMA Raw Error Interrupt Status Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RAWINTERRSTAT0" description="Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." /> + <BitField start="1" size="1" name="RAWINTERRSTAT1" description="Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." /> + <BitField start="2" size="1" name="RAWINTERRSTAT2" description="Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." /> + <BitField start="3" size="1" name="RAWINTERRSTAT3" description="Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." /> + <BitField start="4" size="1" name="RAWINTERRSTAT4" description="Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." /> + <BitField start="5" size="1" name="RAWINTERRSTAT5" description="Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." /> + <BitField start="6" size="1" name="RAWINTERRSTAT6" description="Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." /> + <BitField start="7" size="1" name="RAWINTERRSTAT7" description="Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x01C" size="4" name="ENBLDCHNS" access="ReadOnly" description="DMA Enabled Channel Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="ENABLEDCHANNELS0" description="Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled." /> + <BitField start="1" size="1" name="ENABLEDCHANNELS1" description="Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled." /> + <BitField start="2" size="1" name="ENABLEDCHANNELS2" description="Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled." /> + <BitField start="3" size="1" name="ENABLEDCHANNELS3" description="Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled." /> + <BitField start="4" size="1" name="ENABLEDCHANNELS4" description="Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled." /> + <BitField start="5" size="1" name="ENABLEDCHANNELS5" description="Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled." /> + <BitField start="6" size="1" name="ENABLEDCHANNELS6" description="Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled." /> + <BitField start="7" size="1" name="ENABLEDCHANNELS7" description="Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x020" size="4" name="SOFTBREQ" access="Read/Write" description="DMA Software Burst Request Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="SOFTBREQ0" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." /> + <BitField start="1" size="1" name="SOFTBREQ1" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." /> + <BitField start="2" size="1" name="SOFTBREQ2" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." /> + <BitField start="3" size="1" name="SOFTBREQ3" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." /> + <BitField start="4" size="1" name="SOFTBREQ4" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." /> + <BitField start="5" size="1" name="SOFTBREQ5" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." /> + <BitField start="6" size="1" name="SOFTBREQ6" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." /> + <BitField start="7" size="1" name="SOFTBREQ7" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." /> + <BitField start="8" size="1" name="SOFTBREQ8" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." /> + <BitField start="9" size="1" name="SOFTBREQ9" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." /> + <BitField start="10" size="1" name="SOFTBREQ10" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." /> + <BitField start="11" size="1" name="SOFTBREQ11" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." /> + <BitField start="12" size="1" name="SOFTBREQ12" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." /> + <BitField start="13" size="1" name="SOFTBREQ13" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." /> + <BitField start="14" size="1" name="SOFTBREQ14" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." /> + <BitField start="15" size="1" name="SOFTBREQ15" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." /> + <BitField start="16" size="16" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x024" size="4" name="SOFTSREQ" access="Read/Write" description="DMA Software Single Request Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="SOFTSREQ0" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." /> + <BitField start="1" size="1" name="SOFTSREQ1" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." /> + <BitField start="2" size="1" name="SOFTSREQ2" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." /> + <BitField start="3" size="1" name="SOFTSREQ3" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." /> + <BitField start="4" size="1" name="SOFTSREQ4" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." /> + <BitField start="5" size="1" name="SOFTSREQ5" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." /> + <BitField start="6" size="1" name="SOFTSREQ6" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." /> + <BitField start="7" size="1" name="SOFTSREQ7" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." /> + <BitField start="8" size="1" name="SOFTSREQ8" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." /> + <BitField start="9" size="1" name="SOFTSREQ9" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." /> + <BitField start="10" size="1" name="SOFTSREQ10" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." /> + <BitField start="11" size="1" name="SOFTSREQ11" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." /> + <BitField start="12" size="1" name="SOFTSREQ12" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." /> + <BitField start="13" size="1" name="SOFTSREQ13" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." /> + <BitField start="14" size="1" name="SOFTSREQ14" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." /> + <BitField start="15" size="1" name="SOFTSREQ15" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." /> + <BitField start="16" size="16" name="RESERVED" description="Reserved. Read undefined. Write reserved bits as zero." /> + </Register> + <Register start="+0x028" size="4" name="SOFTLBREQ" access="Read/Write" description="DMA Software Last Burst Request Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="SOFTLBREQ0" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." /> + <BitField start="1" size="1" name="SOFTLBREQ1" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." /> + <BitField start="2" size="1" name="SOFTLBREQ2" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." /> + <BitField start="3" size="1" name="SOFTLBREQ3" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." /> + <BitField start="4" size="1" name="SOFTLBREQ4" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." /> + <BitField start="5" size="1" name="SOFTLBREQ5" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." /> + <BitField start="6" size="1" name="SOFTLBREQ6" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." /> + <BitField start="7" size="1" name="SOFTLBREQ7" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." /> + <BitField start="8" size="1" name="SOFTLBREQ8" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." /> + <BitField start="9" size="1" name="SOFTLBREQ9" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." /> + <BitField start="10" size="1" name="SOFTLBREQ10" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." /> + <BitField start="11" size="1" name="SOFTLBREQ11" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." /> + <BitField start="12" size="1" name="SOFTLBREQ12" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." /> + <BitField start="13" size="1" name="SOFTLBREQ13" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." /> + <BitField start="14" size="1" name="SOFTLBREQ14" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." /> + <BitField start="15" size="1" name="SOFTLBREQ15" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." /> + <BitField start="16" size="16" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x02C" size="4" name="SOFTLSREQ" access="Read/Write" description="DMA Software Last Single Request Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="SOFTLSREQ0" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." /> + <BitField start="1" size="1" name="SOFTLSREQ1" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." /> + <BitField start="2" size="1" name="SOFTLSREQ2" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." /> + <BitField start="3" size="1" name="SOFTLSREQ3" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." /> + <BitField start="4" size="1" name="SOFTLSREQ4" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." /> + <BitField start="5" size="1" name="SOFTLSREQ5" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." /> + <BitField start="6" size="1" name="SOFTLSREQ6" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." /> + <BitField start="7" size="1" name="SOFTLSREQ7" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." /> + <BitField start="8" size="1" name="SOFTLSREQ8" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." /> + <BitField start="9" size="1" name="SOFTLSREQ9" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." /> + <BitField start="10" size="1" name="SOFTLSREQ10" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." /> + <BitField start="11" size="1" name="SOFTLSREQ11" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." /> + <BitField start="12" size="1" name="SOFTLSREQ12" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." /> + <BitField start="13" size="1" name="SOFTLSREQ13" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." /> + <BitField start="14" size="1" name="SOFTLSREQ14" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." /> + <BitField start="15" size="1" name="SOFTLSREQ15" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." /> + <BitField start="16" size="16" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x030" size="4" name="CONFIG" access="Read/Write" description="DMA Configuration Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="E" description="DMA Controller enable: 0 = disabled (default). Disabling the DMA Controller reduces power consumption. 1 = enabled." /> + <BitField start="1" size="1" name="M" description="AHB Master endianness configuration: 0 = little-endian mode (default). 1 = big-endian mode." /> + <BitField start="2" size="30" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x034" size="4" name="SYNC" access="Read/Write" description="DMA Synchronization Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="DMACSYNC0" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled." /> + <BitField start="1" size="1" name="DMACSYNC1" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled." /> + <BitField start="2" size="1" name="DMACSYNC2" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled." /> + <BitField start="3" size="1" name="DMACSYNC3" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled." /> + <BitField start="4" size="1" name="DMACSYNC4" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled." /> + <BitField start="5" size="1" name="DMACSYNC5" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled." /> + <BitField start="6" size="1" name="DMACSYNC6" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled." /> + <BitField start="7" size="1" name="DMACSYNC7" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled." /> + <BitField start="8" size="1" name="DMACSYNC8" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled." /> + <BitField start="9" size="1" name="DMACSYNC9" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled." /> + <BitField start="10" size="1" name="DMACSYNC10" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled." /> + <BitField start="11" size="1" name="DMACSYNC11" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled." /> + <BitField start="12" size="1" name="DMACSYNC12" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled." /> + <BitField start="13" size="1" name="DMACSYNC13" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled." /> + <BitField start="14" size="1" name="DMACSYNC14" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled." /> + <BitField start="15" size="1" name="DMACSYNC15" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled." /> + <BitField start="16" size="16" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x100+0" size="4" name="SRCADDR0" access="Read/Write" description="DMA Channel 0 Source Address Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="SRCADDR" description="DMA source address. Reading this register will return the current source address." /> + </Register> + <Register start="+0x100+32" size="4" name="SRCADDR1" access="Read/Write" description="DMA Channel 0 Source Address Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="SRCADDR" description="DMA source address. Reading this register will return the current source address." /> + </Register> + <Register start="+0x100+64" size="4" name="SRCADDR2" access="Read/Write" description="DMA Channel 0 Source Address Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="SRCADDR" description="DMA source address. Reading this register will return the current source address." /> + </Register> + <Register start="+0x100+96" size="4" name="SRCADDR3" access="Read/Write" description="DMA Channel 0 Source Address Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="SRCADDR" description="DMA source address. Reading this register will return the current source address." /> + </Register> + <Register start="+0x100+128" size="4" name="SRCADDR4" access="Read/Write" description="DMA Channel 0 Source Address Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="SRCADDR" description="DMA source address. Reading this register will return the current source address." /> + </Register> + <Register start="+0x100+160" size="4" name="SRCADDR5" access="Read/Write" description="DMA Channel 0 Source Address Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="SRCADDR" description="DMA source address. Reading this register will return the current source address." /> + </Register> + <Register start="+0x100+192" size="4" name="SRCADDR6" access="Read/Write" description="DMA Channel 0 Source Address Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="SRCADDR" description="DMA source address. Reading this register will return the current source address." /> + </Register> + <Register start="+0x100+224" size="4" name="SRCADDR7" access="Read/Write" description="DMA Channel 0 Source Address Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="SRCADDR" description="DMA source address. Reading this register will return the current source address." /> + </Register> + <Register start="+0x104+0" size="4" name="DESTADDR0" access="Read/Write" description="DMA Channel 0 Destination Address Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="DESTADDR" description="DMA Destination address. Reading this register will return the current destination address." /> + </Register> + <Register start="+0x104+32" size="4" name="DESTADDR1" access="Read/Write" description="DMA Channel 0 Destination Address Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="DESTADDR" description="DMA Destination address. Reading this register will return the current destination address." /> + </Register> + <Register start="+0x104+64" size="4" name="DESTADDR2" access="Read/Write" description="DMA Channel 0 Destination Address Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="DESTADDR" description="DMA Destination address. Reading this register will return the current destination address." /> + </Register> + <Register start="+0x104+96" size="4" name="DESTADDR3" access="Read/Write" description="DMA Channel 0 Destination Address Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="DESTADDR" description="DMA Destination address. Reading this register will return the current destination address." /> + </Register> + <Register start="+0x104+128" size="4" name="DESTADDR4" access="Read/Write" description="DMA Channel 0 Destination Address Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="DESTADDR" description="DMA Destination address. Reading this register will return the current destination address." /> + </Register> + <Register start="+0x104+160" size="4" name="DESTADDR5" access="Read/Write" description="DMA Channel 0 Destination Address Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="DESTADDR" description="DMA Destination address. Reading this register will return the current destination address." /> + </Register> + <Register start="+0x104+192" size="4" name="DESTADDR6" access="Read/Write" description="DMA Channel 0 Destination Address Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="DESTADDR" description="DMA Destination address. Reading this register will return the current destination address." /> + </Register> + <Register start="+0x104+224" size="4" name="DESTADDR7" access="Read/Write" description="DMA Channel 0 Destination Address Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="DESTADDR" description="DMA Destination address. Reading this register will return the current destination address." /> + </Register> + <Register start="+0x108+0" size="4" name="LLI0" access="Read/Write" description="DMA Channel 0 Linked List Item Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="RESERVED" description="Reserved, and must be written as 0." /> + <BitField start="2" size="30" name="LLI" description="Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0." /> + </Register> + <Register start="+0x108+32" size="4" name="LLI1" access="Read/Write" description="DMA Channel 0 Linked List Item Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="RESERVED" description="Reserved, and must be written as 0." /> + <BitField start="2" size="30" name="LLI" description="Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0." /> + </Register> + <Register start="+0x108+64" size="4" name="LLI2" access="Read/Write" description="DMA Channel 0 Linked List Item Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="RESERVED" description="Reserved, and must be written as 0." /> + <BitField start="2" size="30" name="LLI" description="Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0." /> + </Register> + <Register start="+0x108+96" size="4" name="LLI3" access="Read/Write" description="DMA Channel 0 Linked List Item Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="RESERVED" description="Reserved, and must be written as 0." /> + <BitField start="2" size="30" name="LLI" description="Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0." /> + </Register> + <Register start="+0x108+128" size="4" name="LLI4" access="Read/Write" description="DMA Channel 0 Linked List Item Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="RESERVED" description="Reserved, and must be written as 0." /> + <BitField start="2" size="30" name="LLI" description="Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0." /> + </Register> + <Register start="+0x108+160" size="4" name="LLI5" access="Read/Write" description="DMA Channel 0 Linked List Item Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="RESERVED" description="Reserved, and must be written as 0." /> + <BitField start="2" size="30" name="LLI" description="Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0." /> + </Register> + <Register start="+0x108+192" size="4" name="LLI6" access="Read/Write" description="DMA Channel 0 Linked List Item Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="RESERVED" description="Reserved, and must be written as 0." /> + <BitField start="2" size="30" name="LLI" description="Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0." /> + </Register> + <Register start="+0x108+224" size="4" name="LLI7" access="Read/Write" description="DMA Channel 0 Linked List Item Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="RESERVED" description="Reserved, and must be written as 0." /> + <BitField start="2" size="30" name="LLI" description="Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0." /> + </Register> + <Register start="+0x10C+0" size="4" name="CONTROL0" access="Read/Write" description="DMA Channel 0 Control Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="12" name="TRANSFERSIZE" description="Transfer size. This field sets the size of the transfer when the DMA controller is the flow controller, in which case the value must be set before the channel is enabled. Transfer size is updated as data transfers are completed. A read from this field indicates the number of transfers completed on the destination bus. Reading the register when the channel is active does not give useful information because by the time that the software has processed the value read, the channel might have progressed. It is intended to be used only when a channel is enabled and then disabled. The transfer size value is not used if a peripheral is the flow controller." /> + <BitField start="12" size="3" name="SBSIZE" description="Source burst size. Indicates the number of transfers that make up a source burst. This value must be set to the burst size of the source peripheral, or if the source is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the source peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256" /> + <BitField start="15" size="3" name="DBSIZE" description="Destination burst size. Indicates the number of transfers that make up a destination burst transfer request. This value must be set to the burst size of the destination peripheral or, if the destination is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the destination peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256" /> + <BitField start="18" size="3" name="SWIDTH" description="Source transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved" /> + <BitField start="21" size="3" name="DWIDTH" description="Destination transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved" /> + <BitField start="24" size="2" name="RESERVED" description="Reserved, and must be written as 0." /> + <BitField start="26" size="1" name="SI" description="Source increment: 0 - the source address is not incremented after each transfer. 1 - the source address is incremented after each transfer." /> + <BitField start="27" size="1" name="DI" description="Destination increment: 0 - the destination address is not incremented after each transfer. 1 - the destination address is incremented after each transfer." /> + <BitField start="28" size="1" name="PROT1" description="This is provided to the peripheral during a DMA bus access and indicates that the access is in user mode or privileged mode. This information is not used in the LPC178x/177x. 0 - access is in user mode. 1 - access is in privileged mode." /> + <BitField start="29" size="1" name="PROT2" description="This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is bufferable or not bufferable. This information is not used in the LPC178x/177x. 0 - access is not bufferable. 1 - access is bufferable." /> + <BitField start="30" size="1" name="PROT3" description="This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is cacheable or not cacheable. This information is not used in the LPC178x/177x. 0 - access is not cacheable. 1 - access is cacheable." /> + <BitField start="31" size="1" name="I" description="Terminal count interrupt enable bit. 0 - the terminal count interrupt is disabled. 1 - the terminal count interrupt is enabled." /> + </Register> + <Register start="+0x10C+32" size="4" name="CONTROL1" access="Read/Write" description="DMA Channel 0 Control Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="12" name="TRANSFERSIZE" description="Transfer size. This field sets the size of the transfer when the DMA controller is the flow controller, in which case the value must be set before the channel is enabled. Transfer size is updated as data transfers are completed. A read from this field indicates the number of transfers completed on the destination bus. Reading the register when the channel is active does not give useful information because by the time that the software has processed the value read, the channel might have progressed. It is intended to be used only when a channel is enabled and then disabled. The transfer size value is not used if a peripheral is the flow controller." /> + <BitField start="12" size="3" name="SBSIZE" description="Source burst size. Indicates the number of transfers that make up a source burst. This value must be set to the burst size of the source peripheral, or if the source is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the source peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256" /> + <BitField start="15" size="3" name="DBSIZE" description="Destination burst size. Indicates the number of transfers that make up a destination burst transfer request. This value must be set to the burst size of the destination peripheral or, if the destination is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the destination peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256" /> + <BitField start="18" size="3" name="SWIDTH" description="Source transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved" /> + <BitField start="21" size="3" name="DWIDTH" description="Destination transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved" /> + <BitField start="24" size="2" name="RESERVED" description="Reserved, and must be written as 0." /> + <BitField start="26" size="1" name="SI" description="Source increment: 0 - the source address is not incremented after each transfer. 1 - the source address is incremented after each transfer." /> + <BitField start="27" size="1" name="DI" description="Destination increment: 0 - the destination address is not incremented after each transfer. 1 - the destination address is incremented after each transfer." /> + <BitField start="28" size="1" name="PROT1" description="This is provided to the peripheral during a DMA bus access and indicates that the access is in user mode or privileged mode. This information is not used in the LPC178x/177x. 0 - access is in user mode. 1 - access is in privileged mode." /> + <BitField start="29" size="1" name="PROT2" description="This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is bufferable or not bufferable. This information is not used in the LPC178x/177x. 0 - access is not bufferable. 1 - access is bufferable." /> + <BitField start="30" size="1" name="PROT3" description="This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is cacheable or not cacheable. This information is not used in the LPC178x/177x. 0 - access is not cacheable. 1 - access is cacheable." /> + <BitField start="31" size="1" name="I" description="Terminal count interrupt enable bit. 0 - the terminal count interrupt is disabled. 1 - the terminal count interrupt is enabled." /> + </Register> + <Register start="+0x10C+64" size="4" name="CONTROL2" access="Read/Write" description="DMA Channel 0 Control Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="12" name="TRANSFERSIZE" description="Transfer size. This field sets the size of the transfer when the DMA controller is the flow controller, in which case the value must be set before the channel is enabled. Transfer size is updated as data transfers are completed. A read from this field indicates the number of transfers completed on the destination bus. Reading the register when the channel is active does not give useful information because by the time that the software has processed the value read, the channel might have progressed. It is intended to be used only when a channel is enabled and then disabled. The transfer size value is not used if a peripheral is the flow controller." /> + <BitField start="12" size="3" name="SBSIZE" description="Source burst size. Indicates the number of transfers that make up a source burst. This value must be set to the burst size of the source peripheral, or if the source is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the source peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256" /> + <BitField start="15" size="3" name="DBSIZE" description="Destination burst size. Indicates the number of transfers that make up a destination burst transfer request. This value must be set to the burst size of the destination peripheral or, if the destination is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the destination peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256" /> + <BitField start="18" size="3" name="SWIDTH" description="Source transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved" /> + <BitField start="21" size="3" name="DWIDTH" description="Destination transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved" /> + <BitField start="24" size="2" name="RESERVED" description="Reserved, and must be written as 0." /> + <BitField start="26" size="1" name="SI" description="Source increment: 0 - the source address is not incremented after each transfer. 1 - the source address is incremented after each transfer." /> + <BitField start="27" size="1" name="DI" description="Destination increment: 0 - the destination address is not incremented after each transfer. 1 - the destination address is incremented after each transfer." /> + <BitField start="28" size="1" name="PROT1" description="This is provided to the peripheral during a DMA bus access and indicates that the access is in user mode or privileged mode. This information is not used in the LPC178x/177x. 0 - access is in user mode. 1 - access is in privileged mode." /> + <BitField start="29" size="1" name="PROT2" description="This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is bufferable or not bufferable. This information is not used in the LPC178x/177x. 0 - access is not bufferable. 1 - access is bufferable." /> + <BitField start="30" size="1" name="PROT3" description="This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is cacheable or not cacheable. This information is not used in the LPC178x/177x. 0 - access is not cacheable. 1 - access is cacheable." /> + <BitField start="31" size="1" name="I" description="Terminal count interrupt enable bit. 0 - the terminal count interrupt is disabled. 1 - the terminal count interrupt is enabled." /> + </Register> + <Register start="+0x10C+96" size="4" name="CONTROL3" access="Read/Write" description="DMA Channel 0 Control Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="12" name="TRANSFERSIZE" description="Transfer size. This field sets the size of the transfer when the DMA controller is the flow controller, in which case the value must be set before the channel is enabled. Transfer size is updated as data transfers are completed. A read from this field indicates the number of transfers completed on the destination bus. Reading the register when the channel is active does not give useful information because by the time that the software has processed the value read, the channel might have progressed. It is intended to be used only when a channel is enabled and then disabled. The transfer size value is not used if a peripheral is the flow controller." /> + <BitField start="12" size="3" name="SBSIZE" description="Source burst size. Indicates the number of transfers that make up a source burst. This value must be set to the burst size of the source peripheral, or if the source is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the source peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256" /> + <BitField start="15" size="3" name="DBSIZE" description="Destination burst size. Indicates the number of transfers that make up a destination burst transfer request. This value must be set to the burst size of the destination peripheral or, if the destination is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the destination peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256" /> + <BitField start="18" size="3" name="SWIDTH" description="Source transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved" /> + <BitField start="21" size="3" name="DWIDTH" description="Destination transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved" /> + <BitField start="24" size="2" name="RESERVED" description="Reserved, and must be written as 0." /> + <BitField start="26" size="1" name="SI" description="Source increment: 0 - the source address is not incremented after each transfer. 1 - the source address is incremented after each transfer." /> + <BitField start="27" size="1" name="DI" description="Destination increment: 0 - the destination address is not incremented after each transfer. 1 - the destination address is incremented after each transfer." /> + <BitField start="28" size="1" name="PROT1" description="This is provided to the peripheral during a DMA bus access and indicates that the access is in user mode or privileged mode. This information is not used in the LPC178x/177x. 0 - access is in user mode. 1 - access is in privileged mode." /> + <BitField start="29" size="1" name="PROT2" description="This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is bufferable or not bufferable. This information is not used in the LPC178x/177x. 0 - access is not bufferable. 1 - access is bufferable." /> + <BitField start="30" size="1" name="PROT3" description="This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is cacheable or not cacheable. This information is not used in the LPC178x/177x. 0 - access is not cacheable. 1 - access is cacheable." /> + <BitField start="31" size="1" name="I" description="Terminal count interrupt enable bit. 0 - the terminal count interrupt is disabled. 1 - the terminal count interrupt is enabled." /> + </Register> + <Register start="+0x10C+128" size="4" name="CONTROL4" access="Read/Write" description="DMA Channel 0 Control Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="12" name="TRANSFERSIZE" description="Transfer size. This field sets the size of the transfer when the DMA controller is the flow controller, in which case the value must be set before the channel is enabled. Transfer size is updated as data transfers are completed. A read from this field indicates the number of transfers completed on the destination bus. Reading the register when the channel is active does not give useful information because by the time that the software has processed the value read, the channel might have progressed. It is intended to be used only when a channel is enabled and then disabled. The transfer size value is not used if a peripheral is the flow controller." /> + <BitField start="12" size="3" name="SBSIZE" description="Source burst size. Indicates the number of transfers that make up a source burst. This value must be set to the burst size of the source peripheral, or if the source is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the source peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256" /> + <BitField start="15" size="3" name="DBSIZE" description="Destination burst size. Indicates the number of transfers that make up a destination burst transfer request. This value must be set to the burst size of the destination peripheral or, if the destination is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the destination peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256" /> + <BitField start="18" size="3" name="SWIDTH" description="Source transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved" /> + <BitField start="21" size="3" name="DWIDTH" description="Destination transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved" /> + <BitField start="24" size="2" name="RESERVED" description="Reserved, and must be written as 0." /> + <BitField start="26" size="1" name="SI" description="Source increment: 0 - the source address is not incremented after each transfer. 1 - the source address is incremented after each transfer." /> + <BitField start="27" size="1" name="DI" description="Destination increment: 0 - the destination address is not incremented after each transfer. 1 - the destination address is incremented after each transfer." /> + <BitField start="28" size="1" name="PROT1" description="This is provided to the peripheral during a DMA bus access and indicates that the access is in user mode or privileged mode. This information is not used in the LPC178x/177x. 0 - access is in user mode. 1 - access is in privileged mode." /> + <BitField start="29" size="1" name="PROT2" description="This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is bufferable or not bufferable. This information is not used in the LPC178x/177x. 0 - access is not bufferable. 1 - access is bufferable." /> + <BitField start="30" size="1" name="PROT3" description="This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is cacheable or not cacheable. This information is not used in the LPC178x/177x. 0 - access is not cacheable. 1 - access is cacheable." /> + <BitField start="31" size="1" name="I" description="Terminal count interrupt enable bit. 0 - the terminal count interrupt is disabled. 1 - the terminal count interrupt is enabled." /> + </Register> + <Register start="+0x10C+160" size="4" name="CONTROL5" access="Read/Write" description="DMA Channel 0 Control Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="12" name="TRANSFERSIZE" description="Transfer size. This field sets the size of the transfer when the DMA controller is the flow controller, in which case the value must be set before the channel is enabled. Transfer size is updated as data transfers are completed. A read from this field indicates the number of transfers completed on the destination bus. Reading the register when the channel is active does not give useful information because by the time that the software has processed the value read, the channel might have progressed. It is intended to be used only when a channel is enabled and then disabled. The transfer size value is not used if a peripheral is the flow controller." /> + <BitField start="12" size="3" name="SBSIZE" description="Source burst size. Indicates the number of transfers that make up a source burst. This value must be set to the burst size of the source peripheral, or if the source is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the source peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256" /> + <BitField start="15" size="3" name="DBSIZE" description="Destination burst size. Indicates the number of transfers that make up a destination burst transfer request. This value must be set to the burst size of the destination peripheral or, if the destination is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the destination peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256" /> + <BitField start="18" size="3" name="SWIDTH" description="Source transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved" /> + <BitField start="21" size="3" name="DWIDTH" description="Destination transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved" /> + <BitField start="24" size="2" name="RESERVED" description="Reserved, and must be written as 0." /> + <BitField start="26" size="1" name="SI" description="Source increment: 0 - the source address is not incremented after each transfer. 1 - the source address is incremented after each transfer." /> + <BitField start="27" size="1" name="DI" description="Destination increment: 0 - the destination address is not incremented after each transfer. 1 - the destination address is incremented after each transfer." /> + <BitField start="28" size="1" name="PROT1" description="This is provided to the peripheral during a DMA bus access and indicates that the access is in user mode or privileged mode. This information is not used in the LPC178x/177x. 0 - access is in user mode. 1 - access is in privileged mode." /> + <BitField start="29" size="1" name="PROT2" description="This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is bufferable or not bufferable. This information is not used in the LPC178x/177x. 0 - access is not bufferable. 1 - access is bufferable." /> + <BitField start="30" size="1" name="PROT3" description="This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is cacheable or not cacheable. This information is not used in the LPC178x/177x. 0 - access is not cacheable. 1 - access is cacheable." /> + <BitField start="31" size="1" name="I" description="Terminal count interrupt enable bit. 0 - the terminal count interrupt is disabled. 1 - the terminal count interrupt is enabled." /> + </Register> + <Register start="+0x10C+192" size="4" name="CONTROL6" access="Read/Write" description="DMA Channel 0 Control Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="12" name="TRANSFERSIZE" description="Transfer size. This field sets the size of the transfer when the DMA controller is the flow controller, in which case the value must be set before the channel is enabled. Transfer size is updated as data transfers are completed. A read from this field indicates the number of transfers completed on the destination bus. Reading the register when the channel is active does not give useful information because by the time that the software has processed the value read, the channel might have progressed. It is intended to be used only when a channel is enabled and then disabled. The transfer size value is not used if a peripheral is the flow controller." /> + <BitField start="12" size="3" name="SBSIZE" description="Source burst size. Indicates the number of transfers that make up a source burst. This value must be set to the burst size of the source peripheral, or if the source is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the source peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256" /> + <BitField start="15" size="3" name="DBSIZE" description="Destination burst size. Indicates the number of transfers that make up a destination burst transfer request. This value must be set to the burst size of the destination peripheral or, if the destination is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the destination peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256" /> + <BitField start="18" size="3" name="SWIDTH" description="Source transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved" /> + <BitField start="21" size="3" name="DWIDTH" description="Destination transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved" /> + <BitField start="24" size="2" name="RESERVED" description="Reserved, and must be written as 0." /> + <BitField start="26" size="1" name="SI" description="Source increment: 0 - the source address is not incremented after each transfer. 1 - the source address is incremented after each transfer." /> + <BitField start="27" size="1" name="DI" description="Destination increment: 0 - the destination address is not incremented after each transfer. 1 - the destination address is incremented after each transfer." /> + <BitField start="28" size="1" name="PROT1" description="This is provided to the peripheral during a DMA bus access and indicates that the access is in user mode or privileged mode. This information is not used in the LPC178x/177x. 0 - access is in user mode. 1 - access is in privileged mode." /> + <BitField start="29" size="1" name="PROT2" description="This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is bufferable or not bufferable. This information is not used in the LPC178x/177x. 0 - access is not bufferable. 1 - access is bufferable." /> + <BitField start="30" size="1" name="PROT3" description="This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is cacheable or not cacheable. This information is not used in the LPC178x/177x. 0 - access is not cacheable. 1 - access is cacheable." /> + <BitField start="31" size="1" name="I" description="Terminal count interrupt enable bit. 0 - the terminal count interrupt is disabled. 1 - the terminal count interrupt is enabled." /> + </Register> + <Register start="+0x10C+224" size="4" name="CONTROL7" access="Read/Write" description="DMA Channel 0 Control Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="12" name="TRANSFERSIZE" description="Transfer size. This field sets the size of the transfer when the DMA controller is the flow controller, in which case the value must be set before the channel is enabled. Transfer size is updated as data transfers are completed. A read from this field indicates the number of transfers completed on the destination bus. Reading the register when the channel is active does not give useful information because by the time that the software has processed the value read, the channel might have progressed. It is intended to be used only when a channel is enabled and then disabled. The transfer size value is not used if a peripheral is the flow controller." /> + <BitField start="12" size="3" name="SBSIZE" description="Source burst size. Indicates the number of transfers that make up a source burst. This value must be set to the burst size of the source peripheral, or if the source is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the source peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256" /> + <BitField start="15" size="3" name="DBSIZE" description="Destination burst size. Indicates the number of transfers that make up a destination burst transfer request. This value must be set to the burst size of the destination peripheral or, if the destination is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the destination peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256" /> + <BitField start="18" size="3" name="SWIDTH" description="Source transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved" /> + <BitField start="21" size="3" name="DWIDTH" description="Destination transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved" /> + <BitField start="24" size="2" name="RESERVED" description="Reserved, and must be written as 0." /> + <BitField start="26" size="1" name="SI" description="Source increment: 0 - the source address is not incremented after each transfer. 1 - the source address is incremented after each transfer." /> + <BitField start="27" size="1" name="DI" description="Destination increment: 0 - the destination address is not incremented after each transfer. 1 - the destination address is incremented after each transfer." /> + <BitField start="28" size="1" name="PROT1" description="This is provided to the peripheral during a DMA bus access and indicates that the access is in user mode or privileged mode. This information is not used in the LPC178x/177x. 0 - access is in user mode. 1 - access is in privileged mode." /> + <BitField start="29" size="1" name="PROT2" description="This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is bufferable or not bufferable. This information is not used in the LPC178x/177x. 0 - access is not bufferable. 1 - access is bufferable." /> + <BitField start="30" size="1" name="PROT3" description="This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is cacheable or not cacheable. This information is not used in the LPC178x/177x. 0 - access is not cacheable. 1 - access is cacheable." /> + <BitField start="31" size="1" name="I" description="Terminal count interrupt enable bit. 0 - the terminal count interrupt is disabled. 1 - the terminal count interrupt is enabled." /> + </Register> + <Register start="+0x110+0" size="4" name="CONFIG0" access="Read/Write" description="DMA Channel 0 Configuration Register[1]" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="E" description="Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: 0 = channel disabled. 1 = channel enabled. The Channel Enable bit status can also be found by reading the DMACEnbldChns Register. A channel is enabled by setting this bit. A channel can be disabled by clearing the Enable bit. This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled. Any data in the FIFO of the relevant channel is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached, the DMA transfer is completed, or if a channel error is encountered. If a channel must be disabled without losing data in the FIFO, the Halt bit must be set so that further DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable bit can be cleared." /> + <BitField start="1" size="5" name="SRCPERIPHERAL" description="Source peripheral. This value selects the DMA source request peripheral. This field is ignored if the source of the transfer is from memory. See Table 672 for peripheral identification." /> + <BitField start="6" size="5" name="DESTPERIPHERAL" description="Destination peripheral. This value selects the DMA destination request peripheral. This field is ignored if the destination of the transfer is to memory. See Table 672 for peripheral identification." /> + <BitField start="11" size="3" name="TRANSFERTYPE" description="This value indicates the type of transfer and specifies the flow controller. The transfer type can be memory-to-memory, memory-to-peripheral, peripheral-to-memory, or peripheral-to-peripheral. Flow can be controlled by the DMA controller, the source peripheral, or the destination peripheral. Refer to Table 694 for the encoding of this field." /> + <BitField start="14" size="1" name="IE" description="Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel." /> + <BitField start="15" size="1" name="ITC" description="Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel." /> + <BitField start="16" size="1" name="L" description="Lock. When set, this bit enables locked transfers. This information is not used in the LPC178x/177x." /> + <BitField start="17" size="1" name="A" description="Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel. This is a read-only bit." /> + <BitField start="18" size="1" name="H" description="Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The contents of the channel FIFO are drained. This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel." /> + <BitField start="19" size="13" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x110+32" size="4" name="CONFIG1" access="Read/Write" description="DMA Channel 0 Configuration Register[1]" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="E" description="Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: 0 = channel disabled. 1 = channel enabled. The Channel Enable bit status can also be found by reading the DMACEnbldChns Register. A channel is enabled by setting this bit. A channel can be disabled by clearing the Enable bit. This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled. Any data in the FIFO of the relevant channel is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached, the DMA transfer is completed, or if a channel error is encountered. If a channel must be disabled without losing data in the FIFO, the Halt bit must be set so that further DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable bit can be cleared." /> + <BitField start="1" size="5" name="SRCPERIPHERAL" description="Source peripheral. This value selects the DMA source request peripheral. This field is ignored if the source of the transfer is from memory. See Table 672 for peripheral identification." /> + <BitField start="6" size="5" name="DESTPERIPHERAL" description="Destination peripheral. This value selects the DMA destination request peripheral. This field is ignored if the destination of the transfer is to memory. See Table 672 for peripheral identification." /> + <BitField start="11" size="3" name="TRANSFERTYPE" description="This value indicates the type of transfer and specifies the flow controller. The transfer type can be memory-to-memory, memory-to-peripheral, peripheral-to-memory, or peripheral-to-peripheral. Flow can be controlled by the DMA controller, the source peripheral, or the destination peripheral. Refer to Table 694 for the encoding of this field." /> + <BitField start="14" size="1" name="IE" description="Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel." /> + <BitField start="15" size="1" name="ITC" description="Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel." /> + <BitField start="16" size="1" name="L" description="Lock. When set, this bit enables locked transfers. This information is not used in the LPC178x/177x." /> + <BitField start="17" size="1" name="A" description="Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel. This is a read-only bit." /> + <BitField start="18" size="1" name="H" description="Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The contents of the channel FIFO are drained. This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel." /> + <BitField start="19" size="13" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x110+64" size="4" name="CONFIG2" access="Read/Write" description="DMA Channel 0 Configuration Register[1]" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="E" description="Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: 0 = channel disabled. 1 = channel enabled. The Channel Enable bit status can also be found by reading the DMACEnbldChns Register. A channel is enabled by setting this bit. A channel can be disabled by clearing the Enable bit. This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled. Any data in the FIFO of the relevant channel is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached, the DMA transfer is completed, or if a channel error is encountered. If a channel must be disabled without losing data in the FIFO, the Halt bit must be set so that further DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable bit can be cleared." /> + <BitField start="1" size="5" name="SRCPERIPHERAL" description="Source peripheral. This value selects the DMA source request peripheral. This field is ignored if the source of the transfer is from memory. See Table 672 for peripheral identification." /> + <BitField start="6" size="5" name="DESTPERIPHERAL" description="Destination peripheral. This value selects the DMA destination request peripheral. This field is ignored if the destination of the transfer is to memory. See Table 672 for peripheral identification." /> + <BitField start="11" size="3" name="TRANSFERTYPE" description="This value indicates the type of transfer and specifies the flow controller. The transfer type can be memory-to-memory, memory-to-peripheral, peripheral-to-memory, or peripheral-to-peripheral. Flow can be controlled by the DMA controller, the source peripheral, or the destination peripheral. Refer to Table 694 for the encoding of this field." /> + <BitField start="14" size="1" name="IE" description="Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel." /> + <BitField start="15" size="1" name="ITC" description="Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel." /> + <BitField start="16" size="1" name="L" description="Lock. When set, this bit enables locked transfers. This information is not used in the LPC178x/177x." /> + <BitField start="17" size="1" name="A" description="Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel. This is a read-only bit." /> + <BitField start="18" size="1" name="H" description="Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The contents of the channel FIFO are drained. This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel." /> + <BitField start="19" size="13" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x110+96" size="4" name="CONFIG3" access="Read/Write" description="DMA Channel 0 Configuration Register[1]" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="E" description="Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: 0 = channel disabled. 1 = channel enabled. The Channel Enable bit status can also be found by reading the DMACEnbldChns Register. A channel is enabled by setting this bit. A channel can be disabled by clearing the Enable bit. This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled. Any data in the FIFO of the relevant channel is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached, the DMA transfer is completed, or if a channel error is encountered. If a channel must be disabled without losing data in the FIFO, the Halt bit must be set so that further DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable bit can be cleared." /> + <BitField start="1" size="5" name="SRCPERIPHERAL" description="Source peripheral. This value selects the DMA source request peripheral. This field is ignored if the source of the transfer is from memory. See Table 672 for peripheral identification." /> + <BitField start="6" size="5" name="DESTPERIPHERAL" description="Destination peripheral. This value selects the DMA destination request peripheral. This field is ignored if the destination of the transfer is to memory. See Table 672 for peripheral identification." /> + <BitField start="11" size="3" name="TRANSFERTYPE" description="This value indicates the type of transfer and specifies the flow controller. The transfer type can be memory-to-memory, memory-to-peripheral, peripheral-to-memory, or peripheral-to-peripheral. Flow can be controlled by the DMA controller, the source peripheral, or the destination peripheral. Refer to Table 694 for the encoding of this field." /> + <BitField start="14" size="1" name="IE" description="Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel." /> + <BitField start="15" size="1" name="ITC" description="Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel." /> + <BitField start="16" size="1" name="L" description="Lock. When set, this bit enables locked transfers. This information is not used in the LPC178x/177x." /> + <BitField start="17" size="1" name="A" description="Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel. This is a read-only bit." /> + <BitField start="18" size="1" name="H" description="Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The contents of the channel FIFO are drained. This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel." /> + <BitField start="19" size="13" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x110+128" size="4" name="CONFIG4" access="Read/Write" description="DMA Channel 0 Configuration Register[1]" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="E" description="Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: 0 = channel disabled. 1 = channel enabled. The Channel Enable bit status can also be found by reading the DMACEnbldChns Register. A channel is enabled by setting this bit. A channel can be disabled by clearing the Enable bit. This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled. Any data in the FIFO of the relevant channel is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached, the DMA transfer is completed, or if a channel error is encountered. If a channel must be disabled without losing data in the FIFO, the Halt bit must be set so that further DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable bit can be cleared." /> + <BitField start="1" size="5" name="SRCPERIPHERAL" description="Source peripheral. This value selects the DMA source request peripheral. This field is ignored if the source of the transfer is from memory. See Table 672 for peripheral identification." /> + <BitField start="6" size="5" name="DESTPERIPHERAL" description="Destination peripheral. This value selects the DMA destination request peripheral. This field is ignored if the destination of the transfer is to memory. See Table 672 for peripheral identification." /> + <BitField start="11" size="3" name="TRANSFERTYPE" description="This value indicates the type of transfer and specifies the flow controller. The transfer type can be memory-to-memory, memory-to-peripheral, peripheral-to-memory, or peripheral-to-peripheral. Flow can be controlled by the DMA controller, the source peripheral, or the destination peripheral. Refer to Table 694 for the encoding of this field." /> + <BitField start="14" size="1" name="IE" description="Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel." /> + <BitField start="15" size="1" name="ITC" description="Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel." /> + <BitField start="16" size="1" name="L" description="Lock. When set, this bit enables locked transfers. This information is not used in the LPC178x/177x." /> + <BitField start="17" size="1" name="A" description="Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel. This is a read-only bit." /> + <BitField start="18" size="1" name="H" description="Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The contents of the channel FIFO are drained. This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel." /> + <BitField start="19" size="13" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x110+160" size="4" name="CONFIG5" access="Read/Write" description="DMA Channel 0 Configuration Register[1]" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="E" description="Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: 0 = channel disabled. 1 = channel enabled. The Channel Enable bit status can also be found by reading the DMACEnbldChns Register. A channel is enabled by setting this bit. A channel can be disabled by clearing the Enable bit. This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled. Any data in the FIFO of the relevant channel is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached, the DMA transfer is completed, or if a channel error is encountered. If a channel must be disabled without losing data in the FIFO, the Halt bit must be set so that further DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable bit can be cleared." /> + <BitField start="1" size="5" name="SRCPERIPHERAL" description="Source peripheral. This value selects the DMA source request peripheral. This field is ignored if the source of the transfer is from memory. See Table 672 for peripheral identification." /> + <BitField start="6" size="5" name="DESTPERIPHERAL" description="Destination peripheral. This value selects the DMA destination request peripheral. This field is ignored if the destination of the transfer is to memory. See Table 672 for peripheral identification." /> + <BitField start="11" size="3" name="TRANSFERTYPE" description="This value indicates the type of transfer and specifies the flow controller. The transfer type can be memory-to-memory, memory-to-peripheral, peripheral-to-memory, or peripheral-to-peripheral. Flow can be controlled by the DMA controller, the source peripheral, or the destination peripheral. Refer to Table 694 for the encoding of this field." /> + <BitField start="14" size="1" name="IE" description="Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel." /> + <BitField start="15" size="1" name="ITC" description="Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel." /> + <BitField start="16" size="1" name="L" description="Lock. When set, this bit enables locked transfers. This information is not used in the LPC178x/177x." /> + <BitField start="17" size="1" name="A" description="Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel. This is a read-only bit." /> + <BitField start="18" size="1" name="H" description="Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The contents of the channel FIFO are drained. This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel." /> + <BitField start="19" size="13" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x110+192" size="4" name="CONFIG6" access="Read/Write" description="DMA Channel 0 Configuration Register[1]" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="E" description="Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: 0 = channel disabled. 1 = channel enabled. The Channel Enable bit status can also be found by reading the DMACEnbldChns Register. A channel is enabled by setting this bit. A channel can be disabled by clearing the Enable bit. This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled. Any data in the FIFO of the relevant channel is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached, the DMA transfer is completed, or if a channel error is encountered. If a channel must be disabled without losing data in the FIFO, the Halt bit must be set so that further DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable bit can be cleared." /> + <BitField start="1" size="5" name="SRCPERIPHERAL" description="Source peripheral. This value selects the DMA source request peripheral. This field is ignored if the source of the transfer is from memory. See Table 672 for peripheral identification." /> + <BitField start="6" size="5" name="DESTPERIPHERAL" description="Destination peripheral. This value selects the DMA destination request peripheral. This field is ignored if the destination of the transfer is to memory. See Table 672 for peripheral identification." /> + <BitField start="11" size="3" name="TRANSFERTYPE" description="This value indicates the type of transfer and specifies the flow controller. The transfer type can be memory-to-memory, memory-to-peripheral, peripheral-to-memory, or peripheral-to-peripheral. Flow can be controlled by the DMA controller, the source peripheral, or the destination peripheral. Refer to Table 694 for the encoding of this field." /> + <BitField start="14" size="1" name="IE" description="Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel." /> + <BitField start="15" size="1" name="ITC" description="Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel." /> + <BitField start="16" size="1" name="L" description="Lock. When set, this bit enables locked transfers. This information is not used in the LPC178x/177x." /> + <BitField start="17" size="1" name="A" description="Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel. This is a read-only bit." /> + <BitField start="18" size="1" name="H" description="Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The contents of the channel FIFO are drained. This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel." /> + <BitField start="19" size="13" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x110+224" size="4" name="CONFIG7" access="Read/Write" description="DMA Channel 0 Configuration Register[1]" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="E" description="Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: 0 = channel disabled. 1 = channel enabled. The Channel Enable bit status can also be found by reading the DMACEnbldChns Register. A channel is enabled by setting this bit. A channel can be disabled by clearing the Enable bit. This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled. Any data in the FIFO of the relevant channel is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached, the DMA transfer is completed, or if a channel error is encountered. If a channel must be disabled without losing data in the FIFO, the Halt bit must be set so that further DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable bit can be cleared." /> + <BitField start="1" size="5" name="SRCPERIPHERAL" description="Source peripheral. This value selects the DMA source request peripheral. This field is ignored if the source of the transfer is from memory. See Table 672 for peripheral identification." /> + <BitField start="6" size="5" name="DESTPERIPHERAL" description="Destination peripheral. This value selects the DMA destination request peripheral. This field is ignored if the destination of the transfer is to memory. See Table 672 for peripheral identification." /> + <BitField start="11" size="3" name="TRANSFERTYPE" description="This value indicates the type of transfer and specifies the flow controller. The transfer type can be memory-to-memory, memory-to-peripheral, peripheral-to-memory, or peripheral-to-peripheral. Flow can be controlled by the DMA controller, the source peripheral, or the destination peripheral. Refer to Table 694 for the encoding of this field." /> + <BitField start="14" size="1" name="IE" description="Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel." /> + <BitField start="15" size="1" name="ITC" description="Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel." /> + <BitField start="16" size="1" name="L" description="Lock. When set, this bit enables locked transfers. This information is not used in the LPC178x/177x." /> + <BitField start="17" size="1" name="A" description="Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel. This is a read-only bit." /> + <BitField start="18" size="1" name="H" description="Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The contents of the channel FIFO are drained. This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel." /> + <BitField start="19" size="13" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + </RegisterGroup> + <RegisterGroup name="USB" start="0x50008000" description="USB device/host/OTG controller"> + <Register start="+0x100" size="4" name="INTST" access="ReadOnly" description="OTG Interrupt Status" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="TMR" description="Timer time-out." /> + <BitField start="1" size="1" name="REMOVE_PU" description="Remove pull-up. This bit is set by hardware to indicate that software needs to disable the D+ pull-up resistor." /> + <BitField start="2" size="1" name="HNP_FAILURE" description="HNP failed. This bit is set by hardware to indicate that the HNP switching has failed." /> + <BitField start="3" size="1" name="HNP_SUCCESS" description="HNP succeeded. This bit is set by hardware to indicate that the HNP switching has succeeded." /> + <BitField start="4" size="28" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x104" size="4" name="INTEN" access="Read/Write" description="OTG Interrupt Enable" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="TMR_EN" description="1 = enable the corresponding bit in the IntSt register." /> + <BitField start="1" size="1" name="REMOVE_PU_EN" description="1 = enable the corresponding bit in the IntSt register." /> + <BitField start="2" size="1" name="HNP_FAILURE_EN" description="1 = enable the corresponding bit in the IntSt register." /> + <BitField start="3" size="1" name="HNP_SUCCES_EN" description="1 = enable the corresponding bit in the IntSt register." /> + <BitField start="4" size="28" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x108" size="4" name="INTSET" access="WriteOnly" description="OTG Interrupt Set" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="TMR_SET" description="0 = no effect. 1 = set the corresponding bit in the IntSt register." /> + <BitField start="1" size="1" name="REMOVE_PU_SET" description="0 = no effect. 1 = set the corresponding bit in the IntSt register." /> + <BitField start="2" size="1" name="HNP_FAILURE_SET" description="0 = no effect. 1 = set the corresponding bit in the IntSt register." /> + <BitField start="3" size="1" name="HNP_SUCCES_SET" description="0 = no effect. 1 = set the corresponding bit in the IntSt register." /> + <BitField start="4" size="28" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x10C" size="4" name="INTCLR" access="WriteOnly" description="OTG Interrupt Clear" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="TMR_CLR" description="0 = no effect. 1 = clear the corresponding bit in the IntSt register." /> + <BitField start="1" size="1" name="REMOVE_PU_CLR" description="0 = no effect. 1 = clear the corresponding bit in the IntSt register." /> + <BitField start="2" size="1" name="HNP_FAILURE_CLR" description="0 = no effect. 1 = clear the corresponding bit in the IntSt register." /> + <BitField start="3" size="1" name="HNP_SUCCES_CLR" description="0 = no effect. 1 = clear the corresponding bit in the IntSt register." /> + <BitField start="4" size="28" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x110" size="4" name="STCTRL" access="Read/Write" description="OTG Status and Control and USB port select" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="PORT_FUNC" description="Controls connection of USB functions (see Figure 51). Bit 0 is set or cleared by hardware when B_HNP_TRACK or A_HNP_TRACK is set and HNP succeeds. See Section 14.9. 00: U1 = device (OTG), U2 = host 01: U1 = host (OTG), U2 = host 10: Reserved 11: U1 = host, U2 = device In a device-only configuration, the following values are allowed: 00: U1 = device. The USB device controller signals are mapped to the U1 port: USB_CONNECT1, USB_UP_LED1, USB_D+1, USB_D-1. 11: U2 = device. The USB device controller signals are mapped to the U2 port: USB_CONNECT2, USB_UP_LED2, USB_D+2, USB_D-2." /> + <BitField start="2" size="2" name="TMR_SCALE" description="Timer scale selection. This field determines the duration of each timer count. 00: 10 ms (100 KHz) 01: 100 ms (10 KHz) 10: 1000 ms (1 KHz) 11: Reserved" /> + <BitField start="4" size="1" name="TMR_MODE" description="Timer mode selection. 0: monoshot 1: free running" /> + <BitField start="5" size="1" name="TMR_EN" description="Timer enable. When set, TMR_CNT increments. When cleared, TMR_CNT is reset to 0." /> + <BitField start="6" size="1" name="TMR_RST" description="Timer reset. Writing one to this bit resets TMR_CNT to 0. This provides a single bit control for the software to restart the timer when the timer is enabled." /> + <BitField start="7" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="8" size="1" name="B_HNP_TRACK" description="Enable HNP tracking for B-device (peripheral), see Section 14.9. Hardware clears this bit when HNP_SUCCESS or HNP_FAILURE is set." /> + <BitField start="9" size="1" name="A_HNP_TRACK" description="Enable HNP tracking for A-device (host), see Section 14.9. Hardware clears this bit when HNP_SUCCESS or HNP_FAILURE is set." /> + <BitField start="10" size="1" name="PU_REMOVED" description="When the B-device changes its role from peripheral to host, software sets this bit when it removes the D+ pull-up, see Section 14.9. Hardware clears this bit when HNP_SUCCESS or HNP_FAILURE is set." /> + <BitField start="11" size="5" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="16" size="16" name="TMR_CNT" description="Current timer count value." /> + </Register> + <Register start="+0x114" size="4" name="TMR" access="Read/Write" description="OTG Timer" reset_value="0xFFFF" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="16" name="TIMEOUT_CNT" description="The TMR interrupt is set when TMR_CNT reaches this value." /> + <BitField start="16" size="16" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x200" size="4" name="DEVINTST" access="ReadOnly" description="USB Device Interrupt Status" reset_value="0x10" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="FRAME" description="The frame interrupt occurs every 1 ms. This is used in isochronous packet transfers." /> + <BitField start="1" size="1" name="EP_FAST" description="Fast endpoint interrupt. If an Endpoint Interrupt Priority register (USBEpIntPri) bit is set, the corresponding endpoint interrupt will be routed to this bit." /> + <BitField start="2" size="1" name="EP_SLOW" description="Slow endpoints interrupt. If an Endpoint Interrupt Priority Register (USBEpIntPri) bit is not set, the corresponding endpoint interrupt will be routed to this bit." /> + <BitField start="3" size="1" name="DEV_STAT" description="Set when USB Bus reset, USB suspend change or Connect change event occurs. Refer to Section 13.12.6 Set Device Status (Command: 0xFE, Data: write 1 byte) on page 366." /> + <BitField start="4" size="1" name="CCEMPTY" description="The command code register (USBCmdCode) is empty (New command can be written)." /> + <BitField start="5" size="1" name="CDFULL" description="Command data register (USBCmdData) is full (Data can be read now)." /> + <BitField start="6" size="1" name="RxENDPKT" description="The current packet in the endpoint buffer is transferred to the CPU." /> + <BitField start="7" size="1" name="TxENDPKT" description="The number of data bytes transferred to the endpoint buffer equals the number of bytes programmed in the TxPacket length register (USBTxPLen)." /> + <BitField start="8" size="1" name="EP_RLZED" description="Endpoints realized. Set when Realize Endpoint register (USBReEp) or MaxPacketSize register (USBMaxPSize) is updated and the corresponding operation is completed." /> + <BitField start="9" size="1" name="ERR_INT" description="Error Interrupt. Any bus error interrupt from the USB device. Refer to Section 13.12.9 Read Error Status (Command: 0xFB, Data: read 1 byte) on page 368" /> + <BitField start="10" size="22" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x204" size="4" name="DEVINTEN" access="Read/Write" description="USB Device Interrupt Enable" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="FRAMEEN" description="0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri." /> + <BitField start="1" size="1" name="EP_FASTEN" description="0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri." /> + <BitField start="2" size="1" name="EP_SLOWEN" description="0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri." /> + <BitField start="3" size="1" name="DEV_STATEN" description="0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri." /> + <BitField start="4" size="1" name="CCEMPTYEN" description="0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri." /> + <BitField start="5" size="1" name="CDFULLEN" description="0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri." /> + <BitField start="6" size="1" name="RxENDPKTEN" description="0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri." /> + <BitField start="7" size="1" name="TxENDPKTEN" description="0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri." /> + <BitField start="8" size="1" name="EP_RLZEDEN" description="0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri." /> + <BitField start="9" size="1" name="ERR_INTEN" description="0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri." /> + <BitField start="10" size="22" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x208" size="4" name="DEVINTCLR" access="WriteOnly" description="USB Device Interrupt Clear" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="FRAMECLR" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared." /> + <BitField start="1" size="1" name="EP_FASTCLR" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared." /> + <BitField start="2" size="1" name="EP_SLOWCLR" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared." /> + <BitField start="3" size="1" name="DEV_STATCLR" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared." /> + <BitField start="4" size="1" name="CCEMPTYCLR" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared." /> + <BitField start="5" size="1" name="CDFULLCLR" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared." /> + <BitField start="6" size="1" name="RxENDPKTCLR" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared." /> + <BitField start="7" size="1" name="TxENDPKTCLR" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared." /> + <BitField start="8" size="1" name="EP_RLZEDCLR" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared." /> + <BitField start="9" size="1" name="ERR_INTCLR" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared." /> + <BitField start="10" size="22" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x20C" size="4" name="DEVINTSET" access="WriteOnly" description="USB Device Interrupt Set" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="FRAMESET" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set." /> + <BitField start="1" size="1" name="EP_FASTSET" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set." /> + <BitField start="2" size="1" name="EP_SLOWSET" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set." /> + <BitField start="3" size="1" name="DEV_STATSET" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set." /> + <BitField start="4" size="1" name="CCEMPTYSET" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set." /> + <BitField start="5" size="1" name="CDFULLSET" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set." /> + <BitField start="6" size="1" name="RxENDPKTSET" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set." /> + <BitField start="7" size="1" name="TxENDPKTSET" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set." /> + <BitField start="8" size="1" name="EP_RLZEDSET" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set." /> + <BitField start="9" size="1" name="ERR_INTSET" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set." /> + <BitField start="10" size="22" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x210" size="4" name="CMDCODE" access="WriteOnly" description="USB Command Code" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="8" size="8" name="CMD_PHASE" description="The command phase:"> + <Enum name="READ" start="0x02" description="Read" /> + <Enum name="WRITE" start="0x01" description="Write" /> + <Enum name="COMMAND" start="0x05" description="Command" /> + </BitField> + <BitField start="16" size="8" name="CMD_CODE_WDATA" description="This is a multi-purpose field. When CMD_PHASE is Command or Read, this field contains the code for the command (CMD_CODE). When CMD_PHASE is Write, this field contains the command write data (CMD_WDATA)." /> + <BitField start="24" size="8" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x214" size="4" name="CMDDATA" access="ReadOnly" description="USB Command Data" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="CMD_RDATA" description="Command Read Data." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x218" size="4" name="RXDATA" access="ReadOnly" description="USB Receive Data" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="RX_DATA" description="Data received." /> + </Register> + <Register start="+0x21C" size="4" name="TXDATA" access="WriteOnly" description="USB Transmit Data" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="TX_DATA" description="Transmit Data." /> + </Register> + <Register start="+220" size="4" name="RXPLEN" access="ReadOnly" description="USB Receive Packet Length" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="10" name="PKT_LNGTH" description="The remaining number of bytes to be read from the currently selected endpoint's buffer. When this field decrements to 0, the RxENDPKT bit will be set in USBDevIntSt." /> + <BitField start="10" size="1" name="DV" description="Data valid. This bit is useful for isochronous endpoints. Non-isochronous endpoints do not raise an interrupt when an erroneous data packet is received. But invalid data packet can be produced with a bus reset. For isochronous endpoints, data transfer will happen even if an erroneous packet is received. In this case DV bit will not be set for the packet."> + <Enum name="DATA_IS_INVALID_" start="0" description="Data is invalid." /> + <Enum name="DATA_IS_VALID_" start="1" description="Data is valid." /> + </BitField> + <BitField start="11" size="1" name="PKT_RDY" description="The PKT_LNGTH field is valid and the packet is ready for reading." /> + <BitField start="12" size="20" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x224" size="4" name="TXPLEN" access="WriteOnly" description="USB Transmit Packet Length" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="10" name="PKT_LNGTH" description="The remaining number of bytes to be written to the selected endpoint buffer. This field is decremented by 4 by hardware after each write to USBTxData. When this field decrements to 0, the TxENDPKT bit will be set in USBDevIntSt." /> + <BitField start="10" size="22" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x228" size="4" name="CTRL" access="Read/Write" description="USB Control" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RD_EN" description="Read mode control. Enables reading data from the OUT endpoint buffer for the endpoint specified in the LOG_ENDPOINT field using the USBRxData register. This bit is cleared by hardware when the last word of the current packet is read from USBRxData."> + <Enum name="DISABLED_" start="0" description="Disabled." /> + <Enum name="ENABLED_" start="1" description="Enabled." /> + </BitField> + <BitField start="1" size="1" name="WR_EN" description="Write mode control. Enables writing data to the IN endpoint buffer for the endpoint specified in the LOG_ENDPOINT field using the USBTxData register. This bit is cleared by hardware when the number of bytes in USBTxLen have been sent."> + <Enum name="DISABLED_" start="0" description="Disabled." /> + <Enum name="ENABLED_" start="1" description="Enabled." /> + </BitField> + <BitField start="2" size="4" name="LOG_ENDPOINT" description="Logical Endpoint number." /> + <BitField start="6" size="26" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x22C" size="4" name="DEVINTPRI" access="WriteOnly" description="USB Device Interrupt Priority" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="FRAME" description="Frame interrupt routing"> + <Enum name="LP" start="0" description="FRAME interrupt is routed to USB_INT_REQ_LP." /> + <Enum name="HP" start="1" description="FRAME interrupt is routed to USB_INT_REQ_HP." /> + </BitField> + <BitField start="1" size="1" name="EP_FAST" description="Fast endpoint interrupt routing"> + <Enum name="LP" start="0" description="EP_FAST interrupt is routed to USB_INT_REQ_LP." /> + <Enum name="HP" start="1" description="EP_FAST interrupt is routed to USB_INT_REQ_HP." /> + </BitField> + <BitField start="2" size="30" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x230" size="4" name="EPINTST" access="ReadOnly" description="USB Endpoint Interrupt Status" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="EPST0" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." /> + <BitField start="1" size="1" name="EPST1" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." /> + <BitField start="2" size="1" name="EPST2" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." /> + <BitField start="3" size="1" name="EPST3" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." /> + <BitField start="4" size="1" name="EPST4" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." /> + <BitField start="5" size="1" name="EPST5" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." /> + <BitField start="6" size="1" name="EPST6" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." /> + <BitField start="7" size="1" name="EPST7" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." /> + <BitField start="8" size="1" name="EPST8" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." /> + <BitField start="9" size="1" name="EPST9" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." /> + <BitField start="10" size="1" name="EPST10" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." /> + <BitField start="11" size="1" name="EPST11" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." /> + <BitField start="12" size="1" name="EPST12" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." /> + <BitField start="13" size="1" name="EPST13" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." /> + <BitField start="14" size="1" name="EPST14" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." /> + <BitField start="15" size="1" name="EPST15" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." /> + <BitField start="16" size="1" name="EPST16" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." /> + <BitField start="17" size="1" name="EPST17" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." /> + <BitField start="18" size="1" name="EPST18" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." /> + <BitField start="19" size="1" name="EPST19" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." /> + <BitField start="20" size="1" name="EPST20" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." /> + <BitField start="21" size="1" name="EPST21" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." /> + <BitField start="22" size="1" name="EPST22" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." /> + <BitField start="23" size="1" name="EPST23" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." /> + <BitField start="24" size="1" name="EPST24" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." /> + <BitField start="25" size="1" name="EPST25" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." /> + <BitField start="26" size="1" name="EPST26" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." /> + <BitField start="27" size="1" name="EPST27" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." /> + <BitField start="28" size="1" name="EPST28" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." /> + <BitField start="29" size="1" name="EPST29" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." /> + <BitField start="30" size="1" name="EPST30" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." /> + <BitField start="31" size="1" name="EPST31" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." /> + </Register> + <Register start="+0x234" size="4" name="EPINTEN" access="Read/Write" description="USB Endpoint Interrupt Enable" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="EPEN0" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." /> + <BitField start="1" size="1" name="EPEN1" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." /> + <BitField start="2" size="1" name="EPEN2" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." /> + <BitField start="3" size="1" name="EPEN3" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." /> + <BitField start="4" size="1" name="EPEN4" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." /> + <BitField start="5" size="1" name="EPEN5" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." /> + <BitField start="6" size="1" name="EPEN6" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." /> + <BitField start="7" size="1" name="EPEN7" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." /> + <BitField start="8" size="1" name="EPEN8" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." /> + <BitField start="9" size="1" name="EPEN9" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." /> + <BitField start="10" size="1" name="EPEN10" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." /> + <BitField start="11" size="1" name="EPEN11" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." /> + <BitField start="12" size="1" name="EPEN12" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." /> + <BitField start="13" size="1" name="EPEN13" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." /> + <BitField start="14" size="1" name="EPEN14" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." /> + <BitField start="15" size="1" name="EPEN15" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." /> + <BitField start="16" size="1" name="EPEN16" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." /> + <BitField start="17" size="1" name="EPEN17" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." /> + <BitField start="18" size="1" name="EPEN18" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." /> + <BitField start="19" size="1" name="EPEN19" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." /> + <BitField start="20" size="1" name="EPEN20" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." /> + <BitField start="21" size="1" name="EPEN21" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." /> + <BitField start="22" size="1" name="EPEN22" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." /> + <BitField start="23" size="1" name="EPEN23" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." /> + <BitField start="24" size="1" name="EPEN24" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." /> + <BitField start="25" size="1" name="EPEN25" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." /> + <BitField start="26" size="1" name="EPEN26" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." /> + <BitField start="27" size="1" name="EPEN27" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." /> + <BitField start="28" size="1" name="EPEN28" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." /> + <BitField start="29" size="1" name="EPEN29" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." /> + <BitField start="30" size="1" name="EPEN30" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." /> + <BitField start="31" size="1" name="EPEN31" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." /> + </Register> + <Register start="+0x238" size="4" name="EPINTCLR" access="WriteOnly" description="USB Endpoint Interrupt Clear" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="EPCLR0" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." /> + <BitField start="1" size="1" name="EPCLR1" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." /> + <BitField start="2" size="1" name="EPCLR2" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." /> + <BitField start="3" size="1" name="EPCLR3" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." /> + <BitField start="4" size="1" name="EPCLR4" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." /> + <BitField start="5" size="1" name="EPCLR5" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." /> + <BitField start="6" size="1" name="EPCLR6" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." /> + <BitField start="7" size="1" name="EPCLR7" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." /> + <BitField start="8" size="1" name="EPCLR8" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." /> + <BitField start="9" size="1" name="EPCLR9" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." /> + <BitField start="10" size="1" name="EPCLR10" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." /> + <BitField start="11" size="1" name="EPCLR11" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." /> + <BitField start="12" size="1" name="EPCLR12" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." /> + <BitField start="13" size="1" name="EPCLR13" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." /> + <BitField start="14" size="1" name="EPCLR14" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." /> + <BitField start="15" size="1" name="EPCLR15" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." /> + <BitField start="16" size="1" name="EPCLR16" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." /> + <BitField start="17" size="1" name="EPCLR17" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." /> + <BitField start="18" size="1" name="EPCLR18" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." /> + <BitField start="19" size="1" name="EPCLR19" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." /> + <BitField start="20" size="1" name="EPCLR20" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." /> + <BitField start="21" size="1" name="EPCLR21" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." /> + <BitField start="22" size="1" name="EPCLR22" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." /> + <BitField start="23" size="1" name="EPCLR23" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." /> + <BitField start="24" size="1" name="EPCLR24" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." /> + <BitField start="25" size="1" name="EPCLR25" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." /> + <BitField start="26" size="1" name="EPCLR26" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." /> + <BitField start="27" size="1" name="EPCLR27" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." /> + <BitField start="28" size="1" name="EPCLR28" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." /> + <BitField start="29" size="1" name="EPCLR29" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." /> + <BitField start="30" size="1" name="EPCLR30" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." /> + <BitField start="31" size="1" name="EPCLR31" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." /> + </Register> + <Register start="+0x23C" size="4" name="EPINTSET" access="WriteOnly" description="USB Endpoint Interrupt Set" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="EPSET0" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." /> + <BitField start="1" size="1" name="EPSET1" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." /> + <BitField start="2" size="1" name="EPSET2" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." /> + <BitField start="3" size="1" name="EPSET3" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." /> + <BitField start="4" size="1" name="EPSET4" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." /> + <BitField start="5" size="1" name="EPSET5" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." /> + <BitField start="6" size="1" name="EPSET6" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." /> + <BitField start="7" size="1" name="EPSET7" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." /> + <BitField start="8" size="1" name="EPSET8" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." /> + <BitField start="9" size="1" name="EPSET9" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." /> + <BitField start="10" size="1" name="EPSET10" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." /> + <BitField start="11" size="1" name="EPSET11" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." /> + <BitField start="12" size="1" name="EPSET12" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." /> + <BitField start="13" size="1" name="EPSET13" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." /> + <BitField start="14" size="1" name="EPSET14" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." /> + <BitField start="15" size="1" name="EPSET15" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." /> + <BitField start="16" size="1" name="EPSET16" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." /> + <BitField start="17" size="1" name="EPSET17" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." /> + <BitField start="18" size="1" name="EPSET18" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." /> + <BitField start="19" size="1" name="EPSET19" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." /> + <BitField start="20" size="1" name="EPSET20" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." /> + <BitField start="21" size="1" name="EPSET21" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." /> + <BitField start="22" size="1" name="EPSET22" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." /> + <BitField start="23" size="1" name="EPSET23" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." /> + <BitField start="24" size="1" name="EPSET24" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." /> + <BitField start="25" size="1" name="EPSET25" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." /> + <BitField start="26" size="1" name="EPSET26" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." /> + <BitField start="27" size="1" name="EPSET27" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." /> + <BitField start="28" size="1" name="EPSET28" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." /> + <BitField start="29" size="1" name="EPSET29" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." /> + <BitField start="30" size="1" name="EPSET30" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." /> + <BitField start="31" size="1" name="EPSET31" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." /> + </Register> + <Register start="+0x240" size="4" name="EPINTPRI" access="WriteOnly" description="USB Endpoint Priority" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="EPPRI0" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" /> + <BitField start="1" size="1" name="EPPRI1" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" /> + <BitField start="2" size="1" name="EPPRI2" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" /> + <BitField start="3" size="1" name="EPPRI3" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" /> + <BitField start="4" size="1" name="EPPRI4" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" /> + <BitField start="5" size="1" name="EPPRI5" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" /> + <BitField start="6" size="1" name="EPPRI6" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" /> + <BitField start="7" size="1" name="EPPRI7" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" /> + <BitField start="8" size="1" name="EPPRI8" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" /> + <BitField start="9" size="1" name="EPPRI9" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" /> + <BitField start="10" size="1" name="EPPRI10" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" /> + <BitField start="11" size="1" name="EPPRI11" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" /> + <BitField start="12" size="1" name="EPPRI12" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" /> + <BitField start="13" size="1" name="EPPRI13" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" /> + <BitField start="14" size="1" name="EPPRI14" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" /> + <BitField start="15" size="1" name="EPPRI15" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" /> + <BitField start="16" size="1" name="EPPRI16" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" /> + <BitField start="17" size="1" name="EPPRI17" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" /> + <BitField start="18" size="1" name="EPPRI18" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" /> + <BitField start="19" size="1" name="EPPRI19" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" /> + <BitField start="20" size="1" name="EPPRI20" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" /> + <BitField start="21" size="1" name="EPPRI21" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" /> + <BitField start="22" size="1" name="EPPRI22" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" /> + <BitField start="23" size="1" name="EPPRI23" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" /> + <BitField start="24" size="1" name="EPPRI24" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" /> + <BitField start="25" size="1" name="EPPRI25" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" /> + <BitField start="26" size="1" name="EPPRI26" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" /> + <BitField start="27" size="1" name="EPPRI27" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" /> + <BitField start="28" size="1" name="EPPRI28" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" /> + <BitField start="29" size="1" name="EPPRI29" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" /> + <BitField start="30" size="1" name="EPPRI30" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" /> + <BitField start="31" size="1" name="EPPRI31" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" /> + </Register> + <Register start="+0x244" size="4" name="REEP" access="Read/Write" description="USB Realize Endpoint" reset_value="0x3" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="EPR0" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." /> + <BitField start="1" size="1" name="EPR1" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." /> + <BitField start="2" size="1" name="EPR2" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." /> + <BitField start="3" size="1" name="EPR3" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." /> + <BitField start="4" size="1" name="EPR4" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." /> + <BitField start="5" size="1" name="EPR5" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." /> + <BitField start="6" size="1" name="EPR6" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." /> + <BitField start="7" size="1" name="EPR7" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." /> + <BitField start="8" size="1" name="EPR8" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." /> + <BitField start="9" size="1" name="EPR9" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." /> + <BitField start="10" size="1" name="EPR10" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." /> + <BitField start="11" size="1" name="EPR11" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." /> + <BitField start="12" size="1" name="EPR12" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." /> + <BitField start="13" size="1" name="EPR13" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." /> + <BitField start="14" size="1" name="EPR14" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." /> + <BitField start="15" size="1" name="EPR15" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." /> + <BitField start="16" size="1" name="EPR16" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." /> + <BitField start="17" size="1" name="EPR17" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." /> + <BitField start="18" size="1" name="EPR18" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." /> + <BitField start="19" size="1" name="EPR19" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." /> + <BitField start="20" size="1" name="EPR20" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." /> + <BitField start="21" size="1" name="EPR21" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." /> + <BitField start="22" size="1" name="EPR22" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." /> + <BitField start="23" size="1" name="EPR23" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." /> + <BitField start="24" size="1" name="EPR24" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." /> + <BitField start="25" size="1" name="EPR25" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." /> + <BitField start="26" size="1" name="EPR26" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." /> + <BitField start="27" size="1" name="EPR27" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." /> + <BitField start="28" size="1" name="EPR28" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." /> + <BitField start="29" size="1" name="EPR29" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." /> + <BitField start="30" size="1" name="EPR30" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." /> + <BitField start="31" size="1" name="EPR31" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." /> + </Register> + <Register start="+0x248" size="4" name="EPIND" access="WriteOnly" description="USB Endpoint Index" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="PHY_EP" description="Physical endpoint number (0-31)" /> + <BitField start="5" size="27" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x24C" size="4" name="MAXPSIZE" access="Read/Write" description="USB MaxPacketSize" reset_value="0x8" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="10" name="MPS" description="The maximum packet size value." /> + <BitField start="10" size="22" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x250" size="4" name="DMARST" access="ReadOnly" description="USB DMA Request Status" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="EPRST0" description="Control endpoint OUT (DMA cannot be enabled for this endpoint and EP0 bit must be 0)." /> + <BitField start="1" size="1" name="EPRST1" description="Control endpoint IN (DMA cannot be enabled for this endpoint and EP1 bit must be 0)." /> + <BitField start="2" size="1" name="EPRST2" description="Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." /> + <BitField start="3" size="1" name="EPRST3" description="Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." /> + <BitField start="4" size="1" name="EPRST4" description="Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." /> + <BitField start="5" size="1" name="EPRST5" description="Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." /> + <BitField start="6" size="1" name="EPRST6" description="Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." /> + <BitField start="7" size="1" name="EPRST7" description="Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." /> + <BitField start="8" size="1" name="EPRST8" description="Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." /> + <BitField start="9" size="1" name="EPRST9" description="Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." /> + <BitField start="10" size="1" name="EPRST10" description="Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." /> + <BitField start="11" size="1" name="EPRST11" description="Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." /> + <BitField start="12" size="1" name="EPRST12" description="Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." /> + <BitField start="13" size="1" name="EPRST13" description="Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." /> + <BitField start="14" size="1" name="EPRST14" description="Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." /> + <BitField start="15" size="1" name="EPRST15" description="Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." /> + <BitField start="16" size="1" name="EPRST16" description="Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." /> + <BitField start="17" size="1" name="EPRST17" description="Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." /> + <BitField start="18" size="1" name="EPRST18" description="Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." /> + <BitField start="19" size="1" name="EPRST19" description="Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." /> + <BitField start="20" size="1" name="EPRST20" description="Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." /> + <BitField start="21" size="1" name="EPRST21" description="Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." /> + <BitField start="22" size="1" name="EPRST22" description="Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." /> + <BitField start="23" size="1" name="EPRST23" description="Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." /> + <BitField start="24" size="1" name="EPRST24" description="Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." /> + <BitField start="25" size="1" name="EPRST25" description="Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." /> + <BitField start="26" size="1" name="EPRST26" description="Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." /> + <BitField start="27" size="1" name="EPRST27" description="Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." /> + <BitField start="28" size="1" name="EPRST28" description="Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." /> + <BitField start="29" size="1" name="EPRST29" description="Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." /> + <BitField start="30" size="1" name="EPRST30" description="Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." /> + <BitField start="31" size="1" name="EPRST31" description="Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." /> + </Register> + <Register start="+0x254" size="4" name="DMARCLR" access="WriteOnly" description="USB DMA Request Clear" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="EPRCLR0" description="Control endpoint OUT (DMA cannot be enabled for this endpoint and the EP0 bit must be 0)." /> + <BitField start="1" size="1" name="EPRCLR1" description="Control endpoint IN (DMA cannot be enabled for this endpoint and the EP1 bit must be 0)." /> + <BitField start="2" size="1" name="EPRCLR2" description="Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." /> + <BitField start="3" size="1" name="EPRCLR3" description="Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." /> + <BitField start="4" size="1" name="EPRCLR4" description="Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." /> + <BitField start="5" size="1" name="EPRCLR5" description="Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." /> + <BitField start="6" size="1" name="EPRCLR6" description="Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." /> + <BitField start="7" size="1" name="EPRCLR7" description="Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." /> + <BitField start="8" size="1" name="EPRCLR8" description="Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." /> + <BitField start="9" size="1" name="EPRCLR9" description="Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." /> + <BitField start="10" size="1" name="EPRCLR10" description="Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." /> + <BitField start="11" size="1" name="EPRCLR11" description="Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." /> + <BitField start="12" size="1" name="EPRCLR12" description="Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." /> + <BitField start="13" size="1" name="EPRCLR13" description="Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." /> + <BitField start="14" size="1" name="EPRCLR14" description="Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." /> + <BitField start="15" size="1" name="EPRCLR15" description="Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." /> + <BitField start="16" size="1" name="EPRCLR16" description="Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." /> + <BitField start="17" size="1" name="EPRCLR17" description="Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." /> + <BitField start="18" size="1" name="EPRCLR18" description="Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." /> + <BitField start="19" size="1" name="EPRCLR19" description="Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." /> + <BitField start="20" size="1" name="EPRCLR20" description="Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." /> + <BitField start="21" size="1" name="EPRCLR21" description="Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." /> + <BitField start="22" size="1" name="EPRCLR22" description="Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." /> + <BitField start="23" size="1" name="EPRCLR23" description="Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." /> + <BitField start="24" size="1" name="EPRCLR24" description="Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." /> + <BitField start="25" size="1" name="EPRCLR25" description="Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." /> + <BitField start="26" size="1" name="EPRCLR26" description="Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." /> + <BitField start="27" size="1" name="EPRCLR27" description="Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." /> + <BitField start="28" size="1" name="EPRCLR28" description="Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." /> + <BitField start="29" size="1" name="EPRCLR29" description="Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." /> + <BitField start="30" size="1" name="EPRCLR30" description="Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." /> + <BitField start="31" size="1" name="EPRCLR31" description="Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." /> + </Register> + <Register start="+0x258" size="4" name="DMARSET" access="WriteOnly" description="USB DMA Request Set" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="EPRSET0" description="Control endpoint OUT (DMA cannot be enabled for this endpoint and the EP0 bit must be 0)." /> + <BitField start="1" size="1" name="EPRSET1" description="Control endpoint IN (DMA cannot be enabled for this endpoint and the EP1 bit must be 0)." /> + <BitField start="2" size="1" name="EPRSET2" description="Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." /> + <BitField start="3" size="1" name="EPRSET3" description="Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." /> + <BitField start="4" size="1" name="EPRSET4" description="Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." /> + <BitField start="5" size="1" name="EPRSET5" description="Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." /> + <BitField start="6" size="1" name="EPRSET6" description="Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." /> + <BitField start="7" size="1" name="EPRSET7" description="Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." /> + <BitField start="8" size="1" name="EPRSET8" description="Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." /> + <BitField start="9" size="1" name="EPRSET9" description="Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." /> + <BitField start="10" size="1" name="EPRSET10" description="Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." /> + <BitField start="11" size="1" name="EPRSET11" description="Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." /> + <BitField start="12" size="1" name="EPRSET12" description="Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." /> + <BitField start="13" size="1" name="EPRSET13" description="Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." /> + <BitField start="14" size="1" name="EPRSET14" description="Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." /> + <BitField start="15" size="1" name="EPRSET15" description="Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." /> + <BitField start="16" size="1" name="EPRSET16" description="Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." /> + <BitField start="17" size="1" name="EPRSET17" description="Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." /> + <BitField start="18" size="1" name="EPRSET18" description="Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." /> + <BitField start="19" size="1" name="EPRSET19" description="Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." /> + <BitField start="20" size="1" name="EPRSET20" description="Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." /> + <BitField start="21" size="1" name="EPRSET21" description="Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." /> + <BitField start="22" size="1" name="EPRSET22" description="Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." /> + <BitField start="23" size="1" name="EPRSET23" description="Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." /> + <BitField start="24" size="1" name="EPRSET24" description="Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." /> + <BitField start="25" size="1" name="EPRSET25" description="Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." /> + <BitField start="26" size="1" name="EPRSET26" description="Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." /> + <BitField start="27" size="1" name="EPRSET27" description="Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." /> + <BitField start="28" size="1" name="EPRSET28" description="Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." /> + <BitField start="29" size="1" name="EPRSET29" description="Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." /> + <BitField start="30" size="1" name="EPRSET30" description="Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." /> + <BitField start="31" size="1" name="EPRSET31" description="Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." /> + </Register> + <Register start="+0x280" size="4" name="UDCAH" access="Read/Write" description="USB UDCA Head" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="7" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written. The UDCA is aligned to 128-byte boundaries." /> + <BitField start="7" size="25" name="UDCA_ADDR" description="Start address of the UDCA." /> + </Register> + <Register start="+0x284" size="4" name="EPDMAST" access="ReadOnly" description="USB Endpoint DMA Status" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="EP_DMA_ST0" description="Control endpoint OUT (DMA cannot be enabled for this endpoint and the EP0_DMA_ENABLE bit must be 0)." /> + <BitField start="1" size="1" name="EP_DMA_ST1" description="Control endpoint IN (DMA cannot be enabled for this endpoint and the EP1_DMA_ENABLE bit must be 0)." /> + <BitField start="2" size="1" name="EP_DMA_ST2" description="Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." /> + <BitField start="3" size="1" name="EP_DMA_ST3" description="Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." /> + <BitField start="4" size="1" name="EP_DMA_ST4" description="Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." /> + <BitField start="5" size="1" name="EP_DMA_ST5" description="Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." /> + <BitField start="6" size="1" name="EP_DMA_ST6" description="Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." /> + <BitField start="7" size="1" name="EP_DMA_ST7" description="Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." /> + <BitField start="8" size="1" name="EP_DMA_ST8" description="Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." /> + <BitField start="9" size="1" name="EP_DMA_ST9" description="Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." /> + <BitField start="10" size="1" name="EP_DMA_ST10" description="Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." /> + <BitField start="11" size="1" name="EP_DMA_ST11" description="Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." /> + <BitField start="12" size="1" name="EP_DMA_ST12" description="Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." /> + <BitField start="13" size="1" name="EP_DMA_ST13" description="Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." /> + <BitField start="14" size="1" name="EP_DMA_ST14" description="Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." /> + <BitField start="15" size="1" name="EP_DMA_ST15" description="Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." /> + <BitField start="16" size="1" name="EP_DMA_ST16" description="Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." /> + <BitField start="17" size="1" name="EP_DMA_ST17" description="Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." /> + <BitField start="18" size="1" name="EP_DMA_ST18" description="Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." /> + <BitField start="19" size="1" name="EP_DMA_ST19" description="Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." /> + <BitField start="20" size="1" name="EP_DMA_ST20" description="Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." /> + <BitField start="21" size="1" name="EP_DMA_ST21" description="Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." /> + <BitField start="22" size="1" name="EP_DMA_ST22" description="Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." /> + <BitField start="23" size="1" name="EP_DMA_ST23" description="Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." /> + <BitField start="24" size="1" name="EP_DMA_ST24" description="Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." /> + <BitField start="25" size="1" name="EP_DMA_ST25" description="Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." /> + <BitField start="26" size="1" name="EP_DMA_ST26" description="Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." /> + <BitField start="27" size="1" name="EP_DMA_ST27" description="Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." /> + <BitField start="28" size="1" name="EP_DMA_ST28" description="Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." /> + <BitField start="29" size="1" name="EP_DMA_ST29" description="Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." /> + <BitField start="30" size="1" name="EP_DMA_ST30" description="Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." /> + <BitField start="31" size="1" name="EP_DMA_ST31" description="Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." /> + </Register> + <Register start="+0x288" size="4" name="EPDMAEN" access="WriteOnly" description="USB Endpoint DMA Enable" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="EP_DMA_EN0" description="Control endpoint OUT (DMA cannot be enabled for this endpoint and the EP0_DMA_ENABLE bit value must be 0)." /> + <BitField start="1" size="1" name="EP_DMA_EN1" description="Control endpoint IN (DMA cannot be enabled for this endpoint and the EP1_DMA_ENABLE bit must be 0)." /> + <BitField start="2" size="30" name="EP_DMA_EN" description="Endpoint xx(2 <= xx <= 31) DMA enable control bit. 0 = No effect. 1 = Enable the DMA operation for endpoint EPxx." /> + </Register> + <Register start="+0x28C" size="4" name="EPDMADIS" access="WriteOnly" description="USB Endpoint DMA Disable" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="EP_DMA_DIS0" description="Control endpoint OUT (DMA cannot be enabled for this endpoint and the EP0_DMA_DISABLE bit value must be 0)." /> + <BitField start="1" size="1" name="EP_DMA_DIS1" description="Control endpoint IN (DMA cannot be enabled for this endpoint and the EP1_DMA_DISABLE bit value must be 0)." /> + <BitField start="2" size="1" name="EP_DMA_DIS2" description="Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." /> + <BitField start="3" size="1" name="EP_DMA_DIS3" description="Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." /> + <BitField start="4" size="1" name="EP_DMA_DIS4" description="Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." /> + <BitField start="5" size="1" name="EP_DMA_DIS5" description="Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." /> + <BitField start="6" size="1" name="EP_DMA_DIS6" description="Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." /> + <BitField start="7" size="1" name="EP_DMA_DIS7" description="Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." /> + <BitField start="8" size="1" name="EP_DMA_DIS8" description="Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." /> + <BitField start="9" size="1" name="EP_DMA_DIS9" description="Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." /> + <BitField start="10" size="1" name="EP_DMA_DIS10" description="Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." /> + <BitField start="11" size="1" name="EP_DMA_DIS11" description="Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." /> + <BitField start="12" size="1" name="EP_DMA_DIS12" description="Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." /> + <BitField start="13" size="1" name="EP_DMA_DIS13" description="Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." /> + <BitField start="14" size="1" name="EP_DMA_DIS14" description="Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." /> + <BitField start="15" size="1" name="EP_DMA_DIS15" description="Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." /> + <BitField start="16" size="1" name="EP_DMA_DIS16" description="Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." /> + <BitField start="17" size="1" name="EP_DMA_DIS17" description="Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." /> + <BitField start="18" size="1" name="EP_DMA_DIS18" description="Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." /> + <BitField start="19" size="1" name="EP_DMA_DIS19" description="Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." /> + <BitField start="20" size="1" name="EP_DMA_DIS20" description="Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." /> + <BitField start="21" size="1" name="EP_DMA_DIS21" description="Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." /> + <BitField start="22" size="1" name="EP_DMA_DIS22" description="Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." /> + <BitField start="23" size="1" name="EP_DMA_DIS23" description="Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." /> + <BitField start="24" size="1" name="EP_DMA_DIS24" description="Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." /> + <BitField start="25" size="1" name="EP_DMA_DIS25" description="Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." /> + <BitField start="26" size="1" name="EP_DMA_DIS26" description="Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." /> + <BitField start="27" size="1" name="EP_DMA_DIS27" description="Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." /> + <BitField start="28" size="1" name="EP_DMA_DIS28" description="Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." /> + <BitField start="29" size="1" name="EP_DMA_DIS29" description="Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." /> + <BitField start="30" size="1" name="EP_DMA_DIS30" description="Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." /> + <BitField start="31" size="1" name="EP_DMA_DIS31" description="Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." /> + </Register> + <Register start="+0x290" size="4" name="DMAINTST" access="ReadOnly" description="USB DMA Interrupt Status" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="EOT" description="End of Transfer Interrupt bit."> + <Enum name="ALL_BITS_IN_THE_USBE" start="0" description="All bits in the USBEoTIntSt register are 0." /> + <Enum name="AT_LEAST_ONE_BIT_IN_" start="1" description="At least one bit in the USBEoTIntSt is set." /> + </BitField> + <BitField start="1" size="1" name="NDDR" description="New DD Request Interrupt bit."> + <Enum name="ALL_BITS_IN_THE_USBN" start="0" description="All bits in the USBNDDRIntSt register are 0." /> + <Enum name="AT_LEAST_ONE_BIT_IN_" start="1" description="At least one bit in the USBNDDRIntSt is set." /> + </BitField> + <BitField start="2" size="1" name="ERR" description="System Error Interrupt bit."> + <Enum name="ALL_BITS_IN_THE_USBS" start="0" description="All bits in the USBSysErrIntSt register are 0." /> + <Enum name="AT_LEAST_ONE_BIT_IN_" start="1" description="At least one bit in the USBSysErrIntSt is set." /> + </BitField> + <BitField start="3" size="29" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x294" size="4" name="DMAINTEN" access="Read/Write" description="USB DMA Interrupt Enable" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="EOT" description="End of Transfer Interrupt enable bit."> + <Enum name="DISABLED_" start="0" description="Disabled." /> + <Enum name="ENABLED_" start="1" description="Enabled." /> + </BitField> + <BitField start="1" size="1" name="NDDR" description="New DD Request Interrupt enable bit."> + <Enum name="DISABLED_" start="0" description="Disabled." /> + <Enum name="ENABLED_" start="1" description="Enabled." /> + </BitField> + <BitField start="2" size="1" name="ERR" description="System Error Interrupt enable bit."> + <Enum name="DISABLED_" start="0" description="Disabled." /> + <Enum name="ENABLED_" start="1" description="Enabled." /> + </BitField> + <BitField start="3" size="29" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x2A0" size="4" name="EOTINTST" access="ReadOnly" description="USB End of Transfer Interrupt Status" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="EPTXINTST0" description="Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." /> + <BitField start="1" size="1" name="EPTXINTST1" description="Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." /> + <BitField start="2" size="1" name="EPTXINTST2" description="Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." /> + <BitField start="3" size="1" name="EPTXINTST3" description="Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." /> + <BitField start="4" size="1" name="EPTXINTST4" description="Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." /> + <BitField start="5" size="1" name="EPTXINTST5" description="Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." /> + <BitField start="6" size="1" name="EPTXINTST6" description="Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." /> + <BitField start="7" size="1" name="EPTXINTST7" description="Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." /> + <BitField start="8" size="1" name="EPTXINTST8" description="Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." /> + <BitField start="9" size="1" name="EPTXINTST9" description="Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." /> + <BitField start="10" size="1" name="EPTXINTST10" description="Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." /> + <BitField start="11" size="1" name="EPTXINTST11" description="Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." /> + <BitField start="12" size="1" name="EPTXINTST12" description="Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." /> + <BitField start="13" size="1" name="EPTXINTST13" description="Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." /> + <BitField start="14" size="1" name="EPTXINTST14" description="Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." /> + <BitField start="15" size="1" name="EPTXINTST15" description="Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." /> + <BitField start="16" size="1" name="EPTXINTST16" description="Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." /> + <BitField start="17" size="1" name="EPTXINTST17" description="Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." /> + <BitField start="18" size="1" name="EPTXINTST18" description="Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." /> + <BitField start="19" size="1" name="EPTXINTST19" description="Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." /> + <BitField start="20" size="1" name="EPTXINTST20" description="Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." /> + <BitField start="21" size="1" name="EPTXINTST21" description="Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." /> + <BitField start="22" size="1" name="EPTXINTST22" description="Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." /> + <BitField start="23" size="1" name="EPTXINTST23" description="Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." /> + <BitField start="24" size="1" name="EPTXINTST24" description="Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." /> + <BitField start="25" size="1" name="EPTXINTST25" description="Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." /> + <BitField start="26" size="1" name="EPTXINTST26" description="Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." /> + <BitField start="27" size="1" name="EPTXINTST27" description="Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." /> + <BitField start="28" size="1" name="EPTXINTST28" description="Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." /> + <BitField start="29" size="1" name="EPTXINTST29" description="Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." /> + <BitField start="30" size="1" name="EPTXINTST30" description="Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." /> + <BitField start="31" size="1" name="EPTXINTST31" description="Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." /> + </Register> + <Register start="+0x2A4" size="4" name="EOTINTCLR" access="WriteOnly" description="USB End of Transfer Interrupt Clear" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="EPTXINTCLR0" description="Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." /> + <BitField start="1" size="1" name="EPTXINTCLR1" description="Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." /> + <BitField start="2" size="1" name="EPTXINTCLR2" description="Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." /> + <BitField start="3" size="1" name="EPTXINTCLR3" description="Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." /> + <BitField start="4" size="1" name="EPTXINTCLR4" description="Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." /> + <BitField start="5" size="1" name="EPTXINTCLR5" description="Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." /> + <BitField start="6" size="1" name="EPTXINTCLR6" description="Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." /> + <BitField start="7" size="1" name="EPTXINTCLR7" description="Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." /> + <BitField start="8" size="1" name="EPTXINTCLR8" description="Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." /> + <BitField start="9" size="1" name="EPTXINTCLR9" description="Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." /> + <BitField start="10" size="1" name="EPTXINTCLR10" description="Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." /> + <BitField start="11" size="1" name="EPTXINTCLR11" description="Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." /> + <BitField start="12" size="1" name="EPTXINTCLR12" description="Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." /> + <BitField start="13" size="1" name="EPTXINTCLR13" description="Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." /> + <BitField start="14" size="1" name="EPTXINTCLR14" description="Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." /> + <BitField start="15" size="1" name="EPTXINTCLR15" description="Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." /> + <BitField start="16" size="1" name="EPTXINTCLR16" description="Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." /> + <BitField start="17" size="1" name="EPTXINTCLR17" description="Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." /> + <BitField start="18" size="1" name="EPTXINTCLR18" description="Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." /> + <BitField start="19" size="1" name="EPTXINTCLR19" description="Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." /> + <BitField start="20" size="1" name="EPTXINTCLR20" description="Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." /> + <BitField start="21" size="1" name="EPTXINTCLR21" description="Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." /> + <BitField start="22" size="1" name="EPTXINTCLR22" description="Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." /> + <BitField start="23" size="1" name="EPTXINTCLR23" description="Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." /> + <BitField start="24" size="1" name="EPTXINTCLR24" description="Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." /> + <BitField start="25" size="1" name="EPTXINTCLR25" description="Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." /> + <BitField start="26" size="1" name="EPTXINTCLR26" description="Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." /> + <BitField start="27" size="1" name="EPTXINTCLR27" description="Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." /> + <BitField start="28" size="1" name="EPTXINTCLR28" description="Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." /> + <BitField start="29" size="1" name="EPTXINTCLR29" description="Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." /> + <BitField start="30" size="1" name="EPTXINTCLR30" description="Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." /> + <BitField start="31" size="1" name="EPTXINTCLR31" description="Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." /> + </Register> + <Register start="+0x2A8" size="4" name="EOTINTSET" access="WriteOnly" description="USB End of Transfer Interrupt Set" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="EPTXINTSET0" description="Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." /> + <BitField start="1" size="1" name="EPTXINTSET1" description="Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." /> + <BitField start="2" size="1" name="EPTXINTSET2" description="Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." /> + <BitField start="3" size="1" name="EPTXINTSET3" description="Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." /> + <BitField start="4" size="1" name="EPTXINTSET4" description="Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." /> + <BitField start="5" size="1" name="EPTXINTSET5" description="Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." /> + <BitField start="6" size="1" name="EPTXINTSET6" description="Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." /> + <BitField start="7" size="1" name="EPTXINTSET7" description="Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." /> + <BitField start="8" size="1" name="EPTXINTSET8" description="Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." /> + <BitField start="9" size="1" name="EPTXINTSET9" description="Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." /> + <BitField start="10" size="1" name="EPTXINTSET10" description="Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." /> + <BitField start="11" size="1" name="EPTXINTSET11" description="Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." /> + <BitField start="12" size="1" name="EPTXINTSET12" description="Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." /> + <BitField start="13" size="1" name="EPTXINTSET13" description="Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." /> + <BitField start="14" size="1" name="EPTXINTSET14" description="Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." /> + <BitField start="15" size="1" name="EPTXINTSET15" description="Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." /> + <BitField start="16" size="1" name="EPTXINTSET16" description="Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." /> + <BitField start="17" size="1" name="EPTXINTSET17" description="Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." /> + <BitField start="18" size="1" name="EPTXINTSET18" description="Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." /> + <BitField start="19" size="1" name="EPTXINTSET19" description="Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." /> + <BitField start="20" size="1" name="EPTXINTSET20" description="Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." /> + <BitField start="21" size="1" name="EPTXINTSET21" description="Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." /> + <BitField start="22" size="1" name="EPTXINTSET22" description="Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." /> + <BitField start="23" size="1" name="EPTXINTSET23" description="Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." /> + <BitField start="24" size="1" name="EPTXINTSET24" description="Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." /> + <BitField start="25" size="1" name="EPTXINTSET25" description="Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." /> + <BitField start="26" size="1" name="EPTXINTSET26" description="Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." /> + <BitField start="27" size="1" name="EPTXINTSET27" description="Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." /> + <BitField start="28" size="1" name="EPTXINTSET28" description="Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." /> + <BitField start="29" size="1" name="EPTXINTSET29" description="Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." /> + <BitField start="30" size="1" name="EPTXINTSET30" description="Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." /> + <BitField start="31" size="1" name="EPTXINTSET31" description="Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." /> + </Register> + <Register start="+0x2AC" size="4" name="NDDRINTST" access="ReadOnly" description="USB New DD Request Interrupt Status" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="EPNDDINTST0" description="Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." /> + <BitField start="1" size="1" name="EPNDDINTST1" description="Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." /> + <BitField start="2" size="1" name="EPNDDINTST2" description="Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." /> + <BitField start="3" size="1" name="EPNDDINTST3" description="Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." /> + <BitField start="4" size="1" name="EPNDDINTST4" description="Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." /> + <BitField start="5" size="1" name="EPNDDINTST5" description="Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." /> + <BitField start="6" size="1" name="EPNDDINTST6" description="Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." /> + <BitField start="7" size="1" name="EPNDDINTST7" description="Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." /> + <BitField start="8" size="1" name="EPNDDINTST8" description="Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." /> + <BitField start="9" size="1" name="EPNDDINTST9" description="Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." /> + <BitField start="10" size="1" name="EPNDDINTST10" description="Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." /> + <BitField start="11" size="1" name="EPNDDINTST11" description="Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." /> + <BitField start="12" size="1" name="EPNDDINTST12" description="Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." /> + <BitField start="13" size="1" name="EPNDDINTST13" description="Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." /> + <BitField start="14" size="1" name="EPNDDINTST14" description="Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." /> + <BitField start="15" size="1" name="EPNDDINTST15" description="Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." /> + <BitField start="16" size="1" name="EPNDDINTST16" description="Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." /> + <BitField start="17" size="1" name="EPNDDINTST17" description="Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." /> + <BitField start="18" size="1" name="EPNDDINTST18" description="Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." /> + <BitField start="19" size="1" name="EPNDDINTST19" description="Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." /> + <BitField start="20" size="1" name="EPNDDINTST20" description="Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." /> + <BitField start="21" size="1" name="EPNDDINTST21" description="Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." /> + <BitField start="22" size="1" name="EPNDDINTST22" description="Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." /> + <BitField start="23" size="1" name="EPNDDINTST23" description="Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." /> + <BitField start="24" size="1" name="EPNDDINTST24" description="Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." /> + <BitField start="25" size="1" name="EPNDDINTST25" description="Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." /> + <BitField start="26" size="1" name="EPNDDINTST26" description="Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." /> + <BitField start="27" size="1" name="EPNDDINTST27" description="Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." /> + <BitField start="28" size="1" name="EPNDDINTST28" description="Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." /> + <BitField start="29" size="1" name="EPNDDINTST29" description="Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." /> + <BitField start="30" size="1" name="EPNDDINTST30" description="Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." /> + <BitField start="31" size="1" name="EPNDDINTST31" description="Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." /> + </Register> + <Register start="+0x2B0" size="4" name="NDDRINTCLR" access="WriteOnly" description="USB New DD Request Interrupt Clear" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="EPNDDINTCLR0" description="Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." /> + <BitField start="1" size="1" name="EPNDDINTCLR1" description="Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." /> + <BitField start="2" size="1" name="EPNDDINTCLR2" description="Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." /> + <BitField start="3" size="1" name="EPNDDINTCLR3" description="Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." /> + <BitField start="4" size="1" name="EPNDDINTCLR4" description="Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." /> + <BitField start="5" size="1" name="EPNDDINTCLR5" description="Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." /> + <BitField start="6" size="1" name="EPNDDINTCLR6" description="Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." /> + <BitField start="7" size="1" name="EPNDDINTCLR7" description="Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." /> + <BitField start="8" size="1" name="EPNDDINTCLR8" description="Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." /> + <BitField start="9" size="1" name="EPNDDINTCLR9" description="Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." /> + <BitField start="10" size="1" name="EPNDDINTCLR10" description="Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." /> + <BitField start="11" size="1" name="EPNDDINTCLR11" description="Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." /> + <BitField start="12" size="1" name="EPNDDINTCLR12" description="Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." /> + <BitField start="13" size="1" name="EPNDDINTCLR13" description="Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." /> + <BitField start="14" size="1" name="EPNDDINTCLR14" description="Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." /> + <BitField start="15" size="1" name="EPNDDINTCLR15" description="Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." /> + <BitField start="16" size="1" name="EPNDDINTCLR16" description="Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." /> + <BitField start="17" size="1" name="EPNDDINTCLR17" description="Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." /> + <BitField start="18" size="1" name="EPNDDINTCLR18" description="Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." /> + <BitField start="19" size="1" name="EPNDDINTCLR19" description="Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." /> + <BitField start="20" size="1" name="EPNDDINTCLR20" description="Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." /> + <BitField start="21" size="1" name="EPNDDINTCLR21" description="Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." /> + <BitField start="22" size="1" name="EPNDDINTCLR22" description="Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." /> + <BitField start="23" size="1" name="EPNDDINTCLR23" description="Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." /> + <BitField start="24" size="1" name="EPNDDINTCLR24" description="Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." /> + <BitField start="25" size="1" name="EPNDDINTCLR25" description="Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." /> + <BitField start="26" size="1" name="EPNDDINTCLR26" description="Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." /> + <BitField start="27" size="1" name="EPNDDINTCLR27" description="Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." /> + <BitField start="28" size="1" name="EPNDDINTCLR28" description="Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." /> + <BitField start="29" size="1" name="EPNDDINTCLR29" description="Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." /> + <BitField start="30" size="1" name="EPNDDINTCLR30" description="Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." /> + <BitField start="31" size="1" name="EPNDDINTCLR31" description="Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." /> + </Register> + <Register start="+0x2B4" size="4" name="NDDRINTSET" access="WriteOnly" description="USB New DD Request Interrupt Set" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="EPNDDINTSET0" description="Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." /> + <BitField start="1" size="1" name="EPNDDINTSET1" description="Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." /> + <BitField start="2" size="1" name="EPNDDINTSET2" description="Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." /> + <BitField start="3" size="1" name="EPNDDINTSET3" description="Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." /> + <BitField start="4" size="1" name="EPNDDINTSET4" description="Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." /> + <BitField start="5" size="1" name="EPNDDINTSET5" description="Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." /> + <BitField start="6" size="1" name="EPNDDINTSET6" description="Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." /> + <BitField start="7" size="1" name="EPNDDINTSET7" description="Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." /> + <BitField start="8" size="1" name="EPNDDINTSET8" description="Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." /> + <BitField start="9" size="1" name="EPNDDINTSET9" description="Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." /> + <BitField start="10" size="1" name="EPNDDINTSET10" description="Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." /> + <BitField start="11" size="1" name="EPNDDINTSET11" description="Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." /> + <BitField start="12" size="1" name="EPNDDINTSET12" description="Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." /> + <BitField start="13" size="1" name="EPNDDINTSET13" description="Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." /> + <BitField start="14" size="1" name="EPNDDINTSET14" description="Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." /> + <BitField start="15" size="1" name="EPNDDINTSET15" description="Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." /> + <BitField start="16" size="1" name="EPNDDINTSET16" description="Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." /> + <BitField start="17" size="1" name="EPNDDINTSET17" description="Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." /> + <BitField start="18" size="1" name="EPNDDINTSET18" description="Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." /> + <BitField start="19" size="1" name="EPNDDINTSET19" description="Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." /> + <BitField start="20" size="1" name="EPNDDINTSET20" description="Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." /> + <BitField start="21" size="1" name="EPNDDINTSET21" description="Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." /> + <BitField start="22" size="1" name="EPNDDINTSET22" description="Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." /> + <BitField start="23" size="1" name="EPNDDINTSET23" description="Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." /> + <BitField start="24" size="1" name="EPNDDINTSET24" description="Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." /> + <BitField start="25" size="1" name="EPNDDINTSET25" description="Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." /> + <BitField start="26" size="1" name="EPNDDINTSET26" description="Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." /> + <BitField start="27" size="1" name="EPNDDINTSET27" description="Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." /> + <BitField start="28" size="1" name="EPNDDINTSET28" description="Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." /> + <BitField start="29" size="1" name="EPNDDINTSET29" description="Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." /> + <BitField start="30" size="1" name="EPNDDINTSET30" description="Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." /> + <BitField start="31" size="1" name="EPNDDINTSET31" description="Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." /> + </Register> + <Register start="+0x2B8" size="4" name="SYSERRINTST" access="ReadOnly" description="USB System Error Interrupt Status" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="EPERRINTST0" description="Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." /> + <BitField start="1" size="1" name="EPERRINTST1" description="Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." /> + <BitField start="2" size="1" name="EPERRINTST2" description="Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." /> + <BitField start="3" size="1" name="EPERRINTST3" description="Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." /> + <BitField start="4" size="1" name="EPERRINTST4" description="Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." /> + <BitField start="5" size="1" name="EPERRINTST5" description="Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." /> + <BitField start="6" size="1" name="EPERRINTST6" description="Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." /> + <BitField start="7" size="1" name="EPERRINTST7" description="Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." /> + <BitField start="8" size="1" name="EPERRINTST8" description="Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." /> + <BitField start="9" size="1" name="EPERRINTST9" description="Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." /> + <BitField start="10" size="1" name="EPERRINTST10" description="Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." /> + <BitField start="11" size="1" name="EPERRINTST11" description="Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." /> + <BitField start="12" size="1" name="EPERRINTST12" description="Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." /> + <BitField start="13" size="1" name="EPERRINTST13" description="Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." /> + <BitField start="14" size="1" name="EPERRINTST14" description="Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." /> + <BitField start="15" size="1" name="EPERRINTST15" description="Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." /> + <BitField start="16" size="1" name="EPERRINTST16" description="Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." /> + <BitField start="17" size="1" name="EPERRINTST17" description="Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." /> + <BitField start="18" size="1" name="EPERRINTST18" description="Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." /> + <BitField start="19" size="1" name="EPERRINTST19" description="Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." /> + <BitField start="20" size="1" name="EPERRINTST20" description="Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." /> + <BitField start="21" size="1" name="EPERRINTST21" description="Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." /> + <BitField start="22" size="1" name="EPERRINTST22" description="Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." /> + <BitField start="23" size="1" name="EPERRINTST23" description="Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." /> + <BitField start="24" size="1" name="EPERRINTST24" description="Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." /> + <BitField start="25" size="1" name="EPERRINTST25" description="Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." /> + <BitField start="26" size="1" name="EPERRINTST26" description="Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." /> + <BitField start="27" size="1" name="EPERRINTST27" description="Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." /> + <BitField start="28" size="1" name="EPERRINTST28" description="Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." /> + <BitField start="29" size="1" name="EPERRINTST29" description="Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." /> + <BitField start="30" size="1" name="EPERRINTST30" description="Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." /> + <BitField start="31" size="1" name="EPERRINTST31" description="Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." /> + </Register> + <Register start="+0x2BC" size="4" name="SYSERRINTCLR" access="WriteOnly" description="USB System Error Interrupt Clear" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="EPERRINTCLR0" description="Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." /> + <BitField start="1" size="1" name="EPERRINTCLR1" description="Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." /> + <BitField start="2" size="1" name="EPERRINTCLR2" description="Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." /> + <BitField start="3" size="1" name="EPERRINTCLR3" description="Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." /> + <BitField start="4" size="1" name="EPERRINTCLR4" description="Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." /> + <BitField start="5" size="1" name="EPERRINTCLR5" description="Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." /> + <BitField start="6" size="1" name="EPERRINTCLR6" description="Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." /> + <BitField start="7" size="1" name="EPERRINTCLR7" description="Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." /> + <BitField start="8" size="1" name="EPERRINTCLR8" description="Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." /> + <BitField start="9" size="1" name="EPERRINTCLR9" description="Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." /> + <BitField start="10" size="1" name="EPERRINTCLR10" description="Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." /> + <BitField start="11" size="1" name="EPERRINTCLR11" description="Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." /> + <BitField start="12" size="1" name="EPERRINTCLR12" description="Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." /> + <BitField start="13" size="1" name="EPERRINTCLR13" description="Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." /> + <BitField start="14" size="1" name="EPERRINTCLR14" description="Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." /> + <BitField start="15" size="1" name="EPERRINTCLR15" description="Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." /> + <BitField start="16" size="1" name="EPERRINTCLR16" description="Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." /> + <BitField start="17" size="1" name="EPERRINTCLR17" description="Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." /> + <BitField start="18" size="1" name="EPERRINTCLR18" description="Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." /> + <BitField start="19" size="1" name="EPERRINTCLR19" description="Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." /> + <BitField start="20" size="1" name="EPERRINTCLR20" description="Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." /> + <BitField start="21" size="1" name="EPERRINTCLR21" description="Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." /> + <BitField start="22" size="1" name="EPERRINTCLR22" description="Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." /> + <BitField start="23" size="1" name="EPERRINTCLR23" description="Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." /> + <BitField start="24" size="1" name="EPERRINTCLR24" description="Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." /> + <BitField start="25" size="1" name="EPERRINTCLR25" description="Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." /> + <BitField start="26" size="1" name="EPERRINTCLR26" description="Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." /> + <BitField start="27" size="1" name="EPERRINTCLR27" description="Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." /> + <BitField start="28" size="1" name="EPERRINTCLR28" description="Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." /> + <BitField start="29" size="1" name="EPERRINTCLR29" description="Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." /> + <BitField start="30" size="1" name="EPERRINTCLR30" description="Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." /> + <BitField start="31" size="1" name="EPERRINTCLR31" description="Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." /> + </Register> + <Register start="+0x2C0" size="4" name="SYSERRINTSET" access="WriteOnly" description="USB System Error Interrupt Set" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="EPERRINTSET0" description="Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." /> + <BitField start="1" size="1" name="EPERRINTSET1" description="Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." /> + <BitField start="2" size="1" name="EPERRINTSET2" description="Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." /> + <BitField start="3" size="1" name="EPERRINTSET3" description="Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." /> + <BitField start="4" size="1" name="EPERRINTSET4" description="Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." /> + <BitField start="5" size="1" name="EPERRINTSET5" description="Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." /> + <BitField start="6" size="1" name="EPERRINTSET6" description="Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." /> + <BitField start="7" size="1" name="EPERRINTSET7" description="Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." /> + <BitField start="8" size="1" name="EPERRINTSET8" description="Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." /> + <BitField start="9" size="1" name="EPERRINTSET9" description="Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." /> + <BitField start="10" size="1" name="EPERRINTSET10" description="Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." /> + <BitField start="11" size="1" name="EPERRINTSET11" description="Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." /> + <BitField start="12" size="1" name="EPERRINTSET12" description="Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." /> + <BitField start="13" size="1" name="EPERRINTSET13" description="Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." /> + <BitField start="14" size="1" name="EPERRINTSET14" description="Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." /> + <BitField start="15" size="1" name="EPERRINTSET15" description="Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." /> + <BitField start="16" size="1" name="EPERRINTSET16" description="Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." /> + <BitField start="17" size="1" name="EPERRINTSET17" description="Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." /> + <BitField start="18" size="1" name="EPERRINTSET18" description="Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." /> + <BitField start="19" size="1" name="EPERRINTSET19" description="Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." /> + <BitField start="20" size="1" name="EPERRINTSET20" description="Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." /> + <BitField start="21" size="1" name="EPERRINTSET21" description="Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." /> + <BitField start="22" size="1" name="EPERRINTSET22" description="Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." /> + <BitField start="23" size="1" name="EPERRINTSET23" description="Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." /> + <BitField start="24" size="1" name="EPERRINTSET24" description="Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." /> + <BitField start="25" size="1" name="EPERRINTSET25" description="Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." /> + <BitField start="26" size="1" name="EPERRINTSET26" description="Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." /> + <BitField start="27" size="1" name="EPERRINTSET27" description="Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." /> + <BitField start="28" size="1" name="EPERRINTSET28" description="Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." /> + <BitField start="29" size="1" name="EPERRINTSET29" description="Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." /> + <BitField start="30" size="1" name="EPERRINTSET30" description="Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." /> + <BitField start="31" size="1" name="EPERRINTSET31" description="Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." /> + </Register> + <Register start="+0x300" size="4" name="I2C_RX" access="ReadOnly" description="I2C Receive" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="8" name="RXDATA" description="Receive data." /> + </Register> + <Register start="+0x300" size="4" name="I2C_WO" access="WriteOnly" description="I2C Transmit" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="8" name="TXDATA" description="Transmit data." /> + <BitField start="8" size="1" name="START" description="When 1, issue a START condition before transmitting this byte." /> + <BitField start="9" size="1" name="STOP" description="When 1, issue a STOP condition after transmitting this byte." /> + <BitField start="10" size="22" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x304" size="4" name="I2C_STS" access="ReadOnly" description="I2C Status" reset_value="0x0A00" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="TDI" description="Transaction Done Interrupt. This flag is set if a transaction completes successfully. It is cleared by writing a one to bit 0 of the status register. It is unaffected by slave transactions."> + <Enum name="NOT_COMPLETE" start="0" description="Transaction has not completed." /> + <Enum name="COMPLETE" start="1" description="Transaction completed." /> + </BitField> + <BitField start="1" size="1" name="AFI" description="Arbitration Failure Interrupt. When transmitting, if the SDA is low when SDAOUT is high, then this I2C has lost the arbitration to another device on the bus. The Arbitration Failure bit is set when this happens. It is cleared by writing a one to bit 1 of the status register."> + <Enum name="NO_ARBITRATION_FAILU" start="0" description="No arbitration failure on last transmission." /> + <Enum name="ARBITRATION_FAILURE_" start="1" description="Arbitration failure occurred on last transmission." /> + </BitField> + <BitField start="2" size="1" name="NAI" description="No Acknowledge Interrupt. After every byte of data is sent, the transmitter expects an acknowledge from the receiver. This bit is set if the acknowledge is not received. It is cleared when a byte is written to the master TX FIFO."> + <Enum name="ACKNOWLEDGE_RCVD" start="0" description="Last transmission received an acknowledge." /> + <Enum name="NO_ACKNOWLEDGE_RCVD" start="1" description="Last transmission did not receive an acknowledge." /> + </BitField> + <BitField start="3" size="1" name="DRMI" description="Master Data Request Interrupt. Once a transmission is started, the transmitter must have data to transmit as long as it isn't followed by a stop condition or it will hold SCL low until more data is available. The Master Data Request bit is set when the master transmitter is data-starved. If the master TX FIFO is empty and the last byte did not have a STOP condition flag, then SCL is held low until the CPU writes another byte to transmit. This bit is cleared when a byte is written to the master TX FIFO."> + <Enum name="BUSY" start="0" description="Master transmitter does not need data." /> + <Enum name="NEED_DATA" start="1" description="Master transmitter needs data." /> + </BitField> + <BitField start="4" size="1" name="DRSI" description="Slave Data Request Interrupt. Once a transmission is started, the transmitter must have data to transmit as long as it isn't followed by a STOP condition or it will hold SCL low until more data is available. The Slave Data Request bit is set when the slave transmitter is data-starved. If the slave TX FIFO is empty and the last byte transmitted was acknowledged, then SCL is held low until the CPU writes another byte to transmit. This bit is cleared when a byte is written to the slave Tx FIFO."> + <Enum name="BUSY" start="0" description="Slave transmitter does not need data." /> + <Enum name="NEED_DATA" start="1" description="Slave transmitter needs data." /> + </BitField> + <BitField start="5" size="1" name="Active" description="Indicates whether the bus is busy. This bit is set when a START condition has been seen. It is cleared when a STOP condition is seen.." /> + <BitField start="6" size="1" name="SCL" description="The current value of the SCL signal." /> + <BitField start="7" size="1" name="SDA" description="The current value of the SDA signal." /> + <BitField start="8" size="1" name="RFF" description="Receive FIFO Full (RFF). This bit is set when the RX FIFO is full and cannot accept any more data. It is cleared when the RX FIFO is not full. If a byte arrives when the Receive FIFO is full, the SCL is held low until the CPU reads the RX FIFO and makes room for it."> + <Enum name="RX_FIFO_IS_NOT_FULL" start="0" description="RX FIFO is not full" /> + <Enum name="RX_FIFO_IS_FULL" start="1" description="RX FIFO is full" /> + </BitField> + <BitField start="9" size="1" name="RFE" description="Receive FIFO Empty. RFE is set when the RX FIFO is empty and is cleared when the RX FIFO contains valid data."> + <Enum name="DATA" start="0" description="RX FIFO contains data." /> + <Enum name="EMPTY" start="1" description="RX FIFO is empty" /> + </BitField> + <BitField start="10" size="1" name="TFF" description="Transmit FIFO Full. TFF is set when the TX FIFO is full and is cleared when the TX FIFO is not full."> + <Enum name="TX_FIFO_IS_NOT_FULL_" start="0" description="TX FIFO is not full." /> + <Enum name="TX_FIFO_IS_FULL" start="1" description="TX FIFO is full" /> + </BitField> + <BitField start="11" size="1" name="TFE" description="Transmit FIFO Empty. TFE is set when the TX FIFO is empty and is cleared when the TX FIFO contains valid data."> + <Enum name="VALID_DATA" start="0" description="TX FIFO contains valid data." /> + <Enum name="EMPTY" start="1" description="TX FIFO is empty" /> + </BitField> + <BitField start="12" size="20" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x308" size="4" name="I2C_CTL" access="Read/Write" description="I2C Control" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="TDIE" description="Transmit Done Interrupt Enable. This enables the TDI interrupt signalling that this I2C issued a STOP condition."> + <Enum name="DISABLE_THE_TDI_INTE" start="0" description="Disable the TDI interrupt." /> + <Enum name="ENABLE_THE_TDI_INTER" start="1" description="Enable the TDI interrupt." /> + </BitField> + <BitField start="1" size="1" name="AFIE" description="Transmitter Arbitration Failure Interrupt Enable. This enables the AFI interrupt which is asserted during transmission when trying to set SDA high, but the bus is driven low by another device."> + <Enum name="DISABLE_THE_AFI_" start="0" description="Disable the AFI." /> + <Enum name="ENABLE_THE_AFI_" start="1" description="Enable the AFI." /> + </BitField> + <BitField start="2" size="1" name="NAIE" description="Transmitter No Acknowledge Interrupt Enable. This enables the NAI interrupt signalling that transmitted byte was not acknowledged."> + <Enum name="DISABLE_THE_NAI_" start="0" description="Disable the NAI." /> + <Enum name="ENABLE_THE_NAI_" start="1" description="Enable the NAI." /> + </BitField> + <BitField start="3" size="1" name="DRMIE" description="Master Transmitter Data Request Interrupt Enable. This enables the DRMI interrupt which signals that the master transmitter has run out of data, has not issued a STOP, and is holding the SCL line low."> + <Enum name="DISABLE_THE_DRMI_INT" start="0" description="Disable the DRMI interrupt." /> + <Enum name="ENABLE_THE_DRMI_INTE" start="1" description="Enable the DRMI interrupt." /> + </BitField> + <BitField start="4" size="1" name="DRSIE" description="Slave Transmitter Data Request Interrupt Enable. This enables the DRSI interrupt which signals that the slave transmitter has run out of data and the last byte was acknowledged, so the SCL line is being held low."> + <Enum name="DISABLE_THE_DRSI_INT" start="0" description="Disable the DRSI interrupt." /> + <Enum name="ENABLE_THE_DRSI_INTE" start="1" description="Enable the DRSI interrupt." /> + </BitField> + <BitField start="5" size="1" name="REFIE" description="Receive FIFO Full Interrupt Enable. This enables the Receive FIFO Full interrupt to indicate that the receive FIFO cannot accept any more data."> + <Enum name="DISABLE_THE_RFFI_" start="0" description="Disable the RFFI." /> + <Enum name="ENABLE_THE_RFFI_" start="1" description="Enable the RFFI." /> + </BitField> + <BitField start="6" size="1" name="RFDAIE" description="Receive Data Available Interrupt Enable. This enables the DAI interrupt to indicate that data is available in the receive FIFO (i.e. not empty)."> + <Enum name="DISABLE_THE_DAI_" start="0" description="Disable the DAI." /> + <Enum name="ENABLE_THE_DAI_" start="1" description="Enable the DAI." /> + </BitField> + <BitField start="7" size="1" name="TFFIE" description="Transmit FIFO Not Full Interrupt Enable. This enables the Transmit FIFO Not Full interrupt to indicate that the more data can be written to the transmit FIFO. Note that this is not full. It is intended help the CPU to write to the I2C block only when there is room in the FIFO and do this without polling the status register."> + <Enum name="DISABLE_THE_TFFI_" start="0" description="Disable the TFFI." /> + <Enum name="ENABLE_THE_TFFI_" start="1" description="Enable the TFFI." /> + </BitField> + <BitField start="8" size="1" name="SRST" description="Soft reset. This is only needed in unusual circumstances. If a device issues a start condition without issuing a stop condition. A system timer may be used to reset the I2C if the bus remains busy longer than the time-out period. On a soft reset, the Tx and Rx FIFOs are flushed, I2C_STS register is cleared, and all internal state machines are reset to appear idle. The I2C_CLKHI, I2C_CLKLO and I2C_CTL (except Soft Reset Bit) are NOT modified by a soft reset."> + <Enum name="NO_RESET" start="0" description="No reset." /> + <Enum name="RESET" start="1" description="Reset the I2C to idle state. Self clearing." /> + </BitField> + <BitField start="9" size="23" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x30C" size="4" name="I2C_CLKHI" access="Read/Write" description="I2C Clock High" reset_value="0xB9" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="CDHI" description="Clock divisor high. This value is the number of 48 MHz clocks the serial clock (SCL) will be high." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x310" size="4" name="I2C_CLKLO" access="WriteOnly" description="I2C Clock Low" reset_value="0xB9" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="CDLO" description="Clock divisor low. This value is the number of 48 MHz clocks the serial clock (SCL) will be low." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0xFF4" size="4" name="USBCLKCTRL" access="Read/Write" description="USB Clock Control" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="1" size="1" name="DEV_CLK_EN" description="Device clock enable. Enables the usbclk input to the device controller" /> + <BitField start="2" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="3" size="1" name="PORTSEL_CLK_EN" description="Port select register clock enable." /> + <BitField start="4" size="1" name="AHB_CLK_EN" description="AHB clock enable" /> + <BitField start="5" size="27" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0xFF4" size="4" name="OTGCLKCTRL" access="Read/Write" description="OTG clock controller" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="HOST_CLK_EN" description="Host clock enable"> + <Enum name="DISABLE_THE_HOST_CLO" start="0" description="Disable the Host clock." /> + <Enum name="ENABLE_THE_HOST_CLOC" start="1" description="Enable the Host clock." /> + </BitField> + <BitField start="1" size="1" name="DEV_CLK_EN" description="Device clock enable"> + <Enum name="DISABLE_THE_DEVICE_C" start="0" description="Disable the Device clock." /> + <Enum name="ENABLE_THE_DEVICE_CL" start="1" description="Enable the Device clock." /> + </BitField> + <BitField start="2" size="1" name="I2C_CLK_EN" description="I2C clock enable"> + <Enum name="DISABLE_THE_I2C_CLOC" start="0" description="Disable the I2C clock." /> + <Enum name="ENABLE_THE_I2C_CLOCK" start="1" description="Enable the I2C clock." /> + </BitField> + <BitField start="3" size="1" name="OTG_CLK_EN" description="OTG clock enable. In device-only applications, this bit enables access to the PORTSEL register."> + <Enum name="DISABLE_THE_OTG_CLOC" start="0" description="Disable the OTG clock." /> + <Enum name="ENABLE_THE_OTG_CLOCK" start="1" description="Enable the OTG clock." /> + </BitField> + <BitField start="4" size="1" name="AHB_CLK_EN" description="AHB master clock enable"> + <Enum name="DISABLE_THE_AHB_CLOC" start="0" description="Disable the AHB clock." /> + <Enum name="ENABLE_THE_AHB_CLOCK" start="1" description="Enable the AHB clock." /> + </BitField> + <BitField start="5" size="27" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0xFF8" size="4" name="USBCLKST" access="ReadOnly" description="USB Clock Status" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="1" size="1" name="DEV_CLK_ON" description="Device clock on. The usbclk input to the device controller is active	." /> + <BitField start="2" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="3" size="1" name="PORTSEL_CLK_ON" description="Port select register clock on." /> + <BitField start="4" size="1" name="AHB_CLK_ON" description="AHB clock on." /> + <BitField start="5" size="27" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0xFF8" size="4" name="OTGCLKST" access="ReadOnly" description="OTG clock status" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="HOST_CLK_ON" description="Host clock status."> + <Enum name="HOST_CLOCK_IS_NOT_AV" start="0" description="Host clock is not available." /> + <Enum name="HOST_CLOCK_IS_AVAILA" start="1" description="Host clock is available." /> + </BitField> + <BitField start="1" size="1" name="DEV_CLK_ON" description="Device clock status."> + <Enum name="DEVICE_CLOCK_IS_NOT_" start="0" description="Device clock is not available." /> + <Enum name="DEVICE_CLOCK_IS_AVAI" start="1" description="Device clock is available." /> + </BitField> + <BitField start="2" size="1" name="I2C_CLK_ON" description="I2C clock status."> + <Enum name="I2C_CLOCK_IS_NOT_AVA" start="0" description="I2C clock is not available." /> + <Enum name="I2C_CLOCK_IS_AVAILAB" start="1" description="I2C clock is available." /> + </BitField> + <BitField start="3" size="1" name="OTG_CLK_ON" description="OTG clock status."> + <Enum name="OTG_CLOCK_IS_NOT_AVA" start="0" description="OTG clock is not available." /> + <Enum name="OTG_CLOCK_IS_AVAILAB" start="1" description="OTG clock is available." /> + </BitField> + <BitField start="4" size="1" name="AHB_CLK_ON" description="AHB master clock status."> + <Enum name="AHB_CLOCK_IS_NOT_AVA" start="0" description="AHB clock is not available." /> + <Enum name="AHB_CLOCK_IS_AVAILAB" start="1" description="AHB clock is available." /> + </BitField> + <BitField start="5" size="27" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + </RegisterGroup> + <RegisterGroup name="GPIO" start="0x2009C000" description="General Purpose I/O "> + <Register start="+0x000+0" size="4" name="DIR0" access="Read/Write" description="GPIO Port Direction control register." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="PINDIR0" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="1" size="1" name="PINDIR1" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="2" size="1" name="PINDIR2" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="3" size="1" name="PINDIR3" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="4" size="1" name="PINDIR4" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="5" size="1" name="PINDIR5" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="6" size="1" name="PINDIR6" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="7" size="1" name="PINDIR7" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="8" size="1" name="PINDIR8" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="9" size="1" name="PINDIR9" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="10" size="1" name="PINDIR10" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="11" size="1" name="PINDIR11" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="12" size="1" name="PINDIR12" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="13" size="1" name="PINDIR13" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="14" size="1" name="PINDIR14" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="15" size="1" name="PINDIR15" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="16" size="1" name="PINDIR16" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="17" size="1" name="PINDIR17" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="18" size="1" name="PINDIR18" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="19" size="1" name="PINDIR19" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="20" size="1" name="PINDIR20" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="21" size="1" name="PINDIR21" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="22" size="1" name="PINDIR22" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="23" size="1" name="PINDIR23" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="24" size="1" name="PINDIR24" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="25" size="1" name="PINDIR25" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="26" size="1" name="PINDIR26" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="27" size="1" name="PINDIR27" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="28" size="1" name="PINDIR28" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="29" size="1" name="PINDIR29" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="30" size="1" name="PINDIR30" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="31" size="1" name="PINDIR31" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + </Register> + <Register start="+0x000+32" size="4" name="DIR1" access="Read/Write" description="GPIO Port Direction control register." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="PINDIR0" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="1" size="1" name="PINDIR1" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="2" size="1" name="PINDIR2" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="3" size="1" name="PINDIR3" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="4" size="1" name="PINDIR4" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="5" size="1" name="PINDIR5" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="6" size="1" name="PINDIR6" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="7" size="1" name="PINDIR7" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="8" size="1" name="PINDIR8" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="9" size="1" name="PINDIR9" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="10" size="1" name="PINDIR10" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="11" size="1" name="PINDIR11" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="12" size="1" name="PINDIR12" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="13" size="1" name="PINDIR13" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="14" size="1" name="PINDIR14" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="15" size="1" name="PINDIR15" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="16" size="1" name="PINDIR16" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="17" size="1" name="PINDIR17" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="18" size="1" name="PINDIR18" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="19" size="1" name="PINDIR19" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="20" size="1" name="PINDIR20" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="21" size="1" name="PINDIR21" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="22" size="1" name="PINDIR22" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="23" size="1" name="PINDIR23" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="24" size="1" name="PINDIR24" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="25" size="1" name="PINDIR25" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="26" size="1" name="PINDIR26" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="27" size="1" name="PINDIR27" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="28" size="1" name="PINDIR28" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="29" size="1" name="PINDIR29" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="30" size="1" name="PINDIR30" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="31" size="1" name="PINDIR31" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + </Register> + <Register start="+0x000+64" size="4" name="DIR2" access="Read/Write" description="GPIO Port Direction control register." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="PINDIR0" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="1" size="1" name="PINDIR1" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="2" size="1" name="PINDIR2" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="3" size="1" name="PINDIR3" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="4" size="1" name="PINDIR4" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="5" size="1" name="PINDIR5" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="6" size="1" name="PINDIR6" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="7" size="1" name="PINDIR7" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="8" size="1" name="PINDIR8" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="9" size="1" name="PINDIR9" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="10" size="1" name="PINDIR10" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="11" size="1" name="PINDIR11" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="12" size="1" name="PINDIR12" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="13" size="1" name="PINDIR13" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="14" size="1" name="PINDIR14" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="15" size="1" name="PINDIR15" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="16" size="1" name="PINDIR16" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="17" size="1" name="PINDIR17" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="18" size="1" name="PINDIR18" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="19" size="1" name="PINDIR19" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="20" size="1" name="PINDIR20" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="21" size="1" name="PINDIR21" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="22" size="1" name="PINDIR22" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="23" size="1" name="PINDIR23" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="24" size="1" name="PINDIR24" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="25" size="1" name="PINDIR25" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="26" size="1" name="PINDIR26" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="27" size="1" name="PINDIR27" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="28" size="1" name="PINDIR28" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="29" size="1" name="PINDIR29" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="30" size="1" name="PINDIR30" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="31" size="1" name="PINDIR31" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + </Register> + <Register start="+0x000+96" size="4" name="DIR3" access="Read/Write" description="GPIO Port Direction control register." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="PINDIR0" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="1" size="1" name="PINDIR1" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="2" size="1" name="PINDIR2" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="3" size="1" name="PINDIR3" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="4" size="1" name="PINDIR4" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="5" size="1" name="PINDIR5" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="6" size="1" name="PINDIR6" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="7" size="1" name="PINDIR7" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="8" size="1" name="PINDIR8" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="9" size="1" name="PINDIR9" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="10" size="1" name="PINDIR10" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="11" size="1" name="PINDIR11" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="12" size="1" name="PINDIR12" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="13" size="1" name="PINDIR13" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="14" size="1" name="PINDIR14" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="15" size="1" name="PINDIR15" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="16" size="1" name="PINDIR16" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="17" size="1" name="PINDIR17" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="18" size="1" name="PINDIR18" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="19" size="1" name="PINDIR19" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="20" size="1" name="PINDIR20" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="21" size="1" name="PINDIR21" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="22" size="1" name="PINDIR22" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="23" size="1" name="PINDIR23" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="24" size="1" name="PINDIR24" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="25" size="1" name="PINDIR25" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="26" size="1" name="PINDIR26" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="27" size="1" name="PINDIR27" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="28" size="1" name="PINDIR28" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="29" size="1" name="PINDIR29" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="30" size="1" name="PINDIR30" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="31" size="1" name="PINDIR31" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + </Register> + <Register start="+0x000+128" size="4" name="DIR4" access="Read/Write" description="GPIO Port Direction control register." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="PINDIR0" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="1" size="1" name="PINDIR1" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="2" size="1" name="PINDIR2" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="3" size="1" name="PINDIR3" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="4" size="1" name="PINDIR4" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="5" size="1" name="PINDIR5" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="6" size="1" name="PINDIR6" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="7" size="1" name="PINDIR7" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="8" size="1" name="PINDIR8" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="9" size="1" name="PINDIR9" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="10" size="1" name="PINDIR10" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="11" size="1" name="PINDIR11" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="12" size="1" name="PINDIR12" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="13" size="1" name="PINDIR13" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="14" size="1" name="PINDIR14" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="15" size="1" name="PINDIR15" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="16" size="1" name="PINDIR16" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="17" size="1" name="PINDIR17" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="18" size="1" name="PINDIR18" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="19" size="1" name="PINDIR19" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="20" size="1" name="PINDIR20" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="21" size="1" name="PINDIR21" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="22" size="1" name="PINDIR22" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="23" size="1" name="PINDIR23" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="24" size="1" name="PINDIR24" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="25" size="1" name="PINDIR25" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="26" size="1" name="PINDIR26" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="27" size="1" name="PINDIR27" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="28" size="1" name="PINDIR28" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="29" size="1" name="PINDIR29" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="30" size="1" name="PINDIR30" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="31" size="1" name="PINDIR31" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + </Register> + <Register start="+0x010+0" size="4" name="MASK0" access="Read/Write" description="Mask register for Port." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="PINMASK0" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="1" size="1" name="PINMASK1" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="2" size="1" name="PINMASK2" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="3" size="1" name="PINMASK3" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="4" size="1" name="PINMASK4" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="5" size="1" name="PINMASK5" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="6" size="1" name="PINMASK6" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="7" size="1" name="PINMASK7" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="8" size="1" name="PINMASK8" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="9" size="1" name="PINMASK9" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="10" size="1" name="PINMASK10" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="11" size="1" name="PINMASK11" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="12" size="1" name="PINMASK12" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="13" size="1" name="PINMASK13" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="14" size="1" name="PINMASK14" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="15" size="1" name="PINMASK15" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="16" size="1" name="PINMASK16" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="17" size="1" name="PINMASK17" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="18" size="1" name="PINMASK18" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="19" size="1" name="PINMASK19" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="20" size="1" name="PINMASK20" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="21" size="1" name="PINMASK21" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="22" size="1" name="PINMASK22" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="23" size="1" name="PINMASK23" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="24" size="1" name="PINMASK24" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="25" size="1" name="PINMASK25" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="26" size="1" name="PINMASK26" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="27" size="1" name="PINMASK27" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="28" size="1" name="PINMASK28" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="29" size="1" name="PINMASK29" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="30" size="1" name="PINMASK30" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="31" size="1" name="PINMASK31" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + </Register> + <Register start="+0x010+32" size="4" name="MASK1" access="Read/Write" description="Mask register for Port." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="PINMASK0" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="1" size="1" name="PINMASK1" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="2" size="1" name="PINMASK2" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="3" size="1" name="PINMASK3" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="4" size="1" name="PINMASK4" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="5" size="1" name="PINMASK5" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="6" size="1" name="PINMASK6" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="7" size="1" name="PINMASK7" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="8" size="1" name="PINMASK8" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="9" size="1" name="PINMASK9" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="10" size="1" name="PINMASK10" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="11" size="1" name="PINMASK11" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="12" size="1" name="PINMASK12" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="13" size="1" name="PINMASK13" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="14" size="1" name="PINMASK14" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="15" size="1" name="PINMASK15" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="16" size="1" name="PINMASK16" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="17" size="1" name="PINMASK17" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="18" size="1" name="PINMASK18" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="19" size="1" name="PINMASK19" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="20" size="1" name="PINMASK20" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="21" size="1" name="PINMASK21" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="22" size="1" name="PINMASK22" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="23" size="1" name="PINMASK23" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="24" size="1" name="PINMASK24" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="25" size="1" name="PINMASK25" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="26" size="1" name="PINMASK26" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="27" size="1" name="PINMASK27" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="28" size="1" name="PINMASK28" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="29" size="1" name="PINMASK29" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="30" size="1" name="PINMASK30" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="31" size="1" name="PINMASK31" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + </Register> + <Register start="+0x010+64" size="4" name="MASK2" access="Read/Write" description="Mask register for Port." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="PINMASK0" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="1" size="1" name="PINMASK1" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="2" size="1" name="PINMASK2" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="3" size="1" name="PINMASK3" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="4" size="1" name="PINMASK4" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="5" size="1" name="PINMASK5" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="6" size="1" name="PINMASK6" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="7" size="1" name="PINMASK7" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="8" size="1" name="PINMASK8" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="9" size="1" name="PINMASK9" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="10" size="1" name="PINMASK10" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="11" size="1" name="PINMASK11" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="12" size="1" name="PINMASK12" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="13" size="1" name="PINMASK13" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="14" size="1" name="PINMASK14" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="15" size="1" name="PINMASK15" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="16" size="1" name="PINMASK16" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="17" size="1" name="PINMASK17" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="18" size="1" name="PINMASK18" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="19" size="1" name="PINMASK19" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="20" size="1" name="PINMASK20" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="21" size="1" name="PINMASK21" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="22" size="1" name="PINMASK22" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="23" size="1" name="PINMASK23" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="24" size="1" name="PINMASK24" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="25" size="1" name="PINMASK25" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="26" size="1" name="PINMASK26" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="27" size="1" name="PINMASK27" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="28" size="1" name="PINMASK28" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="29" size="1" name="PINMASK29" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="30" size="1" name="PINMASK30" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="31" size="1" name="PINMASK31" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + </Register> + <Register start="+0x010+96" size="4" name="MASK3" access="Read/Write" description="Mask register for Port." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="PINMASK0" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="1" size="1" name="PINMASK1" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="2" size="1" name="PINMASK2" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="3" size="1" name="PINMASK3" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="4" size="1" name="PINMASK4" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="5" size="1" name="PINMASK5" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="6" size="1" name="PINMASK6" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="7" size="1" name="PINMASK7" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="8" size="1" name="PINMASK8" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="9" size="1" name="PINMASK9" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="10" size="1" name="PINMASK10" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="11" size="1" name="PINMASK11" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="12" size="1" name="PINMASK12" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="13" size="1" name="PINMASK13" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="14" size="1" name="PINMASK14" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="15" size="1" name="PINMASK15" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="16" size="1" name="PINMASK16" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="17" size="1" name="PINMASK17" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="18" size="1" name="PINMASK18" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="19" size="1" name="PINMASK19" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="20" size="1" name="PINMASK20" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="21" size="1" name="PINMASK21" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="22" size="1" name="PINMASK22" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="23" size="1" name="PINMASK23" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="24" size="1" name="PINMASK24" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="25" size="1" name="PINMASK25" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="26" size="1" name="PINMASK26" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="27" size="1" name="PINMASK27" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="28" size="1" name="PINMASK28" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="29" size="1" name="PINMASK29" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="30" size="1" name="PINMASK30" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="31" size="1" name="PINMASK31" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + </Register> + <Register start="+0x010+128" size="4" name="MASK4" access="Read/Write" description="Mask register for Port." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="PINMASK0" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="1" size="1" name="PINMASK1" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="2" size="1" name="PINMASK2" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="3" size="1" name="PINMASK3" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="4" size="1" name="PINMASK4" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="5" size="1" name="PINMASK5" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="6" size="1" name="PINMASK6" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="7" size="1" name="PINMASK7" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="8" size="1" name="PINMASK8" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="9" size="1" name="PINMASK9" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="10" size="1" name="PINMASK10" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="11" size="1" name="PINMASK11" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="12" size="1" name="PINMASK12" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="13" size="1" name="PINMASK13" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="14" size="1" name="PINMASK14" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="15" size="1" name="PINMASK15" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="16" size="1" name="PINMASK16" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="17" size="1" name="PINMASK17" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="18" size="1" name="PINMASK18" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="19" size="1" name="PINMASK19" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="20" size="1" name="PINMASK20" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="21" size="1" name="PINMASK21" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="22" size="1" name="PINMASK22" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="23" size="1" name="PINMASK23" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="24" size="1" name="PINMASK24" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="25" size="1" name="PINMASK25" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="26" size="1" name="PINMASK26" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="27" size="1" name="PINMASK27" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="28" size="1" name="PINMASK28" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="29" size="1" name="PINMASK29" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="30" size="1" name="PINMASK30" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="31" size="1" name="PINMASK31" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + </Register> + <Register start="+0x014+0" size="4" name="PIN0" access="Read/Write" description="Port Pin value register using FIOMASK." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="PINVAL0" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="1" size="1" name="PINVAL1" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="2" size="1" name="PINVAL2" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="3" size="1" name="PINVAL3" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="4" size="1" name="PINVAL4" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="5" size="1" name="PINVAL5" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="6" size="1" name="PINVAL6" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="7" size="1" name="PINVAL7" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="8" size="1" name="PINVAL8" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="9" size="1" name="PINVAL9" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="10" size="1" name="PINVAL10" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="11" size="1" name="PINVAL11" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="12" size="1" name="PINVAL12" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="13" size="1" name="PINVAL13" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="14" size="1" name="PINVAL14" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="15" size="1" name="PINVAL15" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="16" size="1" name="PINVAL16" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="17" size="1" name="PINVAL17" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="18" size="1" name="PINVAL18" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="19" size="1" name="PINVAL19" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="20" size="1" name="PINVAL20" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="21" size="1" name="PINVAL21" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="22" size="1" name="PINVAL22" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="23" size="1" name="PINVAL23" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="24" size="1" name="PINVAL24" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="25" size="1" name="PINVAL25" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="26" size="1" name="PINVAL26" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="27" size="1" name="PINVAL27" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="28" size="1" name="PINVAL28" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="29" size="1" name="PINVAL29" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="30" size="1" name="PINVAL30" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="31" size="1" name="PINVAL31" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + </Register> + <Register start="+0x014+32" size="4" name="PIN1" access="Read/Write" description="Port Pin value register using FIOMASK." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="PINVAL0" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="1" size="1" name="PINVAL1" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="2" size="1" name="PINVAL2" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="3" size="1" name="PINVAL3" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="4" size="1" name="PINVAL4" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="5" size="1" name="PINVAL5" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="6" size="1" name="PINVAL6" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="7" size="1" name="PINVAL7" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="8" size="1" name="PINVAL8" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="9" size="1" name="PINVAL9" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="10" size="1" name="PINVAL10" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="11" size="1" name="PINVAL11" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="12" size="1" name="PINVAL12" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="13" size="1" name="PINVAL13" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="14" size="1" name="PINVAL14" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="15" size="1" name="PINVAL15" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="16" size="1" name="PINVAL16" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="17" size="1" name="PINVAL17" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="18" size="1" name="PINVAL18" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="19" size="1" name="PINVAL19" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="20" size="1" name="PINVAL20" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="21" size="1" name="PINVAL21" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="22" size="1" name="PINVAL22" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="23" size="1" name="PINVAL23" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="24" size="1" name="PINVAL24" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="25" size="1" name="PINVAL25" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="26" size="1" name="PINVAL26" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="27" size="1" name="PINVAL27" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="28" size="1" name="PINVAL28" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="29" size="1" name="PINVAL29" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="30" size="1" name="PINVAL30" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="31" size="1" name="PINVAL31" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + </Register> + <Register start="+0x014+64" size="4" name="PIN2" access="Read/Write" description="Port Pin value register using FIOMASK." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="PINVAL0" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="1" size="1" name="PINVAL1" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="2" size="1" name="PINVAL2" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="3" size="1" name="PINVAL3" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="4" size="1" name="PINVAL4" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="5" size="1" name="PINVAL5" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="6" size="1" name="PINVAL6" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="7" size="1" name="PINVAL7" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="8" size="1" name="PINVAL8" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="9" size="1" name="PINVAL9" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="10" size="1" name="PINVAL10" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="11" size="1" name="PINVAL11" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="12" size="1" name="PINVAL12" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="13" size="1" name="PINVAL13" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="14" size="1" name="PINVAL14" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="15" size="1" name="PINVAL15" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="16" size="1" name="PINVAL16" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="17" size="1" name="PINVAL17" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="18" size="1" name="PINVAL18" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="19" size="1" name="PINVAL19" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="20" size="1" name="PINVAL20" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="21" size="1" name="PINVAL21" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="22" size="1" name="PINVAL22" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="23" size="1" name="PINVAL23" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="24" size="1" name="PINVAL24" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="25" size="1" name="PINVAL25" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="26" size="1" name="PINVAL26" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="27" size="1" name="PINVAL27" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="28" size="1" name="PINVAL28" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="29" size="1" name="PINVAL29" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="30" size="1" name="PINVAL30" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="31" size="1" name="PINVAL31" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + </Register> + <Register start="+0x014+96" size="4" name="PIN3" access="Read/Write" description="Port Pin value register using FIOMASK." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="PINVAL0" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="1" size="1" name="PINVAL1" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="2" size="1" name="PINVAL2" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="3" size="1" name="PINVAL3" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="4" size="1" name="PINVAL4" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="5" size="1" name="PINVAL5" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="6" size="1" name="PINVAL6" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="7" size="1" name="PINVAL7" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="8" size="1" name="PINVAL8" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="9" size="1" name="PINVAL9" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="10" size="1" name="PINVAL10" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="11" size="1" name="PINVAL11" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="12" size="1" name="PINVAL12" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="13" size="1" name="PINVAL13" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="14" size="1" name="PINVAL14" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="15" size="1" name="PINVAL15" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="16" size="1" name="PINVAL16" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="17" size="1" name="PINVAL17" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="18" size="1" name="PINVAL18" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="19" size="1" name="PINVAL19" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="20" size="1" name="PINVAL20" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="21" size="1" name="PINVAL21" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="22" size="1" name="PINVAL22" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="23" size="1" name="PINVAL23" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="24" size="1" name="PINVAL24" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="25" size="1" name="PINVAL25" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="26" size="1" name="PINVAL26" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="27" size="1" name="PINVAL27" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="28" size="1" name="PINVAL28" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="29" size="1" name="PINVAL29" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="30" size="1" name="PINVAL30" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="31" size="1" name="PINVAL31" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + </Register> + <Register start="+0x014+128" size="4" name="PIN4" access="Read/Write" description="Port Pin value register using FIOMASK." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="PINVAL0" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="1" size="1" name="PINVAL1" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="2" size="1" name="PINVAL2" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="3" size="1" name="PINVAL3" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="4" size="1" name="PINVAL4" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="5" size="1" name="PINVAL5" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="6" size="1" name="PINVAL6" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="7" size="1" name="PINVAL7" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="8" size="1" name="PINVAL8" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="9" size="1" name="PINVAL9" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="10" size="1" name="PINVAL10" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="11" size="1" name="PINVAL11" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="12" size="1" name="PINVAL12" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="13" size="1" name="PINVAL13" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="14" size="1" name="PINVAL14" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="15" size="1" name="PINVAL15" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="16" size="1" name="PINVAL16" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="17" size="1" name="PINVAL17" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="18" size="1" name="PINVAL18" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="19" size="1" name="PINVAL19" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="20" size="1" name="PINVAL20" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="21" size="1" name="PINVAL21" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="22" size="1" name="PINVAL22" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="23" size="1" name="PINVAL23" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="24" size="1" name="PINVAL24" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="25" size="1" name="PINVAL25" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="26" size="1" name="PINVAL26" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="27" size="1" name="PINVAL27" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="28" size="1" name="PINVAL28" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="29" size="1" name="PINVAL29" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="30" size="1" name="PINVAL30" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="31" size="1" name="PINVAL31" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + </Register> + <Register start="+0x018+0" size="4" name="SET0" access="Read/Write" description="Port Output Set register using FIOMASK." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="PINSET0" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="1" size="1" name="PINSET1" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="2" size="1" name="PINSET2" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="3" size="1" name="PINSET3" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="4" size="1" name="PINSET4" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="5" size="1" name="PINSET5" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="6" size="1" name="PINSET6" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="7" size="1" name="PINSET7" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="8" size="1" name="PINSET8" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="9" size="1" name="PINSET9" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="10" size="1" name="PINSET10" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="11" size="1" name="PINSET11" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="12" size="1" name="PINSET12" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="13" size="1" name="PINSET13" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="14" size="1" name="PINSET14" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="15" size="1" name="PINSET15" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="16" size="1" name="PINSET16" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="17" size="1" name="PINSET17" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="18" size="1" name="PINSET18" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="19" size="1" name="PINSET19" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="20" size="1" name="PINSET20" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="21" size="1" name="PINSET21" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="22" size="1" name="PINSET22" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="23" size="1" name="PINSET23" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="24" size="1" name="PINSET24" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="25" size="1" name="PINSET25" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="26" size="1" name="PINSET26" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="27" size="1" name="PINSET27" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="28" size="1" name="PINSET28" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="29" size="1" name="PINSET29" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="30" size="1" name="PINSET30" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="31" size="1" name="PINSET31" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + </Register> + <Register start="+0x018+32" size="4" name="SET1" access="Read/Write" description="Port Output Set register using FIOMASK." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="PINSET0" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="1" size="1" name="PINSET1" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="2" size="1" name="PINSET2" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="3" size="1" name="PINSET3" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="4" size="1" name="PINSET4" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="5" size="1" name="PINSET5" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="6" size="1" name="PINSET6" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="7" size="1" name="PINSET7" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="8" size="1" name="PINSET8" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="9" size="1" name="PINSET9" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="10" size="1" name="PINSET10" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="11" size="1" name="PINSET11" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="12" size="1" name="PINSET12" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="13" size="1" name="PINSET13" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="14" size="1" name="PINSET14" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="15" size="1" name="PINSET15" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="16" size="1" name="PINSET16" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="17" size="1" name="PINSET17" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="18" size="1" name="PINSET18" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="19" size="1" name="PINSET19" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="20" size="1" name="PINSET20" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="21" size="1" name="PINSET21" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="22" size="1" name="PINSET22" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="23" size="1" name="PINSET23" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="24" size="1" name="PINSET24" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="25" size="1" name="PINSET25" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="26" size="1" name="PINSET26" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="27" size="1" name="PINSET27" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="28" size="1" name="PINSET28" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="29" size="1" name="PINSET29" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="30" size="1" name="PINSET30" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="31" size="1" name="PINSET31" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + </Register> + <Register start="+0x018+64" size="4" name="SET2" access="Read/Write" description="Port Output Set register using FIOMASK." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="PINSET0" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="1" size="1" name="PINSET1" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="2" size="1" name="PINSET2" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="3" size="1" name="PINSET3" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="4" size="1" name="PINSET4" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="5" size="1" name="PINSET5" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="6" size="1" name="PINSET6" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="7" size="1" name="PINSET7" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="8" size="1" name="PINSET8" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="9" size="1" name="PINSET9" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="10" size="1" name="PINSET10" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="11" size="1" name="PINSET11" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="12" size="1" name="PINSET12" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="13" size="1" name="PINSET13" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="14" size="1" name="PINSET14" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="15" size="1" name="PINSET15" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="16" size="1" name="PINSET16" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="17" size="1" name="PINSET17" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="18" size="1" name="PINSET18" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="19" size="1" name="PINSET19" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="20" size="1" name="PINSET20" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="21" size="1" name="PINSET21" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="22" size="1" name="PINSET22" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="23" size="1" name="PINSET23" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="24" size="1" name="PINSET24" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="25" size="1" name="PINSET25" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="26" size="1" name="PINSET26" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="27" size="1" name="PINSET27" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="28" size="1" name="PINSET28" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="29" size="1" name="PINSET29" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="30" size="1" name="PINSET30" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="31" size="1" name="PINSET31" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + </Register> + <Register start="+0x018+96" size="4" name="SET3" access="Read/Write" description="Port Output Set register using FIOMASK." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="PINSET0" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="1" size="1" name="PINSET1" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="2" size="1" name="PINSET2" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="3" size="1" name="PINSET3" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="4" size="1" name="PINSET4" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="5" size="1" name="PINSET5" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="6" size="1" name="PINSET6" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="7" size="1" name="PINSET7" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="8" size="1" name="PINSET8" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="9" size="1" name="PINSET9" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="10" size="1" name="PINSET10" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="11" size="1" name="PINSET11" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="12" size="1" name="PINSET12" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="13" size="1" name="PINSET13" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="14" size="1" name="PINSET14" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="15" size="1" name="PINSET15" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="16" size="1" name="PINSET16" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="17" size="1" name="PINSET17" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="18" size="1" name="PINSET18" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="19" size="1" name="PINSET19" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="20" size="1" name="PINSET20" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="21" size="1" name="PINSET21" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="22" size="1" name="PINSET22" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="23" size="1" name="PINSET23" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="24" size="1" name="PINSET24" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="25" size="1" name="PINSET25" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="26" size="1" name="PINSET26" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="27" size="1" name="PINSET27" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="28" size="1" name="PINSET28" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="29" size="1" name="PINSET29" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="30" size="1" name="PINSET30" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="31" size="1" name="PINSET31" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + </Register> + <Register start="+0x018+128" size="4" name="SET4" access="Read/Write" description="Port Output Set register using FIOMASK." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="PINSET0" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="1" size="1" name="PINSET1" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="2" size="1" name="PINSET2" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="3" size="1" name="PINSET3" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="4" size="1" name="PINSET4" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="5" size="1" name="PINSET5" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="6" size="1" name="PINSET6" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="7" size="1" name="PINSET7" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="8" size="1" name="PINSET8" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="9" size="1" name="PINSET9" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="10" size="1" name="PINSET10" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="11" size="1" name="PINSET11" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="12" size="1" name="PINSET12" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="13" size="1" name="PINSET13" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="14" size="1" name="PINSET14" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="15" size="1" name="PINSET15" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="16" size="1" name="PINSET16" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="17" size="1" name="PINSET17" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="18" size="1" name="PINSET18" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="19" size="1" name="PINSET19" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="20" size="1" name="PINSET20" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="21" size="1" name="PINSET21" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="22" size="1" name="PINSET22" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="23" size="1" name="PINSET23" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="24" size="1" name="PINSET24" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="25" size="1" name="PINSET25" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="26" size="1" name="PINSET26" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="27" size="1" name="PINSET27" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="28" size="1" name="PINSET28" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="29" size="1" name="PINSET29" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="30" size="1" name="PINSET30" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="31" size="1" name="PINSET31" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + </Register> + <Register start="+0x01C+0" size="4" name="CLR0" access="WriteOnly" description="Port Output Clear register using FIOMASK." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="PINCLR0" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="1" size="1" name="PINCLR1" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="2" size="1" name="PINCLR2" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="3" size="1" name="PINCLR3" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="4" size="1" name="PINCLR4" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="5" size="1" name="PINCLR5" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="6" size="1" name="PINCLR6" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="7" size="1" name="PINCLR7" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="8" size="1" name="PINCLR8" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="9" size="1" name="PINCLR9" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="10" size="1" name="PINCLR10" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="11" size="1" name="PINCLR11" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="12" size="1" name="PINCLR12" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="13" size="1" name="PINCLR13" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="14" size="1" name="PINCLR14" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="15" size="1" name="PINCLR15" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="16" size="1" name="PINCLR16" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="17" size="1" name="PINCLR17" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="18" size="1" name="PINCLR18" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="19" size="1" name="PINCLR19" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="20" size="1" name="PINCLR20" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="21" size="1" name="PINCLR21" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="22" size="1" name="PINCLR22" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="23" size="1" name="PINCLR23" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="24" size="1" name="PINCLR24" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="25" size="1" name="PINCLR25" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="26" size="1" name="PINCLR26" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="27" size="1" name="PINCLR27" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="28" size="1" name="PINCLR28" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="29" size="1" name="PINCLR29" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="30" size="1" name="PINCLR30" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="31" size="1" name="PINCLR31" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + </Register> + <Register start="+0x01C+32" size="4" name="CLR1" access="WriteOnly" description="Port Output Clear register using FIOMASK." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="PINCLR0" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="1" size="1" name="PINCLR1" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="2" size="1" name="PINCLR2" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="3" size="1" name="PINCLR3" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="4" size="1" name="PINCLR4" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="5" size="1" name="PINCLR5" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="6" size="1" name="PINCLR6" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="7" size="1" name="PINCLR7" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="8" size="1" name="PINCLR8" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="9" size="1" name="PINCLR9" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="10" size="1" name="PINCLR10" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="11" size="1" name="PINCLR11" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="12" size="1" name="PINCLR12" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="13" size="1" name="PINCLR13" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="14" size="1" name="PINCLR14" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="15" size="1" name="PINCLR15" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="16" size="1" name="PINCLR16" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="17" size="1" name="PINCLR17" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="18" size="1" name="PINCLR18" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="19" size="1" name="PINCLR19" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="20" size="1" name="PINCLR20" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="21" size="1" name="PINCLR21" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="22" size="1" name="PINCLR22" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="23" size="1" name="PINCLR23" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="24" size="1" name="PINCLR24" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="25" size="1" name="PINCLR25" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="26" size="1" name="PINCLR26" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="27" size="1" name="PINCLR27" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="28" size="1" name="PINCLR28" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="29" size="1" name="PINCLR29" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="30" size="1" name="PINCLR30" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="31" size="1" name="PINCLR31" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + </Register> + <Register start="+0x01C+64" size="4" name="CLR2" access="WriteOnly" description="Port Output Clear register using FIOMASK." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="PINCLR0" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="1" size="1" name="PINCLR1" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="2" size="1" name="PINCLR2" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="3" size="1" name="PINCLR3" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="4" size="1" name="PINCLR4" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="5" size="1" name="PINCLR5" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="6" size="1" name="PINCLR6" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="7" size="1" name="PINCLR7" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="8" size="1" name="PINCLR8" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="9" size="1" name="PINCLR9" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="10" size="1" name="PINCLR10" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="11" size="1" name="PINCLR11" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="12" size="1" name="PINCLR12" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="13" size="1" name="PINCLR13" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="14" size="1" name="PINCLR14" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="15" size="1" name="PINCLR15" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="16" size="1" name="PINCLR16" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="17" size="1" name="PINCLR17" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="18" size="1" name="PINCLR18" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="19" size="1" name="PINCLR19" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="20" size="1" name="PINCLR20" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="21" size="1" name="PINCLR21" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="22" size="1" name="PINCLR22" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="23" size="1" name="PINCLR23" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="24" size="1" name="PINCLR24" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="25" size="1" name="PINCLR25" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="26" size="1" name="PINCLR26" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="27" size="1" name="PINCLR27" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="28" size="1" name="PINCLR28" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="29" size="1" name="PINCLR29" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="30" size="1" name="PINCLR30" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="31" size="1" name="PINCLR31" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + </Register> + <Register start="+0x01C+96" size="4" name="CLR3" access="WriteOnly" description="Port Output Clear register using FIOMASK." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="PINCLR0" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="1" size="1" name="PINCLR1" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="2" size="1" name="PINCLR2" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="3" size="1" name="PINCLR3" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="4" size="1" name="PINCLR4" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="5" size="1" name="PINCLR5" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="6" size="1" name="PINCLR6" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="7" size="1" name="PINCLR7" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="8" size="1" name="PINCLR8" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="9" size="1" name="PINCLR9" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="10" size="1" name="PINCLR10" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="11" size="1" name="PINCLR11" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="12" size="1" name="PINCLR12" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="13" size="1" name="PINCLR13" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="14" size="1" name="PINCLR14" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="15" size="1" name="PINCLR15" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="16" size="1" name="PINCLR16" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="17" size="1" name="PINCLR17" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="18" size="1" name="PINCLR18" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="19" size="1" name="PINCLR19" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="20" size="1" name="PINCLR20" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="21" size="1" name="PINCLR21" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="22" size="1" name="PINCLR22" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="23" size="1" name="PINCLR23" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="24" size="1" name="PINCLR24" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="25" size="1" name="PINCLR25" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="26" size="1" name="PINCLR26" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="27" size="1" name="PINCLR27" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="28" size="1" name="PINCLR28" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="29" size="1" name="PINCLR29" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="30" size="1" name="PINCLR30" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="31" size="1" name="PINCLR31" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + </Register> + <Register start="+0x01C+128" size="4" name="CLR4" access="WriteOnly" description="Port Output Clear register using FIOMASK." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="PINCLR0" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="1" size="1" name="PINCLR1" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="2" size="1" name="PINCLR2" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="3" size="1" name="PINCLR3" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="4" size="1" name="PINCLR4" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="5" size="1" name="PINCLR5" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="6" size="1" name="PINCLR6" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="7" size="1" name="PINCLR7" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="8" size="1" name="PINCLR8" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="9" size="1" name="PINCLR9" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="10" size="1" name="PINCLR10" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="11" size="1" name="PINCLR11" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="12" size="1" name="PINCLR12" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="13" size="1" name="PINCLR13" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="14" size="1" name="PINCLR14" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="15" size="1" name="PINCLR15" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="16" size="1" name="PINCLR16" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="17" size="1" name="PINCLR17" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="18" size="1" name="PINCLR18" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="19" size="1" name="PINCLR19" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="20" size="1" name="PINCLR20" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="21" size="1" name="PINCLR21" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="22" size="1" name="PINCLR22" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="23" size="1" name="PINCLR23" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="24" size="1" name="PINCLR24" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="25" size="1" name="PINCLR25" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="26" size="1" name="PINCLR26" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="27" size="1" name="PINCLR27" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="28" size="1" name="PINCLR28" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="29" size="1" name="PINCLR29" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="30" size="1" name="PINCLR30" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="31" size="1" name="PINCLR31" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + </Register> + </RegisterGroup> + <RegisterGroup name="NVIC" start="0xE000E100" description="Nested Vectored Interrupt Controller"> + <Register name="NVIC_ISER0" description="Interrupt Set-Enable Register 0" start="0xE000E100"> + <BitField name="WDT" start="0" size="1" /> + <BitField name="TIMER0" start="1" size="1" /> + <BitField name="TIMER1" start="2" size="1" /> + <BitField name="TIMER2" start="3" size="1" /> + <BitField name="TIMER3" start="4" size="1" /> + <BitField name="UART0" start="5" size="1" /> + <BitField name="UART1" start="6" size="1" /> + <BitField name="UART2" start="7" size="1" /> + <BitField name="UART3" start="8" size="1" /> + <BitField name="PWM1" start="9" size="1" /> + <BitField name="I2C0" start="10" size="1" /> + <BitField name="I2C1" start="11" size="1" /> + <BitField name="I2C2" start="12" size="1" /> + <BitField name="SPI" start="13" size="1" /> + <BitField name="SSP0" start="14" size="1" /> + <BitField name="SSP1" start="15" size="1" /> + <BitField name="PLL0" start="16" size="1" /> + <BitField name="RTC" start="17" size="1" /> + <BitField name="EINT0" start="18" size="1" /> + <BitField name="EINT1" start="19" size="1" /> + <BitField name="EINT2" start="20" size="1" /> + <BitField name="EINT3" start="21" size="1" /> + <BitField name="ADC" start="22" size="1" /> + <BitField name="BOD" start="23" size="1" /> + <BitField name="USB" start="24" size="1" /> + <BitField name="CAN" start="25" size="1" /> + <BitField name="DMA" start="26" size="1" /> + <BitField name="I2S" start="27" size="1" /> + <BitField name="ENET" start="28" size="1" /> + <BitField name="RIT" start="29" size="1" /> + <BitField name="MCPWM" start="30" size="1" /> + <BitField name="QEI" start="31" size="1" /> + </Register> + <Register name="NVIC_ISER1" description="Interrupt Set-Enable Register 1" start="0xE000E104"> + <BitField name="PLL1" start="0" size="1" /> + <BitField name="USBActivity" start="1" size="1" /> + <BitField name="CANActivity" start="2" size="1" /> + </Register> + <Register name="NVIC_ICER0" description="Interrupt Clear-Enable Register 0" start="0xE000E180"> + <BitField name="WDT" start="0" size="1" /> + <BitField name="TIMER0" start="1" size="1" /> + <BitField name="TIMER1" start="2" size="1" /> + <BitField name="TIMER2" start="3" size="1" /> + <BitField name="TIMER3" start="4" size="1" /> + <BitField name="UART0" start="5" size="1" /> + <BitField name="UART1" start="6" size="1" /> + <BitField name="UART2" start="7" size="1" /> + <BitField name="UART3" start="8" size="1" /> + <BitField name="PWM1" start="9" size="1" /> + <BitField name="I2C0" start="10" size="1" /> + <BitField name="I2C1" start="11" size="1" /> + <BitField name="I2C2" start="12" size="1" /> + <BitField name="SPI" start="13" size="1" /> + <BitField name="SSP0" start="14" size="1" /> + <BitField name="SSP1" start="15" size="1" /> + <BitField name="PLL0" start="16" size="1" /> + <BitField name="RTC" start="17" size="1" /> + <BitField name="EINT0" start="18" size="1" /> + <BitField name="EINT1" start="19" size="1" /> + <BitField name="EINT2" start="20" size="1" /> + <BitField name="EINT3" start="21" size="1" /> + <BitField name="ADC" start="22" size="1" /> + <BitField name="BOD" start="23" size="1" /> + <BitField name="USB" start="24" size="1" /> + <BitField name="CAN" start="25" size="1" /> + <BitField name="DMA" start="26" size="1" /> + <BitField name="I2S" start="27" size="1" /> + <BitField name="ENET" start="28" size="1" /> + <BitField name="RIT" start="29" size="1" /> + <BitField name="MCPWM" start="30" size="1" /> + <BitField name="QEI" start="31" size="1" /> + </Register> + <Register name="NVIC_ICER1" description="Interrupt Clear-Enable Register 1" start="0xE000E184"> + <BitField name="PLL1" start="0" size="1" /> + <BitField name="USBActivity" start="1" size="1" /> + <BitField name="CANActivity" start="2" size="1" /> + </Register> + <Register name="NVIC_ISPR0" description="Interrupt Set-Pending Register 0" start="0xE000E200"> + <BitField name="WDT" start="0" size="1" /> + <BitField name="TIMER0" start="1" size="1" /> + <BitField name="TIMER1" start="2" size="1" /> + <BitField name="TIMER2" start="3" size="1" /> + <BitField name="TIMER3" start="4" size="1" /> + <BitField name="UART0" start="5" size="1" /> + <BitField name="UART1" start="6" size="1" /> + <BitField name="UART2" start="7" size="1" /> + <BitField name="UART3" start="8" size="1" /> + <BitField name="PWM1" start="9" size="1" /> + <BitField name="I2C0" start="10" size="1" /> + <BitField name="I2C1" start="11" size="1" /> + <BitField name="I2C2" start="12" size="1" /> + <BitField name="SPI" start="13" size="1" /> + <BitField name="SSP0" start="14" size="1" /> + <BitField name="SSP1" start="15" size="1" /> + <BitField name="PLL0" start="16" size="1" /> + <BitField name="RTC" start="17" size="1" /> + <BitField name="EINT0" start="18" size="1" /> + <BitField name="EINT1" start="19" size="1" /> + <BitField name="EINT2" start="20" size="1" /> + <BitField name="EINT3" start="21" size="1" /> + <BitField name="ADC" start="22" size="1" /> + <BitField name="BOD" start="23" size="1" /> + <BitField name="USB" start="24" size="1" /> + <BitField name="CAN" start="25" size="1" /> + <BitField name="DMA" start="26" size="1" /> + <BitField name="I2S" start="27" size="1" /> + <BitField name="ENET" start="28" size="1" /> + <BitField name="RIT" start="29" size="1" /> + <BitField name="MCPWM" start="30" size="1" /> + <BitField name="QEI" start="31" size="1" /> + </Register> + <Register name="NVIC_ISPR1" description="Interrupt Set-Pending Register 1" start="0xE000E204"> + <BitField name="PLL1" start="0" size="1" /> + <BitField name="USBActivity" start="1" size="1" /> + <BitField name="CANActivity" start="2" size="1" /> + </Register> + <Register name="NVIC_ICPR0" description="Interrupt Clear-Pending Register 0" start="0xE000E280"> + <BitField name="WDT" start="0" size="1" /> + <BitField name="TIMER0" start="1" size="1" /> + <BitField name="TIMER1" start="2" size="1" /> + <BitField name="TIMER2" start="3" size="1" /> + <BitField name="TIMER3" start="4" size="1" /> + <BitField name="UART0" start="5" size="1" /> + <BitField name="UART1" start="6" size="1" /> + <BitField name="UART2" start="7" size="1" /> + <BitField name="UART3" start="8" size="1" /> + <BitField name="PWM1" start="9" size="1" /> + <BitField name="I2C0" start="10" size="1" /> + <BitField name="I2C1" start="11" size="1" /> + <BitField name="I2C2" start="12" size="1" /> + <BitField name="SPI" start="13" size="1" /> + <BitField name="SSP0" start="14" size="1" /> + <BitField name="SSP1" start="15" size="1" /> + <BitField name="PLL0" start="16" size="1" /> + <BitField name="RTC" start="17" size="1" /> + <BitField name="EINT0" start="18" size="1" /> + <BitField name="EINT1" start="19" size="1" /> + <BitField name="EINT2" start="20" size="1" /> + <BitField name="EINT3" start="21" size="1" /> + <BitField name="ADC" start="22" size="1" /> + <BitField name="BOD" start="23" size="1" /> + <BitField name="USB" start="24" size="1" /> + <BitField name="CAN" start="25" size="1" /> + <BitField name="DMA" start="26" size="1" /> + <BitField name="I2S" start="27" size="1" /> + <BitField name="ENET" start="28" size="1" /> + <BitField name="RIT" start="29" size="1" /> + <BitField name="MCPWM" start="30" size="1" /> + <BitField name="QEI" start="31" size="1" /> + </Register> + <Register name="NVIC_ICPR1" description="Interrupt Clear-Pending Register 1" start="0xE000E284"> + <BitField name="PLL1" start="0" size="1" /> + <BitField name="USBActivity" start="1" size="1" /> + <BitField name="CANActivity" start="2" size="1" /> + </Register> + <Register name="NVIC_IABR0" description="Interrupt Active Bit Register 0" start="0xE000E300" access="ReadOnly"> + <BitField name="WDT" start="0" size="1" /> + <BitField name="TIMER0" start="1" size="1" /> + <BitField name="TIMER1" start="2" size="1" /> + <BitField name="TIMER2" start="3" size="1" /> + <BitField name="TIMER3" start="4" size="1" /> + <BitField name="UART0" start="5" size="1" /> + <BitField name="UART1" start="6" size="1" /> + <BitField name="UART2" start="7" size="1" /> + <BitField name="UART3" start="8" size="1" /> + <BitField name="PWM1" start="9" size="1" /> + <BitField name="I2C0" start="10" size="1" /> + <BitField name="I2C1" start="11" size="1" /> + <BitField name="I2C2" start="12" size="1" /> + <BitField name="SPI" start="13" size="1" /> + <BitField name="SSP0" start="14" size="1" /> + <BitField name="SSP1" start="15" size="1" /> + <BitField name="PLL0" start="16" size="1" /> + <BitField name="RTC" start="17" size="1" /> + <BitField name="EINT0" start="18" size="1" /> + <BitField name="EINT1" start="19" size="1" /> + <BitField name="EINT2" start="20" size="1" /> + <BitField name="EINT3" start="21" size="1" /> + <BitField name="ADC" start="22" size="1" /> + <BitField name="BOD" start="23" size="1" /> + <BitField name="USB" start="24" size="1" /> + <BitField name="CAN" start="25" size="1" /> + <BitField name="DMA" start="26" size="1" /> + <BitField name="I2S" start="27" size="1" /> + <BitField name="ENET" start="28" size="1" /> + <BitField name="RIT" start="29" size="1" /> + <BitField name="MCPWM" start="30" size="1" /> + <BitField name="QEI" start="31" size="1" /> + </Register> + <Register name="NVIC_IABR1" description="Interrupt Active Bit Register 1" start="0xE000E304" access="ReadOnly"> + <BitField name="PLL1" start="0" size="1" /> + <BitField name="USBActivity" start="1" size="1" /> + <BitField name="CANActivity" start="2" size="1" /> + </Register> + <Register name="NVIC_IPR0" description="Interrupt Priority Register 0" start="0xE000E400"> + <BitField name="WDT" start="4" size="4" /> + <BitField name="TIMER0" start="12" size="4" /> + <BitField name="TIMER1" start="20" size="4" /> + <BitField name="TIMER2" start="28" size="4" /> + </Register> + <Register name="NVIC_IPR1" description="Interrupt Priority Register 1" start="0xE000E404"> + <BitField name="TIMER3" start="4" size="4" /> + <BitField name="UART0" start="12" size="4" /> + <BitField name="UART1" start="20" size="4" /> + <BitField name="UART2" start="28" size="4" /> + </Register> + <Register name="NVIC_IPR2" description="Interrupt Priority Register 2" start="0xE000E408"> + <BitField name="UART3" start="4" size="4" /> + <BitField name="PWM1" start="12" size="4" /> + <BitField name="I2C0" start="20" size="4" /> + <BitField name="I2C1" start="28" size="4" /> + </Register> + <Register name="NVIC_IPR3" description="Interrupt Priority Register 3" start="0xE000E40C"> + <BitField name="I2C2" start="4" size="4" /> + <BitField name="SPI" start="12" size="4" /> + <BitField name="SSP0" start="20" size="4" /> + <BitField name="SSP1" start="28" size="4" /> + </Register> + <Register name="NVIC_IPR4" description="Interrupt Priority Register 4" start="0xE000E410"> + <BitField name="PLL0" start="4" size="4" /> + <BitField name="RTC" start="12" size="4" /> + <BitField name="EINT0" start="20" size="4" /> + <BitField name="EINT1" start="28" size="4" /> + </Register> + <Register name="NVIC_IPR5" description="Interrupt Priority Register 5" start="0xE000E414"> + <BitField name="EINT2" start="4" size="4" /> + <BitField name="EINT3" start="12" size="4" /> + <BitField name="ADC" start="20" size="4" /> + <BitField name="BOD" start="28" size="4" /> + </Register> + <Register name="NVIC_IPR6" description="Interrupt Priority Register 6" start="0xE000E418"> + <BitField name="USB" start="4" size="4" /> + <BitField name="CAN" start="12" size="4" /> + <BitField name="DMA" start="20" size="4" /> + <BitField name="I2S" start="28" size="4" /> + </Register> + <Register name="NVIC_IPR7" description="Interrupt Priority Register 7" start="0xE000E41C"> + <BitField name="ENET" start="4" size="4" /> + <BitField name="RIT" start="12" size="4" /> + <BitField name="MCPWM" start="20" size="4" /> + <BitField name="QEI" start="28" size="4" /> + </Register> + <Register name="NVIC_IPR8" description="Interrupt Priority Register 8" start="0xE000E420"> + <BitField name="PLL1" start="4" size="4" /> + <BitField name="USBActivity" start="12" size="4" /> + <BitField name="CANActivity" start="20" size="4" /> + </Register> + </RegisterGroup> + <RegisterGroup name="SysTick" start="0xE000E010" description="24-bit System Timer"> + <Register name="SYS_CSR" start="0xE000E010" description="SysTick Control and Status Register"> + <BitField name="COUNTFLAG" start="16" size="1" description="Counter Flag" /> + <BitField name="CLKSOURCE" start="2" size="1" description="Timer Clock Source" /> + <BitField name="TICKINT" start="1" size="1" description="Tick Interrupt Enable" /> + <BitField name="ENABLE" start="0" size="1" description="Enable SysTick Timer" /> + </Register> + <Register name="SYS_RVR" start="0xE000E014" description="SysTick Reload Value Register"> + <BitField name="RELOAD" start="0" size="24" description="Value to load into the SYST_CVR when the counter is enabled and when it reaches 0" /> + </Register> + <Register name="SYS_CVR" start="0xE000E018" description="SysTick Current Value Register Register"> + <BitField name="CURRENT" start="0" size="24" description="The current value of the SysTick counter" /> + </Register> + <Register name="SYS_CALIB" start="0xE000E01C" access="ReadOnly" description="SysTick Calibration Value Register"> + <BitField name="NOREF" start="31" size="1" description="Indicates whether the device provides a reference clock to the processor" /> + <BitField name="SKEW" start="30" size="1" description="Indicates whether the TENMS value is exact" /> + <BitField name="TENMS" start="0" size="24" description="Reload value for 10ms (100Hz) timing, subject to system clock skew errors" /> + </Register> + </RegisterGroup> + <RegisterGroup name="SCB" start="" description="System Control Block"> + <Register name="ACTLR" start="0xE000E008" description="Auxiliary Control Register"> + <BitField name="DISDEFWBUF" start="1" size="1" description="When set to 1, disables write buffer use during default memory map accesses" /> + <BitField name="DISMCYCINT" start="0" size="1" description="When set to 1, disables interruption of load multiple and store multiple instructions" /> + </Register> + <Register name="CPUID" start="0xE000ED00" access="ReadOnly" description="CPUID Register"> + <BitField name="IMPLEMENTER" start="24" size="8" description="Implementer Code" /> + <BitField name="VARIANT" start="20" size="4" description="Variant Number" /> + <BitField name="PARTNO" start="4" size="12" description="Part Number" /> + <BitField name="REVISION" start="0" size="4" description="Revision Number" /> + </Register> + <Register name="ICSR" start="0xE000ED04" description="Interrupt Control and State Register"> + <BitField name="NMIPENDSET" start="31" size="1" description="NMI set-pending bit" /> + <BitField name="PENDSVSET" start="28" size="1" description="PendSV set-pending bit" /> + <BitField name="PENDSVCLR" start="27" size="1" description="PendSV clear-pending bit" /> + <BitField name="PENDSTSET" start="26" size="1" description="SysTick exception set-pending bit" /> + <BitField name="PENDSTCLR" start="25" size="1" description="SysTick exception clear-pending bit" /> + <BitField name="ISRPREEMPT" start="23" size="1" description="" /> + <BitField name="ISRPENDING" start="22" size="1" description="Interrupt pending flag" /> + <BitField name="VECTPENDING" start="12" size="9" description="Indicates the exception number of the highest priority pending enabled exception" /> + <BitField name="RETTOBASE" start="11" size="1" description="Indicates whether there are preempted active exceptions" /> + <BitField name="VECTACTIVE" start="0" size="9" description="Contains the active exception number" /> + </Register> + <Register name="VTOR" start="0xE000ED08" description="Vector Table Offset Register"> + <BitField name="TBLOFF" start="7" size="25" description="Vector table base offset field" /> + </Register> + <Register name="AIRCR" start="0xE000ED0C" description="Application Interrupt and Reset Control Register"> + <BitField name="VECTKEY" start="16" size="16" description="Register key" /> + <BitField name="ENDIANESS" start="15" size="1" description="Data endianness bit" /> + <BitField name="PRIGROUP" start="8" size="3" description="Interrupt priority grouping field" /> + <BitField name="SYSRESETREQ" start="2" size="1" description="System reset request bit" /> + <BitField name="VECTCLRACTIVE" start="1" size="1" description="" /> + <BitField name="VECTRESET" start="0" size="1" description="" /> + </Register> + <Register name="SCR" start="0xE000ED10" description="System Control Register"> + <BitField name="SEVONPEND" start="4" size="1" description="Send event on pending bit" /> + <BitField name="SLEEPDEEP" start="2" size="1" description="Controls whether the processor uses sleep or deep sleep as its low power mode" /> + <BitField name="SLEEPONEXIT" start="1" size="1" description="Indicates sleep-on-exit when returning from Handler mode to Thread mode" /> + </Register> + <Register name="CCR" start="0xE000ED14" access="ReadOnly" description="Configuration and Control Register"> + <BitField name="STKALIGN" start="9" size="1" description="Indicates stack alignment on exception entry" /> + <BitField name="BFHFNMIGN" start="8" size="1" description="Enables handlers with priority -1 or-2 to ignore data BusFaults caused by load and store instructions" /> + <BitField name="DIV_0_TRP" start="4" size="1" description="Enables faulting or halting when the processor executes an SDIVor UDIV instruction with a divisor of 0" /> + <BitField name="UNALIGN_TRP" start="3" size="1" description="Enables unaligned access traps" /> + <BitField name="USERSETMPEND" start="1" size="1" description="Enables unprivileged software access to the STIR" /> + <BitField name="NONBASETHRDENA" start="0" size="1" description="Indicates how the processor enters Thread mode" /> + </Register> + <Register name="SHPR1" start="0xE000ED18" description="System Handler Priority Register 1"> + <BitField name="PRI_6" start="20" size="4" description="Priority of system handler 6 (UsageFault)" /> + <BitField name="PRI_5" start="12" size="4" description="Priority of system handler 5 (BusFault)" /> + <BitField name="PRI_4" start="4" size="4" description="Priority of system handler 4 (MemManage)" /> + </Register> + <Register name="SHPR2" start="0xE000ED1C" description="System Handler Priority Register 2"> + <BitField name="PRI_11" start="28" size="4" description="Priority of system handler 11 (SVCall)" /> + </Register> + <Register name="SHPR3" start="0xE000ED20" description="System Handler Priority Register 3"> + <BitField name="PRI_15" start="28" size="4" description="Priority of system handler 15 (SysTick)" /> + <BitField name="PRI_14" start="20" size="4" description="Priority of system handler 14 (PendSV)" /> + </Register> + <Register name="SHCSR" start="0xE000ED24" description="System Handler Control and State Register"> + <BitField name="USGFAULTENA" start="18" size="1" description="UsageFault enable Bit" /> + <BitField name="BUSFAULTENA" start="17" size="1" description="BusFault Enable Bit" /> + <BitField name="MEMFAULTENA" start="16" size="1" description="MemManage Enable Bit" /> + <BitField name="SVCALLPENDED" start="15" size="1" description="SVCall Pending Bit" /> + <BitField name="BUSFAULTPENDED" start="14" size="1" description="BusFault Exception Pending Bit" /> + <BitField name="MEMFAULTPENDED" start="13" size="1" description="MemManage Exception Pending Bit" /> + <BitField name="USGFAULTPENDED" start="12" size="1" description="UsageFault Exception Pending Bit" /> + <BitField name="SYSTICKACT" start="11" size="1" description="SysTick Exception Active Bit" /> + <BitField name="PENDSVACT" start="10" size="1" description="PendSV Exception Active Bit" /> + <BitField name="MONITORACT" start="8" size="1" description="Debug Monitor Active Bit" /> + <BitField name="SVCALLACT" start="7" size="1" description="SVCall Active Bit" /> + <BitField name="USGFAULTACT" start="3" size="1" description="UsageFault Exception Active Bit" /> + <BitField name="BUSFAULTACT" start="1" size="1" description="BusFault Exception Active Bit" /> + <BitField name="MEMFAULTACT" start="0" size="1" description="MemManage Exception Active Bit" /> + </Register> + <Register name="MMSR" start="0xE000ED28" size="1" description="MemManage Fault Status Register"> + <BitField name="MMARVALID" start="7" size="1" description="MemManage Fault Address Register(MMFAR) valid flag" /> + <BitField name="MSTKERR" start="4" size="1" description="MemManage fault on stacking for exception entry" /> + <BitField name="MUNSTKERR" start="3" size="1" description="MemManage fault on unstacking for a return from exception" /> + <BitField name="DACCVIOL" start="1" size="1" description="Data access violation flag" /> + <BitField name="IACCVIOL" start="0" size="1" description="Instruction access violation flag" /> + </Register> + <Register name="BFSR" start="0xE000ED29" size="1" description="BusFault Status Register"> + <BitField name="BFARVALID" start="7" size="1" description="BusFault Address Register(BFAR) valid flag" /> + <BitField name="STKERR" start="4" size="1" description="BusFault on stacking for exception entry" /> + <BitField name="UNSTKERR" start="3" size="1" description="BusFault on unstacking for a return from exception" /> + <BitField name="IMPRECISERR" start="2" size="1" description="Imprecise data bus error" /> + <BitField name="PRECISERR" start="1" size="1" description="Precise data bus error" /> + <BitField name="IBUSERR" start="0" size="1" description="Instruction bus error" /> + </Register> + <Register name="UFSR" start="0xE000ED2A" size="2" description="UsageFault Status Register"> + <BitField name="DIVBYZERO" start="9" size="1" description="Divide by zero UsageFault" /> + <BitField name="UNALIGNED" start="8" size="1" description="Unaligned access UsageFault" /> + <BitField name="NOCP" start="3" size="1" description="No coprocessor UsageFault" /> + <BitField name="INVPC" start="2" size="1" description="Invalid PC load UsageFault, causedby an invalid PC load by EXC_RETURN" /> + <BitField name="INVSTATE" start="1" size="1" description="Invalid state UsageFault" /> + <BitField name="UNDEFINSTR" start="0" size="1" description="Undefined instruction UsageFault" /> + </Register> + <Register name="HFSR" start="0xE000ED2C" description="HardFault Status Register"> + <BitField name="DEBUGEVT" start="31" size="1" description="" /> + <BitField name="FORCED" start="30" size="1" description="Indicates a forced hard fault, generated by escalation of a fault with configurable priority that cannot be handled, either because of priority or because it is disabled" /> + <BitField name="VECTTBL" start="1" size="1" description="Indicates a BusFault on a vectortable read during exception processing" /> + </Register> + <Register name="MMAR" start="0xE000ED34" description="MemManage Fault Address Register"> + <BitField name="ADDRESS" start="0" size="32" description="When the MMARVALID bit of the MMFSR is set to 1, this field holds the address of the location that generated the MemManage fault" /> + </Register> + <Register name="BFAR" start="0xE000ED38" description="BusFault Address Register"> + <BitField name="ADDRESS" start="0" size="32" description="When the BFARVALID bit of the BFSR is set to1, this field holds the address of the location that generated the BusFault" /> + </Register> + <Register name="AFSR" start="0xE000ED3C" description="Auxiliary Fault Status Register"> + <BitField name="IMPDEF" start="0" size="32" description="Implementation defined, the bits map to the AUXFAULT input signals" /> + </Register> + </RegisterGroup> + <RegisterGroup name="MPU" start="0xE000ED90" description="Memory Protection Unit"> + <Register name="MPU_TYPE" start="0xE000ED90" access="ReadOnly" description="MPU Type Register"> + <BitField name="IREGION" start="16" size="8" description="Number of supported MPU instruction regions" /> + <BitField name="DREGION" start="8" size="8" description="Number of supported MPU data regions" /> + <BitField name="SEPARATE" start="0" size="1" description="Support for unified or separate instruction and date memory maps" /> + </Register> + <Register name="MPU_CTRL" start="0xE000ED94" description="MPU Control Register"> + <BitField name="PRIVDEFENA" start="2" size="1" description="Enables privileged software access to the default memory map" /> + <BitField name="HFNMIENA" start="1" size="1" description="Enable the operation of MPU during hard fault, NMI, and FAULTMASK handlers" /> + <BitField name="ENABLE" start="0" size="1" description="Enable MPU" /> + </Register> + <Register name="MPU_RNR" start="0xE000ED98" description="MPU Region Number Register"> + <BitField name="REGION" start="0" size="8" description="Indicates the MPU region referenced by the MPU_RBAR and MPU_RASR registers" /> + </Register> + <Register name="MPU_RBAR" start="0xE000ED9C" description="MPU Region Base Address Register"> + <BitField name="ADDR" start="5" size="27" description="Region base address field" /> + <BitField name="VALID" start="4" size="1" description="MPU Region Number valid bit" /> + <BitField name="REGION" start="0" size="4" description="MPU region field" /> + </Register> + <Register name="MPU_RASR" start="0xE000EDA0" description="MPU Region Attribute and Size Register"> + <BitField name="XN" start="28" size="1" description="Instruction access disable bit" /> + <BitField name="AP" start="24" size="3" description="Access permission field" /> + <BitField name="TEX" start="19" size="3" description="Memory access attribute" /> + <BitField name="S" start="18" size="1" description="Shareable bit" /> + <BitField name="C" start="17" size="1" description="Memory access attribute" /> + <BitField name="B" start="16" size="1" description="Memory access attribute" /> + <BitField name="SRD" start="8" size="8" description="Subregion disable bits" /> + <BitField name="SIZE" start="1" size="5" description="MPU protection region size" /> + <BitField name="ENABLE" start="0" size="1" description="Region enable bit" /> + </Register> + </RegisterGroup> +</Processor> diff --git a/examples/device/cdc_msc_hid/ses/lpc175x_6x/LPC176x5x_Vectors.s b/examples/device/cdc_msc_hid/ses/lpc175x_6x/LPC176x5x_Vectors.s new file mode 100644 index 000000000..c5fae1310 --- /dev/null +++ b/examples/device/cdc_msc_hid/ses/lpc175x_6x/LPC176x5x_Vectors.s @@ -0,0 +1,418 @@ +/***************************************************************************** + * SEGGER Microcontroller GmbH & Co. KG * + * Solutions for real time microcontroller applications * + ***************************************************************************** + * * + * (c) 2015 SEGGER Microcontroller GmbH & Co. KG * + * * + * Internet: www.segger.com Support: [email protected] * + * * + *****************************************************************************/ + +/***************************************************************************** + * Preprocessor Definitions * + * ------------------------ * + * VECTORS_IN_RAM * + * * + * If defined, an area of RAM will large enough to store the vector table * + * will be reserved. * + * * + *****************************************************************************/ + + .syntax unified + .code 16 + + .section .init, "ax" + .align 0 + +/***************************************************************************** + * Default Exception Handlers * + *****************************************************************************/ + + .thumb_func + .weak NMI_Handler +NMI_Handler: + b . + + .thumb_func + .weak HardFault_Handler +HardFault_Handler: + b . + + .thumb_func + .weak SVC_Handler +SVC_Handler: + b . + + .thumb_func + .weak PendSV_Handler +PendSV_Handler: + b . + + .thumb_func + .weak SysTick_Handler +SysTick_Handler: + b . + + .thumb_func +Dummy_Handler: + b . + +#if defined(__OPTIMIZATION_SMALL) + + .weak WDT_IRQHandler + .thumb_set WDT_IRQHandler,Dummy_Handler + + .weak TIMER0_IRQHandler + .thumb_set TIMER0_IRQHandler,Dummy_Handler + + .weak TIMER1_IRQHandler + .thumb_set TIMER1_IRQHandler,Dummy_Handler + + .weak TIMER2_IRQHandler + .thumb_set TIMER2_IRQHandler,Dummy_Handler + + .weak TIMER3_IRQHandler + .thumb_set TIMER3_IRQHandler,Dummy_Handler + + .weak UART0_IRQHandler + .thumb_set UART0_IRQHandler,Dummy_Handler + + .weak UART1_IRQHandler + .thumb_set UART1_IRQHandler,Dummy_Handler + + .weak UART2_IRQHandler + .thumb_set UART2_IRQHandler,Dummy_Handler + + .weak UART3_IRQHandler + .thumb_set UART3_IRQHandler,Dummy_Handler + + .weak PWM1_IRQHandler + .thumb_set PWM1_IRQHandler,Dummy_Handler + + .weak I2C0_IRQHandler + .thumb_set I2C0_IRQHandler,Dummy_Handler + + .weak I2C1_IRQHandler + .thumb_set I2C1_IRQHandler,Dummy_Handler + + .weak I2C2_IRQHandler + .thumb_set I2C2_IRQHandler,Dummy_Handler + + .weak SPI_IRQHandler + .thumb_set SPI_IRQHandler,Dummy_Handler + + .weak SSP0_IRQHandler + .thumb_set SSP0_IRQHandler,Dummy_Handler + + .weak SSP1_IRQHandler + .thumb_set SSP1_IRQHandler,Dummy_Handler + + .weak PLL0_IRQHandler + .thumb_set PLL0_IRQHandler,Dummy_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Dummy_Handler + + .weak EINT0_IRQHandler + .thumb_set EINT0_IRQHandler,Dummy_Handler + + .weak EINT1_IRQHandler + .thumb_set EINT1_IRQHandler,Dummy_Handler + + .weak EINT2_IRQHandler + .thumb_set EINT2_IRQHandler,Dummy_Handler + + .weak EINT3_IRQHandler + .thumb_set EINT3_IRQHandler,Dummy_Handler + + .weak ADC_IRQHandler + .thumb_set ADC_IRQHandler,Dummy_Handler + + .weak BOD_IRQHandler + .thumb_set BOD_IRQHandler,Dummy_Handler + + .weak USB_IRQHandler + .thumb_set USB_IRQHandler,Dummy_Handler + + .weak CAN_IRQHandler + .thumb_set CAN_IRQHandler,Dummy_Handler + + .weak DMA_IRQHandler + .thumb_set DMA_IRQHandler,Dummy_Handler + + .weak I2S_IRQHandler + .thumb_set I2S_IRQHandler,Dummy_Handler + + .weak ENET_IRQHandler + .thumb_set ENET_IRQHandler,Dummy_Handler + + .weak RIT_IRQHandler + .thumb_set RIT_IRQHandler,Dummy_Handler + + .weak MCPWM_IRQHandler + .thumb_set MCPWM_IRQHandler,Dummy_Handler + + .weak QEI_IRQHandler + .thumb_set QEI_IRQHandler,Dummy_Handler + + .weak PLL1_IRQHandler + .thumb_set PLL1_IRQHandler,Dummy_Handler + + .weak USBActivity_IRQHandler + .thumb_set USBActivity_IRQHandler,Dummy_Handler + + .weak CANActivity_IRQHandler + .thumb_set CANActivity_IRQHandler,Dummy_Handler + +#else + + .thumb_func + .weak WDT_IRQHandler +WDT_IRQHandler: + b . + + .thumb_func + .weak TIMER0_IRQHandler +TIMER0_IRQHandler: + b . + + .thumb_func + .weak TIMER1_IRQHandler +TIMER1_IRQHandler: + b . + + .thumb_func + .weak TIMER2_IRQHandler +TIMER2_IRQHandler: + b . + + .thumb_func + .weak TIMER3_IRQHandler +TIMER3_IRQHandler: + b . + + .thumb_func + .weak UART0_IRQHandler +UART0_IRQHandler: + b . + + .thumb_func + .weak UART1_IRQHandler +UART1_IRQHandler: + b . + + .thumb_func + .weak UART2_IRQHandler +UART2_IRQHandler: + b . + + .thumb_func + .weak UART3_IRQHandler +UART3_IRQHandler: + b . + + .thumb_func + .weak PWM1_IRQHandler +PWM1_IRQHandler: + b . + + .thumb_func + .weak I2C0_IRQHandler +I2C0_IRQHandler: + b . + + .thumb_func + .weak I2C1_IRQHandler +I2C1_IRQHandler: + b . + + .thumb_func + .weak I2C2_IRQHandler +I2C2_IRQHandler: + b . + + .thumb_func + .weak SPI_IRQHandler +SPI_IRQHandler: + b . + + .thumb_func + .weak SSP0_IRQHandler +SSP0_IRQHandler: + b . + + .thumb_func + .weak SSP1_IRQHandler +SSP1_IRQHandler: + b . + + .thumb_func + .weak PLL0_IRQHandler +PLL0_IRQHandler: + b . + + .thumb_func + .weak RTC_IRQHandler +RTC_IRQHandler: + b . + + .thumb_func + .weak EINT0_IRQHandler +EINT0_IRQHandler: + b . + + .thumb_func + .weak EINT1_IRQHandler +EINT1_IRQHandler: + b . + + .thumb_func + .weak EINT2_IRQHandler +EINT2_IRQHandler: + b . + + .thumb_func + .weak EINT3_IRQHandler +EINT3_IRQHandler: + b . + + .thumb_func + .weak ADC_IRQHandler +ADC_IRQHandler: + b . + + .thumb_func + .weak BOD_IRQHandler +BOD_IRQHandler: + b . + + .thumb_func + .weak USB_IRQHandler +USB_IRQHandler: + b . + + .thumb_func + .weak CAN_IRQHandler +CAN_IRQHandler: + b . + + .thumb_func + .weak DMA_IRQHandler +DMA_IRQHandler: + b . + + .thumb_func + .weak I2S_IRQHandler +I2S_IRQHandler: + b . + + .thumb_func + .weak ENET_IRQHandler +ENET_IRQHandler: + b . + + .thumb_func + .weak RIT_IRQHandler +RIT_IRQHandler: + b . + + .thumb_func + .weak MCPWM_IRQHandler +MCPWM_IRQHandler: + b . + + .thumb_func + .weak QEI_IRQHandler +QEI_IRQHandler: + b . + + .thumb_func + .weak PLL1_IRQHandler +PLL1_IRQHandler: + b . + + .thumb_func + .weak USBActivity_IRQHandler +USBActivity_IRQHandler: + b . + + .thumb_func + .weak CANActivity_IRQHandler +CANActivity_IRQHandler: + b . + +#endif + +/***************************************************************************** + * Vector Table * + *****************************************************************************/ + + .section .vectors, "ax" + .align 0 + .global _vectors + .extern __stack_end__ + .extern Reset_Handler + +_vectors: + .word __stack_end__ + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word SVC_Handler + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word PendSV_Handler + .word SysTick_Handler + .word WDT_IRQHandler + .word TIMER0_IRQHandler + .word TIMER1_IRQHandler + .word TIMER2_IRQHandler + .word TIMER3_IRQHandler + .word UART0_IRQHandler + .word UART1_IRQHandler + .word UART2_IRQHandler + .word UART3_IRQHandler + .word PWM1_IRQHandler + .word I2C0_IRQHandler + .word I2C1_IRQHandler + .word I2C2_IRQHandler + .word SPI_IRQHandler + .word SSP0_IRQHandler + .word SSP1_IRQHandler + .word PLL0_IRQHandler + .word RTC_IRQHandler + .word EINT0_IRQHandler + .word EINT1_IRQHandler + .word EINT2_IRQHandler + .word EINT3_IRQHandler + .word ADC_IRQHandler + .word BOD_IRQHandler + .word USB_IRQHandler + .word CAN_IRQHandler + .word DMA_IRQHandler + .word I2S_IRQHandler + .word ENET_IRQHandler + .word RIT_IRQHandler + .word MCPWM_IRQHandler + .word QEI_IRQHandler + .word PLL1_IRQHandler + .word USBActivity_IRQHandler + .word CANActivity_IRQHandler +_vectors_end: + +#ifdef VECTORS_IN_RAM + .section .vectors_ram, "ax" + .align 0 + .global _vectors_ram + +_vectors_ram: + .space _vectors_end - _vectors, 0 +#endif diff --git a/examples/device/device_virtual_com/segger/flash_placement.xml b/examples/device/cdc_msc_hid/ses/lpc175x_6x/flash_placement.xml index 951d23710..79bedc537 100644 --- a/examples/device/device_virtual_com/segger/flash_placement.xml +++ b/examples/device/cdc_msc_hid/ses/lpc175x_6x/flash_placement.xml @@ -17,9 +17,9 @@ <ProgramSection alignment="0x100" load="No" name=".vectors_ram" start="$(RAM_START:$(SRAM_START:))" /> <ProgramSection alignment="4" load="No" name=".fast_run" /> <ProgramSection alignment="4" load="No" name=".data_run" /> - <ProgramSection alignment="4" load="No" name=".tdata_run" /> <ProgramSection alignment="4" load="No" name=".bss" /> <ProgramSection alignment="4" load="No" name=".tbss" /> + <ProgramSection alignment="4" load="No" name=".tdata_run" /> <ProgramSection alignment="4" load="No" name=".non_init" /> <ProgramSection alignment="4" size="__HEAPSIZE__" load="No" name=".heap" /> <ProgramSection alignment="8" size="__STACKSIZE__" load="No" place_from_segment_end="Yes" name=".stack" /> diff --git a/examples/device/cdc_msc_hid/ses/lpc175x_6x/lpc175x_6x.emProject b/examples/device/cdc_msc_hid/ses/lpc175x_6x/lpc175x_6x.emProject new file mode 100644 index 000000000..ecd2dc716 --- /dev/null +++ b/examples/device/cdc_msc_hid/ses/lpc175x_6x/lpc175x_6x.emProject @@ -0,0 +1,112 @@ +<!DOCTYPE CrossStudio_Project_File> +<solution Name="lpc175x_6x" target="8" version="2"> + <project Name="lpc175x_6x"> + <configuration + Name="Common" + Placement="Flash" + Target="LPC4357 Cortex-M4" + arm_architecture="v7M" + arm_core_type="Cortex-M3" + arm_endian="Little" + arm_fp_abi="Soft" + arm_fpu_type="None" + arm_interwork="No" + arm_linker_heap_size="1024" + arm_linker_process_stack_size="0" + arm_linker_stack_size="1024" + arm_simulator_memory_simulation_parameter="RX 00000000,00080000,FFFFFFFF;RWX 10000000,00008000,CDCDCDCD" + arm_target_debug_interface_type="ADIv5" + arm_target_device_name="LPC1769" + arm_target_interface_type="SWD" + build_treat_warnings_as_errors="Yes" + c_preprocessor_definitions="LPC175x_6x;__LPC1700_FAMILY;__LPC176x_SUBFAMILY;ARM_MATH_CM3;FLASH_PLACEMENT=1;CORE_M3;BOARD_LPCXPRESSO1769;CFG_TUSB_MCU=OPT_MCU_LPC175X_6X" + c_user_include_directories="../../src;$(rootDir)/hw;$(rootDir)/src;$(lpcDir)/inc" + debug_register_definition_file="LPC176x5x_Registers.xml" + debug_target_connection="J-Link" + gcc_enable_all_warnings="Yes" + gcc_entry_point="Reset_Handler" + link_use_linker_script_file="No" + linker_memory_map_file="LPC1769_MemoryMap.xml" + linker_section_placement_file="flash_placement.xml" + linker_section_placements_segments="FLASH RX 0x00000000 0x00080000;RAM RWX 0x10000000 0x00008000" + macros="DeviceFamily=LPC1700;DeviceSubFamily=LPC176x;Target=LPC1769;Placement=Flash;rootDir=../../../../..;lpcDir=../../../../../hw/mcu/nxp/lpc_chip_175x_6x" + project_directory="" + project_type="Executable" + target_reset_script="Reset();" + target_script_file="$(ProjectDir)/LPC1700_Target.js" + target_trace_initialize_script="EnableTrace("$(TraceInterfaceType)")" /> + <folder + Name="tinyusb" + exclude="" + filter="*.c;*.h" + path="../../../../../src" + recurse="Yes" /> + <folder Name="hw"> + <folder Name="bsp"> + <file file_name="../../../../../hw/bsp/ansi_escape.h" /> + <file file_name="../../../../../hw/bsp/board.h" /> + <folder Name="lpcxpresso1769"> + <file file_name="../../../../../hw/bsp/lpcxpresso1769/board_lpcxpresso1769.c" /> + <file file_name="../../../../../hw/bsp/lpcxpresso1769/board_lpcxpresso1769.h" /> + </folder> + </folder> + <folder Name="mcu"> + <folder Name="nxp"> + <folder Name="lpc_chip_175x_6x"> + <folder Name="inc"> + <file file_name="../../../../../hw/mcu/nxp/lpc_chip_175x_6x/inc/chip.h" /> + <file file_name="../../../../../hw/mcu/nxp/lpc_chip_175x_6x/inc/chip_lpc175x_6x.h" /> + <file file_name="../../../../../hw/mcu/nxp/lpc_chip_175x_6x/inc/chip_lpc177x_8x.h" /> + <file file_name="../../../../../hw/mcu/nxp/lpc_chip_175x_6x/inc/chip_lpc407x_8x.h" /> + <file file_name="../../../../../hw/mcu/nxp/lpc_chip_175x_6x/inc/clock_17xx_40xx.h" /> + <file file_name="../../../../../hw/mcu/nxp/lpc_chip_175x_6x/inc/cmsis.h" /> + <file file_name="../../../../../hw/mcu/nxp/lpc_chip_175x_6x/inc/cmsis_175x_6x.h" /> + <file file_name="../../../../../hw/mcu/nxp/lpc_chip_175x_6x/inc/core_cm3.h" /> + <file file_name="../../../../../hw/mcu/nxp/lpc_chip_175x_6x/inc/core_cmFunc.h" /> + <file file_name="../../../../../hw/mcu/nxp/lpc_chip_175x_6x/inc/core_cmInstr.h" /> + <file file_name="../../../../../hw/mcu/nxp/lpc_chip_175x_6x/inc/gpio_17xx_40xx.h" /> + <file file_name="../../../../../hw/mcu/nxp/lpc_chip_175x_6x/inc/gpioint_17xx_40xx.h" /> + <file file_name="../../../../../hw/mcu/nxp/lpc_chip_175x_6x/inc/iocon_17xx_40xx.h" /> + <file file_name="../../../../../hw/mcu/nxp/lpc_chip_175x_6x/inc/lpc_types.h" /> + <file file_name="../../../../../hw/mcu/nxp/lpc_chip_175x_6x/inc/sys_config.h" /> + <file file_name="../../../../../hw/mcu/nxp/lpc_chip_175x_6x/inc/sysctl_17xx_40xx.h" /> + <file file_name="../../../../../hw/mcu/nxp/lpc_chip_175x_6x/inc/uart_17xx_40xx.h" /> + </folder> + <folder Name="src"> + <file file_name="../../../../../hw/mcu/nxp/lpc_chip_175x_6x/src/chip_17xx_40xx.c" /> + <file file_name="../../../../../hw/mcu/nxp/lpc_chip_175x_6x/src/clock_17xx_40xx.c" /> + <file file_name="../../../../../hw/mcu/nxp/lpc_chip_175x_6x/src/gpio_17xx_40xx.c" /> + <file file_name="../../../../../hw/mcu/nxp/lpc_chip_175x_6x/src/iocon_17xx_40xx.c" /> + <file file_name="../../../../../hw/mcu/nxp/lpc_chip_175x_6x/src/sysctl_17xx_40xx.c" /> + <file file_name="../../../../../hw/mcu/nxp/lpc_chip_175x_6x/src/sysinit_17xx_40xx.c" /> + <file file_name="../../../../../hw/mcu/nxp/lpc_chip_175x_6x/src/uart_17xx_40xx.c" /> + </folder> + </folder> + </folder> + </folder> + </folder> + <configuration Name="Debug" build_treat_warnings_as_errors="Yes" /> + <folder + Name="src" + exclude="" + filter="*.c;*.h" + path="../../src" + recurse="Yes" /> + <folder Name="System Files"> + <file file_name="flash_placement.xml" /> + <file file_name="LPC1700_Startup.s" /> + <file file_name="LPC1700_Target.js" /> + <file file_name="LPC1769_MemoryMap.xml" /> + <file file_name="LPC176x5x_Registers.xml" /> + <file file_name="LPC176x5x_Vectors.s" /> + <file file_name="thumb_crt0.s" /> + </folder> + <folder + Name="segger_rtt" + exclude="" + filter="*.c;*.h" + path="../../../../../lib/segger_rtt" + recurse="No" /> + </project> + <configuration Name="LPCXpresso 1769" /> +</solution> diff --git a/examples/device/cdc_msc_hid/ses/lpc175x_6x/thumb_crt0.s b/examples/device/cdc_msc_hid/ses/lpc175x_6x/thumb_crt0.s new file mode 100644 index 000000000..17f88e0ca --- /dev/null +++ b/examples/device/cdc_msc_hid/ses/lpc175x_6x/thumb_crt0.s @@ -0,0 +1,415 @@ +// ********************************************************************** +// * SEGGER Microcontroller GmbH * +// * The Embedded Experts * +// ********************************************************************** +// * * +// * (c) 2014 - 2018 SEGGER Microcontroller GmbH * +// * (c) 2001 - 2018 Rowley Associates Limited * +// * * +// * www.segger.com Support: [email protected] * +// * * +// ********************************************************************** +// * * +// * All rights reserved. * +// * * +// * Redistribution and use in source and binary forms, with or * +// * without modification, are permitted provided that the following * +// * conditions are met: * +// * * +// * - Redistributions of source code must retain the above copyright * +// * notice, this list of conditions and the following disclaimer. * +// * * +// * - Neither the name of SEGGER Microcontroller GmbH * +// * nor the names of its contributors may be used to endorse or * +// * promote products derived from this software without specific * +// * prior written permission. * +// * * +// * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND * +// * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, * +// * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * +// * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * +// * DISCLAIMED. * +// * IN NO EVENT SHALL SEGGER Microcontroller GmbH BE LIABLE FOR * +// * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * +// * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT * +// * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * +// * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF * +// * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * +// * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE * +// * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH * +// * DAMAGE. * +// * * +// ********************************************************************** +// +// +// Preprocessor Definitions +// ------------------------ +// APP_ENTRY_POINT +// +// Defines the application entry point function, if undefined this setting +// defaults to "main". +// +// INITIALIZE_STACK +// +// If defined, the contents of the stack will be initialized to a the +// value 0xCC. +// +// INITIALIZE_SECONDARY_SECTIONS +// +// If defined, the .data2, .text2, .rodata2 and .bss2 sections will be initialized. +// +// INITIALIZE_TCM_SECTIONS +// +// If defined, the .data_tcm, .text_tcm, .rodata_tcm and .bss_tcm sections +// will be initialized. +// +// INITIALIZE_USER_SECTIONS +// +// If defined, the function InitializeUserMemorySections will be called prior +// to entering main in order to allow the user to initialize any user defined +// memory sections. +// +// FULL_LIBRARY +// +// If defined then +// - argc, argv are setup by the debug_getargs. +// - the exit symbol is defined and executes on return from main. +// - the exit symbol calls destructors, atexit functions and then debug_exit. +// +// If not defined then +// - argc and argv are zero. +// - the exit symbol is defined, executes on return from main and loops +// + +#ifndef APP_ENTRY_POINT +#define APP_ENTRY_POINT main +#endif + +#ifndef ARGSSPACE +#define ARGSSPACE 128 +#endif + .syntax unified + + .global _start + .extern APP_ENTRY_POINT + .global exit + .weak exit + +#ifdef INITIALIZE_USER_SECTIONS + .extern InitializeUserMemorySections +#endif + + .section .init, "ax" + .code 16 + .balign 2 + .thumb_func + +_start: + /* Set up main stack if size > 0 */ + ldr r1, =__stack_end__ + ldr r0, =__stack_start__ + subs r2, r1, r0 + beq 1f +#ifdef __ARM_EABI__ + movs r2, #0x7 + bics r1, r2 +#endif + mov sp, r1 +#ifdef INITIALIZE_STACK + movs r2, #0xCC + ldr r0, =__stack_start__ + bl memory_set +#endif +1: + + /* Set up process stack if size > 0 */ + ldr r1, =__stack_process_end__ + ldr r0, =__stack_process_start__ + subs r2, r1, r0 + beq 1f +#ifdef __ARM_EABI__ + movs r2, #0x7 + bics r1, r2 +#endif + msr psp, r1 + movs r2, #2 + msr control, r2 +#ifdef INITIALIZE_STACK + movs r2, #0xCC + bl memory_set +#endif +1: + + /* Copy initialized memory sections into RAM (if necessary). */ + ldr r0, =__data_load_start__ + ldr r1, =__data_start__ + ldr r2, =__data_end__ + bl memory_copy + ldr r0, =__text_load_start__ + ldr r1, =__text_start__ + ldr r2, =__text_end__ + bl memory_copy + ldr r0, =__fast_load_start__ + ldr r1, =__fast_start__ + ldr r2, =__fast_end__ + bl memory_copy + ldr r0, =__ctors_load_start__ + ldr r1, =__ctors_start__ + ldr r2, =__ctors_end__ + bl memory_copy + ldr r0, =__dtors_load_start__ + ldr r1, =__dtors_start__ + ldr r2, =__dtors_end__ + bl memory_copy + ldr r0, =__rodata_load_start__ + ldr r1, =__rodata_start__ + ldr r2, =__rodata_end__ + bl memory_copy + ldr r0, =__tdata_load_start__ + ldr r1, =__tdata_start__ + ldr r2, =__tdata_end__ + bl memory_copy +#ifdef INITIALIZE_SECONDARY_SECTIONS + ldr r0, =__data2_load_start__ + ldr r1, =__data2_start__ + ldr r2, =__data2_end__ + bl memory_copy + ldr r0, =__text2_load_start__ + ldr r1, =__text2_start__ + ldr r2, =__text2_end__ + bl memory_copy + ldr r0, =__rodata2_load_start__ + ldr r1, =__rodata2_start__ + ldr r2, =__rodata2_end__ + bl memory_copy +#endif /* #ifdef INITIALIZE_SECONDARY_SECTIONS */ +#ifdef INITIALIZE_TCM_SECTIONS + ldr r0, =__data_tcm_load_start__ + ldr r1, =__data_tcm_start__ + ldr r2, =__data_tcm_end__ + bl memory_copy + ldr r0, =__text_tcm_load_start__ + ldr r1, =__text_tcm_start__ + ldr r2, =__text_tcm_end__ + bl memory_copy + ldr r0, =__rodata_tcm_load_start__ + ldr r1, =__rodata_tcm_start__ + ldr r2, =__rodata_tcm_end__ + bl memory_copy +#endif /* #ifdef INITIALIZE_TCM_SECTIONS */ + + /* Zero the bss. */ + ldr r0, =__bss_start__ + ldr r1, =__bss_end__ + movs r2, #0 + bl memory_set + ldr r0, =__tbss_start__ + ldr r1, =__tbss_end__ + movs r2, #0 + bl memory_set +#ifdef INITIALIZE_SECONDARY_SECTIONS + ldr r0, =__bss2_start__ + ldr r1, =__bss2_end__ + mov r2, #0 + bl memory_set +#endif /* #ifdef INITIALIZE_SECONDARY_SECTIONS */ +#ifdef INITIALIZE_TCM_SECTIONS + ldr r0, =__bss_tcm_start__ + ldr r1, =__bss_tcm_end__ + mov r2, #0 + bl memory_set +#endif /* #ifdef INITIALIZE_TCM_SECTIONS */ + + /* Initialize the heap */ + ldr r0, = __heap_start__ + ldr r1, = __heap_end__ + subs r1, r1, r0 + cmp r1, #8 + blt 1f + movs r2, #0 + str r2, [r0] + adds r0, r0, #4 + str r1, [r0] +1: + +#ifdef INITIALIZE_USER_SECTIONS + ldr r2, =InitializeUserMemorySections + blx r2 +#endif + + /* Call constructors */ + ldr r0, =__ctors_start__ + ldr r1, =__ctors_end__ +ctor_loop: + cmp r0, r1 + beq ctor_end + ldr r2, [r0] + adds r0, #4 + push {r0-r1} + blx r2 + pop {r0-r1} + b ctor_loop +ctor_end: + + /* Setup initial call frame */ + movs r0, #0 + mov lr, r0 + mov r12, sp + + .type start, function +start: + /* Jump to application entry point */ +#ifdef FULL_LIBRARY + movs r0, #ARGSSPACE + ldr r1, =args + ldr r2, =debug_getargs + blx r2 + ldr r1, =args +#else + movs r0, #0 + movs r1, #0 +#endif + ldr r2, =APP_ENTRY_POINT + blx r2 + + .thumb_func +exit: +#ifdef FULL_LIBRARY + mov r5, r0 // save the exit parameter/return result + + /* Call destructors */ + ldr r0, =__dtors_start__ + ldr r1, =__dtors_end__ +dtor_loop: + cmp r0, r1 + beq dtor_end + ldr r2, [r0] + add r0, #4 + push {r0-r1} + blx r2 + pop {r0-r1} + b dtor_loop +dtor_end: + + /* Call atexit functions */ + ldr r2, =_execute_at_exit_fns + blx r2 + + /* Call debug_exit with return result/exit parameter */ + mov r0, r5 + ldr r2, =debug_exit + blx r2 +#endif + + /* Returned from application entry point, loop forever. */ +exit_loop: + b exit_loop + + .thumb_func +memory_copy: + cmp r0, r1 + beq 2f + subs r2, r2, r1 + beq 2f +1: + ldrb r3, [r0] + adds r0, r0, #1 + strb r3, [r1] + adds r1, r1, #1 + subs r2, r2, #1 + bne 1b +2: + bx lr + + .thumb_func +memory_set: + cmp r0, r1 + beq 1f + strb r2, [r0] + adds r0, r0, #1 + b memory_set +1: + bx lr + + // default C/C++ library helpers + +.macro HELPER helper_name + .section .text.\helper_name, "ax", %progbits + .balign 2 + .global \helper_name + .weak \helper_name +\helper_name: + .thumb_func +.endm + +.macro JUMPTO name +#if defined(__thumb__) && !defined(__thumb2__) + mov r12, r0 + ldr r0, =\name + push {r0} + mov r0, r12 + pop {pc} +#else + b \name +#endif +.endm + +HELPER __aeabi_read_tp + ldr r0, =__tbss_start__-8 + bx lr +HELPER abort + b . +HELPER __assert + b . +HELPER __aeabi_assert + b . +HELPER __sync_synchronize + bx lr +HELPER __getchar + JUMPTO debug_getchar +HELPER __putchar + JUMPTO debug_putchar +HELPER __open + JUMPTO debug_fopen +HELPER __close + JUMPTO debug_fclose +HELPER __write + mov r3, r0 + mov r0, r1 + movs r1, #1 + JUMPTO debug_fwrite +HELPER __read + mov r3, r0 + mov r0, r1 + movs r1, #1 + JUMPTO debug_fread +HELPER __seek + push {r4, lr} + mov r4, r0 + bl debug_fseek + cmp r0, #0 + bne 1f + mov r0, r4 + bl debug_ftell + pop {r4, pc} +1: + ldr r0, =-1 + pop {r4, pc} + // char __user_locale_name_buffer[]; + .section .bss.__user_locale_name_buffer, "aw", %nobits + .global __user_locale_name_buffer + .weak __user_locale_name_buffer + __user_locale_name_buffer: + .word 0x0 + +#ifdef FULL_LIBRARY + .bss +args: + .space ARGSSPACE +#endif + + /* Setup attibutes of stack and heap sections so they don't take up room in the elf file */ + .section .stack, "wa", %nobits + .section .stack_process, "wa", %nobits + .section .heap, "wa", %nobits + diff --git a/examples/device/cdc_msc_hid/ses/lpc18xx/LPC1800_Startup.s b/examples/device/cdc_msc_hid/ses/lpc18xx/LPC1800_Startup.s new file mode 100644 index 000000000..e17b60508 --- /dev/null +++ b/examples/device/cdc_msc_hid/ses/lpc18xx/LPC1800_Startup.s @@ -0,0 +1,110 @@ +/***************************************************************************** + * SEGGER Microcontroller GmbH & Co. KG * + * Solutions for real time microcontroller applications * + ***************************************************************************** + * * + * (c) 2017 SEGGER Microcontroller GmbH & Co. KG * + * * + * Internet: www.segger.com Support: [email protected] * + * * + *****************************************************************************/ + +/***************************************************************************** + * Preprocessor Definitions * + * ------------------------ * + * NO_STACK_INIT * + * * + * If defined, the stack pointer will not be initialised. * + * * + * NO_SYSTEM_INIT * + * * + * If defined, the SystemInit() function will not be called. By default * + * SystemInit() is called after reset to enable the clocks and memories to * + * be initialised prior to any C startup initialisation. * + * * + * NO_VTOR_CONFIG * + * * + * If defined, the vector table offset register will not be configured. * + * * + * MEMORY_INIT * + * * + * If defined, the MemoryInit() function will be called. By default * + * MemoryInit() is called after SystemInit() to enable an external memory * + * controller. * + * * + * STACK_INIT_VAL * + * * + * If defined, specifies the initial stack pointer value. If undefined, * + * the stack pointer will be initialised to point to the end of the * + * RAM segment. * + * * + * VECTORS_IN_RAM * + * * + * If defined, the exception vectors will be copied from Flash to RAM. * + * * + *****************************************************************************/ + + .syntax unified + + .global Reset_Handler + .extern _vectors + + .section .init, "ax" + .thumb_func + + .equ VTOR_REG, 0xE000ED08 + +#ifndef STACK_INIT_VAL +#define STACK_INIT_VAL __RAM_segment_end__ +#endif + +Reset_Handler: +#ifndef NO_STACK_INIT + /* Initialise main stack */ + ldr r0, =STACK_INIT_VAL + bic r0, #0x7 + mov sp, r0 +#endif + +#ifndef NO_SYSTEM_INIT + /* Initialise system */ + ldr r0, =SystemInit + blx r0 +#endif + +#ifdef MEMORY_INIT + ldr r0, =MemoryInit + blx r0 +#endif + +#ifdef VECTORS_IN_RAM + /* Copy exception vectors into RAM */ + ldr r0, =__vectors_start__ + ldr r1, =__vectors_end__ + ldr r2, =__vectors_ram_start__ +1: + cmp r0, r1 + beq 2f + ldr r3, [r0] + str r3, [r2] + adds r0, r0, #4 + adds r2, r2, #4 + b 1b +2: +#endif + +#ifndef NO_VTOR_CONFIG + /* Configure vector table offset register */ + ldr r0, =VTOR_REG +#ifdef VECTORS_IN_RAM + ldr r1, =_vectors_ram +#else + ldr r1, =_vectors +#endif + str r1, [r0] +#endif + + /* Jump to program start */ + b _start + + diff --git a/examples/device/cdc_msc_hid/ses/lpc18xx/LPC1800_Target.js b/examples/device/cdc_msc_hid/ses/lpc18xx/LPC1800_Target.js new file mode 100644 index 000000000..20560af43 --- /dev/null +++ b/examples/device/cdc_msc_hid/ses/lpc18xx/LPC1800_Target.js @@ -0,0 +1,19 @@ +/***************************************************************************** + * SEGGER Microcontroller GmbH & Co. KG * + * Solutions for real time microcontroller applications * + ***************************************************************************** + * * + * (c) 2017 SEGGER Microcontroller GmbH & Co. KG * + * * + * Internet: www.segger.com Support: [email protected] * + * * + *****************************************************************************/ + +function Reset() { + TargetInterface.resetAndStop(); +} + +function EnableTrace(traceInterfaceType) { + // TODO: Enable trace +} + diff --git a/examples/device/device_virtual_com/segger/LPC4357 Cortex-M4_MemoryMap.xml b/examples/device/cdc_msc_hid/ses/lpc18xx/LPC1857_MemoryMap.xml index eb42b7bfd..4ded8a9f3 100644 --- a/examples/device/device_virtual_com/segger/LPC4357 Cortex-M4_MemoryMap.xml +++ b/examples/device/cdc_msc_hid/ses/lpc18xx/LPC1857_MemoryMap.xml @@ -1,5 +1,5 @@ <!DOCTYPE Board_Memory_Definition_File> -<root name="LPC4357 Cortex-M4"> +<root name="LPC1857"> <MemorySegment name="RAM" start="0x10000000" size="0x00008000" access="Read/Write" /> <MemorySegment name="FLASH" start="0x1A000000" size="0x00080000" access="ReadOnly" /> <MemorySegment name="FLASH2" start="0x1B000000" size="0x00080000" access="ReadOnly" /> diff --git a/examples/device/device_virtual_com/segger/LPC43xx_Registers.xml b/examples/device/cdc_msc_hid/ses/lpc18xx/LPC18xx_Registers.xml index 9c0946466..5e68d4c0f 100644 --- a/examples/device/device_virtual_com/segger/LPC43xx_Registers.xml +++ b/examples/device/cdc_msc_hid/ses/lpc18xx/LPC18xx_Registers.xml @@ -1,5 +1,5 @@ <!DOCTYPE Register_Definition_File> -<Processor name="LPC43xx" description="Register cmsis file for LPC43xx parts"> +<Processor name="LPC18xx" description="Register cmsis file for LPC18xx parts"> <RegisterGroup name="SCT" start="0x40000000" description="State Configurable Timer (SCT) with dither engine "> <Register start="+0x000" size="4" name="CONFIG" access="Read/Write" description="SCT configuration register" reset_value="0x00007E00" reset_mask="0xFFFFFFFF"> <BitField start="0" size="1" name="UNIFY" description="SCT operation"> @@ -10,7 +10,6 @@ <Enum name="BUS_CLOCK" start="0x0" description="Bus clock. The bus clock clocks the SCT and prescalers." /> <Enum name="PRESCALED_BUS_CLOCK" start="0x1" description="Prescaled bus clock. The SCT clock is the bus clock, but the prescalers are enabled to count only when sampling of the input selected by the CKSEL field finds the selected edge. The minimum pulse width on the clock input is 1 bus clock period. This mode is the high-performance sampled-clock mode." /> <Enum name="SCT_INPUT" start="0x2" description="SCT Input. The input selected by CKSEL clocks the SCT and prescalers. The input is synchronized to the bus clock and possibly inverted. The minimum pulse width on the clock input is 1 bus clock period. This mode is the low-power sampled-clock mode." /> - <Enum name="RESERVED" start="0x3" description="Reserved." /> </BitField> <BitField start="3" size="4" name="CKSEL" description="SCT clock select"> <Enum name="RISING_EDGES_ON_INPU" start="0x0" description="Rising edges on input 0." /> @@ -3839,7 +3838,6 @@ <Enum name="ALL_QUADDUAL" start="0x3" description="All quad/dual. All fields of the command are in quad/dual format." /> </BitField> <BitField start="21" size="3" name="FRAMEFORM" description="This field controls the opcode and address fields."> - <Enum name="RESERVED" start="0x0" description="Reserved." /> <Enum name="OPCODE" start="0x1" description="Opcode. Opcode only, no address." /> <Enum name="OPCODE_ONE_BYTE" start="0x2" description="Opcode one byte. Opcode, least significant byte of address." /> <Enum name="OPCODE_TWO_BYTES" start="0x3" description="Opcode two bytes. Opcode, two least significant bytes of address." /> @@ -3874,8 +3872,6 @@ <Enum name="ALL_QUADDUAL" start="0x3" description="All quad/dual. All fields of the command are in quad/dual format." /> </BitField> <BitField start="21" size="3" name="FRAMEFORM" description="This field controls the opcode and address fields."> - <Enum name="RESERVED" start="0x0" description="Reserved." /> - <Enum name="RESERVED" start="0x1" description="Reserved." /> <Enum name="OPCODE_ONE_BYTE" start="0x2" description="Opcode one byte. Opcode, least-significant byte of address." /> <Enum name="OPCODE_TWO_BYTES" start="0x3" description="Opcode two bytes. Opcode, 2 least-significant bytes of address." /> <Enum name="OPCODE_THREE_BYTES" start="0x4" description="Opcode three bytes. Opcode, 3 least-significant bytes of address." /> @@ -9895,7 +9891,7 @@ <BitField start="2" size="1" name="END_OF_PROG" description="EEPROM program operation finished interrupt status bit. Bit is: - set when this operation has finished OR when one is written to the corresponding bit of the INTSTATSET register. - cleared when one is written to the corresponding bit of the INTSTATCLR register." /> <BitField start="3" size="29" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> </Register> - <Register start="+0xFE4" size="4" name="INTEN" access="ReadOnly" description="EEPROM interrupt enable" reset_value="0" reset_mask="0xFFFFFFFF"> + <Register start="+0xFE4" size="4" name="INTEN" access="WriteOnly" description="EEPROM interrupt enable" reset_value="0" reset_mask="0xFFFFFFFF"> <BitField start="0" size="2" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> <BitField start="2" size="1" name="EE_PROG_DONE" description="EEPROM program operation finished interrupt enable bit. Bit is: - set when one is written in the corresponding bit of the INTENSET register. - cleared when one is written to the corresponding bit of the INTENCLR register." /> <BitField start="3" size="29" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> @@ -9905,6 +9901,11 @@ <BitField start="2" size="1" name="PROG_CLR_ST" description="Clear program operation finished interrupt status bit for EEPROM device. 0 = leave corresponding bit unchanged. 1 = clear corresponding bit." /> <BitField start="3" size="29" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> </Register> + <Register start="+0xFEC" size="4" name="INTSTATSET" access="WriteOnly" description="EEPROM interrupt status set" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="2" size="1" name="PROG_SET_ST" description="Set program operation finished interrupt status bit for EEPROM device. 0 = leave corresponding bit unchanged. 1 = set corresponding bit." /> + <BitField start="3" size="29" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> </RegisterGroup> <RegisterGroup name="ETHERNET" start="0x40010000" description="Ethernet"> <Register start="+0x0000" size="4" name="MAC_CONFIG" access="Read/Write" description="MAC configuration register" reset_value="0x00008000" reset_mask="0xFFFFFFFF"> @@ -9953,7 +9954,7 @@ <Register start="+0x0010" size="4" name="MAC_MII_ADDR" access="Read/Write" description="MII address register" reset_value="0x00000000" reset_mask="0xFFFFFFFF"> <BitField start="0" size="1" name="GB" description="MII busy This register field can be read by the application (Read), can be set to 1 by the application with a register write of 1 (Write Set), and is cleared to 0 by the core (Self Clear). The application cannot clear this type of field, and a register write of 0 to this bit has no effect on this field. This bit should read a logic 0 before writing to this register and the MAC_MII_DATA register. This bit must also be set to 0 during a Write to this register. During a PHY register access, this bit will be set to 1 by the Application to indicate that a Read or Write access is in progress. The MAC_MII_DATA register should be kept valid until this bit is cleared by the MAC during a PHY Write operation. The MAC_MII_DATA register is invalid until this bit is cleared by the MAC during a PHY Read operation. This register should not be written to until this bit is cleared." /> <BitField start="1" size="1" name="W" description="MII write When set, this bit tells the PHY that this will be a Write operation using the MII Data register. If this bit is not set, this will be a Read operation, placing the data in the MII Data register." /> - <BitField start="2" size="4" name="CR" description="CSR clock range The CSR Clock Range selection determines the frequency of the MDC clock. The suggested range of CLK_M4_ETHERNET frequency applicable for each value below (when Bit[5] = 0) ensures that the MDC clock is approximately between the frequency range 1.0 MHz - 2.5 MHz. When bit 5 is set, you can achieve MDC clock of frequency higher than the IEEE 802.3 specified frequency limit of 2.5 MHz and program a clock divider of lower value. For example, when CLK_M4_ETHERNET is of frequency 100 MHz and you program these bits as 1010, then the resultant MDC clock will be of 12.5 MHz which is outside the limit of IEEE 802.3 specified range. Program the values given below only if the interfacing chips supports faster MDC clocks. See Table 554 for bit values." /> + <BitField start="2" size="4" name="CR" description="CSR clock range The CSR Clock Range selection determines the frequency of the MDC clock. The suggested range of CLK_M3_ETHERNET frequency applicable for each value below (when Bit[5] = 0) ensures that the MDC clock is approximately between the frequency range 1.0 MHz - 2.5 MHz. When bit 5 is set, you can achieve MDC clock of frequency higher than the IEEE 802.3 specified frequency limit of 2.5 MHz and program a clock divider of lower value. For example, when CLK_M3_ETHERNET is of frequency 100 MHz and you program these bits as 1010, then the resultant MDC clock will be of 12.5 MHz which is outside the limit of IEEE 802.3 specified range. Program the values given below only if the interfacing chips supports faster MDC clocks. See Table 554 for bit values." /> <BitField start="6" size="5" name="GR" description="MII register These bits select the desired MII register in the selected PHY device." /> <BitField start="11" size="5" name="PA" description="Physical layer address This field tells which of the 32 possible PHY devices are being accessed." /> <BitField start="16" size="16" name="RESERVED" description="Reserved" /> @@ -10436,12 +10437,11 @@ </RegisterGroup> <RegisterGroup name="PMC" start="0x40042000" description="Power Management Controller (PMC)"> <Register start="+0x000" size="4" name="PD0_SLEEP0_HW_ENA" access="Read/Write" description="Hardware sleep event enable register" reset_value="0x00000001" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="1" name="ENA_EVENT0" description="Writing a 1 enables the Cortex-M4 core to put the part
								into any of the Power-down modes Deep-sleep,
								Power-down, or Deep power-down depending on the
								value in the PD0_SLEEP0_MODE register." /> - <BitField start="1" size="1" name="ENA_EVENT1" description="Writing a 1 enables the Cortex-M0 core and the
								Cortex-M0 subsystem core to put the part into any of
								the Power-down modes Deep-sleep, Power-down, or
								Deep power-down depending on the value in the
								PD0_SLEEP0_MODE register." /> - <BitField start="2" size="30" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + <BitField start="0" size="1" name="ENA_EVENT0" description="Writing a 1 enables the Cortex-M3 core to put the part
								into any of the Power-down modes Deep-sleep,
								Power-down, or Deep power-down depending on the
								value in the PD0_SLEEP0_MODE register" /> + <BitField start="1" size="31" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> </Register> <Register start="+0x01C" size="4" name="PD0_SLEEP0_MODE" access="Read/Write" description="Sleep power mode register" reset_value="0x003FFF7F" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="32" name="PWR_STATE" description="Selects between Deep-sleep, Power-down, and Deep power-down modes.
								Only one of the following three values can be programmed in this register:
								0x0030 00AA = Deep-sleep mode
								0x0030 FCBA = Power-down mode
								0x0030 3CBA = Power-down mode with M0SUB SRAM maintained
								0x0030 FF7F = Deep power-down mode" /> + <BitField start="0" size="32" name="PWR_STATE" description="Selects between Deep-sleep, Power-down, and Deep power-down modes.
								Only one of the following three values can be programmed in this register:
								0x0030 00AA = Deep-sleep mode
								0x0030 FCBA = Power-down mode
							
								0x0030 FF7F = Deep power-down mode" /> </Register> </RegisterGroup> <RegisterGroup name="CREG" start="0x40043000" description="Configuration Registers (CREG)"> @@ -10473,13 +10473,13 @@ <Enum name="RESERVED" start="0x2" description="Reserved." /> <Enum name="INACTIVE" start="0x3" description="Inactive." /> </BitField> - <BitField start="8" size="2" name="BODLVL1" description="BOD trip level to generate an interrupt. See the LPC43xx data sheets for the trip values."> + <BitField start="8" size="2" name="BODLVL1" description="BOD trip level to generate an interrupt. See the data sheet for the trip values."> <Enum name="LEVEL_0_INTERRUPT" start="0x0" description="Level 0 interrupt" /> <Enum name="LEVEL_1_INTERRUPT" start="0x1" description="Level 1 interrupt" /> <Enum name="LEVEL_2_INTERRUPT" start="0x2" description="Level 2 interrupt" /> <Enum name="LEVEL_3_INTERRUPT" start="0x3" description="Level 3 interrupt" /> </BitField> - <BitField start="10" size="2" name="BODLVL2" description="BOD trip level to generate a reset. See the LPC43xx data sheets for the trip values."> + <BitField start="10" size="2" name="BODLVL2" description="BOD trip level to generate a reset. See the data sheet for the trip values."> <Enum name="LEVEL_0_RESET" start="0x0" description="Level 0 reset" /> <Enum name="LEVEL_1_RESET" start="0x1" description="Level 1 reset" /> <Enum name="LEVEL_2_RESET" start="0x2" description="Level 2 reset" /> @@ -10505,30 +10505,22 @@ </BitField> <BitField start="18" size="14" name="RESERVED" description="Reserved" /> </Register> - <Register start="+0x100" size="4" name="M4MEMMAP" access="Read/Write" description="ARM Cortex-M4 memory mapping" reset_value="0x10400000" reset_mask="0xFFFFFFFF"> - <BitField start="12" size="20" name="M4MAP" description="Shadow address when accessing memory at address 0x0000 0000" /> + <Register start="+0x100" size="4" name="M3MEMMAP" access="Read/Write" description="ARM Cortex-M3 memory mapping" reset_value="0x10400000" reset_mask="0xFFFFFFFF"> + <BitField start="12" size="20" name="M3MAP" description="Shadow address when accessing memory at address 0x0000 0000" /> </Register> <Register start="+0x118" size="4" name="CREG5" access="Read/Write" description="Chip configuration register 5. Controls JTAG access." reset_value="0" reset_mask="0x00000000"> - <BitField start="0" size="10" name="RESERVED" description="Reserved." /> - <BitField start="10" size="1" name="M0SUBTAPSEL" description="JTAG debug disable for M0SUB co-processor. If this bit is set to 1, it can be changed to 0 only through a chip reset."> - <Enum name="NO_EFFECT" start="0" description="No effect." /> - <Enum name="DISABLE_JTAG_DEBUG" start="1" description="Disable JTAG debug. Once JTAG is disabled, JTAG access remains disabled until the chip is reset by any source." /> - </BitField> - <BitField start="11" size="1" name="M4TAPSEL" description="JTAG debug disable for M4 main processor. If this bit is set to 1, it can be changed to 0 only through a chip reset."> - <Enum name="NO_EFFECT" start="0" description="No effect." /> - <Enum name="DISABLE_JTAG_DEBUG" start="1" description="Disable JTAG debug. Once JTAG is disabled, JTAG access remains disabled until the chip is reset by any source." /> - </BitField> - <BitField start="12" size="1" name="M0APPTAPSEL" description="JTAG debug disable for M0APPco-processor. If this bit is set to 1, it can be changed to 0 only through a chip reset."> + <BitField start="0" size="11" name="RESERVED" description="Reserved." /> + <BitField start="11" size="1" name="M3TAPSEL" description="JTAG debug disable for M3 main processor. If this bit is set to 1, it can be changed to 0 only through a chip reset."> <Enum name="NO_EFFECT" start="0" description="No effect." /> <Enum name="DISABLE_JTAG_DEBUG" start="1" description="Disable JTAG debug. Once JTAG is disabled, JTAG access remains disabled until the chip is reset by any source." /> </BitField> - <BitField start="13" size="19" name="RESERVED" description="Reserved." /> + <BitField start="12" size="20" name="RESERVED" description="Reserved." /> </Register> <Register start="+0x11C" size="4" name="DMAMUX" access="Read/Write" description="DMA mux control" reset_value="0" reset_mask="0x00000000"> <BitField start="0" size="2" name="DMAMUXPER0" description="Select DMA to peripheral connection for DMA peripheral 0."> <Enum name="SPIFI" start="0x0" description="SPIFI" /> <Enum name="SCT_CTOUT_2" start="0x1" description="SCT CTOUT_2" /> - <Enum name="SGPIO14" start="0x2" description="SGPIO14" /> + <Enum name="RESERVED" start="0x2" description="Reserved" /> <Enum name="TIMER3_MATCH_1" start="0x3" description="Timer3 match 1" /> </BitField> <BitField start="2" size="2" name="DMAMUXPER1" description="Select DMA to peripheral connection for DMA peripheral 1"> @@ -10540,8 +10532,6 @@ <BitField start="4" size="2" name="DMAMUXPER2" description="Select DMA to peripheral connection for DMA peripheral 2."> <Enum name="TIMER0_MATCH_1" start="0x0" description="Timer0 match 1" /> <Enum name="USART0_RECEIVE" start="0x1" description="USART0 receive" /> - <Enum name="RESERVED" start="0x2" description="Reserved" /> - <Enum name="RESERVED" start="0x3" description="Reserved" /> </BitField> <BitField start="6" size="2" name="DMAMUXPER3" description="Select DMA to peripheral connection for DMA peripheral 3."> <Enum name="TIMER1_MATCH_0" start="0x0" description="Timer1 match 0" /> @@ -10559,82 +10549,68 @@ <Enum name="TIMER2_MATCH_0" start="0x0" description="Timer2 match 0" /> <Enum name="USART2_TRANSMIT" start="0x1" description="USART2 transmit" /> <Enum name="SSP1_TRANSMIT" start="0x2" description="SSP1 transmit" /> - <Enum name="SGPIO15" start="0x3" description="SGPIO15" /> </BitField> <BitField start="12" size="2" name="DMAMUXPER6" description="Selects DMA to peripheral connection for DMA peripheral 6."> <Enum name="TIMER2_MATCH_1" start="0x0" description="Timer2 match 1" /> <Enum name="USART2_RECEIVE" start="0x1" description="USART2 receive" /> <Enum name="SSP1_RECEIVE" start="0x2" description="SSP1 receive" /> - <Enum name="SGPIO14" start="0x3" description="SGPIO14" /> </BitField> <BitField start="14" size="2" name="DMAMUXPER7" description="Selects DMA to peripheral connection for DMA peripheral 7."> <Enum name="TIMER3_MATCH_0" start="0x0" description="Timer3 match 0" /> <Enum name="USART3_TRANSMIT" start="0x1" description="USART3 transmit" /> <Enum name="SCT_DMA_REQUEST_0" start="0x2" description="SCT DMA request 0" /> - <Enum name="ADCHS_WRITE" start="0x3" description="ADCHS write" /> </BitField> <BitField start="16" size="2" name="DMAMUXPER8" description="Select DMA to peripheral connection for DMA peripheral 8."> <Enum name="TIMER3_MATCH_1" start="0x0" description="Timer3 match 1" /> <Enum name="USART3_RECEIVE" start="0x1" description="USART3 receive" /> <Enum name="SCT_DMA_REQUEST_1" start="0x2" description="SCT DMA request 1" /> - <Enum name="ADCHS_READ" start="0x3" description="ADCHS read" /> </BitField> <BitField start="18" size="2" name="DMAMUXPER9" description="Select DMA to peripheral connection for DMA peripheral 9."> <Enum name="SSP0_RECEIVE" start="0x0" description="SSP0 receive" /> <Enum name="I2S0_DMA_REQUEST_1" start="0x1" description="I2S0 DMA request 1" /> <Enum name="SCT_DMA_REQUEST_1" start="0x2" description="SCT DMA request 1" /> - <Enum name="RESERVED" start="0x3" description="Reserved" /> </BitField> <BitField start="20" size="2" name="DMAMUXPER10" description="Select DMA to peripheral connection for DMA peripheral 10."> <Enum name="SSP0_TRANSMIT" start="0x0" description="SSP0 transmit" /> <Enum name="I2S0_DMA_REQUEST_2" start="0x1" description="I2S0 DMA request 2" /> <Enum name="SCT_DMA_REQUEST_0" start="0x2" description="SCT DMA request 0" /> - <Enum name="RESERVED" start="0x3" description="Reserved" /> </BitField> <BitField start="22" size="2" name="DMAMUXPER11" description="Selects DMA to peripheral connection for DMA peripheral 11."> <Enum name="SSP1_RECEIVE" start="0x0" description="SSP1 receive" /> - <Enum name="SGPIO14" start="0x1" description="SGPIO14" /> <Enum name="USART0_TRANSMIT" start="0x2" description="USART0 transmit" /> - <Enum name="RESERVED" start="0x3" description="Reserved" /> </BitField> <BitField start="24" size="2" name="DMAMUXPER12" description="Select DMA to peripheral connection for DMA peripheral 12."> <Enum name="SSP1_TRANSMIT" start="0x0" description="SSP1 transmit" /> - <Enum name="SGPIO15" start="0x1" description="SGPIO15" /> <Enum name="USART0_RECEIVE" start="0x2" description="USART0 receive" /> - <Enum name="RESERVED" start="0x3" description="Reserved" /> </BitField> <BitField start="26" size="2" name="DMAMUXPER13" description="Select DMA to peripheral connection for DMA peripheral 13."> <Enum name="ADC0" start="0x0" description="ADC0" /> - <Enum name="RESERVED" start="0x1" description="Reserved" /> <Enum name="SSP1_RECEIVE" start="0x2" description="SSP1 receive" /> <Enum name="USART3_RECEIVE" start="0x3" description="USART3 receive" /> </BitField> <BitField start="28" size="2" name="DMAMUXPER14" description="Select DMA to peripheral connection for DMA peripheral 14."> <Enum name="ADC1" start="0x0" description="ADC1" /> - <Enum name="RESERVED" start="0x1" description="Reserved" /> <Enum name="SSP1_TRANSMIT" start="0x2" description="SSP1 transmit" /> <Enum name="USART3_TRANSMIT" start="0x3" description="USART3 transmit" /> </BitField> <BitField start="30" size="2" name="DMAMUXPER15" description="Select DMA to peripheral connection for DMA peripheral 15."> <Enum name="DAC" start="0x0" description="DAC" /> <Enum name="SCT_CTOUT_3" start="0x1" description="SCT CTOUT_3" /> - <Enum name="SGPIO15" start="0x2" description="SGPIO15" /> <Enum name="TIMER3_MATCH_0" start="0x3" description="Timer3 match 0" /> </BitField> </Register> <Register start="+0x120" size="4" name="FLASHCFGA" access="Read/Write" description="Flash accelerator configuration register for flash bank A" reset_value="0x8000F03A" reset_mask="0xFFFFFFFF"> <BitField start="0" size="12" name="RESERVED" description="Reserved. Do not change these bits from the reset value." /> - <BitField start="12" size="4" name="FLASHTIM" description="Flash access time. The value of this field plus 1 gives the number of BASE_M4_CLK clocks used for a flash access. Warning: Improper setting of this value may result in incorrect operation of the device. All other values are allowed but may not be optimal for the supported clock frequencies."> - <Enum name="1_BASE_M4_CLK_CLOCK" start="0x0" description="1 BASE_M4_CLK clock. Use for BASE_M4_CLK up to 21 MHz." /> - <Enum name="2_BASE_M4_CLK_CLOCKS" start="0x1" description="2 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 43 MHz." /> - <Enum name="3_BASE_M4_CLK_CLOCKS" start="0x2" description="3 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 64 MHz." /> - <Enum name="4_BASE_M4_CLK_CLOCKS" start="0x3" description="4 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 86 MHz." /> - <Enum name="5_BASE_M4_CLK_CLOCKS" start="0x4" description="5 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 107 MHz." /> - <Enum name="6_BASE_M4_CLK_CLOCKS" start="0x5" description="6 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 129 MHz." /> - <Enum name="7_BASE_M4_CLK_CLOCKS" start="0x6" description="7 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 150 MHz." /> - <Enum name="8_BASE_M4_CLK_CLOCKS" start="0x7" description="8 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 172 MHz." /> - <Enum name="9_BASE_M4_CLK_CLOCKS" start="0x8" description="9 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 193 MHz." /> - <Enum name="10_BASE_M4_CLK_CLOCK" start="0x9" description="10 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 204 MHz. Safe setting for all allowed conditions." /> + <BitField start="12" size="4" name="FLASHTIM" description="Flash access time. The value of this field plus 1 gives the number of BASE_M3_CLK clocks used for a flash access. Warning: Improper setting of this value may result in incorrect operation of the device. All other values are allowed but may not be optimal for the supported clock frequencies."> + <Enum name="1_BASE_M3_CLK_CLOCK" start="0x0" description="1 BASE_M3_CLK clock. Use for BASE_M3_CLK up to 21 MHz." /> + <Enum name="2_BASE_M3_CLK_CLOCKS" start="0x1" description="2 BASE_M3_CLK clocks. Use for BASE_M3_CLK up to 43 MHz." /> + <Enum name="3_BASE_M3_CLK_CLOCKS" start="0x2" description="3 BASE_M3_CLK clocks. Use for BASE_M3_CLK up to 64 MHz." /> + <Enum name="4_BASE_M3_CLK_CLOCKS" start="0x3" description="4 BASE_M3_CLK clocks. Use for BASE_M3_CLK up to 86 MHz." /> + <Enum name="5_BASE_M3_CLK_CLOCKS" start="0x4" description="5 BASE_M3_CLK clocks. Use for BASE_M3_CLK up to 107 MHz." /> + <Enum name="6_BASE_M3_CLK_CLOCKS" start="0x5" description="6 BASE_M3_CLK clocks. Use for BASE_M3_CLK up to 129 MHz." /> + <Enum name="7_BASE_M3_CLK_CLOCKS" start="0x6" description="7 BASE_M3_CLK clocks. Use for BASE_M3_CLK up to 150 MHz." /> + <Enum name="8_BASE_M3_CLK_CLOCKS" start="0x7" description="8 BASE_M3_CLK clocks. Use for BASE_M3_CLK up to 172 MHz." /> + <Enum name="9_BASE_M3_CLK_CLOCKS" start="0x8" description="9 BASE_M3_CLK clocks. Use for BASE_M3_CLK up to 180 MHz." /> </BitField> <BitField start="16" size="15" name="RESERVED" description="Reserved. Write zeros only to these bits." /> <BitField start="31" size="1" name="POW" description="Flash bank A power control"> @@ -10644,17 +10620,16 @@ </Register> <Register start="+0x124" size="4" name="FLASHCFGB" access="Read/Write" description="Flash accelerator configuration register for flash bank B" reset_value="0x8000F03A" reset_mask="0xFFFFFFFF"> <BitField start="0" size="12" name="RESERVED" description="Reserved. Do not change these bits from the reset value." /> - <BitField start="12" size="4" name="FLASHTIM" description="Flash access time. The value of this field plus 1 gives the number of BASE_M4_CLK clocks used for a flash access. Warning: Improper setting of this value may result in incorrect operation of the device. All other values are allowed but may not be optimal for the supported clock frequencies."> - <Enum name="1_BASE_M4_CLK_CLOCK" start="0x0" description="1 BASE_M4_CLK clock. Use for BASE_M4_CLK up to 21 MHz." /> - <Enum name="2_BASE_M4_CLK_CLOCKS" start="0x1" description="2 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 43 MHz." /> - <Enum name="3_BASE_M4_CLK_CLOCKS" start="0x2" description="3 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 64 MHz." /> - <Enum name="4_BASE_M4_CLK_CLOCKS" start="0x3" description="4 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 86 MHz." /> - <Enum name="5_BASE_M4_CLK_CLOCKS" start="0x4" description="5 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 107 MHz." /> - <Enum name="6_BASE_M4_CLK_CLOCKS" start="0x5" description="6 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 129 MHz." /> - <Enum name="7_BASE_M4_CLK_CLOCKS" start="0x6" description="7 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 150 MHz." /> - <Enum name="8_BASE_M4_CLK_CLOCKS" start="0x7" description="8 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 172 MHz." /> - <Enum name="9_BASE_M4_CLK_CLOCKS" start="0x8" description="9 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 193 MHz." /> - <Enum name="10_BASE_M4_CLK_CLOCK" start="0x9" description="10 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 204 MHz. Safe setting for all allowed conditions." /> + <BitField start="12" size="4" name="FLASHTIM" description="Flash access time. The value of this field plus 1 gives the number of BASE_M3_CLK clocks used for a flash access. Warning: Improper setting of this value may result in incorrect operation of the device. All other values are allowed but may not be optimal for the supported clock frequencies."> + <Enum name="1_BASE_M3_CLK_CLOCK" start="0x0" description="1 BASE_M3_CLK clock. Use for BASE_M3_CLK up to 21 MHz." /> + <Enum name="2_BASE_M3_CLK_CLOCKS" start="0x1" description="2 BASE_M3_CLK clocks. Use for BASE_M3_CLK up to 43 MHz." /> + <Enum name="3_BASE_M3_CLK_CLOCKS" start="0x2" description="3 BASE_M3_CLK clocks. Use for BASE_M3_CLK up to 64 MHz." /> + <Enum name="4_BASE_M3_CLK_CLOCKS" start="0x3" description="4 BASE_M3_CLK clocks. Use for BASE_M3_CLK up to 86 MHz." /> + <Enum name="5_BASE_M3_CLK_CLOCKS" start="0x4" description="5 BASE_M3_CLK clocks. Use for BASE_M3_CLK up to 107 MHz." /> + <Enum name="6_BASE_M3_CLK_CLOCKS" start="0x5" description="6 BASE_M3_CLK clocks. Use for BASE_M3_CLK up to 129 MHz." /> + <Enum name="7_BASE_M3_CLK_CLOCKS" start="0x6" description="7 BASE_M3_CLK clocks. Use for BASE_M3_CLK up to 150 MHz." /> + <Enum name="8_BASE_M3_CLK_CLOCKS" start="0x7" description="8 BASE_M3_CLK clocks. Use for BASE_M3_CLK up to 172 MHz." /> + <Enum name="9_BASE_M3_CLK_CLOCKS" start="0x8" description="9 BASE_M3_CLK clocks. Use for BASE_M3_CLK up to 180 MHz." /> </BitField> <BitField start="16" size="15" name="RESERVED" description="Reserved. Write zeros only to these bits." /> <BitField start="31" size="1" name="POW" description="Flash bank A power control"> @@ -10702,37 +10677,10 @@ </BitField> <BitField start="17" size="15" name="RESERVED" description="Reserved." /> </Register> - <Register start="+0x130" size="4" name="M4TXEVENT" access="Read/Write" description="Cortex-M4 TXEV event clear" reset_value="0" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="1" name="TXEVCLR" description="Cortex-M4 TXEV event."> - <Enum name="CLEAR_THE_TXEV_EVENT" start="0" description="Clear the TXEV event." /> - <Enum name="NO_EFFECT" start="1" description="No effect." /> - </BitField> - <BitField start="1" size="31" name="RESERVED" description="Reserved." /> - </Register> <Register start="+0x200" size="4" name="CHIPID" access="ReadOnly" description="Part ID" reset_value="0" reset_mask="0x00000000"> - <BitField start="0" size="32" name="ID" description="Boundary scan ID code 0x5906 002B or 0x6906 002B = LPC4350/30/20/10 (flashless parts) 0x4906 002B = LPC4357/53 (parts with on-chip flash)" /> + <BitField start="0" size="32" name="ID" description="Boundary scan ID code 0x5284 E02B or 0x6284 E02B = LPC1850/30/20/10
					(flashless parts)
					0x4284 E02B = LPC1857/53 (parts with on-chip flash)" /> </Register> - <Register start="+0x308" size="4" name="M0SUBMEMMAP" access="Read/Write" description="ARM Cortex-M0SUB memory mapping" reset_value="0x18400000" reset_mask="0xFFFFFFFF"> - <BitField start="12" size="20" name="M0SUBMAP" description="Shadow address when accessing memory at address 0x0000 0000" /> - </Register> - <Register start="+0x314" size="4" name="M0SUBTXEVENT" access="Read/Write" description="Cortex-M0SUB TXEV event clear" reset_value="0" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="1" name="TXEVCLR" description="Cortex-M0SUB TXEV event handling."> - <Enum name="CLEAR_THE_TXEV_EVENT" start="0" description="Clear the TXEV event." /> - <Enum name="NO_EFFECT" start="1" description="No effect." /> - </BitField> - <BitField start="1" size="31" name="RESERVED" description="Reserved." /> - </Register> - <Register start="+0x400" size="4" name="M0APPTXEVENT" access="Read/Write" description="Cortex-M0APP TXEV event clear" reset_value="0" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="1" name="TXEVCLR" description="Cortex-M0APP TXEV event handling."> - <Enum name="CLEAR_THE_TXEV_EVENT" start="0" description="Clear the TXEV event." /> - <Enum name="NO_EFFECT" start="1" description="No effect." /> - </BitField> - <BitField start="1" size="31" name="RESERVED" description="Reserved." /> - </Register> - <Register start="+0x404" size="4" name="M0APPMEMMAP" access="Read/Write" description="ARM Cortex-M0APP memory mapping" reset_value="0x20000000" reset_mask="0xFFFFFFFF"> - <BitField start="12" size="20" name="M0APPMAP" description="Shadow address when accessing memory at address 0x0000 0000" /> - </Register> - <Register start="+0x500" size="4" name="USB0FLADJ" access="Read/Write" description="USB0 frame length adjust register" reset_value="0x20" reset_mask="0xFFFFFFFF"> + <Register start="+0x500" size="4" name="USB0FLADJ" access="None" description="USB0 frame length adjust register" reset_value="0x20" reset_mask="0xFFFFFFFF"> <BitField start="0" size="6" name="FLTV" description="Frame length timing value The frame length is given in the number of high-speed bit times in decimal format. Each decimal value change to this register corresponds to 16 high-speed bit times. The SOF cycle time (number of SOF counter clock periods to generate a SOF micro-frame length) is equal to 59488 + value in this field. The default value is decimal 32 (0x20), which results in a SOF cycle time of 60000. 0x00 = 59488 (= 59488 + 0 x 16) 0x01 = 59504 (= 59488 + 1 x 16) 0x02 = 59520 (= 59488 + 2 x 16) ... 0x1F = 59984 (= 59488 + 31 x 16) 0x20 = 60000 (= 59488 + 32 x 16) ... 0x3E = 60480 (= 59488 + 62 x 16) 0x3F = 60496 (= 59488 + 63 x 16)" /> <BitField start="6" size="26" name="RESERVED" description="Reserved" /> </Register> @@ -11778,7 +11726,7 @@ </BitField> <BitField start="29" size="3" name="RESERVED" description="Reserved" /> </Register> - <Register start="+0x06C" size="4" name="BASE_M4_CLK" access="Read/Write" description="Output stage BASE_M4_CLK control register" reset_value="0x01000000" reset_mask="0xFFFFFFFF"> + <Register start="+0x06C" size="4" name="BASE_M3_CLK" access="Read/Write" description="Output stage BASE_M3_CLK control register" reset_value="0x01000000" reset_mask="0xFFFFFFFF"> <BitField start="0" size="1" name="PD" description="Output stage power down"> <Enum name="OUTPUT_STAGE_ENABLED" start="0" description="Output stage enabled (default)" /> <Enum name="POWER_DOWN" start="1" description="power-down" /> @@ -11834,34 +11782,6 @@ </BitField> <BitField start="29" size="3" name="RESERVED" description="Reserved" /> </Register> - <Register start="+0x074" size="4" name="BASE_SPI_CLK" access="Read/Write" description="Output stage BASE_SPI_CLK control register" reset_value="0x01000000" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="1" name="PD" description="Output stage power down"> - <Enum name="OUTPUT_STAGE_ENABLED" start="0" description="Output stage enabled (default)" /> - <Enum name="POWER_DOWN" start="1" description="power-down" /> - </BitField> - <BitField start="1" size="10" name="RESERVED" description="Reserved" /> - <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change"> - <Enum name="DISABLED" start="0" description="Disabled. Autoblocking disabled" /> - <Enum name="ENABLED" start="1" description="Enabled. Autoblocking enabled" /> - </BitField> - <BitField start="12" size="12" name="RESERVED" description="Reserved" /> - <BitField start="24" size="5" name="CLK_SEL" description="Clock source selection. All other values are reserved."> - <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" /> - <Enum name="IRC_DEFAULT" start="0x01" description="IRC (default)" /> - <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" /> - <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" /> - <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" /> - <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" /> - <Enum name="PLL0_FOR_AUDIO" start="0x08" description="PLL0 (for audio)" /> - <Enum name="PLL1" start="0x09" description="PLL1" /> - <Enum name="IDIVA" start="0x0C" description="IDIVA" /> - <Enum name="IDIVB" start="0x0D" description="IDIVB" /> - <Enum name="IDIVC" start="0x0E" description="IDIVC" /> - <Enum name="IDIVD" start="0x0F" description="IDIVD" /> - <Enum name="IDIVE" start="0x10" description="IDIVE" /> - </BitField> - <BitField start="29" size="3" name="RESERVED" description="Reserved" /> - </Register> <Register start="+0x078" size="4" name="BASE_PHY_RX_CLK" access="Read/Write" description="Output stage BASE_PHY_RX_CLK control register" reset_value="0x01000000" reset_mask="0xFFFFFFFF"> <BitField start="0" size="1" name="PD" description="Output stage power down"> <Enum name="OUTPUT_STAGE_ENABLED" start="0" description="Output stage enabled (default)" /> @@ -12517,7 +12437,7 @@ </BitField> <BitField start="3" size="29" name="RESERVED" description="Reserved" /> </Register> - <Register start="+0x400" size="4" name="CLK_M4_BUS_CFG" access="Read/Write" description="CLK_M4_BUS clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF"> + <Register start="+0x400" size="4" name="CLK_M3_BUS_CFG" access="Read/Write" description="CLK_M3_BUS clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF"> <BitField start="0" size="1" name="RUN" description="Run enable"> <Enum name="DISABLED" start="0" description="Clock is disabled." /> <Enum name="ENABLED" start="1" description="Clock is enabled." /> @@ -12532,7 +12452,7 @@ </BitField> <BitField start="3" size="29" name="RESERVED" description="Reserved" /> </Register> - <Register start="+0x0408" size="4" name="CLK_M4_SPIFI_CFG" access="Read/Write" description="CLK_M4_SPIFI clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF"> + <Register start="+0x0408" size="4" name="CLK_M3_SPIFI_CFG" access="Read/Write" description="CLK_M3_SPIFI clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF"> <BitField start="0" size="1" name="RUN" description="Run enable"> <Enum name="DISABLED" start="0" description="Clock is disabled." /> <Enum name="ENABLED" start="1" description="Clock is enabled." /> @@ -12547,7 +12467,7 @@ </BitField> <BitField start="3" size="29" name="RESERVED" description="Reserved" /> </Register> - <Register start="+0x0410" size="4" name="CLK_M4_GPIO_CFG" access="Read/Write" description="CLK_M4_GPIO clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF"> + <Register start="+0x0410" size="4" name="CLK_M3_GPIO_CFG" access="Read/Write" description="CLK_M3_GPIO clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF"> <BitField start="0" size="1" name="RUN" description="Run enable"> <Enum name="DISABLED" start="0" description="Clock is disabled." /> <Enum name="ENABLED" start="1" description="Clock is enabled." /> @@ -12562,7 +12482,7 @@ </BitField> <BitField start="3" size="29" name="RESERVED" description="Reserved" /> </Register> - <Register start="+0x0418" size="4" name="CLK_M4_LCD_CFG" access="Read/Write" description="CLK_M4_LCD clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF"> + <Register start="+0x0418" size="4" name="CLK_M3_LCD_CFG" access="Read/Write" description="CLK_M3_LCD clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF"> <BitField start="0" size="1" name="RUN" description="Run enable"> <Enum name="DISABLED" start="0" description="Clock is disabled." /> <Enum name="ENABLED" start="1" description="Clock is enabled." /> @@ -12577,7 +12497,7 @@ </BitField> <BitField start="3" size="29" name="RESERVED" description="Reserved" /> </Register> - <Register start="+0x0420" size="4" name="CLK_M4_ETHERNET_CFG" access="Read/Write" description="CLK_M4_ETHERNET clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF"> + <Register start="+0x0420" size="4" name="CLK_M3_ETHERNET_CFG" access="Read/Write" description="CLK_M3_ETHERNET clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF"> <BitField start="0" size="1" name="RUN" description="Run enable"> <Enum name="DISABLED" start="0" description="Clock is disabled." /> <Enum name="ENABLED" start="1" description="Clock is enabled." /> @@ -12592,7 +12512,7 @@ </BitField> <BitField start="3" size="29" name="RESERVED" description="Reserved" /> </Register> - <Register start="+0x0428" size="4" name="CLK_M4_USB0_CFG" access="Read/Write" description="CLK_M4_USB0 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF"> + <Register start="+0x0428" size="4" name="CLK_M3_USB0_CFG" access="Read/Write" description="CLK_M3_USB0 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF"> <BitField start="0" size="1" name="RUN" description="Run enable"> <Enum name="DISABLED" start="0" description="Clock is disabled." /> <Enum name="ENABLED" start="1" description="Clock is enabled." /> @@ -12607,7 +12527,7 @@ </BitField> <BitField start="3" size="29" name="RESERVED" description="Reserved" /> </Register> - <Register start="+0x0430" size="4" name="CLK_M4_EMC_CFG" access="Read/Write" description="CLK_M4_EMC clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF"> + <Register start="+0x0430" size="4" name="CLK_M3_EMC_CFG" access="Read/Write" description="CLK_M3_EMC clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF"> <BitField start="0" size="1" name="RUN" description="Run enable"> <Enum name="DISABLED" start="0" description="Clock is disabled." /> <Enum name="ENABLED" start="1" description="Clock is enabled." /> @@ -12622,7 +12542,7 @@ </BitField> <BitField start="3" size="29" name="RESERVED" description="Reserved" /> </Register> - <Register start="+0x0438" size="4" name="CLK_M4_SDIO_CFG" access="Read/Write" description="CLK_M4_SDIO clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF"> + <Register start="+0x0438" size="4" name="CLK_M3_SDIO_CFG" access="Read/Write" description="CLK_M3_SDIO clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF"> <BitField start="0" size="1" name="RUN" description="Run enable"> <Enum name="DISABLED" start="0" description="Clock is disabled." /> <Enum name="ENABLED" start="1" description="Clock is enabled." /> @@ -12637,7 +12557,7 @@ </BitField> <BitField start="3" size="29" name="RESERVED" description="Reserved" /> </Register> - <Register start="+0x0440" size="4" name="CLK_M4_DMA_CFG" access="Read/Write" description="CLK_M4_DMA clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF"> + <Register start="+0x0440" size="4" name="CLK_M3_DMA_CFG" access="Read/Write" description="CLK_M3_DMA clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF"> <BitField start="0" size="1" name="RUN" description="Run enable"> <Enum name="DISABLED" start="0" description="Clock is disabled." /> <Enum name="ENABLED" start="1" description="Clock is enabled." /> @@ -12652,7 +12572,7 @@ </BitField> <BitField start="3" size="29" name="RESERVED" description="Reserved" /> </Register> - <Register start="+0x0448" size="4" name="CLK_M4_M4CORE_CFG" access="Read/Write" description="CLK_M4_M4CORE clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF"> + <Register start="+0x0448" size="4" name="CLK_M3_M3CORE_CFG" access="Read/Write" description="CLK_M3_M3CORE clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF"> <BitField start="0" size="1" name="RUN" description="Run enable"> <Enum name="DISABLED" start="0" description="Clock is disabled." /> <Enum name="ENABLED" start="1" description="Clock is enabled." /> @@ -12667,7 +12587,7 @@ </BitField> <BitField start="3" size="29" name="RESERVED" description="Reserved" /> </Register> - <Register start="+0x0468" size="4" name="CLK_M4_SCT_CFG" access="Read/Write" description="CLK_M4_SCT clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF"> + <Register start="+0x0468" size="4" name="CLK_M3_SCT_CFG" access="Read/Write" description="CLK_M3_SCT clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF"> <BitField start="0" size="1" name="RUN" description="Run enable"> <Enum name="DISABLED" start="0" description="Clock is disabled." /> <Enum name="ENABLED" start="1" description="Clock is enabled." /> @@ -12682,7 +12602,7 @@ </BitField> <BitField start="3" size="29" name="RESERVED" description="Reserved" /> </Register> - <Register start="+0x0470" size="4" name="CLK_M4_USB1_CFG" access="Read/Write" description="CLK_M4_USB1 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF"> + <Register start="+0x0470" size="4" name="CLK_M3_USB1_CFG" access="Read/Write" description="CLK_M3_USB1 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF"> <BitField start="0" size="1" name="RUN" description="Run enable"> <Enum name="DISABLED" start="0" description="Clock is disabled." /> <Enum name="ENABLED" start="1" description="Clock is enabled." /> @@ -12697,7 +12617,7 @@ </BitField> <BitField start="3" size="29" name="RESERVED" description="Reserved" /> </Register> - <Register start="+0x0478" size="4" name="CLK_M4_EMCDIV_CFG" access="Read/Write" description="CLK_M4_EMCDIV clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF"> + <Register start="+0x0478" size="4" name="CLK_M3_EMCDIV_CFG" access="Read/Write" description="CLK_M3_EMCDIV clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF"> <BitField start="0" size="1" name="RUN" description="Run enable"> <Enum name="DISABLED" start="0" description="Clock is disabled." /> <Enum name="ENABLED" start="1" description="Clock is enabled." /> @@ -12717,52 +12637,7 @@ </BitField> <BitField start="8" size="24" name="RESERVED" description="Reserved" /> </Register> - <Register start="+0x0480" size="4" name="CLK_M4_FLASHA_CFG" access="Read/Write" description="CLK_M4_FLASHA clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="1" name="RUN" description="Run enable"> - <Enum name="DISABLED" start="0" description="Clock is disabled." /> - <Enum name="ENABLED" start="1" description="Clock is enabled." /> - </BitField> - <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable"> - <Enum name="DISABLED_" start="0" description="Auto is disabled." /> - <Enum name="ENABLED" start="1" description="Auto is enabled." /> - </BitField> - <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable"> - <Enum name="DISABLED" start="0" description="Wake-up is disabled." /> - <Enum name="ENABLED" start="1" description="Wake-up is enabled." /> - </BitField> - <BitField start="3" size="29" name="RESERVED" description="Reserved" /> - </Register> - <Register start="+0x0488" size="4" name="CLK_M4_FLASHB_CFG" access="Read/Write" description="CLK_M4_FLASHB clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="1" name="RUN" description="Run enable"> - <Enum name="DISABLED" start="0" description="Clock is disabled." /> - <Enum name="ENABLED" start="1" description="Clock is enabled." /> - </BitField> - <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable"> - <Enum name="DISABLED_" start="0" description="Auto is disabled." /> - <Enum name="ENABLED" start="1" description="Auto is enabled." /> - </BitField> - <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable"> - <Enum name="DISABLED" start="0" description="Wake-up is disabled." /> - <Enum name="ENABLED" start="1" description="Wake-up is enabled." /> - </BitField> - <BitField start="3" size="29" name="RESERVED" description="Reserved" /> - </Register> - <Register start="+0x0490" size="4" name="CLK_M4_M0APP_CFG" access="Read/Write" description="CLK_M0APP_CFG clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="1" name="RUN" description="Run enable"> - <Enum name="DISABLED" start="0" description="Clock is disabled." /> - <Enum name="ENABLED" start="1" description="Clock is enabled." /> - </BitField> - <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable"> - <Enum name="DISABLED_" start="0" description="Auto is disabled." /> - <Enum name="ENABLED" start="1" description="Auto is enabled." /> - </BitField> - <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable"> - <Enum name="DISABLED" start="0" description="Wake-up is disabled." /> - <Enum name="ENABLED" start="1" description="Wake-up is enabled." /> - </BitField> - <BitField start="3" size="29" name="RESERVED" description="Reserved" /> - </Register> - <Register start="+0x0498" size="4" name="CLK_M4_ADCHS_CFG" access="Read/Write" description="CLK_ADCHS_CFG clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF"> + <Register start="+0x0480" size="4" name="CLK_M3_FLASHA_CFG" access="Read/Write" description="CLK_M3_FLASHA clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF"> <BitField start="0" size="1" name="RUN" description="Run enable"> <Enum name="DISABLED" start="0" description="Clock is disabled." /> <Enum name="ENABLED" start="1" description="Clock is enabled." /> @@ -12777,7 +12652,7 @@ </BitField> <BitField start="3" size="29" name="RESERVED" description="Reserved" /> </Register> - <Register start="+0x04A0" size="4" name="CLK_M4_EEPROM_CFG" access="Read/Write" description="CLK_EEPROM_CFG clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF"> + <Register start="+0x0488" size="4" name="CLK_M3_FLASHB_CFG" access="Read/Write" description="CLK_M3_FLASHB clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF"> <BitField start="0" size="1" name="RUN" description="Run enable"> <Enum name="DISABLED" start="0" description="Clock is disabled." /> <Enum name="ENABLED" start="1" description="Clock is enabled." /> @@ -12792,7 +12667,7 @@ </BitField> <BitField start="3" size="29" name="RESERVED" description="Reserved" /> </Register> - <Register start="+0x500" size="4" name="CLK_M4_WWDT_CFG" access="Read/Write" description="CLK_M4_WWDT clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF"> + <Register start="+0x04A0" size="4" name="CLK_M3_EEPROM_CFG" access="Read/Write" description="CLK_EEPROM_CFG clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF"> <BitField start="0" size="1" name="RUN" description="Run enable"> <Enum name="DISABLED" start="0" description="Clock is disabled." /> <Enum name="ENABLED" start="1" description="Clock is enabled." /> @@ -12807,7 +12682,7 @@ </BitField> <BitField start="3" size="29" name="RESERVED" description="Reserved" /> </Register> - <Register start="+0x0508" size="4" name="CLK_M4_USART0_CFG" access="Read/Write" description="CLK_M4_USART0 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF"> + <Register start="+0x500" size="4" name="CLK_M3_WWDT_CFG" access="Read/Write" description="CLK_M3_WWDT clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF"> <BitField start="0" size="1" name="RUN" description="Run enable"> <Enum name="DISABLED" start="0" description="Clock is disabled." /> <Enum name="ENABLED" start="1" description="Clock is enabled." /> @@ -12822,7 +12697,7 @@ </BitField> <BitField start="3" size="29" name="RESERVED" description="Reserved" /> </Register> - <Register start="+0x0510" size="4" name="CLK_M4_UART1_CFG" access="Read/Write" description="CLK_M4_UART1 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF"> + <Register start="+0x0508" size="4" name="CLK_M3_USART0_CFG" access="Read/Write" description="CLK_M3_USART0 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF"> <BitField start="0" size="1" name="RUN" description="Run enable"> <Enum name="DISABLED" start="0" description="Clock is disabled." /> <Enum name="ENABLED" start="1" description="Clock is enabled." /> @@ -12837,7 +12712,7 @@ </BitField> <BitField start="3" size="29" name="RESERVED" description="Reserved" /> </Register> - <Register start="+0x0518" size="4" name="CLK_M4_SSP0_CFG" access="Read/Write" description="CLK_M4_SSP0 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF"> + <Register start="+0x0510" size="4" name="CLK_M3_UART1_CFG" access="Read/Write" description="CLK_M3_UART1 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF"> <BitField start="0" size="1" name="RUN" description="Run enable"> <Enum name="DISABLED" start="0" description="Clock is disabled." /> <Enum name="ENABLED" start="1" description="Clock is enabled." /> @@ -12852,7 +12727,7 @@ </BitField> <BitField start="3" size="29" name="RESERVED" description="Reserved" /> </Register> - <Register start="+0x0520" size="4" name="CLK_M4_TIMER0_CFG" access="Read/Write" description="CLK_M4_TIMER0 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF"> + <Register start="+0x0518" size="4" name="CLK_M3_SSP0_CFG" access="Read/Write" description="CLK_M3_SSP0 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF"> <BitField start="0" size="1" name="RUN" description="Run enable"> <Enum name="DISABLED" start="0" description="Clock is disabled." /> <Enum name="ENABLED" start="1" description="Clock is enabled." /> @@ -12867,7 +12742,7 @@ </BitField> <BitField start="3" size="29" name="RESERVED" description="Reserved" /> </Register> - <Register start="+0x0528" size="4" name="CLK_M4_TIMER1_CFG" access="Read/Write" description="CLK_M4_TIMER1clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF"> + <Register start="+0x0520" size="4" name="CLK_M3_TIMER0_CFG" access="Read/Write" description="CLK_M3_TIMER0 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF"> <BitField start="0" size="1" name="RUN" description="Run enable"> <Enum name="DISABLED" start="0" description="Clock is disabled." /> <Enum name="ENABLED" start="1" description="Clock is enabled." /> @@ -12882,7 +12757,7 @@ </BitField> <BitField start="3" size="29" name="RESERVED" description="Reserved" /> </Register> - <Register start="+0x0530" size="4" name="CLK_M4_SCU_CFG" access="Read/Write" description="CLK_M4_SCU clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF"> + <Register start="+0x0528" size="4" name="CLK_M3_TIMER1_CFG" access="Read/Write" description="CLK_M3_TIMER1clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF"> <BitField start="0" size="1" name="RUN" description="Run enable"> <Enum name="DISABLED" start="0" description="Clock is disabled." /> <Enum name="ENABLED" start="1" description="Clock is enabled." /> @@ -12897,7 +12772,7 @@ </BitField> <BitField start="3" size="29" name="RESERVED" description="Reserved" /> </Register> - <Register start="+0x0538" size="4" name="CLK_M4_CREG_CFG" access="Read/Write" description="CLK_M4_CREGclock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF"> + <Register start="+0x0530" size="4" name="CLK_M3_SCU_CFG" access="Read/Write" description="CLK_M3_SCU clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF"> <BitField start="0" size="1" name="RUN" description="Run enable"> <Enum name="DISABLED" start="0" description="Clock is disabled." /> <Enum name="ENABLED" start="1" description="Clock is enabled." /> @@ -12912,7 +12787,7 @@ </BitField> <BitField start="3" size="29" name="RESERVED" description="Reserved" /> </Register> - <Register start="+0x600" size="4" name="CLK_M4_RITIMER_CFG" access="Read/Write" description="CLK_M4_RITIMER clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF"> + <Register start="+0x0538" size="4" name="CLK_M3_CREG_CFG" access="Read/Write" description="CLK_M3_CREG clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF"> <BitField start="0" size="1" name="RUN" description="Run enable"> <Enum name="DISABLED" start="0" description="Clock is disabled." /> <Enum name="ENABLED" start="1" description="Clock is enabled." /> @@ -12927,7 +12802,7 @@ </BitField> <BitField start="3" size="29" name="RESERVED" description="Reserved" /> </Register> - <Register start="+0x0608" size="4" name="CLK_M4_USART2_CFG" access="Read/Write" description="CLK_M4_USART2 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF"> + <Register start="+0x600" size="4" name="CLK_M3_RITIMER_CFG" access="Read/Write" description="CLK_M3_RITIMER clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF"> <BitField start="0" size="1" name="RUN" description="Run enable"> <Enum name="DISABLED" start="0" description="Clock is disabled." /> <Enum name="ENABLED" start="1" description="Clock is enabled." /> @@ -12942,7 +12817,7 @@ </BitField> <BitField start="3" size="29" name="RESERVED" description="Reserved" /> </Register> - <Register start="+0x0610" size="4" name="CLK_M4_USART3_CFG" access="Read/Write" description="CLK_M4_USART3 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF"> + <Register start="+0x0608" size="4" name="CLK_M3_USART2_CFG" access="Read/Write" description="CLK_M3_USART2 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF"> <BitField start="0" size="1" name="RUN" description="Run enable"> <Enum name="DISABLED" start="0" description="Clock is disabled." /> <Enum name="ENABLED" start="1" description="Clock is enabled." /> @@ -12957,7 +12832,7 @@ </BitField> <BitField start="3" size="29" name="RESERVED" description="Reserved" /> </Register> - <Register start="+0x0618" size="4" name="CLK_M4_TIMER2_CFG" access="Read/Write" description="CLK_M4_TIMER2 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF"> + <Register start="+0x0610" size="4" name="CLK_M3_USART3_CFG" access="Read/Write" description="CLK_M3_USART3 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF"> <BitField start="0" size="1" name="RUN" description="Run enable"> <Enum name="DISABLED" start="0" description="Clock is disabled." /> <Enum name="ENABLED" start="1" description="Clock is enabled." /> @@ -12972,7 +12847,7 @@ </BitField> <BitField start="3" size="29" name="RESERVED" description="Reserved" /> </Register> - <Register start="+0x0620" size="4" name="CLK_M4_TIMER3_CFG" access="Read/Write" description="CLK_M4_TIMER3 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF"> + <Register start="+0x0618" size="4" name="CLK_M3_TIMER2_CFG" access="Read/Write" description="CLK_M3_TIMER2 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF"> <BitField start="0" size="1" name="RUN" description="Run enable"> <Enum name="DISABLED" start="0" description="Clock is disabled." /> <Enum name="ENABLED" start="1" description="Clock is enabled." /> @@ -12987,7 +12862,7 @@ </BitField> <BitField start="3" size="29" name="RESERVED" description="Reserved" /> </Register> - <Register start="+0x0628" size="4" name="CLK_M4_SSP1_CFG" access="Read/Write" description="CLK_M4_SSP1 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF"> + <Register start="+0x0620" size="4" name="CLK_M3_TIMER3_CFG" access="Read/Write" description="CLK_M3_TIMER3 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF"> <BitField start="0" size="1" name="RUN" description="Run enable"> <Enum name="DISABLED" start="0" description="Clock is disabled." /> <Enum name="ENABLED" start="1" description="Clock is enabled." /> @@ -13002,7 +12877,7 @@ </BitField> <BitField start="3" size="29" name="RESERVED" description="Reserved" /> </Register> - <Register start="+0x0630" size="4" name="CLK_M4_QEI_CFG" access="Read/Write" description="CLK_M4_QEIclock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF"> + <Register start="+0x0628" size="4" name="CLK_M3_SSP1_CFG" access="Read/Write" description="CLK_M3_SSP1 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF"> <BitField start="0" size="1" name="RUN" description="Run enable"> <Enum name="DISABLED" start="0" description="Clock is disabled." /> <Enum name="ENABLED" start="1" description="Clock is enabled." /> @@ -13017,7 +12892,7 @@ </BitField> <BitField start="3" size="29" name="RESERVED" description="Reserved" /> </Register> - <Register start="+0x0700" size="4" name="CLK_PERIPH_BUS_CFG" access="Read/Write" description="CLK_PERIPH_BUS_CFG clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF"> + <Register start="+0x0630" size="4" name="CLK_M3_QEI_CFG" access="Read/Write" description="CLK_M3_QEIclock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF"> <BitField start="0" size="1" name="RUN" description="Run enable"> <Enum name="DISABLED" start="0" description="Clock is disabled." /> <Enum name="ENABLED" start="1" description="Clock is enabled." /> @@ -13032,37 +12907,7 @@ </BitField> <BitField start="3" size="29" name="RESERVED" description="Reserved" /> </Register> - <Register start="+0x0710" size="4" name="CLK_PERIPH_CORE_CFG" access="Read/Write" description="CLK_PERIPH_CORE_CFG clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="1" name="RUN" description="Run enable"> - <Enum name="DISABLED" start="0" description="Clock is disabled." /> - <Enum name="ENABLED" start="1" description="Clock is enabled." /> - </BitField> - <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable"> - <Enum name="DISABLED_" start="0" description="Auto is disabled." /> - <Enum name="ENABLED" start="1" description="Auto is enabled." /> - </BitField> - <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable"> - <Enum name="DISABLED" start="0" description="Wake-up is disabled." /> - <Enum name="ENABLED" start="1" description="Wake-up is enabled." /> - </BitField> - <BitField start="3" size="29" name="RESERVED" description="Reserved" /> - </Register> - <Register start="+0x0718" size="4" name="CLK_PERIPH_SGPIO_CFG" access="Read/Write" description="CLK_PERIPH_SGPIO_CFG clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="1" name="RUN" description="Run enable"> - <Enum name="DISABLED" start="0" description="Clock is disabled." /> - <Enum name="ENABLED" start="1" description="Clock is enabled." /> - </BitField> - <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable"> - <Enum name="DISABLED_" start="0" description="Auto is disabled." /> - <Enum name="ENABLED" start="1" description="Auto is enabled." /> - </BitField> - <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable"> - <Enum name="DISABLED" start="0" description="Wake-up is disabled." /> - <Enum name="ENABLED" start="1" description="Wake-up is enabled." /> - </BitField> - <BitField start="3" size="29" name="RESERVED" description="Reserved" /> - </Register> - <Register start="+0x800" size="4" name="CLK_USB0_CFG" access="Read/Write" description="CLK_M4_USB0 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF"> + <Register start="+0x800" size="4" name="CLK_USB0_CFG" access="Read/Write" description="CLK_USB0 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF"> <BitField start="0" size="1" name="RUN" description="Run enable"> <Enum name="DISABLED" start="0" description="Clock is disabled." /> <Enum name="ENABLED" start="1" description="Clock is enabled." /> @@ -13092,36 +12937,6 @@ </BitField> <BitField start="3" size="29" name="RESERVED" description="Reserved" /> </Register> - <Register start="+0xA00" size="4" name="CLK_SPI_CFG" access="Read/Write" description="CLK_SPI clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="1" name="RUN" description="Run enable"> - <Enum name="DISABLED" start="0" description="Clock is disabled." /> - <Enum name="ENABLED" start="1" description="Clock is enabled." /> - </BitField> - <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable"> - <Enum name="AUTO_IS_DISABLED_" start="0" description="Auto is disabled." /> - <Enum name="AUTO_IS_ENABLED_" start="1" description="Auto is enabled." /> - </BitField> - <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable"> - <Enum name="WAKE_UP_IS_DISABLED_" start="0" description="Wake-up is disabled." /> - <Enum name="WAKE_UP_IS_ENABLED_" start="1" description="Wake-up is enabled." /> - </BitField> - <BitField start="3" size="29" name="RESERVED" description="Reserved" /> - </Register> - <Register start="+0xB00" size="4" name="CLK_ADCHS_CFG" access="Read/Write" description="CLK_ADCHS clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="1" name="RUN" description="Run enable"> - <Enum name="DISABLED" start="0" description="Clock is disabled." /> - <Enum name="ENABLED" start="1" description="Clock is enabled." /> - </BitField> - <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable"> - <Enum name="AUTO_IS_DISABLED_" start="0" description="Auto is disabled." /> - <Enum name="AUTO_IS_ENABLED_" start="1" description="Auto is enabled." /> - </BitField> - <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable"> - <Enum name="WAKE_UP_IS_DISABLED_" start="0" description="Wake-up is disabled." /> - <Enum name="WAKE_UP_IS_ENABLED_" start="1" description="Wake-up is enabled." /> - </BitField> - <BitField start="3" size="29" name="RESERVED" description="Reserved" /> - </Register> <Register start="+0x104" size="4" name="CLK_APB3_BUS_STAT" access="ReadOnly" description="CLK_APB3_BUS clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF"> <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." /> <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." /> @@ -13194,217 +13009,192 @@ <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." /> <BitField start="3" size="29" name="RESERVED" description="Reserved" /> </Register> - <Register start="+0x404" size="4" name="CLK_M4_BUS_STAT" access="ReadOnly" description="CLK_M4_BUSclock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF"> + <Register start="+0x404" size="4" name="CLK_M3_BUS_STAT" access="ReadOnly" description="CLK_M4_BUSclock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF"> <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." /> <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." /> <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." /> <BitField start="3" size="29" name="RESERVED" description="Reserved" /> </Register> - <Register start="+0x040C" size="4" name="CLK_M4_SPIFI_STAT" access="ReadOnly" description="CLK_M4_SPIFI clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF"> + <Register start="+0x040C" size="4" name="CLK_M3_SPIFI_STAT" access="ReadOnly" description="CLK_M3_SPIFI clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF"> <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." /> <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." /> <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." /> <BitField start="3" size="29" name="RESERVED" description="Reserved" /> </Register> - <Register start="+0x0414" size="4" name="CLK_M4_GPIO_STAT" access="ReadOnly" description="CLK_M4_GPIO clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF"> + <Register start="+0x0414" size="4" name="CLK_M3_GPIO_STAT" access="ReadOnly" description="CLK_M3_GPIO clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF"> <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." /> <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." /> <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." /> <BitField start="3" size="29" name="RESERVED" description="Reserved" /> </Register> - <Register start="+0x041C" size="4" name="CLK_M4_LCD_STAT" access="ReadOnly" description="CLK_M4_LCD clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF"> + <Register start="+0x041C" size="4" name="CLK_M3_LCD_STAT" access="ReadOnly" description="CLK_M3_LCD clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF"> <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." /> <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." /> <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." /> <BitField start="3" size="29" name="RESERVED" description="Reserved" /> </Register> - <Register start="+0x0424" size="4" name="CLK_M4_ETHERNET_STAT" access="ReadOnly" description="CLK_M4_ETHERNET clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF"> + <Register start="+0x0424" size="4" name="CLK_M3_ETHERNET_STAT" access="ReadOnly" description="CLK_M3_ETHERNET clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF"> <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." /> <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." /> <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." /> <BitField start="3" size="29" name="RESERVED" description="Reserved" /> </Register> - <Register start="+0x042C" size="4" name="CLK_M4_USB0_STAT" access="ReadOnly" description="CLK_M4_USB0 clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF"> + <Register start="+0x042C" size="4" name="CLK_M3_USB0_STAT" access="ReadOnly" description="CLK_M3_USB0 clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF"> <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." /> <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." /> <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." /> <BitField start="3" size="29" name="RESERVED" description="Reserved" /> </Register> - <Register start="+0x0434" size="4" name="CLK_M4_EMC_STAT" access="ReadOnly" description="CLK_M4_EMC clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF"> + <Register start="+0x0434" size="4" name="CLK_M3_EMC_STAT" access="ReadOnly" description="CLK_M3_EMC clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF"> <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." /> <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." /> <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." /> <BitField start="3" size="29" name="RESERVED" description="Reserved" /> </Register> - <Register start="+0x043C" size="4" name="CLK_M4_SDIO_STAT" access="ReadOnly" description="CLK_M4_SDIO clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF"> + <Register start="+0x043C" size="4" name="CLK_M3_SDIO_STAT" access="ReadOnly" description="CLK_M3_SDIO clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF"> <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." /> <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." /> <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." /> <BitField start="3" size="29" name="RESERVED" description="Reserved" /> </Register> - <Register start="+0x0444" size="4" name="CLK_M4_DMA_STAT" access="ReadOnly" description="CLK_M4_DMA clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF"> + <Register start="+0x0444" size="4" name="CLK_M3_DMA_STAT" access="ReadOnly" description="CLK_M3_DMA clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF"> <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." /> <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." /> <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." /> <BitField start="3" size="29" name="RESERVED" description="Reserved" /> </Register> - <Register start="+0x044C" size="4" name="CLK_M4_M4CORE_STAT" access="ReadOnly" description="CLK_M4_M3CORE clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF"> + <Register start="+0x044C" size="4" name="CLK_M3_M3CORE_STAT" access="ReadOnly" description="CLK_M3_M3CORE clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF"> <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." /> <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." /> <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." /> <BitField start="3" size="29" name="RESERVED" description="Reserved" /> </Register> - <Register start="+0x046C" size="4" name="CLK_M4_SCT_STAT" access="ReadOnly" description="CLK_M4_SCT clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF"> + <Register start="+0x046C" size="4" name="CLK_M3_SCT_STAT" access="ReadOnly" description="CLK_M3_SCT clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF"> <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." /> <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." /> <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." /> <BitField start="3" size="29" name="RESERVED" description="Reserved" /> </Register> - <Register start="+0x0474" size="4" name="CLK_M4_USB1_STAT" access="ReadOnly" description="CLK_M4_USB1 clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF"> + <Register start="+0x0474" size="4" name="CLK_M3_USB1_STAT" access="ReadOnly" description="CLK_M3_USB1 clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF"> <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." /> <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." /> <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." /> <BitField start="3" size="29" name="RESERVED" description="Reserved" /> </Register> - <Register start="+0x047C" size="4" name="CLK_M4_EMCDIV_STAT" access="ReadOnly" description="CLK_M4_EMCDIV clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF"> + <Register start="+0x047C" size="4" name="CLK_M3_EMCDIV_STAT" access="ReadOnly" description="CLK_M3_EMCDIV clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF"> <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." /> <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." /> <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." /> - <BitField start="3" size="29" name="RESERVED" description="Reserved" /> - </Register> - <Register start="+0x0484" size="4" name="CLK_M4_FLASHA_STAT" access="ReadOnly" description="CLK_M4_FLASHA clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." /> - <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." /> - <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." /> - <BitField start="3" size="29" name="RESERVED" description="Reserved" /> - </Register> - <Register start="+0x048C" size="4" name="CLK_M4_FLASHB_STAT" access="ReadOnly" description="CLK_M4_FLASHB clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." /> - <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." /> - <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." /> - <BitField start="3" size="29" name="RESERVED" description="Reserved" /> - </Register> - <Register start="+0x0494" size="4" name="CLK_M4_M0APP_STAT" access="ReadOnly" description="CLK_M4_MOAPP clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." /> - <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." /> - <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." /> - <BitField start="3" size="29" name="RESERVED" description="Reserved" /> - </Register> - <Register start="+0x049C" size="4" name="CLK_M4_ADCHS_STAT" access="ReadOnly" description="CLK_M4_ADCHS clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." /> - <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." /> - <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." /> - <BitField start="3" size="29" name="RESERVED" description="Reserved" /> - </Register> - <Register start="+0x04A4" size="4" name="CLK_M4_EEPROM_STAT" access="ReadOnly" description="CLK_M4_EEPROM clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." /> - <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." /> - <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." /> - <BitField start="3" size="29" name="RESERVED" description="Reserved" /> + <BitField start="3" size="2" name="RESERVED" description="Reserved" /> + <BitField start="5" size="3" name="DIV" description="Clock divider value"> + <Enum name="DIVIDEBY1" start="0x0" description="No division. Divide by 1." /> + <Enum name="DIVIDEBY2" start="0x1" description="Divide by 2." /> + </BitField> + <BitField start="8" size="24" name="RESERVED" description="Reserved" /> </Register> - <Register start="+0x504" size="4" name="CLK_M4_WWDT_STAT" access="ReadOnly" description="CLK_M4_WWDT clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF"> + <Register start="+0x0484" size="4" name="CLK_M3_FLASHA_STAT" access="ReadOnly" description="CLK_M3_FLASHA clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF"> <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." /> <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." /> <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." /> <BitField start="3" size="29" name="RESERVED" description="Reserved" /> </Register> - <Register start="+0x050C" size="4" name="CLK_M4_USART0_STAT" access="ReadOnly" description="CLK_M4_USART0 clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF"> + <Register start="+0x048C" size="4" name="CLK_M3_FLASHB_STAT" access="ReadOnly" description="CLK_M3_FLASHB clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF"> <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." /> <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." /> <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." /> <BitField start="3" size="29" name="RESERVED" description="Reserved" /> </Register> - <Register start="+0x0514" size="4" name="CLK_M4_UART1_STAT" access="ReadOnly" description="CLK_M4_UART1 clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF"> + <Register start="+0x04A4" size="4" name="CLK_M3_EEPROM_STAT" access="ReadOnly" description="CLK_M3_EEPROM clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF"> <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." /> <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." /> <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." /> <BitField start="3" size="29" name="RESERVED" description="Reserved" /> </Register> - <Register start="+0x051C" size="4" name="CLK_M4_SSP0_STAT" access="ReadOnly" description="CLK_M4_SSP0 clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF"> + <Register start="+0x504" size="4" name="CLK_M3_WWDT_STAT" access="ReadOnly" description="CLK_M3_WWDT clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF"> <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." /> <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." /> <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." /> <BitField start="3" size="29" name="RESERVED" description="Reserved" /> </Register> - <Register start="+0x0524" size="4" name="CLK_M4_TIMER0_STAT" access="ReadOnly" description="CLK_M4_TIMER0 clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF"> + <Register start="+0x050C" size="4" name="CLK_M3_USART0_STAT" access="ReadOnly" description="CLK_M3_USART0 clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF"> <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." /> <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." /> <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." /> <BitField start="3" size="29" name="RESERVED" description="Reserved" /> </Register> - <Register start="+0x052C" size="4" name="CLK_M4_TIMER1_STAT" access="ReadOnly" description="CLK_M4_TIMER1 clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF"> + <Register start="+0x0514" size="4" name="CLK_M3_UART1_STAT" access="ReadOnly" description="CLK_M3_UART1 clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF"> <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." /> <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." /> <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." /> <BitField start="3" size="29" name="RESERVED" description="Reserved" /> </Register> - <Register start="+0x0534" size="4" name="CLK_M4_SCU_STAT" access="ReadOnly" description="CLK_SCU_XXX clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF"> + <Register start="+0x051C" size="4" name="CLK_M3_SSP0_STAT" access="ReadOnly" description="CLK_M3_SSP0 clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF"> <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." /> <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." /> <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." /> <BitField start="3" size="29" name="RESERVED" description="Reserved" /> </Register> - <Register start="+0x053C" size="4" name="CLK_M4_CREG_STAT" access="ReadOnly" description="CLK_M4_CREG clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF"> + <Register start="+0x0524" size="4" name="CLK_M3_TIMER0_STAT" access="ReadOnly" description="CLK_M3_TIMER0 clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF"> <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." /> <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." /> <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." /> <BitField start="3" size="29" name="RESERVED" description="Reserved" /> </Register> - <Register start="+0x604" size="4" name="CLK_M4_RITIMER_STAT" access="ReadOnly" description="CLK_M4_RITIMER clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF"> + <Register start="+0x052C" size="4" name="CLK_M3_TIMER1_STAT" access="ReadOnly" description="CLK_M3_TIMER1 clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF"> <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." /> <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." /> <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." /> <BitField start="3" size="29" name="RESERVED" description="Reserved" /> </Register> - <Register start="+0x060C" size="4" name="CLK_M4_USART2_STAT" access="ReadOnly" description="CLK_M4_USART2 clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF"> + <Register start="+0x0534" size="4" name="CLK_M3_SCU_STAT" access="ReadOnly" description="CLK_SCU_XXX clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF"> <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." /> <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." /> <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." /> <BitField start="3" size="29" name="RESERVED" description="Reserved" /> </Register> - <Register start="+0x0614" size="4" name="CLK_M4_USART3_STAT" access="ReadOnly" description="CLK_M4_USART3 clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF"> + <Register start="+0x053C" size="4" name="CLK_M3_CREG_STAT" access="ReadOnly" description="CLK_M3_CREG clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF"> <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." /> <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." /> <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." /> <BitField start="3" size="29" name="RESERVED" description="Reserved" /> </Register> - <Register start="+0x061C" size="4" name="CLK_M4_TIMER2_STAT" access="ReadOnly" description="CLK_M4_TIMER2 clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF"> + <Register start="+0x604" size="4" name="CLK_M3_RITIMER_STAT" access="ReadOnly" description="CLK_M3_RITIMER clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF"> <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." /> <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." /> <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." /> <BitField start="3" size="29" name="RESERVED" description="Reserved" /> </Register> - <Register start="+0x0624" size="4" name="CLK_M4_TIMER3_STAT" access="ReadOnly" description="CLK_M4_TIMER3 clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF"> + <Register start="+0x060C" size="4" name="CLK_M3_USART2_STAT" access="ReadOnly" description="CLK_M3_USART2 clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF"> <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." /> <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." /> <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." /> <BitField start="3" size="29" name="RESERVED" description="Reserved" /> </Register> - <Register start="+0x062C" size="4" name="CLK_M4_SSP1_STAT" access="ReadOnly" description="CLK_M4_SSP1 clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF"> + <Register start="+0x0614" size="4" name="CLK_M3_USART3_STAT" access="ReadOnly" description="CLK_M3_USART3 clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF"> <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." /> <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." /> <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." /> <BitField start="3" size="29" name="RESERVED" description="Reserved" /> </Register> - <Register start="+0x0634" size="4" name="CLK_M4_QEI_STAT" access="ReadOnly" description="CLK_M4_QEI clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF"> + <Register start="+0x061C" size="4" name="CLK_M3_TIMER2_STAT" access="ReadOnly" description="CLK_M3_TIMER2 clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF"> <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." /> <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." /> <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." /> <BitField start="3" size="29" name="RESERVED" description="Reserved" /> </Register> - <Register start="+0x0704" size="4" name="CLK_PERIPH_BUS_STAT" access="ReadOnly" description="CLK_PERIPH_BUS_STAT clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF"> + <Register start="+0x0624" size="4" name="CLK_M3_TIMER3_STAT" access="ReadOnly" description="CLK_M3_TIMER3 clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF"> <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." /> <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." /> <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." /> <BitField start="3" size="29" name="RESERVED" description="Reserved" /> </Register> - <Register start="+0x0714" size="4" name="CLK_PERIPH_CORE_STAT" access="ReadOnly" description="CLK_CORE_BUS_STAT clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF"> + <Register start="+0x062C" size="4" name="CLK_M3_SSP1_STAT" access="ReadOnly" description="CLK_M3_SSP1 clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF"> <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." /> <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." /> <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." /> <BitField start="3" size="29" name="RESERVED" description="Reserved" /> </Register> - <Register start="+0x071C" size="4" name="CLK_PERIPH_SGPIO_STAT" access="ReadOnly" description="CLK_CORE_SGPIO_STAT clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF"> + <Register start="+0x0634" size="4" name="CLK_M3_QEI_STAT" access="ReadOnly" description="CLK_M3_QEI clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF"> <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." /> <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." /> <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." /> @@ -13422,18 +13212,6 @@ <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." /> <BitField start="3" size="29" name="RESERVED" description="Reserved" /> </Register> - <Register start="+0xA04" size="4" name="CLK_SPI_STAT" access="ReadOnly" description="CLK_SPI clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." /> - <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." /> - <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." /> - <BitField start="3" size="29" name="RESERVED" description="Reserved" /> - </Register> - <Register start="+0xB04" size="4" name="CLK_ADCHS_STAT" access="ReadOnly" description="CLK_ADCHS clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." /> - <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." /> - <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." /> - <BitField start="3" size="29" name="RESERVED" description="Reserved" /> - </Register> </RegisterGroup> <RegisterGroup name="CCU2" start="0x40052000" description="Clock Control Unit (CCU2)"> <Register start="+0x000" size="4" name="PM" access="Read/Write" description="Power mode register" reset_value="0x00000000" reset_mask="0xFFFFFFFF"> @@ -13638,7 +13416,7 @@ <BitField start="10" size="1" name="RESERVED" description="Reserved" /> <BitField start="11" size="1" name="RESERVED" description="Reserved" /> <BitField start="12" size="1" name="M0_SUB_RST" description="Writing a one activates the reset. Writing a 0 clears the reset. This bit must be cleared by software." /> - <BitField start="13" size="1" name="M4_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." /> + <BitField start="13" size="1" name="M3_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." /> <BitField start="14" size="1" name="RESERVED" description="Reserved" /> <BitField start="15" size="1" name="RESERVED" description="Reserved" /> <BitField start="16" size="1" name="LCD_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." /> @@ -13683,11 +13461,9 @@ <BitField start="21" size="1" name="SPIFI_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." /> <BitField start="22" size="1" name="CAN1_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." /> <BitField start="23" size="1" name="CAN0_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." /> - <BitField start="24" size="1" name="M0APP_RST" description="Writing a one activates the reset. Writing a 0 clears the reset. This bit must be cleared by software." /> - <BitField start="25" size="1" name="SGPIO_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." /> - <BitField start="26" size="1" name="SPI_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." /> - <BitField start="27" size="1" name="RESERVED" description="Reserved" /> - <BitField start="28" size="1" name="ADCHS_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." /> + <BitField start="24" size="1" name="RESERVED" description="Reserved." /> + <BitField start="25" size="3" name="RESERVED" description="Reserved" /> + <BitField start="28" size="1" name="RESERVED" description="Reserved." /> <BitField start="29" size="1" name="RESERVED" description="Reserved" /> <BitField start="30" size="1" name="RESERVED" description="Reserved" /> <BitField start="31" size="1" name="RESERVED" description="Reserved" /> @@ -13706,7 +13482,7 @@ <BitField start="20" size="2" name="RESERVED" description="Reserved" /> <BitField start="22" size="2" name="RESERVED" description="Reserved" /> <BitField start="24" size="2" name="M0SUB_RST" description="Status of the M0SUB_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" /> - <BitField start="26" size="2" name="M4_RST" description="Status of the M4_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" /> + <BitField start="26" size="2" name="M3_RST" description="Status of the M3_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" /> <BitField start="28" size="2" name="RESERVED" description="Reserved" /> <BitField start="30" size="2" name="RESERVED" description="Reserved" /> </Register> @@ -13755,11 +13531,9 @@ <BitField start="10" size="2" name="SPIFI_RST" description="Status of the SPIFI_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" /> <BitField start="12" size="2" name="CAN1_RST" description="Status of the CAN1_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" /> <BitField start="14" size="2" name="CAN0_RST" description="Status of the CAN0_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" /> - <BitField start="16" size="2" name="M0APP_RST" description="Status of the M0APP_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" /> - <BitField start="18" size="2" name="SGPIO_RST" description="Status of the SGPIO_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" /> - <BitField start="20" size="2" name="SPI_RST" description="Status of the SPI_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" /> - <BitField start="22" size="2" name="RESERVED" description="Reserved" /> - <BitField start="24" size="2" name="ADCHS_RST" description="Status of the ADCHS_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" /> + <BitField start="16" size="2" name="RESERVED" description="Reserved." /> + <BitField start="18" size="6" name="RESERVED" description="Reserved" /> + <BitField start="24" size="2" name="RESERVED" description="Reserved" /> <BitField start="26" size="2" name="RESERVED" description="Reserved" /> <BitField start="28" size="2" name="RESERVED" description="Reserved" /> <BitField start="30" size="2" name="RESERVED" description="Reserved" /> @@ -13778,7 +13552,7 @@ <BitField start="10" size="1" name="RESERVED" description="Reserved" /> <BitField start="11" size="1" name="RESERVED" description="Reserved" /> <BitField start="12" size="1" name="M0SUB_RST" description="Current status of the M0SUB_RST 0 = Reset asserted 1 = No reset" /> - <BitField start="13" size="1" name="M4_RST" description="Current status of the M4_RST 0 = Reset asserted 1 = No reset" /> + <BitField start="13" size="1" name="M3_RST" description="Current status of the M3_RST 0 = Reset asserted 1 = No reset" /> <BitField start="14" size="1" name="RESERVED" description="Reserved" /> <BitField start="15" size="1" name="RESERVED" description="Reserved" /> <BitField start="16" size="1" name="LCD_RST" description="Current status of the LCD_RST 0 = Reset asserted 1 = No reset" /> @@ -13823,11 +13597,9 @@ <BitField start="21" size="1" name="SPIFI_RST" description="Current status of the SPIFI_RST 0 = Reset asserted 1 = No reset" /> <BitField start="22" size="1" name="CAN1_RST" description="Current status of the CAN1_RST 0 = Reset asserted 1 = No reset" /> <BitField start="23" size="1" name="CAN0_RST" description="Current status of the CAN0_RST 0 = Reset asserted 1 = No reset" /> - <BitField start="24" size="1" name="M0APP_RST" description="Current status of the M0APP_RST 0 = Reset asserted 1 = No reset" /> - <BitField start="25" size="1" name="SGPIO_RST" description="Current status of the SGPIO_RST 0 = Reset asserted 1 = No reset" /> - <BitField start="26" size="1" name="SPI_RST" description="Current status of the SPI_RST 0 = Reset asserted 1 = No reset" /> - <BitField start="27" size="1" name="RESERVED" description="Reserved." /> - <BitField start="28" size="1" name="ADCHS_RST" description="Current status of the ADCHS_RST 0 = Reset asserted 1 = No reset" /> + <BitField start="24" size="1" name="RESERVED" description="Reserved." /> + <BitField start="25" size="3" name="RESERVED" description="Reserved." /> + <BitField start="28" size="1" name="RESERVED" description="Reserved." /> <BitField start="29" size="1" name="RESERVED" description="Reserved." /> <BitField start="30" size="1" name="RESERVED" description="Reserved." /> <BitField start="31" size="1" name="RESERVED" description="Reserved." /> @@ -13857,11 +13629,6 @@ <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated" /> <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." /> </Register> - <Register start="+0x430" size="4" name="RESET_EXT_STAT12" access="Read/Write" description="Reset external status register" reset_value="0x8" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="3" name="RESERVED" description="Reserved. Do not modify; read as logic 0." /> - <BitField start="3" size="1" name="MASTER_RESET" description="Reset activated by MASTER_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated" /> - <BitField start="4" size="28" name="RESERVED" description="Reserved. Do not modify; read as logic 0." /> - </Register> <Register start="+0x434" size="4" name="RESET_EXT_STAT13" access="Read/Write" description="Reset external status register" reset_value="0x8" reset_mask="0xFFFFFFFF"> <BitField start="0" size="3" name="RESERVED" description="Reserved. Do not modify; read as logic 0." /> <BitField start="3" size="1" name="MASTER_RESET" description="Reset activated by MASTER_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated" /> @@ -14037,26 +13804,6 @@ <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated" /> <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." /> </Register> - <Register start="+0x04E0" size="4" name="RESET_EXT_STAT56" access="Read/Write" description="Reset external status register" reset_value="0x8" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." /> - <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated" /> - <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." /> - </Register> - <Register start="+0x04E4" size="4" name="RESET_EXT_STAT57" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." /> - <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated" /> - <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." /> - </Register> - <Register start="+0x04E8" size="4" name="RESET_EXT_STAT58" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." /> - <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated" /> - <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." /> - </Register> - <Register start="+0x04F0" size="4" name="RESET_EXT_STAT60" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." /> - <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated" /> - <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." /> - </Register> </RegisterGroup> <RegisterGroup name="WWDT" start="0x40080000" description="Windowed Watchdog timer (WWDT) "> <Register start="+0x000" size="4" name="MOD" access="Read/Write" description="Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer." reset_value="0" reset_mask="0xFFFFFFFF"> @@ -25090,7 +24837,7 @@ <BitField start="16" size="16" name="RESERVED" description="Reserved" /> </Register> <Register start="+0x180" size="4" name="CLKDIV" access="Read/Write" description="CAN clock divider register" reset_value="0x0001" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="4" name="CLKDIVVAL" description="
								Clock divider value 
								CAN_CLK = PCLK/(CLKDIVVAL +1)
								
								0000: CAN_CLK = PCLK divided by 1.
								0001: CAN_CLK = PCLK divided by 2.
								0010: CAN_CLK = PCLK divided by 3.
								0011: CAN_CLK = PCLK divided by 4.
								0100: CAN_CLK = PCLK divided by 5.
								...
								1111: CAN_CLK = PCLK divided by 16.
								
							" /> + <BitField start="0" size="4" name="CLKDIVVAL" description="
								Clock divider value 
								CAN_CLK = PCLK/(CLKDIVVAL +1)
								
								0000: CAN_CLK = PCLK divided by 1.
								0001: CAN_CLK = PCLK divided by 2.
								0010: CAN_CLK = PCLK divided by 3.
								0011: CAN_CLK = PCLK divided by 4.
								0100: CAN_CLK = PCLK divided by 5.
								...
								1111: CAN_CLK = PCLK divided by 16.
							" /> <BitField start="4" size="28" name="RESERVED" description="reserved" /> </Register> </RegisterGroup> @@ -25334,7 +25081,7 @@ </BitField> <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x3 to 0xF are reserved."> <Enum name="CTIN_0" start="0x0" description="CTIN_0" /> - <Enum name="SGPIO3" start="0x1" description="SGPIO3" /> + <Enum name="RESERVED" start="0x1" description="Reserved" /> <Enum name="T0_CAP0" start="0x2" description="T0_CAP0" /> </BitField> <BitField start="8" size="24" name="RESERVED" description="Reserved" /> @@ -25382,7 +25129,7 @@ </BitField> <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x3 to 0xF are reserved."> <Enum name="CTIN_2" start="0x0" description="CTIN_2" /> - <Enum name="SGPIO3_DIV" start="0x1" description="SGPIO3_DIV" /> + <Enum name="RESERVED" start="0x1" description="Reserved" /> <Enum name="T0_CAP2" start="0x2" description="T0_CAP2" /> </BitField> <BitField start="8" size="24" name="RESERVED" description="Reserved" /> @@ -25430,7 +25177,7 @@ </BitField> <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x3 to 0xF are reserved."> <Enum name="CTIN_0" start="0x0" description="CTIN_0" /> - <Enum name="SGPIO12" start="0x1" description="SGPIO12" /> + <Enum name="RESERVED" start="0x1" description="Reserved" /> <Enum name="T1_CAP0" start="0x2" description="T1_CAP0" /> </BitField> <BitField start="8" size="24" name="RESERVED" description="Reserved" /> @@ -25526,7 +25273,7 @@ </BitField> <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x4 to 0xF are reserved."> <Enum name="CTIN_0" start="0x0" description="CTIN_0" /> - <Enum name="SGPIO12_DIV" start="0x1" description="SGPIO12_DIV" /> + <Enum name="RESERVED" start="0x1" description="Reserved" /> <Enum name="T2_CAP0" start="0x2" description="T2_CAP0" /> </BitField> <BitField start="8" size="24" name="RESERVED" description="Reserved" /> @@ -25723,8 +25470,8 @@ </BitField> <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x3 to 0xF are reserved."> <Enum name="CTIN_0" start="0x0" description="CTIN_0" /> - <Enum name="SGPIO3" start="0x1" description="SGPIO3" /> - <Enum name="SGPIO3_DIV" start="0x2" description="SGPIO3_DIV" /> + <Enum name="RESERVED" start="0x1" description="Reserved" /> + <Enum name="RESERVED" start="0x2" description="Reserved" /> </BitField> <BitField start="8" size="24" name="RESERVED" description="Reserved" /> </Register> @@ -25748,7 +25495,7 @@ <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x3 to 0xF are reserved."> <Enum name="CTIN_1" start="0x0" description="CTIN_1" /> <Enum name="USART2_TX_ACTIVE" start="0x1" description="USART2 TX active" /> - <Enum name="SGPIO12" start="0x2" description="SGPIO12" /> + <Enum name="RESERVED" start="0x2" description="Reserved" /> </BitField> <BitField start="8" size="24" name="RESERVED" description="Reserved" /> </Register> @@ -25771,8 +25518,8 @@ </BitField> <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x3 to 0xF are reserved."> <Enum name="CTIN_2" start="0x0" description="CTIN_2" /> - <Enum name="SGPIO12" start="0x1" description="SGPIO12" /> - <Enum name="SGPIO12_DIV" start="0x2" description="SGPIO12_DIV" /> + <Enum name="RESERVED" start="0x1" description="Reserved" /> + <Enum name="RESERVED" start="0x2" description="Reserved" /> </BitField> <BitField start="8" size="24" name="RESERVED" description="Reserved" /> </Register> @@ -25846,7 +25593,7 @@ <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x3 to 0xF are reserved."> <Enum name="CTIN_5" start="0x0" description="CTIN_5" /> <Enum name="USART2_RX_ACTIVE" start="0x1" description="USART2 RX active" /> - <Enum name="SGPIO12_DIV" start="0x2" description="SGPIO12_DIV" /> + <Enum name="RESERVED" start="0x2" description="Reserved" /> </BitField> <BitField start="8" size="24" name="RESERVED" description="Reserved" /> </Register> @@ -25900,37 +25647,6 @@ </BitField> <BitField start="8" size="24" name="RESERVED" description="Reserved" /> </Register> - <Register start="+0x060" size="4" name="ADCHS_TRIGGER_IN" access="Read/Write" description="ADCHS trigger input multiplexer (GIMA output 24)" reset_value="0" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="1" name="INV" description="Invert input"> - <Enum name="NOT_INVERTED" start="0" description="Not inverted." /> - <Enum name="INPUT_INVERTED" start="1" description="Input inverted." /> - </BitField> - <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection"> - <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." /> - <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." /> - </BitField> - <BitField start="2" size="1" name="SYNCH" description="Enable synchronization"> - <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable synchronization." /> - <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable synchronization." /> - </BitField> - <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation."> - <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." /> - <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." /> - </BitField> - <BitField start="4" size="4" name="SELECT" description="Select input. Values 0xA to 0xF are reserved."> - <Enum name="GPIO6_28" start="0x0" description="GPIO6[28]" /> - <Enum name="GPIO5_3" start="0x1" description="GPIO5[3]" /> - <Enum name="SGPIO10" start="0x2" description="SGPIO10" /> - <Enum name="SGPIO12" start="0x3" description="SGPIO12" /> - <Enum name="RESERVED" start="0x4" description="Reserved" /> - <Enum name="MCOB2" start="0x5" description="MCOB2" /> - <Enum name="CTOUT_0_OR_T0_MAT0" start="0x6" description="CTOUT_0 or T0_MAT0" /> - <Enum name="CTOUT_8_OR_T2_MAT0" start="0x7" description="CTOUT_8 or T2_MAT0" /> - <Enum name="T0_MAT0" start="0x8" description="T0_MAT0" /> - <Enum name="T2_MAT0" start="0x9" description="T2_MAT0" /> - </BitField> - <BitField start="8" size="24" name="RESERVED" description="Reserved" /> - </Register> <Register start="+0x064" size="4" name="EVENTROUTER_13_IN" access="Read/Write" description="Event router input 13 multiplexer (GIMA output 25)" reset_value="0" reset_mask="0xFFFFFFFF"> <BitField start="0" size="1" name="INV" description="Invert input"> <Enum name="NOT_INVERTED" start="0" description="Not inverted." /> @@ -25950,7 +25666,7 @@ </BitField> <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x3 to 0xF are reserved."> <Enum name="CTOUT_2_OR_T0_MAT2" start="0x0" description="CTOUT_2 or T0_MAT2" /> - <Enum name="SGPIO3" start="0x1" description="SGPIO3" /> + <Enum name="RESERVED" start="0x1" description="Reserved" /> <Enum name="T0_MAT2" start="0x2" description="T0_MAT2" /> </BitField> <BitField start="8" size="24" name="RESERVED" description="Reserved" /> @@ -25974,7 +25690,7 @@ </BitField> <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x3 to 0xF are reserved."> <Enum name="CTOUT_6_OR_T1_MAT2" start="0x0" description="CTOUT_6 or T1_MAT2" /> - <Enum name="SGPIO12" start="0x1" description="SGPIO12" /> + <Enum name="RESERVED" start="0x1" description="Reserved" /> <Enum name="T1_MAT2" start="0x2" description="T1_MAT2" /> </BitField> <BitField start="8" size="24" name="RESERVED" description="Reserved" /> @@ -26562,7 +26278,7 @@ <BitField start="16" size="16" name="RESERVED" description="Reserved" /> </Register> <Register start="+0x180" size="4" name="CLKDIV" access="Read/Write" description="CAN clock divider register" reset_value="0x0001" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="4" name="CLKDIVVAL" description="
								Clock divider value 
								CAN_CLK = PCLK/(CLKDIVVAL +1)
								
								0000: CAN_CLK = PCLK divided by 1.
								0001: CAN_CLK = PCLK divided by 2.
								0010: CAN_CLK = PCLK divided by 3.
								0011: CAN_CLK = PCLK divided by 4.
								0100: CAN_CLK = PCLK divided by 5.
								...
								1111: CAN_CLK = PCLK divided by 16.
								
							" /> + <BitField start="0" size="4" name="CLKDIVVAL" description="
								Clock divider value 
								CAN_CLK = PCLK/(CLKDIVVAL +1)
								
								0000: CAN_CLK = PCLK divided by 1.
								0001: CAN_CLK = PCLK divided by 2.
								0010: CAN_CLK = PCLK divided by 3.
								0011: CAN_CLK = PCLK divided by 4.
								0100: CAN_CLK = PCLK divided by 5.
								...
								1111: CAN_CLK = PCLK divided by 16.
							" /> <BitField start="4" size="28" name="RESERVED" description="reserved" /> </Register> </RegisterGroup> @@ -26800,531 +26516,6 @@ <BitField start="17" size="15" name="RESERVED" description="Reserved. Always 0." /> </Register> </RegisterGroup> - <RegisterGroup name="ADCHS" start="0x400F0000" description="12-bit Analog-to-Digital Converter High-Speed (ADCHS)"> - <Register start="+0x0000" size="4" name="FLUSH" access="WriteOnly" description="Flushes FIFO" reset_value="0x00000000" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="1" name="FIFO_FLUSH" description="1= fifo is cleared" /> - <BitField start="1" size="31" name="RESERVED" description="Reserved." /> - </Register> - <Register start="+0x0004" size="4" name="DMA_REQ" access="Read/Write" description="Set or clear DMA write request" reset_value="0x00000001" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="1" name="DMA_REQ_WR" description="1 = Dma_req_wr is set (initially used to fill second table), 0 = Dma_req_wr is cleared" /> - <BitField start="1" size="31" name="RESERVED" description="Reserved." /> - </Register> - <Register start="+0x0008" size="4" name="FIFO_STS" access="ReadOnly" description="Indicates FIFO fill level status" reset_value="0x00000000" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="5" name="LEVEL" description="0 = FIFO is empty 1...15 = FIFO is partially full 16 = FIFO is full" /> - <BitField start="5" size="27" name="RESERVED" description="Reserved." /> - </Register> - <Register start="+0x000C" size="4" name="FIFO_CFG" access="Read/Write" description="Configures FIFO fill level that triggers interrupt and packing 1 or 2 samples per word." reset_value="0x00000010" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="1" name="PACKED_READ" description="0 = one sample is packed in one 32-bit read cycle 1 = two samples are packed in one 32-bit read cycle" /> - <BitField start="1" size="5" name="LEVEL" description="When the FIFO contains more or equal than FIFO_LEVEL samples interrupt flag FIFO_FULL interrupt will be set and DMA_Read_Req will be raised." /> - <BitField start="6" size="26" name="RESERVED" description="Reserved" /> - </Register> - <Register start="+0x0010" size="4" name="TRIGGER" access="WriteOnly" description="Enable software trigger to start descriptor processing" reset_value="0x00000000" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="1" name="SW_TRIGGER" description="Auto cleared" /> - <BitField start="1" size="31" name="RESERVED" description="Reserved" /> - </Register> - <Register start="+0x0014" size="4" name="DSCR_STS" access="Read/Write" description="Indicates active descriptor table and descriptor entry" reset_value="0x00000000" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="1" name="ACT_TABLE" description="0 = table 0 is active 1 = table 1 is active." /> - <BitField start="1" size="3" name="ACT_DESCRIPTOR" description="ID of the descriptor that is active." /> - <BitField start="4" size="28" name="RESERVED" description="Reserved" /> - </Register> - <Register start="+0x0018" size="4" name="POWER_DOWN" access="Read/Write" description="Set or clear power down mode" reset_value="0x00000001" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="1" name="PD_CTRL" description="0 = disable power down mode. Register holds value until set by writing 1 to this bit or by descriptor processor when descriptor field POWER_DOWN is set. 1 = enable power down mode. Register holds value until cleared by writing 0 to this bit or by descriptor processor when waking up RECOVERY_TIME before a conversion." /> - <BitField start="1" size="31" name="RESERVED" description="Reserved" /> - </Register> - <Register start="+0x001C" size="4" name="CONFIG" access="Read/Write" description="Configures external trigger mode, store channel ID in FIFO and walk-up recovery time from power down." reset_value="0x00002400" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="2" name="TRIGGER__MASK" description="00 = triggers off 01 = software trigger only 10 = external trigger only 11 = both triggers allowed" /> - <BitField start="2" size="2" name="TRIGGER_MODE" description="00 = rising external trigger 01 = falling external trigger 10 = low external trigger 11 = high external trigger" /> - <BitField start="4" size="1" name="TRIGGER_SYNC" description="0 = do not synchronize external trigger input 1 = synchronize external trigger input" /> - <BitField start="5" size="1" name="CHANNEL_ID_EN" description="0 = do not add channel ID to FIFO output data 1 = add channel ID to FIFO output data" /> - <BitField start="6" size="8" name="RECOVERY_TIME" description="ADC recovery time from power down" /> - <BitField start="14" size="18" name="RESERVED" description="Reserved" /> - </Register> - <Register start="+0x0020" size="4" name="THR_A" access="Read/Write" description="Configures window comparator A levels." reset_value="0x0FFF0000" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="12" name="THR_LOW_A" description="Low Compare Threshold Register A: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair A." /> - <BitField start="16" size="12" name="THR_HIGH_A" description="High Compare Threshold Register A: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair A." /> - <BitField start="28" size="4" name="RESERVED" description="Reserved." /> - </Register> - <Register start="+0x0024" size="4" name="THR_B" access="Read/Write" description="Configures window comparator B levels." reset_value="0x0FFF0000" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="12" name="THR_LOW_B" description="Low Compare Threshold Register B: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair A." /> - <BitField start="16" size="12" name="THR_HIGH_B" description="High Compare Threshold Register B: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair A." /> - <BitField start="28" size="4" name="RESERVED" description="Reserved." /> - </Register> - <Register start="+0x0028+0" size="4" name="LAST_SAMPLE[0]" access="ReadOnly" description="Contains last converted sample of input M [M=0..5) and result of window comparator." reset_value="0x00000000" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion on this channel completes. This bit is cleared whenever this register is read." /> - <BitField start="1" size="1" name="OVERRUN" description="This bit will be set to a 1 if a new conversion on this channel completes and overwrites the previous contents of the RESULT field before it has been read - i.e. while the DONE bit is set. This bit is cleared, along with the DONE bit, whenever this register is read. This bit (in any of the registers) will cause an overrun interrupt request to be asserted if the overrun interrupt is enabled." /> - <BitField start="2" size="2" name="THCMP_RANGE" description="Threshold Range Comparison result 00: In Range 01: Below Range 10: Above Range 11: Reserved" /> - <BitField start="4" size="2" name="THCMP_CROSS" description="Threshold Crossing Comparison result 00: No Threshold Crossing detected 01: Downward Threshold Crossing detected 10: Upward Threshold Crossing detected 11: Reserved" /> - <BitField start="6" size="12" name="SAMPLE" description="12-Bit value of last converted sample for this channel" /> - <BitField start="17" size="4" name="RESERVED" description="Reserved" /> - <BitField start="21" size="11" name="RESERVED" description="Reserved" /> - </Register> - <Register start="+0x0028+4" size="4" name="LAST_SAMPLE[1]" access="ReadOnly" description="Contains last converted sample of input M [M=0..5) and result of window comparator." reset_value="0x00000000" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion on this channel completes. This bit is cleared whenever this register is read." /> - <BitField start="1" size="1" name="OVERRUN" description="This bit will be set to a 1 if a new conversion on this channel completes and overwrites the previous contents of the RESULT field before it has been read - i.e. while the DONE bit is set. This bit is cleared, along with the DONE bit, whenever this register is read. This bit (in any of the registers) will cause an overrun interrupt request to be asserted if the overrun interrupt is enabled." /> - <BitField start="2" size="2" name="THCMP_RANGE" description="Threshold Range Comparison result 00: In Range 01: Below Range 10: Above Range 11: Reserved" /> - <BitField start="4" size="2" name="THCMP_CROSS" description="Threshold Crossing Comparison result 00: No Threshold Crossing detected 01: Downward Threshold Crossing detected 10: Upward Threshold Crossing detected 11: Reserved" /> - <BitField start="6" size="12" name="SAMPLE" description="12-Bit value of last converted sample for this channel" /> - <BitField start="17" size="4" name="RESERVED" description="Reserved" /> - <BitField start="21" size="11" name="RESERVED" description="Reserved" /> - </Register> - <Register start="+0x0028+8" size="4" name="LAST_SAMPLE[2]" access="ReadOnly" description="Contains last converted sample of input M [M=0..5) and result of window comparator." reset_value="0x00000000" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion on this channel completes. This bit is cleared whenever this register is read." /> - <BitField start="1" size="1" name="OVERRUN" description="This bit will be set to a 1 if a new conversion on this channel completes and overwrites the previous contents of the RESULT field before it has been read - i.e. while the DONE bit is set. This bit is cleared, along with the DONE bit, whenever this register is read. This bit (in any of the registers) will cause an overrun interrupt request to be asserted if the overrun interrupt is enabled." /> - <BitField start="2" size="2" name="THCMP_RANGE" description="Threshold Range Comparison result 00: In Range 01: Below Range 10: Above Range 11: Reserved" /> - <BitField start="4" size="2" name="THCMP_CROSS" description="Threshold Crossing Comparison result 00: No Threshold Crossing detected 01: Downward Threshold Crossing detected 10: Upward Threshold Crossing detected 11: Reserved" /> - <BitField start="6" size="12" name="SAMPLE" description="12-Bit value of last converted sample for this channel" /> - <BitField start="17" size="4" name="RESERVED" description="Reserved" /> - <BitField start="21" size="11" name="RESERVED" description="Reserved" /> - </Register> - <Register start="+0x0028+12" size="4" name="LAST_SAMPLE[3]" access="ReadOnly" description="Contains last converted sample of input M [M=0..5) and result of window comparator." reset_value="0x00000000" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion on this channel completes. This bit is cleared whenever this register is read." /> - <BitField start="1" size="1" name="OVERRUN" description="This bit will be set to a 1 if a new conversion on this channel completes and overwrites the previous contents of the RESULT field before it has been read - i.e. while the DONE bit is set. This bit is cleared, along with the DONE bit, whenever this register is read. This bit (in any of the registers) will cause an overrun interrupt request to be asserted if the overrun interrupt is enabled." /> - <BitField start="2" size="2" name="THCMP_RANGE" description="Threshold Range Comparison result 00: In Range 01: Below Range 10: Above Range 11: Reserved" /> - <BitField start="4" size="2" name="THCMP_CROSS" description="Threshold Crossing Comparison result 00: No Threshold Crossing detected 01: Downward Threshold Crossing detected 10: Upward Threshold Crossing detected 11: Reserved" /> - <BitField start="6" size="12" name="SAMPLE" description="12-Bit value of last converted sample for this channel" /> - <BitField start="17" size="4" name="RESERVED" description="Reserved" /> - <BitField start="21" size="11" name="RESERVED" description="Reserved" /> - </Register> - <Register start="+0x0028+16" size="4" name="LAST_SAMPLE[4]" access="ReadOnly" description="Contains last converted sample of input M [M=0..5) and result of window comparator." reset_value="0x00000000" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion on this channel completes. This bit is cleared whenever this register is read." /> - <BitField start="1" size="1" name="OVERRUN" description="This bit will be set to a 1 if a new conversion on this channel completes and overwrites the previous contents of the RESULT field before it has been read - i.e. while the DONE bit is set. This bit is cleared, along with the DONE bit, whenever this register is read. This bit (in any of the registers) will cause an overrun interrupt request to be asserted if the overrun interrupt is enabled." /> - <BitField start="2" size="2" name="THCMP_RANGE" description="Threshold Range Comparison result 00: In Range 01: Below Range 10: Above Range 11: Reserved" /> - <BitField start="4" size="2" name="THCMP_CROSS" description="Threshold Crossing Comparison result 00: No Threshold Crossing detected 01: Downward Threshold Crossing detected 10: Upward Threshold Crossing detected 11: Reserved" /> - <BitField start="6" size="12" name="SAMPLE" description="12-Bit value of last converted sample for this channel" /> - <BitField start="17" size="4" name="RESERVED" description="Reserved" /> - <BitField start="21" size="11" name="RESERVED" description="Reserved" /> - </Register> - <Register start="+0x0028+20" size="4" name="LAST_SAMPLE[5]" access="ReadOnly" description="Contains last converted sample of input M [M=0..5) and result of window comparator." reset_value="0x00000000" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion on this channel completes. This bit is cleared whenever this register is read." /> - <BitField start="1" size="1" name="OVERRUN" description="This bit will be set to a 1 if a new conversion on this channel completes and overwrites the previous contents of the RESULT field before it has been read - i.e. while the DONE bit is set. This bit is cleared, along with the DONE bit, whenever this register is read. This bit (in any of the registers) will cause an overrun interrupt request to be asserted if the overrun interrupt is enabled." /> - <BitField start="2" size="2" name="THCMP_RANGE" description="Threshold Range Comparison result 00: In Range 01: Below Range 10: Above Range 11: Reserved" /> - <BitField start="4" size="2" name="THCMP_CROSS" description="Threshold Crossing Comparison result 00: No Threshold Crossing detected 01: Downward Threshold Crossing detected 10: Upward Threshold Crossing detected 11: Reserved" /> - <BitField start="6" size="12" name="SAMPLE" description="12-Bit value of last converted sample for this channel" /> - <BitField start="17" size="4" name="RESERVED" description="Reserved" /> - <BitField start="21" size="11" name="RESERVED" description="Reserved" /> - </Register> - <Register start="+0x0104" size="4" name="ADC_SPEED" access="Read/Write" description="ADC speed control" reset_value="0x00000000" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="4" name="DGEC0" description="Speed0" /> - <BitField start="4" size="4" name="DGEC1" description="Speed1" /> - <BitField start="8" size="4" name="DGEC2" description="Speed2" /> - <BitField start="12" size="4" name="DGEC3" description="Speed3" /> - <BitField start="16" size="4" name="DGEC4" description="Speed4" /> - <BitField start="20" size="4" name="DGEC5" description="Speed5" /> - <BitField start="24" size="8" name="RESERVED" description="Reserved" /> - </Register> - <Register start="+0x0108" size="4" name="POWER_CONTROL" access="Read/Write" description="Configures ADC power vs. speed, DC-in biasing, output format and power gating." reset_value="0x00000000" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="4" name="CRS" description="current setting for power versus speed programming" /> - <BitField start="4" size="6" name="DCINNEG" description="AC-DC coupling selection 0 = No dc bias 1 = DC bias on vin_neg side" /> - <BitField start="10" size="6" name="DCINPOS" description="AC-DC coupling selection 0 = No dc bias 1 = DC bias on vin_pos side" /> - <BitField start="16" size="1" name="TWOS" description="Output data format selection 0 = offset binary 1 = two's complement" /> - <BitField start="17" size="1" name="POWER_SWITCH" description="0 = ADC is powered down 1 = ADC is active" /> - <BitField start="18" size="1" name="BGAP_SWITCH" description="0 = ADC band gap reference is powered down 1 = ADC band gap reference is active" /> - <BitField start="19" size="13" name="RESERVED" description="Reserved" /> - </Register> - <Register start="+0x0200+0" size="4" name="FIFO_OUTPUT[0]" access="ReadOnly" description="FIFO output mapped to 16 consecutive address locations. An output contains the value and input channel ID of one or two converted samples" reset_value="0x00008000" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="12" name="SAMPLE" description="Value of first converted sample" /> - <BitField start="12" size="3" name="CHAN_ID" description="Channel number of first converted sample: 000: channel _0 or CHANNEL_ID_EN =0 001: channel _1 010: channel _2 011: channel _3 100: channel _4 101: channel _5 110: reserved 111: recovery_ error" /> - <BitField start="15" size="1" name="EMPTY" description="0: FIFO not empty 1: FIFO empty" /> - <BitField start="16" size="12" name="SAMPLE2" description="Value of second converted sample. This field is only valid if PACKED_READ is set else it is 0x0" /> - <BitField start="28" size="3" name="CHAN_ID2" description="Channel number of second converted sample This field is only valid if CHANNEL_ID_EN and PACKED_READ are set else it is 0x0" /> - <BitField start="31" size="1" name="EMPTY2" description="0: FIFO not empty 1: FIFO empty and PACKED_READ is set" /> - </Register> - <Register start="+0x0200+4" size="4" name="FIFO_OUTPUT[1]" access="ReadOnly" description="FIFO output mapped to 16 consecutive address locations. An output contains the value and input channel ID of one or two converted samples" reset_value="0x00008000" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="12" name="SAMPLE" description="Value of first converted sample" /> - <BitField start="12" size="3" name="CHAN_ID" description="Channel number of first converted sample: 000: channel _0 or CHANNEL_ID_EN =0 001: channel _1 010: channel _2 011: channel _3 100: channel _4 101: channel _5 110: reserved 111: recovery_ error" /> - <BitField start="15" size="1" name="EMPTY" description="0: FIFO not empty 1: FIFO empty" /> - <BitField start="16" size="12" name="SAMPLE2" description="Value of second converted sample. This field is only valid if PACKED_READ is set else it is 0x0" /> - <BitField start="28" size="3" name="CHAN_ID2" description="Channel number of second converted sample This field is only valid if CHANNEL_ID_EN and PACKED_READ are set else it is 0x0" /> - <BitField start="31" size="1" name="EMPTY2" description="0: FIFO not empty 1: FIFO empty and PACKED_READ is set" /> - </Register> - <Register start="+0x0200+8" size="4" name="FIFO_OUTPUT[2]" access="ReadOnly" description="FIFO output mapped to 16 consecutive address locations. An output contains the value and input channel ID of one or two converted samples" reset_value="0x00008000" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="12" name="SAMPLE" description="Value of first converted sample" /> - <BitField start="12" size="3" name="CHAN_ID" description="Channel number of first converted sample: 000: channel _0 or CHANNEL_ID_EN =0 001: channel _1 010: channel _2 011: channel _3 100: channel _4 101: channel _5 110: reserved 111: recovery_ error" /> - <BitField start="15" size="1" name="EMPTY" description="0: FIFO not empty 1: FIFO empty" /> - <BitField start="16" size="12" name="SAMPLE2" description="Value of second converted sample. This field is only valid if PACKED_READ is set else it is 0x0" /> - <BitField start="28" size="3" name="CHAN_ID2" description="Channel number of second converted sample This field is only valid if CHANNEL_ID_EN and PACKED_READ are set else it is 0x0" /> - <BitField start="31" size="1" name="EMPTY2" description="0: FIFO not empty 1: FIFO empty and PACKED_READ is set" /> - </Register> - <Register start="+0x0200+12" size="4" name="FIFO_OUTPUT[3]" access="ReadOnly" description="FIFO output mapped to 16 consecutive address locations. An output contains the value and input channel ID of one or two converted samples" reset_value="0x00008000" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="12" name="SAMPLE" description="Value of first converted sample" /> - <BitField start="12" size="3" name="CHAN_ID" description="Channel number of first converted sample: 000: channel _0 or CHANNEL_ID_EN =0 001: channel _1 010: channel _2 011: channel _3 100: channel _4 101: channel _5 110: reserved 111: recovery_ error" /> - <BitField start="15" size="1" name="EMPTY" description="0: FIFO not empty 1: FIFO empty" /> - <BitField start="16" size="12" name="SAMPLE2" description="Value of second converted sample. This field is only valid if PACKED_READ is set else it is 0x0" /> - <BitField start="28" size="3" name="CHAN_ID2" description="Channel number of second converted sample This field is only valid if CHANNEL_ID_EN and PACKED_READ are set else it is 0x0" /> - <BitField start="31" size="1" name="EMPTY2" description="0: FIFO not empty 1: FIFO empty and PACKED_READ is set" /> - </Register> - <Register start="+0x0200+16" size="4" name="FIFO_OUTPUT[4]" access="ReadOnly" description="FIFO output mapped to 16 consecutive address locations. An output contains the value and input channel ID of one or two converted samples" reset_value="0x00008000" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="12" name="SAMPLE" description="Value of first converted sample" /> - <BitField start="12" size="3" name="CHAN_ID" description="Channel number of first converted sample: 000: channel _0 or CHANNEL_ID_EN =0 001: channel _1 010: channel _2 011: channel _3 100: channel _4 101: channel _5 110: reserved 111: recovery_ error" /> - <BitField start="15" size="1" name="EMPTY" description="0: FIFO not empty 1: FIFO empty" /> - <BitField start="16" size="12" name="SAMPLE2" description="Value of second converted sample. This field is only valid if PACKED_READ is set else it is 0x0" /> - <BitField start="28" size="3" name="CHAN_ID2" description="Channel number of second converted sample This field is only valid if CHANNEL_ID_EN and PACKED_READ are set else it is 0x0" /> - <BitField start="31" size="1" name="EMPTY2" description="0: FIFO not empty 1: FIFO empty and PACKED_READ is set" /> - </Register> - <Register start="+0x0200+20" size="4" name="FIFO_OUTPUT[5]" access="ReadOnly" description="FIFO output mapped to 16 consecutive address locations. An output contains the value and input channel ID of one or two converted samples" reset_value="0x00008000" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="12" name="SAMPLE" description="Value of first converted sample" /> - <BitField start="12" size="3" name="CHAN_ID" description="Channel number of first converted sample: 000: channel _0 or CHANNEL_ID_EN =0 001: channel _1 010: channel _2 011: channel _3 100: channel _4 101: channel _5 110: reserved 111: recovery_ error" /> - <BitField start="15" size="1" name="EMPTY" description="0: FIFO not empty 1: FIFO empty" /> - <BitField start="16" size="12" name="SAMPLE2" description="Value of second converted sample. This field is only valid if PACKED_READ is set else it is 0x0" /> - <BitField start="28" size="3" name="CHAN_ID2" description="Channel number of second converted sample This field is only valid if CHANNEL_ID_EN and PACKED_READ are set else it is 0x0" /> - <BitField start="31" size="1" name="EMPTY2" description="0: FIFO not empty 1: FIFO empty and PACKED_READ is set" /> - </Register> - <Register start="+0x0200+24" size="4" name="FIFO_OUTPUT[6]" access="ReadOnly" description="FIFO output mapped to 16 consecutive address locations. An output contains the value and input channel ID of one or two converted samples" reset_value="0x00008000" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="12" name="SAMPLE" description="Value of first converted sample" /> - <BitField start="12" size="3" name="CHAN_ID" description="Channel number of first converted sample: 000: channel _0 or CHANNEL_ID_EN =0 001: channel _1 010: channel _2 011: channel _3 100: channel _4 101: channel _5 110: reserved 111: recovery_ error" /> - <BitField start="15" size="1" name="EMPTY" description="0: FIFO not empty 1: FIFO empty" /> - <BitField start="16" size="12" name="SAMPLE2" description="Value of second converted sample. This field is only valid if PACKED_READ is set else it is 0x0" /> - <BitField start="28" size="3" name="CHAN_ID2" description="Channel number of second converted sample This field is only valid if CHANNEL_ID_EN and PACKED_READ are set else it is 0x0" /> - <BitField start="31" size="1" name="EMPTY2" description="0: FIFO not empty 1: FIFO empty and PACKED_READ is set" /> - </Register> - <Register start="+0x0200+28" size="4" name="FIFO_OUTPUT[7]" access="ReadOnly" description="FIFO output mapped to 16 consecutive address locations. An output contains the value and input channel ID of one or two converted samples" reset_value="0x00008000" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="12" name="SAMPLE" description="Value of first converted sample" /> - <BitField start="12" size="3" name="CHAN_ID" description="Channel number of first converted sample: 000: channel _0 or CHANNEL_ID_EN =0 001: channel _1 010: channel _2 011: channel _3 100: channel _4 101: channel _5 110: reserved 111: recovery_ error" /> - <BitField start="15" size="1" name="EMPTY" description="0: FIFO not empty 1: FIFO empty" /> - <BitField start="16" size="12" name="SAMPLE2" description="Value of second converted sample. This field is only valid if PACKED_READ is set else it is 0x0" /> - <BitField start="28" size="3" name="CHAN_ID2" description="Channel number of second converted sample This field is only valid if CHANNEL_ID_EN and PACKED_READ are set else it is 0x0" /> - <BitField start="31" size="1" name="EMPTY2" description="0: FIFO not empty 1: FIFO empty and PACKED_READ is set" /> - </Register> - <Register start="+0x0200+32" size="4" name="FIFO_OUTPUT[8]" access="ReadOnly" description="FIFO output mapped to 16 consecutive address locations. An output contains the value and input channel ID of one or two converted samples" reset_value="0x00008000" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="12" name="SAMPLE" description="Value of first converted sample" /> - <BitField start="12" size="3" name="CHAN_ID" description="Channel number of first converted sample: 000: channel _0 or CHANNEL_ID_EN =0 001: channel _1 010: channel _2 011: channel _3 100: channel _4 101: channel _5 110: reserved 111: recovery_ error" /> - <BitField start="15" size="1" name="EMPTY" description="0: FIFO not empty 1: FIFO empty" /> - <BitField start="16" size="12" name="SAMPLE2" description="Value of second converted sample. This field is only valid if PACKED_READ is set else it is 0x0" /> - <BitField start="28" size="3" name="CHAN_ID2" description="Channel number of second converted sample This field is only valid if CHANNEL_ID_EN and PACKED_READ are set else it is 0x0" /> - <BitField start="31" size="1" name="EMPTY2" description="0: FIFO not empty 1: FIFO empty and PACKED_READ is set" /> - </Register> - <Register start="+0x0200+36" size="4" name="FIFO_OUTPUT[9]" access="ReadOnly" description="FIFO output mapped to 16 consecutive address locations. An output contains the value and input channel ID of one or two converted samples" reset_value="0x00008000" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="12" name="SAMPLE" description="Value of first converted sample" /> - <BitField start="12" size="3" name="CHAN_ID" description="Channel number of first converted sample: 000: channel _0 or CHANNEL_ID_EN =0 001: channel _1 010: channel _2 011: channel _3 100: channel _4 101: channel _5 110: reserved 111: recovery_ error" /> - <BitField start="15" size="1" name="EMPTY" description="0: FIFO not empty 1: FIFO empty" /> - <BitField start="16" size="12" name="SAMPLE2" description="Value of second converted sample. This field is only valid if PACKED_READ is set else it is 0x0" /> - <BitField start="28" size="3" name="CHAN_ID2" description="Channel number of second converted sample This field is only valid if CHANNEL_ID_EN and PACKED_READ are set else it is 0x0" /> - <BitField start="31" size="1" name="EMPTY2" description="0: FIFO not empty 1: FIFO empty and PACKED_READ is set" /> - </Register> - <Register start="+0x0200+40" size="4" name="FIFO_OUTPUT[10]" access="ReadOnly" description="FIFO output mapped to 16 consecutive address locations. An output contains the value and input channel ID of one or two converted samples" reset_value="0x00008000" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="12" name="SAMPLE" description="Value of first converted sample" /> - <BitField start="12" size="3" name="CHAN_ID" description="Channel number of first converted sample: 000: channel _0 or CHANNEL_ID_EN =0 001: channel _1 010: channel _2 011: channel _3 100: channel _4 101: channel _5 110: reserved 111: recovery_ error" /> - <BitField start="15" size="1" name="EMPTY" description="0: FIFO not empty 1: FIFO empty" /> - <BitField start="16" size="12" name="SAMPLE2" description="Value of second converted sample. This field is only valid if PACKED_READ is set else it is 0x0" /> - <BitField start="28" size="3" name="CHAN_ID2" description="Channel number of second converted sample This field is only valid if CHANNEL_ID_EN and PACKED_READ are set else it is 0x0" /> - <BitField start="31" size="1" name="EMPTY2" description="0: FIFO not empty 1: FIFO empty and PACKED_READ is set" /> - </Register> - <Register start="+0x0200+44" size="4" name="FIFO_OUTPUT[11]" access="ReadOnly" description="FIFO output mapped to 16 consecutive address locations. An output contains the value and input channel ID of one or two converted samples" reset_value="0x00008000" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="12" name="SAMPLE" description="Value of first converted sample" /> - <BitField start="12" size="3" name="CHAN_ID" description="Channel number of first converted sample: 000: channel _0 or CHANNEL_ID_EN =0 001: channel _1 010: channel _2 011: channel _3 100: channel _4 101: channel _5 110: reserved 111: recovery_ error" /> - <BitField start="15" size="1" name="EMPTY" description="0: FIFO not empty 1: FIFO empty" /> - <BitField start="16" size="12" name="SAMPLE2" description="Value of second converted sample. This field is only valid if PACKED_READ is set else it is 0x0" /> - <BitField start="28" size="3" name="CHAN_ID2" description="Channel number of second converted sample This field is only valid if CHANNEL_ID_EN and PACKED_READ are set else it is 0x0" /> - <BitField start="31" size="1" name="EMPTY2" description="0: FIFO not empty 1: FIFO empty and PACKED_READ is set" /> - </Register> - <Register start="+0x0200+48" size="4" name="FIFO_OUTPUT[12]" access="ReadOnly" description="FIFO output mapped to 16 consecutive address locations. An output contains the value and input channel ID of one or two converted samples" reset_value="0x00008000" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="12" name="SAMPLE" description="Value of first converted sample" /> - <BitField start="12" size="3" name="CHAN_ID" description="Channel number of first converted sample: 000: channel _0 or CHANNEL_ID_EN =0 001: channel _1 010: channel _2 011: channel _3 100: channel _4 101: channel _5 110: reserved 111: recovery_ error" /> - <BitField start="15" size="1" name="EMPTY" description="0: FIFO not empty 1: FIFO empty" /> - <BitField start="16" size="12" name="SAMPLE2" description="Value of second converted sample. This field is only valid if PACKED_READ is set else it is 0x0" /> - <BitField start="28" size="3" name="CHAN_ID2" description="Channel number of second converted sample This field is only valid if CHANNEL_ID_EN and PACKED_READ are set else it is 0x0" /> - <BitField start="31" size="1" name="EMPTY2" description="0: FIFO not empty 1: FIFO empty and PACKED_READ is set" /> - </Register> - <Register start="+0x0200+52" size="4" name="FIFO_OUTPUT[13]" access="ReadOnly" description="FIFO output mapped to 16 consecutive address locations. An output contains the value and input channel ID of one or two converted samples" reset_value="0x00008000" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="12" name="SAMPLE" description="Value of first converted sample" /> - <BitField start="12" size="3" name="CHAN_ID" description="Channel number of first converted sample: 000: channel _0 or CHANNEL_ID_EN =0 001: channel _1 010: channel _2 011: channel _3 100: channel _4 101: channel _5 110: reserved 111: recovery_ error" /> - <BitField start="15" size="1" name="EMPTY" description="0: FIFO not empty 1: FIFO empty" /> - <BitField start="16" size="12" name="SAMPLE2" description="Value of second converted sample. This field is only valid if PACKED_READ is set else it is 0x0" /> - <BitField start="28" size="3" name="CHAN_ID2" description="Channel number of second converted sample This field is only valid if CHANNEL_ID_EN and PACKED_READ are set else it is 0x0" /> - <BitField start="31" size="1" name="EMPTY2" description="0: FIFO not empty 1: FIFO empty and PACKED_READ is set" /> - </Register> - <Register start="+0x0200+56" size="4" name="FIFO_OUTPUT[14]" access="ReadOnly" description="FIFO output mapped to 16 consecutive address locations. An output contains the value and input channel ID of one or two converted samples" reset_value="0x00008000" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="12" name="SAMPLE" description="Value of first converted sample" /> - <BitField start="12" size="3" name="CHAN_ID" description="Channel number of first converted sample: 000: channel _0 or CHANNEL_ID_EN =0 001: channel _1 010: channel _2 011: channel _3 100: channel _4 101: channel _5 110: reserved 111: recovery_ error" /> - <BitField start="15" size="1" name="EMPTY" description="0: FIFO not empty 1: FIFO empty" /> - <BitField start="16" size="12" name="SAMPLE2" description="Value of second converted sample. This field is only valid if PACKED_READ is set else it is 0x0" /> - <BitField start="28" size="3" name="CHAN_ID2" description="Channel number of second converted sample This field is only valid if CHANNEL_ID_EN and PACKED_READ are set else it is 0x0" /> - <BitField start="31" size="1" name="EMPTY2" description="0: FIFO not empty 1: FIFO empty and PACKED_READ is set" /> - </Register> - <Register start="+0x0200+60" size="4" name="FIFO_OUTPUT[15]" access="ReadOnly" description="FIFO output mapped to 16 consecutive address locations. An output contains the value and input channel ID of one or two converted samples" reset_value="0x00008000" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="12" name="SAMPLE" description="Value of first converted sample" /> - <BitField start="12" size="3" name="CHAN_ID" description="Channel number of first converted sample: 000: channel _0 or CHANNEL_ID_EN =0 001: channel _1 010: channel _2 011: channel _3 100: channel _4 101: channel _5 110: reserved 111: recovery_ error" /> - <BitField start="15" size="1" name="EMPTY" description="0: FIFO not empty 1: FIFO empty" /> - <BitField start="16" size="12" name="SAMPLE2" description="Value of second converted sample. This field is only valid if PACKED_READ is set else it is 0x0" /> - <BitField start="28" size="3" name="CHAN_ID2" description="Channel number of second converted sample This field is only valid if CHANNEL_ID_EN and PACKED_READ are set else it is 0x0" /> - <BitField start="31" size="1" name="EMPTY2" description="0: FIFO not empty 1: FIFO empty and PACKED_READ is set" /> - </Register> - <Register start="+0x0300+0" size="4" name="DESCRIPTOR0_[0]" access="Read/Write" description="Table 0 descriptor n, n= 0 to 7" reset_value="0x000090E0" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="3" name="CHANNEL_NR" description="0: convert input 0 1: convert input 1 2: convert input 2 3: convert input 3 4: convert input 4 5: convert input 5 6,7: reserved" /> - <BitField start="3" size="1" name="HALT" description="0: After this descriptor continue with the next descriptor. 1: halt after this descriptor is processed. Restart at a new trigger." /> - <BitField start="4" size="1" name="INTERRUPT" description="1: Raise interrupt when ADC result is available" /> - <BitField start="5" size="1" name="POWER_DOWN" description="1: Power down after this conversion." /> - <BitField start="6" size="2" name="BRANCH" description="00: Continue with next descriptor (wraps around after top). 01: Branch to the first descriptor in this table. 10: Swap tables and branch to the first descriptor of the new table. 11: reserved (do not store sample). Continue with next descriptor (wraps around after top)." /> - <BitField start="8" size="14" name="MATCH_VALUE" description="Evaluate this descriptor when descriptor timer value is equal to match value." /> - <BitField start="22" size="2" name="THRESHOLD_SEL" description="Indicates which threshold comparison level register set is to be used: 00: no comparison, 01: THR_A. 10: THR_B. 11: Reserved" /> - <BitField start="24" size="1" name="RESET_TIMER" description="1: reset descriptor timer." /> - <BitField start="25" size="6" name="RESERVED" description="Reserved" /> - <BitField start="31" size="1" name="UPDATE_TABLE" description="1: Update table with all 8 descriptors of this table. Descriptors of this table that are written without this bit set are not updated until any descriptor of this table is written with this bit set. This field is write only. A read returns 0x0." /> - </Register> - <Register start="+0x0300+4" size="4" name="DESCRIPTOR0_[1]" access="Read/Write" description="Table 0 descriptor n, n= 0 to 7" reset_value="0x000090E0" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="3" name="CHANNEL_NR" description="0: convert input 0 1: convert input 1 2: convert input 2 3: convert input 3 4: convert input 4 5: convert input 5 6,7: reserved" /> - <BitField start="3" size="1" name="HALT" description="0: After this descriptor continue with the next descriptor. 1: halt after this descriptor is processed. Restart at a new trigger." /> - <BitField start="4" size="1" name="INTERRUPT" description="1: Raise interrupt when ADC result is available" /> - <BitField start="5" size="1" name="POWER_DOWN" description="1: Power down after this conversion." /> - <BitField start="6" size="2" name="BRANCH" description="00: Continue with next descriptor (wraps around after top). 01: Branch to the first descriptor in this table. 10: Swap tables and branch to the first descriptor of the new table. 11: reserved (do not store sample). Continue with next descriptor (wraps around after top)." /> - <BitField start="8" size="14" name="MATCH_VALUE" description="Evaluate this descriptor when descriptor timer value is equal to match value." /> - <BitField start="22" size="2" name="THRESHOLD_SEL" description="Indicates which threshold comparison level register set is to be used: 00: no comparison, 01: THR_A. 10: THR_B. 11: Reserved" /> - <BitField start="24" size="1" name="RESET_TIMER" description="1: reset descriptor timer." /> - <BitField start="25" size="6" name="RESERVED" description="Reserved" /> - <BitField start="31" size="1" name="UPDATE_TABLE" description="1: Update table with all 8 descriptors of this table. Descriptors of this table that are written without this bit set are not updated until any descriptor of this table is written with this bit set. This field is write only. A read returns 0x0." /> - </Register> - <Register start="+0x0300+8" size="4" name="DESCRIPTOR0_[2]" access="Read/Write" description="Table 0 descriptor n, n= 0 to 7" reset_value="0x000090E0" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="3" name="CHANNEL_NR" description="0: convert input 0 1: convert input 1 2: convert input 2 3: convert input 3 4: convert input 4 5: convert input 5 6,7: reserved" /> - <BitField start="3" size="1" name="HALT" description="0: After this descriptor continue with the next descriptor. 1: halt after this descriptor is processed. Restart at a new trigger." /> - <BitField start="4" size="1" name="INTERRUPT" description="1: Raise interrupt when ADC result is available" /> - <BitField start="5" size="1" name="POWER_DOWN" description="1: Power down after this conversion." /> - <BitField start="6" size="2" name="BRANCH" description="00: Continue with next descriptor (wraps around after top). 01: Branch to the first descriptor in this table. 10: Swap tables and branch to the first descriptor of the new table. 11: reserved (do not store sample). Continue with next descriptor (wraps around after top)." /> - <BitField start="8" size="14" name="MATCH_VALUE" description="Evaluate this descriptor when descriptor timer value is equal to match value." /> - <BitField start="22" size="2" name="THRESHOLD_SEL" description="Indicates which threshold comparison level register set is to be used: 00: no comparison, 01: THR_A. 10: THR_B. 11: Reserved" /> - <BitField start="24" size="1" name="RESET_TIMER" description="1: reset descriptor timer." /> - <BitField start="25" size="6" name="RESERVED" description="Reserved" /> - <BitField start="31" size="1" name="UPDATE_TABLE" description="1: Update table with all 8 descriptors of this table. Descriptors of this table that are written without this bit set are not updated until any descriptor of this table is written with this bit set. This field is write only. A read returns 0x0." /> - </Register> - <Register start="+0x0300+12" size="4" name="DESCRIPTOR0_[3]" access="Read/Write" description="Table 0 descriptor n, n= 0 to 7" reset_value="0x000090E0" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="3" name="CHANNEL_NR" description="0: convert input 0 1: convert input 1 2: convert input 2 3: convert input 3 4: convert input 4 5: convert input 5 6,7: reserved" /> - <BitField start="3" size="1" name="HALT" description="0: After this descriptor continue with the next descriptor. 1: halt after this descriptor is processed. Restart at a new trigger." /> - <BitField start="4" size="1" name="INTERRUPT" description="1: Raise interrupt when ADC result is available" /> - <BitField start="5" size="1" name="POWER_DOWN" description="1: Power down after this conversion." /> - <BitField start="6" size="2" name="BRANCH" description="00: Continue with next descriptor (wraps around after top). 01: Branch to the first descriptor in this table. 10: Swap tables and branch to the first descriptor of the new table. 11: reserved (do not store sample). Continue with next descriptor (wraps around after top)." /> - <BitField start="8" size="14" name="MATCH_VALUE" description="Evaluate this descriptor when descriptor timer value is equal to match value." /> - <BitField start="22" size="2" name="THRESHOLD_SEL" description="Indicates which threshold comparison level register set is to be used: 00: no comparison, 01: THR_A. 10: THR_B. 11: Reserved" /> - <BitField start="24" size="1" name="RESET_TIMER" description="1: reset descriptor timer." /> - <BitField start="25" size="6" name="RESERVED" description="Reserved" /> - <BitField start="31" size="1" name="UPDATE_TABLE" description="1: Update table with all 8 descriptors of this table. Descriptors of this table that are written without this bit set are not updated until any descriptor of this table is written with this bit set. This field is write only. A read returns 0x0." /> - </Register> - <Register start="+0x0300+16" size="4" name="DESCRIPTOR0_[4]" access="Read/Write" description="Table 0 descriptor n, n= 0 to 7" reset_value="0x000090E0" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="3" name="CHANNEL_NR" description="0: convert input 0 1: convert input 1 2: convert input 2 3: convert input 3 4: convert input 4 5: convert input 5 6,7: reserved" /> - <BitField start="3" size="1" name="HALT" description="0: After this descriptor continue with the next descriptor. 1: halt after this descriptor is processed. Restart at a new trigger." /> - <BitField start="4" size="1" name="INTERRUPT" description="1: Raise interrupt when ADC result is available" /> - <BitField start="5" size="1" name="POWER_DOWN" description="1: Power down after this conversion." /> - <BitField start="6" size="2" name="BRANCH" description="00: Continue with next descriptor (wraps around after top). 01: Branch to the first descriptor in this table. 10: Swap tables and branch to the first descriptor of the new table. 11: reserved (do not store sample). Continue with next descriptor (wraps around after top)." /> - <BitField start="8" size="14" name="MATCH_VALUE" description="Evaluate this descriptor when descriptor timer value is equal to match value." /> - <BitField start="22" size="2" name="THRESHOLD_SEL" description="Indicates which threshold comparison level register set is to be used: 00: no comparison, 01: THR_A. 10: THR_B. 11: Reserved" /> - <BitField start="24" size="1" name="RESET_TIMER" description="1: reset descriptor timer." /> - <BitField start="25" size="6" name="RESERVED" description="Reserved" /> - <BitField start="31" size="1" name="UPDATE_TABLE" description="1: Update table with all 8 descriptors of this table. Descriptors of this table that are written without this bit set are not updated until any descriptor of this table is written with this bit set. This field is write only. A read returns 0x0." /> - </Register> - <Register start="+0x0300+20" size="4" name="DESCRIPTOR0_[5]" access="Read/Write" description="Table 0 descriptor n, n= 0 to 7" reset_value="0x000090E0" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="3" name="CHANNEL_NR" description="0: convert input 0 1: convert input 1 2: convert input 2 3: convert input 3 4: convert input 4 5: convert input 5 6,7: reserved" /> - <BitField start="3" size="1" name="HALT" description="0: After this descriptor continue with the next descriptor. 1: halt after this descriptor is processed. Restart at a new trigger." /> - <BitField start="4" size="1" name="INTERRUPT" description="1: Raise interrupt when ADC result is available" /> - <BitField start="5" size="1" name="POWER_DOWN" description="1: Power down after this conversion." /> - <BitField start="6" size="2" name="BRANCH" description="00: Continue with next descriptor (wraps around after top). 01: Branch to the first descriptor in this table. 10: Swap tables and branch to the first descriptor of the new table. 11: reserved (do not store sample). Continue with next descriptor (wraps around after top)." /> - <BitField start="8" size="14" name="MATCH_VALUE" description="Evaluate this descriptor when descriptor timer value is equal to match value." /> - <BitField start="22" size="2" name="THRESHOLD_SEL" description="Indicates which threshold comparison level register set is to be used: 00: no comparison, 01: THR_A. 10: THR_B. 11: Reserved" /> - <BitField start="24" size="1" name="RESET_TIMER" description="1: reset descriptor timer." /> - <BitField start="25" size="6" name="RESERVED" description="Reserved" /> - <BitField start="31" size="1" name="UPDATE_TABLE" description="1: Update table with all 8 descriptors of this table. Descriptors of this table that are written without this bit set are not updated until any descriptor of this table is written with this bit set. This field is write only. A read returns 0x0." /> - </Register> - <Register start="+0x0300+24" size="4" name="DESCRIPTOR0_[6]" access="Read/Write" description="Table 0 descriptor n, n= 0 to 7" reset_value="0x000090E0" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="3" name="CHANNEL_NR" description="0: convert input 0 1: convert input 1 2: convert input 2 3: convert input 3 4: convert input 4 5: convert input 5 6,7: reserved" /> - <BitField start="3" size="1" name="HALT" description="0: After this descriptor continue with the next descriptor. 1: halt after this descriptor is processed. Restart at a new trigger." /> - <BitField start="4" size="1" name="INTERRUPT" description="1: Raise interrupt when ADC result is available" /> - <BitField start="5" size="1" name="POWER_DOWN" description="1: Power down after this conversion." /> - <BitField start="6" size="2" name="BRANCH" description="00: Continue with next descriptor (wraps around after top). 01: Branch to the first descriptor in this table. 10: Swap tables and branch to the first descriptor of the new table. 11: reserved (do not store sample). Continue with next descriptor (wraps around after top)." /> - <BitField start="8" size="14" name="MATCH_VALUE" description="Evaluate this descriptor when descriptor timer value is equal to match value." /> - <BitField start="22" size="2" name="THRESHOLD_SEL" description="Indicates which threshold comparison level register set is to be used: 00: no comparison, 01: THR_A. 10: THR_B. 11: Reserved" /> - <BitField start="24" size="1" name="RESET_TIMER" description="1: reset descriptor timer." /> - <BitField start="25" size="6" name="RESERVED" description="Reserved" /> - <BitField start="31" size="1" name="UPDATE_TABLE" description="1: Update table with all 8 descriptors of this table. Descriptors of this table that are written without this bit set are not updated until any descriptor of this table is written with this bit set. This field is write only. A read returns 0x0." /> - </Register> - <Register start="+0x0300+28" size="4" name="DESCRIPTOR0_[7]" access="Read/Write" description="Table 0 descriptor n, n= 0 to 7" reset_value="0x000090E0" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="3" name="CHANNEL_NR" description="0: convert input 0 1: convert input 1 2: convert input 2 3: convert input 3 4: convert input 4 5: convert input 5 6,7: reserved" /> - <BitField start="3" size="1" name="HALT" description="0: After this descriptor continue with the next descriptor. 1: halt after this descriptor is processed. Restart at a new trigger." /> - <BitField start="4" size="1" name="INTERRUPT" description="1: Raise interrupt when ADC result is available" /> - <BitField start="5" size="1" name="POWER_DOWN" description="1: Power down after this conversion." /> - <BitField start="6" size="2" name="BRANCH" description="00: Continue with next descriptor (wraps around after top). 01: Branch to the first descriptor in this table. 10: Swap tables and branch to the first descriptor of the new table. 11: reserved (do not store sample). Continue with next descriptor (wraps around after top)." /> - <BitField start="8" size="14" name="MATCH_VALUE" description="Evaluate this descriptor when descriptor timer value is equal to match value." /> - <BitField start="22" size="2" name="THRESHOLD_SEL" description="Indicates which threshold comparison level register set is to be used: 00: no comparison, 01: THR_A. 10: THR_B. 11: Reserved" /> - <BitField start="24" size="1" name="RESET_TIMER" description="1: reset descriptor timer." /> - <BitField start="25" size="6" name="RESERVED" description="Reserved" /> - <BitField start="31" size="1" name="UPDATE_TABLE" description="1: Update table with all 8 descriptors of this table. Descriptors of this table that are written without this bit set are not updated until any descriptor of this table is written with this bit set. This field is write only. A read returns 0x0." /> - </Register> - <Register start="+0x0320+0" size="4" name="DESCRIPTOR1_[0]" access="Read/Write" description="Table 1 descriptors n, n=0 to 7" reset_value="0x000090E0" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="3" name="CHANNEL_NR" description="0: convert input 0 1: convert input 1 2: convert input 2 3: convert input 3 4: convert input 4 5: convert input 5 6,7: reserved" /> - <BitField start="3" size="1" name="HALT" description="0: After this descriptor continue with the next descriptor. 1: halt after this descriptor is processed. Restart at a new trigger." /> - <BitField start="4" size="1" name="INTERRUPT" description="1: Raise interrupt when ADC result is available" /> - <BitField start="5" size="1" name="POWER_DOWN" description="1: Power down after this conversion." /> - <BitField start="6" size="2" name="BRANCH" description="00: Continue with next descriptor (wraps around after top). 01: Branch to the first descriptor in this table. 10: Swap tables and branch to the first descriptor of the new table. 11: reserved (do not store sample). Continue with next descriptor (wraps around after top)." /> - <BitField start="8" size="14" name="MATCH_VALUE" description="Evaluate this descriptor when descriptor timer value is equal to match value." /> - <BitField start="22" size="2" name="THRESHOLD_SEL" description="Indicates which threshold comparison level register set is to be used: 00: no comparison, 01: THR_A. 10: THR_B. 11: Reserved" /> - <BitField start="24" size="1" name="RESET_TIMER" description="1: reset descriptor timer." /> - <BitField start="25" size="6" name="RESERVED" description="Reserved" /> - <BitField start="31" size="1" name="UPDATE_TABLE" description="1: Update table with all 8 descriptors of this table. Descriptors of this table that are written without this bit set are not updated until any descriptor of this table is written with this bit set. This field is write only. A read returns 0x0." /> - </Register> - <Register start="+0x0320+4" size="4" name="DESCRIPTOR1_[1]" access="Read/Write" description="Table 1 descriptors n, n=0 to 7" reset_value="0x000090E0" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="3" name="CHANNEL_NR" description="0: convert input 0 1: convert input 1 2: convert input 2 3: convert input 3 4: convert input 4 5: convert input 5 6,7: reserved" /> - <BitField start="3" size="1" name="HALT" description="0: After this descriptor continue with the next descriptor. 1: halt after this descriptor is processed. Restart at a new trigger." /> - <BitField start="4" size="1" name="INTERRUPT" description="1: Raise interrupt when ADC result is available" /> - <BitField start="5" size="1" name="POWER_DOWN" description="1: Power down after this conversion." /> - <BitField start="6" size="2" name="BRANCH" description="00: Continue with next descriptor (wraps around after top). 01: Branch to the first descriptor in this table. 10: Swap tables and branch to the first descriptor of the new table. 11: reserved (do not store sample). Continue with next descriptor (wraps around after top)." /> - <BitField start="8" size="14" name="MATCH_VALUE" description="Evaluate this descriptor when descriptor timer value is equal to match value." /> - <BitField start="22" size="2" name="THRESHOLD_SEL" description="Indicates which threshold comparison level register set is to be used: 00: no comparison, 01: THR_A. 10: THR_B. 11: Reserved" /> - <BitField start="24" size="1" name="RESET_TIMER" description="1: reset descriptor timer." /> - <BitField start="25" size="6" name="RESERVED" description="Reserved" /> - <BitField start="31" size="1" name="UPDATE_TABLE" description="1: Update table with all 8 descriptors of this table. Descriptors of this table that are written without this bit set are not updated until any descriptor of this table is written with this bit set. This field is write only. A read returns 0x0." /> - </Register> - <Register start="+0x0320+8" size="4" name="DESCRIPTOR1_[2]" access="Read/Write" description="Table 1 descriptors n, n=0 to 7" reset_value="0x000090E0" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="3" name="CHANNEL_NR" description="0: convert input 0 1: convert input 1 2: convert input 2 3: convert input 3 4: convert input 4 5: convert input 5 6,7: reserved" /> - <BitField start="3" size="1" name="HALT" description="0: After this descriptor continue with the next descriptor. 1: halt after this descriptor is processed. Restart at a new trigger." /> - <BitField start="4" size="1" name="INTERRUPT" description="1: Raise interrupt when ADC result is available" /> - <BitField start="5" size="1" name="POWER_DOWN" description="1: Power down after this conversion." /> - <BitField start="6" size="2" name="BRANCH" description="00: Continue with next descriptor (wraps around after top). 01: Branch to the first descriptor in this table. 10: Swap tables and branch to the first descriptor of the new table. 11: reserved (do not store sample). Continue with next descriptor (wraps around after top)." /> - <BitField start="8" size="14" name="MATCH_VALUE" description="Evaluate this descriptor when descriptor timer value is equal to match value." /> - <BitField start="22" size="2" name="THRESHOLD_SEL" description="Indicates which threshold comparison level register set is to be used: 00: no comparison, 01: THR_A. 10: THR_B. 11: Reserved" /> - <BitField start="24" size="1" name="RESET_TIMER" description="1: reset descriptor timer." /> - <BitField start="25" size="6" name="RESERVED" description="Reserved" /> - <BitField start="31" size="1" name="UPDATE_TABLE" description="1: Update table with all 8 descriptors of this table. Descriptors of this table that are written without this bit set are not updated until any descriptor of this table is written with this bit set. This field is write only. A read returns 0x0." /> - </Register> - <Register start="+0x0320+12" size="4" name="DESCRIPTOR1_[3]" access="Read/Write" description="Table 1 descriptors n, n=0 to 7" reset_value="0x000090E0" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="3" name="CHANNEL_NR" description="0: convert input 0 1: convert input 1 2: convert input 2 3: convert input 3 4: convert input 4 5: convert input 5 6,7: reserved" /> - <BitField start="3" size="1" name="HALT" description="0: After this descriptor continue with the next descriptor. 1: halt after this descriptor is processed. Restart at a new trigger." /> - <BitField start="4" size="1" name="INTERRUPT" description="1: Raise interrupt when ADC result is available" /> - <BitField start="5" size="1" name="POWER_DOWN" description="1: Power down after this conversion." /> - <BitField start="6" size="2" name="BRANCH" description="00: Continue with next descriptor (wraps around after top). 01: Branch to the first descriptor in this table. 10: Swap tables and branch to the first descriptor of the new table. 11: reserved (do not store sample). Continue with next descriptor (wraps around after top)." /> - <BitField start="8" size="14" name="MATCH_VALUE" description="Evaluate this descriptor when descriptor timer value is equal to match value." /> - <BitField start="22" size="2" name="THRESHOLD_SEL" description="Indicates which threshold comparison level register set is to be used: 00: no comparison, 01: THR_A. 10: THR_B. 11: Reserved" /> - <BitField start="24" size="1" name="RESET_TIMER" description="1: reset descriptor timer." /> - <BitField start="25" size="6" name="RESERVED" description="Reserved" /> - <BitField start="31" size="1" name="UPDATE_TABLE" description="1: Update table with all 8 descriptors of this table. Descriptors of this table that are written without this bit set are not updated until any descriptor of this table is written with this bit set. This field is write only. A read returns 0x0." /> - </Register> - <Register start="+0x0320+16" size="4" name="DESCRIPTOR1_[4]" access="Read/Write" description="Table 1 descriptors n, n=0 to 7" reset_value="0x000090E0" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="3" name="CHANNEL_NR" description="0: convert input 0 1: convert input 1 2: convert input 2 3: convert input 3 4: convert input 4 5: convert input 5 6,7: reserved" /> - <BitField start="3" size="1" name="HALT" description="0: After this descriptor continue with the next descriptor. 1: halt after this descriptor is processed. Restart at a new trigger." /> - <BitField start="4" size="1" name="INTERRUPT" description="1: Raise interrupt when ADC result is available" /> - <BitField start="5" size="1" name="POWER_DOWN" description="1: Power down after this conversion." /> - <BitField start="6" size="2" name="BRANCH" description="00: Continue with next descriptor (wraps around after top). 01: Branch to the first descriptor in this table. 10: Swap tables and branch to the first descriptor of the new table. 11: reserved (do not store sample). Continue with next descriptor (wraps around after top)." /> - <BitField start="8" size="14" name="MATCH_VALUE" description="Evaluate this descriptor when descriptor timer value is equal to match value." /> - <BitField start="22" size="2" name="THRESHOLD_SEL" description="Indicates which threshold comparison level register set is to be used: 00: no comparison, 01: THR_A. 10: THR_B. 11: Reserved" /> - <BitField start="24" size="1" name="RESET_TIMER" description="1: reset descriptor timer." /> - <BitField start="25" size="6" name="RESERVED" description="Reserved" /> - <BitField start="31" size="1" name="UPDATE_TABLE" description="1: Update table with all 8 descriptors of this table. Descriptors of this table that are written without this bit set are not updated until any descriptor of this table is written with this bit set. This field is write only. A read returns 0x0." /> - </Register> - <Register start="+0x0320+20" size="4" name="DESCRIPTOR1_[5]" access="Read/Write" description="Table 1 descriptors n, n=0 to 7" reset_value="0x000090E0" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="3" name="CHANNEL_NR" description="0: convert input 0 1: convert input 1 2: convert input 2 3: convert input 3 4: convert input 4 5: convert input 5 6,7: reserved" /> - <BitField start="3" size="1" name="HALT" description="0: After this descriptor continue with the next descriptor. 1: halt after this descriptor is processed. Restart at a new trigger." /> - <BitField start="4" size="1" name="INTERRUPT" description="1: Raise interrupt when ADC result is available" /> - <BitField start="5" size="1" name="POWER_DOWN" description="1: Power down after this conversion." /> - <BitField start="6" size="2" name="BRANCH" description="00: Continue with next descriptor (wraps around after top). 01: Branch to the first descriptor in this table. 10: Swap tables and branch to the first descriptor of the new table. 11: reserved (do not store sample). Continue with next descriptor (wraps around after top)." /> - <BitField start="8" size="14" name="MATCH_VALUE" description="Evaluate this descriptor when descriptor timer value is equal to match value." /> - <BitField start="22" size="2" name="THRESHOLD_SEL" description="Indicates which threshold comparison level register set is to be used: 00: no comparison, 01: THR_A. 10: THR_B. 11: Reserved" /> - <BitField start="24" size="1" name="RESET_TIMER" description="1: reset descriptor timer." /> - <BitField start="25" size="6" name="RESERVED" description="Reserved" /> - <BitField start="31" size="1" name="UPDATE_TABLE" description="1: Update table with all 8 descriptors of this table. Descriptors of this table that are written without this bit set are not updated until any descriptor of this table is written with this bit set. This field is write only. A read returns 0x0." /> - </Register> - <Register start="+0x0320+24" size="4" name="DESCRIPTOR1_[6]" access="Read/Write" description="Table 1 descriptors n, n=0 to 7" reset_value="0x000090E0" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="3" name="CHANNEL_NR" description="0: convert input 0 1: convert input 1 2: convert input 2 3: convert input 3 4: convert input 4 5: convert input 5 6,7: reserved" /> - <BitField start="3" size="1" name="HALT" description="0: After this descriptor continue with the next descriptor. 1: halt after this descriptor is processed. Restart at a new trigger." /> - <BitField start="4" size="1" name="INTERRUPT" description="1: Raise interrupt when ADC result is available" /> - <BitField start="5" size="1" name="POWER_DOWN" description="1: Power down after this conversion." /> - <BitField start="6" size="2" name="BRANCH" description="00: Continue with next descriptor (wraps around after top). 01: Branch to the first descriptor in this table. 10: Swap tables and branch to the first descriptor of the new table. 11: reserved (do not store sample). Continue with next descriptor (wraps around after top)." /> - <BitField start="8" size="14" name="MATCH_VALUE" description="Evaluate this descriptor when descriptor timer value is equal to match value." /> - <BitField start="22" size="2" name="THRESHOLD_SEL" description="Indicates which threshold comparison level register set is to be used: 00: no comparison, 01: THR_A. 10: THR_B. 11: Reserved" /> - <BitField start="24" size="1" name="RESET_TIMER" description="1: reset descriptor timer." /> - <BitField start="25" size="6" name="RESERVED" description="Reserved" /> - <BitField start="31" size="1" name="UPDATE_TABLE" description="1: Update table with all 8 descriptors of this table. Descriptors of this table that are written without this bit set are not updated until any descriptor of this table is written with this bit set. This field is write only. A read returns 0x0." /> - </Register> - <Register start="+0x0320+28" size="4" name="DESCRIPTOR1_[7]" access="Read/Write" description="Table 1 descriptors n, n=0 to 7" reset_value="0x000090E0" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="3" name="CHANNEL_NR" description="0: convert input 0 1: convert input 1 2: convert input 2 3: convert input 3 4: convert input 4 5: convert input 5 6,7: reserved" /> - <BitField start="3" size="1" name="HALT" description="0: After this descriptor continue with the next descriptor. 1: halt after this descriptor is processed. Restart at a new trigger." /> - <BitField start="4" size="1" name="INTERRUPT" description="1: Raise interrupt when ADC result is available" /> - <BitField start="5" size="1" name="POWER_DOWN" description="1: Power down after this conversion." /> - <BitField start="6" size="2" name="BRANCH" description="00: Continue with next descriptor (wraps around after top). 01: Branch to the first descriptor in this table. 10: Swap tables and branch to the first descriptor of the new table. 11: reserved (do not store sample). Continue with next descriptor (wraps around after top)." /> - <BitField start="8" size="14" name="MATCH_VALUE" description="Evaluate this descriptor when descriptor timer value is equal to match value." /> - <BitField start="22" size="2" name="THRESHOLD_SEL" description="Indicates which threshold comparison level register set is to be used: 00: no comparison, 01: THR_A. 10: THR_B. 11: Reserved" /> - <BitField start="24" size="1" name="RESET_TIMER" description="1: reset descriptor timer." /> - <BitField start="25" size="6" name="RESERVED" description="Reserved" /> - <BitField start="31" size="1" name="UPDATE_TABLE" description="1: Update table with all 8 descriptors of this table. Descriptors of this table that are written without this bit set are not updated until any descriptor of this table is written with this bit set. This field is write only. A read returns 0x0." /> - </Register> - <Register start="+0x0F00" size="4" name="CLR_EN0" access="WriteOnly" description="Interrupt 0 clear mask" reset_value="0x00000000" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="7" name="CEN0" description="Interrupt clear enable" /> - <BitField start="7" size="25" name="RESERVED" description="Reserved" /> - </Register> - <Register start="+0x0F04" size="4" name="SET_EN0" access="WriteOnly" description="Interrupt 0 set mask" reset_value="0x00000000" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="7" name="SEN0" description="Interrupt set enable" /> - <BitField start="7" size="25" name="RESERVED" description="Reserved" /> - </Register> - <Register start="+0x0F08" size="4" name="MASK0" access="ReadOnly" description="Interrupt 0 mask" reset_value="0x00000000" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="7" name="M0" description="Interrupt enable" /> - <BitField start="7" size="25" name="RESERVED" description="Reserved" /> - </Register> - <Register start="+0x0F0C" size="4" name="STATUS0" access="ReadOnly" description="Interrupt 0 status. Interrupt 0 contains FIFO fill level, descriptor status and ADC range under/overflow" reset_value="0x00000000" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="1" name="FIFO_FULL" description="0: number of samples in FIFO less than or equal to FIFO_LEVEL 1: number of samples in FIFO is more than FIFO_LEVEL" /> - <BitField start="1" size="1" name="FIFO_EMPTY" description="0: FIFO is not empty 1: FIFO is empty" /> - <BitField start="2" size="1" name="FIFO_OVERFLOW" description="FIFO was full; conversion sample is not stored and lost" /> - <BitField start="3" size="1" name="DSCR_DONE" description="The descriptor INTERRUPT field was enabled and its sample is converted." /> - <BitField start="4" size="1" name="DSCR_ERROR" description="The ADC was not fully woken up when a sample was converted and the conversion results is unreliable" /> - <BitField start="5" size="1" name="ADC_OVF" description="Converted sample value was over range of the 12 bit output code." /> - <BitField start="6" size="1" name="ADC_UNF" description="Converted sample value was under range of the 12 bit output code." /> - <BitField start="7" size="25" name="RESERVED" description="Reserved" /> - </Register> - <Register start="+0x0F10" size="4" name="CLR_STAT0" access="WriteOnly" description="Interrupt 0 clear status" reset_value="0x00000000" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="7" name="CSTAT0" description="Interrupt clear status" /> - <BitField start="7" size="25" name="RESERVED" description="Reserved" /> - </Register> - <Register start="+0x0F14" size="4" name="SET_STAT0" access="WriteOnly" description="Interrupt 0 set status" reset_value="0x00000000" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="7" name="SSTAT0" description="Interrupt set status" /> - <BitField start="7" size="25" name="RESERVED" description="Reserved" /> - </Register> - <Register start="+0x0F20" size="4" name="CLR_EN1" access="WriteOnly" description="Interrupt 1 mask clear enable." reset_value="0x00000000" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="30" name="CEN1" description="Interrupt clear enable" /> - <BitField start="30" size="2" name="RESERVED" description="Reserved" /> - </Register> - <Register start="+0x0F24" size="4" name="SET_EN1" access="WriteOnly" description="Interrupt 1 mask set enable" reset_value="0x00000000" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="30" name="SEN1" description="Interrupt set enable" /> - <BitField start="30" size="2" name="RESERVED" description="Reserved" /> - </Register> - <Register start="+0x0F28" size="4" name="MASK1" access="ReadOnly" description="Interrupt 1 mask" reset_value="0x00000000" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="30" name="M1" description="Interrupt enable" /> - <BitField start="30" size="2" name="RESERVED" description="Reserved" /> - </Register> - <Register start="+0x0F2C" size="4" name="STATUS1" access="ReadOnly" description="Interrupt 1 status. Interrupt 1 contains window comparator results and register last LAST_SAMPLE[M] overrun." reset_value="0x00000000" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="1" name="THCMP_BRANGE0" description="Input channel 0 result below range" /> - <BitField start="1" size="1" name="THCMP_ARANGE0" description="Input channel 0 result above range" /> - <BitField start="2" size="1" name="THCMP_DCROSS0" description="Input channel 0 result downward threshold crossing detected" /> - <BitField start="3" size="1" name="THCMP_UCROSS0" description="Input channel 0 result upward threshold crossing detected" /> - <BitField start="4" size="1" name="OVERRUN_0" description="A new conversion on channel m completed and has overwritten the previous contents of register LAST_SAMPLE [0] before it has been read" /> - <BitField start="5" size="1" name="THCMP_BRANGE1" description="Input channel 1 result below range" /> - <BitField start="6" size="1" name="THCMP_ARANGE1" description="Input channel 1 result above range" /> - <BitField start="7" size="1" name="THCMP_DCROSS1" description="Input channel 1 result downward threshold crossing detected" /> - <BitField start="8" size="1" name="THCMP_UCROSS1" description="Input channel 1 result upward threshold crossing detected" /> - <BitField start="9" size="1" name="OVERRUN_1" description="A new conversion on channel m completed and has overwritten the previous contents of register LAST_SAMPLE [1] before it has been read" /> - <BitField start="10" size="1" name="THCMP_BRANGE2" description="Input channel 2 result below range" /> - <BitField start="11" size="1" name="THCMP_ARANGE2" description="Input channel 2 result above range" /> - <BitField start="12" size="1" name="THCMP_DCROSS2" description="Input channel 2 result downward threshold crossing detected" /> - <BitField start="13" size="1" name="THCMP_UCROSS2" description="Input channel 2 result upward threshold crossing detected" /> - <BitField start="14" size="1" name="OVERRUN_2" description="A new conversion on channel m completed and has overwritten the previous contents of register LAST_SAMPLE [2] before it has been read" /> - <BitField start="15" size="1" name="THCMP_BRANGE3" description="Input channel 3 result below range" /> - <BitField start="16" size="1" name="THCMP_ARANGE3" description="Input channel 3 result above range" /> - <BitField start="17" size="1" name="THCMP_DCROSS3" description="Input channel 3 result downward threshold crossing detected" /> - <BitField start="18" size="1" name="THCMP_UCROSS3" description="Input channel 3 result upward threshold crossing detected" /> - <BitField start="19" size="1" name="OVERRUN_3" description="A new conversion on channel m completed and has overwritten the previous contents of register LAST_SAMPLE [3] before it has been read" /> - <BitField start="20" size="1" name="THCMP_BRANGE4" description="Input channel 4 result below range" /> - <BitField start="21" size="1" name="THCMP_ARANGE4" description="Input channel 4 result above range" /> - <BitField start="22" size="1" name="THCMP_DCROSS4" description="Input channel 4 result downward threshold crossing detected" /> - <BitField start="23" size="1" name="THCMP_UCROSS4" description="Input channel 4 result upward threshold crossing detected" /> - <BitField start="24" size="1" name="OVERRUN_4" description="A new conversion on channel m completed and has overwritten the previous contents of register LAST_SAMPLE [4] before it has been read" /> - <BitField start="25" size="1" name="THCMP_BRANGE5" description="Input channel 5 result below range" /> - <BitField start="26" size="1" name="THCMP_ARANGE5" description="Input channel 5 result above range" /> - <BitField start="27" size="1" name="THCMP_DCROSS5" description="Input channel 5 result downward threshold crossing detected" /> - <BitField start="28" size="1" name="THCMP_UCROSS5" description="Input channel 5 result upward threshold crossing detected" /> - <BitField start="29" size="1" name="OVERRUN_5" description="A new conversion on channel m completed and has overwritten the previous contents of register LAST_SAMPLE [5] before it has been read" /> - <BitField start="30" size="2" name="RESERVED" description="Reserved." /> - </Register> - <Register start="+0x0F30" size="4" name="CLR_STAT1" access="WriteOnly" description="Interrupt 1 clear status" reset_value="0x00000000" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="30" name="CSTAT1" description="Interrupt clear status" /> - <BitField start="30" size="2" name="RESERVED" description="Reserved." /> - </Register> - <Register start="+0x0F34" size="4" name="SET_STAT1" access="WriteOnly" description="Interrupt 1 set status" reset_value="0x00000000" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="30" name="SSTAT1" description="Interrupt set status" /> - <BitField start="30" size="2" name="RESERVED" description="Reserved." /> - </Register> - </RegisterGroup> <RegisterGroup name="GPIO_PORT" start="0x400F4000" description="GPIO port "> <Register start="+0x0000+0" size="1" name="B[0]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF"> <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." /> @@ -30767,2213 +29958,6 @@ <BitField start="31" size="1" name="NOTP31" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." /> </Register> </RegisterGroup> - <RegisterGroup name="SPI" start="0x40100000" description="SPI "> - <Register start="+0x000" size="4" name="CR" access="Read/Write" description="SPI Control Register. This register controls the operation of the SPI." reset_value="0x00" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> - <BitField start="2" size="1" name="BITENABLE" description="The SPI controller sends and receives 8 bits of data per transfer."> - <Enum name="THE_SPI_CONTROLLER_S" start="1" description="The SPI controller sends and receives the number of bits selected by bits 11:8." /> - </BitField> - <BitField start="3" size="1" name="CPHA" description="Clock phase control determines the relationship between the data and the clock on SPI transfers, and controls when a slave transfer is defined as starting and ending."> - <Enum name="FIRST_EDGE" start="0" description="Data is sampled on the first clock edge of SCK. A transfer starts and ends with activation and deactivation of the SSEL signal." /> - <Enum name="SECOND_EDGE" start="1" description="Data is sampled on the second clock edge of the SCK. A transfer starts with the first clock edge, and ends with the last sampling edge when the SSEL signal is active." /> - </BitField> - <BitField start="4" size="1" name="CPOL" description="Clock polarity control."> - <Enum name="SCK_IS_ACTIVE_HIGH_" start="0" description="SCK is active high." /> - <Enum name="SCK_IS_ACTIVE_LOW_" start="1" description="SCK is active low." /> - </BitField> - <BitField start="5" size="1" name="MSTR" description="Master mode select."> - <Enum name="SLAVE" start="0" description="The SPI operates in Slave mode." /> - <Enum name="MASTER" start="1" description="The SPI operates in Master mode." /> - </BitField> - <BitField start="6" size="1" name="LSBF" description="LSB First controls which direction each byte is shifted when transferred."> - <Enum name="MSB" start="0" description="SPI data is transferred MSB (bit 7) first." /> - <Enum name="LSB" start="1" description="SPI data is transferred LSB (bit 0) first." /> - </BitField> - <BitField start="7" size="1" name="SPIE" description="Serial peripheral interrupt enable."> - <Enum name="INTBLOCK" start="0" description="SPI interrupts are inhibited." /> - <Enum name="HWINT" start="1" description="A hardware interrupt is generated each time the SPIF or MODF bits are activated." /> - </BitField> - <BitField start="8" size="4" name="BITS" description="When bit 2 of this register is 1, this field controls the number of bits per transfer:"> - <Enum name="8_BITS_PER_TRANSFER" start="0x8" description="8 bits per transfer" /> - <Enum name="9_BITS_PER_TRANSFER" start="0x9" description="9 bits per transfer" /> - <Enum name="10_BITS_PER_TRANSFER" start="0xA" description="10 bits per transfer" /> - <Enum name="11_BITS_PER_TRANSFER" start="0xB" description="11 bits per transfer" /> - <Enum name="12_BITS_PER_TRANSFER" start="0xC" description="12 bits per transfer" /> - <Enum name="13_BITS_PER_TRANSFER" start="0xD" description="13 bits per transfer" /> - <Enum name="14_BITS_PER_TRANSFER" start="0xE" description="14 bits per transfer" /> - <Enum name="15_BITS_PER_TRANSFER" start="0xF" description="15 bits per transfer" /> - <Enum name="16_BITS_PER_TRANSFER" start="0x0" description="16 bits per transfer" /> - </BitField> - <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> - </Register> - <Register start="+0x004" size="4" name="SR" access="ReadOnly" description="SPI Status Register. This register shows the status of the SPI." reset_value="0x00" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="3" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> - <BitField start="3" size="1" name="ABRT" description="Slave abort. When 1, this bit indicates that a slave abort has occurred. This bit is cleared by reading this register." /> - <BitField start="4" size="1" name="MODF" description="Mode fault. when 1, this bit indicates that a Mode fault error has occurred. This bit is cleared by reading this register, then writing the SPI0 control register." /> - <BitField start="5" size="1" name="ROVR" description="Read overrun. When 1, this bit indicates that a read overrun has occurred. This bit is cleared by reading this register." /> - <BitField start="6" size="1" name="WCOL" description="Write collision. When 1, this bit indicates that a write collision has occurred. This bit is cleared by reading this register, then accessing the SPI Data Register." /> - <BitField start="7" size="1" name="SPIF" description="SPI transfer complete flag. When 1, this bit indicates when a SPI data transfer is complete. When a master, this bit is set at the end of the last cycle of the transfer. When a slave, this bit is set on the last data sampling edge of the SCK. This bit is cleared by first reading this register, then accessing the SPI Data Register. Note: this is not the SPI interrupt flag. This flag is found in the SPINT register." /> - <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> - </Register> - <Register start="+0x008" size="4" name="DR" access="None" description="SPI Data Register. This bi-directional register provides the transmit and receive data for the SPI. Transmit data is provided to the SPI0 by writing to this register. Data received by the SPI0 can be read from this register." reset_value="0x00" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="8" name="DATALOW" description="SPI Bi-directional data port." /> - <BitField start="8" size="8" name="DATAHIGH" description="If bit 2 of the SPCR is 1 and bits 11:8 are other than 1000, some or all of these bits contain the additional transmit and receive bits. When less than 16 bits are selected, the more significant among these bits read as zeroes." /> - <BitField start="16" size="16" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> - </Register> - <Register start="+0x00C" size="4" name="CCR" access="Read/Write" description="SPI Clock Counter Register. This register controls the frequency of a master's SCK0." reset_value="0x00" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="8" name="COUNTER" description="SPI0 Clock counter setting." /> - <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> - </Register> - <Register start="+0x010" size="4" name="TCR" access="Read/Write" description="SPI Test Control register. For functional testing only." reset_value="0x00" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="1" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> - <BitField start="1" size="7" name="TEST" description="SPI test mode. When 0, the SPI operates normally. When 1, SCK will always be on, independent of master mode select and data availability setting." /> - <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> - </Register> - <Register start="+0x014" size="4" name="TSR" access="Read/Write" description="SPI Test Status register. For functional testing only." reset_value="0x00" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="3" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> - <BitField start="3" size="1" name="ABRT" description="Slave abort." /> - <BitField start="4" size="1" name="MODF" description="Mode fault." /> - <BitField start="5" size="1" name="ROVR" description="Read overrun." /> - <BitField start="6" size="1" name="WCOL" description="Write collision." /> - <BitField start="7" size="1" name="SPIF" description="SPI transfer complete flag." /> - <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> - </Register> - <Register start="+0x01C" size="4" name="INT" access="Read/Write" description="SPI Interrupt Flag. This register contains the interrupt flag for the SPI interface." reset_value="0x00" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="1" name="SPIF" description="SPI interrupt flag. Set by the SPI interface to generate an interrupt. Cleared by writing a 1 to this bit. Note: this bit will be set once when SPIE = 1 and at least one of SPIF and WCOL bits is 1. However, only when the SPI Interrupt bit is set and SPI0 Interrupt is enabled in the NVIC, SPI based interrupt can be processed by interrupt handling software." /> - <BitField start="1" size="7" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> - <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> - </Register> - </RegisterGroup> - <RegisterGroup name="SGPIO" start="0x40101000" description="Serial GPIO (SGPIO)"> - <Register start="+0x0000+0" size="4" name="OUT_MUX_CFG[0]" access="Read/Write" description="Pin multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="4" name="P_OUT_CFG" description="Output control of output SGPIOn. All other values are reserved."> - <Enum name="DOUT_DOUTM1" start="0x0" description="dout_doutm1 (1-bit mode)" /> - <Enum name="DOUT_DOUTM2A" start="0x1" description="dout_doutm2a (2-bit mode 2a)" /> - <Enum name="DOUT_DOUTM2B" start="0x2" description="dout_doutm2b (2-bit mode 2b)" /> - <Enum name="DOUT_DOUTM2C" start="0x3" description="dout_doutm2c (2-bit mode 2c)" /> - <Enum name="GPIO_OUT_LEVEL_SET" start="0x4" description="gpio_out (level set by GPIO_OUTREG)" /> - <Enum name="DOUT_DOUTM4A" start="0x5" description="dout_doutm4a (4-bit mode 4a)" /> - <Enum name="DOUT_DOUTM4B" start="0x6" description="dout_doutm4b (4-bit mode 4b)" /> - <Enum name="DOUT_DOUTM4C" start="0x7" description="dout_doutm4c (4-bit mode 4c)" /> - <Enum name="CLK_OUT" start="0x8" description="clk_out" /> - <Enum name="DOUT_DOUTM8A" start="0x9" description="dout_doutm8a (8-bit mode 8a)" /> - <Enum name="DOUT_DOUTM8B" start="0xA" description="dout_doutm8b (8-bit mode 8b)" /> - <Enum name="DOUT_DOUTM8C" start="0xB" description="dout_doutm8c (8-bit mode 8c)" /> - </BitField> - <BitField start="4" size="3" name="P_OE_CFG" description="Output enable source. All other values are reserved."> - <Enum name="GPIO_OE_STATE_SET_B" start="0x0" description="gpio_oe (state set by GPIO_OEREG)" /> - <Enum name="DOUT_OEM1_1_BIT_MOD" start="0x4" description="dout_oem1 (1-bit mode)" /> - <Enum name="DOUT_OEM2_2_BIT_MOD" start="0x5" description="dout_oem2 (2-bit mode)" /> - <Enum name="DOUT_OEM4_4_BIT_MOD" start="0x6" description="dout_oem4 (4-bit mode)" /> - <Enum name="DOUT_OEM8_8_BIT_MOD" start="0x7" description="dout_oem8 (8-bit mode)" /> - </BitField> - <BitField start="7" size="25" name="RESERVED" description="Reserved." /> - </Register> - <Register start="+0x0000+4" size="4" name="OUT_MUX_CFG[1]" access="Read/Write" description="Pin multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="4" name="P_OUT_CFG" description="Output control of output SGPIOn. All other values are reserved."> - <Enum name="DOUT_DOUTM1" start="0x0" description="dout_doutm1 (1-bit mode)" /> - <Enum name="DOUT_DOUTM2A" start="0x1" description="dout_doutm2a (2-bit mode 2a)" /> - <Enum name="DOUT_DOUTM2B" start="0x2" description="dout_doutm2b (2-bit mode 2b)" /> - <Enum name="DOUT_DOUTM2C" start="0x3" description="dout_doutm2c (2-bit mode 2c)" /> - <Enum name="GPIO_OUT_LEVEL_SET" start="0x4" description="gpio_out (level set by GPIO_OUTREG)" /> - <Enum name="DOUT_DOUTM4A" start="0x5" description="dout_doutm4a (4-bit mode 4a)" /> - <Enum name="DOUT_DOUTM4B" start="0x6" description="dout_doutm4b (4-bit mode 4b)" /> - <Enum name="DOUT_DOUTM4C" start="0x7" description="dout_doutm4c (4-bit mode 4c)" /> - <Enum name="CLK_OUT" start="0x8" description="clk_out" /> - <Enum name="DOUT_DOUTM8A" start="0x9" description="dout_doutm8a (8-bit mode 8a)" /> - <Enum name="DOUT_DOUTM8B" start="0xA" description="dout_doutm8b (8-bit mode 8b)" /> - <Enum name="DOUT_DOUTM8C" start="0xB" description="dout_doutm8c (8-bit mode 8c)" /> - </BitField> - <BitField start="4" size="3" name="P_OE_CFG" description="Output enable source. All other values are reserved."> - <Enum name="GPIO_OE_STATE_SET_B" start="0x0" description="gpio_oe (state set by GPIO_OEREG)" /> - <Enum name="DOUT_OEM1_1_BIT_MOD" start="0x4" description="dout_oem1 (1-bit mode)" /> - <Enum name="DOUT_OEM2_2_BIT_MOD" start="0x5" description="dout_oem2 (2-bit mode)" /> - <Enum name="DOUT_OEM4_4_BIT_MOD" start="0x6" description="dout_oem4 (4-bit mode)" /> - <Enum name="DOUT_OEM8_8_BIT_MOD" start="0x7" description="dout_oem8 (8-bit mode)" /> - </BitField> - <BitField start="7" size="25" name="RESERVED" description="Reserved." /> - </Register> - <Register start="+0x0000+8" size="4" name="OUT_MUX_CFG[2]" access="Read/Write" description="Pin multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="4" name="P_OUT_CFG" description="Output control of output SGPIOn. All other values are reserved."> - <Enum name="DOUT_DOUTM1" start="0x0" description="dout_doutm1 (1-bit mode)" /> - <Enum name="DOUT_DOUTM2A" start="0x1" description="dout_doutm2a (2-bit mode 2a)" /> - <Enum name="DOUT_DOUTM2B" start="0x2" description="dout_doutm2b (2-bit mode 2b)" /> - <Enum name="DOUT_DOUTM2C" start="0x3" description="dout_doutm2c (2-bit mode 2c)" /> - <Enum name="GPIO_OUT_LEVEL_SET" start="0x4" description="gpio_out (level set by GPIO_OUTREG)" /> - <Enum name="DOUT_DOUTM4A" start="0x5" description="dout_doutm4a (4-bit mode 4a)" /> - <Enum name="DOUT_DOUTM4B" start="0x6" description="dout_doutm4b (4-bit mode 4b)" /> - <Enum name="DOUT_DOUTM4C" start="0x7" description="dout_doutm4c (4-bit mode 4c)" /> - <Enum name="CLK_OUT" start="0x8" description="clk_out" /> - <Enum name="DOUT_DOUTM8A" start="0x9" description="dout_doutm8a (8-bit mode 8a)" /> - <Enum name="DOUT_DOUTM8B" start="0xA" description="dout_doutm8b (8-bit mode 8b)" /> - <Enum name="DOUT_DOUTM8C" start="0xB" description="dout_doutm8c (8-bit mode 8c)" /> - </BitField> - <BitField start="4" size="3" name="P_OE_CFG" description="Output enable source. All other values are reserved."> - <Enum name="GPIO_OE_STATE_SET_B" start="0x0" description="gpio_oe (state set by GPIO_OEREG)" /> - <Enum name="DOUT_OEM1_1_BIT_MOD" start="0x4" description="dout_oem1 (1-bit mode)" /> - <Enum name="DOUT_OEM2_2_BIT_MOD" start="0x5" description="dout_oem2 (2-bit mode)" /> - <Enum name="DOUT_OEM4_4_BIT_MOD" start="0x6" description="dout_oem4 (4-bit mode)" /> - <Enum name="DOUT_OEM8_8_BIT_MOD" start="0x7" description="dout_oem8 (8-bit mode)" /> - </BitField> - <BitField start="7" size="25" name="RESERVED" description="Reserved." /> - </Register> - <Register start="+0x0000+12" size="4" name="OUT_MUX_CFG[3]" access="Read/Write" description="Pin multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="4" name="P_OUT_CFG" description="Output control of output SGPIOn. All other values are reserved."> - <Enum name="DOUT_DOUTM1" start="0x0" description="dout_doutm1 (1-bit mode)" /> - <Enum name="DOUT_DOUTM2A" start="0x1" description="dout_doutm2a (2-bit mode 2a)" /> - <Enum name="DOUT_DOUTM2B" start="0x2" description="dout_doutm2b (2-bit mode 2b)" /> - <Enum name="DOUT_DOUTM2C" start="0x3" description="dout_doutm2c (2-bit mode 2c)" /> - <Enum name="GPIO_OUT_LEVEL_SET" start="0x4" description="gpio_out (level set by GPIO_OUTREG)" /> - <Enum name="DOUT_DOUTM4A" start="0x5" description="dout_doutm4a (4-bit mode 4a)" /> - <Enum name="DOUT_DOUTM4B" start="0x6" description="dout_doutm4b (4-bit mode 4b)" /> - <Enum name="DOUT_DOUTM4C" start="0x7" description="dout_doutm4c (4-bit mode 4c)" /> - <Enum name="CLK_OUT" start="0x8" description="clk_out" /> - <Enum name="DOUT_DOUTM8A" start="0x9" description="dout_doutm8a (8-bit mode 8a)" /> - <Enum name="DOUT_DOUTM8B" start="0xA" description="dout_doutm8b (8-bit mode 8b)" /> - <Enum name="DOUT_DOUTM8C" start="0xB" description="dout_doutm8c (8-bit mode 8c)" /> - </BitField> - <BitField start="4" size="3" name="P_OE_CFG" description="Output enable source. All other values are reserved."> - <Enum name="GPIO_OE_STATE_SET_B" start="0x0" description="gpio_oe (state set by GPIO_OEREG)" /> - <Enum name="DOUT_OEM1_1_BIT_MOD" start="0x4" description="dout_oem1 (1-bit mode)" /> - <Enum name="DOUT_OEM2_2_BIT_MOD" start="0x5" description="dout_oem2 (2-bit mode)" /> - <Enum name="DOUT_OEM4_4_BIT_MOD" start="0x6" description="dout_oem4 (4-bit mode)" /> - <Enum name="DOUT_OEM8_8_BIT_MOD" start="0x7" description="dout_oem8 (8-bit mode)" /> - </BitField> - <BitField start="7" size="25" name="RESERVED" description="Reserved." /> - </Register> - <Register start="+0x0000+16" size="4" name="OUT_MUX_CFG[4]" access="Read/Write" description="Pin multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="4" name="P_OUT_CFG" description="Output control of output SGPIOn. All other values are reserved."> - <Enum name="DOUT_DOUTM1" start="0x0" description="dout_doutm1 (1-bit mode)" /> - <Enum name="DOUT_DOUTM2A" start="0x1" description="dout_doutm2a (2-bit mode 2a)" /> - <Enum name="DOUT_DOUTM2B" start="0x2" description="dout_doutm2b (2-bit mode 2b)" /> - <Enum name="DOUT_DOUTM2C" start="0x3" description="dout_doutm2c (2-bit mode 2c)" /> - <Enum name="GPIO_OUT_LEVEL_SET" start="0x4" description="gpio_out (level set by GPIO_OUTREG)" /> - <Enum name="DOUT_DOUTM4A" start="0x5" description="dout_doutm4a (4-bit mode 4a)" /> - <Enum name="DOUT_DOUTM4B" start="0x6" description="dout_doutm4b (4-bit mode 4b)" /> - <Enum name="DOUT_DOUTM4C" start="0x7" description="dout_doutm4c (4-bit mode 4c)" /> - <Enum name="CLK_OUT" start="0x8" description="clk_out" /> - <Enum name="DOUT_DOUTM8A" start="0x9" description="dout_doutm8a (8-bit mode 8a)" /> - <Enum name="DOUT_DOUTM8B" start="0xA" description="dout_doutm8b (8-bit mode 8b)" /> - <Enum name="DOUT_DOUTM8C" start="0xB" description="dout_doutm8c (8-bit mode 8c)" /> - </BitField> - <BitField start="4" size="3" name="P_OE_CFG" description="Output enable source. All other values are reserved."> - <Enum name="GPIO_OE_STATE_SET_B" start="0x0" description="gpio_oe (state set by GPIO_OEREG)" /> - <Enum name="DOUT_OEM1_1_BIT_MOD" start="0x4" description="dout_oem1 (1-bit mode)" /> - <Enum name="DOUT_OEM2_2_BIT_MOD" start="0x5" description="dout_oem2 (2-bit mode)" /> - <Enum name="DOUT_OEM4_4_BIT_MOD" start="0x6" description="dout_oem4 (4-bit mode)" /> - <Enum name="DOUT_OEM8_8_BIT_MOD" start="0x7" description="dout_oem8 (8-bit mode)" /> - </BitField> - <BitField start="7" size="25" name="RESERVED" description="Reserved." /> - </Register> - <Register start="+0x0000+20" size="4" name="OUT_MUX_CFG[5]" access="Read/Write" description="Pin multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="4" name="P_OUT_CFG" description="Output control of output SGPIOn. All other values are reserved."> - <Enum name="DOUT_DOUTM1" start="0x0" description="dout_doutm1 (1-bit mode)" /> - <Enum name="DOUT_DOUTM2A" start="0x1" description="dout_doutm2a (2-bit mode 2a)" /> - <Enum name="DOUT_DOUTM2B" start="0x2" description="dout_doutm2b (2-bit mode 2b)" /> - <Enum name="DOUT_DOUTM2C" start="0x3" description="dout_doutm2c (2-bit mode 2c)" /> - <Enum name="GPIO_OUT_LEVEL_SET" start="0x4" description="gpio_out (level set by GPIO_OUTREG)" /> - <Enum name="DOUT_DOUTM4A" start="0x5" description="dout_doutm4a (4-bit mode 4a)" /> - <Enum name="DOUT_DOUTM4B" start="0x6" description="dout_doutm4b (4-bit mode 4b)" /> - <Enum name="DOUT_DOUTM4C" start="0x7" description="dout_doutm4c (4-bit mode 4c)" /> - <Enum name="CLK_OUT" start="0x8" description="clk_out" /> - <Enum name="DOUT_DOUTM8A" start="0x9" description="dout_doutm8a (8-bit mode 8a)" /> - <Enum name="DOUT_DOUTM8B" start="0xA" description="dout_doutm8b (8-bit mode 8b)" /> - <Enum name="DOUT_DOUTM8C" start="0xB" description="dout_doutm8c (8-bit mode 8c)" /> - </BitField> - <BitField start="4" size="3" name="P_OE_CFG" description="Output enable source. All other values are reserved."> - <Enum name="GPIO_OE_STATE_SET_B" start="0x0" description="gpio_oe (state set by GPIO_OEREG)" /> - <Enum name="DOUT_OEM1_1_BIT_MOD" start="0x4" description="dout_oem1 (1-bit mode)" /> - <Enum name="DOUT_OEM2_2_BIT_MOD" start="0x5" description="dout_oem2 (2-bit mode)" /> - <Enum name="DOUT_OEM4_4_BIT_MOD" start="0x6" description="dout_oem4 (4-bit mode)" /> - <Enum name="DOUT_OEM8_8_BIT_MOD" start="0x7" description="dout_oem8 (8-bit mode)" /> - </BitField> - <BitField start="7" size="25" name="RESERVED" description="Reserved." /> - </Register> - <Register start="+0x0000+24" size="4" name="OUT_MUX_CFG[6]" access="Read/Write" description="Pin multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="4" name="P_OUT_CFG" description="Output control of output SGPIOn. All other values are reserved."> - <Enum name="DOUT_DOUTM1" start="0x0" description="dout_doutm1 (1-bit mode)" /> - <Enum name="DOUT_DOUTM2A" start="0x1" description="dout_doutm2a (2-bit mode 2a)" /> - <Enum name="DOUT_DOUTM2B" start="0x2" description="dout_doutm2b (2-bit mode 2b)" /> - <Enum name="DOUT_DOUTM2C" start="0x3" description="dout_doutm2c (2-bit mode 2c)" /> - <Enum name="GPIO_OUT_LEVEL_SET" start="0x4" description="gpio_out (level set by GPIO_OUTREG)" /> - <Enum name="DOUT_DOUTM4A" start="0x5" description="dout_doutm4a (4-bit mode 4a)" /> - <Enum name="DOUT_DOUTM4B" start="0x6" description="dout_doutm4b (4-bit mode 4b)" /> - <Enum name="DOUT_DOUTM4C" start="0x7" description="dout_doutm4c (4-bit mode 4c)" /> - <Enum name="CLK_OUT" start="0x8" description="clk_out" /> - <Enum name="DOUT_DOUTM8A" start="0x9" description="dout_doutm8a (8-bit mode 8a)" /> - <Enum name="DOUT_DOUTM8B" start="0xA" description="dout_doutm8b (8-bit mode 8b)" /> - <Enum name="DOUT_DOUTM8C" start="0xB" description="dout_doutm8c (8-bit mode 8c)" /> - </BitField> - <BitField start="4" size="3" name="P_OE_CFG" description="Output enable source. All other values are reserved."> - <Enum name="GPIO_OE_STATE_SET_B" start="0x0" description="gpio_oe (state set by GPIO_OEREG)" /> - <Enum name="DOUT_OEM1_1_BIT_MOD" start="0x4" description="dout_oem1 (1-bit mode)" /> - <Enum name="DOUT_OEM2_2_BIT_MOD" start="0x5" description="dout_oem2 (2-bit mode)" /> - <Enum name="DOUT_OEM4_4_BIT_MOD" start="0x6" description="dout_oem4 (4-bit mode)" /> - <Enum name="DOUT_OEM8_8_BIT_MOD" start="0x7" description="dout_oem8 (8-bit mode)" /> - </BitField> - <BitField start="7" size="25" name="RESERVED" description="Reserved." /> - </Register> - <Register start="+0x0000+28" size="4" name="OUT_MUX_CFG[7]" access="Read/Write" description="Pin multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="4" name="P_OUT_CFG" description="Output control of output SGPIOn. All other values are reserved."> - <Enum name="DOUT_DOUTM1" start="0x0" description="dout_doutm1 (1-bit mode)" /> - <Enum name="DOUT_DOUTM2A" start="0x1" description="dout_doutm2a (2-bit mode 2a)" /> - <Enum name="DOUT_DOUTM2B" start="0x2" description="dout_doutm2b (2-bit mode 2b)" /> - <Enum name="DOUT_DOUTM2C" start="0x3" description="dout_doutm2c (2-bit mode 2c)" /> - <Enum name="GPIO_OUT_LEVEL_SET" start="0x4" description="gpio_out (level set by GPIO_OUTREG)" /> - <Enum name="DOUT_DOUTM4A" start="0x5" description="dout_doutm4a (4-bit mode 4a)" /> - <Enum name="DOUT_DOUTM4B" start="0x6" description="dout_doutm4b (4-bit mode 4b)" /> - <Enum name="DOUT_DOUTM4C" start="0x7" description="dout_doutm4c (4-bit mode 4c)" /> - <Enum name="CLK_OUT" start="0x8" description="clk_out" /> - <Enum name="DOUT_DOUTM8A" start="0x9" description="dout_doutm8a (8-bit mode 8a)" /> - <Enum name="DOUT_DOUTM8B" start="0xA" description="dout_doutm8b (8-bit mode 8b)" /> - <Enum name="DOUT_DOUTM8C" start="0xB" description="dout_doutm8c (8-bit mode 8c)" /> - </BitField> - <BitField start="4" size="3" name="P_OE_CFG" description="Output enable source. All other values are reserved."> - <Enum name="GPIO_OE_STATE_SET_B" start="0x0" description="gpio_oe (state set by GPIO_OEREG)" /> - <Enum name="DOUT_OEM1_1_BIT_MOD" start="0x4" description="dout_oem1 (1-bit mode)" /> - <Enum name="DOUT_OEM2_2_BIT_MOD" start="0x5" description="dout_oem2 (2-bit mode)" /> - <Enum name="DOUT_OEM4_4_BIT_MOD" start="0x6" description="dout_oem4 (4-bit mode)" /> - <Enum name="DOUT_OEM8_8_BIT_MOD" start="0x7" description="dout_oem8 (8-bit mode)" /> - </BitField> - <BitField start="7" size="25" name="RESERVED" description="Reserved." /> - </Register> - <Register start="+0x0000+32" size="4" name="OUT_MUX_CFG[8]" access="Read/Write" description="Pin multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="4" name="P_OUT_CFG" description="Output control of output SGPIOn. All other values are reserved."> - <Enum name="DOUT_DOUTM1" start="0x0" description="dout_doutm1 (1-bit mode)" /> - <Enum name="DOUT_DOUTM2A" start="0x1" description="dout_doutm2a (2-bit mode 2a)" /> - <Enum name="DOUT_DOUTM2B" start="0x2" description="dout_doutm2b (2-bit mode 2b)" /> - <Enum name="DOUT_DOUTM2C" start="0x3" description="dout_doutm2c (2-bit mode 2c)" /> - <Enum name="GPIO_OUT_LEVEL_SET" start="0x4" description="gpio_out (level set by GPIO_OUTREG)" /> - <Enum name="DOUT_DOUTM4A" start="0x5" description="dout_doutm4a (4-bit mode 4a)" /> - <Enum name="DOUT_DOUTM4B" start="0x6" description="dout_doutm4b (4-bit mode 4b)" /> - <Enum name="DOUT_DOUTM4C" start="0x7" description="dout_doutm4c (4-bit mode 4c)" /> - <Enum name="CLK_OUT" start="0x8" description="clk_out" /> - <Enum name="DOUT_DOUTM8A" start="0x9" description="dout_doutm8a (8-bit mode 8a)" /> - <Enum name="DOUT_DOUTM8B" start="0xA" description="dout_doutm8b (8-bit mode 8b)" /> - <Enum name="DOUT_DOUTM8C" start="0xB" description="dout_doutm8c (8-bit mode 8c)" /> - </BitField> - <BitField start="4" size="3" name="P_OE_CFG" description="Output enable source. All other values are reserved."> - <Enum name="GPIO_OE_STATE_SET_B" start="0x0" description="gpio_oe (state set by GPIO_OEREG)" /> - <Enum name="DOUT_OEM1_1_BIT_MOD" start="0x4" description="dout_oem1 (1-bit mode)" /> - <Enum name="DOUT_OEM2_2_BIT_MOD" start="0x5" description="dout_oem2 (2-bit mode)" /> - <Enum name="DOUT_OEM4_4_BIT_MOD" start="0x6" description="dout_oem4 (4-bit mode)" /> - <Enum name="DOUT_OEM8_8_BIT_MOD" start="0x7" description="dout_oem8 (8-bit mode)" /> - </BitField> - <BitField start="7" size="25" name="RESERVED" description="Reserved." /> - </Register> - <Register start="+0x0000+36" size="4" name="OUT_MUX_CFG[9]" access="Read/Write" description="Pin multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="4" name="P_OUT_CFG" description="Output control of output SGPIOn. All other values are reserved."> - <Enum name="DOUT_DOUTM1" start="0x0" description="dout_doutm1 (1-bit mode)" /> - <Enum name="DOUT_DOUTM2A" start="0x1" description="dout_doutm2a (2-bit mode 2a)" /> - <Enum name="DOUT_DOUTM2B" start="0x2" description="dout_doutm2b (2-bit mode 2b)" /> - <Enum name="DOUT_DOUTM2C" start="0x3" description="dout_doutm2c (2-bit mode 2c)" /> - <Enum name="GPIO_OUT_LEVEL_SET" start="0x4" description="gpio_out (level set by GPIO_OUTREG)" /> - <Enum name="DOUT_DOUTM4A" start="0x5" description="dout_doutm4a (4-bit mode 4a)" /> - <Enum name="DOUT_DOUTM4B" start="0x6" description="dout_doutm4b (4-bit mode 4b)" /> - <Enum name="DOUT_DOUTM4C" start="0x7" description="dout_doutm4c (4-bit mode 4c)" /> - <Enum name="CLK_OUT" start="0x8" description="clk_out" /> - <Enum name="DOUT_DOUTM8A" start="0x9" description="dout_doutm8a (8-bit mode 8a)" /> - <Enum name="DOUT_DOUTM8B" start="0xA" description="dout_doutm8b (8-bit mode 8b)" /> - <Enum name="DOUT_DOUTM8C" start="0xB" description="dout_doutm8c (8-bit mode 8c)" /> - </BitField> - <BitField start="4" size="3" name="P_OE_CFG" description="Output enable source. All other values are reserved."> - <Enum name="GPIO_OE_STATE_SET_B" start="0x0" description="gpio_oe (state set by GPIO_OEREG)" /> - <Enum name="DOUT_OEM1_1_BIT_MOD" start="0x4" description="dout_oem1 (1-bit mode)" /> - <Enum name="DOUT_OEM2_2_BIT_MOD" start="0x5" description="dout_oem2 (2-bit mode)" /> - <Enum name="DOUT_OEM4_4_BIT_MOD" start="0x6" description="dout_oem4 (4-bit mode)" /> - <Enum name="DOUT_OEM8_8_BIT_MOD" start="0x7" description="dout_oem8 (8-bit mode)" /> - </BitField> - <BitField start="7" size="25" name="RESERVED" description="Reserved." /> - </Register> - <Register start="+0x0000+40" size="4" name="OUT_MUX_CFG[10]" access="Read/Write" description="Pin multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="4" name="P_OUT_CFG" description="Output control of output SGPIOn. All other values are reserved."> - <Enum name="DOUT_DOUTM1" start="0x0" description="dout_doutm1 (1-bit mode)" /> - <Enum name="DOUT_DOUTM2A" start="0x1" description="dout_doutm2a (2-bit mode 2a)" /> - <Enum name="DOUT_DOUTM2B" start="0x2" description="dout_doutm2b (2-bit mode 2b)" /> - <Enum name="DOUT_DOUTM2C" start="0x3" description="dout_doutm2c (2-bit mode 2c)" /> - <Enum name="GPIO_OUT_LEVEL_SET" start="0x4" description="gpio_out (level set by GPIO_OUTREG)" /> - <Enum name="DOUT_DOUTM4A" start="0x5" description="dout_doutm4a (4-bit mode 4a)" /> - <Enum name="DOUT_DOUTM4B" start="0x6" description="dout_doutm4b (4-bit mode 4b)" /> - <Enum name="DOUT_DOUTM4C" start="0x7" description="dout_doutm4c (4-bit mode 4c)" /> - <Enum name="CLK_OUT" start="0x8" description="clk_out" /> - <Enum name="DOUT_DOUTM8A" start="0x9" description="dout_doutm8a (8-bit mode 8a)" /> - <Enum name="DOUT_DOUTM8B" start="0xA" description="dout_doutm8b (8-bit mode 8b)" /> - <Enum name="DOUT_DOUTM8C" start="0xB" description="dout_doutm8c (8-bit mode 8c)" /> - </BitField> - <BitField start="4" size="3" name="P_OE_CFG" description="Output enable source. All other values are reserved."> - <Enum name="GPIO_OE_STATE_SET_B" start="0x0" description="gpio_oe (state set by GPIO_OEREG)" /> - <Enum name="DOUT_OEM1_1_BIT_MOD" start="0x4" description="dout_oem1 (1-bit mode)" /> - <Enum name="DOUT_OEM2_2_BIT_MOD" start="0x5" description="dout_oem2 (2-bit mode)" /> - <Enum name="DOUT_OEM4_4_BIT_MOD" start="0x6" description="dout_oem4 (4-bit mode)" /> - <Enum name="DOUT_OEM8_8_BIT_MOD" start="0x7" description="dout_oem8 (8-bit mode)" /> - </BitField> - <BitField start="7" size="25" name="RESERVED" description="Reserved." /> - </Register> - <Register start="+0x0000+44" size="4" name="OUT_MUX_CFG[11]" access="Read/Write" description="Pin multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="4" name="P_OUT_CFG" description="Output control of output SGPIOn. All other values are reserved."> - <Enum name="DOUT_DOUTM1" start="0x0" description="dout_doutm1 (1-bit mode)" /> - <Enum name="DOUT_DOUTM2A" start="0x1" description="dout_doutm2a (2-bit mode 2a)" /> - <Enum name="DOUT_DOUTM2B" start="0x2" description="dout_doutm2b (2-bit mode 2b)" /> - <Enum name="DOUT_DOUTM2C" start="0x3" description="dout_doutm2c (2-bit mode 2c)" /> - <Enum name="GPIO_OUT_LEVEL_SET" start="0x4" description="gpio_out (level set by GPIO_OUTREG)" /> - <Enum name="DOUT_DOUTM4A" start="0x5" description="dout_doutm4a (4-bit mode 4a)" /> - <Enum name="DOUT_DOUTM4B" start="0x6" description="dout_doutm4b (4-bit mode 4b)" /> - <Enum name="DOUT_DOUTM4C" start="0x7" description="dout_doutm4c (4-bit mode 4c)" /> - <Enum name="CLK_OUT" start="0x8" description="clk_out" /> - <Enum name="DOUT_DOUTM8A" start="0x9" description="dout_doutm8a (8-bit mode 8a)" /> - <Enum name="DOUT_DOUTM8B" start="0xA" description="dout_doutm8b (8-bit mode 8b)" /> - <Enum name="DOUT_DOUTM8C" start="0xB" description="dout_doutm8c (8-bit mode 8c)" /> - </BitField> - <BitField start="4" size="3" name="P_OE_CFG" description="Output enable source. All other values are reserved."> - <Enum name="GPIO_OE_STATE_SET_B" start="0x0" description="gpio_oe (state set by GPIO_OEREG)" /> - <Enum name="DOUT_OEM1_1_BIT_MOD" start="0x4" description="dout_oem1 (1-bit mode)" /> - <Enum name="DOUT_OEM2_2_BIT_MOD" start="0x5" description="dout_oem2 (2-bit mode)" /> - <Enum name="DOUT_OEM4_4_BIT_MOD" start="0x6" description="dout_oem4 (4-bit mode)" /> - <Enum name="DOUT_OEM8_8_BIT_MOD" start="0x7" description="dout_oem8 (8-bit mode)" /> - </BitField> - <BitField start="7" size="25" name="RESERVED" description="Reserved." /> - </Register> - <Register start="+0x0000+48" size="4" name="OUT_MUX_CFG[12]" access="Read/Write" description="Pin multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="4" name="P_OUT_CFG" description="Output control of output SGPIOn. All other values are reserved."> - <Enum name="DOUT_DOUTM1" start="0x0" description="dout_doutm1 (1-bit mode)" /> - <Enum name="DOUT_DOUTM2A" start="0x1" description="dout_doutm2a (2-bit mode 2a)" /> - <Enum name="DOUT_DOUTM2B" start="0x2" description="dout_doutm2b (2-bit mode 2b)" /> - <Enum name="DOUT_DOUTM2C" start="0x3" description="dout_doutm2c (2-bit mode 2c)" /> - <Enum name="GPIO_OUT_LEVEL_SET" start="0x4" description="gpio_out (level set by GPIO_OUTREG)" /> - <Enum name="DOUT_DOUTM4A" start="0x5" description="dout_doutm4a (4-bit mode 4a)" /> - <Enum name="DOUT_DOUTM4B" start="0x6" description="dout_doutm4b (4-bit mode 4b)" /> - <Enum name="DOUT_DOUTM4C" start="0x7" description="dout_doutm4c (4-bit mode 4c)" /> - <Enum name="CLK_OUT" start="0x8" description="clk_out" /> - <Enum name="DOUT_DOUTM8A" start="0x9" description="dout_doutm8a (8-bit mode 8a)" /> - <Enum name="DOUT_DOUTM8B" start="0xA" description="dout_doutm8b (8-bit mode 8b)" /> - <Enum name="DOUT_DOUTM8C" start="0xB" description="dout_doutm8c (8-bit mode 8c)" /> - </BitField> - <BitField start="4" size="3" name="P_OE_CFG" description="Output enable source. All other values are reserved."> - <Enum name="GPIO_OE_STATE_SET_B" start="0x0" description="gpio_oe (state set by GPIO_OEREG)" /> - <Enum name="DOUT_OEM1_1_BIT_MOD" start="0x4" description="dout_oem1 (1-bit mode)" /> - <Enum name="DOUT_OEM2_2_BIT_MOD" start="0x5" description="dout_oem2 (2-bit mode)" /> - <Enum name="DOUT_OEM4_4_BIT_MOD" start="0x6" description="dout_oem4 (4-bit mode)" /> - <Enum name="DOUT_OEM8_8_BIT_MOD" start="0x7" description="dout_oem8 (8-bit mode)" /> - </BitField> - <BitField start="7" size="25" name="RESERVED" description="Reserved." /> - </Register> - <Register start="+0x0000+52" size="4" name="OUT_MUX_CFG[13]" access="Read/Write" description="Pin multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="4" name="P_OUT_CFG" description="Output control of output SGPIOn. All other values are reserved."> - <Enum name="DOUT_DOUTM1" start="0x0" description="dout_doutm1 (1-bit mode)" /> - <Enum name="DOUT_DOUTM2A" start="0x1" description="dout_doutm2a (2-bit mode 2a)" /> - <Enum name="DOUT_DOUTM2B" start="0x2" description="dout_doutm2b (2-bit mode 2b)" /> - <Enum name="DOUT_DOUTM2C" start="0x3" description="dout_doutm2c (2-bit mode 2c)" /> - <Enum name="GPIO_OUT_LEVEL_SET" start="0x4" description="gpio_out (level set by GPIO_OUTREG)" /> - <Enum name="DOUT_DOUTM4A" start="0x5" description="dout_doutm4a (4-bit mode 4a)" /> - <Enum name="DOUT_DOUTM4B" start="0x6" description="dout_doutm4b (4-bit mode 4b)" /> - <Enum name="DOUT_DOUTM4C" start="0x7" description="dout_doutm4c (4-bit mode 4c)" /> - <Enum name="CLK_OUT" start="0x8" description="clk_out" /> - <Enum name="DOUT_DOUTM8A" start="0x9" description="dout_doutm8a (8-bit mode 8a)" /> - <Enum name="DOUT_DOUTM8B" start="0xA" description="dout_doutm8b (8-bit mode 8b)" /> - <Enum name="DOUT_DOUTM8C" start="0xB" description="dout_doutm8c (8-bit mode 8c)" /> - </BitField> - <BitField start="4" size="3" name="P_OE_CFG" description="Output enable source. All other values are reserved."> - <Enum name="GPIO_OE_STATE_SET_B" start="0x0" description="gpio_oe (state set by GPIO_OEREG)" /> - <Enum name="DOUT_OEM1_1_BIT_MOD" start="0x4" description="dout_oem1 (1-bit mode)" /> - <Enum name="DOUT_OEM2_2_BIT_MOD" start="0x5" description="dout_oem2 (2-bit mode)" /> - <Enum name="DOUT_OEM4_4_BIT_MOD" start="0x6" description="dout_oem4 (4-bit mode)" /> - <Enum name="DOUT_OEM8_8_BIT_MOD" start="0x7" description="dout_oem8 (8-bit mode)" /> - </BitField> - <BitField start="7" size="25" name="RESERVED" description="Reserved." /> - </Register> - <Register start="+0x0000+56" size="4" name="OUT_MUX_CFG[14]" access="Read/Write" description="Pin multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="4" name="P_OUT_CFG" description="Output control of output SGPIOn. All other values are reserved."> - <Enum name="DOUT_DOUTM1" start="0x0" description="dout_doutm1 (1-bit mode)" /> - <Enum name="DOUT_DOUTM2A" start="0x1" description="dout_doutm2a (2-bit mode 2a)" /> - <Enum name="DOUT_DOUTM2B" start="0x2" description="dout_doutm2b (2-bit mode 2b)" /> - <Enum name="DOUT_DOUTM2C" start="0x3" description="dout_doutm2c (2-bit mode 2c)" /> - <Enum name="GPIO_OUT_LEVEL_SET" start="0x4" description="gpio_out (level set by GPIO_OUTREG)" /> - <Enum name="DOUT_DOUTM4A" start="0x5" description="dout_doutm4a (4-bit mode 4a)" /> - <Enum name="DOUT_DOUTM4B" start="0x6" description="dout_doutm4b (4-bit mode 4b)" /> - <Enum name="DOUT_DOUTM4C" start="0x7" description="dout_doutm4c (4-bit mode 4c)" /> - <Enum name="CLK_OUT" start="0x8" description="clk_out" /> - <Enum name="DOUT_DOUTM8A" start="0x9" description="dout_doutm8a (8-bit mode 8a)" /> - <Enum name="DOUT_DOUTM8B" start="0xA" description="dout_doutm8b (8-bit mode 8b)" /> - <Enum name="DOUT_DOUTM8C" start="0xB" description="dout_doutm8c (8-bit mode 8c)" /> - </BitField> - <BitField start="4" size="3" name="P_OE_CFG" description="Output enable source. All other values are reserved."> - <Enum name="GPIO_OE_STATE_SET_B" start="0x0" description="gpio_oe (state set by GPIO_OEREG)" /> - <Enum name="DOUT_OEM1_1_BIT_MOD" start="0x4" description="dout_oem1 (1-bit mode)" /> - <Enum name="DOUT_OEM2_2_BIT_MOD" start="0x5" description="dout_oem2 (2-bit mode)" /> - <Enum name="DOUT_OEM4_4_BIT_MOD" start="0x6" description="dout_oem4 (4-bit mode)" /> - <Enum name="DOUT_OEM8_8_BIT_MOD" start="0x7" description="dout_oem8 (8-bit mode)" /> - </BitField> - <BitField start="7" size="25" name="RESERVED" description="Reserved." /> - </Register> - <Register start="+0x0000+60" size="4" name="OUT_MUX_CFG[15]" access="Read/Write" description="Pin multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="4" name="P_OUT_CFG" description="Output control of output SGPIOn. All other values are reserved."> - <Enum name="DOUT_DOUTM1" start="0x0" description="dout_doutm1 (1-bit mode)" /> - <Enum name="DOUT_DOUTM2A" start="0x1" description="dout_doutm2a (2-bit mode 2a)" /> - <Enum name="DOUT_DOUTM2B" start="0x2" description="dout_doutm2b (2-bit mode 2b)" /> - <Enum name="DOUT_DOUTM2C" start="0x3" description="dout_doutm2c (2-bit mode 2c)" /> - <Enum name="GPIO_OUT_LEVEL_SET" start="0x4" description="gpio_out (level set by GPIO_OUTREG)" /> - <Enum name="DOUT_DOUTM4A" start="0x5" description="dout_doutm4a (4-bit mode 4a)" /> - <Enum name="DOUT_DOUTM4B" start="0x6" description="dout_doutm4b (4-bit mode 4b)" /> - <Enum name="DOUT_DOUTM4C" start="0x7" description="dout_doutm4c (4-bit mode 4c)" /> - <Enum name="CLK_OUT" start="0x8" description="clk_out" /> - <Enum name="DOUT_DOUTM8A" start="0x9" description="dout_doutm8a (8-bit mode 8a)" /> - <Enum name="DOUT_DOUTM8B" start="0xA" description="dout_doutm8b (8-bit mode 8b)" /> - <Enum name="DOUT_DOUTM8C" start="0xB" description="dout_doutm8c (8-bit mode 8c)" /> - </BitField> - <BitField start="4" size="3" name="P_OE_CFG" description="Output enable source. All other values are reserved."> - <Enum name="GPIO_OE_STATE_SET_B" start="0x0" description="gpio_oe (state set by GPIO_OEREG)" /> - <Enum name="DOUT_OEM1_1_BIT_MOD" start="0x4" description="dout_oem1 (1-bit mode)" /> - <Enum name="DOUT_OEM2_2_BIT_MOD" start="0x5" description="dout_oem2 (2-bit mode)" /> - <Enum name="DOUT_OEM4_4_BIT_MOD" start="0x6" description="dout_oem4 (4-bit mode)" /> - <Enum name="DOUT_OEM8_8_BIT_MOD" start="0x7" description="dout_oem8 (8-bit mode)" /> - </BitField> - <BitField start="7" size="25" name="RESERVED" description="Reserved." /> - </Register> - <Register start="+0x0040+0" size="4" name="SGPIO_MUX_CFG[0]" access="Read/Write" description="SGPIO multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="1" name="EXT_CLK_ENABLE" description="Select clock signal."> - <Enum name="INTERNAL_CLOCK_SIGNA" start="0x0" description="Internal clock signal (slice)" /> - <Enum name="EXTERNAL_CLOCK_SIGNA" start="0x1" description="External clock signal (pin)" /> - </BitField> - <BitField start="1" size="2" name="CLK_SOURCE_PIN_MODE" description="Select source clock pin."> - <Enum name="SGPIO8" start="0x0" description="SGPIO8" /> - <Enum name="SGPIO9" start="0x1" description="SGPIO9" /> - <Enum name="SGPIO10" start="0x2" description="SGPIO10" /> - <Enum name="SGPIO11" start="0x3" description="SGPIO11" /> - </BitField> - <BitField start="3" size="2" name="CLK_SOURCE_SLICE_MODE" description="Select clock source slice. Note that slices D, H, O and P do not support this mode."> - <Enum name="SLICE_D" start="0x0" description="Slice D" /> - <Enum name="SLICE_H" start="0x1" description="Slice H" /> - <Enum name="SLICE_O" start="0x2" description="Slice O" /> - <Enum name="SLICE_P" start="0x3" description="Slice P" /> - </BitField> - <BitField start="5" size="2" name="QUALIFIER_MODE" description="Select qualifier mode."> - <Enum name="ENABLE" start="0x0" description="Enable" /> - <Enum name="DISABLE" start="0x1" description="Disable" /> - <Enum name="SLICE_SEE_BITS_QUAL" start="0x2" description="Slice (see bits QUALIFIER_SLICE_MODE in this register)" /> - <Enum name="EXTERNAL_SGPIO_PIN" start="0x3" description="External SGPIO pin (SGPIO8, SGPIO9, SGPIO10, or SGPIO11)" /> - </BitField> - <BitField start="7" size="2" name="QUALIFIER_PIN_MODE" description="Select qualifier pin."> - <Enum name="SGPIO8" start="0x0" description="SGPIO8" /> - <Enum name="SGPIO9" start="0x1" description="SGPIO9" /> - <Enum name="SGPIO10" start="0x2" description="SGPIO10" /> - <Enum name="SGPIO11" start="0x3" description="SGPIO11" /> - </BitField> - <BitField start="9" size="2" name="QUALIFIER_SLICE_MODE" description="Select qualifier slice."> - <Enum name="SLICE_A" start="0x0" description="Slice A, but for slice A slice D is used." /> - <Enum name="SLICE_H" start="0x1" description="Slice H, but for slice H slice O is used." /> - <Enum name="SLICE_I" start="0x2" description="Slice I, but for slice I slice D is used." /> - <Enum name="SLICE_P" start="0x3" description="Slice P, but for slice P slice O is used." /> - </BitField> - <BitField start="11" size="1" name="CONCAT_ENABLE" description="Enable concatenation."> - <Enum name="EXTERNAL_DATA_PIN" start="0x0" description="External data pin" /> - <Enum name="CONCATENATE_DATA" start="0x1" description="Concatenate data" /> - </BitField> - <BitField start="12" size="2" name="CONCAT_ORDER" description="Select concatenation order"> - <Enum name="SELF_LOOP" start="0x0" description="Self-loop" /> - <Enum name="2_SLICES" start="0x1" description="2 slices" /> - <Enum name="4_SLICES" start="0x2" description="4 slices" /> - <Enum name="8_SLICES" start="0x3" description="8 slices" /> - </BitField> - <BitField start="14" size="18" name="RESERVED" description="Reserved" /> - </Register> - <Register start="+0x0040+4" size="4" name="SGPIO_MUX_CFG[1]" access="Read/Write" description="SGPIO multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="1" name="EXT_CLK_ENABLE" description="Select clock signal."> - <Enum name="INTERNAL_CLOCK_SIGNA" start="0x0" description="Internal clock signal (slice)" /> - <Enum name="EXTERNAL_CLOCK_SIGNA" start="0x1" description="External clock signal (pin)" /> - </BitField> - <BitField start="1" size="2" name="CLK_SOURCE_PIN_MODE" description="Select source clock pin."> - <Enum name="SGPIO8" start="0x0" description="SGPIO8" /> - <Enum name="SGPIO9" start="0x1" description="SGPIO9" /> - <Enum name="SGPIO10" start="0x2" description="SGPIO10" /> - <Enum name="SGPIO11" start="0x3" description="SGPIO11" /> - </BitField> - <BitField start="3" size="2" name="CLK_SOURCE_SLICE_MODE" description="Select clock source slice. Note that slices D, H, O and P do not support this mode."> - <Enum name="SLICE_D" start="0x0" description="Slice D" /> - <Enum name="SLICE_H" start="0x1" description="Slice H" /> - <Enum name="SLICE_O" start="0x2" description="Slice O" /> - <Enum name="SLICE_P" start="0x3" description="Slice P" /> - </BitField> - <BitField start="5" size="2" name="QUALIFIER_MODE" description="Select qualifier mode."> - <Enum name="ENABLE" start="0x0" description="Enable" /> - <Enum name="DISABLE" start="0x1" description="Disable" /> - <Enum name="SLICE_SEE_BITS_QUAL" start="0x2" description="Slice (see bits QUALIFIER_SLICE_MODE in this register)" /> - <Enum name="EXTERNAL_SGPIO_PIN" start="0x3" description="External SGPIO pin (SGPIO8, SGPIO9, SGPIO10, or SGPIO11)" /> - </BitField> - <BitField start="7" size="2" name="QUALIFIER_PIN_MODE" description="Select qualifier pin."> - <Enum name="SGPIO8" start="0x0" description="SGPIO8" /> - <Enum name="SGPIO9" start="0x1" description="SGPIO9" /> - <Enum name="SGPIO10" start="0x2" description="SGPIO10" /> - <Enum name="SGPIO11" start="0x3" description="SGPIO11" /> - </BitField> - <BitField start="9" size="2" name="QUALIFIER_SLICE_MODE" description="Select qualifier slice."> - <Enum name="SLICE_A" start="0x0" description="Slice A, but for slice A slice D is used." /> - <Enum name="SLICE_H" start="0x1" description="Slice H, but for slice H slice O is used." /> - <Enum name="SLICE_I" start="0x2" description="Slice I, but for slice I slice D is used." /> - <Enum name="SLICE_P" start="0x3" description="Slice P, but for slice P slice O is used." /> - </BitField> - <BitField start="11" size="1" name="CONCAT_ENABLE" description="Enable concatenation."> - <Enum name="EXTERNAL_DATA_PIN" start="0x0" description="External data pin" /> - <Enum name="CONCATENATE_DATA" start="0x1" description="Concatenate data" /> - </BitField> - <BitField start="12" size="2" name="CONCAT_ORDER" description="Select concatenation order"> - <Enum name="SELF_LOOP" start="0x0" description="Self-loop" /> - <Enum name="2_SLICES" start="0x1" description="2 slices" /> - <Enum name="4_SLICES" start="0x2" description="4 slices" /> - <Enum name="8_SLICES" start="0x3" description="8 slices" /> - </BitField> - <BitField start="14" size="18" name="RESERVED" description="Reserved" /> - </Register> - <Register start="+0x0040+8" size="4" name="SGPIO_MUX_CFG[2]" access="Read/Write" description="SGPIO multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="1" name="EXT_CLK_ENABLE" description="Select clock signal."> - <Enum name="INTERNAL_CLOCK_SIGNA" start="0x0" description="Internal clock signal (slice)" /> - <Enum name="EXTERNAL_CLOCK_SIGNA" start="0x1" description="External clock signal (pin)" /> - </BitField> - <BitField start="1" size="2" name="CLK_SOURCE_PIN_MODE" description="Select source clock pin."> - <Enum name="SGPIO8" start="0x0" description="SGPIO8" /> - <Enum name="SGPIO9" start="0x1" description="SGPIO9" /> - <Enum name="SGPIO10" start="0x2" description="SGPIO10" /> - <Enum name="SGPIO11" start="0x3" description="SGPIO11" /> - </BitField> - <BitField start="3" size="2" name="CLK_SOURCE_SLICE_MODE" description="Select clock source slice. Note that slices D, H, O and P do not support this mode."> - <Enum name="SLICE_D" start="0x0" description="Slice D" /> - <Enum name="SLICE_H" start="0x1" description="Slice H" /> - <Enum name="SLICE_O" start="0x2" description="Slice O" /> - <Enum name="SLICE_P" start="0x3" description="Slice P" /> - </BitField> - <BitField start="5" size="2" name="QUALIFIER_MODE" description="Select qualifier mode."> - <Enum name="ENABLE" start="0x0" description="Enable" /> - <Enum name="DISABLE" start="0x1" description="Disable" /> - <Enum name="SLICE_SEE_BITS_QUAL" start="0x2" description="Slice (see bits QUALIFIER_SLICE_MODE in this register)" /> - <Enum name="EXTERNAL_SGPIO_PIN" start="0x3" description="External SGPIO pin (SGPIO8, SGPIO9, SGPIO10, or SGPIO11)" /> - </BitField> - <BitField start="7" size="2" name="QUALIFIER_PIN_MODE" description="Select qualifier pin."> - <Enum name="SGPIO8" start="0x0" description="SGPIO8" /> - <Enum name="SGPIO9" start="0x1" description="SGPIO9" /> - <Enum name="SGPIO10" start="0x2" description="SGPIO10" /> - <Enum name="SGPIO11" start="0x3" description="SGPIO11" /> - </BitField> - <BitField start="9" size="2" name="QUALIFIER_SLICE_MODE" description="Select qualifier slice."> - <Enum name="SLICE_A" start="0x0" description="Slice A, but for slice A slice D is used." /> - <Enum name="SLICE_H" start="0x1" description="Slice H, but for slice H slice O is used." /> - <Enum name="SLICE_I" start="0x2" description="Slice I, but for slice I slice D is used." /> - <Enum name="SLICE_P" start="0x3" description="Slice P, but for slice P slice O is used." /> - </BitField> - <BitField start="11" size="1" name="CONCAT_ENABLE" description="Enable concatenation."> - <Enum name="EXTERNAL_DATA_PIN" start="0x0" description="External data pin" /> - <Enum name="CONCATENATE_DATA" start="0x1" description="Concatenate data" /> - </BitField> - <BitField start="12" size="2" name="CONCAT_ORDER" description="Select concatenation order"> - <Enum name="SELF_LOOP" start="0x0" description="Self-loop" /> - <Enum name="2_SLICES" start="0x1" description="2 slices" /> - <Enum name="4_SLICES" start="0x2" description="4 slices" /> - <Enum name="8_SLICES" start="0x3" description="8 slices" /> - </BitField> - <BitField start="14" size="18" name="RESERVED" description="Reserved" /> - </Register> - <Register start="+0x0040+12" size="4" name="SGPIO_MUX_CFG[3]" access="Read/Write" description="SGPIO multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="1" name="EXT_CLK_ENABLE" description="Select clock signal."> - <Enum name="INTERNAL_CLOCK_SIGNA" start="0x0" description="Internal clock signal (slice)" /> - <Enum name="EXTERNAL_CLOCK_SIGNA" start="0x1" description="External clock signal (pin)" /> - </BitField> - <BitField start="1" size="2" name="CLK_SOURCE_PIN_MODE" description="Select source clock pin."> - <Enum name="SGPIO8" start="0x0" description="SGPIO8" /> - <Enum name="SGPIO9" start="0x1" description="SGPIO9" /> - <Enum name="SGPIO10" start="0x2" description="SGPIO10" /> - <Enum name="SGPIO11" start="0x3" description="SGPIO11" /> - </BitField> - <BitField start="3" size="2" name="CLK_SOURCE_SLICE_MODE" description="Select clock source slice. Note that slices D, H, O and P do not support this mode."> - <Enum name="SLICE_D" start="0x0" description="Slice D" /> - <Enum name="SLICE_H" start="0x1" description="Slice H" /> - <Enum name="SLICE_O" start="0x2" description="Slice O" /> - <Enum name="SLICE_P" start="0x3" description="Slice P" /> - </BitField> - <BitField start="5" size="2" name="QUALIFIER_MODE" description="Select qualifier mode."> - <Enum name="ENABLE" start="0x0" description="Enable" /> - <Enum name="DISABLE" start="0x1" description="Disable" /> - <Enum name="SLICE_SEE_BITS_QUAL" start="0x2" description="Slice (see bits QUALIFIER_SLICE_MODE in this register)" /> - <Enum name="EXTERNAL_SGPIO_PIN" start="0x3" description="External SGPIO pin (SGPIO8, SGPIO9, SGPIO10, or SGPIO11)" /> - </BitField> - <BitField start="7" size="2" name="QUALIFIER_PIN_MODE" description="Select qualifier pin."> - <Enum name="SGPIO8" start="0x0" description="SGPIO8" /> - <Enum name="SGPIO9" start="0x1" description="SGPIO9" /> - <Enum name="SGPIO10" start="0x2" description="SGPIO10" /> - <Enum name="SGPIO11" start="0x3" description="SGPIO11" /> - </BitField> - <BitField start="9" size="2" name="QUALIFIER_SLICE_MODE" description="Select qualifier slice."> - <Enum name="SLICE_A" start="0x0" description="Slice A, but for slice A slice D is used." /> - <Enum name="SLICE_H" start="0x1" description="Slice H, but for slice H slice O is used." /> - <Enum name="SLICE_I" start="0x2" description="Slice I, but for slice I slice D is used." /> - <Enum name="SLICE_P" start="0x3" description="Slice P, but for slice P slice O is used." /> - </BitField> - <BitField start="11" size="1" name="CONCAT_ENABLE" description="Enable concatenation."> - <Enum name="EXTERNAL_DATA_PIN" start="0x0" description="External data pin" /> - <Enum name="CONCATENATE_DATA" start="0x1" description="Concatenate data" /> - </BitField> - <BitField start="12" size="2" name="CONCAT_ORDER" description="Select concatenation order"> - <Enum name="SELF_LOOP" start="0x0" description="Self-loop" /> - <Enum name="2_SLICES" start="0x1" description="2 slices" /> - <Enum name="4_SLICES" start="0x2" description="4 slices" /> - <Enum name="8_SLICES" start="0x3" description="8 slices" /> - </BitField> - <BitField start="14" size="18" name="RESERVED" description="Reserved" /> - </Register> - <Register start="+0x0040+16" size="4" name="SGPIO_MUX_CFG[4]" access="Read/Write" description="SGPIO multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="1" name="EXT_CLK_ENABLE" description="Select clock signal."> - <Enum name="INTERNAL_CLOCK_SIGNA" start="0x0" description="Internal clock signal (slice)" /> - <Enum name="EXTERNAL_CLOCK_SIGNA" start="0x1" description="External clock signal (pin)" /> - </BitField> - <BitField start="1" size="2" name="CLK_SOURCE_PIN_MODE" description="Select source clock pin."> - <Enum name="SGPIO8" start="0x0" description="SGPIO8" /> - <Enum name="SGPIO9" start="0x1" description="SGPIO9" /> - <Enum name="SGPIO10" start="0x2" description="SGPIO10" /> - <Enum name="SGPIO11" start="0x3" description="SGPIO11" /> - </BitField> - <BitField start="3" size="2" name="CLK_SOURCE_SLICE_MODE" description="Select clock source slice. Note that slices D, H, O and P do not support this mode."> - <Enum name="SLICE_D" start="0x0" description="Slice D" /> - <Enum name="SLICE_H" start="0x1" description="Slice H" /> - <Enum name="SLICE_O" start="0x2" description="Slice O" /> - <Enum name="SLICE_P" start="0x3" description="Slice P" /> - </BitField> - <BitField start="5" size="2" name="QUALIFIER_MODE" description="Select qualifier mode."> - <Enum name="ENABLE" start="0x0" description="Enable" /> - <Enum name="DISABLE" start="0x1" description="Disable" /> - <Enum name="SLICE_SEE_BITS_QUAL" start="0x2" description="Slice (see bits QUALIFIER_SLICE_MODE in this register)" /> - <Enum name="EXTERNAL_SGPIO_PIN" start="0x3" description="External SGPIO pin (SGPIO8, SGPIO9, SGPIO10, or SGPIO11)" /> - </BitField> - <BitField start="7" size="2" name="QUALIFIER_PIN_MODE" description="Select qualifier pin."> - <Enum name="SGPIO8" start="0x0" description="SGPIO8" /> - <Enum name="SGPIO9" start="0x1" description="SGPIO9" /> - <Enum name="SGPIO10" start="0x2" description="SGPIO10" /> - <Enum name="SGPIO11" start="0x3" description="SGPIO11" /> - </BitField> - <BitField start="9" size="2" name="QUALIFIER_SLICE_MODE" description="Select qualifier slice."> - <Enum name="SLICE_A" start="0x0" description="Slice A, but for slice A slice D is used." /> - <Enum name="SLICE_H" start="0x1" description="Slice H, but for slice H slice O is used." /> - <Enum name="SLICE_I" start="0x2" description="Slice I, but for slice I slice D is used." /> - <Enum name="SLICE_P" start="0x3" description="Slice P, but for slice P slice O is used." /> - </BitField> - <BitField start="11" size="1" name="CONCAT_ENABLE" description="Enable concatenation."> - <Enum name="EXTERNAL_DATA_PIN" start="0x0" description="External data pin" /> - <Enum name="CONCATENATE_DATA" start="0x1" description="Concatenate data" /> - </BitField> - <BitField start="12" size="2" name="CONCAT_ORDER" description="Select concatenation order"> - <Enum name="SELF_LOOP" start="0x0" description="Self-loop" /> - <Enum name="2_SLICES" start="0x1" description="2 slices" /> - <Enum name="4_SLICES" start="0x2" description="4 slices" /> - <Enum name="8_SLICES" start="0x3" description="8 slices" /> - </BitField> - <BitField start="14" size="18" name="RESERVED" description="Reserved" /> - </Register> - <Register start="+0x0040+20" size="4" name="SGPIO_MUX_CFG[5]" access="Read/Write" description="SGPIO multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="1" name="EXT_CLK_ENABLE" description="Select clock signal."> - <Enum name="INTERNAL_CLOCK_SIGNA" start="0x0" description="Internal clock signal (slice)" /> - <Enum name="EXTERNAL_CLOCK_SIGNA" start="0x1" description="External clock signal (pin)" /> - </BitField> - <BitField start="1" size="2" name="CLK_SOURCE_PIN_MODE" description="Select source clock pin."> - <Enum name="SGPIO8" start="0x0" description="SGPIO8" /> - <Enum name="SGPIO9" start="0x1" description="SGPIO9" /> - <Enum name="SGPIO10" start="0x2" description="SGPIO10" /> - <Enum name="SGPIO11" start="0x3" description="SGPIO11" /> - </BitField> - <BitField start="3" size="2" name="CLK_SOURCE_SLICE_MODE" description="Select clock source slice. Note that slices D, H, O and P do not support this mode."> - <Enum name="SLICE_D" start="0x0" description="Slice D" /> - <Enum name="SLICE_H" start="0x1" description="Slice H" /> - <Enum name="SLICE_O" start="0x2" description="Slice O" /> - <Enum name="SLICE_P" start="0x3" description="Slice P" /> - </BitField> - <BitField start="5" size="2" name="QUALIFIER_MODE" description="Select qualifier mode."> - <Enum name="ENABLE" start="0x0" description="Enable" /> - <Enum name="DISABLE" start="0x1" description="Disable" /> - <Enum name="SLICE_SEE_BITS_QUAL" start="0x2" description="Slice (see bits QUALIFIER_SLICE_MODE in this register)" /> - <Enum name="EXTERNAL_SGPIO_PIN" start="0x3" description="External SGPIO pin (SGPIO8, SGPIO9, SGPIO10, or SGPIO11)" /> - </BitField> - <BitField start="7" size="2" name="QUALIFIER_PIN_MODE" description="Select qualifier pin."> - <Enum name="SGPIO8" start="0x0" description="SGPIO8" /> - <Enum name="SGPIO9" start="0x1" description="SGPIO9" /> - <Enum name="SGPIO10" start="0x2" description="SGPIO10" /> - <Enum name="SGPIO11" start="0x3" description="SGPIO11" /> - </BitField> - <BitField start="9" size="2" name="QUALIFIER_SLICE_MODE" description="Select qualifier slice."> - <Enum name="SLICE_A" start="0x0" description="Slice A, but for slice A slice D is used." /> - <Enum name="SLICE_H" start="0x1" description="Slice H, but for slice H slice O is used." /> - <Enum name="SLICE_I" start="0x2" description="Slice I, but for slice I slice D is used." /> - <Enum name="SLICE_P" start="0x3" description="Slice P, but for slice P slice O is used." /> - </BitField> - <BitField start="11" size="1" name="CONCAT_ENABLE" description="Enable concatenation."> - <Enum name="EXTERNAL_DATA_PIN" start="0x0" description="External data pin" /> - <Enum name="CONCATENATE_DATA" start="0x1" description="Concatenate data" /> - </BitField> - <BitField start="12" size="2" name="CONCAT_ORDER" description="Select concatenation order"> - <Enum name="SELF_LOOP" start="0x0" description="Self-loop" /> - <Enum name="2_SLICES" start="0x1" description="2 slices" /> - <Enum name="4_SLICES" start="0x2" description="4 slices" /> - <Enum name="8_SLICES" start="0x3" description="8 slices" /> - </BitField> - <BitField start="14" size="18" name="RESERVED" description="Reserved" /> - </Register> - <Register start="+0x0040+24" size="4" name="SGPIO_MUX_CFG[6]" access="Read/Write" description="SGPIO multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="1" name="EXT_CLK_ENABLE" description="Select clock signal."> - <Enum name="INTERNAL_CLOCK_SIGNA" start="0x0" description="Internal clock signal (slice)" /> - <Enum name="EXTERNAL_CLOCK_SIGNA" start="0x1" description="External clock signal (pin)" /> - </BitField> - <BitField start="1" size="2" name="CLK_SOURCE_PIN_MODE" description="Select source clock pin."> - <Enum name="SGPIO8" start="0x0" description="SGPIO8" /> - <Enum name="SGPIO9" start="0x1" description="SGPIO9" /> - <Enum name="SGPIO10" start="0x2" description="SGPIO10" /> - <Enum name="SGPIO11" start="0x3" description="SGPIO11" /> - </BitField> - <BitField start="3" size="2" name="CLK_SOURCE_SLICE_MODE" description="Select clock source slice. Note that slices D, H, O and P do not support this mode."> - <Enum name="SLICE_D" start="0x0" description="Slice D" /> - <Enum name="SLICE_H" start="0x1" description="Slice H" /> - <Enum name="SLICE_O" start="0x2" description="Slice O" /> - <Enum name="SLICE_P" start="0x3" description="Slice P" /> - </BitField> - <BitField start="5" size="2" name="QUALIFIER_MODE" description="Select qualifier mode."> - <Enum name="ENABLE" start="0x0" description="Enable" /> - <Enum name="DISABLE" start="0x1" description="Disable" /> - <Enum name="SLICE_SEE_BITS_QUAL" start="0x2" description="Slice (see bits QUALIFIER_SLICE_MODE in this register)" /> - <Enum name="EXTERNAL_SGPIO_PIN" start="0x3" description="External SGPIO pin (SGPIO8, SGPIO9, SGPIO10, or SGPIO11)" /> - </BitField> - <BitField start="7" size="2" name="QUALIFIER_PIN_MODE" description="Select qualifier pin."> - <Enum name="SGPIO8" start="0x0" description="SGPIO8" /> - <Enum name="SGPIO9" start="0x1" description="SGPIO9" /> - <Enum name="SGPIO10" start="0x2" description="SGPIO10" /> - <Enum name="SGPIO11" start="0x3" description="SGPIO11" /> - </BitField> - <BitField start="9" size="2" name="QUALIFIER_SLICE_MODE" description="Select qualifier slice."> - <Enum name="SLICE_A" start="0x0" description="Slice A, but for slice A slice D is used." /> - <Enum name="SLICE_H" start="0x1" description="Slice H, but for slice H slice O is used." /> - <Enum name="SLICE_I" start="0x2" description="Slice I, but for slice I slice D is used." /> - <Enum name="SLICE_P" start="0x3" description="Slice P, but for slice P slice O is used." /> - </BitField> - <BitField start="11" size="1" name="CONCAT_ENABLE" description="Enable concatenation."> - <Enum name="EXTERNAL_DATA_PIN" start="0x0" description="External data pin" /> - <Enum name="CONCATENATE_DATA" start="0x1" description="Concatenate data" /> - </BitField> - <BitField start="12" size="2" name="CONCAT_ORDER" description="Select concatenation order"> - <Enum name="SELF_LOOP" start="0x0" description="Self-loop" /> - <Enum name="2_SLICES" start="0x1" description="2 slices" /> - <Enum name="4_SLICES" start="0x2" description="4 slices" /> - <Enum name="8_SLICES" start="0x3" description="8 slices" /> - </BitField> - <BitField start="14" size="18" name="RESERVED" description="Reserved" /> - </Register> - <Register start="+0x0040+28" size="4" name="SGPIO_MUX_CFG[7]" access="Read/Write" description="SGPIO multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="1" name="EXT_CLK_ENABLE" description="Select clock signal."> - <Enum name="INTERNAL_CLOCK_SIGNA" start="0x0" description="Internal clock signal (slice)" /> - <Enum name="EXTERNAL_CLOCK_SIGNA" start="0x1" description="External clock signal (pin)" /> - </BitField> - <BitField start="1" size="2" name="CLK_SOURCE_PIN_MODE" description="Select source clock pin."> - <Enum name="SGPIO8" start="0x0" description="SGPIO8" /> - <Enum name="SGPIO9" start="0x1" description="SGPIO9" /> - <Enum name="SGPIO10" start="0x2" description="SGPIO10" /> - <Enum name="SGPIO11" start="0x3" description="SGPIO11" /> - </BitField> - <BitField start="3" size="2" name="CLK_SOURCE_SLICE_MODE" description="Select clock source slice. Note that slices D, H, O and P do not support this mode."> - <Enum name="SLICE_D" start="0x0" description="Slice D" /> - <Enum name="SLICE_H" start="0x1" description="Slice H" /> - <Enum name="SLICE_O" start="0x2" description="Slice O" /> - <Enum name="SLICE_P" start="0x3" description="Slice P" /> - </BitField> - <BitField start="5" size="2" name="QUALIFIER_MODE" description="Select qualifier mode."> - <Enum name="ENABLE" start="0x0" description="Enable" /> - <Enum name="DISABLE" start="0x1" description="Disable" /> - <Enum name="SLICE_SEE_BITS_QUAL" start="0x2" description="Slice (see bits QUALIFIER_SLICE_MODE in this register)" /> - <Enum name="EXTERNAL_SGPIO_PIN" start="0x3" description="External SGPIO pin (SGPIO8, SGPIO9, SGPIO10, or SGPIO11)" /> - </BitField> - <BitField start="7" size="2" name="QUALIFIER_PIN_MODE" description="Select qualifier pin."> - <Enum name="SGPIO8" start="0x0" description="SGPIO8" /> - <Enum name="SGPIO9" start="0x1" description="SGPIO9" /> - <Enum name="SGPIO10" start="0x2" description="SGPIO10" /> - <Enum name="SGPIO11" start="0x3" description="SGPIO11" /> - </BitField> - <BitField start="9" size="2" name="QUALIFIER_SLICE_MODE" description="Select qualifier slice."> - <Enum name="SLICE_A" start="0x0" description="Slice A, but for slice A slice D is used." /> - <Enum name="SLICE_H" start="0x1" description="Slice H, but for slice H slice O is used." /> - <Enum name="SLICE_I" start="0x2" description="Slice I, but for slice I slice D is used." /> - <Enum name="SLICE_P" start="0x3" description="Slice P, but for slice P slice O is used." /> - </BitField> - <BitField start="11" size="1" name="CONCAT_ENABLE" description="Enable concatenation."> - <Enum name="EXTERNAL_DATA_PIN" start="0x0" description="External data pin" /> - <Enum name="CONCATENATE_DATA" start="0x1" description="Concatenate data" /> - </BitField> - <BitField start="12" size="2" name="CONCAT_ORDER" description="Select concatenation order"> - <Enum name="SELF_LOOP" start="0x0" description="Self-loop" /> - <Enum name="2_SLICES" start="0x1" description="2 slices" /> - <Enum name="4_SLICES" start="0x2" description="4 slices" /> - <Enum name="8_SLICES" start="0x3" description="8 slices" /> - </BitField> - <BitField start="14" size="18" name="RESERVED" description="Reserved" /> - </Register> - <Register start="+0x0040+32" size="4" name="SGPIO_MUX_CFG[8]" access="Read/Write" description="SGPIO multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="1" name="EXT_CLK_ENABLE" description="Select clock signal."> - <Enum name="INTERNAL_CLOCK_SIGNA" start="0x0" description="Internal clock signal (slice)" /> - <Enum name="EXTERNAL_CLOCK_SIGNA" start="0x1" description="External clock signal (pin)" /> - </BitField> - <BitField start="1" size="2" name="CLK_SOURCE_PIN_MODE" description="Select source clock pin."> - <Enum name="SGPIO8" start="0x0" description="SGPIO8" /> - <Enum name="SGPIO9" start="0x1" description="SGPIO9" /> - <Enum name="SGPIO10" start="0x2" description="SGPIO10" /> - <Enum name="SGPIO11" start="0x3" description="SGPIO11" /> - </BitField> - <BitField start="3" size="2" name="CLK_SOURCE_SLICE_MODE" description="Select clock source slice. Note that slices D, H, O and P do not support this mode."> - <Enum name="SLICE_D" start="0x0" description="Slice D" /> - <Enum name="SLICE_H" start="0x1" description="Slice H" /> - <Enum name="SLICE_O" start="0x2" description="Slice O" /> - <Enum name="SLICE_P" start="0x3" description="Slice P" /> - </BitField> - <BitField start="5" size="2" name="QUALIFIER_MODE" description="Select qualifier mode."> - <Enum name="ENABLE" start="0x0" description="Enable" /> - <Enum name="DISABLE" start="0x1" description="Disable" /> - <Enum name="SLICE_SEE_BITS_QUAL" start="0x2" description="Slice (see bits QUALIFIER_SLICE_MODE in this register)" /> - <Enum name="EXTERNAL_SGPIO_PIN" start="0x3" description="External SGPIO pin (SGPIO8, SGPIO9, SGPIO10, or SGPIO11)" /> - </BitField> - <BitField start="7" size="2" name="QUALIFIER_PIN_MODE" description="Select qualifier pin."> - <Enum name="SGPIO8" start="0x0" description="SGPIO8" /> - <Enum name="SGPIO9" start="0x1" description="SGPIO9" /> - <Enum name="SGPIO10" start="0x2" description="SGPIO10" /> - <Enum name="SGPIO11" start="0x3" description="SGPIO11" /> - </BitField> - <BitField start="9" size="2" name="QUALIFIER_SLICE_MODE" description="Select qualifier slice."> - <Enum name="SLICE_A" start="0x0" description="Slice A, but for slice A slice D is used." /> - <Enum name="SLICE_H" start="0x1" description="Slice H, but for slice H slice O is used." /> - <Enum name="SLICE_I" start="0x2" description="Slice I, but for slice I slice D is used." /> - <Enum name="SLICE_P" start="0x3" description="Slice P, but for slice P slice O is used." /> - </BitField> - <BitField start="11" size="1" name="CONCAT_ENABLE" description="Enable concatenation."> - <Enum name="EXTERNAL_DATA_PIN" start="0x0" description="External data pin" /> - <Enum name="CONCATENATE_DATA" start="0x1" description="Concatenate data" /> - </BitField> - <BitField start="12" size="2" name="CONCAT_ORDER" description="Select concatenation order"> - <Enum name="SELF_LOOP" start="0x0" description="Self-loop" /> - <Enum name="2_SLICES" start="0x1" description="2 slices" /> - <Enum name="4_SLICES" start="0x2" description="4 slices" /> - <Enum name="8_SLICES" start="0x3" description="8 slices" /> - </BitField> - <BitField start="14" size="18" name="RESERVED" description="Reserved" /> - </Register> - <Register start="+0x0040+36" size="4" name="SGPIO_MUX_CFG[9]" access="Read/Write" description="SGPIO multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="1" name="EXT_CLK_ENABLE" description="Select clock signal."> - <Enum name="INTERNAL_CLOCK_SIGNA" start="0x0" description="Internal clock signal (slice)" /> - <Enum name="EXTERNAL_CLOCK_SIGNA" start="0x1" description="External clock signal (pin)" /> - </BitField> - <BitField start="1" size="2" name="CLK_SOURCE_PIN_MODE" description="Select source clock pin."> - <Enum name="SGPIO8" start="0x0" description="SGPIO8" /> - <Enum name="SGPIO9" start="0x1" description="SGPIO9" /> - <Enum name="SGPIO10" start="0x2" description="SGPIO10" /> - <Enum name="SGPIO11" start="0x3" description="SGPIO11" /> - </BitField> - <BitField start="3" size="2" name="CLK_SOURCE_SLICE_MODE" description="Select clock source slice. Note that slices D, H, O and P do not support this mode."> - <Enum name="SLICE_D" start="0x0" description="Slice D" /> - <Enum name="SLICE_H" start="0x1" description="Slice H" /> - <Enum name="SLICE_O" start="0x2" description="Slice O" /> - <Enum name="SLICE_P" start="0x3" description="Slice P" /> - </BitField> - <BitField start="5" size="2" name="QUALIFIER_MODE" description="Select qualifier mode."> - <Enum name="ENABLE" start="0x0" description="Enable" /> - <Enum name="DISABLE" start="0x1" description="Disable" /> - <Enum name="SLICE_SEE_BITS_QUAL" start="0x2" description="Slice (see bits QUALIFIER_SLICE_MODE in this register)" /> - <Enum name="EXTERNAL_SGPIO_PIN" start="0x3" description="External SGPIO pin (SGPIO8, SGPIO9, SGPIO10, or SGPIO11)" /> - </BitField> - <BitField start="7" size="2" name="QUALIFIER_PIN_MODE" description="Select qualifier pin."> - <Enum name="SGPIO8" start="0x0" description="SGPIO8" /> - <Enum name="SGPIO9" start="0x1" description="SGPIO9" /> - <Enum name="SGPIO10" start="0x2" description="SGPIO10" /> - <Enum name="SGPIO11" start="0x3" description="SGPIO11" /> - </BitField> - <BitField start="9" size="2" name="QUALIFIER_SLICE_MODE" description="Select qualifier slice."> - <Enum name="SLICE_A" start="0x0" description="Slice A, but for slice A slice D is used." /> - <Enum name="SLICE_H" start="0x1" description="Slice H, but for slice H slice O is used." /> - <Enum name="SLICE_I" start="0x2" description="Slice I, but for slice I slice D is used." /> - <Enum name="SLICE_P" start="0x3" description="Slice P, but for slice P slice O is used." /> - </BitField> - <BitField start="11" size="1" name="CONCAT_ENABLE" description="Enable concatenation."> - <Enum name="EXTERNAL_DATA_PIN" start="0x0" description="External data pin" /> - <Enum name="CONCATENATE_DATA" start="0x1" description="Concatenate data" /> - </BitField> - <BitField start="12" size="2" name="CONCAT_ORDER" description="Select concatenation order"> - <Enum name="SELF_LOOP" start="0x0" description="Self-loop" /> - <Enum name="2_SLICES" start="0x1" description="2 slices" /> - <Enum name="4_SLICES" start="0x2" description="4 slices" /> - <Enum name="8_SLICES" start="0x3" description="8 slices" /> - </BitField> - <BitField start="14" size="18" name="RESERVED" description="Reserved" /> - </Register> - <Register start="+0x0040+40" size="4" name="SGPIO_MUX_CFG[10]" access="Read/Write" description="SGPIO multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="1" name="EXT_CLK_ENABLE" description="Select clock signal."> - <Enum name="INTERNAL_CLOCK_SIGNA" start="0x0" description="Internal clock signal (slice)" /> - <Enum name="EXTERNAL_CLOCK_SIGNA" start="0x1" description="External clock signal (pin)" /> - </BitField> - <BitField start="1" size="2" name="CLK_SOURCE_PIN_MODE" description="Select source clock pin."> - <Enum name="SGPIO8" start="0x0" description="SGPIO8" /> - <Enum name="SGPIO9" start="0x1" description="SGPIO9" /> - <Enum name="SGPIO10" start="0x2" description="SGPIO10" /> - <Enum name="SGPIO11" start="0x3" description="SGPIO11" /> - </BitField> - <BitField start="3" size="2" name="CLK_SOURCE_SLICE_MODE" description="Select clock source slice. Note that slices D, H, O and P do not support this mode."> - <Enum name="SLICE_D" start="0x0" description="Slice D" /> - <Enum name="SLICE_H" start="0x1" description="Slice H" /> - <Enum name="SLICE_O" start="0x2" description="Slice O" /> - <Enum name="SLICE_P" start="0x3" description="Slice P" /> - </BitField> - <BitField start="5" size="2" name="QUALIFIER_MODE" description="Select qualifier mode."> - <Enum name="ENABLE" start="0x0" description="Enable" /> - <Enum name="DISABLE" start="0x1" description="Disable" /> - <Enum name="SLICE_SEE_BITS_QUAL" start="0x2" description="Slice (see bits QUALIFIER_SLICE_MODE in this register)" /> - <Enum name="EXTERNAL_SGPIO_PIN" start="0x3" description="External SGPIO pin (SGPIO8, SGPIO9, SGPIO10, or SGPIO11)" /> - </BitField> - <BitField start="7" size="2" name="QUALIFIER_PIN_MODE" description="Select qualifier pin."> - <Enum name="SGPIO8" start="0x0" description="SGPIO8" /> - <Enum name="SGPIO9" start="0x1" description="SGPIO9" /> - <Enum name="SGPIO10" start="0x2" description="SGPIO10" /> - <Enum name="SGPIO11" start="0x3" description="SGPIO11" /> - </BitField> - <BitField start="9" size="2" name="QUALIFIER_SLICE_MODE" description="Select qualifier slice."> - <Enum name="SLICE_A" start="0x0" description="Slice A, but for slice A slice D is used." /> - <Enum name="SLICE_H" start="0x1" description="Slice H, but for slice H slice O is used." /> - <Enum name="SLICE_I" start="0x2" description="Slice I, but for slice I slice D is used." /> - <Enum name="SLICE_P" start="0x3" description="Slice P, but for slice P slice O is used." /> - </BitField> - <BitField start="11" size="1" name="CONCAT_ENABLE" description="Enable concatenation."> - <Enum name="EXTERNAL_DATA_PIN" start="0x0" description="External data pin" /> - <Enum name="CONCATENATE_DATA" start="0x1" description="Concatenate data" /> - </BitField> - <BitField start="12" size="2" name="CONCAT_ORDER" description="Select concatenation order"> - <Enum name="SELF_LOOP" start="0x0" description="Self-loop" /> - <Enum name="2_SLICES" start="0x1" description="2 slices" /> - <Enum name="4_SLICES" start="0x2" description="4 slices" /> - <Enum name="8_SLICES" start="0x3" description="8 slices" /> - </BitField> - <BitField start="14" size="18" name="RESERVED" description="Reserved" /> - </Register> - <Register start="+0x0040+44" size="4" name="SGPIO_MUX_CFG[11]" access="Read/Write" description="SGPIO multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="1" name="EXT_CLK_ENABLE" description="Select clock signal."> - <Enum name="INTERNAL_CLOCK_SIGNA" start="0x0" description="Internal clock signal (slice)" /> - <Enum name="EXTERNAL_CLOCK_SIGNA" start="0x1" description="External clock signal (pin)" /> - </BitField> - <BitField start="1" size="2" name="CLK_SOURCE_PIN_MODE" description="Select source clock pin."> - <Enum name="SGPIO8" start="0x0" description="SGPIO8" /> - <Enum name="SGPIO9" start="0x1" description="SGPIO9" /> - <Enum name="SGPIO10" start="0x2" description="SGPIO10" /> - <Enum name="SGPIO11" start="0x3" description="SGPIO11" /> - </BitField> - <BitField start="3" size="2" name="CLK_SOURCE_SLICE_MODE" description="Select clock source slice. Note that slices D, H, O and P do not support this mode."> - <Enum name="SLICE_D" start="0x0" description="Slice D" /> - <Enum name="SLICE_H" start="0x1" description="Slice H" /> - <Enum name="SLICE_O" start="0x2" description="Slice O" /> - <Enum name="SLICE_P" start="0x3" description="Slice P" /> - </BitField> - <BitField start="5" size="2" name="QUALIFIER_MODE" description="Select qualifier mode."> - <Enum name="ENABLE" start="0x0" description="Enable" /> - <Enum name="DISABLE" start="0x1" description="Disable" /> - <Enum name="SLICE_SEE_BITS_QUAL" start="0x2" description="Slice (see bits QUALIFIER_SLICE_MODE in this register)" /> - <Enum name="EXTERNAL_SGPIO_PIN" start="0x3" description="External SGPIO pin (SGPIO8, SGPIO9, SGPIO10, or SGPIO11)" /> - </BitField> - <BitField start="7" size="2" name="QUALIFIER_PIN_MODE" description="Select qualifier pin."> - <Enum name="SGPIO8" start="0x0" description="SGPIO8" /> - <Enum name="SGPIO9" start="0x1" description="SGPIO9" /> - <Enum name="SGPIO10" start="0x2" description="SGPIO10" /> - <Enum name="SGPIO11" start="0x3" description="SGPIO11" /> - </BitField> - <BitField start="9" size="2" name="QUALIFIER_SLICE_MODE" description="Select qualifier slice."> - <Enum name="SLICE_A" start="0x0" description="Slice A, but for slice A slice D is used." /> - <Enum name="SLICE_H" start="0x1" description="Slice H, but for slice H slice O is used." /> - <Enum name="SLICE_I" start="0x2" description="Slice I, but for slice I slice D is used." /> - <Enum name="SLICE_P" start="0x3" description="Slice P, but for slice P slice O is used." /> - </BitField> - <BitField start="11" size="1" name="CONCAT_ENABLE" description="Enable concatenation."> - <Enum name="EXTERNAL_DATA_PIN" start="0x0" description="External data pin" /> - <Enum name="CONCATENATE_DATA" start="0x1" description="Concatenate data" /> - </BitField> - <BitField start="12" size="2" name="CONCAT_ORDER" description="Select concatenation order"> - <Enum name="SELF_LOOP" start="0x0" description="Self-loop" /> - <Enum name="2_SLICES" start="0x1" description="2 slices" /> - <Enum name="4_SLICES" start="0x2" description="4 slices" /> - <Enum name="8_SLICES" start="0x3" description="8 slices" /> - </BitField> - <BitField start="14" size="18" name="RESERVED" description="Reserved" /> - </Register> - <Register start="+0x0040+48" size="4" name="SGPIO_MUX_CFG[12]" access="Read/Write" description="SGPIO multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="1" name="EXT_CLK_ENABLE" description="Select clock signal."> - <Enum name="INTERNAL_CLOCK_SIGNA" start="0x0" description="Internal clock signal (slice)" /> - <Enum name="EXTERNAL_CLOCK_SIGNA" start="0x1" description="External clock signal (pin)" /> - </BitField> - <BitField start="1" size="2" name="CLK_SOURCE_PIN_MODE" description="Select source clock pin."> - <Enum name="SGPIO8" start="0x0" description="SGPIO8" /> - <Enum name="SGPIO9" start="0x1" description="SGPIO9" /> - <Enum name="SGPIO10" start="0x2" description="SGPIO10" /> - <Enum name="SGPIO11" start="0x3" description="SGPIO11" /> - </BitField> - <BitField start="3" size="2" name="CLK_SOURCE_SLICE_MODE" description="Select clock source slice. Note that slices D, H, O and P do not support this mode."> - <Enum name="SLICE_D" start="0x0" description="Slice D" /> - <Enum name="SLICE_H" start="0x1" description="Slice H" /> - <Enum name="SLICE_O" start="0x2" description="Slice O" /> - <Enum name="SLICE_P" start="0x3" description="Slice P" /> - </BitField> - <BitField start="5" size="2" name="QUALIFIER_MODE" description="Select qualifier mode."> - <Enum name="ENABLE" start="0x0" description="Enable" /> - <Enum name="DISABLE" start="0x1" description="Disable" /> - <Enum name="SLICE_SEE_BITS_QUAL" start="0x2" description="Slice (see bits QUALIFIER_SLICE_MODE in this register)" /> - <Enum name="EXTERNAL_SGPIO_PIN" start="0x3" description="External SGPIO pin (SGPIO8, SGPIO9, SGPIO10, or SGPIO11)" /> - </BitField> - <BitField start="7" size="2" name="QUALIFIER_PIN_MODE" description="Select qualifier pin."> - <Enum name="SGPIO8" start="0x0" description="SGPIO8" /> - <Enum name="SGPIO9" start="0x1" description="SGPIO9" /> - <Enum name="SGPIO10" start="0x2" description="SGPIO10" /> - <Enum name="SGPIO11" start="0x3" description="SGPIO11" /> - </BitField> - <BitField start="9" size="2" name="QUALIFIER_SLICE_MODE" description="Select qualifier slice."> - <Enum name="SLICE_A" start="0x0" description="Slice A, but for slice A slice D is used." /> - <Enum name="SLICE_H" start="0x1" description="Slice H, but for slice H slice O is used." /> - <Enum name="SLICE_I" start="0x2" description="Slice I, but for slice I slice D is used." /> - <Enum name="SLICE_P" start="0x3" description="Slice P, but for slice P slice O is used." /> - </BitField> - <BitField start="11" size="1" name="CONCAT_ENABLE" description="Enable concatenation."> - <Enum name="EXTERNAL_DATA_PIN" start="0x0" description="External data pin" /> - <Enum name="CONCATENATE_DATA" start="0x1" description="Concatenate data" /> - </BitField> - <BitField start="12" size="2" name="CONCAT_ORDER" description="Select concatenation order"> - <Enum name="SELF_LOOP" start="0x0" description="Self-loop" /> - <Enum name="2_SLICES" start="0x1" description="2 slices" /> - <Enum name="4_SLICES" start="0x2" description="4 slices" /> - <Enum name="8_SLICES" start="0x3" description="8 slices" /> - </BitField> - <BitField start="14" size="18" name="RESERVED" description="Reserved" /> - </Register> - <Register start="+0x0040+52" size="4" name="SGPIO_MUX_CFG[13]" access="Read/Write" description="SGPIO multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="1" name="EXT_CLK_ENABLE" description="Select clock signal."> - <Enum name="INTERNAL_CLOCK_SIGNA" start="0x0" description="Internal clock signal (slice)" /> - <Enum name="EXTERNAL_CLOCK_SIGNA" start="0x1" description="External clock signal (pin)" /> - </BitField> - <BitField start="1" size="2" name="CLK_SOURCE_PIN_MODE" description="Select source clock pin."> - <Enum name="SGPIO8" start="0x0" description="SGPIO8" /> - <Enum name="SGPIO9" start="0x1" description="SGPIO9" /> - <Enum name="SGPIO10" start="0x2" description="SGPIO10" /> - <Enum name="SGPIO11" start="0x3" description="SGPIO11" /> - </BitField> - <BitField start="3" size="2" name="CLK_SOURCE_SLICE_MODE" description="Select clock source slice. Note that slices D, H, O and P do not support this mode."> - <Enum name="SLICE_D" start="0x0" description="Slice D" /> - <Enum name="SLICE_H" start="0x1" description="Slice H" /> - <Enum name="SLICE_O" start="0x2" description="Slice O" /> - <Enum name="SLICE_P" start="0x3" description="Slice P" /> - </BitField> - <BitField start="5" size="2" name="QUALIFIER_MODE" description="Select qualifier mode."> - <Enum name="ENABLE" start="0x0" description="Enable" /> - <Enum name="DISABLE" start="0x1" description="Disable" /> - <Enum name="SLICE_SEE_BITS_QUAL" start="0x2" description="Slice (see bits QUALIFIER_SLICE_MODE in this register)" /> - <Enum name="EXTERNAL_SGPIO_PIN" start="0x3" description="External SGPIO pin (SGPIO8, SGPIO9, SGPIO10, or SGPIO11)" /> - </BitField> - <BitField start="7" size="2" name="QUALIFIER_PIN_MODE" description="Select qualifier pin."> - <Enum name="SGPIO8" start="0x0" description="SGPIO8" /> - <Enum name="SGPIO9" start="0x1" description="SGPIO9" /> - <Enum name="SGPIO10" start="0x2" description="SGPIO10" /> - <Enum name="SGPIO11" start="0x3" description="SGPIO11" /> - </BitField> - <BitField start="9" size="2" name="QUALIFIER_SLICE_MODE" description="Select qualifier slice."> - <Enum name="SLICE_A" start="0x0" description="Slice A, but for slice A slice D is used." /> - <Enum name="SLICE_H" start="0x1" description="Slice H, but for slice H slice O is used." /> - <Enum name="SLICE_I" start="0x2" description="Slice I, but for slice I slice D is used." /> - <Enum name="SLICE_P" start="0x3" description="Slice P, but for slice P slice O is used." /> - </BitField> - <BitField start="11" size="1" name="CONCAT_ENABLE" description="Enable concatenation."> - <Enum name="EXTERNAL_DATA_PIN" start="0x0" description="External data pin" /> - <Enum name="CONCATENATE_DATA" start="0x1" description="Concatenate data" /> - </BitField> - <BitField start="12" size="2" name="CONCAT_ORDER" description="Select concatenation order"> - <Enum name="SELF_LOOP" start="0x0" description="Self-loop" /> - <Enum name="2_SLICES" start="0x1" description="2 slices" /> - <Enum name="4_SLICES" start="0x2" description="4 slices" /> - <Enum name="8_SLICES" start="0x3" description="8 slices" /> - </BitField> - <BitField start="14" size="18" name="RESERVED" description="Reserved" /> - </Register> - <Register start="+0x0040+56" size="4" name="SGPIO_MUX_CFG[14]" access="Read/Write" description="SGPIO multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="1" name="EXT_CLK_ENABLE" description="Select clock signal."> - <Enum name="INTERNAL_CLOCK_SIGNA" start="0x0" description="Internal clock signal (slice)" /> - <Enum name="EXTERNAL_CLOCK_SIGNA" start="0x1" description="External clock signal (pin)" /> - </BitField> - <BitField start="1" size="2" name="CLK_SOURCE_PIN_MODE" description="Select source clock pin."> - <Enum name="SGPIO8" start="0x0" description="SGPIO8" /> - <Enum name="SGPIO9" start="0x1" description="SGPIO9" /> - <Enum name="SGPIO10" start="0x2" description="SGPIO10" /> - <Enum name="SGPIO11" start="0x3" description="SGPIO11" /> - </BitField> - <BitField start="3" size="2" name="CLK_SOURCE_SLICE_MODE" description="Select clock source slice. Note that slices D, H, O and P do not support this mode."> - <Enum name="SLICE_D" start="0x0" description="Slice D" /> - <Enum name="SLICE_H" start="0x1" description="Slice H" /> - <Enum name="SLICE_O" start="0x2" description="Slice O" /> - <Enum name="SLICE_P" start="0x3" description="Slice P" /> - </BitField> - <BitField start="5" size="2" name="QUALIFIER_MODE" description="Select qualifier mode."> - <Enum name="ENABLE" start="0x0" description="Enable" /> - <Enum name="DISABLE" start="0x1" description="Disable" /> - <Enum name="SLICE_SEE_BITS_QUAL" start="0x2" description="Slice (see bits QUALIFIER_SLICE_MODE in this register)" /> - <Enum name="EXTERNAL_SGPIO_PIN" start="0x3" description="External SGPIO pin (SGPIO8, SGPIO9, SGPIO10, or SGPIO11)" /> - </BitField> - <BitField start="7" size="2" name="QUALIFIER_PIN_MODE" description="Select qualifier pin."> - <Enum name="SGPIO8" start="0x0" description="SGPIO8" /> - <Enum name="SGPIO9" start="0x1" description="SGPIO9" /> - <Enum name="SGPIO10" start="0x2" description="SGPIO10" /> - <Enum name="SGPIO11" start="0x3" description="SGPIO11" /> - </BitField> - <BitField start="9" size="2" name="QUALIFIER_SLICE_MODE" description="Select qualifier slice."> - <Enum name="SLICE_A" start="0x0" description="Slice A, but for slice A slice D is used." /> - <Enum name="SLICE_H" start="0x1" description="Slice H, but for slice H slice O is used." /> - <Enum name="SLICE_I" start="0x2" description="Slice I, but for slice I slice D is used." /> - <Enum name="SLICE_P" start="0x3" description="Slice P, but for slice P slice O is used." /> - </BitField> - <BitField start="11" size="1" name="CONCAT_ENABLE" description="Enable concatenation."> - <Enum name="EXTERNAL_DATA_PIN" start="0x0" description="External data pin" /> - <Enum name="CONCATENATE_DATA" start="0x1" description="Concatenate data" /> - </BitField> - <BitField start="12" size="2" name="CONCAT_ORDER" description="Select concatenation order"> - <Enum name="SELF_LOOP" start="0x0" description="Self-loop" /> - <Enum name="2_SLICES" start="0x1" description="2 slices" /> - <Enum name="4_SLICES" start="0x2" description="4 slices" /> - <Enum name="8_SLICES" start="0x3" description="8 slices" /> - </BitField> - <BitField start="14" size="18" name="RESERVED" description="Reserved" /> - </Register> - <Register start="+0x0040+60" size="4" name="SGPIO_MUX_CFG[15]" access="Read/Write" description="SGPIO multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="1" name="EXT_CLK_ENABLE" description="Select clock signal."> - <Enum name="INTERNAL_CLOCK_SIGNA" start="0x0" description="Internal clock signal (slice)" /> - <Enum name="EXTERNAL_CLOCK_SIGNA" start="0x1" description="External clock signal (pin)" /> - </BitField> - <BitField start="1" size="2" name="CLK_SOURCE_PIN_MODE" description="Select source clock pin."> - <Enum name="SGPIO8" start="0x0" description="SGPIO8" /> - <Enum name="SGPIO9" start="0x1" description="SGPIO9" /> - <Enum name="SGPIO10" start="0x2" description="SGPIO10" /> - <Enum name="SGPIO11" start="0x3" description="SGPIO11" /> - </BitField> - <BitField start="3" size="2" name="CLK_SOURCE_SLICE_MODE" description="Select clock source slice. Note that slices D, H, O and P do not support this mode."> - <Enum name="SLICE_D" start="0x0" description="Slice D" /> - <Enum name="SLICE_H" start="0x1" description="Slice H" /> - <Enum name="SLICE_O" start="0x2" description="Slice O" /> - <Enum name="SLICE_P" start="0x3" description="Slice P" /> - </BitField> - <BitField start="5" size="2" name="QUALIFIER_MODE" description="Select qualifier mode."> - <Enum name="ENABLE" start="0x0" description="Enable" /> - <Enum name="DISABLE" start="0x1" description="Disable" /> - <Enum name="SLICE_SEE_BITS_QUAL" start="0x2" description="Slice (see bits QUALIFIER_SLICE_MODE in this register)" /> - <Enum name="EXTERNAL_SGPIO_PIN" start="0x3" description="External SGPIO pin (SGPIO8, SGPIO9, SGPIO10, or SGPIO11)" /> - </BitField> - <BitField start="7" size="2" name="QUALIFIER_PIN_MODE" description="Select qualifier pin."> - <Enum name="SGPIO8" start="0x0" description="SGPIO8" /> - <Enum name="SGPIO9" start="0x1" description="SGPIO9" /> - <Enum name="SGPIO10" start="0x2" description="SGPIO10" /> - <Enum name="SGPIO11" start="0x3" description="SGPIO11" /> - </BitField> - <BitField start="9" size="2" name="QUALIFIER_SLICE_MODE" description="Select qualifier slice."> - <Enum name="SLICE_A" start="0x0" description="Slice A, but for slice A slice D is used." /> - <Enum name="SLICE_H" start="0x1" description="Slice H, but for slice H slice O is used." /> - <Enum name="SLICE_I" start="0x2" description="Slice I, but for slice I slice D is used." /> - <Enum name="SLICE_P" start="0x3" description="Slice P, but for slice P slice O is used." /> - </BitField> - <BitField start="11" size="1" name="CONCAT_ENABLE" description="Enable concatenation."> - <Enum name="EXTERNAL_DATA_PIN" start="0x0" description="External data pin" /> - <Enum name="CONCATENATE_DATA" start="0x1" description="Concatenate data" /> - </BitField> - <BitField start="12" size="2" name="CONCAT_ORDER" description="Select concatenation order"> - <Enum name="SELF_LOOP" start="0x0" description="Self-loop" /> - <Enum name="2_SLICES" start="0x1" description="2 slices" /> - <Enum name="4_SLICES" start="0x2" description="4 slices" /> - <Enum name="8_SLICES" start="0x3" description="8 slices" /> - </BitField> - <BitField start="14" size="18" name="RESERVED" description="Reserved" /> - </Register> - <Register start="+0x0080+0" size="4" name="SLICE_MUX_CFG[0]" access="Read/Write" description="Slice multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="1" name="MATCH_MODE" description="Match mode. Selects whether the match filter is active or whether data is captured."> - <Enum name="DO_NOT_MATCH_DATA" start="0x0" description="Do not match data." /> - <Enum name="MATCH_DATA" start="0x1" description="Match data." /> - </BitField> - <BitField start="1" size="1" name="CLK_CAPTURE_MODE" description="Capture clock mode"> - <Enum name="USE_RISING_CLOCK_EDG" start="0x0" description="Use rising clock edge." /> - <Enum name="USE_FALLING_CLOCK_ED" start="0x1" description="Use falling clock edge." /> - </BitField> - <BitField start="2" size="1" name="CLKGEN_MODE" description="Clock generation mode. Selects the clock generated by the slice counter or by an external pin or other slice as shift clock."> - <Enum name="USE_CLOCK_INTERNALLY" start="0x0" description="Use clock internally generated by COUNTER." /> - <Enum name="USE_EXTERNAL_CLOCK_F" start="0x1" description="Use external clock from a pin or other slice." /> - </BitField> - <BitField start="3" size="1" name="INV_OUT_CLK" description="Invert output clock"> - <Enum name="NORMAL_CLOCK" start="0x0" description="Normal clock." /> - <Enum name="INVERTED_CLOCK" start="0x1" description="Inverted clock." /> - </BitField> - <BitField start="4" size="2" name="DATA_CAPTURE_MODE" description="Condition for input bit match interrupt"> - <Enum name="DETECT_RISING_EDGE" start="0x0" description="Detect rising edge." /> - <Enum name="DETECT_FALLING_EDGE" start="0x1" description="Detect falling edge." /> - <Enum name="DETECT_LOW_LEVEL" start="0x2" description="Detect LOW level." /> - <Enum name="DETECT_HIGH_LEVEL" start="0x3" description="Detect HIGH level." /> - </BitField> - <BitField start="6" size="2" name="PARALLEL_MODE" description="Parallel mode"> - <Enum name="SHIFT_1_BIT_PER_CLOC" start="0x0" description="Shift 1 bit per clock." /> - <Enum name="SHIFT_2_BITS_PER_CLO" start="0x1" description="Shift 2 bits per clock." /> - <Enum name="SHIFT_4_BITS_PER_CLO" start="0x2" description="Shift 4 bits per clock." /> - <Enum name="SHIFT_1_BYTE_PER_CLO" start="0x3" description="Shift 1 byte per clock." /> - </BitField> - <BitField start="8" size="1" name="INV_QUALIFIER" description="Inversion qualifier"> - <Enum name="USE_NORMAL_QUALIFIER" start="0x0" description="Use normal qualifier." /> - <Enum name="USE_INVERTED_QUALIFI" start="0x1" description="Use inverted qualifier." /> - </BitField> - <BitField start="9" size="23" name="RESERVED" description="Reserved." /> - </Register> - <Register start="+0x0080+4" size="4" name="SLICE_MUX_CFG[1]" access="Read/Write" description="Slice multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="1" name="MATCH_MODE" description="Match mode. Selects whether the match filter is active or whether data is captured."> - <Enum name="DO_NOT_MATCH_DATA" start="0x0" description="Do not match data." /> - <Enum name="MATCH_DATA" start="0x1" description="Match data." /> - </BitField> - <BitField start="1" size="1" name="CLK_CAPTURE_MODE" description="Capture clock mode"> - <Enum name="USE_RISING_CLOCK_EDG" start="0x0" description="Use rising clock edge." /> - <Enum name="USE_FALLING_CLOCK_ED" start="0x1" description="Use falling clock edge." /> - </BitField> - <BitField start="2" size="1" name="CLKGEN_MODE" description="Clock generation mode. Selects the clock generated by the slice counter or by an external pin or other slice as shift clock."> - <Enum name="USE_CLOCK_INTERNALLY" start="0x0" description="Use clock internally generated by COUNTER." /> - <Enum name="USE_EXTERNAL_CLOCK_F" start="0x1" description="Use external clock from a pin or other slice." /> - </BitField> - <BitField start="3" size="1" name="INV_OUT_CLK" description="Invert output clock"> - <Enum name="NORMAL_CLOCK" start="0x0" description="Normal clock." /> - <Enum name="INVERTED_CLOCK" start="0x1" description="Inverted clock." /> - </BitField> - <BitField start="4" size="2" name="DATA_CAPTURE_MODE" description="Condition for input bit match interrupt"> - <Enum name="DETECT_RISING_EDGE" start="0x0" description="Detect rising edge." /> - <Enum name="DETECT_FALLING_EDGE" start="0x1" description="Detect falling edge." /> - <Enum name="DETECT_LOW_LEVEL" start="0x2" description="Detect LOW level." /> - <Enum name="DETECT_HIGH_LEVEL" start="0x3" description="Detect HIGH level." /> - </BitField> - <BitField start="6" size="2" name="PARALLEL_MODE" description="Parallel mode"> - <Enum name="SHIFT_1_BIT_PER_CLOC" start="0x0" description="Shift 1 bit per clock." /> - <Enum name="SHIFT_2_BITS_PER_CLO" start="0x1" description="Shift 2 bits per clock." /> - <Enum name="SHIFT_4_BITS_PER_CLO" start="0x2" description="Shift 4 bits per clock." /> - <Enum name="SHIFT_1_BYTE_PER_CLO" start="0x3" description="Shift 1 byte per clock." /> - </BitField> - <BitField start="8" size="1" name="INV_QUALIFIER" description="Inversion qualifier"> - <Enum name="USE_NORMAL_QUALIFIER" start="0x0" description="Use normal qualifier." /> - <Enum name="USE_INVERTED_QUALIFI" start="0x1" description="Use inverted qualifier." /> - </BitField> - <BitField start="9" size="23" name="RESERVED" description="Reserved." /> - </Register> - <Register start="+0x0080+8" size="4" name="SLICE_MUX_CFG[2]" access="Read/Write" description="Slice multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="1" name="MATCH_MODE" description="Match mode. Selects whether the match filter is active or whether data is captured."> - <Enum name="DO_NOT_MATCH_DATA" start="0x0" description="Do not match data." /> - <Enum name="MATCH_DATA" start="0x1" description="Match data." /> - </BitField> - <BitField start="1" size="1" name="CLK_CAPTURE_MODE" description="Capture clock mode"> - <Enum name="USE_RISING_CLOCK_EDG" start="0x0" description="Use rising clock edge." /> - <Enum name="USE_FALLING_CLOCK_ED" start="0x1" description="Use falling clock edge." /> - </BitField> - <BitField start="2" size="1" name="CLKGEN_MODE" description="Clock generation mode. Selects the clock generated by the slice counter or by an external pin or other slice as shift clock."> - <Enum name="USE_CLOCK_INTERNALLY" start="0x0" description="Use clock internally generated by COUNTER." /> - <Enum name="USE_EXTERNAL_CLOCK_F" start="0x1" description="Use external clock from a pin or other slice." /> - </BitField> - <BitField start="3" size="1" name="INV_OUT_CLK" description="Invert output clock"> - <Enum name="NORMAL_CLOCK" start="0x0" description="Normal clock." /> - <Enum name="INVERTED_CLOCK" start="0x1" description="Inverted clock." /> - </BitField> - <BitField start="4" size="2" name="DATA_CAPTURE_MODE" description="Condition for input bit match interrupt"> - <Enum name="DETECT_RISING_EDGE" start="0x0" description="Detect rising edge." /> - <Enum name="DETECT_FALLING_EDGE" start="0x1" description="Detect falling edge." /> - <Enum name="DETECT_LOW_LEVEL" start="0x2" description="Detect LOW level." /> - <Enum name="DETECT_HIGH_LEVEL" start="0x3" description="Detect HIGH level." /> - </BitField> - <BitField start="6" size="2" name="PARALLEL_MODE" description="Parallel mode"> - <Enum name="SHIFT_1_BIT_PER_CLOC" start="0x0" description="Shift 1 bit per clock." /> - <Enum name="SHIFT_2_BITS_PER_CLO" start="0x1" description="Shift 2 bits per clock." /> - <Enum name="SHIFT_4_BITS_PER_CLO" start="0x2" description="Shift 4 bits per clock." /> - <Enum name="SHIFT_1_BYTE_PER_CLO" start="0x3" description="Shift 1 byte per clock." /> - </BitField> - <BitField start="8" size="1" name="INV_QUALIFIER" description="Inversion qualifier"> - <Enum name="USE_NORMAL_QUALIFIER" start="0x0" description="Use normal qualifier." /> - <Enum name="USE_INVERTED_QUALIFI" start="0x1" description="Use inverted qualifier." /> - </BitField> - <BitField start="9" size="23" name="RESERVED" description="Reserved." /> - </Register> - <Register start="+0x0080+12" size="4" name="SLICE_MUX_CFG[3]" access="Read/Write" description="Slice multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="1" name="MATCH_MODE" description="Match mode. Selects whether the match filter is active or whether data is captured."> - <Enum name="DO_NOT_MATCH_DATA" start="0x0" description="Do not match data." /> - <Enum name="MATCH_DATA" start="0x1" description="Match data." /> - </BitField> - <BitField start="1" size="1" name="CLK_CAPTURE_MODE" description="Capture clock mode"> - <Enum name="USE_RISING_CLOCK_EDG" start="0x0" description="Use rising clock edge." /> - <Enum name="USE_FALLING_CLOCK_ED" start="0x1" description="Use falling clock edge." /> - </BitField> - <BitField start="2" size="1" name="CLKGEN_MODE" description="Clock generation mode. Selects the clock generated by the slice counter or by an external pin or other slice as shift clock."> - <Enum name="USE_CLOCK_INTERNALLY" start="0x0" description="Use clock internally generated by COUNTER." /> - <Enum name="USE_EXTERNAL_CLOCK_F" start="0x1" description="Use external clock from a pin or other slice." /> - </BitField> - <BitField start="3" size="1" name="INV_OUT_CLK" description="Invert output clock"> - <Enum name="NORMAL_CLOCK" start="0x0" description="Normal clock." /> - <Enum name="INVERTED_CLOCK" start="0x1" description="Inverted clock." /> - </BitField> - <BitField start="4" size="2" name="DATA_CAPTURE_MODE" description="Condition for input bit match interrupt"> - <Enum name="DETECT_RISING_EDGE" start="0x0" description="Detect rising edge." /> - <Enum name="DETECT_FALLING_EDGE" start="0x1" description="Detect falling edge." /> - <Enum name="DETECT_LOW_LEVEL" start="0x2" description="Detect LOW level." /> - <Enum name="DETECT_HIGH_LEVEL" start="0x3" description="Detect HIGH level." /> - </BitField> - <BitField start="6" size="2" name="PARALLEL_MODE" description="Parallel mode"> - <Enum name="SHIFT_1_BIT_PER_CLOC" start="0x0" description="Shift 1 bit per clock." /> - <Enum name="SHIFT_2_BITS_PER_CLO" start="0x1" description="Shift 2 bits per clock." /> - <Enum name="SHIFT_4_BITS_PER_CLO" start="0x2" description="Shift 4 bits per clock." /> - <Enum name="SHIFT_1_BYTE_PER_CLO" start="0x3" description="Shift 1 byte per clock." /> - </BitField> - <BitField start="8" size="1" name="INV_QUALIFIER" description="Inversion qualifier"> - <Enum name="USE_NORMAL_QUALIFIER" start="0x0" description="Use normal qualifier." /> - <Enum name="USE_INVERTED_QUALIFI" start="0x1" description="Use inverted qualifier." /> - </BitField> - <BitField start="9" size="23" name="RESERVED" description="Reserved." /> - </Register> - <Register start="+0x0080+16" size="4" name="SLICE_MUX_CFG[4]" access="Read/Write" description="Slice multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="1" name="MATCH_MODE" description="Match mode. Selects whether the match filter is active or whether data is captured."> - <Enum name="DO_NOT_MATCH_DATA" start="0x0" description="Do not match data." /> - <Enum name="MATCH_DATA" start="0x1" description="Match data." /> - </BitField> - <BitField start="1" size="1" name="CLK_CAPTURE_MODE" description="Capture clock mode"> - <Enum name="USE_RISING_CLOCK_EDG" start="0x0" description="Use rising clock edge." /> - <Enum name="USE_FALLING_CLOCK_ED" start="0x1" description="Use falling clock edge." /> - </BitField> - <BitField start="2" size="1" name="CLKGEN_MODE" description="Clock generation mode. Selects the clock generated by the slice counter or by an external pin or other slice as shift clock."> - <Enum name="USE_CLOCK_INTERNALLY" start="0x0" description="Use clock internally generated by COUNTER." /> - <Enum name="USE_EXTERNAL_CLOCK_F" start="0x1" description="Use external clock from a pin or other slice." /> - </BitField> - <BitField start="3" size="1" name="INV_OUT_CLK" description="Invert output clock"> - <Enum name="NORMAL_CLOCK" start="0x0" description="Normal clock." /> - <Enum name="INVERTED_CLOCK" start="0x1" description="Inverted clock." /> - </BitField> - <BitField start="4" size="2" name="DATA_CAPTURE_MODE" description="Condition for input bit match interrupt"> - <Enum name="DETECT_RISING_EDGE" start="0x0" description="Detect rising edge." /> - <Enum name="DETECT_FALLING_EDGE" start="0x1" description="Detect falling edge." /> - <Enum name="DETECT_LOW_LEVEL" start="0x2" description="Detect LOW level." /> - <Enum name="DETECT_HIGH_LEVEL" start="0x3" description="Detect HIGH level." /> - </BitField> - <BitField start="6" size="2" name="PARALLEL_MODE" description="Parallel mode"> - <Enum name="SHIFT_1_BIT_PER_CLOC" start="0x0" description="Shift 1 bit per clock." /> - <Enum name="SHIFT_2_BITS_PER_CLO" start="0x1" description="Shift 2 bits per clock." /> - <Enum name="SHIFT_4_BITS_PER_CLO" start="0x2" description="Shift 4 bits per clock." /> - <Enum name="SHIFT_1_BYTE_PER_CLO" start="0x3" description="Shift 1 byte per clock." /> - </BitField> - <BitField start="8" size="1" name="INV_QUALIFIER" description="Inversion qualifier"> - <Enum name="USE_NORMAL_QUALIFIER" start="0x0" description="Use normal qualifier." /> - <Enum name="USE_INVERTED_QUALIFI" start="0x1" description="Use inverted qualifier." /> - </BitField> - <BitField start="9" size="23" name="RESERVED" description="Reserved." /> - </Register> - <Register start="+0x0080+20" size="4" name="SLICE_MUX_CFG[5]" access="Read/Write" description="Slice multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="1" name="MATCH_MODE" description="Match mode. Selects whether the match filter is active or whether data is captured."> - <Enum name="DO_NOT_MATCH_DATA" start="0x0" description="Do not match data." /> - <Enum name="MATCH_DATA" start="0x1" description="Match data." /> - </BitField> - <BitField start="1" size="1" name="CLK_CAPTURE_MODE" description="Capture clock mode"> - <Enum name="USE_RISING_CLOCK_EDG" start="0x0" description="Use rising clock edge." /> - <Enum name="USE_FALLING_CLOCK_ED" start="0x1" description="Use falling clock edge." /> - </BitField> - <BitField start="2" size="1" name="CLKGEN_MODE" description="Clock generation mode. Selects the clock generated by the slice counter or by an external pin or other slice as shift clock."> - <Enum name="USE_CLOCK_INTERNALLY" start="0x0" description="Use clock internally generated by COUNTER." /> - <Enum name="USE_EXTERNAL_CLOCK_F" start="0x1" description="Use external clock from a pin or other slice." /> - </BitField> - <BitField start="3" size="1" name="INV_OUT_CLK" description="Invert output clock"> - <Enum name="NORMAL_CLOCK" start="0x0" description="Normal clock." /> - <Enum name="INVERTED_CLOCK" start="0x1" description="Inverted clock." /> - </BitField> - <BitField start="4" size="2" name="DATA_CAPTURE_MODE" description="Condition for input bit match interrupt"> - <Enum name="DETECT_RISING_EDGE" start="0x0" description="Detect rising edge." /> - <Enum name="DETECT_FALLING_EDGE" start="0x1" description="Detect falling edge." /> - <Enum name="DETECT_LOW_LEVEL" start="0x2" description="Detect LOW level." /> - <Enum name="DETECT_HIGH_LEVEL" start="0x3" description="Detect HIGH level." /> - </BitField> - <BitField start="6" size="2" name="PARALLEL_MODE" description="Parallel mode"> - <Enum name="SHIFT_1_BIT_PER_CLOC" start="0x0" description="Shift 1 bit per clock." /> - <Enum name="SHIFT_2_BITS_PER_CLO" start="0x1" description="Shift 2 bits per clock." /> - <Enum name="SHIFT_4_BITS_PER_CLO" start="0x2" description="Shift 4 bits per clock." /> - <Enum name="SHIFT_1_BYTE_PER_CLO" start="0x3" description="Shift 1 byte per clock." /> - </BitField> - <BitField start="8" size="1" name="INV_QUALIFIER" description="Inversion qualifier"> - <Enum name="USE_NORMAL_QUALIFIER" start="0x0" description="Use normal qualifier." /> - <Enum name="USE_INVERTED_QUALIFI" start="0x1" description="Use inverted qualifier." /> - </BitField> - <BitField start="9" size="23" name="RESERVED" description="Reserved." /> - </Register> - <Register start="+0x0080+24" size="4" name="SLICE_MUX_CFG[6]" access="Read/Write" description="Slice multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="1" name="MATCH_MODE" description="Match mode. Selects whether the match filter is active or whether data is captured."> - <Enum name="DO_NOT_MATCH_DATA" start="0x0" description="Do not match data." /> - <Enum name="MATCH_DATA" start="0x1" description="Match data." /> - </BitField> - <BitField start="1" size="1" name="CLK_CAPTURE_MODE" description="Capture clock mode"> - <Enum name="USE_RISING_CLOCK_EDG" start="0x0" description="Use rising clock edge." /> - <Enum name="USE_FALLING_CLOCK_ED" start="0x1" description="Use falling clock edge." /> - </BitField> - <BitField start="2" size="1" name="CLKGEN_MODE" description="Clock generation mode. Selects the clock generated by the slice counter or by an external pin or other slice as shift clock."> - <Enum name="USE_CLOCK_INTERNALLY" start="0x0" description="Use clock internally generated by COUNTER." /> - <Enum name="USE_EXTERNAL_CLOCK_F" start="0x1" description="Use external clock from a pin or other slice." /> - </BitField> - <BitField start="3" size="1" name="INV_OUT_CLK" description="Invert output clock"> - <Enum name="NORMAL_CLOCK" start="0x0" description="Normal clock." /> - <Enum name="INVERTED_CLOCK" start="0x1" description="Inverted clock." /> - </BitField> - <BitField start="4" size="2" name="DATA_CAPTURE_MODE" description="Condition for input bit match interrupt"> - <Enum name="DETECT_RISING_EDGE" start="0x0" description="Detect rising edge." /> - <Enum name="DETECT_FALLING_EDGE" start="0x1" description="Detect falling edge." /> - <Enum name="DETECT_LOW_LEVEL" start="0x2" description="Detect LOW level." /> - <Enum name="DETECT_HIGH_LEVEL" start="0x3" description="Detect HIGH level." /> - </BitField> - <BitField start="6" size="2" name="PARALLEL_MODE" description="Parallel mode"> - <Enum name="SHIFT_1_BIT_PER_CLOC" start="0x0" description="Shift 1 bit per clock." /> - <Enum name="SHIFT_2_BITS_PER_CLO" start="0x1" description="Shift 2 bits per clock." /> - <Enum name="SHIFT_4_BITS_PER_CLO" start="0x2" description="Shift 4 bits per clock." /> - <Enum name="SHIFT_1_BYTE_PER_CLO" start="0x3" description="Shift 1 byte per clock." /> - </BitField> - <BitField start="8" size="1" name="INV_QUALIFIER" description="Inversion qualifier"> - <Enum name="USE_NORMAL_QUALIFIER" start="0x0" description="Use normal qualifier." /> - <Enum name="USE_INVERTED_QUALIFI" start="0x1" description="Use inverted qualifier." /> - </BitField> - <BitField start="9" size="23" name="RESERVED" description="Reserved." /> - </Register> - <Register start="+0x0080+28" size="4" name="SLICE_MUX_CFG[7]" access="Read/Write" description="Slice multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="1" name="MATCH_MODE" description="Match mode. Selects whether the match filter is active or whether data is captured."> - <Enum name="DO_NOT_MATCH_DATA" start="0x0" description="Do not match data." /> - <Enum name="MATCH_DATA" start="0x1" description="Match data." /> - </BitField> - <BitField start="1" size="1" name="CLK_CAPTURE_MODE" description="Capture clock mode"> - <Enum name="USE_RISING_CLOCK_EDG" start="0x0" description="Use rising clock edge." /> - <Enum name="USE_FALLING_CLOCK_ED" start="0x1" description="Use falling clock edge." /> - </BitField> - <BitField start="2" size="1" name="CLKGEN_MODE" description="Clock generation mode. Selects the clock generated by the slice counter or by an external pin or other slice as shift clock."> - <Enum name="USE_CLOCK_INTERNALLY" start="0x0" description="Use clock internally generated by COUNTER." /> - <Enum name="USE_EXTERNAL_CLOCK_F" start="0x1" description="Use external clock from a pin or other slice." /> - </BitField> - <BitField start="3" size="1" name="INV_OUT_CLK" description="Invert output clock"> - <Enum name="NORMAL_CLOCK" start="0x0" description="Normal clock." /> - <Enum name="INVERTED_CLOCK" start="0x1" description="Inverted clock." /> - </BitField> - <BitField start="4" size="2" name="DATA_CAPTURE_MODE" description="Condition for input bit match interrupt"> - <Enum name="DETECT_RISING_EDGE" start="0x0" description="Detect rising edge." /> - <Enum name="DETECT_FALLING_EDGE" start="0x1" description="Detect falling edge." /> - <Enum name="DETECT_LOW_LEVEL" start="0x2" description="Detect LOW level." /> - <Enum name="DETECT_HIGH_LEVEL" start="0x3" description="Detect HIGH level." /> - </BitField> - <BitField start="6" size="2" name="PARALLEL_MODE" description="Parallel mode"> - <Enum name="SHIFT_1_BIT_PER_CLOC" start="0x0" description="Shift 1 bit per clock." /> - <Enum name="SHIFT_2_BITS_PER_CLO" start="0x1" description="Shift 2 bits per clock." /> - <Enum name="SHIFT_4_BITS_PER_CLO" start="0x2" description="Shift 4 bits per clock." /> - <Enum name="SHIFT_1_BYTE_PER_CLO" start="0x3" description="Shift 1 byte per clock." /> - </BitField> - <BitField start="8" size="1" name="INV_QUALIFIER" description="Inversion qualifier"> - <Enum name="USE_NORMAL_QUALIFIER" start="0x0" description="Use normal qualifier." /> - <Enum name="USE_INVERTED_QUALIFI" start="0x1" description="Use inverted qualifier." /> - </BitField> - <BitField start="9" size="23" name="RESERVED" description="Reserved." /> - </Register> - <Register start="+0x0080+32" size="4" name="SLICE_MUX_CFG[8]" access="Read/Write" description="Slice multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="1" name="MATCH_MODE" description="Match mode. Selects whether the match filter is active or whether data is captured."> - <Enum name="DO_NOT_MATCH_DATA" start="0x0" description="Do not match data." /> - <Enum name="MATCH_DATA" start="0x1" description="Match data." /> - </BitField> - <BitField start="1" size="1" name="CLK_CAPTURE_MODE" description="Capture clock mode"> - <Enum name="USE_RISING_CLOCK_EDG" start="0x0" description="Use rising clock edge." /> - <Enum name="USE_FALLING_CLOCK_ED" start="0x1" description="Use falling clock edge." /> - </BitField> - <BitField start="2" size="1" name="CLKGEN_MODE" description="Clock generation mode. Selects the clock generated by the slice counter or by an external pin or other slice as shift clock."> - <Enum name="USE_CLOCK_INTERNALLY" start="0x0" description="Use clock internally generated by COUNTER." /> - <Enum name="USE_EXTERNAL_CLOCK_F" start="0x1" description="Use external clock from a pin or other slice." /> - </BitField> - <BitField start="3" size="1" name="INV_OUT_CLK" description="Invert output clock"> - <Enum name="NORMAL_CLOCK" start="0x0" description="Normal clock." /> - <Enum name="INVERTED_CLOCK" start="0x1" description="Inverted clock." /> - </BitField> - <BitField start="4" size="2" name="DATA_CAPTURE_MODE" description="Condition for input bit match interrupt"> - <Enum name="DETECT_RISING_EDGE" start="0x0" description="Detect rising edge." /> - <Enum name="DETECT_FALLING_EDGE" start="0x1" description="Detect falling edge." /> - <Enum name="DETECT_LOW_LEVEL" start="0x2" description="Detect LOW level." /> - <Enum name="DETECT_HIGH_LEVEL" start="0x3" description="Detect HIGH level." /> - </BitField> - <BitField start="6" size="2" name="PARALLEL_MODE" description="Parallel mode"> - <Enum name="SHIFT_1_BIT_PER_CLOC" start="0x0" description="Shift 1 bit per clock." /> - <Enum name="SHIFT_2_BITS_PER_CLO" start="0x1" description="Shift 2 bits per clock." /> - <Enum name="SHIFT_4_BITS_PER_CLO" start="0x2" description="Shift 4 bits per clock." /> - <Enum name="SHIFT_1_BYTE_PER_CLO" start="0x3" description="Shift 1 byte per clock." /> - </BitField> - <BitField start="8" size="1" name="INV_QUALIFIER" description="Inversion qualifier"> - <Enum name="USE_NORMAL_QUALIFIER" start="0x0" description="Use normal qualifier." /> - <Enum name="USE_INVERTED_QUALIFI" start="0x1" description="Use inverted qualifier." /> - </BitField> - <BitField start="9" size="23" name="RESERVED" description="Reserved." /> - </Register> - <Register start="+0x0080+36" size="4" name="SLICE_MUX_CFG[9]" access="Read/Write" description="Slice multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="1" name="MATCH_MODE" description="Match mode. Selects whether the match filter is active or whether data is captured."> - <Enum name="DO_NOT_MATCH_DATA" start="0x0" description="Do not match data." /> - <Enum name="MATCH_DATA" start="0x1" description="Match data." /> - </BitField> - <BitField start="1" size="1" name="CLK_CAPTURE_MODE" description="Capture clock mode"> - <Enum name="USE_RISING_CLOCK_EDG" start="0x0" description="Use rising clock edge." /> - <Enum name="USE_FALLING_CLOCK_ED" start="0x1" description="Use falling clock edge." /> - </BitField> - <BitField start="2" size="1" name="CLKGEN_MODE" description="Clock generation mode. Selects the clock generated by the slice counter or by an external pin or other slice as shift clock."> - <Enum name="USE_CLOCK_INTERNALLY" start="0x0" description="Use clock internally generated by COUNTER." /> - <Enum name="USE_EXTERNAL_CLOCK_F" start="0x1" description="Use external clock from a pin or other slice." /> - </BitField> - <BitField start="3" size="1" name="INV_OUT_CLK" description="Invert output clock"> - <Enum name="NORMAL_CLOCK" start="0x0" description="Normal clock." /> - <Enum name="INVERTED_CLOCK" start="0x1" description="Inverted clock." /> - </BitField> - <BitField start="4" size="2" name="DATA_CAPTURE_MODE" description="Condition for input bit match interrupt"> - <Enum name="DETECT_RISING_EDGE" start="0x0" description="Detect rising edge." /> - <Enum name="DETECT_FALLING_EDGE" start="0x1" description="Detect falling edge." /> - <Enum name="DETECT_LOW_LEVEL" start="0x2" description="Detect LOW level." /> - <Enum name="DETECT_HIGH_LEVEL" start="0x3" description="Detect HIGH level." /> - </BitField> - <BitField start="6" size="2" name="PARALLEL_MODE" description="Parallel mode"> - <Enum name="SHIFT_1_BIT_PER_CLOC" start="0x0" description="Shift 1 bit per clock." /> - <Enum name="SHIFT_2_BITS_PER_CLO" start="0x1" description="Shift 2 bits per clock." /> - <Enum name="SHIFT_4_BITS_PER_CLO" start="0x2" description="Shift 4 bits per clock." /> - <Enum name="SHIFT_1_BYTE_PER_CLO" start="0x3" description="Shift 1 byte per clock." /> - </BitField> - <BitField start="8" size="1" name="INV_QUALIFIER" description="Inversion qualifier"> - <Enum name="USE_NORMAL_QUALIFIER" start="0x0" description="Use normal qualifier." /> - <Enum name="USE_INVERTED_QUALIFI" start="0x1" description="Use inverted qualifier." /> - </BitField> - <BitField start="9" size="23" name="RESERVED" description="Reserved." /> - </Register> - <Register start="+0x0080+40" size="4" name="SLICE_MUX_CFG[10]" access="Read/Write" description="Slice multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="1" name="MATCH_MODE" description="Match mode. Selects whether the match filter is active or whether data is captured."> - <Enum name="DO_NOT_MATCH_DATA" start="0x0" description="Do not match data." /> - <Enum name="MATCH_DATA" start="0x1" description="Match data." /> - </BitField> - <BitField start="1" size="1" name="CLK_CAPTURE_MODE" description="Capture clock mode"> - <Enum name="USE_RISING_CLOCK_EDG" start="0x0" description="Use rising clock edge." /> - <Enum name="USE_FALLING_CLOCK_ED" start="0x1" description="Use falling clock edge." /> - </BitField> - <BitField start="2" size="1" name="CLKGEN_MODE" description="Clock generation mode. Selects the clock generated by the slice counter or by an external pin or other slice as shift clock."> - <Enum name="USE_CLOCK_INTERNALLY" start="0x0" description="Use clock internally generated by COUNTER." /> - <Enum name="USE_EXTERNAL_CLOCK_F" start="0x1" description="Use external clock from a pin or other slice." /> - </BitField> - <BitField start="3" size="1" name="INV_OUT_CLK" description="Invert output clock"> - <Enum name="NORMAL_CLOCK" start="0x0" description="Normal clock." /> - <Enum name="INVERTED_CLOCK" start="0x1" description="Inverted clock." /> - </BitField> - <BitField start="4" size="2" name="DATA_CAPTURE_MODE" description="Condition for input bit match interrupt"> - <Enum name="DETECT_RISING_EDGE" start="0x0" description="Detect rising edge." /> - <Enum name="DETECT_FALLING_EDGE" start="0x1" description="Detect falling edge." /> - <Enum name="DETECT_LOW_LEVEL" start="0x2" description="Detect LOW level." /> - <Enum name="DETECT_HIGH_LEVEL" start="0x3" description="Detect HIGH level." /> - </BitField> - <BitField start="6" size="2" name="PARALLEL_MODE" description="Parallel mode"> - <Enum name="SHIFT_1_BIT_PER_CLOC" start="0x0" description="Shift 1 bit per clock." /> - <Enum name="SHIFT_2_BITS_PER_CLO" start="0x1" description="Shift 2 bits per clock." /> - <Enum name="SHIFT_4_BITS_PER_CLO" start="0x2" description="Shift 4 bits per clock." /> - <Enum name="SHIFT_1_BYTE_PER_CLO" start="0x3" description="Shift 1 byte per clock." /> - </BitField> - <BitField start="8" size="1" name="INV_QUALIFIER" description="Inversion qualifier"> - <Enum name="USE_NORMAL_QUALIFIER" start="0x0" description="Use normal qualifier." /> - <Enum name="USE_INVERTED_QUALIFI" start="0x1" description="Use inverted qualifier." /> - </BitField> - <BitField start="9" size="23" name="RESERVED" description="Reserved." /> - </Register> - <Register start="+0x0080+44" size="4" name="SLICE_MUX_CFG[11]" access="Read/Write" description="Slice multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="1" name="MATCH_MODE" description="Match mode. Selects whether the match filter is active or whether data is captured."> - <Enum name="DO_NOT_MATCH_DATA" start="0x0" description="Do not match data." /> - <Enum name="MATCH_DATA" start="0x1" description="Match data." /> - </BitField> - <BitField start="1" size="1" name="CLK_CAPTURE_MODE" description="Capture clock mode"> - <Enum name="USE_RISING_CLOCK_EDG" start="0x0" description="Use rising clock edge." /> - <Enum name="USE_FALLING_CLOCK_ED" start="0x1" description="Use falling clock edge." /> - </BitField> - <BitField start="2" size="1" name="CLKGEN_MODE" description="Clock generation mode. Selects the clock generated by the slice counter or by an external pin or other slice as shift clock."> - <Enum name="USE_CLOCK_INTERNALLY" start="0x0" description="Use clock internally generated by COUNTER." /> - <Enum name="USE_EXTERNAL_CLOCK_F" start="0x1" description="Use external clock from a pin or other slice." /> - </BitField> - <BitField start="3" size="1" name="INV_OUT_CLK" description="Invert output clock"> - <Enum name="NORMAL_CLOCK" start="0x0" description="Normal clock." /> - <Enum name="INVERTED_CLOCK" start="0x1" description="Inverted clock." /> - </BitField> - <BitField start="4" size="2" name="DATA_CAPTURE_MODE" description="Condition for input bit match interrupt"> - <Enum name="DETECT_RISING_EDGE" start="0x0" description="Detect rising edge." /> - <Enum name="DETECT_FALLING_EDGE" start="0x1" description="Detect falling edge." /> - <Enum name="DETECT_LOW_LEVEL" start="0x2" description="Detect LOW level." /> - <Enum name="DETECT_HIGH_LEVEL" start="0x3" description="Detect HIGH level." /> - </BitField> - <BitField start="6" size="2" name="PARALLEL_MODE" description="Parallel mode"> - <Enum name="SHIFT_1_BIT_PER_CLOC" start="0x0" description="Shift 1 bit per clock." /> - <Enum name="SHIFT_2_BITS_PER_CLO" start="0x1" description="Shift 2 bits per clock." /> - <Enum name="SHIFT_4_BITS_PER_CLO" start="0x2" description="Shift 4 bits per clock." /> - <Enum name="SHIFT_1_BYTE_PER_CLO" start="0x3" description="Shift 1 byte per clock." /> - </BitField> - <BitField start="8" size="1" name="INV_QUALIFIER" description="Inversion qualifier"> - <Enum name="USE_NORMAL_QUALIFIER" start="0x0" description="Use normal qualifier." /> - <Enum name="USE_INVERTED_QUALIFI" start="0x1" description="Use inverted qualifier." /> - </BitField> - <BitField start="9" size="23" name="RESERVED" description="Reserved." /> - </Register> - <Register start="+0x0080+48" size="4" name="SLICE_MUX_CFG[12]" access="Read/Write" description="Slice multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="1" name="MATCH_MODE" description="Match mode. Selects whether the match filter is active or whether data is captured."> - <Enum name="DO_NOT_MATCH_DATA" start="0x0" description="Do not match data." /> - <Enum name="MATCH_DATA" start="0x1" description="Match data." /> - </BitField> - <BitField start="1" size="1" name="CLK_CAPTURE_MODE" description="Capture clock mode"> - <Enum name="USE_RISING_CLOCK_EDG" start="0x0" description="Use rising clock edge." /> - <Enum name="USE_FALLING_CLOCK_ED" start="0x1" description="Use falling clock edge." /> - </BitField> - <BitField start="2" size="1" name="CLKGEN_MODE" description="Clock generation mode. Selects the clock generated by the slice counter or by an external pin or other slice as shift clock."> - <Enum name="USE_CLOCK_INTERNALLY" start="0x0" description="Use clock internally generated by COUNTER." /> - <Enum name="USE_EXTERNAL_CLOCK_F" start="0x1" description="Use external clock from a pin or other slice." /> - </BitField> - <BitField start="3" size="1" name="INV_OUT_CLK" description="Invert output clock"> - <Enum name="NORMAL_CLOCK" start="0x0" description="Normal clock." /> - <Enum name="INVERTED_CLOCK" start="0x1" description="Inverted clock." /> - </BitField> - <BitField start="4" size="2" name="DATA_CAPTURE_MODE" description="Condition for input bit match interrupt"> - <Enum name="DETECT_RISING_EDGE" start="0x0" description="Detect rising edge." /> - <Enum name="DETECT_FALLING_EDGE" start="0x1" description="Detect falling edge." /> - <Enum name="DETECT_LOW_LEVEL" start="0x2" description="Detect LOW level." /> - <Enum name="DETECT_HIGH_LEVEL" start="0x3" description="Detect HIGH level." /> - </BitField> - <BitField start="6" size="2" name="PARALLEL_MODE" description="Parallel mode"> - <Enum name="SHIFT_1_BIT_PER_CLOC" start="0x0" description="Shift 1 bit per clock." /> - <Enum name="SHIFT_2_BITS_PER_CLO" start="0x1" description="Shift 2 bits per clock." /> - <Enum name="SHIFT_4_BITS_PER_CLO" start="0x2" description="Shift 4 bits per clock." /> - <Enum name="SHIFT_1_BYTE_PER_CLO" start="0x3" description="Shift 1 byte per clock." /> - </BitField> - <BitField start="8" size="1" name="INV_QUALIFIER" description="Inversion qualifier"> - <Enum name="USE_NORMAL_QUALIFIER" start="0x0" description="Use normal qualifier." /> - <Enum name="USE_INVERTED_QUALIFI" start="0x1" description="Use inverted qualifier." /> - </BitField> - <BitField start="9" size="23" name="RESERVED" description="Reserved." /> - </Register> - <Register start="+0x0080+52" size="4" name="SLICE_MUX_CFG[13]" access="Read/Write" description="Slice multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="1" name="MATCH_MODE" description="Match mode. Selects whether the match filter is active or whether data is captured."> - <Enum name="DO_NOT_MATCH_DATA" start="0x0" description="Do not match data." /> - <Enum name="MATCH_DATA" start="0x1" description="Match data." /> - </BitField> - <BitField start="1" size="1" name="CLK_CAPTURE_MODE" description="Capture clock mode"> - <Enum name="USE_RISING_CLOCK_EDG" start="0x0" description="Use rising clock edge." /> - <Enum name="USE_FALLING_CLOCK_ED" start="0x1" description="Use falling clock edge." /> - </BitField> - <BitField start="2" size="1" name="CLKGEN_MODE" description="Clock generation mode. Selects the clock generated by the slice counter or by an external pin or other slice as shift clock."> - <Enum name="USE_CLOCK_INTERNALLY" start="0x0" description="Use clock internally generated by COUNTER." /> - <Enum name="USE_EXTERNAL_CLOCK_F" start="0x1" description="Use external clock from a pin or other slice." /> - </BitField> - <BitField start="3" size="1" name="INV_OUT_CLK" description="Invert output clock"> - <Enum name="NORMAL_CLOCK" start="0x0" description="Normal clock." /> - <Enum name="INVERTED_CLOCK" start="0x1" description="Inverted clock." /> - </BitField> - <BitField start="4" size="2" name="DATA_CAPTURE_MODE" description="Condition for input bit match interrupt"> - <Enum name="DETECT_RISING_EDGE" start="0x0" description="Detect rising edge." /> - <Enum name="DETECT_FALLING_EDGE" start="0x1" description="Detect falling edge." /> - <Enum name="DETECT_LOW_LEVEL" start="0x2" description="Detect LOW level." /> - <Enum name="DETECT_HIGH_LEVEL" start="0x3" description="Detect HIGH level." /> - </BitField> - <BitField start="6" size="2" name="PARALLEL_MODE" description="Parallel mode"> - <Enum name="SHIFT_1_BIT_PER_CLOC" start="0x0" description="Shift 1 bit per clock." /> - <Enum name="SHIFT_2_BITS_PER_CLO" start="0x1" description="Shift 2 bits per clock." /> - <Enum name="SHIFT_4_BITS_PER_CLO" start="0x2" description="Shift 4 bits per clock." /> - <Enum name="SHIFT_1_BYTE_PER_CLO" start="0x3" description="Shift 1 byte per clock." /> - </BitField> - <BitField start="8" size="1" name="INV_QUALIFIER" description="Inversion qualifier"> - <Enum name="USE_NORMAL_QUALIFIER" start="0x0" description="Use normal qualifier." /> - <Enum name="USE_INVERTED_QUALIFI" start="0x1" description="Use inverted qualifier." /> - </BitField> - <BitField start="9" size="23" name="RESERVED" description="Reserved." /> - </Register> - <Register start="+0x0080+56" size="4" name="SLICE_MUX_CFG[14]" access="Read/Write" description="Slice multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="1" name="MATCH_MODE" description="Match mode. Selects whether the match filter is active or whether data is captured."> - <Enum name="DO_NOT_MATCH_DATA" start="0x0" description="Do not match data." /> - <Enum name="MATCH_DATA" start="0x1" description="Match data." /> - </BitField> - <BitField start="1" size="1" name="CLK_CAPTURE_MODE" description="Capture clock mode"> - <Enum name="USE_RISING_CLOCK_EDG" start="0x0" description="Use rising clock edge." /> - <Enum name="USE_FALLING_CLOCK_ED" start="0x1" description="Use falling clock edge." /> - </BitField> - <BitField start="2" size="1" name="CLKGEN_MODE" description="Clock generation mode. Selects the clock generated by the slice counter or by an external pin or other slice as shift clock."> - <Enum name="USE_CLOCK_INTERNALLY" start="0x0" description="Use clock internally generated by COUNTER." /> - <Enum name="USE_EXTERNAL_CLOCK_F" start="0x1" description="Use external clock from a pin or other slice." /> - </BitField> - <BitField start="3" size="1" name="INV_OUT_CLK" description="Invert output clock"> - <Enum name="NORMAL_CLOCK" start="0x0" description="Normal clock." /> - <Enum name="INVERTED_CLOCK" start="0x1" description="Inverted clock." /> - </BitField> - <BitField start="4" size="2" name="DATA_CAPTURE_MODE" description="Condition for input bit match interrupt"> - <Enum name="DETECT_RISING_EDGE" start="0x0" description="Detect rising edge." /> - <Enum name="DETECT_FALLING_EDGE" start="0x1" description="Detect falling edge." /> - <Enum name="DETECT_LOW_LEVEL" start="0x2" description="Detect LOW level." /> - <Enum name="DETECT_HIGH_LEVEL" start="0x3" description="Detect HIGH level." /> - </BitField> - <BitField start="6" size="2" name="PARALLEL_MODE" description="Parallel mode"> - <Enum name="SHIFT_1_BIT_PER_CLOC" start="0x0" description="Shift 1 bit per clock." /> - <Enum name="SHIFT_2_BITS_PER_CLO" start="0x1" description="Shift 2 bits per clock." /> - <Enum name="SHIFT_4_BITS_PER_CLO" start="0x2" description="Shift 4 bits per clock." /> - <Enum name="SHIFT_1_BYTE_PER_CLO" start="0x3" description="Shift 1 byte per clock." /> - </BitField> - <BitField start="8" size="1" name="INV_QUALIFIER" description="Inversion qualifier"> - <Enum name="USE_NORMAL_QUALIFIER" start="0x0" description="Use normal qualifier." /> - <Enum name="USE_INVERTED_QUALIFI" start="0x1" description="Use inverted qualifier." /> - </BitField> - <BitField start="9" size="23" name="RESERVED" description="Reserved." /> - </Register> - <Register start="+0x0080+60" size="4" name="SLICE_MUX_CFG[15]" access="Read/Write" description="Slice multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="1" name="MATCH_MODE" description="Match mode. Selects whether the match filter is active or whether data is captured."> - <Enum name="DO_NOT_MATCH_DATA" start="0x0" description="Do not match data." /> - <Enum name="MATCH_DATA" start="0x1" description="Match data." /> - </BitField> - <BitField start="1" size="1" name="CLK_CAPTURE_MODE" description="Capture clock mode"> - <Enum name="USE_RISING_CLOCK_EDG" start="0x0" description="Use rising clock edge." /> - <Enum name="USE_FALLING_CLOCK_ED" start="0x1" description="Use falling clock edge." /> - </BitField> - <BitField start="2" size="1" name="CLKGEN_MODE" description="Clock generation mode. Selects the clock generated by the slice counter or by an external pin or other slice as shift clock."> - <Enum name="USE_CLOCK_INTERNALLY" start="0x0" description="Use clock internally generated by COUNTER." /> - <Enum name="USE_EXTERNAL_CLOCK_F" start="0x1" description="Use external clock from a pin or other slice." /> - </BitField> - <BitField start="3" size="1" name="INV_OUT_CLK" description="Invert output clock"> - <Enum name="NORMAL_CLOCK" start="0x0" description="Normal clock." /> - <Enum name="INVERTED_CLOCK" start="0x1" description="Inverted clock." /> - </BitField> - <BitField start="4" size="2" name="DATA_CAPTURE_MODE" description="Condition for input bit match interrupt"> - <Enum name="DETECT_RISING_EDGE" start="0x0" description="Detect rising edge." /> - <Enum name="DETECT_FALLING_EDGE" start="0x1" description="Detect falling edge." /> - <Enum name="DETECT_LOW_LEVEL" start="0x2" description="Detect LOW level." /> - <Enum name="DETECT_HIGH_LEVEL" start="0x3" description="Detect HIGH level." /> - </BitField> - <BitField start="6" size="2" name="PARALLEL_MODE" description="Parallel mode"> - <Enum name="SHIFT_1_BIT_PER_CLOC" start="0x0" description="Shift 1 bit per clock." /> - <Enum name="SHIFT_2_BITS_PER_CLO" start="0x1" description="Shift 2 bits per clock." /> - <Enum name="SHIFT_4_BITS_PER_CLO" start="0x2" description="Shift 4 bits per clock." /> - <Enum name="SHIFT_1_BYTE_PER_CLO" start="0x3" description="Shift 1 byte per clock." /> - </BitField> - <BitField start="8" size="1" name="INV_QUALIFIER" description="Inversion qualifier"> - <Enum name="USE_NORMAL_QUALIFIER" start="0x0" description="Use normal qualifier." /> - <Enum name="USE_INVERTED_QUALIFI" start="0x1" description="Use inverted qualifier." /> - </BitField> - <BitField start="9" size="23" name="RESERVED" description="Reserved." /> - </Register> - <Register start="+0x00C0+0" size="4" name="REG[0]" access="Read/Write" description="Slice data registers. Each time COUNT0 reaches 0x0 the register shifts loading bit 31 with data captured from DIN(n). DOUT(n) is set to REG(0)" reset_value="0" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="32" name="REG" description="At each active shift clock the register shifts right; loading REG(31) with data captured from DIN(n) and DOUT(n) is set to REG(0)." /> - </Register> - <Register start="+0x00C0+4" size="4" name="REG[1]" access="Read/Write" description="Slice data registers. Each time COUNT0 reaches 0x0 the register shifts loading bit 31 with data captured from DIN(n). DOUT(n) is set to REG(0)" reset_value="0" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="32" name="REG" description="At each active shift clock the register shifts right; loading REG(31) with data captured from DIN(n) and DOUT(n) is set to REG(0)." /> - </Register> - <Register start="+0x00C0+8" size="4" name="REG[2]" access="Read/Write" description="Slice data registers. Each time COUNT0 reaches 0x0 the register shifts loading bit 31 with data captured from DIN(n). DOUT(n) is set to REG(0)" reset_value="0" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="32" name="REG" description="At each active shift clock the register shifts right; loading REG(31) with data captured from DIN(n) and DOUT(n) is set to REG(0)." /> - </Register> - <Register start="+0x00C0+12" size="4" name="REG[3]" access="Read/Write" description="Slice data registers. Each time COUNT0 reaches 0x0 the register shifts loading bit 31 with data captured from DIN(n). DOUT(n) is set to REG(0)" reset_value="0" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="32" name="REG" description="At each active shift clock the register shifts right; loading REG(31) with data captured from DIN(n) and DOUT(n) is set to REG(0)." /> - </Register> - <Register start="+0x00C0+16" size="4" name="REG[4]" access="Read/Write" description="Slice data registers. Each time COUNT0 reaches 0x0 the register shifts loading bit 31 with data captured from DIN(n). DOUT(n) is set to REG(0)" reset_value="0" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="32" name="REG" description="At each active shift clock the register shifts right; loading REG(31) with data captured from DIN(n) and DOUT(n) is set to REG(0)." /> - </Register> - <Register start="+0x00C0+20" size="4" name="REG[5]" access="Read/Write" description="Slice data registers. Each time COUNT0 reaches 0x0 the register shifts loading bit 31 with data captured from DIN(n). DOUT(n) is set to REG(0)" reset_value="0" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="32" name="REG" description="At each active shift clock the register shifts right; loading REG(31) with data captured from DIN(n) and DOUT(n) is set to REG(0)." /> - </Register> - <Register start="+0x00C0+24" size="4" name="REG[6]" access="Read/Write" description="Slice data registers. Each time COUNT0 reaches 0x0 the register shifts loading bit 31 with data captured from DIN(n). DOUT(n) is set to REG(0)" reset_value="0" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="32" name="REG" description="At each active shift clock the register shifts right; loading REG(31) with data captured from DIN(n) and DOUT(n) is set to REG(0)." /> - </Register> - <Register start="+0x00C0+28" size="4" name="REG[7]" access="Read/Write" description="Slice data registers. Each time COUNT0 reaches 0x0 the register shifts loading bit 31 with data captured from DIN(n). DOUT(n) is set to REG(0)" reset_value="0" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="32" name="REG" description="At each active shift clock the register shifts right; loading REG(31) with data captured from DIN(n) and DOUT(n) is set to REG(0)." /> - </Register> - <Register start="+0x00C0+32" size="4" name="REG[8]" access="Read/Write" description="Slice data registers. Each time COUNT0 reaches 0x0 the register shifts loading bit 31 with data captured from DIN(n). DOUT(n) is set to REG(0)" reset_value="0" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="32" name="REG" description="At each active shift clock the register shifts right; loading REG(31) with data captured from DIN(n) and DOUT(n) is set to REG(0)." /> - </Register> - <Register start="+0x00C0+36" size="4" name="REG[9]" access="Read/Write" description="Slice data registers. Each time COUNT0 reaches 0x0 the register shifts loading bit 31 with data captured from DIN(n). DOUT(n) is set to REG(0)" reset_value="0" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="32" name="REG" description="At each active shift clock the register shifts right; loading REG(31) with data captured from DIN(n) and DOUT(n) is set to REG(0)." /> - </Register> - <Register start="+0x00C0+40" size="4" name="REG[10]" access="Read/Write" description="Slice data registers. Each time COUNT0 reaches 0x0 the register shifts loading bit 31 with data captured from DIN(n). DOUT(n) is set to REG(0)" reset_value="0" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="32" name="REG" description="At each active shift clock the register shifts right; loading REG(31) with data captured from DIN(n) and DOUT(n) is set to REG(0)." /> - </Register> - <Register start="+0x00C0+44" size="4" name="REG[11]" access="Read/Write" description="Slice data registers. Each time COUNT0 reaches 0x0 the register shifts loading bit 31 with data captured from DIN(n). DOUT(n) is set to REG(0)" reset_value="0" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="32" name="REG" description="At each active shift clock the register shifts right; loading REG(31) with data captured from DIN(n) and DOUT(n) is set to REG(0)." /> - </Register> - <Register start="+0x00C0+48" size="4" name="REG[12]" access="Read/Write" description="Slice data registers. Each time COUNT0 reaches 0x0 the register shifts loading bit 31 with data captured from DIN(n). DOUT(n) is set to REG(0)" reset_value="0" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="32" name="REG" description="At each active shift clock the register shifts right; loading REG(31) with data captured from DIN(n) and DOUT(n) is set to REG(0)." /> - </Register> - <Register start="+0x00C0+52" size="4" name="REG[13]" access="Read/Write" description="Slice data registers. Each time COUNT0 reaches 0x0 the register shifts loading bit 31 with data captured from DIN(n). DOUT(n) is set to REG(0)" reset_value="0" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="32" name="REG" description="At each active shift clock the register shifts right; loading REG(31) with data captured from DIN(n) and DOUT(n) is set to REG(0)." /> - </Register> - <Register start="+0x00C0+56" size="4" name="REG[14]" access="Read/Write" description="Slice data registers. Each time COUNT0 reaches 0x0 the register shifts loading bit 31 with data captured from DIN(n). DOUT(n) is set to REG(0)" reset_value="0" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="32" name="REG" description="At each active shift clock the register shifts right; loading REG(31) with data captured from DIN(n) and DOUT(n) is set to REG(0)." /> - </Register> - <Register start="+0x00C0+60" size="4" name="REG[15]" access="Read/Write" description="Slice data registers. Each time COUNT0 reaches 0x0 the register shifts loading bit 31 with data captured from DIN(n). DOUT(n) is set to REG(0)" reset_value="0" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="32" name="REG" description="At each active shift clock the register shifts right; loading REG(31) with data captured from DIN(n) and DOUT(n) is set to REG(0)." /> - </Register> - <Register start="+0x0100+0" size="4" name="REG_SS[0]" access="Read/Write" description="Slice data shadow registers. Each time POS reaches 0x0 the contents of REG_SS is exchanged with the content of REG" reset_value="0" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="32" name="REG_SS" description="Each time POS reaches 0x0 the contents of REG_SS is exchanged with the content of REG." /> - </Register> - <Register start="+0x0100+4" size="4" name="REG_SS[1]" access="Read/Write" description="Slice data shadow registers. Each time POS reaches 0x0 the contents of REG_SS is exchanged with the content of REG" reset_value="0" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="32" name="REG_SS" description="Each time POS reaches 0x0 the contents of REG_SS is exchanged with the content of REG." /> - </Register> - <Register start="+0x0100+8" size="4" name="REG_SS[2]" access="Read/Write" description="Slice data shadow registers. Each time POS reaches 0x0 the contents of REG_SS is exchanged with the content of REG" reset_value="0" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="32" name="REG_SS" description="Each time POS reaches 0x0 the contents of REG_SS is exchanged with the content of REG." /> - </Register> - <Register start="+0x0100+12" size="4" name="REG_SS[3]" access="Read/Write" description="Slice data shadow registers. Each time POS reaches 0x0 the contents of REG_SS is exchanged with the content of REG" reset_value="0" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="32" name="REG_SS" description="Each time POS reaches 0x0 the contents of REG_SS is exchanged with the content of REG." /> - </Register> - <Register start="+0x0100+16" size="4" name="REG_SS[4]" access="Read/Write" description="Slice data shadow registers. Each time POS reaches 0x0 the contents of REG_SS is exchanged with the content of REG" reset_value="0" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="32" name="REG_SS" description="Each time POS reaches 0x0 the contents of REG_SS is exchanged with the content of REG." /> - </Register> - <Register start="+0x0100+20" size="4" name="REG_SS[5]" access="Read/Write" description="Slice data shadow registers. Each time POS reaches 0x0 the contents of REG_SS is exchanged with the content of REG" reset_value="0" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="32" name="REG_SS" description="Each time POS reaches 0x0 the contents of REG_SS is exchanged with the content of REG." /> - </Register> - <Register start="+0x0100+24" size="4" name="REG_SS[6]" access="Read/Write" description="Slice data shadow registers. Each time POS reaches 0x0 the contents of REG_SS is exchanged with the content of REG" reset_value="0" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="32" name="REG_SS" description="Each time POS reaches 0x0 the contents of REG_SS is exchanged with the content of REG." /> - </Register> - <Register start="+0x0100+28" size="4" name="REG_SS[7]" access="Read/Write" description="Slice data shadow registers. Each time POS reaches 0x0 the contents of REG_SS is exchanged with the content of REG" reset_value="0" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="32" name="REG_SS" description="Each time POS reaches 0x0 the contents of REG_SS is exchanged with the content of REG." /> - </Register> - <Register start="+0x0100+32" size="4" name="REG_SS[8]" access="Read/Write" description="Slice data shadow registers. Each time POS reaches 0x0 the contents of REG_SS is exchanged with the content of REG" reset_value="0" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="32" name="REG_SS" description="Each time POS reaches 0x0 the contents of REG_SS is exchanged with the content of REG." /> - </Register> - <Register start="+0x0100+36" size="4" name="REG_SS[9]" access="Read/Write" description="Slice data shadow registers. Each time POS reaches 0x0 the contents of REG_SS is exchanged with the content of REG" reset_value="0" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="32" name="REG_SS" description="Each time POS reaches 0x0 the contents of REG_SS is exchanged with the content of REG." /> - </Register> - <Register start="+0x0100+40" size="4" name="REG_SS[10]" access="Read/Write" description="Slice data shadow registers. Each time POS reaches 0x0 the contents of REG_SS is exchanged with the content of REG" reset_value="0" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="32" name="REG_SS" description="Each time POS reaches 0x0 the contents of REG_SS is exchanged with the content of REG." /> - </Register> - <Register start="+0x0100+44" size="4" name="REG_SS[11]" access="Read/Write" description="Slice data shadow registers. Each time POS reaches 0x0 the contents of REG_SS is exchanged with the content of REG" reset_value="0" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="32" name="REG_SS" description="Each time POS reaches 0x0 the contents of REG_SS is exchanged with the content of REG." /> - </Register> - <Register start="+0x0100+48" size="4" name="REG_SS[12]" access="Read/Write" description="Slice data shadow registers. Each time POS reaches 0x0 the contents of REG_SS is exchanged with the content of REG" reset_value="0" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="32" name="REG_SS" description="Each time POS reaches 0x0 the contents of REG_SS is exchanged with the content of REG." /> - </Register> - <Register start="+0x0100+52" size="4" name="REG_SS[13]" access="Read/Write" description="Slice data shadow registers. Each time POS reaches 0x0 the contents of REG_SS is exchanged with the content of REG" reset_value="0" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="32" name="REG_SS" description="Each time POS reaches 0x0 the contents of REG_SS is exchanged with the content of REG." /> - </Register> - <Register start="+0x0100+56" size="4" name="REG_SS[14]" access="Read/Write" description="Slice data shadow registers. Each time POS reaches 0x0 the contents of REG_SS is exchanged with the content of REG" reset_value="0" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="32" name="REG_SS" description="Each time POS reaches 0x0 the contents of REG_SS is exchanged with the content of REG." /> - </Register> - <Register start="+0x0100+60" size="4" name="REG_SS[15]" access="Read/Write" description="Slice data shadow registers. Each time POS reaches 0x0 the contents of REG_SS is exchanged with the content of REG" reset_value="0" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="32" name="REG_SS" description="Each time POS reaches 0x0 the contents of REG_SS is exchanged with the content of REG." /> - </Register> - <Register start="+0x0140+0" size="4" name="PRESET[0]" access="Read/Write" description="Reload value of COUNT0, loaded when COUNT0 reaches 0x0" reset_value="0" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="12" name="PRESET" description="Counter reload value; loaded when COUNT reaches 0x0." /> - <BitField start="12" size="20" name="RESERVED" description="Reserved." /> - </Register> - <Register start="+0x0140+4" size="4" name="PRESET[1]" access="Read/Write" description="Reload value of COUNT0, loaded when COUNT0 reaches 0x0" reset_value="0" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="12" name="PRESET" description="Counter reload value; loaded when COUNT reaches 0x0." /> - <BitField start="12" size="20" name="RESERVED" description="Reserved." /> - </Register> - <Register start="+0x0140+8" size="4" name="PRESET[2]" access="Read/Write" description="Reload value of COUNT0, loaded when COUNT0 reaches 0x0" reset_value="0" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="12" name="PRESET" description="Counter reload value; loaded when COUNT reaches 0x0." /> - <BitField start="12" size="20" name="RESERVED" description="Reserved." /> - </Register> - <Register start="+0x0140+12" size="4" name="PRESET[3]" access="Read/Write" description="Reload value of COUNT0, loaded when COUNT0 reaches 0x0" reset_value="0" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="12" name="PRESET" description="Counter reload value; loaded when COUNT reaches 0x0." /> - <BitField start="12" size="20" name="RESERVED" description="Reserved." /> - </Register> - <Register start="+0x0140+16" size="4" name="PRESET[4]" access="Read/Write" description="Reload value of COUNT0, loaded when COUNT0 reaches 0x0" reset_value="0" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="12" name="PRESET" description="Counter reload value; loaded when COUNT reaches 0x0." /> - <BitField start="12" size="20" name="RESERVED" description="Reserved." /> - </Register> - <Register start="+0x0140+20" size="4" name="PRESET[5]" access="Read/Write" description="Reload value of COUNT0, loaded when COUNT0 reaches 0x0" reset_value="0" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="12" name="PRESET" description="Counter reload value; loaded when COUNT reaches 0x0." /> - <BitField start="12" size="20" name="RESERVED" description="Reserved." /> - </Register> - <Register start="+0x0140+24" size="4" name="PRESET[6]" access="Read/Write" description="Reload value of COUNT0, loaded when COUNT0 reaches 0x0" reset_value="0" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="12" name="PRESET" description="Counter reload value; loaded when COUNT reaches 0x0." /> - <BitField start="12" size="20" name="RESERVED" description="Reserved." /> - </Register> - <Register start="+0x0140+28" size="4" name="PRESET[7]" access="Read/Write" description="Reload value of COUNT0, loaded when COUNT0 reaches 0x0" reset_value="0" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="12" name="PRESET" description="Counter reload value; loaded when COUNT reaches 0x0." /> - <BitField start="12" size="20" name="RESERVED" description="Reserved." /> - </Register> - <Register start="+0x0140+32" size="4" name="PRESET[8]" access="Read/Write" description="Reload value of COUNT0, loaded when COUNT0 reaches 0x0" reset_value="0" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="12" name="PRESET" description="Counter reload value; loaded when COUNT reaches 0x0." /> - <BitField start="12" size="20" name="RESERVED" description="Reserved." /> - </Register> - <Register start="+0x0140+36" size="4" name="PRESET[9]" access="Read/Write" description="Reload value of COUNT0, loaded when COUNT0 reaches 0x0" reset_value="0" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="12" name="PRESET" description="Counter reload value; loaded when COUNT reaches 0x0." /> - <BitField start="12" size="20" name="RESERVED" description="Reserved." /> - </Register> - <Register start="+0x0140+40" size="4" name="PRESET[10]" access="Read/Write" description="Reload value of COUNT0, loaded when COUNT0 reaches 0x0" reset_value="0" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="12" name="PRESET" description="Counter reload value; loaded when COUNT reaches 0x0." /> - <BitField start="12" size="20" name="RESERVED" description="Reserved." /> - </Register> - <Register start="+0x0140+44" size="4" name="PRESET[11]" access="Read/Write" description="Reload value of COUNT0, loaded when COUNT0 reaches 0x0" reset_value="0" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="12" name="PRESET" description="Counter reload value; loaded when COUNT reaches 0x0." /> - <BitField start="12" size="20" name="RESERVED" description="Reserved." /> - </Register> - <Register start="+0x0140+48" size="4" name="PRESET[12]" access="Read/Write" description="Reload value of COUNT0, loaded when COUNT0 reaches 0x0" reset_value="0" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="12" name="PRESET" description="Counter reload value; loaded when COUNT reaches 0x0." /> - <BitField start="12" size="20" name="RESERVED" description="Reserved." /> - </Register> - <Register start="+0x0140+52" size="4" name="PRESET[13]" access="Read/Write" description="Reload value of COUNT0, loaded when COUNT0 reaches 0x0" reset_value="0" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="12" name="PRESET" description="Counter reload value; loaded when COUNT reaches 0x0." /> - <BitField start="12" size="20" name="RESERVED" description="Reserved." /> - </Register> - <Register start="+0x0140+56" size="4" name="PRESET[14]" access="Read/Write" description="Reload value of COUNT0, loaded when COUNT0 reaches 0x0" reset_value="0" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="12" name="PRESET" description="Counter reload value; loaded when COUNT reaches 0x0." /> - <BitField start="12" size="20" name="RESERVED" description="Reserved." /> - </Register> - <Register start="+0x0140+60" size="4" name="PRESET[15]" access="Read/Write" description="Reload value of COUNT0, loaded when COUNT0 reaches 0x0" reset_value="0" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="12" name="PRESET" description="Counter reload value; loaded when COUNT reaches 0x0." /> - <BitField start="12" size="20" name="RESERVED" description="Reserved." /> - </Register> - <Register start="+0x0180+0" size="4" name="COUNT[0]" access="Read/Write" description="Down counter, counts down each clock cycle." reset_value="0" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="12" name="COUNT" description="Down counter, counts down each shift clock cycle. Next count after 0x0 is PRESET." /> - <BitField start="12" size="20" name="RESERVED" description="Reserved." /> - </Register> - <Register start="+0x0180+4" size="4" name="COUNT[1]" access="Read/Write" description="Down counter, counts down each clock cycle." reset_value="0" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="12" name="COUNT" description="Down counter, counts down each shift clock cycle. Next count after 0x0 is PRESET." /> - <BitField start="12" size="20" name="RESERVED" description="Reserved." /> - </Register> - <Register start="+0x0180+8" size="4" name="COUNT[2]" access="Read/Write" description="Down counter, counts down each clock cycle." reset_value="0" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="12" name="COUNT" description="Down counter, counts down each shift clock cycle. Next count after 0x0 is PRESET." /> - <BitField start="12" size="20" name="RESERVED" description="Reserved." /> - </Register> - <Register start="+0x0180+12" size="4" name="COUNT[3]" access="Read/Write" description="Down counter, counts down each clock cycle." reset_value="0" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="12" name="COUNT" description="Down counter, counts down each shift clock cycle. Next count after 0x0 is PRESET." /> - <BitField start="12" size="20" name="RESERVED" description="Reserved." /> - </Register> - <Register start="+0x0180+16" size="4" name="COUNT[4]" access="Read/Write" description="Down counter, counts down each clock cycle." reset_value="0" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="12" name="COUNT" description="Down counter, counts down each shift clock cycle. Next count after 0x0 is PRESET." /> - <BitField start="12" size="20" name="RESERVED" description="Reserved." /> - </Register> - <Register start="+0x0180+20" size="4" name="COUNT[5]" access="Read/Write" description="Down counter, counts down each clock cycle." reset_value="0" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="12" name="COUNT" description="Down counter, counts down each shift clock cycle. Next count after 0x0 is PRESET." /> - <BitField start="12" size="20" name="RESERVED" description="Reserved." /> - </Register> - <Register start="+0x0180+24" size="4" name="COUNT[6]" access="Read/Write" description="Down counter, counts down each clock cycle." reset_value="0" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="12" name="COUNT" description="Down counter, counts down each shift clock cycle. Next count after 0x0 is PRESET." /> - <BitField start="12" size="20" name="RESERVED" description="Reserved." /> - </Register> - <Register start="+0x0180+28" size="4" name="COUNT[7]" access="Read/Write" description="Down counter, counts down each clock cycle." reset_value="0" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="12" name="COUNT" description="Down counter, counts down each shift clock cycle. Next count after 0x0 is PRESET." /> - <BitField start="12" size="20" name="RESERVED" description="Reserved." /> - </Register> - <Register start="+0x0180+32" size="4" name="COUNT[8]" access="Read/Write" description="Down counter, counts down each clock cycle." reset_value="0" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="12" name="COUNT" description="Down counter, counts down each shift clock cycle. Next count after 0x0 is PRESET." /> - <BitField start="12" size="20" name="RESERVED" description="Reserved." /> - </Register> - <Register start="+0x0180+36" size="4" name="COUNT[9]" access="Read/Write" description="Down counter, counts down each clock cycle." reset_value="0" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="12" name="COUNT" description="Down counter, counts down each shift clock cycle. Next count after 0x0 is PRESET." /> - <BitField start="12" size="20" name="RESERVED" description="Reserved." /> - </Register> - <Register start="+0x0180+40" size="4" name="COUNT[10]" access="Read/Write" description="Down counter, counts down each clock cycle." reset_value="0" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="12" name="COUNT" description="Down counter, counts down each shift clock cycle. Next count after 0x0 is PRESET." /> - <BitField start="12" size="20" name="RESERVED" description="Reserved." /> - </Register> - <Register start="+0x0180+44" size="4" name="COUNT[11]" access="Read/Write" description="Down counter, counts down each clock cycle." reset_value="0" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="12" name="COUNT" description="Down counter, counts down each shift clock cycle. Next count after 0x0 is PRESET." /> - <BitField start="12" size="20" name="RESERVED" description="Reserved." /> - </Register> - <Register start="+0x0180+48" size="4" name="COUNT[12]" access="Read/Write" description="Down counter, counts down each clock cycle." reset_value="0" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="12" name="COUNT" description="Down counter, counts down each shift clock cycle. Next count after 0x0 is PRESET." /> - <BitField start="12" size="20" name="RESERVED" description="Reserved." /> - </Register> - <Register start="+0x0180+52" size="4" name="COUNT[13]" access="Read/Write" description="Down counter, counts down each clock cycle." reset_value="0" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="12" name="COUNT" description="Down counter, counts down each shift clock cycle. Next count after 0x0 is PRESET." /> - <BitField start="12" size="20" name="RESERVED" description="Reserved." /> - </Register> - <Register start="+0x0180+56" size="4" name="COUNT[14]" access="Read/Write" description="Down counter, counts down each clock cycle." reset_value="0" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="12" name="COUNT" description="Down counter, counts down each shift clock cycle. Next count after 0x0 is PRESET." /> - <BitField start="12" size="20" name="RESERVED" description="Reserved." /> - </Register> - <Register start="+0x0180+60" size="4" name="COUNT[15]" access="Read/Write" description="Down counter, counts down each clock cycle." reset_value="0" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="12" name="COUNT" description="Down counter, counts down each shift clock cycle. Next count after 0x0 is PRESET." /> - <BitField start="12" size="20" name="RESERVED" description="Reserved." /> - </Register> - <Register start="+0x01C0+0" size="4" name="POS[0]" access="Read/Write" description="Each time COUNT0 reaches 0x0 POS counts down." reset_value="0" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="8" name="POS" description="Each time COUNT reaches 0x0 POS counts down." /> - <BitField start="8" size="8" name="POS_RESET" description="Reload value for POS after POS reaches 0x0." /> - <BitField start="16" size="16" name="RESERVED" description="Reserved." /> - </Register> - <Register start="+0x01C0+4" size="4" name="POS[1]" access="Read/Write" description="Each time COUNT0 reaches 0x0 POS counts down." reset_value="0" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="8" name="POS" description="Each time COUNT reaches 0x0 POS counts down." /> - <BitField start="8" size="8" name="POS_RESET" description="Reload value for POS after POS reaches 0x0." /> - <BitField start="16" size="16" name="RESERVED" description="Reserved." /> - </Register> - <Register start="+0x01C0+8" size="4" name="POS[2]" access="Read/Write" description="Each time COUNT0 reaches 0x0 POS counts down." reset_value="0" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="8" name="POS" description="Each time COUNT reaches 0x0 POS counts down." /> - <BitField start="8" size="8" name="POS_RESET" description="Reload value for POS after POS reaches 0x0." /> - <BitField start="16" size="16" name="RESERVED" description="Reserved." /> - </Register> - <Register start="+0x01C0+12" size="4" name="POS[3]" access="Read/Write" description="Each time COUNT0 reaches 0x0 POS counts down." reset_value="0" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="8" name="POS" description="Each time COUNT reaches 0x0 POS counts down." /> - <BitField start="8" size="8" name="POS_RESET" description="Reload value for POS after POS reaches 0x0." /> - <BitField start="16" size="16" name="RESERVED" description="Reserved." /> - </Register> - <Register start="+0x01C0+16" size="4" name="POS[4]" access="Read/Write" description="Each time COUNT0 reaches 0x0 POS counts down." reset_value="0" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="8" name="POS" description="Each time COUNT reaches 0x0 POS counts down." /> - <BitField start="8" size="8" name="POS_RESET" description="Reload value for POS after POS reaches 0x0." /> - <BitField start="16" size="16" name="RESERVED" description="Reserved." /> - </Register> - <Register start="+0x01C0+20" size="4" name="POS[5]" access="Read/Write" description="Each time COUNT0 reaches 0x0 POS counts down." reset_value="0" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="8" name="POS" description="Each time COUNT reaches 0x0 POS counts down." /> - <BitField start="8" size="8" name="POS_RESET" description="Reload value for POS after POS reaches 0x0." /> - <BitField start="16" size="16" name="RESERVED" description="Reserved." /> - </Register> - <Register start="+0x01C0+24" size="4" name="POS[6]" access="Read/Write" description="Each time COUNT0 reaches 0x0 POS counts down." reset_value="0" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="8" name="POS" description="Each time COUNT reaches 0x0 POS counts down." /> - <BitField start="8" size="8" name="POS_RESET" description="Reload value for POS after POS reaches 0x0." /> - <BitField start="16" size="16" name="RESERVED" description="Reserved." /> - </Register> - <Register start="+0x01C0+28" size="4" name="POS[7]" access="Read/Write" description="Each time COUNT0 reaches 0x0 POS counts down." reset_value="0" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="8" name="POS" description="Each time COUNT reaches 0x0 POS counts down." /> - <BitField start="8" size="8" name="POS_RESET" description="Reload value for POS after POS reaches 0x0." /> - <BitField start="16" size="16" name="RESERVED" description="Reserved." /> - </Register> - <Register start="+0x01C0+32" size="4" name="POS[8]" access="Read/Write" description="Each time COUNT0 reaches 0x0 POS counts down." reset_value="0" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="8" name="POS" description="Each time COUNT reaches 0x0 POS counts down." /> - <BitField start="8" size="8" name="POS_RESET" description="Reload value for POS after POS reaches 0x0." /> - <BitField start="16" size="16" name="RESERVED" description="Reserved." /> - </Register> - <Register start="+0x01C0+36" size="4" name="POS[9]" access="Read/Write" description="Each time COUNT0 reaches 0x0 POS counts down." reset_value="0" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="8" name="POS" description="Each time COUNT reaches 0x0 POS counts down." /> - <BitField start="8" size="8" name="POS_RESET" description="Reload value for POS after POS reaches 0x0." /> - <BitField start="16" size="16" name="RESERVED" description="Reserved." /> - </Register> - <Register start="+0x01C0+40" size="4" name="POS[10]" access="Read/Write" description="Each time COUNT0 reaches 0x0 POS counts down." reset_value="0" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="8" name="POS" description="Each time COUNT reaches 0x0 POS counts down." /> - <BitField start="8" size="8" name="POS_RESET" description="Reload value for POS after POS reaches 0x0." /> - <BitField start="16" size="16" name="RESERVED" description="Reserved." /> - </Register> - <Register start="+0x01C0+44" size="4" name="POS[11]" access="Read/Write" description="Each time COUNT0 reaches 0x0 POS counts down." reset_value="0" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="8" name="POS" description="Each time COUNT reaches 0x0 POS counts down." /> - <BitField start="8" size="8" name="POS_RESET" description="Reload value for POS after POS reaches 0x0." /> - <BitField start="16" size="16" name="RESERVED" description="Reserved." /> - </Register> - <Register start="+0x01C0+48" size="4" name="POS[12]" access="Read/Write" description="Each time COUNT0 reaches 0x0 POS counts down." reset_value="0" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="8" name="POS" description="Each time COUNT reaches 0x0 POS counts down." /> - <BitField start="8" size="8" name="POS_RESET" description="Reload value for POS after POS reaches 0x0." /> - <BitField start="16" size="16" name="RESERVED" description="Reserved." /> - </Register> - <Register start="+0x01C0+52" size="4" name="POS[13]" access="Read/Write" description="Each time COUNT0 reaches 0x0 POS counts down." reset_value="0" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="8" name="POS" description="Each time COUNT reaches 0x0 POS counts down." /> - <BitField start="8" size="8" name="POS_RESET" description="Reload value for POS after POS reaches 0x0." /> - <BitField start="16" size="16" name="RESERVED" description="Reserved." /> - </Register> - <Register start="+0x01C0+56" size="4" name="POS[14]" access="Read/Write" description="Each time COUNT0 reaches 0x0 POS counts down." reset_value="0" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="8" name="POS" description="Each time COUNT reaches 0x0 POS counts down." /> - <BitField start="8" size="8" name="POS_RESET" description="Reload value for POS after POS reaches 0x0." /> - <BitField start="16" size="16" name="RESERVED" description="Reserved." /> - </Register> - <Register start="+0x01C0+60" size="4" name="POS[15]" access="Read/Write" description="Each time COUNT0 reaches 0x0 POS counts down." reset_value="0" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="8" name="POS" description="Each time COUNT reaches 0x0 POS counts down." /> - <BitField start="8" size="8" name="POS_RESET" description="Reload value for POS after POS reaches 0x0." /> - <BitField start="16" size="16" name="RESERVED" description="Reserved." /> - </Register> - <Register start="+0x0200" size="4" name="MASK_A" access="Read/Write" description="Mask for pattern match function of slice A" reset_value="0" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="32" name="MASK_A" description="Mask for pattern match function of slice A 0 = No effect. 1 = Mask this bit." /> - </Register> - <Register start="+0x0204" size="4" name="MASK_H" access="Read/Write" description="Mask for pattern match function of slice H" reset_value="0" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="32" name="MASK_H" description="Mask for pattern match function of slice H 0 = No effect. 1 = Mask this bit." /> - </Register> - <Register start="+0x0208" size="4" name="MASK_I" access="Read/Write" description="Mask for pattern match function of slice I" reset_value="0" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="32" name="MASK_I" description="Mask for pattern match function of slice I 0 = No effect . 1 = Mask this bit." /> - </Register> - <Register start="+0x020C" size="4" name="MASK_P" access="Read/Write" description="Mask for pattern match function of slice P" reset_value="0" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="32" name="MASK_P" description="Mask for pattern match function of slice P 0 = No effect. 1 = Mask this bit." /> - </Register> - <Register start="+0x0210" size="4" name="GPIO_INREG" access="ReadOnly" description="GPIO input status register" reset_value="0" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="16" name="GPIO_INi" description="Bit i reflects the input state of SGPIO pin i . 0 = LOW 1 = HIGH" /> - <BitField start="16" size="16" name="RESERVED" description="Reserved." /> - </Register> - <Register start="+0x0214" size="4" name="GPIO_OUTREG" access="Read/Write" description="GPIO output control register" reset_value="0" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="16" name="GPIO_OUT" description="GPIO output register. Bit i sets the output of SGPIO pin i. 0 = LOW 1 = HIGH" /> - <BitField start="16" size="16" name="RESERVED" description="Reserved." /> - </Register> - <Register start="+0x0218" size="4" name="GPIO_OENREG" access="Read/Write" description="GPIO OE control register" reset_value="0" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="16" name="GPIO_OE" description="Bit i selects the output enable state of SGPIO pin i. 0 = GPIO output i is tri-stated . 1 = GPIO output i is active." /> - <BitField start="16" size="16" name="RESERVED" description="Reserved." /> - </Register> - <Register start="+0x021C" size="4" name="CTRL_ENABLE" access="Read/Write" description="Enables the slice COUNT counter" reset_value="0" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="16" name="CTRL_EN" description="Slice count enable. Bit n controls slice n (0 = slice A, ..., 15 = slice P). 0 = Disables slice shift clock. 1 = Starts COUNTn or external shift clock." /> - <BitField start="16" size="16" name="RESERVED" description="Reserved." /> - </Register> - <Register start="+0x0220" size="4" name="CTRL_DISABLE" access="Read/Write" description="Disables the slice POS counter" reset_value="0" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="16" name="CTRL_DIS" description="Slice count disable. Bit n controls slice n, (0 = slice A, ..., 15 = slice P). 0 = Enables COUNT and POS counters. The counters start counting when the CTRL_EN bit or bits are set in the CTRL_ENABLED register. 1 = Disables POS counter of slice n." /> - <BitField start="16" size="16" name="RESERVED" description="Reserved." /> - </Register> - <Register start="+0x0F00" size="4" name="CLR_EN_0" access="WriteOnly" description="Shift clock interrupt clear mask" reset_value="0" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="16" name="CLR_SCI" description="1 = Shift clock interrupt clear mask of slice n." /> - <BitField start="16" size="16" name="RESERVED" description="Reserved." /> - </Register> - <Register start="+0x0F04" size="4" name="SET_EN_0" access="WriteOnly" description="Shift clock interrupt set mask" reset_value="0" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="16" name="SET_SCI" description="1 = Shift clock interrupt set mask of slice n." /> - <BitField start="16" size="16" name="RESERVED" description="Reserved." /> - </Register> - <Register start="+0x0F08" size="4" name="ENABLE_0" access="ReadOnly" description="Shift clock interrupt enable" reset_value="0" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="16" name="ENABLE_SCI" description="1 = Shift clock interrupt enable of slice n." /> - <BitField start="16" size="16" name="RESERVED" description="Reserved." /> - </Register> - <Register start="+0x0F0C" size="4" name="STATUS_0" access="ReadOnly" description="Shift clock interrupt status" reset_value="0" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="16" name="STATUS_SCI" description="Shift clock interrupt status of slice n." /> - <BitField start="16" size="16" name="RESERVED" description="Reserved." /> - </Register> - <Register start="+0x0F10" size="4" name="CLR_STATUS_0" access="WriteOnly" description="Shift clock interrupt clear status" reset_value="0" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="16" name="CLR_STATUS_SCI" description="Shift clock interrupt clear status of slice n." /> - <BitField start="16" size="16" name="RESERVED" description="Reserved." /> - </Register> - <Register start="+0x0F14" size="4" name="SET_STATUS_0" access="WriteOnly" description="Shift clock interrupt set status" reset_value="0" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="16" name="SET_STATUS_SCI" description="Shift clock interrupt set status of slice n." /> - <BitField start="16" size="16" name="RESERVED" description="Reserved." /> - </Register> - <Register start="+0x0F20" size="4" name="CLR_EN_1" access="WriteOnly" description="Exchange clock interrupt clear mask" reset_value="0" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="16" name="CLR_EN_CCI" description="1 = Exchange clock interrupt clear mask of slice n." /> - <BitField start="16" size="16" name="RESERVED" description="Reserved." /> - </Register> - <Register start="+0x0F24" size="4" name="SET_EN_1" access="WriteOnly" description="Exchange clock interrupt set mask" reset_value="0" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="16" name="SET_EN_CCI" description="1 = Exchange clock interrupt set mask of slice n." /> - <BitField start="16" size="16" name="RESERVED" description="Reserved." /> - </Register> - <Register start="+0x0F28" size="4" name="ENABLE_1" access="ReadOnly" description="Exchange clock interrupt enable" reset_value="0" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="16" name="ENABLE_CCI" description="Exchange clock interrupt enable of slice n." /> - <BitField start="16" size="16" name="RESERVED" description="Reserved." /> - </Register> - <Register start="+0x0F2C" size="4" name="STATUS_1" access="ReadOnly" description="Exchange clock interrupt status" reset_value="0" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="16" name="STATUS_CCI" description="Exchange clock interrupt status of slice n." /> - <BitField start="16" size="16" name="RESERVED" description="Reserved." /> - </Register> - <Register start="+0x0F30" size="4" name="CLR_STATUS_1" access="WriteOnly" description="Exchange clock interrupt clear status" reset_value="0" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="16" name="CLR_STATUS_CCI" description="Exchange clock interrupt clear status of slice n." /> - <BitField start="16" size="16" name="RESERVED" description="Reserved." /> - </Register> - <Register start="+0x0F34" size="4" name="SET_STATUS_1" access="WriteOnly" description="Exchange clock interrupt set status" reset_value="0" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="16" name="SET_STATUS_CCI" description="Exchange clock interrupt set status of slice n." /> - <BitField start="16" size="16" name="RESERVED" description="Reserved." /> - </Register> - <Register start="+0x0F40" size="4" name="CLR_EN_2" access="WriteOnly" description="Pattern match interrupt clear mask" reset_value="0" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="16" name="CLR_EN2_PMI" description="1 = Match interrupt clear mask of slice n." /> - <BitField start="16" size="16" name="RESERVED" description="Reserved." /> - </Register> - <Register start="+0x0F44" size="4" name="SET_EN_2" access="WriteOnly" description="Pattern match interrupt set mask" reset_value="0" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="16" name="SET_EN_PMI" description="1 = Match interrupt set mask of slice n." /> - <BitField start="16" size="16" name="RESERVED" description="Reserved." /> - </Register> - <Register start="+0x0F48" size="4" name="ENABLE_2" access="ReadOnly" description="Pattern match interrupt enable" reset_value="0" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="16" name="ENABLE_PMI" description="Match interrupt enable of slice n." /> - <BitField start="16" size="16" name="RESERVED" description="Reserved." /> - </Register> - <Register start="+0x0F4C" size="4" name="STATUS_2" access="ReadOnly" description="Pattern match interrupt status" reset_value="0" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="16" name="STATUS_PMI" description="Match interrupt status of slice n." /> - <BitField start="16" size="16" name="RESERVED" description="Reserved." /> - </Register> - <Register start="+0x0F50" size="4" name="CLR_STATUS_2" access="WriteOnly" description="Pattern match interrupt clear status" reset_value="0" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="16" name="CLR_STATUS_PMI" description="Match interrupt clear status of slice n." /> - <BitField start="16" size="16" name="RESERVED" description="Reserved." /> - </Register> - <Register start="+0x0F54" size="4" name="SET_STATUS_2" access="WriteOnly" description="Pattern match interrupt set status" reset_value="0" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="16" name="SET_STATUS_PMI" description="Match interrupt set status of slice n." /> - <BitField start="16" size="16" name="RESERVED" description="Reserved." /> - </Register> - <Register start="+0x0F60" size="4" name="CLR_EN_3" access="WriteOnly" description="Input interrupt clear mask" reset_value="0" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="16" name="CLR_EN_INPI" description="1 = Input interrupt clear mask of slice n." /> - <BitField start="16" size="16" name="RESERVED" description="Reserved." /> - </Register> - <Register start="+0x0F64" size="4" name="SET_EN_3" access="WriteOnly" description="Input bit match interrupt set mask" reset_value="0" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="16" name="SET_EN_INPI" description="1 = Input interrupt set mask of slice n." /> - <BitField start="16" size="16" name="RESERVED" description="Reserved." /> - </Register> - <Register start="+0x0F68" size="4" name="ENABLE_3" access="ReadOnly" description="Input bit match interrupt enable" reset_value="0" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="16" name="ENABLE3_INPI" description="Input interrupt enable of slice n." /> - <BitField start="16" size="16" name="RESERVED" description="Reserved." /> - </Register> - <Register start="+0x0F6C" size="4" name="STATUS_3" access="ReadOnly" description="Input bit match interrupt status" reset_value="0" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="16" name="STATUS_INPI" description="Input interrupt status of slice n." /> - <BitField start="16" size="16" name="RESERVED" description="Reserved." /> - </Register> - <Register start="+0x0F70" size="4" name="CLR_STATUS_3" access="WriteOnly" description="Input bit match interrupt clear status" reset_value="0" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="16" name="CLR_STATUS_INPI" description="Input interrupt clear status of slice n." /> - <BitField start="16" size="16" name="RESERVED" description="Reserved." /> - </Register> - <Register start="+0x0F74" size="4" name="SET_STATUS_3" access="WriteOnly" description="Input bit match interrupt set status" reset_value="0" reset_mask="0xFFFFFFFF"> - <BitField start="0" size="16" name="SET_STATUS_INPI" description="Shift interrupt set status of slice n." /> - <BitField start="16" size="16" name="RESERVED" description="Reserved." /> - </Register> - </RegisterGroup> <RegisterGroup name="NVIC" start="0xE000E100" description="Nested Vectored Interrupt Controller"> <Register name="NVIC_ISER0" description="Interrupt Set-Enable Register 0" start="0xE000E100"> <BitField name="DAC" start="0" size="1" /> @@ -32994,7 +29978,6 @@ <BitField name="ADC0" start="17" size="1" /> <BitField name="I2C0" start="18" size="1" /> <BitField name="I2C1" start="19" size="1" /> - <BitField name="SPI_INT" start="20" size="1" /> <BitField name="ADC1" start="21" size="1" /> <BitField name="SSP0" start="22" size="1" /> <BitField name="SSP1" start="23" size="1" /> @@ -33005,7 +29988,6 @@ <BitField name="I2S0" start="28" size="1" /> <BitField name="I2S1" start="29" size="1" /> <BitField name="SPIFI" start="30" size="1" /> - <BitField name="SGPIO_IINT" start="31" size="1" /> </Register> <Register name="NVIC_ISER1" description="Interrupt Set-Enable Register 1" start="0xE000E104"> <BitField name="PIN_INT0" start="0" size="1" /> @@ -33020,7 +30002,6 @@ <BitField name="GINT1" start="9" size="1" /> <BitField name="EVENTROUTER" start="10" size="1" /> <BitField name="C_CAN1" start="11" size="1" /> - <BitField name="ADCHS" start="13" size="1" /> <BitField name="ATIMER" start="14" size="1" /> <BitField name="RTC" start="15" size="1" /> <BitField name="WWDT" start="17" size="1" /> @@ -33046,7 +30027,6 @@ <BitField name="ADC0" start="17" size="1" /> <BitField name="I2C0" start="18" size="1" /> <BitField name="I2C1" start="19" size="1" /> - <BitField name="SPI_INT" start="20" size="1" /> <BitField name="ADC1" start="21" size="1" /> <BitField name="SSP0" start="22" size="1" /> <BitField name="SSP1" start="23" size="1" /> @@ -33057,7 +30037,6 @@ <BitField name="I2S0" start="28" size="1" /> <BitField name="I2S1" start="29" size="1" /> <BitField name="SPIFI" start="30" size="1" /> - <BitField name="SGPIO_IINT" start="31" size="1" /> </Register> <Register name="NVIC_ICER1" description="Interrupt Clear-Enable Register 1" start="0xE000E184"> <BitField name="PIN_INT0" start="0" size="1" /> @@ -33072,7 +30051,6 @@ <BitField name="GINT1" start="9" size="1" /> <BitField name="EVENTROUTER" start="10" size="1" /> <BitField name="C_CAN1" start="11" size="1" /> - <BitField name="ADCHS" start="13" size="1" /> <BitField name="ATIMER" start="14" size="1" /> <BitField name="RTC" start="15" size="1" /> <BitField name="WWDT" start="17" size="1" /> @@ -33098,7 +30076,6 @@ <BitField name="ADC0" start="17" size="1" /> <BitField name="I2C0" start="18" size="1" /> <BitField name="I2C1" start="19" size="1" /> - <BitField name="SPI_INT" start="20" size="1" /> <BitField name="ADC1" start="21" size="1" /> <BitField name="SSP0" start="22" size="1" /> <BitField name="SSP1" start="23" size="1" /> @@ -33109,7 +30086,6 @@ <BitField name="I2S0" start="28" size="1" /> <BitField name="I2S1" start="29" size="1" /> <BitField name="SPIFI" start="30" size="1" /> - <BitField name="SGPIO_IINT" start="31" size="1" /> </Register> <Register name="NVIC_ISPR1" description="Interrupt Set-Pending Register 1" start="0xE000E204"> <BitField name="PIN_INT0" start="0" size="1" /> @@ -33124,7 +30100,6 @@ <BitField name="GINT1" start="9" size="1" /> <BitField name="EVENTROUTER" start="10" size="1" /> <BitField name="C_CAN1" start="11" size="1" /> - <BitField name="ADCHS" start="13" size="1" /> <BitField name="ATIMER" start="14" size="1" /> <BitField name="RTC" start="15" size="1" /> <BitField name="WWDT" start="17" size="1" /> @@ -33150,7 +30125,6 @@ <BitField name="ADC0" start="17" size="1" /> <BitField name="I2C0" start="18" size="1" /> <BitField name="I2C1" start="19" size="1" /> - <BitField name="SPI_INT" start="20" size="1" /> <BitField name="ADC1" start="21" size="1" /> <BitField name="SSP0" start="22" size="1" /> <BitField name="SSP1" start="23" size="1" /> @@ -33161,7 +30135,6 @@ <BitField name="I2S0" start="28" size="1" /> <BitField name="I2S1" start="29" size="1" /> <BitField name="SPIFI" start="30" size="1" /> - <BitField name="SGPIO_IINT" start="31" size="1" /> </Register> <Register name="NVIC_ICPR1" description="Interrupt Clear-Pending Register 1" start="0xE000E284"> <BitField name="PIN_INT0" start="0" size="1" /> @@ -33176,7 +30149,6 @@ <BitField name="GINT1" start="9" size="1" /> <BitField name="EVENTROUTER" start="10" size="1" /> <BitField name="C_CAN1" start="11" size="1" /> - <BitField name="ADCHS" start="13" size="1" /> <BitField name="ATIMER" start="14" size="1" /> <BitField name="RTC" start="15" size="1" /> <BitField name="WWDT" start="17" size="1" /> @@ -33202,7 +30174,6 @@ <BitField name="ADC0" start="17" size="1" /> <BitField name="I2C0" start="18" size="1" /> <BitField name="I2C1" start="19" size="1" /> - <BitField name="SPI_INT" start="20" size="1" /> <BitField name="ADC1" start="21" size="1" /> <BitField name="SSP0" start="22" size="1" /> <BitField name="SSP1" start="23" size="1" /> @@ -33213,7 +30184,6 @@ <BitField name="I2S0" start="28" size="1" /> <BitField name="I2S1" start="29" size="1" /> <BitField name="SPIFI" start="30" size="1" /> - <BitField name="SGPIO_IINT" start="31" size="1" /> </Register> <Register name="NVIC_IABR1" description="Interrupt Active Bit Register 1" start="0xE000E304" access="ReadOnly"> <BitField name="PIN_INT0" start="0" size="1" /> @@ -33228,7 +30198,6 @@ <BitField name="GINT1" start="9" size="1" /> <BitField name="EVENTROUTER" start="10" size="1" /> <BitField name="C_CAN1" start="11" size="1" /> - <BitField name="ADCHS" start="13" size="1" /> <BitField name="ATIMER" start="14" size="1" /> <BitField name="RTC" start="15" size="1" /> <BitField name="WWDT" start="17" size="1" /> @@ -33236,80 +30205,77 @@ <BitField name="QEI" start="20" size="1" /> </Register> <Register name="NVIC_IPR0" description="Interrupt Priority Register 0" start="0xE000E400"> - <BitField name="DAC" start="5" size="3" /> - <BitField name="DMA" start="21" size="3" /> + <BitField name="DAC" start="4" size="4" /> + <BitField name="DMA" start="20" size="4" /> </Register> <Register name="NVIC_IPR1" description="Interrupt Priority Register 1" start="0xE000E404"> - <BitField name="FLASH" start="5" size="3" /> - <BitField name="ETHERNET" start="13" size="3" /> - <BitField name="SDIO" start="21" size="3" /> - <BitField name="LCD" start="29" size="3" /> + <BitField name="FLASH" start="4" size="4" /> + <BitField name="ETHERNET" start="12" size="4" /> + <BitField name="SDIO" start="20" size="4" /> + <BitField name="LCD" start="28" size="4" /> </Register> <Register name="NVIC_IPR2" description="Interrupt Priority Register 2" start="0xE000E408"> - <BitField name="USB0" start="5" size="3" /> - <BitField name="USB1" start="13" size="3" /> - <BitField name="SCT" start="21" size="3" /> - <BitField name="RITIMER" start="29" size="3" /> + <BitField name="USB0" start="4" size="4" /> + <BitField name="USB1" start="12" size="4" /> + <BitField name="SCT" start="20" size="4" /> + <BitField name="RITIMER" start="28" size="4" /> </Register> <Register name="NVIC_IPR3" description="Interrupt Priority Register 3" start="0xE000E40C"> - <BitField name="TIMER0" start="5" size="3" /> - <BitField name="TIMER1" start="13" size="3" /> - <BitField name="TIMER2" start="21" size="3" /> - <BitField name="TIMER3" start="29" size="3" /> + <BitField name="TIMER0" start="4" size="4" /> + <BitField name="TIMER1" start="12" size="4" /> + <BitField name="TIMER2" start="20" size="4" /> + <BitField name="TIMER3" start="28" size="4" /> </Register> <Register name="NVIC_IPR4" description="Interrupt Priority Register 4" start="0xE000E410"> - <BitField name="MCPWM" start="5" size="3" /> - <BitField name="ADC0" start="13" size="3" /> - <BitField name="I2C0" start="21" size="3" /> - <BitField name="I2C1" start="29" size="3" /> + <BitField name="MCPWM" start="4" size="4" /> + <BitField name="ADC0" start="12" size="4" /> + <BitField name="I2C0" start="20" size="4" /> + <BitField name="I2C1" start="28" size="4" /> </Register> <Register name="NVIC_IPR5" description="Interrupt Priority Register 5" start="0xE000E414"> - <BitField name="SPI_INT" start="5" size="3" /> - <BitField name="ADC1" start="13" size="3" /> - <BitField name="SSP0" start="21" size="3" /> - <BitField name="SSP1" start="29" size="3" /> + <BitField name="ADC1" start="12" size="4" /> + <BitField name="SSP0" start="20" size="4" /> + <BitField name="SSP1" start="28" size="4" /> </Register> <Register name="NVIC_IPR6" description="Interrupt Priority Register 6" start="0xE000E418"> - <BitField name="USART0" start="5" size="3" /> - <BitField name="UART1" start="13" size="3" /> - <BitField name="USART2" start="21" size="3" /> - <BitField name="USART3" start="29" size="3" /> + <BitField name="USART0" start="4" size="4" /> + <BitField name="UART1" start="12" size="4" /> + <BitField name="USART2" start="20" size="4" /> + <BitField name="USART3" start="28" size="4" /> </Register> <Register name="NVIC_IPR7" description="Interrupt Priority Register 7" start="0xE000E41C"> - <BitField name="I2S0" start="5" size="3" /> - <BitField name="I2S1" start="13" size="3" /> - <BitField name="SPIFI" start="21" size="3" /> - <BitField name="SGPIO_IINT" start="29" size="3" /> + <BitField name="I2S0" start="4" size="4" /> + <BitField name="I2S1" start="12" size="4" /> + <BitField name="SPIFI" start="20" size="4" /> </Register> <Register name="NVIC_IPR8" description="Interrupt Priority Register 8" start="0xE000E420"> - <BitField name="PIN_INT0" start="5" size="3" /> - <BitField name="PIN_INT1" start="13" size="3" /> - <BitField name="PIN_INT2" start="21" size="3" /> - <BitField name="PIN_INT3" start="29" size="3" /> + <BitField name="PIN_INT0" start="4" size="4" /> + <BitField name="PIN_INT1" start="12" size="4" /> + <BitField name="PIN_INT2" start="20" size="4" /> + <BitField name="PIN_INT3" start="28" size="4" /> </Register> <Register name="NVIC_IPR9" description="Interrupt Priority Register 9" start="0xE000E424"> - <BitField name="PIN_INT4" start="5" size="3" /> - <BitField name="PIN_INT5" start="13" size="3" /> - <BitField name="PIN_INT6" start="21" size="3" /> - <BitField name="PIN_INT7" start="29" size="3" /> + <BitField name="PIN_INT4" start="4" size="4" /> + <BitField name="PIN_INT5" start="12" size="4" /> + <BitField name="PIN_INT6" start="20" size="4" /> + <BitField name="PIN_INT7" start="28" size="4" /> </Register> <Register name="NVIC_IPR10" description="Interrupt Priority Register 10" start="0xE000E428"> - <BitField name="GINT0" start="5" size="3" /> - <BitField name="GINT1" start="13" size="3" /> - <BitField name="EVENTROUTER" start="21" size="3" /> - <BitField name="C_CAN1" start="29" size="3" /> + <BitField name="GINT0" start="4" size="4" /> + <BitField name="GINT1" start="12" size="4" /> + <BitField name="EVENTROUTER" start="20" size="4" /> + <BitField name="C_CAN1" start="28" size="4" /> </Register> <Register name="NVIC_IPR11" description="Interrupt Priority Register 11" start="0xE000E42C"> - <BitField name="ADCHS" start="13" size="3" /> - <BitField name="ATIMER" start="21" size="3" /> - <BitField name="RTC" start="29" size="3" /> + <BitField name="ATIMER" start="20" size="4" /> + <BitField name="RTC" start="28" size="4" /> </Register> <Register name="NVIC_IPR12" description="Interrupt Priority Register 12" start="0xE000E430"> - <BitField name="WWDT" start="13" size="3" /> - <BitField name="C_CAN0" start="29" size="3" /> + <BitField name="WWDT" start="12" size="4" /> + <BitField name="C_CAN0" start="28" size="4" /> </Register> <Register name="NVIC_IPR13" description="Interrupt Priority Register 13" start="0xE000E434"> - <BitField name="QEI" start="5" size="3" /> + <BitField name="QEI" start="4" size="4" /> </Register> </RegisterGroup> <RegisterGroup name="SysTick" start="0xE000E010" description="24-bit System Timer"> @@ -33333,8 +30299,6 @@ </RegisterGroup> <RegisterGroup name="SCB" start="" description="System Control Block"> <Register name="ACTLR" start="0xE000E008" description="Auxiliary Control Register"> - <BitField name="DISOOFP" start="9" size="1" description="Disables floating pointinstructions completing outof order with respect to integer instructions" /> - <BitField name="DISFPCA" start="8" size="1" description="When set to 1, disables IT folding" /> <BitField name="DISFOLD" start="2" size="1" description="When set to 1, disables write buffer use during default memory map accesses" /> <BitField name="DISDEFWBUF" start="1" size="1" description="When set to 1, disables write buffer use during default memory map accesses" /> <BitField name="DISMCYCINT" start="0" size="1" description="When set to 1, disables interruption of load multiple and store multiple instructions" /> @@ -33382,16 +30346,16 @@ <BitField name="NONBASETHRDENA" start="0" size="1" description="Indicates how the processor enters Thread mode" /> </Register> <Register name="SHPR1" start="0xE000ED18" description="System Handler Priority Register 1"> - <BitField name="PRI_6" start="21" size="3" description="Priority of system handler 6 (UsageFault)" /> - <BitField name="PRI_5" start="13" size="3" description="Priority of system handler 5 (BusFault)" /> - <BitField name="PRI_4" start="5" size="3" description="Priority of system handler 4 (MemManage)" /> + <BitField name="PRI_6" start="20" size="4" description="Priority of system handler 6 (UsageFault)" /> + <BitField name="PRI_5" start="12" size="4" description="Priority of system handler 5 (BusFault)" /> + <BitField name="PRI_4" start="4" size="4" description="Priority of system handler 4 (MemManage)" /> </Register> <Register name="SHPR2" start="0xE000ED1C" description="System Handler Priority Register 2"> - <BitField name="PRI_11" start="29" size="3" description="Priority of system handler 11 (SVCall)" /> + <BitField name="PRI_11" start="28" size="4" description="Priority of system handler 11 (SVCall)" /> </Register> <Register name="SHPR3" start="0xE000ED20" description="System Handler Priority Register 3"> - <BitField name="PRI_15" start="29" size="3" description="Priority of system handler 15 (SysTick)" /> - <BitField name="PRI_14" start="21" size="3" description="Priority of system handler 14 (PendSV)" /> + <BitField name="PRI_15" start="28" size="4" description="Priority of system handler 15 (SysTick)" /> + <BitField name="PRI_14" start="20" size="4" description="Priority of system handler 14 (PendSV)" /> </Register> <Register name="SHCSR" start="0xE000ED24" description="System Handler Control and State Register"> <BitField name="USGFAULTENA" start="18" size="1" description="UsageFault enable Bit" /> @@ -33411,7 +30375,6 @@ </Register> <Register name="MMSR" start="0xE000ED28" size="1" description="MemManage Fault Status Register"> <BitField name="MMARVALID" start="7" size="1" description="MemManage Fault Address Register(MMFAR) valid flag" /> - <BitField name="MLSPERR" start="5" size="1" description="Indicates a MemManage fault occurred during floating-point lazy state preservation" /> <BitField name="MSTKERR" start="4" size="1" description="MemManage fault on stacking for exception entry" /> <BitField name="MUNSTKERR" start="3" size="1" description="MemManage fault on unstacking for a return from exception" /> <BitField name="DACCVIOL" start="1" size="1" description="Data access violation flag" /> @@ -33419,7 +30382,6 @@ </Register> <Register name="BFSR" start="0xE000ED29" size="1" description="BusFault Status Register"> <BitField name="BFARVALID" start="7" size="1" description="BusFault Address Register(BFAR) valid flag" /> - <BitField name="LSPERR" start="5" size="1" description="Indicates a bus fault occurred during floating-point lazy state preservation" /> <BitField name="STKERR" start="4" size="1" description="BusFault on stacking for exception entry" /> <BitField name="UNSTKERR" start="3" size="1" description="BusFault on unstacking for a return from exception" /> <BitField name="IMPRECISERR" start="2" size="1" description="Imprecise data bus error" /> @@ -33456,42 +30418,6 @@ <BitField name="IMPDEF" start="0" size="32" description="Implementation defined, the bits map to the AUXFAULT input signals" /> </Register> </RegisterGroup> - <RegisterGroup name="FPU" description="Floating Point Unit"> - <Register name="CPACR" start="0xE000ED88" description="Coprocessor Access Control Register"> - <BitField name="CP11" start="22" size="2" description="Access privileges for coprocessor 11" /> - <BitField name="CP10" start="20" size="2" description="Access privileges for coprocessor 10" /> - </Register> - <Register name="FPCCR" start="0xE000EF34" description="Floating-point Context Control Register"> - <BitField name="ASPEN" start="31" size="1" description="Automatic State Preservation" /> - <BitField name="LSPEN" start="30" size="1" description="Lazy State Preservation Enabled" /> - <BitField name="MONRDY" start="8" size="1" description="Monitor Ready" /> - <BitField name="BFRDY" start="6" size="1" description="BusFault Ready" /> - <BitField name="MMRDY" start="5" size="1" description="MemManage Ready" /> - <BitField name="HFRDY" start="4" size="1" description="HardFault Ready" /> - <BitField name="THREAD" start="3" size="1" description="Thread Mode Allocated Stack Frame" /> - <BitField name="USER" start="1" size="1" description="User Allocated Stack Frame" /> - <BitField name="LSPACT" start="0" size="1" description="Lazy State Preservation Active" /> - </Register> - <Register name="FPCAR" start="0xE000EF38" description="Floating-point Context Address Register"> - <BitField name="ADDRESSS" start="3" size="29" description="The location of the unpopulated floating-point register space allocated on an exception stack frame" /> - </Register> - <Register name="FPDSCR" start="0xE000EF3C" description="Floating-point Status Control Register"> - <BitField name="N" start="31" size="1" description="Negative condition code flag" /> - <BitField name="Z" start="30" size="1" description="Zero condition code flag" /> - <BitField name="C" start="29" size="1" description="Carry condition code flag" /> - <BitField name="V" start="28" size="1" description="Overflow condition code flag" /> - <BitField name="AHP" start="26" size="1" description="Alternative half-precision control bit" /> - <BitField name="DN" start="25" size="1" description="Default NaN mode control bit" /> - <BitField name="FZ" start="24" size="1" description="Flush-to-zero mode control bit" /> - <BitField name="RMode" start="22" size="2" description="Rounding Mode control field" /> - <BitField name="IDC" start="7" size="1" description="Input Denormal cumulative exception bit" /> - <BitField name="IXC" start="4" size="1" description="Inexact cumulative exception bit" /> - <BitField name="UFC" start="3" size="1" description="Underflow cumulative exception bit" /> - <BitField name="OFC" start="2" size="1" description="Overflow cumulative exception bit" /> - <BitField name="DZC" start="1" size="1" description="Division by Zero cumulative exception bit" /> - <BitField name="IOC" start="0" size="1" description="Invalid Operation cumulative exception bit" /> - </Register> - </RegisterGroup> <RegisterGroup name="MPU" start="0xE000ED90" description="Memory Protection Unit"> <Register name="MPU_TYPE" start="0xE000ED90" access="ReadOnly" description="MPU Type Register"> <BitField name="IREGION" start="16" size="8" description="Number of supported MPU instruction regions" /> diff --git a/examples/device/device_virtual_com/segger/LPC43xx_Vectors.s b/examples/device/cdc_msc_hid/ses/lpc18xx/LPC18xx_Vectors.s index ab223b8a1..8f9a39e42 100644 --- a/examples/device/device_virtual_com/segger/LPC43xx_Vectors.s +++ b/examples/device/cdc_msc_hid/ses/lpc18xx/LPC18xx_Vectors.s @@ -114,9 +114,6 @@ Dummy_Handler: .weak I2C1_IRQHandler .thumb_set I2C1_IRQHandler,Dummy_Handler - .weak SPI_INT_IRQHandler - .thumb_set SPI_INT_IRQHandler,Dummy_Handler - .weak ADC1_IRQHandler .thumb_set ADC1_IRQHandler,Dummy_Handler @@ -147,9 +144,6 @@ Dummy_Handler: .weak SPIFI_IRQHandler .thumb_set SPIFI_IRQHandler,Dummy_Handler - .weak SGPIO_IINT_IRQHandler - .thumb_set SGPIO_IINT_IRQHandler,Dummy_Handler - .weak PIN_INT0_IRQHandler .thumb_set PIN_INT0_IRQHandler,Dummy_Handler @@ -186,9 +180,6 @@ Dummy_Handler: .weak C_CAN1_IRQHandler .thumb_set C_CAN1_IRQHandler,Dummy_Handler - .weak ADCHS_IRQHandler - .thumb_set ADCHS_IRQHandler,Dummy_Handler - .weak ATIMER_IRQHandler .thumb_set ATIMER_IRQHandler,Dummy_Handler @@ -297,11 +288,6 @@ I2C1_IRQHandler: b . .thumb_func - .weak SPI_INT_IRQHandler -SPI_INT_IRQHandler: - b . - - .thumb_func .weak ADC1_IRQHandler ADC1_IRQHandler: b . @@ -352,11 +338,6 @@ SPIFI_IRQHandler: b . .thumb_func - .weak SGPIO_IINT_IRQHandler -SGPIO_IINT_IRQHandler: - b . - - .thumb_func .weak PIN_INT0_IRQHandler PIN_INT0_IRQHandler: b . @@ -417,11 +398,6 @@ C_CAN1_IRQHandler: b . .thumb_func - .weak ADCHS_IRQHandler -ADCHS_IRQHandler: - b . - - .thumb_func .weak ATIMER_IRQHandler ATIMER_IRQHandler: b . @@ -495,7 +471,7 @@ _vectors: .word ADC0_IRQHandler .word I2C0_IRQHandler .word I2C1_IRQHandler - .word SPI_INT_IRQHandler + .word Dummy_Handler /* Reserved */ .word ADC1_IRQHandler .word SSP0_IRQHandler .word SSP1_IRQHandler @@ -506,7 +482,7 @@ _vectors: .word I2S0_IRQHandler .word I2S1_IRQHandler .word SPIFI_IRQHandler - .word SGPIO_IINT_IRQHandler + .word Dummy_Handler /* Reserved */ .word PIN_INT0_IRQHandler .word PIN_INT1_IRQHandler .word PIN_INT2_IRQHandler @@ -520,7 +496,7 @@ _vectors: .word EVENTROUTER_IRQHandler .word C_CAN1_IRQHandler .word Dummy_Handler /* Reserved */ - .word ADCHS_IRQHandler + .word Dummy_Handler /* Reserved */ .word ATIMER_IRQHandler .word RTC_IRQHandler .word Dummy_Handler /* Reserved */ diff --git a/examples/device/cdc_msc_hid/ses/lpc18xx/flash_placement.xml b/examples/device/cdc_msc_hid/ses/lpc18xx/flash_placement.xml new file mode 100644 index 000000000..79bedc537 --- /dev/null +++ b/examples/device/cdc_msc_hid/ses/lpc18xx/flash_placement.xml @@ -0,0 +1,37 @@ +<!DOCTYPE Linker_Placement_File> +<Root name="Flash Section Placement"> + <MemorySegment name="$(FLASH_NAME:FLASH)"> + <ProgramSection alignment="0x100" load="Yes" name=".vectors" start="$(FLASH_START:)" /> + <ProgramSection alignment="4" load="Yes" name=".init" /> + <ProgramSection alignment="4" load="Yes" name=".init_rodata" /> + <ProgramSection alignment="4" load="Yes" name=".text" /> + <ProgramSection alignment="4" load="Yes" name=".dtors" /> + <ProgramSection alignment="4" load="Yes" name=".ctors" /> + <ProgramSection alignment="4" load="Yes" name=".rodata" /> + <ProgramSection alignment="4" load="Yes" name=".ARM.exidx" address_symbol="__exidx_start" end_symbol="__exidx_end" /> + <ProgramSection alignment="4" load="Yes" runin=".fast_run" name=".fast" /> + <ProgramSection alignment="4" load="Yes" runin=".data_run" name=".data" /> + <ProgramSection alignment="4" load="Yes" runin=".tdata_run" name=".tdata" /> + </MemorySegment> + <MemorySegment name="$(RAM_NAME:RAM);SRAM"> + <ProgramSection alignment="0x100" load="No" name=".vectors_ram" start="$(RAM_START:$(SRAM_START:))" /> + <ProgramSection alignment="4" load="No" name=".fast_run" /> + <ProgramSection alignment="4" load="No" name=".data_run" /> + <ProgramSection alignment="4" load="No" name=".bss" /> + <ProgramSection alignment="4" load="No" name=".tbss" /> + <ProgramSection alignment="4" load="No" name=".tdata_run" /> + <ProgramSection alignment="4" load="No" name=".non_init" /> + <ProgramSection alignment="4" size="__HEAPSIZE__" load="No" name=".heap" /> + <ProgramSection alignment="8" size="__STACKSIZE__" load="No" place_from_segment_end="Yes" name=".stack" /> + <ProgramSection alignment="8" size="__STACKSIZE_PROCESS__" load="No" name=".stack_process" /> + </MemorySegment> + <MemorySegment name="$(FLASH2_NAME:FLASH2)"> + <ProgramSection alignment="4" load="Yes" name=".text2" /> + <ProgramSection alignment="4" load="Yes" name=".rodata2" /> + <ProgramSection alignment="4" load="Yes" runin=".data2_run" name=".data2" /> + </MemorySegment> + <MemorySegment name="$(RAM2_NAME:RAM2)"> + <ProgramSection alignment="4" load="No" name=".data2_run" /> + <ProgramSection alignment="4" load="No" name=".bss2" /> + </MemorySegment> +</Root> diff --git a/examples/device/cdc_msc_hid/ses/lpc18xx/lpc18xx.emProject b/examples/device/cdc_msc_hid/ses/lpc18xx/lpc18xx.emProject new file mode 100644 index 000000000..4435c60f4 --- /dev/null +++ b/examples/device/cdc_msc_hid/ses/lpc18xx/lpc18xx.emProject @@ -0,0 +1,131 @@ +<!DOCTYPE CrossStudio_Project_File> +<solution Name="lpc18xx" target="8" version="2"> + <project Name="lpc18xx"> + <configuration + Name="Common" + Placement="Flash" + Target="LPC1857" + arm_architecture="v7M" + arm_core_type="Cortex-M3" + arm_endian="Little" + arm_fpu_type="None" + arm_interwork="No" + arm_linker_heap_size="256" + arm_linker_process_stack_size="0" + arm_linker_stack_size="256" + arm_simulator_memory_simulation_parameter="RAM;0x10000000;0x00008000;ROM;0x1A000000;0x00080000;ROM;0x1B000000;0x00080000;RAM;0x20000000;0x00010000" + arm_target_debug_interface_type="ADIv5" + arm_target_device_name="LPC1857" + arm_target_interface_type="SWD" + build_treat_warnings_as_errors="Yes" + c_preprocessor_definitions="LPC18xx;__LPC1800_FAMILY;__LPC185x_SUBFAMILY;ARM_MATH_CM3;FLASH_PLACEMENT=1;CORE_M3;BOARD_MCB1800;CFG_TUSB_MCU=OPT_MCU_LPC18XX;CFG_TUSB_MEM_SECTION= __attribute__((section(".bss2")))" + c_user_include_directories="../../src;$(rootDir)/hw;$(rootDir)/src;$(lpcDir)//inc;$(lpcDir)//inc/config_18xx" + debug_register_definition_file="$(ProjectDir)/LPC18xx_Registers.xml" + debug_target_connection="J-Link" + gcc_enable_all_warnings="Yes" + gcc_entry_point="Reset_Handler" + linker_memory_map_file="$(ProjectDir)/LPC1857_MemoryMap.xml" + linker_section_placement_file="$(ProjectDir)/flash_placement.xml" + macros="DeviceFamily=LPC1800;DeviceSubFamily=LPC185x;Target=LPC1857;Placement=Flash;rootDir=../../../../..;lpcDir=../../../../../hw/mcu/nxp/lpc_chip_18xx" + package_dependencies="LPC1800" + project_directory="" + project_type="Executable" + target_reset_script="Reset();" + target_trace_initialize_script="EnableTrace("$(TraceInterfaceType)")" /> + <folder Name="System Files"> + <file file_name="thumb_crt0.s" /> + <file file_name="LPC1800_Startup.s" /> + <file file_name="LPC18xx_Vectors.s"> + <configuration Name="Common" file_type="Assembly" /> + </file> + <file file_name="LPC1857_MemoryMap.xml" /> + <file file_name="flash_placement.xml" /> + <file file_name="LPC1800_Target.js"> + <configuration Name="Common" file_type="Reset Script" /> + </file> + </folder> + <configuration + Name="Debug" + link_use_linker_script_file="No" + linker_section_placement_file="flash_placement.xml" /> + <folder Name="hw"> + <folder Name="bsp"> + <file file_name="../../../../../hw/bsp/ansi_escape.h" /> + <file file_name="../../../../../hw/bsp/board.h" /> + <folder Name="mcb1800"> + <file file_name="../../../../../hw/bsp/mcb1800/board_mcb1800.c" /> + <file file_name="../../../../../hw/bsp/mcb1800/board_mcb1800.h" /> + </folder> + </folder> + <folder Name="mcu"> + <folder Name="nxp"> + <folder Name="lpc_chip_18xx"> + <folder Name="inc"> + <file file_name="../../../../../hw/mcu/nxp/lpc_chip_18xx/inc/arm_common_tables.h" /> + <file file_name="../../../../../hw/mcu/nxp/lpc_chip_18xx/inc/arm_math.h" /> + <file file_name="../../../../../hw/mcu/nxp/lpc_chip_18xx/inc/cguccu_18xx_43xx.h" /> + <file file_name="../../../../../hw/mcu/nxp/lpc_chip_18xx/inc/chip.h" /> + <file file_name="../../../../../hw/mcu/nxp/lpc_chip_18xx/inc/chip_clocks.h" /> + <file file_name="../../../../../hw/mcu/nxp/lpc_chip_18xx/inc/chip_lpc18xx.h" /> + <file file_name="../../../../../hw/mcu/nxp/lpc_chip_18xx/inc/chip_lpc43xx.h" /> + <file file_name="../../../../../hw/mcu/nxp/lpc_chip_18xx/inc/clock_18xx_43xx.h" /> + <file file_name="../../../../../hw/mcu/nxp/lpc_chip_18xx/inc/cmsis.h" /> + <file file_name="../../../../../hw/mcu/nxp/lpc_chip_18xx/inc/cmsis_18xx.h" /> + <file file_name="../../../../../hw/mcu/nxp/lpc_chip_18xx/inc/cmsis_43xx.h" /> + <file file_name="../../../../../hw/mcu/nxp/lpc_chip_18xx/inc/cmsis_43xx_m0app.h" /> + <file file_name="../../../../../hw/mcu/nxp/lpc_chip_18xx/inc/cmsis_43xx_m0sub.h" /> + <file file_name="../../../../../hw/mcu/nxp/lpc_chip_18xx/inc/core_cm0.h" /> + <file file_name="../../../../../hw/mcu/nxp/lpc_chip_18xx/inc/core_cm0plus.h" /> + <file file_name="../../../../../hw/mcu/nxp/lpc_chip_18xx/inc/core_cm3.h" /> + <file file_name="../../../../../hw/mcu/nxp/lpc_chip_18xx/inc/core_cm4.h" /> + <file file_name="../../../../../hw/mcu/nxp/lpc_chip_18xx/inc/core_cm4_simd.h" /> + <file file_name="../../../../../hw/mcu/nxp/lpc_chip_18xx/inc/core_cmFunc.h" /> + <file file_name="../../../../../hw/mcu/nxp/lpc_chip_18xx/inc/core_cmInstr.h" /> + <file file_name="../../../../../hw/mcu/nxp/lpc_chip_18xx/inc/core_sc000.h" /> + <file file_name="../../../../../hw/mcu/nxp/lpc_chip_18xx/inc/core_sc300.h" /> + <file file_name="../../../../../hw/mcu/nxp/lpc_chip_18xx/inc/creg_18xx_43xx.h" /> + <file file_name="../../../../../hw/mcu/nxp/lpc_chip_18xx/inc/gpio_18xx_43xx.h" /> + <file file_name="../../../../../hw/mcu/nxp/lpc_chip_18xx/inc/lpc_types.h" /> + <file file_name="../../../../../hw/mcu/nxp/lpc_chip_18xx/inc/uart_18xx_43xx.h" /> + <file file_name="../../../../../hw/mcu/nxp/lpc_chip_18xx/inc/usbhs_18xx_43xx.h" /> + <folder Name="config_18xx"> + <file file_name="../../../../../hw/mcu/nxp/lpc_chip_18xx/inc/config_18xx/cmsis_18xx.h" /> + <file file_name="../../../../../hw/mcu/nxp/lpc_chip_18xx/inc/config_18xx/sys_config.h" /> + </folder> + </folder> + <folder Name="src"> + <file file_name="../../../../../hw/mcu/nxp/lpc_chip_18xx/src/chip_18xx_43xx.c" /> + <file file_name="../../../../../hw/mcu/nxp/lpc_chip_18xx/src/clock_18xx_43xx.c" /> + <file file_name="../../../../../hw/mcu/nxp/lpc_chip_18xx/src/gpio_18xx_43xx.c" /> + <file file_name="../../../../../hw/mcu/nxp/lpc_chip_18xx/src/sysinit_18xx_43xx.c" /> + <file file_name="../../../../../hw/mcu/nxp/lpc_chip_18xx/src/uart_18xx_43xx.c" /> + </folder> + </folder> + </folder> + </folder> + </folder> + <folder + Name="segger_rtt" + exclude="" + filter="*.c;*.h" + path="../../../../../lib/segger_rtt" + recurse="No" /> + <folder + Name="src" + exclude="" + filter="*.c;*.h" + path="../../src" + recurse="Yes" /> + <folder + Name="tinyusb" + exclude="" + filter="*.c;*.h" + path="../../../../../src" + recurse="Yes" /> + </project> + <configuration + Name="MCB1800" + c_preprocessor_definitions="DEBUG" + gcc_debugging_level="Level 3" + gcc_optimization_level="None" /> +</solution> diff --git a/examples/device/cdc_msc_hid/ses/lpc18xx/thumb_crt0.s b/examples/device/cdc_msc_hid/ses/lpc18xx/thumb_crt0.s new file mode 100644 index 000000000..17f88e0ca --- /dev/null +++ b/examples/device/cdc_msc_hid/ses/lpc18xx/thumb_crt0.s @@ -0,0 +1,415 @@ +// ********************************************************************** +// * SEGGER Microcontroller GmbH * +// * The Embedded Experts * +// ********************************************************************** +// * * +// * (c) 2014 - 2018 SEGGER Microcontroller GmbH * +// * (c) 2001 - 2018 Rowley Associates Limited * +// * * +// * www.segger.com Support: [email protected] * +// * * +// ********************************************************************** +// * * +// * All rights reserved. * +// * * +// * Redistribution and use in source and binary forms, with or * +// * without modification, are permitted provided that the following * +// * conditions are met: * +// * * +// * - Redistributions of source code must retain the above copyright * +// * notice, this list of conditions and the following disclaimer. * +// * * +// * - Neither the name of SEGGER Microcontroller GmbH * +// * nor the names of its contributors may be used to endorse or * +// * promote products derived from this software without specific * +// * prior written permission. * +// * * +// * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND * +// * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, * +// * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * +// * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * +// * DISCLAIMED. * +// * IN NO EVENT SHALL SEGGER Microcontroller GmbH BE LIABLE FOR * +// * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * +// * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT * +// * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * +// * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF * +// * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * +// * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE * +// * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH * +// * DAMAGE. * +// * * +// ********************************************************************** +// +// +// Preprocessor Definitions +// ------------------------ +// APP_ENTRY_POINT +// +// Defines the application entry point function, if undefined this setting +// defaults to "main". +// +// INITIALIZE_STACK +// +// If defined, the contents of the stack will be initialized to a the +// value 0xCC. +// +// INITIALIZE_SECONDARY_SECTIONS +// +// If defined, the .data2, .text2, .rodata2 and .bss2 sections will be initialized. +// +// INITIALIZE_TCM_SECTIONS +// +// If defined, the .data_tcm, .text_tcm, .rodata_tcm and .bss_tcm sections +// will be initialized. +// +// INITIALIZE_USER_SECTIONS +// +// If defined, the function InitializeUserMemorySections will be called prior +// to entering main in order to allow the user to initialize any user defined +// memory sections. +// +// FULL_LIBRARY +// +// If defined then +// - argc, argv are setup by the debug_getargs. +// - the exit symbol is defined and executes on return from main. +// - the exit symbol calls destructors, atexit functions and then debug_exit. +// +// If not defined then +// - argc and argv are zero. +// - the exit symbol is defined, executes on return from main and loops +// + +#ifndef APP_ENTRY_POINT +#define APP_ENTRY_POINT main +#endif + +#ifndef ARGSSPACE +#define ARGSSPACE 128 +#endif + .syntax unified + + .global _start + .extern APP_ENTRY_POINT + .global exit + .weak exit + +#ifdef INITIALIZE_USER_SECTIONS + .extern InitializeUserMemorySections +#endif + + .section .init, "ax" + .code 16 + .balign 2 + .thumb_func + +_start: + /* Set up main stack if size > 0 */ + ldr r1, =__stack_end__ + ldr r0, =__stack_start__ + subs r2, r1, r0 + beq 1f +#ifdef __ARM_EABI__ + movs r2, #0x7 + bics r1, r2 +#endif + mov sp, r1 +#ifdef INITIALIZE_STACK + movs r2, #0xCC + ldr r0, =__stack_start__ + bl memory_set +#endif +1: + + /* Set up process stack if size > 0 */ + ldr r1, =__stack_process_end__ + ldr r0, =__stack_process_start__ + subs r2, r1, r0 + beq 1f +#ifdef __ARM_EABI__ + movs r2, #0x7 + bics r1, r2 +#endif + msr psp, r1 + movs r2, #2 + msr control, r2 +#ifdef INITIALIZE_STACK + movs r2, #0xCC + bl memory_set +#endif +1: + + /* Copy initialized memory sections into RAM (if necessary). */ + ldr r0, =__data_load_start__ + ldr r1, =__data_start__ + ldr r2, =__data_end__ + bl memory_copy + ldr r0, =__text_load_start__ + ldr r1, =__text_start__ + ldr r2, =__text_end__ + bl memory_copy + ldr r0, =__fast_load_start__ + ldr r1, =__fast_start__ + ldr r2, =__fast_end__ + bl memory_copy + ldr r0, =__ctors_load_start__ + ldr r1, =__ctors_start__ + ldr r2, =__ctors_end__ + bl memory_copy + ldr r0, =__dtors_load_start__ + ldr r1, =__dtors_start__ + ldr r2, =__dtors_end__ + bl memory_copy + ldr r0, =__rodata_load_start__ + ldr r1, =__rodata_start__ + ldr r2, =__rodata_end__ + bl memory_copy + ldr r0, =__tdata_load_start__ + ldr r1, =__tdata_start__ + ldr r2, =__tdata_end__ + bl memory_copy +#ifdef INITIALIZE_SECONDARY_SECTIONS + ldr r0, =__data2_load_start__ + ldr r1, =__data2_start__ + ldr r2, =__data2_end__ + bl memory_copy + ldr r0, =__text2_load_start__ + ldr r1, =__text2_start__ + ldr r2, =__text2_end__ + bl memory_copy + ldr r0, =__rodata2_load_start__ + ldr r1, =__rodata2_start__ + ldr r2, =__rodata2_end__ + bl memory_copy +#endif /* #ifdef INITIALIZE_SECONDARY_SECTIONS */ +#ifdef INITIALIZE_TCM_SECTIONS + ldr r0, =__data_tcm_load_start__ + ldr r1, =__data_tcm_start__ + ldr r2, =__data_tcm_end__ + bl memory_copy + ldr r0, =__text_tcm_load_start__ + ldr r1, =__text_tcm_start__ + ldr r2, =__text_tcm_end__ + bl memory_copy + ldr r0, =__rodata_tcm_load_start__ + ldr r1, =__rodata_tcm_start__ + ldr r2, =__rodata_tcm_end__ + bl memory_copy +#endif /* #ifdef INITIALIZE_TCM_SECTIONS */ + + /* Zero the bss. */ + ldr r0, =__bss_start__ + ldr r1, =__bss_end__ + movs r2, #0 + bl memory_set + ldr r0, =__tbss_start__ + ldr r1, =__tbss_end__ + movs r2, #0 + bl memory_set +#ifdef INITIALIZE_SECONDARY_SECTIONS + ldr r0, =__bss2_start__ + ldr r1, =__bss2_end__ + mov r2, #0 + bl memory_set +#endif /* #ifdef INITIALIZE_SECONDARY_SECTIONS */ +#ifdef INITIALIZE_TCM_SECTIONS + ldr r0, =__bss_tcm_start__ + ldr r1, =__bss_tcm_end__ + mov r2, #0 + bl memory_set +#endif /* #ifdef INITIALIZE_TCM_SECTIONS */ + + /* Initialize the heap */ + ldr r0, = __heap_start__ + ldr r1, = __heap_end__ + subs r1, r1, r0 + cmp r1, #8 + blt 1f + movs r2, #0 + str r2, [r0] + adds r0, r0, #4 + str r1, [r0] +1: + +#ifdef INITIALIZE_USER_SECTIONS + ldr r2, =InitializeUserMemorySections + blx r2 +#endif + + /* Call constructors */ + ldr r0, =__ctors_start__ + ldr r1, =__ctors_end__ +ctor_loop: + cmp r0, r1 + beq ctor_end + ldr r2, [r0] + adds r0, #4 + push {r0-r1} + blx r2 + pop {r0-r1} + b ctor_loop +ctor_end: + + /* Setup initial call frame */ + movs r0, #0 + mov lr, r0 + mov r12, sp + + .type start, function +start: + /* Jump to application entry point */ +#ifdef FULL_LIBRARY + movs r0, #ARGSSPACE + ldr r1, =args + ldr r2, =debug_getargs + blx r2 + ldr r1, =args +#else + movs r0, #0 + movs r1, #0 +#endif + ldr r2, =APP_ENTRY_POINT + blx r2 + + .thumb_func +exit: +#ifdef FULL_LIBRARY + mov r5, r0 // save the exit parameter/return result + + /* Call destructors */ + ldr r0, =__dtors_start__ + ldr r1, =__dtors_end__ +dtor_loop: + cmp r0, r1 + beq dtor_end + ldr r2, [r0] + add r0, #4 + push {r0-r1} + blx r2 + pop {r0-r1} + b dtor_loop +dtor_end: + + /* Call atexit functions */ + ldr r2, =_execute_at_exit_fns + blx r2 + + /* Call debug_exit with return result/exit parameter */ + mov r0, r5 + ldr r2, =debug_exit + blx r2 +#endif + + /* Returned from application entry point, loop forever. */ +exit_loop: + b exit_loop + + .thumb_func +memory_copy: + cmp r0, r1 + beq 2f + subs r2, r2, r1 + beq 2f +1: + ldrb r3, [r0] + adds r0, r0, #1 + strb r3, [r1] + adds r1, r1, #1 + subs r2, r2, #1 + bne 1b +2: + bx lr + + .thumb_func +memory_set: + cmp r0, r1 + beq 1f + strb r2, [r0] + adds r0, r0, #1 + b memory_set +1: + bx lr + + // default C/C++ library helpers + +.macro HELPER helper_name + .section .text.\helper_name, "ax", %progbits + .balign 2 + .global \helper_name + .weak \helper_name +\helper_name: + .thumb_func +.endm + +.macro JUMPTO name +#if defined(__thumb__) && !defined(__thumb2__) + mov r12, r0 + ldr r0, =\name + push {r0} + mov r0, r12 + pop {pc} +#else + b \name +#endif +.endm + +HELPER __aeabi_read_tp + ldr r0, =__tbss_start__-8 + bx lr +HELPER abort + b . +HELPER __assert + b . +HELPER __aeabi_assert + b . +HELPER __sync_synchronize + bx lr +HELPER __getchar + JUMPTO debug_getchar +HELPER __putchar + JUMPTO debug_putchar +HELPER __open + JUMPTO debug_fopen +HELPER __close + JUMPTO debug_fclose +HELPER __write + mov r3, r0 + mov r0, r1 + movs r1, #1 + JUMPTO debug_fwrite +HELPER __read + mov r3, r0 + mov r0, r1 + movs r1, #1 + JUMPTO debug_fread +HELPER __seek + push {r4, lr} + mov r4, r0 + bl debug_fseek + cmp r0, #0 + bne 1f + mov r0, r4 + bl debug_ftell + pop {r4, pc} +1: + ldr r0, =-1 + pop {r4, pc} + // char __user_locale_name_buffer[]; + .section .bss.__user_locale_name_buffer, "aw", %nobits + .global __user_locale_name_buffer + .weak __user_locale_name_buffer + __user_locale_name_buffer: + .word 0x0 + +#ifdef FULL_LIBRARY + .bss +args: + .space ARGSSPACE +#endif + + /* Setup attibutes of stack and heap sections so they don't take up room in the elf file */ + .section .stack, "wa", %nobits + .section .stack_process, "wa", %nobits + .section .heap, "wa", %nobits + diff --git a/examples/device/device_virtual_com/segger/LPC4300_Startup.s b/examples/device/cdc_msc_hid/ses/lpc40xx/LPC4000_Startup.s index 3df2ad963..03bf54def 100644 --- a/examples/device/device_virtual_com/segger/LPC4300_Startup.s +++ b/examples/device/cdc_msc_hid/ses/lpc40xx/LPC4000_Startup.s @@ -67,8 +67,7 @@ Reset_Handler: #ifndef NO_STACK_INIT /* Initialise main stack */ ldr r0, =STACK_INIT_VAL - ldr r1, =0x7 - bics r0, r1 + bic r0, #0x7 mov sp, r0 #endif @@ -76,6 +75,9 @@ Reset_Handler: /* Initialise system */ ldr r0, =SystemInit blx r0 + .pushsection .init_array, "aw", %init_array + .word SystemCoreClockUpdate + .popsection #endif #ifdef MEMORY_INIT diff --git a/examples/device/cdc_msc_hid/ses/lpc40xx/LPC4000_Target.js b/examples/device/cdc_msc_hid/ses/lpc40xx/LPC4000_Target.js new file mode 100644 index 000000000..20560af43 --- /dev/null +++ b/examples/device/cdc_msc_hid/ses/lpc40xx/LPC4000_Target.js @@ -0,0 +1,19 @@ +/***************************************************************************** + * SEGGER Microcontroller GmbH & Co. KG * + * Solutions for real time microcontroller applications * + ***************************************************************************** + * * + * (c) 2017 SEGGER Microcontroller GmbH & Co. KG * + * * + * Internet: www.segger.com Support: [email protected] * + * * + *****************************************************************************/ + +function Reset() { + TargetInterface.resetAndStop(); +} + +function EnableTrace(traceInterfaceType) { + // TODO: Enable trace +} + diff --git a/examples/device/cdc_msc_hid/ses/lpc40xx/LPC4088FBD208_MemoryMap.xml b/examples/device/cdc_msc_hid/ses/lpc40xx/LPC4088FBD208_MemoryMap.xml new file mode 100644 index 000000000..9b8f2d9b4 --- /dev/null +++ b/examples/device/cdc_msc_hid/ses/lpc40xx/LPC4088FBD208_MemoryMap.xml @@ -0,0 +1,6 @@ +<!DOCTYPE Board_Memory_Definition_File> +<root name="LPC4088FBD208"> + <MemorySegment name="FLASH" start="0x00000000" size="0x00080000" access="ReadOnly" /> + <MemorySegment name="RAM" start="0x10000000" size="0x00010000" access="Read/Write" /> + <MemorySegment name="RAM2" start="0x20000000" size="0x00008000" access="Read/Write" /> +</root> diff --git a/examples/device/cdc_msc_hid/ses/lpc40xx/LPC408x_7x_Registers.xml b/examples/device/cdc_msc_hid/ses/lpc40xx/LPC408x_7x_Registers.xml new file mode 100644 index 000000000..4a4c08179 --- /dev/null +++ b/examples/device/cdc_msc_hid/ses/lpc40xx/LPC408x_7x_Registers.xml @@ -0,0 +1,18992 @@ +<!DOCTYPE Register_Definition_File> +<Processor name="LPC408x_7x" description="LPC408x/7x M4"> + <RegisterGroup name="FLASHCTRL" start="0x00200000" description="EEPROM/flash"> + <Register start="+0x020" size="4" name="FMSSTART" access="Read/Write" description="Signature start address register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="17" name="START" description="Signature generation start address (corresponds to AHB byte address bits[20:4])." /> + <BitField start="17" size="15" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x024" size="4" name="FMSSTOP" access="Read/Write" description="Signature stop-address register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="17" name="STOP" description="BIST stop address divided by 16 (corresponds to AHB byte address [20:4])." /> + <BitField start="17" size="1" name="SIG_START" description="Start control bit for signature generation."> + <Enum name="STOP" start="0" description="Signature generation is stopped" /> + <Enum name="START" start="1" description="Initiate signature generation" /> + </BitField> + <BitField start="18" size="14" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x02C" size="4" name="FMSW0" access="ReadOnly" description="128-bit signature Word 0" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="SW0_31_0" description="Word 0 of 128-bit signature (bits 31 to 0)." /> + </Register> + <Register start="+0x030" size="4" name="FMSW1" access="ReadOnly" description="128-bit signature Word 1" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="SW1_63_32" description="Word 1 of 128-bit signature (bits 63 to 32)." /> + </Register> + <Register start="+0x034" size="4" name="FMSW2" access="ReadOnly" description="128-bit signature Word 2" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="SW2_95_64" description="Word 2 of 128-bit signature (bits 95 to 64)." /> + </Register> + <Register start="+0x038" size="4" name="FMSW3" access="ReadOnly" description="128-bit signature Word 3" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="SW3_127_96" description="Word 3 of 128-bit signature (bits 127 to 96)." /> + </Register> + <Register start="+0x080" size="4" name="EECMD" access="Read/Write" description="EEPROM command register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="CMD" description="Command. 000: 8-bit read 001: 16-bit read 010: 32-bit read 011: 8-bit write 100: 16-bit write 101: 32-bit write 110: erase/program page 111: reserved" /> + <BitField start="3" size="1" name="RDPREFETCH" description="Read data prefetch bit. 0: do not prefetch next read data as result of reading from the read data register. 1: prefetch read data as result of reading from the read data register. When this bit is set multiple consecutive data elements can be read without the need of programming new address values in the address register. The address post-increment and the automatic read data prefetch (if enabled) allow only reading from the read data register to be done to read the data." /> + <BitField start="4" size="28" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x084" size="4" name="EEADDR" access="Read/Write" description="EEPROM address register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="12" name="ADDR" description="EEPROM Address. Lower 6 bits are don't care." /> + <BitField start="12" size="20" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x088" size="4" name="EEWDATA" access="WriteOnly" description="EEPROM write data register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="WDATA" description="Write data. In case of: 8-bit write operations: bits [7:0] must contain valid write data. 16-bit write operations: bits [15:0] must contain valid write data. 32-bit write operations: bits [31:0] must contain valid write data." /> + </Register> + <Register start="+0x08C" size="4" name="EERDATA" access="ReadOnly" description="EEPROM read data register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="RDATA" description="Read data. In case of: 8-bit read operations: bits [7:0] contain read data, others are zero. 16-bit read operations: bits [15:0] contain read data, others are zero. 32-bit read operations: bits [31:0] contain read data." /> + </Register> + <Register start="+0x090" size="4" name="EEWSTATE" access="Read/Write" description="EEPROM wait state register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="PHASE3" description="Wait states 3 (minus 1 encoded). The number of system clock periods required to give a minimum time of 15 ns." /> + <BitField start="8" size="8" name="PHASE2" description="Wait states 2 (minus 1 encoded). The number of system clock periods required to give a minimum time of 55 ns." /> + <BitField start="16" size="8" name="PHASE1" description="Wait states 1 (minus 1 encoded). The number of system clock periods required to give a minimum time of 35 ns." /> + <BitField start="24" size="8" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x094" size="4" name="EECLKDIV" access="Read/Write" description="EEPROM clock divider register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="16" name="CLKDIV" description="Division factor (minus 1 encoded)." /> + <BitField start="16" size="16" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x098" size="4" name="EEPWRDWN" access="Read/Write" description="EEPROM power-down register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="PWRDWN" description="Power down mode bit. 0: not in power down mode. 1: power down mode (this will put all EEPROM devices in power down)." /> + <BitField start="1" size="31" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0xFE0" size="4" name="STAT" access="ReadOnly" description="Signature generation status register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + <BitField start="2" size="1" name="SIG_DONE" description="When 1, a previously started signature generation has completed. See FMSTATCLR register description for clearing this flag." /> + <BitField start="3" size="23" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + <BitField start="26" size="1" name="END_OF_RDWR" description="EEPROM read/write operation finished interrupt status bit. Bit is: - set when this operation has finished OR when 1 is written in the corresponding bit of the EEINTSTATSET register. - cleared when 1 is written to the corresponding bit of the EEINTSTATCLR register." /> + <BitField start="27" size="1" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + <BitField start="28" size="1" name="END_OF_PROG1" description="EEPROM program operation finished interrupt status bit. Bit is: - set when this operation has finished OR when 1 is written to the corresponding bit of the EEINTSTATSET register. - cleared when 1 is written to the corresponding bit of the EEINTSTATCLR register." /> + <BitField start="29" size="3" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0xFE4" size="4" name="INTEN" access="ReadOnly" description="EEPROM interrupt enable" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="26" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + <BitField start="26" size="1" name="EE_RW_DONE" description="EEPROM read/write operation finished interrupt enable bit. Bit is: - set when 1 is written to the corresponding bit of the EEINTENSET register. - cleared when 1 is written to the corresponding bit of the EEINTENCLR register." /> + <BitField start="27" size="1" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + <BitField start="28" size="1" name="EE_PROG_DONE" description="EEPROM program operation finished interrupt enable bit. Bit is: - set when 1 is written in the corresponding bit of the EEINTENSET register. - cleared when 1 is written to the corresponding bit of the EEINTENCLR register." /> + <BitField start="29" size="3" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0xFE8" size="4" name="STATCLR" access="WriteOnly" description="Signature generation status clear register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="2" size="1" name="SIG_DONE_CLR" description="Writing a 1 to this bits clears the signature generation completion flag (SIG_DONE) in the FMSTAT register." /> + <BitField start="3" size="23" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="26" size="1" name="RDWR_CLR_ST" description="Clear read/write operation finished interrupt status bit (EEPROM). 0 leave corresponding bit unchanged. 1 clear corresponding bit." /> + <BitField start="27" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="28" size="1" name="PROG1_CLR_ST" description="Clear program operation finished interrupt status bit for EEPROM device 1. 0 leave corresponding bit unchanged. 1 clear corresponding bit." /> + <BitField start="29" size="3" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0xFD8" size="4" name="ENCLR" access="WriteOnly" description="EEPROM interrupt enable clear" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="26" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="26" size="1" name="RDWR_CLR_EN" description="Clear read/write operation finished interrupt enable bit (EEPROM). 0: leave corresponding bit unchanged. 1: clear corresponding bit." /> + <BitField start="27" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="28" size="1" name="PROG1_CLR_EN" description="Clear program operation finished interrupt enable bit for EEPROM device 1. 0: leave corresponding bit unchanged. 1: clear corresponding bit." /> + <BitField start="29" size="3" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0xFDC" size="4" name="ENSET" access="WriteOnly" description="EEPROM interrupt enable set" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="26" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="26" size="1" name="RDWR_SET_EN" description="Set read/write operation finished interrupt enable bit (EEPROM). 0: leave corresponding bit unchanged. 1: set corresponding bit." /> + <BitField start="27" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="28" size="1" name="PROG1_SET_EN" description="Set program operation finished interrupt enable bit for EEPROM device 1. 0: leave corresponding bit unchanged. 1: set corresponding bit." /> + <BitField start="29" size="3" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + </RegisterGroup> + <RegisterGroup name="GPDMA" start="0x20080000" description="General Purpose DMA controller Modification"> + <Register start="+0x000" size="4" name="INTSTAT" access="ReadOnly" description="DMA Interrupt Status Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="INTSTAT0" description="Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request." /> + <BitField start="1" size="1" name="INTSTAT1" description="Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request." /> + <BitField start="2" size="1" name="INTSTAT2" description="Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request." /> + <BitField start="3" size="1" name="INTSTAT3" description="Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request." /> + <BitField start="4" size="1" name="INTSTAT4" description="Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request." /> + <BitField start="5" size="1" name="INTSTAT5" description="Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request." /> + <BitField start="6" size="1" name="INTSTAT6" description="Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request." /> + <BitField start="7" size="1" name="INTSTAT7" description="Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x004" size="4" name="INTTCSTAT" access="ReadOnly" description="DMA Interrupt Terminal Count Request Status Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="INTTCSTAT0" description="Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." /> + <BitField start="1" size="1" name="INTTCSTAT1" description="Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." /> + <BitField start="2" size="1" name="INTTCSTAT2" description="Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." /> + <BitField start="3" size="1" name="INTTCSTAT3" description="Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." /> + <BitField start="4" size="1" name="INTTCSTAT4" description="Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." /> + <BitField start="5" size="1" name="INTTCSTAT5" description="Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." /> + <BitField start="6" size="1" name="INTTCSTAT6" description="Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." /> + <BitField start="7" size="1" name="INTTCSTAT7" description="Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x008" size="4" name="INTTCCLEAR" access="WriteOnly" description="DMA Interrupt Terminal Count Request Clear Register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="INTTCCLEAR0" description="Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt." /> + <BitField start="1" size="1" name="INTTCCLEAR1" description="Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt." /> + <BitField start="2" size="1" name="INTTCCLEAR2" description="Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt." /> + <BitField start="3" size="1" name="INTTCCLEAR3" description="Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt." /> + <BitField start="4" size="1" name="INTTCCLEAR4" description="Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt." /> + <BitField start="5" size="1" name="INTTCCLEAR5" description="Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt." /> + <BitField start="6" size="1" name="INTTCCLEAR6" description="Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt." /> + <BitField start="7" size="1" name="INTTCCLEAR7" description="Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x00C" size="4" name="INTERRSTAT" access="ReadOnly" description="DMA Interrupt Error Status Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="INTERRSTAT0" description="Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." /> + <BitField start="1" size="1" name="INTERRSTAT1" description="Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." /> + <BitField start="2" size="1" name="INTERRSTAT2" description="Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." /> + <BitField start="3" size="1" name="INTERRSTAT3" description="Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." /> + <BitField start="4" size="1" name="INTERRSTAT4" description="Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." /> + <BitField start="5" size="1" name="INTERRSTAT5" description="Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." /> + <BitField start="6" size="1" name="INTERRSTAT6" description="Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." /> + <BitField start="7" size="1" name="INTERRSTAT7" description="Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x010" size="4" name="INTERRCLR" access="WriteOnly" description="DMA Interrupt Error Clear Register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="INTERRCLR0" description="Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt." /> + <BitField start="1" size="1" name="INTERRCLR1" description="Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt." /> + <BitField start="2" size="1" name="INTERRCLR2" description="Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt." /> + <BitField start="3" size="1" name="INTERRCLR3" description="Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt." /> + <BitField start="4" size="1" name="INTERRCLR4" description="Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt." /> + <BitField start="5" size="1" name="INTERRCLR5" description="Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt." /> + <BitField start="6" size="1" name="INTERRCLR6" description="Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt." /> + <BitField start="7" size="1" name="INTERRCLR7" description="Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x014" size="4" name="RAWINTTCSTAT" access="ReadOnly" description="DMA Raw Interrupt Terminal Count Status Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RAWINTTCSTAT0" description="Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." /> + <BitField start="1" size="1" name="RAWINTTCSTAT1" description="Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." /> + <BitField start="2" size="1" name="RAWINTTCSTAT2" description="Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." /> + <BitField start="3" size="1" name="RAWINTTCSTAT3" description="Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." /> + <BitField start="4" size="1" name="RAWINTTCSTAT4" description="Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." /> + <BitField start="5" size="1" name="RAWINTTCSTAT5" description="Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." /> + <BitField start="6" size="1" name="RAWINTTCSTAT6" description="Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." /> + <BitField start="7" size="1" name="RAWINTTCSTAT7" description="Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x018" size="4" name="RAWINTERRSTAT" access="ReadOnly" description="DMA Raw Error Interrupt Status Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RAWINTERRSTAT0" description="Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." /> + <BitField start="1" size="1" name="RAWINTERRSTAT1" description="Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." /> + <BitField start="2" size="1" name="RAWINTERRSTAT2" description="Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." /> + <BitField start="3" size="1" name="RAWINTERRSTAT3" description="Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." /> + <BitField start="4" size="1" name="RAWINTERRSTAT4" description="Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." /> + <BitField start="5" size="1" name="RAWINTERRSTAT5" description="Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." /> + <BitField start="6" size="1" name="RAWINTERRSTAT6" description="Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." /> + <BitField start="7" size="1" name="RAWINTERRSTAT7" description="Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x01C" size="4" name="ENBLDCHNS" access="ReadOnly" description="DMA Enabled Channel Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="ENABLEDCHANNELS0" description="Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled." /> + <BitField start="1" size="1" name="ENABLEDCHANNELS1" description="Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled." /> + <BitField start="2" size="1" name="ENABLEDCHANNELS2" description="Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled." /> + <BitField start="3" size="1" name="ENABLEDCHANNELS3" description="Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled." /> + <BitField start="4" size="1" name="ENABLEDCHANNELS4" description="Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled." /> + <BitField start="5" size="1" name="ENABLEDCHANNELS5" description="Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled." /> + <BitField start="6" size="1" name="ENABLEDCHANNELS6" description="Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled." /> + <BitField start="7" size="1" name="ENABLEDCHANNELS7" description="Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x020" size="4" name="SOFTBREQ" access="Read/Write" description="DMA Software Burst Request Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="SOFTBREQ0" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." /> + <BitField start="1" size="1" name="SOFTBREQ1" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." /> + <BitField start="2" size="1" name="SOFTBREQ2" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." /> + <BitField start="3" size="1" name="SOFTBREQ3" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." /> + <BitField start="4" size="1" name="SOFTBREQ4" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." /> + <BitField start="5" size="1" name="SOFTBREQ5" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." /> + <BitField start="6" size="1" name="SOFTBREQ6" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." /> + <BitField start="7" size="1" name="SOFTBREQ7" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." /> + <BitField start="8" size="1" name="SOFTBREQ8" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." /> + <BitField start="9" size="1" name="SOFTBREQ9" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." /> + <BitField start="10" size="1" name="SOFTBREQ10" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." /> + <BitField start="11" size="1" name="SOFTBREQ11" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." /> + <BitField start="12" size="1" name="SOFTBREQ12" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." /> + <BitField start="13" size="1" name="SOFTBREQ13" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." /> + <BitField start="14" size="1" name="SOFTBREQ14" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." /> + <BitField start="15" size="1" name="SOFTBREQ15" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." /> + <BitField start="16" size="16" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x024" size="4" name="SOFTSREQ" access="Read/Write" description="DMA Software Single Request Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="SOFTSREQ0" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." /> + <BitField start="1" size="1" name="SOFTSREQ1" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." /> + <BitField start="2" size="1" name="SOFTSREQ2" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." /> + <BitField start="3" size="1" name="SOFTSREQ3" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." /> + <BitField start="4" size="1" name="SOFTSREQ4" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." /> + <BitField start="5" size="1" name="SOFTSREQ5" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." /> + <BitField start="6" size="1" name="SOFTSREQ6" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." /> + <BitField start="7" size="1" name="SOFTSREQ7" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." /> + <BitField start="8" size="1" name="SOFTSREQ8" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." /> + <BitField start="9" size="1" name="SOFTSREQ9" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." /> + <BitField start="10" size="1" name="SOFTSREQ10" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." /> + <BitField start="11" size="1" name="SOFTSREQ11" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." /> + <BitField start="12" size="1" name="SOFTSREQ12" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." /> + <BitField start="13" size="1" name="SOFTSREQ13" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." /> + <BitField start="14" size="1" name="SOFTSREQ14" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." /> + <BitField start="15" size="1" name="SOFTSREQ15" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." /> + <BitField start="16" size="16" name="RESERVED" description="Reserved. Read undefined. Write reserved bits as zero." /> + </Register> + <Register start="+0x028" size="4" name="SOFTLBREQ" access="Read/Write" description="DMA Software Last Burst Request Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="SOFTLBREQ0" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." /> + <BitField start="1" size="1" name="SOFTLBREQ1" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." /> + <BitField start="2" size="1" name="SOFTLBREQ2" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." /> + <BitField start="3" size="1" name="SOFTLBREQ3" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." /> + <BitField start="4" size="1" name="SOFTLBREQ4" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." /> + <BitField start="5" size="1" name="SOFTLBREQ5" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." /> + <BitField start="6" size="1" name="SOFTLBREQ6" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." /> + <BitField start="7" size="1" name="SOFTLBREQ7" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." /> + <BitField start="8" size="1" name="SOFTLBREQ8" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." /> + <BitField start="9" size="1" name="SOFTLBREQ9" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." /> + <BitField start="10" size="1" name="SOFTLBREQ10" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." /> + <BitField start="11" size="1" name="SOFTLBREQ11" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." /> + <BitField start="12" size="1" name="SOFTLBREQ12" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." /> + <BitField start="13" size="1" name="SOFTLBREQ13" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." /> + <BitField start="14" size="1" name="SOFTLBREQ14" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." /> + <BitField start="15" size="1" name="SOFTLBREQ15" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." /> + <BitField start="16" size="16" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x02C" size="4" name="SOFTLSREQ" access="Read/Write" description="DMA Software Last Single Request Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="SOFTLSREQ0" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." /> + <BitField start="1" size="1" name="SOFTLSREQ1" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." /> + <BitField start="2" size="1" name="SOFTLSREQ2" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." /> + <BitField start="3" size="1" name="SOFTLSREQ3" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." /> + <BitField start="4" size="1" name="SOFTLSREQ4" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." /> + <BitField start="5" size="1" name="SOFTLSREQ5" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." /> + <BitField start="6" size="1" name="SOFTLSREQ6" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." /> + <BitField start="7" size="1" name="SOFTLSREQ7" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." /> + <BitField start="8" size="1" name="SOFTLSREQ8" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." /> + <BitField start="9" size="1" name="SOFTLSREQ9" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." /> + <BitField start="10" size="1" name="SOFTLSREQ10" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." /> + <BitField start="11" size="1" name="SOFTLSREQ11" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." /> + <BitField start="12" size="1" name="SOFTLSREQ12" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." /> + <BitField start="13" size="1" name="SOFTLSREQ13" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." /> + <BitField start="14" size="1" name="SOFTLSREQ14" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." /> + <BitField start="15" size="1" name="SOFTLSREQ15" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." /> + <BitField start="16" size="16" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x030" size="4" name="CONFIG" access="Read/Write" description="DMA Configuration Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="E" description="DMA Controller enable: 0 = disabled (default). Disabling the DMA Controller reduces power consumption. 1 = enabled." /> + <BitField start="1" size="1" name="M" description="AHB Master endianness configuration: 0 = little-endian mode (default). 1 = big-endian mode." /> + <BitField start="2" size="30" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x034" size="4" name="SYNC" access="Read/Write" description="DMA Synchronization Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="DMACSYNC0" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled." /> + <BitField start="1" size="1" name="DMACSYNC1" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled." /> + <BitField start="2" size="1" name="DMACSYNC2" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled." /> + <BitField start="3" size="1" name="DMACSYNC3" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled." /> + <BitField start="4" size="1" name="DMACSYNC4" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled." /> + <BitField start="5" size="1" name="DMACSYNC5" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled." /> + <BitField start="6" size="1" name="DMACSYNC6" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled." /> + <BitField start="7" size="1" name="DMACSYNC7" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled." /> + <BitField start="8" size="1" name="DMACSYNC8" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled." /> + <BitField start="9" size="1" name="DMACSYNC9" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled." /> + <BitField start="10" size="1" name="DMACSYNC10" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled." /> + <BitField start="11" size="1" name="DMACSYNC11" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled." /> + <BitField start="12" size="1" name="DMACSYNC12" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled." /> + <BitField start="13" size="1" name="DMACSYNC13" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled." /> + <BitField start="14" size="1" name="DMACSYNC14" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled." /> + <BitField start="15" size="1" name="DMACSYNC15" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled." /> + <BitField start="16" size="16" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x100+0" size="4" name="SRCADDR0" access="Read/Write" description="DMA Channel 0 Source Address Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="SRCADDR" description="DMA source address. Reading this register will return the current source address." /> + </Register> + <Register start="+0x100+32" size="4" name="SRCADDR1" access="Read/Write" description="DMA Channel 0 Source Address Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="SRCADDR" description="DMA source address. Reading this register will return the current source address." /> + </Register> + <Register start="+0x100+64" size="4" name="SRCADDR2" access="Read/Write" description="DMA Channel 0 Source Address Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="SRCADDR" description="DMA source address. Reading this register will return the current source address." /> + </Register> + <Register start="+0x100+96" size="4" name="SRCADDR3" access="Read/Write" description="DMA Channel 0 Source Address Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="SRCADDR" description="DMA source address. Reading this register will return the current source address." /> + </Register> + <Register start="+0x100+128" size="4" name="SRCADDR4" access="Read/Write" description="DMA Channel 0 Source Address Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="SRCADDR" description="DMA source address. Reading this register will return the current source address." /> + </Register> + <Register start="+0x100+160" size="4" name="SRCADDR5" access="Read/Write" description="DMA Channel 0 Source Address Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="SRCADDR" description="DMA source address. Reading this register will return the current source address." /> + </Register> + <Register start="+0x100+192" size="4" name="SRCADDR6" access="Read/Write" description="DMA Channel 0 Source Address Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="SRCADDR" description="DMA source address. Reading this register will return the current source address." /> + </Register> + <Register start="+0x100+224" size="4" name="SRCADDR7" access="Read/Write" description="DMA Channel 0 Source Address Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="SRCADDR" description="DMA source address. Reading this register will return the current source address." /> + </Register> + <Register start="+0x104+0" size="4" name="DESTADDR0" access="Read/Write" description="DMA Channel 0 Destination Address Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="DESTADDR" description="DMA Destination address. Reading this register will return the current destination address." /> + </Register> + <Register start="+0x104+32" size="4" name="DESTADDR1" access="Read/Write" description="DMA Channel 0 Destination Address Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="DESTADDR" description="DMA Destination address. Reading this register will return the current destination address." /> + </Register> + <Register start="+0x104+64" size="4" name="DESTADDR2" access="Read/Write" description="DMA Channel 0 Destination Address Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="DESTADDR" description="DMA Destination address. Reading this register will return the current destination address." /> + </Register> + <Register start="+0x104+96" size="4" name="DESTADDR3" access="Read/Write" description="DMA Channel 0 Destination Address Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="DESTADDR" description="DMA Destination address. Reading this register will return the current destination address." /> + </Register> + <Register start="+0x104+128" size="4" name="DESTADDR4" access="Read/Write" description="DMA Channel 0 Destination Address Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="DESTADDR" description="DMA Destination address. Reading this register will return the current destination address." /> + </Register> + <Register start="+0x104+160" size="4" name="DESTADDR5" access="Read/Write" description="DMA Channel 0 Destination Address Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="DESTADDR" description="DMA Destination address. Reading this register will return the current destination address." /> + </Register> + <Register start="+0x104+192" size="4" name="DESTADDR6" access="Read/Write" description="DMA Channel 0 Destination Address Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="DESTADDR" description="DMA Destination address. Reading this register will return the current destination address." /> + </Register> + <Register start="+0x104+224" size="4" name="DESTADDR7" access="Read/Write" description="DMA Channel 0 Destination Address Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="DESTADDR" description="DMA Destination address. Reading this register will return the current destination address." /> + </Register> + <Register start="+0x108+0" size="4" name="LLI0" access="Read/Write" description="DMA Channel 0 Linked List Item Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="RESERVED" description="Reserved, and must be written as 0." /> + <BitField start="2" size="30" name="LLI" description="Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0." /> + </Register> + <Register start="+0x108+32" size="4" name="LLI1" access="Read/Write" description="DMA Channel 0 Linked List Item Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="RESERVED" description="Reserved, and must be written as 0." /> + <BitField start="2" size="30" name="LLI" description="Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0." /> + </Register> + <Register start="+0x108+64" size="4" name="LLI2" access="Read/Write" description="DMA Channel 0 Linked List Item Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="RESERVED" description="Reserved, and must be written as 0." /> + <BitField start="2" size="30" name="LLI" description="Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0." /> + </Register> + <Register start="+0x108+96" size="4" name="LLI3" access="Read/Write" description="DMA Channel 0 Linked List Item Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="RESERVED" description="Reserved, and must be written as 0." /> + <BitField start="2" size="30" name="LLI" description="Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0." /> + </Register> + <Register start="+0x108+128" size="4" name="LLI4" access="Read/Write" description="DMA Channel 0 Linked List Item Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="RESERVED" description="Reserved, and must be written as 0." /> + <BitField start="2" size="30" name="LLI" description="Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0." /> + </Register> + <Register start="+0x108+160" size="4" name="LLI5" access="Read/Write" description="DMA Channel 0 Linked List Item Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="RESERVED" description="Reserved, and must be written as 0." /> + <BitField start="2" size="30" name="LLI" description="Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0." /> + </Register> + <Register start="+0x108+192" size="4" name="LLI6" access="Read/Write" description="DMA Channel 0 Linked List Item Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="RESERVED" description="Reserved, and must be written as 0." /> + <BitField start="2" size="30" name="LLI" description="Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0." /> + </Register> + <Register start="+0x108+224" size="4" name="LLI7" access="Read/Write" description="DMA Channel 0 Linked List Item Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="RESERVED" description="Reserved, and must be written as 0." /> + <BitField start="2" size="30" name="LLI" description="Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0." /> + </Register> + <Register start="+0x10C+0" size="4" name="CONTROL0" access="Read/Write" description="DMA Channel 0 Control Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="12" name="TRANSFERSIZE" description="Transfer size. This field sets the size of the transfer when the DMA controller is the flow controller, in which case the value must be set before the channel is enabled. Transfer size is updated as data transfers are completed. A read from this field indicates the number of transfers completed on the destination bus. Reading the register when the channel is active does not give useful information because by the time that the software has processed the value read, the channel might have progressed. It is intended to be used only when a channel is enabled and then disabled. The transfer size value is not used if a peripheral is the flow controller." /> + <BitField start="12" size="3" name="SBSIZE" description="Source burst size. Indicates the number of transfers that make up a source burst. This value must be set to the burst size of the source peripheral, or if the source is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the source peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256" /> + <BitField start="15" size="3" name="DBSIZE" description="Destination burst size. Indicates the number of transfers that make up a destination burst transfer request. This value must be set to the burst size of the destination peripheral or, if the destination is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the destination peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256" /> + <BitField start="18" size="3" name="SWIDTH" description="Source transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved" /> + <BitField start="21" size="3" name="DWIDTH" description="Destination transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved" /> + <BitField start="24" size="2" name="RESERVED" description="Reserved, and must be written as 0." /> + <BitField start="26" size="1" name="SI" description="Source increment: 0 - the source address is not incremented after each transfer. 1 - the source address is incremented after each transfer." /> + <BitField start="27" size="1" name="DI" description="Destination increment: 0 - the destination address is not incremented after each transfer. 1 - the destination address is incremented after each transfer." /> + <BitField start="28" size="1" name="PROT1" description="This is provided to the peripheral during a DMA bus access and indicates that the access is in user mode or privileged mode. This information is not used in the LPC178x/177x. 0 - access is in user mode. 1 - access is in privileged mode." /> + <BitField start="29" size="1" name="PROT2" description="This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is bufferable or not bufferable. This information is not used in the LPC178x/177x. 0 - access is not bufferable. 1 - access is bufferable." /> + <BitField start="30" size="1" name="PROT3" description="This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is cacheable or not cacheable. This information is not used in the LPC178x/177x. 0 - access is not cacheable. 1 - access is cacheable." /> + <BitField start="31" size="1" name="I" description="Terminal count interrupt enable bit. 0 - the terminal count interrupt is disabled. 1 - the terminal count interrupt is enabled." /> + </Register> + <Register start="+0x10C+32" size="4" name="CONTROL1" access="Read/Write" description="DMA Channel 0 Control Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="12" name="TRANSFERSIZE" description="Transfer size. This field sets the size of the transfer when the DMA controller is the flow controller, in which case the value must be set before the channel is enabled. Transfer size is updated as data transfers are completed. A read from this field indicates the number of transfers completed on the destination bus. Reading the register when the channel is active does not give useful information because by the time that the software has processed the value read, the channel might have progressed. It is intended to be used only when a channel is enabled and then disabled. The transfer size value is not used if a peripheral is the flow controller." /> + <BitField start="12" size="3" name="SBSIZE" description="Source burst size. Indicates the number of transfers that make up a source burst. This value must be set to the burst size of the source peripheral, or if the source is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the source peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256" /> + <BitField start="15" size="3" name="DBSIZE" description="Destination burst size. Indicates the number of transfers that make up a destination burst transfer request. This value must be set to the burst size of the destination peripheral or, if the destination is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the destination peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256" /> + <BitField start="18" size="3" name="SWIDTH" description="Source transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved" /> + <BitField start="21" size="3" name="DWIDTH" description="Destination transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved" /> + <BitField start="24" size="2" name="RESERVED" description="Reserved, and must be written as 0." /> + <BitField start="26" size="1" name="SI" description="Source increment: 0 - the source address is not incremented after each transfer. 1 - the source address is incremented after each transfer." /> + <BitField start="27" size="1" name="DI" description="Destination increment: 0 - the destination address is not incremented after each transfer. 1 - the destination address is incremented after each transfer." /> + <BitField start="28" size="1" name="PROT1" description="This is provided to the peripheral during a DMA bus access and indicates that the access is in user mode or privileged mode. This information is not used in the LPC178x/177x. 0 - access is in user mode. 1 - access is in privileged mode." /> + <BitField start="29" size="1" name="PROT2" description="This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is bufferable or not bufferable. This information is not used in the LPC178x/177x. 0 - access is not bufferable. 1 - access is bufferable." /> + <BitField start="30" size="1" name="PROT3" description="This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is cacheable or not cacheable. This information is not used in the LPC178x/177x. 0 - access is not cacheable. 1 - access is cacheable." /> + <BitField start="31" size="1" name="I" description="Terminal count interrupt enable bit. 0 - the terminal count interrupt is disabled. 1 - the terminal count interrupt is enabled." /> + </Register> + <Register start="+0x10C+64" size="4" name="CONTROL2" access="Read/Write" description="DMA Channel 0 Control Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="12" name="TRANSFERSIZE" description="Transfer size. This field sets the size of the transfer when the DMA controller is the flow controller, in which case the value must be set before the channel is enabled. Transfer size is updated as data transfers are completed. A read from this field indicates the number of transfers completed on the destination bus. Reading the register when the channel is active does not give useful information because by the time that the software has processed the value read, the channel might have progressed. It is intended to be used only when a channel is enabled and then disabled. The transfer size value is not used if a peripheral is the flow controller." /> + <BitField start="12" size="3" name="SBSIZE" description="Source burst size. Indicates the number of transfers that make up a source burst. This value must be set to the burst size of the source peripheral, or if the source is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the source peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256" /> + <BitField start="15" size="3" name="DBSIZE" description="Destination burst size. Indicates the number of transfers that make up a destination burst transfer request. This value must be set to the burst size of the destination peripheral or, if the destination is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the destination peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256" /> + <BitField start="18" size="3" name="SWIDTH" description="Source transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved" /> + <BitField start="21" size="3" name="DWIDTH" description="Destination transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved" /> + <BitField start="24" size="2" name="RESERVED" description="Reserved, and must be written as 0." /> + <BitField start="26" size="1" name="SI" description="Source increment: 0 - the source address is not incremented after each transfer. 1 - the source address is incremented after each transfer." /> + <BitField start="27" size="1" name="DI" description="Destination increment: 0 - the destination address is not incremented after each transfer. 1 - the destination address is incremented after each transfer." /> + <BitField start="28" size="1" name="PROT1" description="This is provided to the peripheral during a DMA bus access and indicates that the access is in user mode or privileged mode. This information is not used in the LPC178x/177x. 0 - access is in user mode. 1 - access is in privileged mode." /> + <BitField start="29" size="1" name="PROT2" description="This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is bufferable or not bufferable. This information is not used in the LPC178x/177x. 0 - access is not bufferable. 1 - access is bufferable." /> + <BitField start="30" size="1" name="PROT3" description="This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is cacheable or not cacheable. This information is not used in the LPC178x/177x. 0 - access is not cacheable. 1 - access is cacheable." /> + <BitField start="31" size="1" name="I" description="Terminal count interrupt enable bit. 0 - the terminal count interrupt is disabled. 1 - the terminal count interrupt is enabled." /> + </Register> + <Register start="+0x10C+96" size="4" name="CONTROL3" access="Read/Write" description="DMA Channel 0 Control Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="12" name="TRANSFERSIZE" description="Transfer size. This field sets the size of the transfer when the DMA controller is the flow controller, in which case the value must be set before the channel is enabled. Transfer size is updated as data transfers are completed. A read from this field indicates the number of transfers completed on the destination bus. Reading the register when the channel is active does not give useful information because by the time that the software has processed the value read, the channel might have progressed. It is intended to be used only when a channel is enabled and then disabled. The transfer size value is not used if a peripheral is the flow controller." /> + <BitField start="12" size="3" name="SBSIZE" description="Source burst size. Indicates the number of transfers that make up a source burst. This value must be set to the burst size of the source peripheral, or if the source is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the source peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256" /> + <BitField start="15" size="3" name="DBSIZE" description="Destination burst size. Indicates the number of transfers that make up a destination burst transfer request. This value must be set to the burst size of the destination peripheral or, if the destination is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the destination peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256" /> + <BitField start="18" size="3" name="SWIDTH" description="Source transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved" /> + <BitField start="21" size="3" name="DWIDTH" description="Destination transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved" /> + <BitField start="24" size="2" name="RESERVED" description="Reserved, and must be written as 0." /> + <BitField start="26" size="1" name="SI" description="Source increment: 0 - the source address is not incremented after each transfer. 1 - the source address is incremented after each transfer." /> + <BitField start="27" size="1" name="DI" description="Destination increment: 0 - the destination address is not incremented after each transfer. 1 - the destination address is incremented after each transfer." /> + <BitField start="28" size="1" name="PROT1" description="This is provided to the peripheral during a DMA bus access and indicates that the access is in user mode or privileged mode. This information is not used in the LPC178x/177x. 0 - access is in user mode. 1 - access is in privileged mode." /> + <BitField start="29" size="1" name="PROT2" description="This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is bufferable or not bufferable. This information is not used in the LPC178x/177x. 0 - access is not bufferable. 1 - access is bufferable." /> + <BitField start="30" size="1" name="PROT3" description="This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is cacheable or not cacheable. This information is not used in the LPC178x/177x. 0 - access is not cacheable. 1 - access is cacheable." /> + <BitField start="31" size="1" name="I" description="Terminal count interrupt enable bit. 0 - the terminal count interrupt is disabled. 1 - the terminal count interrupt is enabled." /> + </Register> + <Register start="+0x10C+128" size="4" name="CONTROL4" access="Read/Write" description="DMA Channel 0 Control Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="12" name="TRANSFERSIZE" description="Transfer size. This field sets the size of the transfer when the DMA controller is the flow controller, in which case the value must be set before the channel is enabled. Transfer size is updated as data transfers are completed. A read from this field indicates the number of transfers completed on the destination bus. Reading the register when the channel is active does not give useful information because by the time that the software has processed the value read, the channel might have progressed. It is intended to be used only when a channel is enabled and then disabled. The transfer size value is not used if a peripheral is the flow controller." /> + <BitField start="12" size="3" name="SBSIZE" description="Source burst size. Indicates the number of transfers that make up a source burst. This value must be set to the burst size of the source peripheral, or if the source is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the source peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256" /> + <BitField start="15" size="3" name="DBSIZE" description="Destination burst size. Indicates the number of transfers that make up a destination burst transfer request. This value must be set to the burst size of the destination peripheral or, if the destination is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the destination peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256" /> + <BitField start="18" size="3" name="SWIDTH" description="Source transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved" /> + <BitField start="21" size="3" name="DWIDTH" description="Destination transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved" /> + <BitField start="24" size="2" name="RESERVED" description="Reserved, and must be written as 0." /> + <BitField start="26" size="1" name="SI" description="Source increment: 0 - the source address is not incremented after each transfer. 1 - the source address is incremented after each transfer." /> + <BitField start="27" size="1" name="DI" description="Destination increment: 0 - the destination address is not incremented after each transfer. 1 - the destination address is incremented after each transfer." /> + <BitField start="28" size="1" name="PROT1" description="This is provided to the peripheral during a DMA bus access and indicates that the access is in user mode or privileged mode. This information is not used in the LPC178x/177x. 0 - access is in user mode. 1 - access is in privileged mode." /> + <BitField start="29" size="1" name="PROT2" description="This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is bufferable or not bufferable. This information is not used in the LPC178x/177x. 0 - access is not bufferable. 1 - access is bufferable." /> + <BitField start="30" size="1" name="PROT3" description="This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is cacheable or not cacheable. This information is not used in the LPC178x/177x. 0 - access is not cacheable. 1 - access is cacheable." /> + <BitField start="31" size="1" name="I" description="Terminal count interrupt enable bit. 0 - the terminal count interrupt is disabled. 1 - the terminal count interrupt is enabled." /> + </Register> + <Register start="+0x10C+160" size="4" name="CONTROL5" access="Read/Write" description="DMA Channel 0 Control Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="12" name="TRANSFERSIZE" description="Transfer size. This field sets the size of the transfer when the DMA controller is the flow controller, in which case the value must be set before the channel is enabled. Transfer size is updated as data transfers are completed. A read from this field indicates the number of transfers completed on the destination bus. Reading the register when the channel is active does not give useful information because by the time that the software has processed the value read, the channel might have progressed. It is intended to be used only when a channel is enabled and then disabled. The transfer size value is not used if a peripheral is the flow controller." /> + <BitField start="12" size="3" name="SBSIZE" description="Source burst size. Indicates the number of transfers that make up a source burst. This value must be set to the burst size of the source peripheral, or if the source is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the source peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256" /> + <BitField start="15" size="3" name="DBSIZE" description="Destination burst size. Indicates the number of transfers that make up a destination burst transfer request. This value must be set to the burst size of the destination peripheral or, if the destination is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the destination peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256" /> + <BitField start="18" size="3" name="SWIDTH" description="Source transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved" /> + <BitField start="21" size="3" name="DWIDTH" description="Destination transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved" /> + <BitField start="24" size="2" name="RESERVED" description="Reserved, and must be written as 0." /> + <BitField start="26" size="1" name="SI" description="Source increment: 0 - the source address is not incremented after each transfer. 1 - the source address is incremented after each transfer." /> + <BitField start="27" size="1" name="DI" description="Destination increment: 0 - the destination address is not incremented after each transfer. 1 - the destination address is incremented after each transfer." /> + <BitField start="28" size="1" name="PROT1" description="This is provided to the peripheral during a DMA bus access and indicates that the access is in user mode or privileged mode. This information is not used in the LPC178x/177x. 0 - access is in user mode. 1 - access is in privileged mode." /> + <BitField start="29" size="1" name="PROT2" description="This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is bufferable or not bufferable. This information is not used in the LPC178x/177x. 0 - access is not bufferable. 1 - access is bufferable." /> + <BitField start="30" size="1" name="PROT3" description="This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is cacheable or not cacheable. This information is not used in the LPC178x/177x. 0 - access is not cacheable. 1 - access is cacheable." /> + <BitField start="31" size="1" name="I" description="Terminal count interrupt enable bit. 0 - the terminal count interrupt is disabled. 1 - the terminal count interrupt is enabled." /> + </Register> + <Register start="+0x10C+192" size="4" name="CONTROL6" access="Read/Write" description="DMA Channel 0 Control Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="12" name="TRANSFERSIZE" description="Transfer size. This field sets the size of the transfer when the DMA controller is the flow controller, in which case the value must be set before the channel is enabled. Transfer size is updated as data transfers are completed. A read from this field indicates the number of transfers completed on the destination bus. Reading the register when the channel is active does not give useful information because by the time that the software has processed the value read, the channel might have progressed. It is intended to be used only when a channel is enabled and then disabled. The transfer size value is not used if a peripheral is the flow controller." /> + <BitField start="12" size="3" name="SBSIZE" description="Source burst size. Indicates the number of transfers that make up a source burst. This value must be set to the burst size of the source peripheral, or if the source is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the source peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256" /> + <BitField start="15" size="3" name="DBSIZE" description="Destination burst size. Indicates the number of transfers that make up a destination burst transfer request. This value must be set to the burst size of the destination peripheral or, if the destination is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the destination peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256" /> + <BitField start="18" size="3" name="SWIDTH" description="Source transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved" /> + <BitField start="21" size="3" name="DWIDTH" description="Destination transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved" /> + <BitField start="24" size="2" name="RESERVED" description="Reserved, and must be written as 0." /> + <BitField start="26" size="1" name="SI" description="Source increment: 0 - the source address is not incremented after each transfer. 1 - the source address is incremented after each transfer." /> + <BitField start="27" size="1" name="DI" description="Destination increment: 0 - the destination address is not incremented after each transfer. 1 - the destination address is incremented after each transfer." /> + <BitField start="28" size="1" name="PROT1" description="This is provided to the peripheral during a DMA bus access and indicates that the access is in user mode or privileged mode. This information is not used in the LPC178x/177x. 0 - access is in user mode. 1 - access is in privileged mode." /> + <BitField start="29" size="1" name="PROT2" description="This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is bufferable or not bufferable. This information is not used in the LPC178x/177x. 0 - access is not bufferable. 1 - access is bufferable." /> + <BitField start="30" size="1" name="PROT3" description="This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is cacheable or not cacheable. This information is not used in the LPC178x/177x. 0 - access is not cacheable. 1 - access is cacheable." /> + <BitField start="31" size="1" name="I" description="Terminal count interrupt enable bit. 0 - the terminal count interrupt is disabled. 1 - the terminal count interrupt is enabled." /> + </Register> + <Register start="+0x10C+224" size="4" name="CONTROL7" access="Read/Write" description="DMA Channel 0 Control Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="12" name="TRANSFERSIZE" description="Transfer size. This field sets the size of the transfer when the DMA controller is the flow controller, in which case the value must be set before the channel is enabled. Transfer size is updated as data transfers are completed. A read from this field indicates the number of transfers completed on the destination bus. Reading the register when the channel is active does not give useful information because by the time that the software has processed the value read, the channel might have progressed. It is intended to be used only when a channel is enabled and then disabled. The transfer size value is not used if a peripheral is the flow controller." /> + <BitField start="12" size="3" name="SBSIZE" description="Source burst size. Indicates the number of transfers that make up a source burst. This value must be set to the burst size of the source peripheral, or if the source is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the source peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256" /> + <BitField start="15" size="3" name="DBSIZE" description="Destination burst size. Indicates the number of transfers that make up a destination burst transfer request. This value must be set to the burst size of the destination peripheral or, if the destination is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the destination peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256" /> + <BitField start="18" size="3" name="SWIDTH" description="Source transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved" /> + <BitField start="21" size="3" name="DWIDTH" description="Destination transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved" /> + <BitField start="24" size="2" name="RESERVED" description="Reserved, and must be written as 0." /> + <BitField start="26" size="1" name="SI" description="Source increment: 0 - the source address is not incremented after each transfer. 1 - the source address is incremented after each transfer." /> + <BitField start="27" size="1" name="DI" description="Destination increment: 0 - the destination address is not incremented after each transfer. 1 - the destination address is incremented after each transfer." /> + <BitField start="28" size="1" name="PROT1" description="This is provided to the peripheral during a DMA bus access and indicates that the access is in user mode or privileged mode. This information is not used in the LPC178x/177x. 0 - access is in user mode. 1 - access is in privileged mode." /> + <BitField start="29" size="1" name="PROT2" description="This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is bufferable or not bufferable. This information is not used in the LPC178x/177x. 0 - access is not bufferable. 1 - access is bufferable." /> + <BitField start="30" size="1" name="PROT3" description="This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is cacheable or not cacheable. This information is not used in the LPC178x/177x. 0 - access is not cacheable. 1 - access is cacheable." /> + <BitField start="31" size="1" name="I" description="Terminal count interrupt enable bit. 0 - the terminal count interrupt is disabled. 1 - the terminal count interrupt is enabled." /> + </Register> + <Register start="+0x110+0" size="4" name="CONFIG0" access="Read/Write" description="DMA Channel 0 Configuration Register[1]" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="E" description="Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: 0 = channel disabled. 1 = channel enabled. The Channel Enable bit status can also be found by reading the DMACEnbldChns Register. A channel is enabled by setting this bit. A channel can be disabled by clearing the Enable bit. This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled. Any data in the FIFO of the relevant channel is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached, the DMA transfer is completed, or if a channel error is encountered. If a channel must be disabled without losing data in the FIFO, the Halt bit must be set so that further DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable bit can be cleared." /> + <BitField start="1" size="5" name="SRCPERIPHERAL" description="Source peripheral. This value selects the DMA source request peripheral. This field is ignored if the source of the transfer is from memory. See Table 672 for peripheral identification." /> + <BitField start="6" size="5" name="DESTPERIPHERAL" description="Destination peripheral. This value selects the DMA destination request peripheral. This field is ignored if the destination of the transfer is to memory. See Table 672 for peripheral identification." /> + <BitField start="11" size="3" name="TRANSFERTYPE" description="This value indicates the type of transfer and specifies the flow controller. The transfer type can be memory-to-memory, memory-to-peripheral, peripheral-to-memory, or peripheral-to-peripheral. Flow can be controlled by the DMA controller, the source peripheral, or the destination peripheral. Refer to Table 694 for the encoding of this field." /> + <BitField start="14" size="1" name="IE" description="Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel." /> + <BitField start="15" size="1" name="ITC" description="Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel." /> + <BitField start="16" size="1" name="L" description="Lock. When set, this bit enables locked transfers. This information is not used in the LPC178x/177x." /> + <BitField start="17" size="1" name="A" description="Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel. This is a read-only bit." /> + <BitField start="18" size="1" name="H" description="Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The contents of the channel FIFO are drained. This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel." /> + <BitField start="19" size="13" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x110+32" size="4" name="CONFIG1" access="Read/Write" description="DMA Channel 0 Configuration Register[1]" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="E" description="Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: 0 = channel disabled. 1 = channel enabled. The Channel Enable bit status can also be found by reading the DMACEnbldChns Register. A channel is enabled by setting this bit. A channel can be disabled by clearing the Enable bit. This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled. Any data in the FIFO of the relevant channel is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached, the DMA transfer is completed, or if a channel error is encountered. If a channel must be disabled without losing data in the FIFO, the Halt bit must be set so that further DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable bit can be cleared." /> + <BitField start="1" size="5" name="SRCPERIPHERAL" description="Source peripheral. This value selects the DMA source request peripheral. This field is ignored if the source of the transfer is from memory. See Table 672 for peripheral identification." /> + <BitField start="6" size="5" name="DESTPERIPHERAL" description="Destination peripheral. This value selects the DMA destination request peripheral. This field is ignored if the destination of the transfer is to memory. See Table 672 for peripheral identification." /> + <BitField start="11" size="3" name="TRANSFERTYPE" description="This value indicates the type of transfer and specifies the flow controller. The transfer type can be memory-to-memory, memory-to-peripheral, peripheral-to-memory, or peripheral-to-peripheral. Flow can be controlled by the DMA controller, the source peripheral, or the destination peripheral. Refer to Table 694 for the encoding of this field." /> + <BitField start="14" size="1" name="IE" description="Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel." /> + <BitField start="15" size="1" name="ITC" description="Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel." /> + <BitField start="16" size="1" name="L" description="Lock. When set, this bit enables locked transfers. This information is not used in the LPC178x/177x." /> + <BitField start="17" size="1" name="A" description="Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel. This is a read-only bit." /> + <BitField start="18" size="1" name="H" description="Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The contents of the channel FIFO are drained. This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel." /> + <BitField start="19" size="13" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x110+64" size="4" name="CONFIG2" access="Read/Write" description="DMA Channel 0 Configuration Register[1]" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="E" description="Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: 0 = channel disabled. 1 = channel enabled. The Channel Enable bit status can also be found by reading the DMACEnbldChns Register. A channel is enabled by setting this bit. A channel can be disabled by clearing the Enable bit. This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled. Any data in the FIFO of the relevant channel is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached, the DMA transfer is completed, or if a channel error is encountered. If a channel must be disabled without losing data in the FIFO, the Halt bit must be set so that further DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable bit can be cleared." /> + <BitField start="1" size="5" name="SRCPERIPHERAL" description="Source peripheral. This value selects the DMA source request peripheral. This field is ignored if the source of the transfer is from memory. See Table 672 for peripheral identification." /> + <BitField start="6" size="5" name="DESTPERIPHERAL" description="Destination peripheral. This value selects the DMA destination request peripheral. This field is ignored if the destination of the transfer is to memory. See Table 672 for peripheral identification." /> + <BitField start="11" size="3" name="TRANSFERTYPE" description="This value indicates the type of transfer and specifies the flow controller. The transfer type can be memory-to-memory, memory-to-peripheral, peripheral-to-memory, or peripheral-to-peripheral. Flow can be controlled by the DMA controller, the source peripheral, or the destination peripheral. Refer to Table 694 for the encoding of this field." /> + <BitField start="14" size="1" name="IE" description="Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel." /> + <BitField start="15" size="1" name="ITC" description="Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel." /> + <BitField start="16" size="1" name="L" description="Lock. When set, this bit enables locked transfers. This information is not used in the LPC178x/177x." /> + <BitField start="17" size="1" name="A" description="Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel. This is a read-only bit." /> + <BitField start="18" size="1" name="H" description="Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The contents of the channel FIFO are drained. This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel." /> + <BitField start="19" size="13" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x110+96" size="4" name="CONFIG3" access="Read/Write" description="DMA Channel 0 Configuration Register[1]" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="E" description="Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: 0 = channel disabled. 1 = channel enabled. The Channel Enable bit status can also be found by reading the DMACEnbldChns Register. A channel is enabled by setting this bit. A channel can be disabled by clearing the Enable bit. This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled. Any data in the FIFO of the relevant channel is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached, the DMA transfer is completed, or if a channel error is encountered. If a channel must be disabled without losing data in the FIFO, the Halt bit must be set so that further DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable bit can be cleared." /> + <BitField start="1" size="5" name="SRCPERIPHERAL" description="Source peripheral. This value selects the DMA source request peripheral. This field is ignored if the source of the transfer is from memory. See Table 672 for peripheral identification." /> + <BitField start="6" size="5" name="DESTPERIPHERAL" description="Destination peripheral. This value selects the DMA destination request peripheral. This field is ignored if the destination of the transfer is to memory. See Table 672 for peripheral identification." /> + <BitField start="11" size="3" name="TRANSFERTYPE" description="This value indicates the type of transfer and specifies the flow controller. The transfer type can be memory-to-memory, memory-to-peripheral, peripheral-to-memory, or peripheral-to-peripheral. Flow can be controlled by the DMA controller, the source peripheral, or the destination peripheral. Refer to Table 694 for the encoding of this field." /> + <BitField start="14" size="1" name="IE" description="Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel." /> + <BitField start="15" size="1" name="ITC" description="Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel." /> + <BitField start="16" size="1" name="L" description="Lock. When set, this bit enables locked transfers. This information is not used in the LPC178x/177x." /> + <BitField start="17" size="1" name="A" description="Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel. This is a read-only bit." /> + <BitField start="18" size="1" name="H" description="Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The contents of the channel FIFO are drained. This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel." /> + <BitField start="19" size="13" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x110+128" size="4" name="CONFIG4" access="Read/Write" description="DMA Channel 0 Configuration Register[1]" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="E" description="Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: 0 = channel disabled. 1 = channel enabled. The Channel Enable bit status can also be found by reading the DMACEnbldChns Register. A channel is enabled by setting this bit. A channel can be disabled by clearing the Enable bit. This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled. Any data in the FIFO of the relevant channel is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached, the DMA transfer is completed, or if a channel error is encountered. If a channel must be disabled without losing data in the FIFO, the Halt bit must be set so that further DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable bit can be cleared." /> + <BitField start="1" size="5" name="SRCPERIPHERAL" description="Source peripheral. This value selects the DMA source request peripheral. This field is ignored if the source of the transfer is from memory. See Table 672 for peripheral identification." /> + <BitField start="6" size="5" name="DESTPERIPHERAL" description="Destination peripheral. This value selects the DMA destination request peripheral. This field is ignored if the destination of the transfer is to memory. See Table 672 for peripheral identification." /> + <BitField start="11" size="3" name="TRANSFERTYPE" description="This value indicates the type of transfer and specifies the flow controller. The transfer type can be memory-to-memory, memory-to-peripheral, peripheral-to-memory, or peripheral-to-peripheral. Flow can be controlled by the DMA controller, the source peripheral, or the destination peripheral. Refer to Table 694 for the encoding of this field." /> + <BitField start="14" size="1" name="IE" description="Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel." /> + <BitField start="15" size="1" name="ITC" description="Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel." /> + <BitField start="16" size="1" name="L" description="Lock. When set, this bit enables locked transfers. This information is not used in the LPC178x/177x." /> + <BitField start="17" size="1" name="A" description="Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel. This is a read-only bit." /> + <BitField start="18" size="1" name="H" description="Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The contents of the channel FIFO are drained. This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel." /> + <BitField start="19" size="13" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x110+160" size="4" name="CONFIG5" access="Read/Write" description="DMA Channel 0 Configuration Register[1]" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="E" description="Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: 0 = channel disabled. 1 = channel enabled. The Channel Enable bit status can also be found by reading the DMACEnbldChns Register. A channel is enabled by setting this bit. A channel can be disabled by clearing the Enable bit. This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled. Any data in the FIFO of the relevant channel is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached, the DMA transfer is completed, or if a channel error is encountered. If a channel must be disabled without losing data in the FIFO, the Halt bit must be set so that further DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable bit can be cleared." /> + <BitField start="1" size="5" name="SRCPERIPHERAL" description="Source peripheral. This value selects the DMA source request peripheral. This field is ignored if the source of the transfer is from memory. See Table 672 for peripheral identification." /> + <BitField start="6" size="5" name="DESTPERIPHERAL" description="Destination peripheral. This value selects the DMA destination request peripheral. This field is ignored if the destination of the transfer is to memory. See Table 672 for peripheral identification." /> + <BitField start="11" size="3" name="TRANSFERTYPE" description="This value indicates the type of transfer and specifies the flow controller. The transfer type can be memory-to-memory, memory-to-peripheral, peripheral-to-memory, or peripheral-to-peripheral. Flow can be controlled by the DMA controller, the source peripheral, or the destination peripheral. Refer to Table 694 for the encoding of this field." /> + <BitField start="14" size="1" name="IE" description="Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel." /> + <BitField start="15" size="1" name="ITC" description="Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel." /> + <BitField start="16" size="1" name="L" description="Lock. When set, this bit enables locked transfers. This information is not used in the LPC178x/177x." /> + <BitField start="17" size="1" name="A" description="Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel. This is a read-only bit." /> + <BitField start="18" size="1" name="H" description="Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The contents of the channel FIFO are drained. This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel." /> + <BitField start="19" size="13" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x110+192" size="4" name="CONFIG6" access="Read/Write" description="DMA Channel 0 Configuration Register[1]" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="E" description="Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: 0 = channel disabled. 1 = channel enabled. The Channel Enable bit status can also be found by reading the DMACEnbldChns Register. A channel is enabled by setting this bit. A channel can be disabled by clearing the Enable bit. This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled. Any data in the FIFO of the relevant channel is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached, the DMA transfer is completed, or if a channel error is encountered. If a channel must be disabled without losing data in the FIFO, the Halt bit must be set so that further DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable bit can be cleared." /> + <BitField start="1" size="5" name="SRCPERIPHERAL" description="Source peripheral. This value selects the DMA source request peripheral. This field is ignored if the source of the transfer is from memory. See Table 672 for peripheral identification." /> + <BitField start="6" size="5" name="DESTPERIPHERAL" description="Destination peripheral. This value selects the DMA destination request peripheral. This field is ignored if the destination of the transfer is to memory. See Table 672 for peripheral identification." /> + <BitField start="11" size="3" name="TRANSFERTYPE" description="This value indicates the type of transfer and specifies the flow controller. The transfer type can be memory-to-memory, memory-to-peripheral, peripheral-to-memory, or peripheral-to-peripheral. Flow can be controlled by the DMA controller, the source peripheral, or the destination peripheral. Refer to Table 694 for the encoding of this field." /> + <BitField start="14" size="1" name="IE" description="Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel." /> + <BitField start="15" size="1" name="ITC" description="Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel." /> + <BitField start="16" size="1" name="L" description="Lock. When set, this bit enables locked transfers. This information is not used in the LPC178x/177x." /> + <BitField start="17" size="1" name="A" description="Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel. This is a read-only bit." /> + <BitField start="18" size="1" name="H" description="Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The contents of the channel FIFO are drained. This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel." /> + <BitField start="19" size="13" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x110+224" size="4" name="CONFIG7" access="Read/Write" description="DMA Channel 0 Configuration Register[1]" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="E" description="Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: 0 = channel disabled. 1 = channel enabled. The Channel Enable bit status can also be found by reading the DMACEnbldChns Register. A channel is enabled by setting this bit. A channel can be disabled by clearing the Enable bit. This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled. Any data in the FIFO of the relevant channel is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached, the DMA transfer is completed, or if a channel error is encountered. If a channel must be disabled without losing data in the FIFO, the Halt bit must be set so that further DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable bit can be cleared." /> + <BitField start="1" size="5" name="SRCPERIPHERAL" description="Source peripheral. This value selects the DMA source request peripheral. This field is ignored if the source of the transfer is from memory. See Table 672 for peripheral identification." /> + <BitField start="6" size="5" name="DESTPERIPHERAL" description="Destination peripheral. This value selects the DMA destination request peripheral. This field is ignored if the destination of the transfer is to memory. See Table 672 for peripheral identification." /> + <BitField start="11" size="3" name="TRANSFERTYPE" description="This value indicates the type of transfer and specifies the flow controller. The transfer type can be memory-to-memory, memory-to-peripheral, peripheral-to-memory, or peripheral-to-peripheral. Flow can be controlled by the DMA controller, the source peripheral, or the destination peripheral. Refer to Table 694 for the encoding of this field." /> + <BitField start="14" size="1" name="IE" description="Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel." /> + <BitField start="15" size="1" name="ITC" description="Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel." /> + <BitField start="16" size="1" name="L" description="Lock. When set, this bit enables locked transfers. This information is not used in the LPC178x/177x." /> + <BitField start="17" size="1" name="A" description="Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel. This is a read-only bit." /> + <BitField start="18" size="1" name="H" description="Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The contents of the channel FIFO are drained. This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel." /> + <BitField start="19" size="13" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + </RegisterGroup> + <RegisterGroup name="ETHERNET" start="0x20084000" description="Ethernet"> + <Register start="+0x000" size="4" name="MAC1" access="Read/Write" description="MAC configuration register 1." reset_value="0x8000" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RXENABLE" description="RECEIVE ENABLE. Set this to allow receive frames to be received. Internally the MAC synchronizes this control bit to the incoming receive stream." /> + <BitField start="1" size="1" name="PARF" description="PASS ALL RECEIVE FRAMES. When enabled (set to 1), the MAC will pass all frames regardless of type (normal vs. Control). When disabled, the MAC does not pass valid Control frames." /> + <BitField start="2" size="1" name="RXFLOWCTRL" description="RX FLOW CONTROL. When enabled (set to 1), the MAC acts upon received PAUSE Flow Control frames. When disabled, received PAUSE Flow Control frames are ignored." /> + <BitField start="3" size="1" name="TXFLOWCTRL" description="TX FLOW CONTROL. When enabled (set to 1), PAUSE Flow Control frames are allowed to be transmitted. When disabled, Flow Control frames are blocked." /> + <BitField start="4" size="1" name="LOOPBACK" description="Setting this bit will cause the MAC Transmit interface to be looped back to the MAC Receive interface. Clearing this bit results in normal operation." /> + <BitField start="5" size="3" name="RESERVED" description="Unused" /> + <BitField start="8" size="1" name="RESETTX" description="Setting this bit will put the Transmit Function logic in reset." /> + <BitField start="9" size="1" name="RESETMCSTX" description="Setting this bit resets the MAC Control Sublayer / Transmit logic. The MCS logic implements flow control." /> + <BitField start="10" size="1" name="RESETRX" description="Setting this bit will put the Ethernet receive logic in reset." /> + <BitField start="11" size="1" name="RESETMCSRX" description="Setting this bit resets the MAC Control Sublayer / Receive logic. The MCS logic implements flow control." /> + <BitField start="12" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="14" size="1" name="SIMRESET" description="SIMULATION RESET. Setting this bit will cause a reset to the random number generator within the Transmit Function." /> + <BitField start="15" size="1" name="SOFTRESET" description="SOFT RESET. Setting this bit will put all modules within the MAC in reset except the Host Interface." /> + <BitField start="16" size="16" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x004" size="4" name="MAC2" access="Read/Write" description="MAC configuration register 2." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="FULLDUPLEX" description="When enabled (set to 1), the MAC operates in Full-Duplex mode. When disabled, the MAC operates in Half-Duplex mode." /> + <BitField start="1" size="1" name="FLC" description="FRAMELENGTH CHECKING. When enabled (set to 1), both transmit and receive frame lengths are compared to the Length/Type field. If the Length/Type field represents a length then the check is performed. Mismatches are reported in the StatusInfo word for each received frame." /> + <BitField start="2" size="1" name="HFEN" description="HUGE FRAME ENABLEWhen enabled (set to 1), frames of any length are transmitted and received." /> + <BitField start="3" size="1" name="DELAYEDCRC" description="DELAYED CRC. This bit determines the number of bytes, if any, of proprietary header information that exist on the front of IEEE 802.3 frames. When 1, four bytes of header (ignored by the CRC function) are added. When 0, there is no proprietary header." /> + <BitField start="4" size="1" name="CRCEN" description="CRC ENABLESet this bit to append a CRC to every frame whether padding was required or not. Must be set if PAD/CRC ENABLE is set. Clear this bit if frames presented to the MAC contain a CRC." /> + <BitField start="5" size="1" name="PADCRCEN" description="PAD CRC ENABLE. Set this bit to have the MAC pad all short frames. Clear this bit if frames presented to the MAC have a valid length. This bit is used in conjunction with AUTO PAD ENABLE and VLAN PAD ENABLE. See Table 153 - Pad Operation for details on the pad function." /> + <BitField start="6" size="1" name="VLANPADEN" description="VLAN PAD ENABLE. Set this bit to cause the MAC to pad all short frames to 64 bytes and append a valid CRC. Consult Table 153 - Pad Operation for more information on the various padding features. Note: This bit is ignored if PAD / CRC ENABLE is cleared." /> + <BitField start="7" size="1" name="AUTODETPADEN" description="AUTODETECTPAD ENABLE. Set this bit to cause the MAC to automatically detect the type of frame, either tagged or un-tagged, by comparing the two octets following the source address with 0x8100 (VLAN Protocol ID) and pad accordingly. Table 153 - Pad Operation provides a description of the pad function based on the configuration of this register. Note: This bit is ignored if PAD / CRC ENABLE is cleared." /> + <BitField start="8" size="1" name="PPENF" description="PURE PREAMBLE ENFORCEMEN. When enabled (set to 1), the MAC will verify the content of the preamble to ensure it contains 0x55 and is error-free. A packet with an incorrect preamble is discarded. When disabled, no preamble checking is performed." /> + <BitField start="9" size="1" name="LPENF" description="LONG PREAMBLE ENFORCEMENT. When enabled (set to 1), the MAC only allows receive packets which contain preamble fields less than 12 bytes in length. When disabled, the MAC allows any length preamble as per the Standard." /> + <BitField start="10" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="12" size="1" name="NOBACKOFF" description="When enabled (set to 1), the MAC will immediately retransmit following a collision rather than using the Binary Exponential Backoff algorithm as specified in the Standard." /> + <BitField start="13" size="1" name="BP_NOBACKOFF" description="BACK PRESSURE / NO BACKOFF. When enabled (set to 1), after the MAC incidentally causes a collision during back pressure, it will immediately retransmit without backoff, reducing the chance of further collisions and ensuring transmit packets get sent." /> + <BitField start="14" size="1" name="EXCESSDEFER" description="When enabled (set to 1) the MAC will defer to carrier indefinitely as per the Standard. When disabled, the MAC will abort when the excessive deferral limit is reached." /> + <BitField start="15" size="17" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x008" size="4" name="IPGT" access="Read/Write" description="Back-to-Back Inter-Packet-Gap register." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="7" name="BTOBINTEGAP" description="BACK-TO-BACK INTER-PACKET-GAP.This is a programmable field representing the nibble time offset of the minimum possible period between the end of any transmitted packet to the beginning of the next. In Full-Duplex mode, the register value should be the desired period in nibble times minus 3. In Half-Duplex mode, the register value should be the desired period in nibble times minus 6. In Full-Duplex the recommended setting is 0x15 (21d), which represents the minimum IPG of 960 ns (in 100 Mbps mode) or 9.6 us (in 10 Mbps mode). In Half-Duplex the recommended setting is 0x12 (18d), which also represents the minimum IPG of 960 ns (in 100 Mbps mode) or 9.6 us (in 10 Mbps mode)." /> + <BitField start="7" size="25" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x00C" size="4" name="IPGR" access="Read/Write" description="Non Back-to-Back Inter-Packet-Gap register." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="7" name="NBTOBINTEGAP2" description="NON-BACK-TO-BACK INTER-PACKET-GAP PART2. This is a programmable field representing the Non-Back-to-Back Inter-Packet-Gap. The recommended value is 0x12 (18d), which represents the minimum IPG of 960 ns (in 100 Mbps mode) or 9.6 us (in 10 Mbps mode)." /> + <BitField start="7" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="8" size="7" name="NBTOBINTEGAP1" description="NON-BACK-TO-BACK INTER-PACKET-GAP PART1. This is a programmable field representing the optional carrierSense window referenced in IEEE 802.3/4.2.3.2.1 'Carrier Deference'. If carrier is detected during the timing of IPGR1, the MAC defers to carrier. If, however, carrier becomes active after IPGR1, the MAC continues timing IPGR2 and transmits, knowingly causing a collision, thus ensuring fair access to medium. Its range of values is 0x0 to IPGR2. The recommended value is 0xC (12d)" /> + <BitField start="15" size="17" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x010" size="4" name="CLRT" access="Read/Write" description="Collision window / Retry register." reset_value="0x370F" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="4" name="RETRANSMAX" description="RETRANSMISSION MAXIMUM.This is a programmable field specifying the number of retransmission attempts following a collision before aborting the packet due to excessive collisions. The Standard specifies the attemptLimit to be 0xF (15d). See IEEE 802.3/4.2.3.2.5." /> + <BitField start="4" size="4" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="8" size="6" name="COLLWIN" description="COLLISION WINDOW. This is a programmable field representing the slot time or collision window during which collisions occur in properly configured networks. The default value of 0x37 (55d) represents a 56 byte window following the preamble and SFD." /> + <BitField start="14" size="18" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x014" size="4" name="MAXF" access="Read/Write" description="Maximum Frame register." reset_value="0x0600" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="16" name="MAXFLEN" description="MAXIMUM FRAME LENGTH. This field resets to the value 0x0600, which represents a maximum receive frame of 1536 octets. An untagged maximum size Ethernet frame is 1518 octets. A tagged frame adds four octets for a total of 1522 octets. If a shorter maximum length restriction is desired, program this 16-bit field." /> + <BitField start="16" size="16" name="RESERVED" description="Unused" /> + </Register> + <Register start="+0x018" size="4" name="SUPP" access="Read/Write" description="PHY Support register." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="RESERVED" description="Unused" /> + <BitField start="8" size="1" name="SPEED" description="This bit configures the Reduced MII logic for the current operating speed. When set, 100 Mbps mode is selected. When cleared, 10 Mbps mode is selected." /> + <BitField start="9" size="23" name="RESERVED" description="Unused" /> + </Register> + <Register start="+0x01C" size="4" name="TEST" access="Read/Write" description="Test register." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="SCPQ" description="SHORTCUT PAUSE QUANTA. This bit reduces the effective PAUSE quanta from 64 byte-times to 1 byte-time." /> + <BitField start="1" size="1" name="TESTPAUSE" description="This bit causes the MAC Control sublayer to inhibit transmissions, just as if a PAUSE Receive Control frame with a nonzero pause time parameter was received." /> + <BitField start="2" size="1" name="TESTBP" description="TEST BACKPRESSURE. Setting this bit will cause the MAC to assert backpressure on the link. Backpressure causes preamble to be transmitted, raising carrier sense. A transmit packet from the system will be sent during backpressure." /> + <BitField start="3" size="29" name="RESERVED" description="Unused" /> + </Register> + <Register start="+0x020" size="4" name="MCFG" access="Read/Write" description="MII Mgmt Configuration register." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="SCANINC" description="SCAN INCREMENT. Set this bit to cause the MII Management hardware to perform read cycles across a range of PHYs. When set, the MII Management hardware will perform read cycles from address 1 through the value set in PHY ADDRESS[4:0]. Clear this bit to allow continuous reads of the same PHY." /> + <BitField start="1" size="1" name="SUPPPREAMBLE" description="SUPPRESS PREAMBLE. Set this bit to cause the MII Management hardware to perform read/write cycles without the 32-bit preamble field. Clear this bit to cause normal cycles to be performed. Some PHYs support suppressed preamble." /> + <BitField start="2" size="4" name="CLOCKSEL" description="CLOCK SELECT. This field is used by the clock divide logic in creating the MII Management Clock (MDC) which IEEE 802.3u defines to be no faster than 2.5 MHz. Some PHYs support clock rates up to 12.5 MHz, however. The AHB bus clock (HCLK) is divided by the specified amount. Refer to Table 160 below for the definition of values for this field." /> + <BitField start="6" size="9" name="RESERVED" description="Unused" /> + <BitField start="15" size="1" name="RESETMIIMGMT" description="RESET MII MGMT. This bit resets the MII Management hardware." /> + <BitField start="16" size="16" name="RESERVED" description="Unused" /> + </Register> + <Register start="+0x024" size="4" name="MCMD" access="Read/Write" description="MII Mgmt Command register." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="READ" description="This bit causes the MII Management hardware to perform a single Read cycle. The Read data is returned in Register MRDD (MII Mgmt Read Data)." /> + <BitField start="1" size="1" name="SCAN" description="This bit causes the MII Management hardware to perform Read cycles continuously. This is useful for monitoring Link Fail for example." /> + <BitField start="2" size="30" name="RESERVED" description="Unused" /> + </Register> + <Register start="+0x028" size="4" name="MADR" access="Read/Write" description="MII Mgmt Address register." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="REGADDR" description="REGISTER ADDRESS. This field represents the 5-bit Register Address field of Mgmt cycles. Up to 32 registers can be accessed." /> + <BitField start="5" size="3" name="RESERVED" description="Unused" /> + <BitField start="8" size="5" name="PHYADDR" description="PHY ADDRESS. This field represents the 5-bit PHY Address field of Mgmt cycles. Up to 31 PHYs can be addressed (0 is reserved)." /> + <BitField start="13" size="19" name="RESERVED" description="Unused" /> + </Register> + <Register start="+0x02C" size="4" name="MWTD" access="WriteOnly" description="MII Mgmt Write Data register." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="16" name="WRITEDATA" description="WRITE DATA. When written, an MII Mgmt write cycle is performed using the 16-bit data and the pre-configured PHY and Register addresses from the MII Mgmt Address register (MADR)." /> + <BitField start="16" size="16" name="RESERVED" description="Unused" /> + </Register> + <Register start="+0x030" size="4" name="MRDD" access="ReadOnly" description="MII Mgmt Read Data register." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="16" name="READDATA" description="READ DATA. Following an MII Mgmt Read Cycle, the 16-bit data can be read from this location." /> + <BitField start="16" size="16" name="RESERVED" description="Unused" /> + </Register> + <Register start="+0x034" size="4" name="MIND" access="ReadOnly" description="MII Mgmt Indicators register." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="BUSY" description="When 1 is returned - indicates MII Mgmt is currently performing an MII Mgmt Read or Write cycle." /> + <BitField start="1" size="1" name="SCANNING" description="When 1 is returned - indicates a scan operation (continuous MII Mgmt Read cycles) is in progress." /> + <BitField start="2" size="1" name="NOTVALID" description="When 1 is returned - indicates MII Mgmt Read cycle has not completed and the Read Data is not yet valid." /> + <BitField start="3" size="1" name="MIILINKFAIL" description="When 1 is returned - indicates that an MII Mgmt link fail has occurred." /> + <BitField start="4" size="28" name="RESERVED" description="Unused" /> + </Register> + <Register start="+0x040" size="4" name="SA0" access="Read/Write" description="Station Address 0 register." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="SADDR2" description="STATION ADDRESS, 2nd octet. This field holds the second octet of the station address." /> + <BitField start="8" size="8" name="SADDR1" description="STATION ADDRESS, 1st octet. This field holds the first octet of the station address." /> + <BitField start="16" size="16" name="RESERVED" description="Unused" /> + </Register> + <Register start="+0x044" size="4" name="SA1" access="Read/Write" description="Station Address 1 register." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="SADDR4" description="STATION ADDRESS, 4th octet. This field holds the fourth octet of the station address." /> + <BitField start="8" size="8" name="SADDR3" description="STATION ADDRESS, 3rd octet. This field holds the third octet of the station address." /> + <BitField start="16" size="16" name="RESERVED" description="Unused" /> + </Register> + <Register start="+0x048" size="4" name="SA2" access="Read/Write" description="Station Address 2 register." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="SADDR6" description="STATION ADDRESS, 6th octet. This field holds the sixth octet of the station address." /> + <BitField start="8" size="8" name="SADDR5" description="STATION ADDRESS, 5th octet. This field holds the fifth octet of the station address." /> + <BitField start="16" size="16" name="RESERVED" description="Unused" /> + </Register> + <Register start="+0x100" size="4" name="COMMAND" access="Read/Write" description="Command register." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RXENABLE" description="Enable receive." /> + <BitField start="1" size="1" name="TXENABLE" description="Enable transmit." /> + <BitField start="2" size="1" name="RESERVED" description="Unused" /> + <BitField start="3" size="1" name="REGRESET" description="When a 1 is written, all datapaths and the host registers are reset. The MAC needs to be reset separately." /> + <BitField start="4" size="1" name="TXRESET" description="When a 1 is written, the transmit datapath is reset." /> + <BitField start="5" size="1" name="RXRESET" description="When a 1 is written, the receive datapath is reset." /> + <BitField start="6" size="1" name="PASSRUNTFRAME" description="When set to 1 , passes runt frames s1maller than 64 bytes to memory unless they have a CRC error. If 0 runt frames are filtered out." /> + <BitField start="7" size="1" name="PASSRXFILTER" description="When set to 1 , disables receive filtering i.e. all frames received are written to memory." /> + <BitField start="8" size="1" name="TXFLOWCONTROL" description="Enable IEEE 802.3 / clause 31 flow control sending pause frames in full duplex and continuous preamble in half duplex." /> + <BitField start="9" size="1" name="RMII" description="When set to 1 , RMII mode is selected; if 0, MII mode is selected." /> + <BitField start="10" size="1" name="FULLDUPLEX" description="When set to 1 , indicates full duplex operation." /> + <BitField start="11" size="21" name="RESERVED" description="Unused" /> + </Register> + <Register start="+0x104" size="4" name="STATUS" access="ReadOnly" description="Status register." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RXSTATUS" description="If 1, the receive channel is active. If 0, the receive channel is inactive." /> + <BitField start="1" size="1" name="TXSTATUS" description="If 1, the transmit channel is active. If 0, the transmit channel is inactive." /> + <BitField start="2" size="30" name="RESERVED" description="Unused" /> + </Register> + <Register start="+0x108" size="4" name="RXDESCRIPTOR" access="Read/Write" description="Receive descriptor base address register." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="RESERVED" description="Fixed to 00" /> + <BitField start="2" size="30" name="RXDESCRIPTOR" description="MSBs of receive descriptor base address." /> + </Register> + <Register start="+0x10C" size="4" name="RXSTATUS" access="Read/Write" description="Receive status base address register." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="RESERVED" description="Fixed to 000" /> + <BitField start="3" size="29" name="RXSTATUS" description="MSBs of receive status base address." /> + </Register> + <Register start="+0x110" size="4" name="RXDESCRIPTORNUMBER" access="Read/Write" description="Receive number of descriptors register." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="16" name="RXDESCRIPTORN" description="RxDescriptorNumber. Number of descriptors in the descriptor array for which RxDescriptor is the base address. The number of descriptors is minus one encoded." /> + <BitField start="16" size="16" name="RESERVED" description="Unused" /> + </Register> + <Register start="+0x114" size="4" name="RXPRODUCEINDEX" access="ReadOnly" description="Receive produce index register." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="16" name="RXPRODUCEIX" description="Index of the descriptor that is going to be filled next by the receive datapath." /> + <BitField start="16" size="16" name="RESERVED" description="Unused" /> + </Register> + <Register start="+0x118" size="4" name="RXCONSUMEINDEX" access="Read/Write" description="Receive consume index register." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="16" name="RXCONSUMEIX" description="Index of the descriptor that is going to be processed next by the receive" /> + <BitField start="16" size="16" name="RESERVED" description="Unused" /> + </Register> + <Register start="+0x11C" size="4" name="TXDESCRIPTOR" access="Read/Write" description="Transmit descriptor base address register." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="RESERVED" description="Fixed to 00" /> + <BitField start="2" size="30" name="TXD" description="TxDescriptor. MSBs of transmit descriptor base address." /> + </Register> + <Register start="+0x120" size="4" name="TXSTATUS" access="Read/Write" description="Transmit status base address register." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="RESERVED" description="Fixed to 00" /> + <BitField start="2" size="30" name="TXSTAT" description="TxStatus. MSBs of transmit status base address." /> + </Register> + <Register start="+0x124" size="4" name="TXDESCRIPTORNUMBER" access="Read/Write" description="Transmit number of descriptors register." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="16" name="TXDN" description="TxDescriptorNumber. Number of descriptors in the descriptor array for which TxDescriptor is the base address. The register is minus one encoded." /> + <BitField start="16" size="16" name="RESERVED" description="Unused" /> + </Register> + <Register start="+0x128" size="4" name="TXPRODUCEINDEX" access="Read/Write" description="Transmit produce index register." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="16" name="TXPI" description="TxProduceIndex. Index of the descriptor that is going to be filled next by the transmit software driver." /> + <BitField start="16" size="16" name="RESERVED" description="Unused" /> + </Register> + <Register start="+0x12C" size="4" name="TXCONSUMEINDEX" access="ReadOnly" description="Transmit consume index register." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="16" name="TXCI" description="TxConsumeIndex. Index of the descriptor that is going to be transmitted next by the transmit datapath." /> + <BitField start="16" size="16" name="RESERVED" description="Unused" /> + </Register> + <Register start="+0x158" size="4" name="TSV0" access="ReadOnly" description="Transmit status vector 0 register." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="CRCERR" description="CRC error. The attached CRC in the packet did not match the internally generated CRC." /> + <BitField start="1" size="1" name="LCE" description="Length check error. Indicates the frame length field does not match the actual number of data items and is not a type field." /> + <BitField start="2" size="1" name="LOR" description="Length out of range. Indicates that frame type/length field was larger than 1500 bytes. The EMAC doesn't distinguish the frame type and frame length, so, e.g. when the IP(0x8000) or ARP(0x0806) packets are received, it compares the frame type with the max length and gives the "Length out of range" error. In fact, this bit is not an error indication, but simply a statement by the chip regarding the status of the received frame." /> + <BitField start="3" size="1" name="DONE" description="Transmission of packet was completed." /> + <BitField start="4" size="1" name="MULTICAST" description="Packet's destination was a multicast address." /> + <BitField start="5" size="1" name="BROADCAST" description="Packet's destination was a broadcast address." /> + <BitField start="6" size="1" name="PACKETDEFER" description="Packet was deferred for at least one attempt, but less than an excessive defer." /> + <BitField start="7" size="1" name="EXDF" description="Excessive Defer. Packet was deferred in excess of 6071 nibble times in 100 Mbps or 24287 bit times in 10 Mbps mode." /> + <BitField start="8" size="1" name="EXCOL" description="Excessive Collision. Packet was aborted due to exceeding of maximum allowed number of collisions." /> + <BitField start="9" size="1" name="LCOL" description="Late Collision. Collision occurred beyond collision window, 512 bit times." /> + <BitField start="10" size="1" name="GIANT" description="Byte count in frame was greater than can be represented in the transmit byte count field in TSV1." /> + <BitField start="11" size="1" name="UNDERRUN" description="Host side caused buffer underrun." /> + <BitField start="12" size="16" name="TOTALBYTES" description="The total number of bytes transferred including collided attempts." /> + <BitField start="28" size="1" name="CONTROLFRAME" description="The frame was a control frame." /> + <BitField start="29" size="1" name="PAUSE" description="The frame was a control frame with a valid PAUSE opcode." /> + <BitField start="30" size="1" name="BACKPRESSURE" description="Carrier-sense method backpressure was previously applied." /> + <BitField start="31" size="1" name="VLAN" description="Frame's length/type field contained 0x8100 which is the VLAN protocol identifier." /> + </Register> + <Register start="+0x15C" size="4" name="TSV1" access="ReadOnly" description="Transmit status vector 1 register." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="16" name="TBC" description="Transmit byte count. The total number of bytes in the frame, not counting the collided bytes." /> + <BitField start="16" size="4" name="TCC" description="Transmit collision count. Number of collisions the current packet incurred during transmission attempts. The maximum number of collisions (16) cannot be represented." /> + <BitField start="20" size="12" name="RESERVED" description="Unused" /> + </Register> + <Register start="+0x160" size="4" name="RSV" access="ReadOnly" description="Receive status vector register." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="16" name="RBC" description="Received byte count. Indicates length of received frame." /> + <BitField start="16" size="1" name="PPI" description="Packet previously ignored. Indicates that a packet was dropped." /> + <BitField start="17" size="1" name="RXDVSEEN" description="RXDV event previously seen. Indicates that the last receive event seen was not long enough to be a valid packet." /> + <BitField start="18" size="1" name="CESEEN" description="Carrier event previously seen. Indicates that at some time since the last receive statistics, a carrier event was detected." /> + <BitField start="19" size="1" name="RCV" description="Receive code violation. Indicates that received PHY data does not represent a valid receive code." /> + <BitField start="20" size="1" name="CRCERR" description="CRC error. The attached CRC in the packet did not match the internally generated CRC." /> + <BitField start="21" size="1" name="LCERR" description="Length check error. Indicates the frame length field does not match the actual number of data items and is not a type field." /> + <BitField start="22" size="1" name="LOR" description="Length out of range. Indicates that frame type/length field was larger than 1518 bytes. The EMAC doesn't distinguish the frame type and frame length, so, e.g. when the IP(0x8000) or ARP(0x0806) packets are received, it compares the frame type with the max length and gives the "Length out of range" error. In fact, this bit is not an error indication, but simply a statement by the chip regarding the status of the received frame." /> + <BitField start="23" size="1" name="ROK" description="Receive OK. The packet had valid CRC and no symbol errors." /> + <BitField start="24" size="1" name="MULTICAST" description="The packet destination was a multicast address." /> + <BitField start="25" size="1" name="BROADCAST" description="The packet destination was a broadcast address." /> + <BitField start="26" size="1" name="DRIBBLENIBBLE" description="Indicates that after the end of packet another 1-7 bits were received. A single nibble, called dribble nibble, is formed but not sent out." /> + <BitField start="27" size="1" name="CONTROLFRAME" description="The frame was a control frame." /> + <BitField start="28" size="1" name="PAUSE" description="The frame was a control frame with a valid PAUSE opcode." /> + <BitField start="29" size="1" name="UO" description="Unsupported Opcode. The current frame was recognized as a Control Frame but contains an unknown opcode." /> + <BitField start="30" size="1" name="VLAN" description="Frame's length/type field contained 0x8100 which is the VLAN protocol identifier." /> + <BitField start="31" size="1" name="RESERVED" description="Unused" /> + </Register> + <Register start="+0x170" size="4" name="FLOWCONTROLCOUNTER" access="Read/Write" description="Flow control counter register." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="16" name="MC" description="MirrorCounter. In full duplex mode the MirrorCounter specifies the number of cycles before re-issuing the Pause control frame." /> + <BitField start="16" size="16" name="PT" description="PauseTimer. In full-duplex mode the PauseTimer specifies the value that is inserted into the pause timer field of a pause flow control frame. In half duplex mode the PauseTimer specifies the number of backpressure cycles." /> + </Register> + <Register start="+0x174" size="4" name="FLOWCONTROLSTATUS" access="ReadOnly" description="Flow control status register." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="16" name="MCC" description="MirrorCounterCurrent. In full duplex mode this register represents the current value of the datapath's mirror counter which counts up to the value specified by the MirrorCounter field in the FlowControlCounter register. In half duplex mode the register counts until it reaches the value of the PauseTimer bits in the FlowControlCounter register." /> + <BitField start="16" size="16" name="RESERVED" description="Unused" /> + </Register> + <Register start="+0x200" size="4" name="RXFILTERCTRL" access="Read/Write" description="Receive filter control register." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="AUE" description="AcceptUnicastEn. When set to 1, all unicast frames are accepted." /> + <BitField start="1" size="1" name="ABE" description="AcceptBroadcastEn. When set to 1, all broadcast frames are accepted." /> + <BitField start="2" size="1" name="AME" description="AcceptMulticastEn. When set to 1, all multicast frames are accepted." /> + <BitField start="3" size="1" name="AUHE" description="AcceptUnicastHashEn. When set to 1, unicast frames that pass the imperfect hash filter are accepted." /> + <BitField start="4" size="1" name="AMHE" description="AcceptMulticastHashEn. When set to 1, multicast frames that pass the imperfect hash filter are accepted." /> + <BitField start="5" size="1" name="APE" description="AcceptPerfectEn. When set to 1, the frames with a destination address identical to the station address are accepted." /> + <BitField start="6" size="6" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="12" size="1" name="MPEW" description="MagicPacketEnWoL. When set to 1, the result of the magic packet filter will generate a WoL interrupt when there is a match." /> + <BitField start="13" size="1" name="RFEW" description="RxFilterEnWoL. When set to 1, the result of the perfect address matching filter and the imperfect hash filter will generate a WoL interrupt when there is a match." /> + <BitField start="14" size="18" name="RESERVED" description="Unused" /> + </Register> + <Register start="+0x204" size="4" name="RXFILTERWOLSTATUS" access="ReadOnly" description="Receive filter WoL status register." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="AUW" description="AcceptUnicastWoL. When the value is 1, a unicast frames caused WoL." /> + <BitField start="1" size="1" name="ABW" description="AcceptBroadcastWoL. When the value is 1, a broadcast frame caused WoL." /> + <BitField start="2" size="1" name="AMW" description="AcceptMulticastWoL. When the value is 1, a multicast frame caused WoL." /> + <BitField start="3" size="1" name="AUHW" description="AcceptUnicastHashWoL. When the value is 1, a unicast frame that passes the imperfect hash filter caused WoL." /> + <BitField start="4" size="1" name="AMHW" description="AcceptMulticastHashWoL. When the value is 1, a multicast frame that passes the imperfect hash filter caused WoL." /> + <BitField start="5" size="1" name="APW" description="AcceptPerfectWoL. When the value is 1, the perfect address matching filter caused WoL." /> + <BitField start="6" size="1" name="RESERVED" description="Unused" /> + <BitField start="7" size="1" name="RFW" description="RxFilterWoL. When the value is 1, the receive filter caused WoL." /> + <BitField start="8" size="1" name="MPW" description="MagicPacketWoL. When the value is 1, the magic packet filter caused WoL." /> + <BitField start="9" size="23" name="RESERVED" description="Unused" /> + </Register> + <Register start="+0x208" size="4" name="RXFILTERWOLCLEAR" access="WriteOnly" description="Receive filter WoL clear register." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="AUWCLR" description="AcceptUnicastWoLClr. When a 1 is written, the corresponding status bit in the RxFilterWoLStatus register is cleared." /> + <BitField start="1" size="1" name="ABWCLR" description="AcceptBroadcastWoLClr. When a 1 is written, the corresponding status bit in the RxFilterWoLStatus register is cleared." /> + <BitField start="2" size="1" name="AMWCLR" description="AcceptMulticastWoLClr. When a 1 is written, the corresponding status bit in the RxFilterWoLStatus register is cleared." /> + <BitField start="3" size="1" name="AUHWCLR" description="AcceptUnicastHashWoLClr. When a 1 is written, the corresponding status bit in the RxFilterWoLStatus register is cleared." /> + <BitField start="4" size="1" name="AMHWCLR" description="AcceptMulticastHashWoLClr. When a 1 is written, the corresponding status bit in the RxFilterWoLStatus register is cleared." /> + <BitField start="5" size="1" name="APWCLR" description="AcceptPerfectWoLClr. When a 1 is written, the corresponding status bit in the RxFilterWoLStatus register is cleared." /> + <BitField start="6" size="1" name="RESERVED" description="Unused" /> + <BitField start="7" size="1" name="RFWCLR" description="RxFilterWoLClr. When a 1 is written, the corresponding status bit in the RxFilterWoLStatus register is cleared." /> + <BitField start="8" size="1" name="MPWCLR" description="MagicPacketWoLClr. When a 1 is written, the corresponding status bit in the RxFilterWoLStatus register is cleared." /> + <BitField start="9" size="23" name="RESERVED" description="Unused" /> + </Register> + <Register start="+0x210" size="4" name="HASHFILTERL" access="Read/Write" description="Hash filter table LSBs register." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="HFL" description="HashFilterL. Bits 31:0 of the imperfect filter hash table for receive filtering." /> + </Register> + <Register start="+0x214" size="4" name="HASHFILTERH" access="Read/Write" description="Hash filter table MSBs register." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="HFH" description="Bits 63:32 of the imperfect filter hash table for receive filtering." /> + </Register> + <Register start="+0xFE0" size="4" name="INTSTATUS" access="ReadOnly" description="Interrupt status register." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RXOVERRUNINT" description="Interrupt set on a fatal overrun error in the receive queue. The fatal interrupt should be resolved by a Rx soft-reset. The bit is not set when there is a nonfatal overrun error." /> + <BitField start="1" size="1" name="RXERRORINT" description="Interrupt trigger on receive errors: AlignmentError, RangeError, LengthError, SymbolError, CRCError or NoDescriptor or Overrun." /> + <BitField start="2" size="1" name="RXFINISHEDINT" description="Interrupt triggered when all receive descriptors have been processed i.e. on the transition to the situation where ProduceIndex == ConsumeIndex." /> + <BitField start="3" size="1" name="RXDONEINT" description="Interrupt triggered when a receive descriptor has been processed while the Interrupt bit in the Control field of the descriptor was set." /> + <BitField start="4" size="1" name="TXUNDERRUNINT" description="Interrupt set on a fatal underrun error in the transmit queue. The fatal interrupt should be resolved by a Tx soft-reset. The bit is not set when there is a nonfatal underrun error." /> + <BitField start="5" size="1" name="TXERRORINT" description="Interrupt trigger on transmit errors: LateCollision, ExcessiveCollision and ExcessiveDefer, NoDescriptor or Underrun." /> + <BitField start="6" size="1" name="TXFINISHEDINT" description="Interrupt triggered when all transmit descriptors have been processed i.e. on the transition to the situation where ProduceIndex == ConsumeIndex." /> + <BitField start="7" size="1" name="TXDONEINT" description="Interrupt triggered when a descriptor has been transmitted while the Interrupt bit in the Control field of the descriptor was set." /> + <BitField start="8" size="4" name="RESERVED" description="Unused" /> + <BitField start="12" size="1" name="SOFTINT" description="Interrupt triggered by software writing a 1 to the SoftIntSet bit in the IntSet register." /> + <BitField start="13" size="1" name="WAKEUPINT" description="Interrupt triggered by a Wake-up event detected by the receive filter." /> + <BitField start="14" size="18" name="RESERVED" description="Unused" /> + </Register> + <Register start="+0xFE4" size="4" name="INTENABLE" access="Read/Write" description="Interrupt enable register." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RXOVERRUNINTEN" description="Enable for interrupt trigger on receive buffer overrun or descriptor underrun situations." /> + <BitField start="1" size="1" name="RXERRORINTEN" description="Enable for interrupt trigger on receive errors." /> + <BitField start="2" size="1" name="RXFINISHEDINTEN" description="Enable for interrupt triggered when all receive descriptors have been processed i.e. on the transition to the situation where ProduceIndex == ConsumeIndex." /> + <BitField start="3" size="1" name="RXDONEINTEN" description="Enable for interrupt triggered when a receive descriptor has been processed while the Interrupt bit in the Control field of the descriptor was set." /> + <BitField start="4" size="1" name="TXUNDERRUNINTEN" description="Enable for interrupt trigger on transmit buffer or descriptor underrun situations." /> + <BitField start="5" size="1" name="TXERRORINTEN" description="Enable for interrupt trigger on transmit errors." /> + <BitField start="6" size="1" name="TXFINISHEDINTEN" description="Enable for interrupt triggered when all transmit descriptors have been processed i.e. on the transition to the situation where ProduceIndex == ConsumeIndex." /> + <BitField start="7" size="1" name="TXDONEINTEN" description="Enable for interrupt triggered when a descriptor has been transmitted while the Interrupt bit in the Control field of the descriptor was set." /> + <BitField start="8" size="4" name="RESERVED" description="Unused" /> + <BitField start="12" size="1" name="SOFTINTEN" description="Enable for interrupt triggered by the SoftInt bit in the IntStatus register, caused by software writing a 1 to the SoftIntSet bit in the IntSet register." /> + <BitField start="13" size="1" name="WAKEUPINTEN" description="Enable for interrupt triggered by a Wake-up event detected by the receive filter." /> + <BitField start="14" size="18" name="RESERVED" description="Unused" /> + </Register> + <Register start="+0xFE8" size="4" name="INTCLEAR" access="WriteOnly" description="Interrupt clear register." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RXOVERRUNINTCLR" description="Writing a 1 clears the corresponding status bit in interrupt status register IntStatus." /> + <BitField start="1" size="1" name="RXERRORINTCLR" description="Writing a 1 clears the corresponding status bit in interrupt status register IntStatus." /> + <BitField start="2" size="1" name="RXFINISHEDINTCLR" description="Writing a 1 clears the corresponding status bit in interrupt status register IntStatus." /> + <BitField start="3" size="1" name="RXDONEINTCLR" description="Writing a 1 clears the corresponding status bit in interrupt status register IntStatus." /> + <BitField start="4" size="1" name="TXUNDERRUNINTCLR" description="Writing a 1 clears the corresponding status bit in interrupt status register IntStatus." /> + <BitField start="5" size="1" name="TXERRORINTCLR" description="Writing a 1 clears the corresponding status bit in interrupt status register IntStatus." /> + <BitField start="6" size="1" name="TXFINISHEDINTCLR" description="Writing a 1 clears the corresponding status bit in interrupt status register IntStatus." /> + <BitField start="7" size="1" name="TXDONEINTCLR" description="Writing a 1 clears the corresponding status bit in interrupt status register IntStatus." /> + <BitField start="8" size="4" name="RESERVED" description="Unused" /> + <BitField start="12" size="1" name="SOFTINTCLR" description="Writing a 1 clears the corresponding status bit in interrupt status register IntStatus." /> + <BitField start="13" size="1" name="WAKEUPINTCLR" description="Writing a 1 clears the corresponding status bit in interrupt status register IntStatus." /> + <BitField start="14" size="18" name="RESERVED" description="Unused" /> + </Register> + <Register start="+0xFEC" size="4" name="INTSET" access="WriteOnly" description="Interrupt set register." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RXOVERRUNINTSET" description="Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus." /> + <BitField start="1" size="1" name="RXERRORINTSET" description="Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus." /> + <BitField start="2" size="1" name="RXFINISHEDINTSET" description="Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus." /> + <BitField start="3" size="1" name="RXDONEINTSET" description="Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus." /> + <BitField start="4" size="1" name="TXUNDERRUNINTSET" description="Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus." /> + <BitField start="5" size="1" name="TXERRORINTSET" description="Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus." /> + <BitField start="6" size="1" name="TXFINISHEDINTSET" description="Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus." /> + <BitField start="7" size="1" name="TXDONEINTSET" description="Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus." /> + <BitField start="8" size="4" name="RESERVED" description="Unused" /> + <BitField start="12" size="1" name="SOFTINTSET" description="Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus." /> + <BitField start="13" size="1" name="WAKEUPINTSET" description="Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus." /> + <BitField start="14" size="18" name="RESERVED" description="Unused" /> + </Register> + <Register start="+0xFF4" size="4" name="POWERDOWN" access="Read/Write" description="Power-down register." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="31" name="RESERVED" description="Unused" /> + <BitField start="31" size="1" name="PD" description="PowerDownMACAHB. If true, all AHB accesses will return a read/write error, except accesses to the Power-Down register." /> + </Register> + </RegisterGroup> + <RegisterGroup name="LCD" start="0x20088000" description="LCD controller Modification "> + <Register start="+0x000" size="4" name="TIMH" access="Read/Write" description="Horizontal Timing Control register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="2" size="6" name="PPL" description="Pixels-per-line. The PPL bit field specifies the number of pixels in each line or row of the screen. PPL is a 6-bit value that represents between 16 and 1024 pixels per line. PPL counts the number of pixel clocks that occur before the HFP is applied. Program the value required divided by 16, minus 1. Actual pixels-per-line = 16 * (PPL + 1). For example, to obtain 320 pixels per line, program PPL as (320/16) -1 = 19." /> + <BitField start="8" size="8" name="HSW" description="Horizontal synchronization pulse width. The 8-bit HSW field specifies the pulse width of the line clock in passive mode, or the horizontal synchronization pulse in active mode. Program with desired value minus 1." /> + <BitField start="16" size="8" name="HFP" description="Horizontal front porch. The 8-bit HFP field sets the number of pixel clock intervals at the end of each line or row of pixels, before the LCD line clock is pulsed. When a complete line of pixels is transmitted to the LCD driver, the value in HFP counts the number of pixel clocks to wait before asserting the line clock. HFP can generate a period of 1-256 pixel clock cycles. Program with desired value minus 1." /> + <BitField start="24" size="8" name="HBP" description="Horizontal back porch. The 8-bit HBP field is used to specify the number of pixel clock periods inserted at the beginning of each line or row of pixels. After the line clock for the previous line has been deasserted, the value in HBP counts the number of pixel clocks to wait before starting the next display line. HBP can generate a delay of 1-256 pixel clock cycles. Program with desired value minus 1." /> + </Register> + <Register start="+0x004" size="4" name="TIMV" access="Read/Write" description="Vertical Timing Control register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="10" name="LPP" description="Lines per panel. This is the number of active lines per screen. The LPP field specifies the total number of lines or rows on the LCD panel being controlled. LPP is a 10-bit value allowing between 1 and 1024 lines. Program the register with the number of lines per LCD panel, minus 1. For dual panel displays, program the register with the number of lines on each of the upper and lower panels." /> + <BitField start="10" size="6" name="VSW" description="Vertical synchronization pulse width. This is the number of horizontal synchronization lines. The 6-bit VSW field specifies the pulse width of the vertical synchronization pulse. Program the register with the number of lines required, minus one. The number of horizontal synchronization lines must be small (for example, program to zero) for passive STN LCDs. The higher the value the worse the contrast on STN LCDs." /> + <BitField start="16" size="8" name="VFP" description="Vertical front porch. This is the number of inactive lines at the end of a frame, before the vertical synchronization period. The 8-bit VFP field specifies the number of line clocks to insert at the end of each frame. When a complete frame of pixels is transmitted to the LCD display, the value in VFP is used to count the number of line clock periods to wait. After the count has elapsed, the vertical synchronization signal, LCD_FP, is asserted in active mode, or extra line clocks are inserted as specified by the VSW bit-field in passive mode. VFP generates 0-255 line clock cycles. Program to zero on passive displays for improved contrast." /> + <BitField start="24" size="8" name="VBP" description="Vertical back porch. This is the number of inactive lines at the start of a frame, after the vertical synchronization period. The 8-bit VBP field specifies the number of line clocks inserted at the beginning of each frame. The VBP count starts immediately after the vertical synchronization signal for the previous frame has been negated for active mode, or the extra line clocks have been inserted as specified by the VSW bit field in passive mode. After this has occurred, the count value in VBP sets the number of line clock periods inserted before the next frame. VBP generates 0 to 255 extra line clock cycles. Program to zero on passive displays for improved contrast." /> + </Register> + <Register start="+0x008" size="4" name="POL" access="Read/Write" description="Clock and Signal Polarity Control register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="PCD_LO" description="Lower five bits of panel clock divisor. The ten-bit PCD field, comprising PCD_HI (bits 31:27 of this register) and PCD_LO, is used to derive the LCD panel clock frequency LCD_DCLK from the input clock, LCD_DCLK = LCDCLK/(PCD+2). For monochrome STN displays with a 4 or 8-bit interface, the panel clock is a factor of four and eight down from the actual individual pixel clock rate. For color STN displays, 22/3 pixels are output per LCD_DCLK cycle, so the panel clock is 0.375 times the pixel rate. For TFT displays, the pixel clock divider can be bypassed by setting the BCD bit in this register. Note: data path latency forces some restrictions on the usable minimum values for the panel clock divider in STN modes: Single panel color mode, PCD = 1 (LCD_DCLK = LCDCLK/3). Dual panel color mode, PCD = 4 (LCD_DCLK = LCDCLK/6). Single panel monochrome 4-bit interface mode, PCD = 2(LCD_DCLK = LCDCLK/4). Dual panel monochrome 4-bit interface mode and single panel monochrome 8-bit interface mode, PCD = 6(LCD_DCLK = LCDCLK/8). Dual panel monochrome 8-bit interface mode, PCD = 14(LCD_DCLK = LCDCLK/16)." /> + <BitField start="5" size="1" name="CLKSEL" description="Clock Select. This bit controls the selection of the source for LCDCLK. 0 = the clock source for the LCD block is CCLK. 1 = the clock source for the LCD block is LCD_CLKIN (external clock input for the LVD)." /> + <BitField start="6" size="5" name="ACB" description="AC bias pin frequency. The AC bias pin frequency is only applicable to STN displays. These require the pixel voltage polarity to periodically reverse to prevent damage caused by DC charge accumulation. Program this field with the required value minus one to apply the number of line clocks between each toggle of the AC bias pin, LCD_ENAB_M. This field has no effect if the LCD is operating in TFT mode, when the LCD_ENAB_M pin is used as a data enable signal." /> + <BitField start="11" size="1" name="IVS" description="Invert vertical synchronization. The IVS bit inverts the polarity of the LCD_FP signal. 0 = LCD_FP pin is active HIGH and inactive LOW. 1 = LCD_FP pin is active LOW and inactive HIGH." /> + <BitField start="12" size="1" name="IHS" description="Invert horizontal synchronization. The IHS bit inverts the polarity of the LCD_LP signal. 0 = LCD_LP pin is active HIGH and inactive LOW. 1 = LCD_LP pin is active LOW and inactive HIGH." /> + <BitField start="13" size="1" name="IPC" description="Invert panel clock. The IPC bit selects the edge of the panel clock on which pixel data is driven out onto the LCD data lines. 0 = Data is driven on the LCD data lines on the rising edge of LCD_DCLK. 1 = Data is driven on the LCD data lines on the falling edge of LCD_DCLK." /> + <BitField start="14" size="1" name="IOE" description="Invert output enable. This bit selects the active polarity of the output enable signal in TFT mode. In this mode, the LCD_ENAB_M pin is used as an enable that indicates to the LCD panel when valid display data is available. In active display mode, data is driven onto the LCD data lines at the programmed edge of LCD_DCLK when LCD_ENAB_M is in its active state. 0 = LCD_ENAB_M output pin is active HIGH in TFT mode. 1 = LCD_ENAB_M output pin is active LOW in TFT mode." /> + <BitField start="15" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="16" size="10" name="CPL" description="Clocks per line. This field specifies the number of actual LCD_DCLK clocks to the LCD panel on each line. This is the number of PPL divided by either 1 (for TFT), 4 or 8 (for monochrome passive), 2 2/3 (for color passive), minus one. This must be correctly programmed in addition to the PPL bit in the LCD_TIMH register for the LCD display to work correctly." /> + <BitField start="26" size="1" name="BCD" description="Bypass pixel clock divider. Setting this to 1 bypasses the pixel clock divider logic. This is mainly used for TFT displays." /> + <BitField start="27" size="5" name="PCD_HI" description="Upper five bits of panel clock divisor. See description for PCD_LO, in bits [4:0] of this register." /> + </Register> + <Register start="+0x00C" size="4" name="LE" access="Read/Write" description="Line End Control register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="7" name="LED" description="Line-end delay. Controls Line-end signal delay from the rising-edge of the last panel clock, LCD_DCLK. Program with the number of LCDCLK clock periods minus 1." /> + <BitField start="7" size="9" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="16" size="1" name="LEE" description="LCD Line end enable. 0 = LCD_LE disabled (held LOW). 1 = LCD_LE signal active." /> + <BitField start="17" size="15" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x010" size="4" name="UPBASE" access="Read/Write" description="Upper Panel Frame Base Address register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="3" size="29" name="LCDUPBASE" description="LCD upper panel base address. This is the start address of the upper panel frame data in memory and is doubleword aligned." /> + </Register> + <Register start="+0x014" size="4" name="LPBASE" access="Read/Write" description="Lower Panel Frame Base Address register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="3" size="29" name="LCDLPBASE" description="LCD lower panel base address. This is the start address of the lower panel frame data in memory and is doubleword aligned." /> + </Register> + <Register start="+0x018" size="4" name="CTRL" access="Read/Write" description="LCD Control register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="LCDEN" description="LCD enable control bit. 0 = LCD disabled. Signals LCD_LP, LCD_DCLK, LCD_FP, LCD_ENAB_M, and LCD_LE are low. 1 = LCD enabled. Signals LCD_LP, LCD_DCLK, LCD_FP, LCD_ENAB_M, and LCD_LE are high. See LCD power-up and power-down sequence for details on LCD power sequencing." /> + <BitField start="1" size="3" name="LCDBPP" description="LCD bits per pixel. Selects the number of bits per LCD pixel: 000 = 1 bpp. 001 = 2 bpp. 010 = 4 bpp. 011 = 8 bpp. 100 = 16 bpp. 101 = 24 bpp (TFT panel only). 110 = 16 bpp, 5:6:5 mode. 111 = 12 bpp, 4:4:4 mode." /> + <BitField start="4" size="1" name="LCDBW" description="STN LCD monochrome/color selection. 0 = STN LCD is color. 1 = STN LCD is monochrome. This bit has no meaning in TFT mode." /> + <BitField start="5" size="1" name="LCDTFT" description="LCD panel TFT type selection. 0 = LCD is an STN display. Use gray scaler. 1 = LCD is a TFT display. Do not use gray scaler." /> + <BitField start="6" size="1" name="LCDMONO8" description="Monochrome LCD interface width. Controls whether a monochrome STN LCD uses a 4 or 8-bit parallel interface. It has no meaning in other modes and must be programmed to zero. 0 = monochrome LCD uses a 4-bit interface. 1 = monochrome LCD uses a 8-bit interface." /> + <BitField start="7" size="1" name="LCDDUAL" description="Single or Dual LCD panel selection. STN LCD interface is: 0 = single-panel. 1 = dual-panel." /> + <BitField start="8" size="1" name="BGR" description="Color format selection. 0 = RGB: normal output. 1 = BGR: red and blue swapped." /> + <BitField start="9" size="1" name="BEBO" description="Big-endian Byte Order. Controls byte ordering in memory: 0 = little-endian byte order. 1 = big-endian byte order." /> + <BitField start="10" size="1" name="BEPO" description="Big-Endian Pixel Ordering. Controls pixel ordering within a byte: 0 = little-endian ordering within a byte. 1 = big-endian pixel ordering within a byte. The BEPO bit selects between little and big-endian pixel packing for 1, 2, and 4 bpp display modes, it has no effect on 8 or 16 bpp pixel formats. See Pixel serializer for more information on the data format." /> + <BitField start="11" size="1" name="LCDPWR" description="LCD power enable. 0 = power not gated through to LCD panel and LCD_VD[23:0] signals disabled, (held LOW). 1 = power gated through to LCD panel and LCD_VD[23:0] signals enabled, (active). See LCD power-up and power-down sequence for details on LCD power sequencing." /> + <BitField start="12" size="2" name="LCDVCOMP" description="LCD Vertical Compare Interrupt. Generate VComp interrupt at: 00 = start of vertical synchronization. 01 = start of back porch. 10 = start of active video. 11 = start of front porch." /> + <BitField start="14" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="16" size="1" name="WATERMARK" description="LCD DMA FIFO watermark level. Controls when DMA requests are generated: 0 = An LCD DMA request is generated when either of the DMA FIFOs have four or more empty locations. 1 = An LCD DMA request is generated when either of the DMA FIFOs have eight or more empty locations." /> + <BitField start="17" size="15" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x01C" size="4" name="INTMSK" access="Read/Write" description="Interrupt Mask register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="1" size="1" name="FUFIM" description="FIFO underflow interrupt enable. 0: The FIFO underflow interrupt is disabled. 1: Interrupt will be generated when the FIFO underflows." /> + <BitField start="2" size="1" name="LNBUIM" description="LCD next base address update interrupt enable. 0: The base address update interrupt is disabled. 1: Interrupt will be generated when the LCD base address registers have been updated from the next address registers." /> + <BitField start="3" size="1" name="VCOMPIM" description="Vertical compare interrupt enable. 0: The vertical compare time interrupt is disabled. 1: Interrupt will be generated when the vertical compare time (as defined by LcdVComp field in the LCD_CTRL register) is reached." /> + <BitField start="4" size="1" name="BERIM" description="AHB master error interrupt enable. 0: The AHB Master error interrupt is disabled. 1: Interrupt will be generated when an AHB Master error occurs." /> + <BitField start="5" size="27" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x020" size="4" name="INTRAW" access="ReadOnly" description="Raw Interrupt Status register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="1" size="1" name="FUFRIS" description="FIFO underflow raw interrupt status. Set when either the upper or lower DMA FIFOs have been read accessed when empty causing an underflow condition to occur. Generates an interrupt if the FUFIM bit in the LCD_INTMSK register is set." /> + <BitField start="2" size="1" name="LNBURIS" description="LCD next address base update raw interrupt status. Mode dependent. Set when the current base address registers have been successfully updated by the next address registers. Signifies that a new next address can be loaded if double buffering is in use. Generates an interrupt if the LNBUIM bit in the LCD_INTMSK register is set." /> + <BitField start="3" size="1" name="VCOMPRIS" description="Vertical compare raw interrupt status. Set when one of the four vertical regions is reached, as selected by the LcdVComp bits in the LCD_CTRL register. Generates an interrupt if the VCompIM bit in the LCD_INTMSK register is set." /> + <BitField start="4" size="1" name="BERRAW" description="AHB master bus error raw interrupt status. Set when the AHB master interface receives a bus error response from a slave. Generates an interrupt if the BERIM bit in the LCD_INTMSK register is set." /> + <BitField start="5" size="27" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x024" size="4" name="INTSTAT" access="ReadOnly" description="Masked Interrupt Status register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + <BitField start="1" size="1" name="FUFMIS" description="FIFO underflow masked interrupt status. Set when the both the FUFRIS bit in the LCD_INTRAW register and the FUFIM bit in the LCD_INTMSK register are set." /> + <BitField start="2" size="1" name="LNBUMIS" description="LCD next address base update masked interrupt status. Set when the both the LNBURIS bit in the LCD_INTRAW register and the LNBUIM bit in the LCD_INTMSK register are set." /> + <BitField start="3" size="1" name="VCOMPMIS" description="Vertical compare masked interrupt status. Set when the both the VCompRIS bit in the LCD_INTRAW register and the VCompIM bit in the LCD_INTMSK register are set." /> + <BitField start="4" size="1" name="BERMIS" description="AHB master bus error masked interrupt status. Set when the both the BERRAW bit in the LCD_INTRAW register and the BERIM bit in the LCD_INTMSK register are set." /> + <BitField start="5" size="27" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x028" size="4" name="INTCLR" access="WriteOnly" description="Interrupt Clear register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="1" size="1" name="FUFIC" description="FIFO underflow interrupt clear. Writing a 1 to this bit clears the FIFO underflow interrupt." /> + <BitField start="2" size="1" name="LNBUIC" description="LCD next address base update interrupt clear. Writing a 1 to this bit clears the LCD next address base update interrupt." /> + <BitField start="3" size="1" name="VCOMPIC" description="Vertical compare interrupt clear. Writing a 1 to this bit clears the vertical compare interrupt." /> + <BitField start="4" size="1" name="BERIC" description="AHB master error interrupt clear. Writing a 1 to this bit clears the AHB master error interrupt." /> + <BitField start="5" size="27" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x02C" size="4" name="UPCURR" access="ReadOnly" description="Upper Panel Current Address Value register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="LCDUPCURR" description="LCD Upper Panel Current Address. Contains the current LCD upper panel data DMA address." /> + </Register> + <Register start="+0x030" size="4" name="LPCURR" access="ReadOnly" description="Lower Panel Current Address Value register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="LCDLPCURR" description="LCD Lower Panel Current Address. Contains the current LCD lower panel data DMA address." /> + </Register> + <Register start="+0x200+0" size="4" name="PAL[0]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="5" size="5" name="G04_0" description="Green palette data." /> + <BitField start="10" size="5" name="B04_0" description="Blue palette data." /> + <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="21" size="5" name="G14_0" description="Green palette data." /> + <BitField start="26" size="5" name="B14_0" description="Blue palette data." /> + <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + </Register> + <Register start="+0x200+4" size="4" name="PAL[1]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="5" size="5" name="G04_0" description="Green palette data." /> + <BitField start="10" size="5" name="B04_0" description="Blue palette data." /> + <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="21" size="5" name="G14_0" description="Green palette data." /> + <BitField start="26" size="5" name="B14_0" description="Blue palette data." /> + <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + </Register> + <Register start="+0x200+8" size="4" name="PAL[2]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="5" size="5" name="G04_0" description="Green palette data." /> + <BitField start="10" size="5" name="B04_0" description="Blue palette data." /> + <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="21" size="5" name="G14_0" description="Green palette data." /> + <BitField start="26" size="5" name="B14_0" description="Blue palette data." /> + <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + </Register> + <Register start="+0x200+12" size="4" name="PAL[3]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="5" size="5" name="G04_0" description="Green palette data." /> + <BitField start="10" size="5" name="B04_0" description="Blue palette data." /> + <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="21" size="5" name="G14_0" description="Green palette data." /> + <BitField start="26" size="5" name="B14_0" description="Blue palette data." /> + <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + </Register> + <Register start="+0x200+16" size="4" name="PAL[4]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="5" size="5" name="G04_0" description="Green palette data." /> + <BitField start="10" size="5" name="B04_0" description="Blue palette data." /> + <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="21" size="5" name="G14_0" description="Green palette data." /> + <BitField start="26" size="5" name="B14_0" description="Blue palette data." /> + <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + </Register> + <Register start="+0x200+20" size="4" name="PAL[5]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="5" size="5" name="G04_0" description="Green palette data." /> + <BitField start="10" size="5" name="B04_0" description="Blue palette data." /> + <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="21" size="5" name="G14_0" description="Green palette data." /> + <BitField start="26" size="5" name="B14_0" description="Blue palette data." /> + <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + </Register> + <Register start="+0x200+24" size="4" name="PAL[6]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="5" size="5" name="G04_0" description="Green palette data." /> + <BitField start="10" size="5" name="B04_0" description="Blue palette data." /> + <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="21" size="5" name="G14_0" description="Green palette data." /> + <BitField start="26" size="5" name="B14_0" description="Blue palette data." /> + <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + </Register> + <Register start="+0x200+28" size="4" name="PAL[7]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="5" size="5" name="G04_0" description="Green palette data." /> + <BitField start="10" size="5" name="B04_0" description="Blue palette data." /> + <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="21" size="5" name="G14_0" description="Green palette data." /> + <BitField start="26" size="5" name="B14_0" description="Blue palette data." /> + <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + </Register> + <Register start="+0x200+32" size="4" name="PAL[8]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="5" size="5" name="G04_0" description="Green palette data." /> + <BitField start="10" size="5" name="B04_0" description="Blue palette data." /> + <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="21" size="5" name="G14_0" description="Green palette data." /> + <BitField start="26" size="5" name="B14_0" description="Blue palette data." /> + <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + </Register> + <Register start="+0x200+36" size="4" name="PAL[9]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="5" size="5" name="G04_0" description="Green palette data." /> + <BitField start="10" size="5" name="B04_0" description="Blue palette data." /> + <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="21" size="5" name="G14_0" description="Green palette data." /> + <BitField start="26" size="5" name="B14_0" description="Blue palette data." /> + <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + </Register> + <Register start="+0x200+40" size="4" name="PAL[10]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="5" size="5" name="G04_0" description="Green palette data." /> + <BitField start="10" size="5" name="B04_0" description="Blue palette data." /> + <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="21" size="5" name="G14_0" description="Green palette data." /> + <BitField start="26" size="5" name="B14_0" description="Blue palette data." /> + <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + </Register> + <Register start="+0x200+44" size="4" name="PAL[11]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="5" size="5" name="G04_0" description="Green palette data." /> + <BitField start="10" size="5" name="B04_0" description="Blue palette data." /> + <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="21" size="5" name="G14_0" description="Green palette data." /> + <BitField start="26" size="5" name="B14_0" description="Blue palette data." /> + <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + </Register> + <Register start="+0x200+48" size="4" name="PAL[12]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="5" size="5" name="G04_0" description="Green palette data." /> + <BitField start="10" size="5" name="B04_0" description="Blue palette data." /> + <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="21" size="5" name="G14_0" description="Green palette data." /> + <BitField start="26" size="5" name="B14_0" description="Blue palette data." /> + <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + </Register> + <Register start="+0x200+52" size="4" name="PAL[13]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="5" size="5" name="G04_0" description="Green palette data." /> + <BitField start="10" size="5" name="B04_0" description="Blue palette data." /> + <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="21" size="5" name="G14_0" description="Green palette data." /> + <BitField start="26" size="5" name="B14_0" description="Blue palette data." /> + <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + </Register> + <Register start="+0x200+56" size="4" name="PAL[14]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="5" size="5" name="G04_0" description="Green palette data." /> + <BitField start="10" size="5" name="B04_0" description="Blue palette data." /> + <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="21" size="5" name="G14_0" description="Green palette data." /> + <BitField start="26" size="5" name="B14_0" description="Blue palette data." /> + <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + </Register> + <Register start="+0x200+60" size="4" name="PAL[15]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="5" size="5" name="G04_0" description="Green palette data." /> + <BitField start="10" size="5" name="B04_0" description="Blue palette data." /> + <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="21" size="5" name="G14_0" description="Green palette data." /> + <BitField start="26" size="5" name="B14_0" description="Blue palette data." /> + <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + </Register> + <Register start="+0x200+64" size="4" name="PAL[16]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="5" size="5" name="G04_0" description="Green palette data." /> + <BitField start="10" size="5" name="B04_0" description="Blue palette data." /> + <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="21" size="5" name="G14_0" description="Green palette data." /> + <BitField start="26" size="5" name="B14_0" description="Blue palette data." /> + <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + </Register> + <Register start="+0x200+68" size="4" name="PAL[17]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="5" size="5" name="G04_0" description="Green palette data." /> + <BitField start="10" size="5" name="B04_0" description="Blue palette data." /> + <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="21" size="5" name="G14_0" description="Green palette data." /> + <BitField start="26" size="5" name="B14_0" description="Blue palette data." /> + <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + </Register> + <Register start="+0x200+72" size="4" name="PAL[18]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="5" size="5" name="G04_0" description="Green palette data." /> + <BitField start="10" size="5" name="B04_0" description="Blue palette data." /> + <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="21" size="5" name="G14_0" description="Green palette data." /> + <BitField start="26" size="5" name="B14_0" description="Blue palette data." /> + <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + </Register> + <Register start="+0x200+76" size="4" name="PAL[19]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="5" size="5" name="G04_0" description="Green palette data." /> + <BitField start="10" size="5" name="B04_0" description="Blue palette data." /> + <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="21" size="5" name="G14_0" description="Green palette data." /> + <BitField start="26" size="5" name="B14_0" description="Blue palette data." /> + <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + </Register> + <Register start="+0x200+80" size="4" name="PAL[20]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="5" size="5" name="G04_0" description="Green palette data." /> + <BitField start="10" size="5" name="B04_0" description="Blue palette data." /> + <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="21" size="5" name="G14_0" description="Green palette data." /> + <BitField start="26" size="5" name="B14_0" description="Blue palette data." /> + <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + </Register> + <Register start="+0x200+84" size="4" name="PAL[21]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="5" size="5" name="G04_0" description="Green palette data." /> + <BitField start="10" size="5" name="B04_0" description="Blue palette data." /> + <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="21" size="5" name="G14_0" description="Green palette data." /> + <BitField start="26" size="5" name="B14_0" description="Blue palette data." /> + <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + </Register> + <Register start="+0x200+88" size="4" name="PAL[22]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="5" size="5" name="G04_0" description="Green palette data." /> + <BitField start="10" size="5" name="B04_0" description="Blue palette data." /> + <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="21" size="5" name="G14_0" description="Green palette data." /> + <BitField start="26" size="5" name="B14_0" description="Blue palette data." /> + <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + </Register> + <Register start="+0x200+92" size="4" name="PAL[23]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="5" size="5" name="G04_0" description="Green palette data." /> + <BitField start="10" size="5" name="B04_0" description="Blue palette data." /> + <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="21" size="5" name="G14_0" description="Green palette data." /> + <BitField start="26" size="5" name="B14_0" description="Blue palette data." /> + <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + </Register> + <Register start="+0x200+96" size="4" name="PAL[24]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="5" size="5" name="G04_0" description="Green palette data." /> + <BitField start="10" size="5" name="B04_0" description="Blue palette data." /> + <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="21" size="5" name="G14_0" description="Green palette data." /> + <BitField start="26" size="5" name="B14_0" description="Blue palette data." /> + <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + </Register> + <Register start="+0x200+100" size="4" name="PAL[25]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="5" size="5" name="G04_0" description="Green palette data." /> + <BitField start="10" size="5" name="B04_0" description="Blue palette data." /> + <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="21" size="5" name="G14_0" description="Green palette data." /> + <BitField start="26" size="5" name="B14_0" description="Blue palette data." /> + <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + </Register> + <Register start="+0x200+104" size="4" name="PAL[26]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="5" size="5" name="G04_0" description="Green palette data." /> + <BitField start="10" size="5" name="B04_0" description="Blue palette data." /> + <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="21" size="5" name="G14_0" description="Green palette data." /> + <BitField start="26" size="5" name="B14_0" description="Blue palette data." /> + <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + </Register> + <Register start="+0x200+108" size="4" name="PAL[27]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="5" size="5" name="G04_0" description="Green palette data." /> + <BitField start="10" size="5" name="B04_0" description="Blue palette data." /> + <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="21" size="5" name="G14_0" description="Green palette data." /> + <BitField start="26" size="5" name="B14_0" description="Blue palette data." /> + <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + </Register> + <Register start="+0x200+112" size="4" name="PAL[28]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="5" size="5" name="G04_0" description="Green palette data." /> + <BitField start="10" size="5" name="B04_0" description="Blue palette data." /> + <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="21" size="5" name="G14_0" description="Green palette data." /> + <BitField start="26" size="5" name="B14_0" description="Blue palette data." /> + <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + </Register> + <Register start="+0x200+116" size="4" name="PAL[29]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="5" size="5" name="G04_0" description="Green palette data." /> + <BitField start="10" size="5" name="B04_0" description="Blue palette data." /> + <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="21" size="5" name="G14_0" description="Green palette data." /> + <BitField start="26" size="5" name="B14_0" description="Blue palette data." /> + <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + </Register> + <Register start="+0x200+120" size="4" name="PAL[30]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="5" size="5" name="G04_0" description="Green palette data." /> + <BitField start="10" size="5" name="B04_0" description="Blue palette data." /> + <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="21" size="5" name="G14_0" description="Green palette data." /> + <BitField start="26" size="5" name="B14_0" description="Blue palette data." /> + <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + </Register> + <Register start="+0x200+124" size="4" name="PAL[31]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="5" size="5" name="G04_0" description="Green palette data." /> + <BitField start="10" size="5" name="B04_0" description="Blue palette data." /> + <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="21" size="5" name="G14_0" description="Green palette data." /> + <BitField start="26" size="5" name="B14_0" description="Blue palette data." /> + <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + </Register> + <Register start="+0x200+128" size="4" name="PAL[32]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="5" size="5" name="G04_0" description="Green palette data." /> + <BitField start="10" size="5" name="B04_0" description="Blue palette data." /> + <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="21" size="5" name="G14_0" description="Green palette data." /> + <BitField start="26" size="5" name="B14_0" description="Blue palette data." /> + <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + </Register> + <Register start="+0x200+132" size="4" name="PAL[33]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="5" size="5" name="G04_0" description="Green palette data." /> + <BitField start="10" size="5" name="B04_0" description="Blue palette data." /> + <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="21" size="5" name="G14_0" description="Green palette data." /> + <BitField start="26" size="5" name="B14_0" description="Blue palette data." /> + <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + </Register> + <Register start="+0x200+136" size="4" name="PAL[34]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="5" size="5" name="G04_0" description="Green palette data." /> + <BitField start="10" size="5" name="B04_0" description="Blue palette data." /> + <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="21" size="5" name="G14_0" description="Green palette data." /> + <BitField start="26" size="5" name="B14_0" description="Blue palette data." /> + <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + </Register> + <Register start="+0x200+140" size="4" name="PAL[35]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="5" size="5" name="G04_0" description="Green palette data." /> + <BitField start="10" size="5" name="B04_0" description="Blue palette data." /> + <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="21" size="5" name="G14_0" description="Green palette data." /> + <BitField start="26" size="5" name="B14_0" description="Blue palette data." /> + <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + </Register> + <Register start="+0x200+144" size="4" name="PAL[36]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="5" size="5" name="G04_0" description="Green palette data." /> + <BitField start="10" size="5" name="B04_0" description="Blue palette data." /> + <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="21" size="5" name="G14_0" description="Green palette data." /> + <BitField start="26" size="5" name="B14_0" description="Blue palette data." /> + <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + </Register> + <Register start="+0x200+148" size="4" name="PAL[37]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="5" size="5" name="G04_0" description="Green palette data." /> + <BitField start="10" size="5" name="B04_0" description="Blue palette data." /> + <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="21" size="5" name="G14_0" description="Green palette data." /> + <BitField start="26" size="5" name="B14_0" description="Blue palette data." /> + <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + </Register> + <Register start="+0x200+152" size="4" name="PAL[38]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="5" size="5" name="G04_0" description="Green palette data." /> + <BitField start="10" size="5" name="B04_0" description="Blue palette data." /> + <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="21" size="5" name="G14_0" description="Green palette data." /> + <BitField start="26" size="5" name="B14_0" description="Blue palette data." /> + <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + </Register> + <Register start="+0x200+156" size="4" name="PAL[39]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="5" size="5" name="G04_0" description="Green palette data." /> + <BitField start="10" size="5" name="B04_0" description="Blue palette data." /> + <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="21" size="5" name="G14_0" description="Green palette data." /> + <BitField start="26" size="5" name="B14_0" description="Blue palette data." /> + <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + </Register> + <Register start="+0x200+160" size="4" name="PAL[40]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="5" size="5" name="G04_0" description="Green palette data." /> + <BitField start="10" size="5" name="B04_0" description="Blue palette data." /> + <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="21" size="5" name="G14_0" description="Green palette data." /> + <BitField start="26" size="5" name="B14_0" description="Blue palette data." /> + <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + </Register> + <Register start="+0x200+164" size="4" name="PAL[41]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="5" size="5" name="G04_0" description="Green palette data." /> + <BitField start="10" size="5" name="B04_0" description="Blue palette data." /> + <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="21" size="5" name="G14_0" description="Green palette data." /> + <BitField start="26" size="5" name="B14_0" description="Blue palette data." /> + <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + </Register> + <Register start="+0x200+168" size="4" name="PAL[42]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="5" size="5" name="G04_0" description="Green palette data." /> + <BitField start="10" size="5" name="B04_0" description="Blue palette data." /> + <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="21" size="5" name="G14_0" description="Green palette data." /> + <BitField start="26" size="5" name="B14_0" description="Blue palette data." /> + <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + </Register> + <Register start="+0x200+172" size="4" name="PAL[43]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="5" size="5" name="G04_0" description="Green palette data." /> + <BitField start="10" size="5" name="B04_0" description="Blue palette data." /> + <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="21" size="5" name="G14_0" description="Green palette data." /> + <BitField start="26" size="5" name="B14_0" description="Blue palette data." /> + <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + </Register> + <Register start="+0x200+176" size="4" name="PAL[44]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="5" size="5" name="G04_0" description="Green palette data." /> + <BitField start="10" size="5" name="B04_0" description="Blue palette data." /> + <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="21" size="5" name="G14_0" description="Green palette data." /> + <BitField start="26" size="5" name="B14_0" description="Blue palette data." /> + <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + </Register> + <Register start="+0x200+180" size="4" name="PAL[45]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="5" size="5" name="G04_0" description="Green palette data." /> + <BitField start="10" size="5" name="B04_0" description="Blue palette data." /> + <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="21" size="5" name="G14_0" description="Green palette data." /> + <BitField start="26" size="5" name="B14_0" description="Blue palette data." /> + <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + </Register> + <Register start="+0x200+184" size="4" name="PAL[46]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="5" size="5" name="G04_0" description="Green palette data." /> + <BitField start="10" size="5" name="B04_0" description="Blue palette data." /> + <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="21" size="5" name="G14_0" description="Green palette data." /> + <BitField start="26" size="5" name="B14_0" description="Blue palette data." /> + <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + </Register> + <Register start="+0x200+188" size="4" name="PAL[47]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="5" size="5" name="G04_0" description="Green palette data." /> + <BitField start="10" size="5" name="B04_0" description="Blue palette data." /> + <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="21" size="5" name="G14_0" description="Green palette data." /> + <BitField start="26" size="5" name="B14_0" description="Blue palette data." /> + <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + </Register> + <Register start="+0x200+192" size="4" name="PAL[48]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="5" size="5" name="G04_0" description="Green palette data." /> + <BitField start="10" size="5" name="B04_0" description="Blue palette data." /> + <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="21" size="5" name="G14_0" description="Green palette data." /> + <BitField start="26" size="5" name="B14_0" description="Blue palette data." /> + <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + </Register> + <Register start="+0x200+196" size="4" name="PAL[49]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="5" size="5" name="G04_0" description="Green palette data." /> + <BitField start="10" size="5" name="B04_0" description="Blue palette data." /> + <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="21" size="5" name="G14_0" description="Green palette data." /> + <BitField start="26" size="5" name="B14_0" description="Blue palette data." /> + <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + </Register> + <Register start="+0x200+200" size="4" name="PAL[50]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="5" size="5" name="G04_0" description="Green palette data." /> + <BitField start="10" size="5" name="B04_0" description="Blue palette data." /> + <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="21" size="5" name="G14_0" description="Green palette data." /> + <BitField start="26" size="5" name="B14_0" description="Blue palette data." /> + <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + </Register> + <Register start="+0x200+204" size="4" name="PAL[51]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="5" size="5" name="G04_0" description="Green palette data." /> + <BitField start="10" size="5" name="B04_0" description="Blue palette data." /> + <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="21" size="5" name="G14_0" description="Green palette data." /> + <BitField start="26" size="5" name="B14_0" description="Blue palette data." /> + <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + </Register> + <Register start="+0x200+208" size="4" name="PAL[52]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="5" size="5" name="G04_0" description="Green palette data." /> + <BitField start="10" size="5" name="B04_0" description="Blue palette data." /> + <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="21" size="5" name="G14_0" description="Green palette data." /> + <BitField start="26" size="5" name="B14_0" description="Blue palette data." /> + <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + </Register> + <Register start="+0x200+212" size="4" name="PAL[53]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="5" size="5" name="G04_0" description="Green palette data." /> + <BitField start="10" size="5" name="B04_0" description="Blue palette data." /> + <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="21" size="5" name="G14_0" description="Green palette data." /> + <BitField start="26" size="5" name="B14_0" description="Blue palette data." /> + <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + </Register> + <Register start="+0x200+216" size="4" name="PAL[54]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="5" size="5" name="G04_0" description="Green palette data." /> + <BitField start="10" size="5" name="B04_0" description="Blue palette data." /> + <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="21" size="5" name="G14_0" description="Green palette data." /> + <BitField start="26" size="5" name="B14_0" description="Blue palette data." /> + <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + </Register> + <Register start="+0x200+220" size="4" name="PAL[55]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="5" size="5" name="G04_0" description="Green palette data." /> + <BitField start="10" size="5" name="B04_0" description="Blue palette data." /> + <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="21" size="5" name="G14_0" description="Green palette data." /> + <BitField start="26" size="5" name="B14_0" description="Blue palette data." /> + <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + </Register> + <Register start="+0x200+224" size="4" name="PAL[56]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="5" size="5" name="G04_0" description="Green palette data." /> + <BitField start="10" size="5" name="B04_0" description="Blue palette data." /> + <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="21" size="5" name="G14_0" description="Green palette data." /> + <BitField start="26" size="5" name="B14_0" description="Blue palette data." /> + <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + </Register> + <Register start="+0x200+228" size="4" name="PAL[57]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="5" size="5" name="G04_0" description="Green palette data." /> + <BitField start="10" size="5" name="B04_0" description="Blue palette data." /> + <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="21" size="5" name="G14_0" description="Green palette data." /> + <BitField start="26" size="5" name="B14_0" description="Blue palette data." /> + <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + </Register> + <Register start="+0x200+232" size="4" name="PAL[58]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="5" size="5" name="G04_0" description="Green palette data." /> + <BitField start="10" size="5" name="B04_0" description="Blue palette data." /> + <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="21" size="5" name="G14_0" description="Green palette data." /> + <BitField start="26" size="5" name="B14_0" description="Blue palette data." /> + <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + </Register> + <Register start="+0x200+236" size="4" name="PAL[59]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="5" size="5" name="G04_0" description="Green palette data." /> + <BitField start="10" size="5" name="B04_0" description="Blue palette data." /> + <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="21" size="5" name="G14_0" description="Green palette data." /> + <BitField start="26" size="5" name="B14_0" description="Blue palette data." /> + <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + </Register> + <Register start="+0x200+240" size="4" name="PAL[60]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="5" size="5" name="G04_0" description="Green palette data." /> + <BitField start="10" size="5" name="B04_0" description="Blue palette data." /> + <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="21" size="5" name="G14_0" description="Green palette data." /> + <BitField start="26" size="5" name="B14_0" description="Blue palette data." /> + <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + </Register> + <Register start="+0x200+244" size="4" name="PAL[61]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="5" size="5" name="G04_0" description="Green palette data." /> + <BitField start="10" size="5" name="B04_0" description="Blue palette data." /> + <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="21" size="5" name="G14_0" description="Green palette data." /> + <BitField start="26" size="5" name="B14_0" description="Blue palette data." /> + <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + </Register> + <Register start="+0x200+248" size="4" name="PAL[62]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="5" size="5" name="G04_0" description="Green palette data." /> + <BitField start="10" size="5" name="B04_0" description="Blue palette data." /> + <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="21" size="5" name="G14_0" description="Green palette data." /> + <BitField start="26" size="5" name="B14_0" description="Blue palette data." /> + <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + </Register> + <Register start="+0x200+252" size="4" name="PAL[63]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="5" size="5" name="G04_0" description="Green palette data." /> + <BitField start="10" size="5" name="B04_0" description="Blue palette data." /> + <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="21" size="5" name="G14_0" description="Green palette data." /> + <BitField start="26" size="5" name="B14_0" description="Blue palette data." /> + <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + </Register> + <Register start="+0x200+256" size="4" name="PAL[64]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="5" size="5" name="G04_0" description="Green palette data." /> + <BitField start="10" size="5" name="B04_0" description="Blue palette data." /> + <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="21" size="5" name="G14_0" description="Green palette data." /> + <BitField start="26" size="5" name="B14_0" description="Blue palette data." /> + <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + </Register> + <Register start="+0x200+260" size="4" name="PAL[65]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="5" size="5" name="G04_0" description="Green palette data." /> + <BitField start="10" size="5" name="B04_0" description="Blue palette data." /> + <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="21" size="5" name="G14_0" description="Green palette data." /> + <BitField start="26" size="5" name="B14_0" description="Blue palette data." /> + <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + </Register> + <Register start="+0x200+264" size="4" name="PAL[66]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="5" size="5" name="G04_0" description="Green palette data." /> + <BitField start="10" size="5" name="B04_0" description="Blue palette data." /> + <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="21" size="5" name="G14_0" description="Green palette data." /> + <BitField start="26" size="5" name="B14_0" description="Blue palette data." /> + <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + </Register> + <Register start="+0x200+268" size="4" name="PAL[67]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="5" size="5" name="G04_0" description="Green palette data." /> + <BitField start="10" size="5" name="B04_0" description="Blue palette data." /> + <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="21" size="5" name="G14_0" description="Green palette data." /> + <BitField start="26" size="5" name="B14_0" description="Blue palette data." /> + <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + </Register> + <Register start="+0x200+272" size="4" name="PAL[68]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="5" size="5" name="G04_0" description="Green palette data." /> + <BitField start="10" size="5" name="B04_0" description="Blue palette data." /> + <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="21" size="5" name="G14_0" description="Green palette data." /> + <BitField start="26" size="5" name="B14_0" description="Blue palette data." /> + <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + </Register> + <Register start="+0x200+276" size="4" name="PAL[69]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="5" size="5" name="G04_0" description="Green palette data." /> + <BitField start="10" size="5" name="B04_0" description="Blue palette data." /> + <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="21" size="5" name="G14_0" description="Green palette data." /> + <BitField start="26" size="5" name="B14_0" description="Blue palette data." /> + <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + </Register> + <Register start="+0x200+280" size="4" name="PAL[70]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="5" size="5" name="G04_0" description="Green palette data." /> + <BitField start="10" size="5" name="B04_0" description="Blue palette data." /> + <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="21" size="5" name="G14_0" description="Green palette data." /> + <BitField start="26" size="5" name="B14_0" description="Blue palette data." /> + <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + </Register> + <Register start="+0x200+284" size="4" name="PAL[71]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="5" size="5" name="G04_0" description="Green palette data." /> + <BitField start="10" size="5" name="B04_0" description="Blue palette data." /> + <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="21" size="5" name="G14_0" description="Green palette data." /> + <BitField start="26" size="5" name="B14_0" description="Blue palette data." /> + <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + </Register> + <Register start="+0x200+288" size="4" name="PAL[72]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="5" size="5" name="G04_0" description="Green palette data." /> + <BitField start="10" size="5" name="B04_0" description="Blue palette data." /> + <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="21" size="5" name="G14_0" description="Green palette data." /> + <BitField start="26" size="5" name="B14_0" description="Blue palette data." /> + <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + </Register> + <Register start="+0x200+292" size="4" name="PAL[73]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="5" size="5" name="G04_0" description="Green palette data." /> + <BitField start="10" size="5" name="B04_0" description="Blue palette data." /> + <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="21" size="5" name="G14_0" description="Green palette data." /> + <BitField start="26" size="5" name="B14_0" description="Blue palette data." /> + <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + </Register> + <Register start="+0x200+296" size="4" name="PAL[74]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="5" size="5" name="G04_0" description="Green palette data." /> + <BitField start="10" size="5" name="B04_0" description="Blue palette data." /> + <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="21" size="5" name="G14_0" description="Green palette data." /> + <BitField start="26" size="5" name="B14_0" description="Blue palette data." /> + <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + </Register> + <Register start="+0x200+300" size="4" name="PAL[75]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="5" size="5" name="G04_0" description="Green palette data." /> + <BitField start="10" size="5" name="B04_0" description="Blue palette data." /> + <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="21" size="5" name="G14_0" description="Green palette data." /> + <BitField start="26" size="5" name="B14_0" description="Blue palette data." /> + <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + </Register> + <Register start="+0x200+304" size="4" name="PAL[76]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="5" size="5" name="G04_0" description="Green palette data." /> + <BitField start="10" size="5" name="B04_0" description="Blue palette data." /> + <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="21" size="5" name="G14_0" description="Green palette data." /> + <BitField start="26" size="5" name="B14_0" description="Blue palette data." /> + <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + </Register> + <Register start="+0x200+308" size="4" name="PAL[77]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="5" size="5" name="G04_0" description="Green palette data." /> + <BitField start="10" size="5" name="B04_0" description="Blue palette data." /> + <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="21" size="5" name="G14_0" description="Green palette data." /> + <BitField start="26" size="5" name="B14_0" description="Blue palette data." /> + <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + </Register> + <Register start="+0x200+312" size="4" name="PAL[78]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="5" size="5" name="G04_0" description="Green palette data." /> + <BitField start="10" size="5" name="B04_0" description="Blue palette data." /> + <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="21" size="5" name="G14_0" description="Green palette data." /> + <BitField start="26" size="5" name="B14_0" description="Blue palette data." /> + <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + </Register> + <Register start="+0x200+316" size="4" name="PAL[79]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="5" size="5" name="G04_0" description="Green palette data." /> + <BitField start="10" size="5" name="B04_0" description="Blue palette data." /> + <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="21" size="5" name="G14_0" description="Green palette data." /> + <BitField start="26" size="5" name="B14_0" description="Blue palette data." /> + <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + </Register> + <Register start="+0x200+320" size="4" name="PAL[80]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="5" size="5" name="G04_0" description="Green palette data." /> + <BitField start="10" size="5" name="B04_0" description="Blue palette data." /> + <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="21" size="5" name="G14_0" description="Green palette data." /> + <BitField start="26" size="5" name="B14_0" description="Blue palette data." /> + <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + </Register> + <Register start="+0x200+324" size="4" name="PAL[81]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="5" size="5" name="G04_0" description="Green palette data." /> + <BitField start="10" size="5" name="B04_0" description="Blue palette data." /> + <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="21" size="5" name="G14_0" description="Green palette data." /> + <BitField start="26" size="5" name="B14_0" description="Blue palette data." /> + <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + </Register> + <Register start="+0x200+328" size="4" name="PAL[82]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="5" size="5" name="G04_0" description="Green palette data." /> + <BitField start="10" size="5" name="B04_0" description="Blue palette data." /> + <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="21" size="5" name="G14_0" description="Green palette data." /> + <BitField start="26" size="5" name="B14_0" description="Blue palette data." /> + <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + </Register> + <Register start="+0x200+332" size="4" name="PAL[83]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="5" size="5" name="G04_0" description="Green palette data." /> + <BitField start="10" size="5" name="B04_0" description="Blue palette data." /> + <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="21" size="5" name="G14_0" description="Green palette data." /> + <BitField start="26" size="5" name="B14_0" description="Blue palette data." /> + <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + </Register> + <Register start="+0x200+336" size="4" name="PAL[84]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="5" size="5" name="G04_0" description="Green palette data." /> + <BitField start="10" size="5" name="B04_0" description="Blue palette data." /> + <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="21" size="5" name="G14_0" description="Green palette data." /> + <BitField start="26" size="5" name="B14_0" description="Blue palette data." /> + <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + </Register> + <Register start="+0x200+340" size="4" name="PAL[85]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="5" size="5" name="G04_0" description="Green palette data." /> + <BitField start="10" size="5" name="B04_0" description="Blue palette data." /> + <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="21" size="5" name="G14_0" description="Green palette data." /> + <BitField start="26" size="5" name="B14_0" description="Blue palette data." /> + <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + </Register> + <Register start="+0x200+344" size="4" name="PAL[86]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="5" size="5" name="G04_0" description="Green palette data." /> + <BitField start="10" size="5" name="B04_0" description="Blue palette data." /> + <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="21" size="5" name="G14_0" description="Green palette data." /> + <BitField start="26" size="5" name="B14_0" description="Blue palette data." /> + <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + </Register> + <Register start="+0x200+348" size="4" name="PAL[87]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="5" size="5" name="G04_0" description="Green palette data." /> + <BitField start="10" size="5" name="B04_0" description="Blue palette data." /> + <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="21" size="5" name="G14_0" description="Green palette data." /> + <BitField start="26" size="5" name="B14_0" description="Blue palette data." /> + <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + </Register> + <Register start="+0x200+352" size="4" name="PAL[88]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="5" size="5" name="G04_0" description="Green palette data." /> + <BitField start="10" size="5" name="B04_0" description="Blue palette data." /> + <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="21" size="5" name="G14_0" description="Green palette data." /> + <BitField start="26" size="5" name="B14_0" description="Blue palette data." /> + <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + </Register> + <Register start="+0x200+356" size="4" name="PAL[89]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="5" size="5" name="G04_0" description="Green palette data." /> + <BitField start="10" size="5" name="B04_0" description="Blue palette data." /> + <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="21" size="5" name="G14_0" description="Green palette data." /> + <BitField start="26" size="5" name="B14_0" description="Blue palette data." /> + <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + </Register> + <Register start="+0x200+360" size="4" name="PAL[90]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="5" size="5" name="G04_0" description="Green palette data." /> + <BitField start="10" size="5" name="B04_0" description="Blue palette data." /> + <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="21" size="5" name="G14_0" description="Green palette data." /> + <BitField start="26" size="5" name="B14_0" description="Blue palette data." /> + <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + </Register> + <Register start="+0x200+364" size="4" name="PAL[91]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="5" size="5" name="G04_0" description="Green palette data." /> + <BitField start="10" size="5" name="B04_0" description="Blue palette data." /> + <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="21" size="5" name="G14_0" description="Green palette data." /> + <BitField start="26" size="5" name="B14_0" description="Blue palette data." /> + <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + </Register> + <Register start="+0x200+368" size="4" name="PAL[92]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="5" size="5" name="G04_0" description="Green palette data." /> + <BitField start="10" size="5" name="B04_0" description="Blue palette data." /> + <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="21" size="5" name="G14_0" description="Green palette data." /> + <BitField start="26" size="5" name="B14_0" description="Blue palette data." /> + <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + </Register> + <Register start="+0x200+372" size="4" name="PAL[93]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="5" size="5" name="G04_0" description="Green palette data." /> + <BitField start="10" size="5" name="B04_0" description="Blue palette data." /> + <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="21" size="5" name="G14_0" description="Green palette data." /> + <BitField start="26" size="5" name="B14_0" description="Blue palette data." /> + <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + </Register> + <Register start="+0x200+376" size="4" name="PAL[94]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="5" size="5" name="G04_0" description="Green palette data." /> + <BitField start="10" size="5" name="B04_0" description="Blue palette data." /> + <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="21" size="5" name="G14_0" description="Green palette data." /> + <BitField start="26" size="5" name="B14_0" description="Blue palette data." /> + <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + </Register> + <Register start="+0x200+380" size="4" name="PAL[95]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="5" size="5" name="G04_0" description="Green palette data." /> + <BitField start="10" size="5" name="B04_0" description="Blue palette data." /> + <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="21" size="5" name="G14_0" description="Green palette data." /> + <BitField start="26" size="5" name="B14_0" description="Blue palette data." /> + <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + </Register> + <Register start="+0x200+384" size="4" name="PAL[96]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="5" size="5" name="G04_0" description="Green palette data." /> + <BitField start="10" size="5" name="B04_0" description="Blue palette data." /> + <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="21" size="5" name="G14_0" description="Green palette data." /> + <BitField start="26" size="5" name="B14_0" description="Blue palette data." /> + <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + </Register> + <Register start="+0x200+388" size="4" name="PAL[97]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="5" size="5" name="G04_0" description="Green palette data." /> + <BitField start="10" size="5" name="B04_0" description="Blue palette data." /> + <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="21" size="5" name="G14_0" description="Green palette data." /> + <BitField start="26" size="5" name="B14_0" description="Blue palette data." /> + <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + </Register> + <Register start="+0x200+392" size="4" name="PAL[98]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="5" size="5" name="G04_0" description="Green palette data." /> + <BitField start="10" size="5" name="B04_0" description="Blue palette data." /> + <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="21" size="5" name="G14_0" description="Green palette data." /> + <BitField start="26" size="5" name="B14_0" description="Blue palette data." /> + <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + </Register> + <Register start="+0x200+396" size="4" name="PAL[99]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="5" size="5" name="G04_0" description="Green palette data." /> + <BitField start="10" size="5" name="B04_0" description="Blue palette data." /> + <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="21" size="5" name="G14_0" description="Green palette data." /> + <BitField start="26" size="5" name="B14_0" description="Blue palette data." /> + <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + </Register> + <Register start="+0x200+400" size="4" name="PAL[100]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="5" size="5" name="G04_0" description="Green palette data." /> + <BitField start="10" size="5" name="B04_0" description="Blue palette data." /> + <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="21" size="5" name="G14_0" description="Green palette data." /> + <BitField start="26" size="5" name="B14_0" description="Blue palette data." /> + <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + </Register> + <Register start="+0x200+404" size="4" name="PAL[101]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="5" size="5" name="G04_0" description="Green palette data." /> + <BitField start="10" size="5" name="B04_0" description="Blue palette data." /> + <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="21" size="5" name="G14_0" description="Green palette data." /> + <BitField start="26" size="5" name="B14_0" description="Blue palette data." /> + <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + </Register> + <Register start="+0x200+408" size="4" name="PAL[102]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="5" size="5" name="G04_0" description="Green palette data." /> + <BitField start="10" size="5" name="B04_0" description="Blue palette data." /> + <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="21" size="5" name="G14_0" description="Green palette data." /> + <BitField start="26" size="5" name="B14_0" description="Blue palette data." /> + <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + </Register> + <Register start="+0x200+412" size="4" name="PAL[103]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="5" size="5" name="G04_0" description="Green palette data." /> + <BitField start="10" size="5" name="B04_0" description="Blue palette data." /> + <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="21" size="5" name="G14_0" description="Green palette data." /> + <BitField start="26" size="5" name="B14_0" description="Blue palette data." /> + <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + </Register> + <Register start="+0x200+416" size="4" name="PAL[104]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="5" size="5" name="G04_0" description="Green palette data." /> + <BitField start="10" size="5" name="B04_0" description="Blue palette data." /> + <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="21" size="5" name="G14_0" description="Green palette data." /> + <BitField start="26" size="5" name="B14_0" description="Blue palette data." /> + <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + </Register> + <Register start="+0x200+420" size="4" name="PAL[105]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="5" size="5" name="G04_0" description="Green palette data." /> + <BitField start="10" size="5" name="B04_0" description="Blue palette data." /> + <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="21" size="5" name="G14_0" description="Green palette data." /> + <BitField start="26" size="5" name="B14_0" description="Blue palette data." /> + <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + </Register> + <Register start="+0x200+424" size="4" name="PAL[106]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="5" size="5" name="G04_0" description="Green palette data." /> + <BitField start="10" size="5" name="B04_0" description="Blue palette data." /> + <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="21" size="5" name="G14_0" description="Green palette data." /> + <BitField start="26" size="5" name="B14_0" description="Blue palette data." /> + <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + </Register> + <Register start="+0x200+428" size="4" name="PAL[107]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="5" size="5" name="G04_0" description="Green palette data." /> + <BitField start="10" size="5" name="B04_0" description="Blue palette data." /> + <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="21" size="5" name="G14_0" description="Green palette data." /> + <BitField start="26" size="5" name="B14_0" description="Blue palette data." /> + <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + </Register> + <Register start="+0x200+432" size="4" name="PAL[108]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="5" size="5" name="G04_0" description="Green palette data." /> + <BitField start="10" size="5" name="B04_0" description="Blue palette data." /> + <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="21" size="5" name="G14_0" description="Green palette data." /> + <BitField start="26" size="5" name="B14_0" description="Blue palette data." /> + <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + </Register> + <Register start="+0x200+436" size="4" name="PAL[109]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="5" size="5" name="G04_0" description="Green palette data." /> + <BitField start="10" size="5" name="B04_0" description="Blue palette data." /> + <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="21" size="5" name="G14_0" description="Green palette data." /> + <BitField start="26" size="5" name="B14_0" description="Blue palette data." /> + <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + </Register> + <Register start="+0x200+440" size="4" name="PAL[110]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="5" size="5" name="G04_0" description="Green palette data." /> + <BitField start="10" size="5" name="B04_0" description="Blue palette data." /> + <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="21" size="5" name="G14_0" description="Green palette data." /> + <BitField start="26" size="5" name="B14_0" description="Blue palette data." /> + <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + </Register> + <Register start="+0x200+444" size="4" name="PAL[111]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="5" size="5" name="G04_0" description="Green palette data." /> + <BitField start="10" size="5" name="B04_0" description="Blue palette data." /> + <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="21" size="5" name="G14_0" description="Green palette data." /> + <BitField start="26" size="5" name="B14_0" description="Blue palette data." /> + <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + </Register> + <Register start="+0x200+448" size="4" name="PAL[112]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="5" size="5" name="G04_0" description="Green palette data." /> + <BitField start="10" size="5" name="B04_0" description="Blue palette data." /> + <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="21" size="5" name="G14_0" description="Green palette data." /> + <BitField start="26" size="5" name="B14_0" description="Blue palette data." /> + <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + </Register> + <Register start="+0x200+452" size="4" name="PAL[113]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="5" size="5" name="G04_0" description="Green palette data." /> + <BitField start="10" size="5" name="B04_0" description="Blue palette data." /> + <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="21" size="5" name="G14_0" description="Green palette data." /> + <BitField start="26" size="5" name="B14_0" description="Blue palette data." /> + <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + </Register> + <Register start="+0x200+456" size="4" name="PAL[114]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="5" size="5" name="G04_0" description="Green palette data." /> + <BitField start="10" size="5" name="B04_0" description="Blue palette data." /> + <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="21" size="5" name="G14_0" description="Green palette data." /> + <BitField start="26" size="5" name="B14_0" description="Blue palette data." /> + <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + </Register> + <Register start="+0x200+460" size="4" name="PAL[115]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="5" size="5" name="G04_0" description="Green palette data." /> + <BitField start="10" size="5" name="B04_0" description="Blue palette data." /> + <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="21" size="5" name="G14_0" description="Green palette data." /> + <BitField start="26" size="5" name="B14_0" description="Blue palette data." /> + <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + </Register> + <Register start="+0x200+464" size="4" name="PAL[116]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="5" size="5" name="G04_0" description="Green palette data." /> + <BitField start="10" size="5" name="B04_0" description="Blue palette data." /> + <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="21" size="5" name="G14_0" description="Green palette data." /> + <BitField start="26" size="5" name="B14_0" description="Blue palette data." /> + <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + </Register> + <Register start="+0x200+468" size="4" name="PAL[117]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="5" size="5" name="G04_0" description="Green palette data." /> + <BitField start="10" size="5" name="B04_0" description="Blue palette data." /> + <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="21" size="5" name="G14_0" description="Green palette data." /> + <BitField start="26" size="5" name="B14_0" description="Blue palette data." /> + <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + </Register> + <Register start="+0x200+472" size="4" name="PAL[118]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="5" size="5" name="G04_0" description="Green palette data." /> + <BitField start="10" size="5" name="B04_0" description="Blue palette data." /> + <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="21" size="5" name="G14_0" description="Green palette data." /> + <BitField start="26" size="5" name="B14_0" description="Blue palette data." /> + <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + </Register> + <Register start="+0x200+476" size="4" name="PAL[119]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="5" size="5" name="G04_0" description="Green palette data." /> + <BitField start="10" size="5" name="B04_0" description="Blue palette data." /> + <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="21" size="5" name="G14_0" description="Green palette data." /> + <BitField start="26" size="5" name="B14_0" description="Blue palette data." /> + <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + </Register> + <Register start="+0x200+480" size="4" name="PAL[120]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="5" size="5" name="G04_0" description="Green palette data." /> + <BitField start="10" size="5" name="B04_0" description="Blue palette data." /> + <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="21" size="5" name="G14_0" description="Green palette data." /> + <BitField start="26" size="5" name="B14_0" description="Blue palette data." /> + <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + </Register> + <Register start="+0x200+484" size="4" name="PAL[121]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="5" size="5" name="G04_0" description="Green palette data." /> + <BitField start="10" size="5" name="B04_0" description="Blue palette data." /> + <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="21" size="5" name="G14_0" description="Green palette data." /> + <BitField start="26" size="5" name="B14_0" description="Blue palette data." /> + <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + </Register> + <Register start="+0x200+488" size="4" name="PAL[122]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="5" size="5" name="G04_0" description="Green palette data." /> + <BitField start="10" size="5" name="B04_0" description="Blue palette data." /> + <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="21" size="5" name="G14_0" description="Green palette data." /> + <BitField start="26" size="5" name="B14_0" description="Blue palette data." /> + <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + </Register> + <Register start="+0x200+492" size="4" name="PAL[123]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="5" size="5" name="G04_0" description="Green palette data." /> + <BitField start="10" size="5" name="B04_0" description="Blue palette data." /> + <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="21" size="5" name="G14_0" description="Green palette data." /> + <BitField start="26" size="5" name="B14_0" description="Blue palette data." /> + <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + </Register> + <Register start="+0x200+496" size="4" name="PAL[124]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="5" size="5" name="G04_0" description="Green palette data." /> + <BitField start="10" size="5" name="B04_0" description="Blue palette data." /> + <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="21" size="5" name="G14_0" description="Green palette data." /> + <BitField start="26" size="5" name="B14_0" description="Blue palette data." /> + <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + </Register> + <Register start="+0x200+500" size="4" name="PAL[125]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="5" size="5" name="G04_0" description="Green palette data." /> + <BitField start="10" size="5" name="B04_0" description="Blue palette data." /> + <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="21" size="5" name="G14_0" description="Green palette data." /> + <BitField start="26" size="5" name="B14_0" description="Blue palette data." /> + <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + </Register> + <Register start="+0x200+504" size="4" name="PAL[126]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="5" size="5" name="G04_0" description="Green palette data." /> + <BitField start="10" size="5" name="B04_0" description="Blue palette data." /> + <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="21" size="5" name="G14_0" description="Green palette data." /> + <BitField start="26" size="5" name="B14_0" description="Blue palette data." /> + <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + </Register> + <Register start="+0x200+508" size="4" name="PAL[127]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="5" size="5" name="G04_0" description="Green palette data." /> + <BitField start="10" size="5" name="B04_0" description="Blue palette data." /> + <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." /> + <BitField start="21" size="5" name="G14_0" description="Green palette data." /> + <BitField start="26" size="5" name="B14_0" description="Blue palette data." /> + <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." /> + </Register> + <Register start="+0x800+0" size="4" name="CRSR_IMG[0]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+4" size="4" name="CRSR_IMG[1]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+8" size="4" name="CRSR_IMG[2]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+12" size="4" name="CRSR_IMG[3]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+16" size="4" name="CRSR_IMG[4]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+20" size="4" name="CRSR_IMG[5]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+24" size="4" name="CRSR_IMG[6]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+28" size="4" name="CRSR_IMG[7]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+32" size="4" name="CRSR_IMG[8]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+36" size="4" name="CRSR_IMG[9]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+40" size="4" name="CRSR_IMG[10]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+44" size="4" name="CRSR_IMG[11]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+48" size="4" name="CRSR_IMG[12]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+52" size="4" name="CRSR_IMG[13]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+56" size="4" name="CRSR_IMG[14]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+60" size="4" name="CRSR_IMG[15]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+64" size="4" name="CRSR_IMG[16]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+68" size="4" name="CRSR_IMG[17]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+72" size="4" name="CRSR_IMG[18]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+76" size="4" name="CRSR_IMG[19]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+80" size="4" name="CRSR_IMG[20]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+84" size="4" name="CRSR_IMG[21]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+88" size="4" name="CRSR_IMG[22]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+92" size="4" name="CRSR_IMG[23]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+96" size="4" name="CRSR_IMG[24]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+100" size="4" name="CRSR_IMG[25]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+104" size="4" name="CRSR_IMG[26]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+108" size="4" name="CRSR_IMG[27]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+112" size="4" name="CRSR_IMG[28]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+116" size="4" name="CRSR_IMG[29]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+120" size="4" name="CRSR_IMG[30]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+124" size="4" name="CRSR_IMG[31]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+128" size="4" name="CRSR_IMG[32]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+132" size="4" name="CRSR_IMG[33]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+136" size="4" name="CRSR_IMG[34]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+140" size="4" name="CRSR_IMG[35]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+144" size="4" name="CRSR_IMG[36]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+148" size="4" name="CRSR_IMG[37]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+152" size="4" name="CRSR_IMG[38]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+156" size="4" name="CRSR_IMG[39]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+160" size="4" name="CRSR_IMG[40]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+164" size="4" name="CRSR_IMG[41]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+168" size="4" name="CRSR_IMG[42]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+172" size="4" name="CRSR_IMG[43]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+176" size="4" name="CRSR_IMG[44]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+180" size="4" name="CRSR_IMG[45]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+184" size="4" name="CRSR_IMG[46]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+188" size="4" name="CRSR_IMG[47]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+192" size="4" name="CRSR_IMG[48]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+196" size="4" name="CRSR_IMG[49]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+200" size="4" name="CRSR_IMG[50]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+204" size="4" name="CRSR_IMG[51]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+208" size="4" name="CRSR_IMG[52]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+212" size="4" name="CRSR_IMG[53]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+216" size="4" name="CRSR_IMG[54]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+220" size="4" name="CRSR_IMG[55]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+224" size="4" name="CRSR_IMG[56]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+228" size="4" name="CRSR_IMG[57]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+232" size="4" name="CRSR_IMG[58]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+236" size="4" name="CRSR_IMG[59]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+240" size="4" name="CRSR_IMG[60]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+244" size="4" name="CRSR_IMG[61]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+248" size="4" name="CRSR_IMG[62]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+252" size="4" name="CRSR_IMG[63]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+256" size="4" name="CRSR_IMG[64]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+260" size="4" name="CRSR_IMG[65]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+264" size="4" name="CRSR_IMG[66]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+268" size="4" name="CRSR_IMG[67]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+272" size="4" name="CRSR_IMG[68]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+276" size="4" name="CRSR_IMG[69]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+280" size="4" name="CRSR_IMG[70]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+284" size="4" name="CRSR_IMG[71]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+288" size="4" name="CRSR_IMG[72]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+292" size="4" name="CRSR_IMG[73]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+296" size="4" name="CRSR_IMG[74]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+300" size="4" name="CRSR_IMG[75]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+304" size="4" name="CRSR_IMG[76]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+308" size="4" name="CRSR_IMG[77]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+312" size="4" name="CRSR_IMG[78]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+316" size="4" name="CRSR_IMG[79]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+320" size="4" name="CRSR_IMG[80]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+324" size="4" name="CRSR_IMG[81]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+328" size="4" name="CRSR_IMG[82]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+332" size="4" name="CRSR_IMG[83]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+336" size="4" name="CRSR_IMG[84]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+340" size="4" name="CRSR_IMG[85]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+344" size="4" name="CRSR_IMG[86]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+348" size="4" name="CRSR_IMG[87]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+352" size="4" name="CRSR_IMG[88]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+356" size="4" name="CRSR_IMG[89]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+360" size="4" name="CRSR_IMG[90]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+364" size="4" name="CRSR_IMG[91]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+368" size="4" name="CRSR_IMG[92]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+372" size="4" name="CRSR_IMG[93]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+376" size="4" name="CRSR_IMG[94]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+380" size="4" name="CRSR_IMG[95]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+384" size="4" name="CRSR_IMG[96]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+388" size="4" name="CRSR_IMG[97]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+392" size="4" name="CRSR_IMG[98]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+396" size="4" name="CRSR_IMG[99]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+400" size="4" name="CRSR_IMG[100]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+404" size="4" name="CRSR_IMG[101]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+408" size="4" name="CRSR_IMG[102]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+412" size="4" name="CRSR_IMG[103]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+416" size="4" name="CRSR_IMG[104]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+420" size="4" name="CRSR_IMG[105]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+424" size="4" name="CRSR_IMG[106]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+428" size="4" name="CRSR_IMG[107]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+432" size="4" name="CRSR_IMG[108]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+436" size="4" name="CRSR_IMG[109]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+440" size="4" name="CRSR_IMG[110]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+444" size="4" name="CRSR_IMG[111]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+448" size="4" name="CRSR_IMG[112]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+452" size="4" name="CRSR_IMG[113]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+456" size="4" name="CRSR_IMG[114]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+460" size="4" name="CRSR_IMG[115]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+464" size="4" name="CRSR_IMG[116]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+468" size="4" name="CRSR_IMG[117]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+472" size="4" name="CRSR_IMG[118]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+476" size="4" name="CRSR_IMG[119]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+480" size="4" name="CRSR_IMG[120]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+484" size="4" name="CRSR_IMG[121]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+488" size="4" name="CRSR_IMG[122]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+492" size="4" name="CRSR_IMG[123]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+496" size="4" name="CRSR_IMG[124]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+500" size="4" name="CRSR_IMG[125]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+504" size="4" name="CRSR_IMG[126]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+508" size="4" name="CRSR_IMG[127]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+512" size="4" name="CRSR_IMG[128]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+516" size="4" name="CRSR_IMG[129]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+520" size="4" name="CRSR_IMG[130]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+524" size="4" name="CRSR_IMG[131]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+528" size="4" name="CRSR_IMG[132]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+532" size="4" name="CRSR_IMG[133]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+536" size="4" name="CRSR_IMG[134]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+540" size="4" name="CRSR_IMG[135]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+544" size="4" name="CRSR_IMG[136]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+548" size="4" name="CRSR_IMG[137]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+552" size="4" name="CRSR_IMG[138]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+556" size="4" name="CRSR_IMG[139]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+560" size="4" name="CRSR_IMG[140]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+564" size="4" name="CRSR_IMG[141]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+568" size="4" name="CRSR_IMG[142]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+572" size="4" name="CRSR_IMG[143]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+576" size="4" name="CRSR_IMG[144]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+580" size="4" name="CRSR_IMG[145]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+584" size="4" name="CRSR_IMG[146]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+588" size="4" name="CRSR_IMG[147]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+592" size="4" name="CRSR_IMG[148]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+596" size="4" name="CRSR_IMG[149]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+600" size="4" name="CRSR_IMG[150]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+604" size="4" name="CRSR_IMG[151]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+608" size="4" name="CRSR_IMG[152]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+612" size="4" name="CRSR_IMG[153]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+616" size="4" name="CRSR_IMG[154]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+620" size="4" name="CRSR_IMG[155]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+624" size="4" name="CRSR_IMG[156]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+628" size="4" name="CRSR_IMG[157]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+632" size="4" name="CRSR_IMG[158]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+636" size="4" name="CRSR_IMG[159]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+640" size="4" name="CRSR_IMG[160]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+644" size="4" name="CRSR_IMG[161]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+648" size="4" name="CRSR_IMG[162]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+652" size="4" name="CRSR_IMG[163]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+656" size="4" name="CRSR_IMG[164]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+660" size="4" name="CRSR_IMG[165]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+664" size="4" name="CRSR_IMG[166]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+668" size="4" name="CRSR_IMG[167]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+672" size="4" name="CRSR_IMG[168]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+676" size="4" name="CRSR_IMG[169]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+680" size="4" name="CRSR_IMG[170]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+684" size="4" name="CRSR_IMG[171]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+688" size="4" name="CRSR_IMG[172]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+692" size="4" name="CRSR_IMG[173]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+696" size="4" name="CRSR_IMG[174]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+700" size="4" name="CRSR_IMG[175]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+704" size="4" name="CRSR_IMG[176]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+708" size="4" name="CRSR_IMG[177]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+712" size="4" name="CRSR_IMG[178]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+716" size="4" name="CRSR_IMG[179]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+720" size="4" name="CRSR_IMG[180]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+724" size="4" name="CRSR_IMG[181]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+728" size="4" name="CRSR_IMG[182]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+732" size="4" name="CRSR_IMG[183]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+736" size="4" name="CRSR_IMG[184]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+740" size="4" name="CRSR_IMG[185]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+744" size="4" name="CRSR_IMG[186]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+748" size="4" name="CRSR_IMG[187]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+752" size="4" name="CRSR_IMG[188]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+756" size="4" name="CRSR_IMG[189]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+760" size="4" name="CRSR_IMG[190]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+764" size="4" name="CRSR_IMG[191]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+768" size="4" name="CRSR_IMG[192]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+772" size="4" name="CRSR_IMG[193]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+776" size="4" name="CRSR_IMG[194]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+780" size="4" name="CRSR_IMG[195]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+784" size="4" name="CRSR_IMG[196]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+788" size="4" name="CRSR_IMG[197]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+792" size="4" name="CRSR_IMG[198]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+796" size="4" name="CRSR_IMG[199]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+800" size="4" name="CRSR_IMG[200]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+804" size="4" name="CRSR_IMG[201]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+808" size="4" name="CRSR_IMG[202]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+812" size="4" name="CRSR_IMG[203]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+816" size="4" name="CRSR_IMG[204]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+820" size="4" name="CRSR_IMG[205]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+824" size="4" name="CRSR_IMG[206]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+828" size="4" name="CRSR_IMG[207]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+832" size="4" name="CRSR_IMG[208]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+836" size="4" name="CRSR_IMG[209]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+840" size="4" name="CRSR_IMG[210]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+844" size="4" name="CRSR_IMG[211]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+848" size="4" name="CRSR_IMG[212]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+852" size="4" name="CRSR_IMG[213]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+856" size="4" name="CRSR_IMG[214]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+860" size="4" name="CRSR_IMG[215]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+864" size="4" name="CRSR_IMG[216]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+868" size="4" name="CRSR_IMG[217]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+872" size="4" name="CRSR_IMG[218]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+876" size="4" name="CRSR_IMG[219]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+880" size="4" name="CRSR_IMG[220]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+884" size="4" name="CRSR_IMG[221]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+888" size="4" name="CRSR_IMG[222]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+892" size="4" name="CRSR_IMG[223]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+896" size="4" name="CRSR_IMG[224]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+900" size="4" name="CRSR_IMG[225]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+904" size="4" name="CRSR_IMG[226]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+908" size="4" name="CRSR_IMG[227]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+912" size="4" name="CRSR_IMG[228]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+916" size="4" name="CRSR_IMG[229]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+920" size="4" name="CRSR_IMG[230]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+924" size="4" name="CRSR_IMG[231]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+928" size="4" name="CRSR_IMG[232]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+932" size="4" name="CRSR_IMG[233]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+936" size="4" name="CRSR_IMG[234]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+940" size="4" name="CRSR_IMG[235]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+944" size="4" name="CRSR_IMG[236]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+948" size="4" name="CRSR_IMG[237]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+952" size="4" name="CRSR_IMG[238]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+956" size="4" name="CRSR_IMG[239]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+960" size="4" name="CRSR_IMG[240]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+964" size="4" name="CRSR_IMG[241]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+968" size="4" name="CRSR_IMG[242]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+972" size="4" name="CRSR_IMG[243]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+976" size="4" name="CRSR_IMG[244]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+980" size="4" name="CRSR_IMG[245]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+984" size="4" name="CRSR_IMG[246]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+988" size="4" name="CRSR_IMG[247]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+992" size="4" name="CRSR_IMG[248]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+996" size="4" name="CRSR_IMG[249]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+1000" size="4" name="CRSR_IMG[250]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+1004" size="4" name="CRSR_IMG[251]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+1008" size="4" name="CRSR_IMG[252]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+1012" size="4" name="CRSR_IMG[253]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+1016" size="4" name="CRSR_IMG[254]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0x800+1020" size="4" name="CRSR_IMG[255]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." /> + </Register> + <Register start="+0xC00" size="4" name="CRSR_CTRL" access="Read/Write" description="Cursor Control register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="CRSRON" description="Cursor enable. 0 = Cursor is not displayed. 1 = Cursor is displayed." /> + <BitField start="1" size="3" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="4" size="2" name="CRSRNUM1_0" description="Cursor image number. If the selected cursor size is 6x64, this field has no effect. If the selected cursor size is 32x32: 00 = Cursor0. 01 = Cursor1. 10 = Cursor2. 11 = Cursor3." /> + <BitField start="6" size="26" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0xC04" size="4" name="CRSR_CFG" access="Read/Write" description="Cursor Configuration register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="CRSRSIZE" description="Cursor size selection. 0 = 32x32 pixel cursor. Allows for 4 defined cursors. 1 = 64x64 pixel cursor." /> + <BitField start="1" size="1" name="FRAMESYNC" description="Cursor frame synchronization type. 0 = Cursor coordinates are asynchronous. 1 = Cursor coordinates are synchronized to the frame synchronization pulse." /> + <BitField start="2" size="30" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0xC08" size="4" name="CRSR_PAL0" access="Read/Write" description="Cursor Palette register 0" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="RED" description="Red color component" /> + <BitField start="8" size="8" name="GREEN" description="Green color component" /> + <BitField start="16" size="8" name="BLUE" description="Blue color component." /> + <BitField start="24" size="8" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0xC0C" size="4" name="CRSR_PAL1" access="Read/Write" description="Cursor Palette register 1" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="RED" description="Red color component" /> + <BitField start="8" size="8" name="GREEN" description="Green color component" /> + <BitField start="16" size="8" name="BLUE" description="Blue color component." /> + <BitField start="24" size="8" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0xC10" size="4" name="CRSR_XY" access="Read/Write" description="Cursor XY Position register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="10" name="CRSRX" description="X ordinate of the cursor origin measured in pixels. When 0, the left edge of the cursor is at the left of the display." /> + <BitField start="10" size="6" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="16" size="10" name="CRSRY" description="Y ordinate of the cursor origin measured in pixels. When 0, the top edge of the cursor is at the top of the display." /> + <BitField start="26" size="6" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0xC14" size="4" name="CRSR_CLIP" access="Read/Write" description="Cursor Clip Position register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="6" name="CRSRCLIPX" description="Cursor clip position for X direction. Distance from the left edge of the cursor image to the first displayed pixel in the cursor. When 0, the first pixel of the cursor line is displayed." /> + <BitField start="6" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="8" size="6" name="CRSRCLIPY" description="Cursor clip position for Y direction. Distance from the top of the cursor image to the first displayed pixel in the cursor. When 0, the first displayed pixel is from the top line of the cursor image." /> + <BitField start="14" size="18" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0xC20" size="4" name="CRSR_INTMSK" access="Read/Write" description="Cursor Interrupt Mask register" reset_value="0x0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="CRSRIM" description="Cursor interrupt mask. When clear, the cursor never interrupts the processor. When set, the cursor interrupts the processor immediately after reading of the last word of cursor image." /> + <BitField start="1" size="31" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0xC24" size="4" name="CRSR_INTCLR" access="WriteOnly" description="Cursor Interrupt Clear register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="CRSRIC" description="Cursor interrupt clear. Writing a 0 to this bit has no effect. Writing a 1 to this bit causes the cursor interrupt status to be cleared." /> + <BitField start="1" size="31" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0xC28" size="4" name="CRSR_INTRAW" access="ReadOnly" description="Cursor Raw Interrupt Status register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="CRSRRIS" description="Cursor raw interrupt status. The cursor interrupt status is set immediately after the last data is read from the cursor image for the current frame. This bit is cleared by writing to the CrsrIC bit in the CRSR_INTCLR register." /> + <BitField start="1" size="31" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0xC2C" size="4" name="CRSR_INTSTAT" access="ReadOnly" description="Cursor Masked Interrupt Status register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="CRSRMIS" description="Cursor masked interrupt status. The cursor interrupt status is set immediately after the last data read from the cursor image for the current frame, providing that the corresponding bit in the CRSR_INTMSK register is set. The bit remains clear if the CRSR_INTMSK register is clear. This bit is cleared by writing to the CRSR_INTCLR register." /> + <BitField start="1" size="31" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + </RegisterGroup> + <RegisterGroup name="USB" start="0x2008C000" description=" USB device controller "> + <Register start="+0x100" size="4" name="INTST" access="ReadOnly" description="OTG Interrupt Status" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="TMR" description="Timer time-out." /> + <BitField start="1" size="1" name="REMOVE_PU" description="Remove pull-up. This bit is set by hardware to indicate that software needs to disable the D+ pull-up resistor." /> + <BitField start="2" size="1" name="HNP_FAILURE" description="HNP failed. This bit is set by hardware to indicate that the HNP switching has failed." /> + <BitField start="3" size="1" name="HNP_SUCCESS" description="HNP succeeded. This bit is set by hardware to indicate that the HNP switching has succeeded." /> + <BitField start="4" size="28" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x104" size="4" name="INTEN" access="Read/Write" description="OTG Interrupt Enable" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="TMR_EN" description="1 = enable the corresponding bit in the IntSt register." /> + <BitField start="1" size="1" name="REMOVE_PU_EN" description="1 = enable the corresponding bit in the IntSt register." /> + <BitField start="2" size="1" name="HNP_FAILURE_EN" description="1 = enable the corresponding bit in the IntSt register." /> + <BitField start="3" size="1" name="HNP_SUCCES_EN" description="1 = enable the corresponding bit in the IntSt register." /> + <BitField start="4" size="28" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x108" size="4" name="INTSET" access="WriteOnly" description="OTG Interrupt Set" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="TMR_SET" description="0 = no effect. 1 = set the corresponding bit in the IntSt register." /> + <BitField start="1" size="1" name="REMOVE_PU_SET" description="0 = no effect. 1 = set the corresponding bit in the IntSt register." /> + <BitField start="2" size="1" name="HNP_FAILURE_SET" description="0 = no effect. 1 = set the corresponding bit in the IntSt register." /> + <BitField start="3" size="1" name="HNP_SUCCES_SET" description="0 = no effect. 1 = set the corresponding bit in the IntSt register." /> + <BitField start="4" size="28" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x10C" size="4" name="INCLR" access="WriteOnly" description="OTG Interrupt Clear" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="TMR_CLR" description="0 = no effect. 1 = clear the corresponding bit in the IntSt register." /> + <BitField start="1" size="1" name="REMOVE_PU_CLR" description="0 = no effect. 1 = clear the corresponding bit in the IntSt register." /> + <BitField start="2" size="1" name="HNP_FAILURE_CLR" description="0 = no effect. 1 = clear the corresponding bit in the IntSt register." /> + <BitField start="3" size="1" name="HNP_SUCCES_CLR" description="0 = no effect. 1 = clear the corresponding bit in the IntSt register." /> + <BitField start="4" size="28" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x110" size="4" name="PORTSEL" access="Read/Write" description="USB Port Select. The USBPortSel register is identical to the OTGStCtrl register (see Section 15.8.6). In device-only operations only bits 0 and 1 of this register are used to control the routing of USB pins to Port 1 or Port 2." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="PORTSEL" description="Selects which USB port the device controller signals are mapped to. Other values are reserved."> + <Enum name="PORTU1" start="0x0" description="The USB device controller signals are mapped to the U1 port: USB_CONNECT1, USB_UP_LED1, USB_D+1, USB_D-1." /> + <Enum name="PORTU2" start="0x3" description="The USB device controller signals are mapped to the U2 port: USB_CONNECT2, USB_UP_LED2, USB_D+2, USB_D-2." /> + </BitField> + <BitField start="2" size="2" name="TMR_SCALE" description="Timer scale selection. This field determines the duration of each timer count. 00: 10 ms (100 KHz) 01: 100 ms (10 KHz) 10: 1000 ms (1 KHz) 11: Reserved" /> + <BitField start="4" size="1" name="TMR_MODE" description="Timer mode selection. 0: monoshot 1: free running" /> + <BitField start="5" size="1" name="TMR_EN" description="Timer enable. When set, TMR_CNT increments. When cleared, TMR_CNT is reset to 0." /> + <BitField start="6" size="1" name="TMR_RST" description="Timer reset. Writing one to this bit resets TMR_CNT to 0. This provides a single bit control for the software to restart the timer when the timer is enabled." /> + <BitField start="7" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="8" size="1" name="B_HNP_TRACK" description="Enable HNP tracking for B-device (peripheral), see Section 15.9. Hardware clears this bit when HNP_SUCCESS or HNP_FAILURE is set." /> + <BitField start="9" size="1" name="A_HNP_TRACK" description="Enable HNP tracking for A-device (host), see Section 15.9. Hardware clears this bit when HNP_SUCCESS or HNP_FAILURE is set." /> + <BitField start="10" size="1" name="PU_REMOVED" description="When the B-device changes its role from peripheral to host, software sets this bit when it removes the D+ pull-up, see Section 15.9. Hardware clears this bit when HNP_SUCCESS or HNP_FAILURE is set." /> + <BitField start="11" size="5" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="16" size="16" name="TMR_CNT" description="Current timer count value." /> + <BitField start="2" size="30" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x114" size="4" name="TMR" access="Read/Write" description="OTG Timer" reset_value="0xFFFF" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="16" name="TIMEOUT_CNT" description="The TMR interrupt is set when TMR_CNT reaches this value." /> + <BitField start="16" size="16" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x200" size="4" name="DEVINTST" access="ReadOnly" description="USB Device Interrupt Status" reset_value="0x10" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="FRAME" description="The frame interrupt occurs every 1 ms. This is used in isochronous packet transfers." /> + <BitField start="1" size="1" name="EP_FAST" description="Fast endpoint interrupt. If an Endpoint Interrupt Priority register (USBEpIntPri) bit is set, the corresponding endpoint interrupt will be routed to this bit." /> + <BitField start="2" size="1" name="EP_SLOW" description="Slow endpoints interrupt. If an Endpoint Interrupt Priority Register (USBEpIntPri) bit is not set, the corresponding endpoint interrupt will be routed to this bit." /> + <BitField start="3" size="1" name="DEV_STAT" description="Set when USB Bus reset, USB suspend change or Connect change event occurs. Refer to Section 13.12.6 Set Device Status (Command: 0xFE, Data: write 1 byte) on page 366." /> + <BitField start="4" size="1" name="CCEMPTY" description="The command code register (USBCmdCode) is empty (New command can be written)." /> + <BitField start="5" size="1" name="CDFULL" description="Command data register (USBCmdData) is full (Data can be read now)." /> + <BitField start="6" size="1" name="RxENDPKT" description="The current packet in the endpoint buffer is transferred to the CPU." /> + <BitField start="7" size="1" name="TxENDPKT" description="The number of data bytes transferred to the endpoint buffer equals the number of bytes programmed in the TxPacket length register (USBTxPLen)." /> + <BitField start="8" size="1" name="EP_RLZED" description="Endpoints realized. Set when Realize Endpoint register (USBReEp) or MaxPacketSize register (USBMaxPSize) is updated and the corresponding operation is completed." /> + <BitField start="9" size="1" name="ERR_INT" description="Error Interrupt. Any bus error interrupt from the USB device. Refer to Section 13.12.9 Read Error Status (Command: 0xFB, Data: read 1 byte) on page 368" /> + <BitField start="10" size="22" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x204" size="4" name="DEVINTEN" access="Read/Write" description="USB Device Interrupt Enable" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="FRAMEEN" description="0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri." /> + <BitField start="1" size="1" name="EP_FASTEN" description="0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri." /> + <BitField start="2" size="1" name="EP_SLOWEN" description="0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri." /> + <BitField start="3" size="1" name="DEV_STATEN" description="0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri." /> + <BitField start="4" size="1" name="CCEMPTYEN" description="0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri." /> + <BitField start="5" size="1" name="CDFULLEN" description="0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri." /> + <BitField start="6" size="1" name="RxENDPKTEN" description="0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri." /> + <BitField start="7" size="1" name="TxENDPKTEN" description="0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri." /> + <BitField start="8" size="1" name="EP_RLZEDEN" description="0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri." /> + <BitField start="9" size="1" name="ERR_INTEN" description="0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri." /> + <BitField start="10" size="22" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x208" size="4" name="DEVINTCLR" access="WriteOnly" description="USB Device Interrupt Clear" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="FRAMECLR" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared." /> + <BitField start="1" size="1" name="EP_FASTCLR" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared." /> + <BitField start="2" size="1" name="EP_SLOWCLR" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared." /> + <BitField start="3" size="1" name="DEV_STATCLR" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared." /> + <BitField start="4" size="1" name="CCEMPTYCLR" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared." /> + <BitField start="5" size="1" name="CDFULLCLR" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared." /> + <BitField start="6" size="1" name="RxENDPKTCLR" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared." /> + <BitField start="7" size="1" name="TxENDPKTCLR" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared." /> + <BitField start="8" size="1" name="EP_RLZEDCLR" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared." /> + <BitField start="9" size="1" name="ERR_INTCLR" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared." /> + <BitField start="10" size="22" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x20C" size="4" name="DEVINTSET" access="WriteOnly" description="USB Device Interrupt Set" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="FRAMESET" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set." /> + <BitField start="1" size="1" name="EP_FASTSET" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set." /> + <BitField start="2" size="1" name="EP_SLOWSET" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set." /> + <BitField start="3" size="1" name="DEV_STATSET" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set." /> + <BitField start="4" size="1" name="CCEMPTYSET" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set." /> + <BitField start="5" size="1" name="CDFULLSET" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set." /> + <BitField start="6" size="1" name="RxENDPKTSET" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set." /> + <BitField start="7" size="1" name="TxENDPKTSET" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set." /> + <BitField start="8" size="1" name="EP_RLZEDSET" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set." /> + <BitField start="9" size="1" name="ERR_INTSET" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set." /> + <BitField start="10" size="22" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x22C" size="4" name="DEVINTPRI" access="WriteOnly" description="USB Device Interrupt Priority" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="FRAME" description="Frame interrupt routing"> + <Enum name="LP" start="0" description="FRAME interrupt is routed to USB_INT_REQ_LP." /> + <Enum name="HP" start="1" description="FRAME interrupt is routed to USB_INT_REQ_HP." /> + </BitField> + <BitField start="1" size="1" name="EP_FAST" description="Fast endpoint interrupt routing"> + <Enum name="LP" start="0" description="EP_FAST interrupt is routed to USB_INT_REQ_LP." /> + <Enum name="HP" start="1" description="EP_FAST interrupt is routed to USB_INT_REQ_HP." /> + </BitField> + <BitField start="2" size="30" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x230" size="4" name="EPINTST" access="ReadOnly" description="USB Endpoint Interrupt Status" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="EPST0" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." /> + <BitField start="1" size="1" name="EPST1" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." /> + <BitField start="2" size="1" name="EPST2" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." /> + <BitField start="3" size="1" name="EPST3" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." /> + <BitField start="4" size="1" name="EPST4" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." /> + <BitField start="5" size="1" name="EPST5" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." /> + <BitField start="6" size="1" name="EPST6" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." /> + <BitField start="7" size="1" name="EPST7" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." /> + <BitField start="8" size="1" name="EPST8" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." /> + <BitField start="9" size="1" name="EPST9" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." /> + <BitField start="10" size="1" name="EPST10" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." /> + <BitField start="11" size="1" name="EPST11" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." /> + <BitField start="12" size="1" name="EPST12" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." /> + <BitField start="13" size="1" name="EPST13" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." /> + <BitField start="14" size="1" name="EPST14" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." /> + <BitField start="15" size="1" name="EPST15" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." /> + <BitField start="16" size="1" name="EPST16" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." /> + <BitField start="17" size="1" name="EPST17" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." /> + <BitField start="18" size="1" name="EPST18" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." /> + <BitField start="19" size="1" name="EPST19" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." /> + <BitField start="20" size="1" name="EPST20" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." /> + <BitField start="21" size="1" name="EPST21" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." /> + <BitField start="22" size="1" name="EPST22" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." /> + <BitField start="23" size="1" name="EPST23" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." /> + <BitField start="24" size="1" name="EPST24" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." /> + <BitField start="25" size="1" name="EPST25" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." /> + <BitField start="26" size="1" name="EPST26" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." /> + <BitField start="27" size="1" name="EPST27" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." /> + <BitField start="28" size="1" name="EPST28" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." /> + <BitField start="29" size="1" name="EPST29" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." /> + <BitField start="30" size="1" name="EPST30" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." /> + <BitField start="31" size="1" name="EPST31" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." /> + </Register> + <Register start="+0x234" size="4" name="EPINTEN" access="Read/Write" description="USB Endpoint Interrupt Enable" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="EPEN0" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." /> + <BitField start="1" size="1" name="EPEN1" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." /> + <BitField start="2" size="1" name="EPEN2" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." /> + <BitField start="3" size="1" name="EPEN3" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." /> + <BitField start="4" size="1" name="EPEN4" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." /> + <BitField start="5" size="1" name="EPEN5" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." /> + <BitField start="6" size="1" name="EPEN6" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." /> + <BitField start="7" size="1" name="EPEN7" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." /> + <BitField start="8" size="1" name="EPEN8" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." /> + <BitField start="9" size="1" name="EPEN9" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." /> + <BitField start="10" size="1" name="EPEN10" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." /> + <BitField start="11" size="1" name="EPEN11" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." /> + <BitField start="12" size="1" name="EPEN12" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." /> + <BitField start="13" size="1" name="EPEN13" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." /> + <BitField start="14" size="1" name="EPEN14" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." /> + <BitField start="15" size="1" name="EPEN15" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." /> + <BitField start="16" size="1" name="EPEN16" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." /> + <BitField start="17" size="1" name="EPEN17" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." /> + <BitField start="18" size="1" name="EPEN18" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." /> + <BitField start="19" size="1" name="EPEN19" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." /> + <BitField start="20" size="1" name="EPEN20" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." /> + <BitField start="21" size="1" name="EPEN21" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." /> + <BitField start="22" size="1" name="EPEN22" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." /> + <BitField start="23" size="1" name="EPEN23" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." /> + <BitField start="24" size="1" name="EPEN24" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." /> + <BitField start="25" size="1" name="EPEN25" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." /> + <BitField start="26" size="1" name="EPEN26" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." /> + <BitField start="27" size="1" name="EPEN27" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." /> + <BitField start="28" size="1" name="EPEN28" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." /> + <BitField start="29" size="1" name="EPEN29" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." /> + <BitField start="30" size="1" name="EPEN30" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." /> + <BitField start="31" size="1" name="EPEN31" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." /> + </Register> + <Register start="+0x238" size="4" name="EPINTCLR" access="WriteOnly" description="USB Endpoint Interrupt Clear" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="EPCLR0" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." /> + <BitField start="1" size="1" name="EPCLR1" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." /> + <BitField start="2" size="1" name="EPCLR2" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." /> + <BitField start="3" size="1" name="EPCLR3" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." /> + <BitField start="4" size="1" name="EPCLR4" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." /> + <BitField start="5" size="1" name="EPCLR5" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." /> + <BitField start="6" size="1" name="EPCLR6" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." /> + <BitField start="7" size="1" name="EPCLR7" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." /> + <BitField start="8" size="1" name="EPCLR8" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." /> + <BitField start="9" size="1" name="EPCLR9" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." /> + <BitField start="10" size="1" name="EPCLR10" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." /> + <BitField start="11" size="1" name="EPCLR11" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." /> + <BitField start="12" size="1" name="EPCLR12" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." /> + <BitField start="13" size="1" name="EPCLR13" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." /> + <BitField start="14" size="1" name="EPCLR14" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." /> + <BitField start="15" size="1" name="EPCLR15" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." /> + <BitField start="16" size="1" name="EPCLR16" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." /> + <BitField start="17" size="1" name="EPCLR17" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." /> + <BitField start="18" size="1" name="EPCLR18" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." /> + <BitField start="19" size="1" name="EPCLR19" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." /> + <BitField start="20" size="1" name="EPCLR20" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." /> + <BitField start="21" size="1" name="EPCLR21" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." /> + <BitField start="22" size="1" name="EPCLR22" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." /> + <BitField start="23" size="1" name="EPCLR23" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." /> + <BitField start="24" size="1" name="EPCLR24" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." /> + <BitField start="25" size="1" name="EPCLR25" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." /> + <BitField start="26" size="1" name="EPCLR26" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." /> + <BitField start="27" size="1" name="EPCLR27" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." /> + <BitField start="28" size="1" name="EPCLR28" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." /> + <BitField start="29" size="1" name="EPCLR29" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." /> + <BitField start="30" size="1" name="EPCLR30" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." /> + <BitField start="31" size="1" name="EPCLR31" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." /> + </Register> + <Register start="+0x23C" size="4" name="EPINTSET" access="WriteOnly" description="USB Endpoint Interrupt Set" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="EPSET0" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." /> + <BitField start="1" size="1" name="EPSET1" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." /> + <BitField start="2" size="1" name="EPSET2" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." /> + <BitField start="3" size="1" name="EPSET3" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." /> + <BitField start="4" size="1" name="EPSET4" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." /> + <BitField start="5" size="1" name="EPSET5" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." /> + <BitField start="6" size="1" name="EPSET6" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." /> + <BitField start="7" size="1" name="EPSET7" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." /> + <BitField start="8" size="1" name="EPSET8" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." /> + <BitField start="9" size="1" name="EPSET9" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." /> + <BitField start="10" size="1" name="EPSET10" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." /> + <BitField start="11" size="1" name="EPSET11" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." /> + <BitField start="12" size="1" name="EPSET12" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." /> + <BitField start="13" size="1" name="EPSET13" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." /> + <BitField start="14" size="1" name="EPSET14" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." /> + <BitField start="15" size="1" name="EPSET15" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." /> + <BitField start="16" size="1" name="EPSET16" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." /> + <BitField start="17" size="1" name="EPSET17" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." /> + <BitField start="18" size="1" name="EPSET18" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." /> + <BitField start="19" size="1" name="EPSET19" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." /> + <BitField start="20" size="1" name="EPSET20" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." /> + <BitField start="21" size="1" name="EPSET21" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." /> + <BitField start="22" size="1" name="EPSET22" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." /> + <BitField start="23" size="1" name="EPSET23" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." /> + <BitField start="24" size="1" name="EPSET24" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." /> + <BitField start="25" size="1" name="EPSET25" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." /> + <BitField start="26" size="1" name="EPSET26" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." /> + <BitField start="27" size="1" name="EPSET27" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." /> + <BitField start="28" size="1" name="EPSET28" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." /> + <BitField start="29" size="1" name="EPSET29" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." /> + <BitField start="30" size="1" name="EPSET30" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." /> + <BitField start="31" size="1" name="EPSET31" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." /> + </Register> + <Register start="+0x240" size="4" name="EPINTPRI" access="WriteOnly" description="USB Endpoint Priority" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="EPPRI0" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" /> + <BitField start="1" size="1" name="EPPRI1" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" /> + <BitField start="2" size="1" name="EPPRI2" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" /> + <BitField start="3" size="1" name="EPPRI3" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" /> + <BitField start="4" size="1" name="EPPRI4" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" /> + <BitField start="5" size="1" name="EPPRI5" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" /> + <BitField start="6" size="1" name="EPPRI6" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" /> + <BitField start="7" size="1" name="EPPRI7" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" /> + <BitField start="8" size="1" name="EPPRI8" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" /> + <BitField start="9" size="1" name="EPPRI9" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" /> + <BitField start="10" size="1" name="EPPRI10" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" /> + <BitField start="11" size="1" name="EPPRI11" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" /> + <BitField start="12" size="1" name="EPPRI12" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" /> + <BitField start="13" size="1" name="EPPRI13" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" /> + <BitField start="14" size="1" name="EPPRI14" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" /> + <BitField start="15" size="1" name="EPPRI15" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" /> + <BitField start="16" size="1" name="EPPRI16" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" /> + <BitField start="17" size="1" name="EPPRI17" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" /> + <BitField start="18" size="1" name="EPPRI18" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" /> + <BitField start="19" size="1" name="EPPRI19" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" /> + <BitField start="20" size="1" name="EPPRI20" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" /> + <BitField start="21" size="1" name="EPPRI21" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" /> + <BitField start="22" size="1" name="EPPRI22" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" /> + <BitField start="23" size="1" name="EPPRI23" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" /> + <BitField start="24" size="1" name="EPPRI24" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" /> + <BitField start="25" size="1" name="EPPRI25" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" /> + <BitField start="26" size="1" name="EPPRI26" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" /> + <BitField start="27" size="1" name="EPPRI27" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" /> + <BitField start="28" size="1" name="EPPRI28" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" /> + <BitField start="29" size="1" name="EPPRI29" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" /> + <BitField start="30" size="1" name="EPPRI30" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" /> + <BitField start="31" size="1" name="EPPRI31" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" /> + </Register> + <Register start="+0x244" size="4" name="REEP" access="Read/Write" description="USB Realize Endpoint" reset_value="0x3" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="EPR0" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." /> + <BitField start="1" size="1" name="EPR1" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." /> + <BitField start="2" size="1" name="EPR2" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." /> + <BitField start="3" size="1" name="EPR3" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." /> + <BitField start="4" size="1" name="EPR4" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." /> + <BitField start="5" size="1" name="EPR5" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." /> + <BitField start="6" size="1" name="EPR6" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." /> + <BitField start="7" size="1" name="EPR7" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." /> + <BitField start="8" size="1" name="EPR8" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." /> + <BitField start="9" size="1" name="EPR9" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." /> + <BitField start="10" size="1" name="EPR10" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." /> + <BitField start="11" size="1" name="EPR11" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." /> + <BitField start="12" size="1" name="EPR12" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." /> + <BitField start="13" size="1" name="EPR13" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." /> + <BitField start="14" size="1" name="EPR14" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." /> + <BitField start="15" size="1" name="EPR15" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." /> + <BitField start="16" size="1" name="EPR16" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." /> + <BitField start="17" size="1" name="EPR17" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." /> + <BitField start="18" size="1" name="EPR18" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." /> + <BitField start="19" size="1" name="EPR19" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." /> + <BitField start="20" size="1" name="EPR20" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." /> + <BitField start="21" size="1" name="EPR21" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." /> + <BitField start="22" size="1" name="EPR22" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." /> + <BitField start="23" size="1" name="EPR23" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." /> + <BitField start="24" size="1" name="EPR24" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." /> + <BitField start="25" size="1" name="EPR25" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." /> + <BitField start="26" size="1" name="EPR26" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." /> + <BitField start="27" size="1" name="EPR27" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." /> + <BitField start="28" size="1" name="EPR28" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." /> + <BitField start="29" size="1" name="EPR29" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." /> + <BitField start="30" size="1" name="EPR30" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." /> + <BitField start="31" size="1" name="EPR31" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." /> + </Register> + <Register start="+0x248" size="4" name="EPIN" access="WriteOnly" description="USB Endpoint Index" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="PHY_EP" description="Physical endpoint number (0-31)" /> + <BitField start="5" size="27" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x24C" size="4" name="MAXPSIZE" access="Read/Write" description="USB MaxPacketSize" reset_value="0x8" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="10" name="MPS" description="The maximum packet size value." /> + <BitField start="10" size="22" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x218" size="4" name="RXDATA" access="ReadOnly" description="USB Receive Data" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="RX_DATA" description="Data received." /> + </Register> + <Register start="+220" size="4" name="RXPLEN" access="ReadOnly" description="USB Receive Packet Length" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="10" name="PKT_LNGTH" description="The remaining number of bytes to be read from the currently selected endpoint's buffer. When this field decrements to 0, the RxENDPKT bit will be set in USBDevIntSt." /> + <BitField start="10" size="1" name="DV" description="Data valid. This bit is useful for isochronous endpoints. Non-isochronous endpoints do not raise an interrupt when an erroneous data packet is received. But invalid data packet can be produced with a bus reset. For isochronous endpoints, data transfer will happen even if an erroneous packet is received. In this case DV bit will not be set for the packet."> + <Enum name="DATA_IS_INVALID_" start="0" description="Data is invalid." /> + <Enum name="DATA_IS_VALID_" start="1" description="Data is valid." /> + </BitField> + <BitField start="11" size="1" name="PKT_RDY" description="The PKT_LNGTH field is valid and the packet is ready for reading." /> + <BitField start="12" size="20" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x21C" size="4" name="TXDATA" access="WriteOnly" description="USB Transmit Data" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="TX_DATA" description="Transmit Data." /> + </Register> + <Register start="+0x224" size="4" name="TXPLEN" access="WriteOnly" description="USB Transmit Packet Length" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="10" name="PKT_LNGTH" description="The remaining number of bytes to be written to the selected endpoint buffer. This field is decremented by 4 by hardware after each write to USBTxData. When this field decrements to 0, the TxENDPKT bit will be set in USBDevIntSt." /> + <BitField start="10" size="22" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x228" size="4" name="CTRL" access="Read/Write" description="USB Control" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RD_EN" description="Read mode control. Enables reading data from the OUT endpoint buffer for the endpoint specified in the LOG_ENDPOINT field using the USBRxData register. This bit is cleared by hardware when the last word of the current packet is read from USBRxData."> + <Enum name="DISABLED_" start="0" description="Disabled." /> + <Enum name="ENABLED_" start="1" description="Enabled." /> + </BitField> + <BitField start="1" size="1" name="WR_EN" description="Write mode control. Enables writing data to the IN endpoint buffer for the endpoint specified in the LOG_ENDPOINT field using the USBTxData register. This bit is cleared by hardware when the number of bytes in USBTxLen have been sent."> + <Enum name="DISABLED_" start="0" description="Disabled." /> + <Enum name="ENABLED_" start="1" description="Enabled." /> + </BitField> + <BitField start="2" size="4" name="LOG_ENDPOINT" description="Logical Endpoint number." /> + <BitField start="6" size="26" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x210" size="4" name="CMDCODE" access="WriteOnly" description="USB Command Code" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="8" size="8" name="CMD_PHASE" description="The command phase:"> + <Enum name="READ" start="0x02" description="Read" /> + <Enum name="WRITE" start="0x01" description="Write" /> + <Enum name="COMMAND" start="0x05" description="Command" /> + </BitField> + <BitField start="16" size="8" name="CMD_CODE_WDATA" description="This is a multi-purpose field. When CMD_PHASE is Command or Read, this field contains the code for the command (CMD_CODE). When CMD_PHASE is Write, this field contains the command write data (CMD_WDATA)." /> + <BitField start="24" size="8" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x214" size="4" name="CMDDATA" access="ReadOnly" description="USB Command Data" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="CMD_RDATA" description="Command Read Data." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x250" size="4" name="DMARST" access="ReadOnly" description="USB DMA Request Status" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="EPRST0" description="Control endpoint OUT (DMA cannot be enabled for this endpoint and EP0 bit must be 0)." /> + <BitField start="1" size="1" name="EPRST1" description="Control endpoint IN (DMA cannot be enabled for this endpoint and EP1 bit must be 0)." /> + <BitField start="2" size="1" name="EPRST2" description="Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." /> + <BitField start="3" size="1" name="EPRST3" description="Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." /> + <BitField start="4" size="1" name="EPRST4" description="Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." /> + <BitField start="5" size="1" name="EPRST5" description="Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." /> + <BitField start="6" size="1" name="EPRST6" description="Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." /> + <BitField start="7" size="1" name="EPRST7" description="Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." /> + <BitField start="8" size="1" name="EPRST8" description="Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." /> + <BitField start="9" size="1" name="EPRST9" description="Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." /> + <BitField start="10" size="1" name="EPRST10" description="Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." /> + <BitField start="11" size="1" name="EPRST11" description="Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." /> + <BitField start="12" size="1" name="EPRST12" description="Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." /> + <BitField start="13" size="1" name="EPRST13" description="Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." /> + <BitField start="14" size="1" name="EPRST14" description="Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." /> + <BitField start="15" size="1" name="EPRST15" description="Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." /> + <BitField start="16" size="1" name="EPRST16" description="Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." /> + <BitField start="17" size="1" name="EPRST17" description="Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." /> + <BitField start="18" size="1" name="EPRST18" description="Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." /> + <BitField start="19" size="1" name="EPRST19" description="Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." /> + <BitField start="20" size="1" name="EPRST20" description="Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." /> + <BitField start="21" size="1" name="EPRST21" description="Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." /> + <BitField start="22" size="1" name="EPRST22" description="Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." /> + <BitField start="23" size="1" name="EPRST23" description="Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." /> + <BitField start="24" size="1" name="EPRST24" description="Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." /> + <BitField start="25" size="1" name="EPRST25" description="Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." /> + <BitField start="26" size="1" name="EPRST26" description="Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." /> + <BitField start="27" size="1" name="EPRST27" description="Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." /> + <BitField start="28" size="1" name="EPRST28" description="Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." /> + <BitField start="29" size="1" name="EPRST29" description="Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." /> + <BitField start="30" size="1" name="EPRST30" description="Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." /> + <BitField start="31" size="1" name="EPRST31" description="Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." /> + </Register> + <Register start="+0x254" size="4" name="DMARCLR" access="WriteOnly" description="USB DMA Request Clear" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="EPRCLR0" description="Control endpoint OUT (DMA cannot be enabled for this endpoint and the EP0 bit must be 0)." /> + <BitField start="1" size="1" name="EPRCLR1" description="Control endpoint IN (DMA cannot be enabled for this endpoint and the EP1 bit must be 0)." /> + <BitField start="2" size="1" name="EPRCLR2" description="Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." /> + <BitField start="3" size="1" name="EPRCLR3" description="Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." /> + <BitField start="4" size="1" name="EPRCLR4" description="Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." /> + <BitField start="5" size="1" name="EPRCLR5" description="Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." /> + <BitField start="6" size="1" name="EPRCLR6" description="Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." /> + <BitField start="7" size="1" name="EPRCLR7" description="Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." /> + <BitField start="8" size="1" name="EPRCLR8" description="Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." /> + <BitField start="9" size="1" name="EPRCLR9" description="Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." /> + <BitField start="10" size="1" name="EPRCLR10" description="Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." /> + <BitField start="11" size="1" name="EPRCLR11" description="Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." /> + <BitField start="12" size="1" name="EPRCLR12" description="Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." /> + <BitField start="13" size="1" name="EPRCLR13" description="Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." /> + <BitField start="14" size="1" name="EPRCLR14" description="Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." /> + <BitField start="15" size="1" name="EPRCLR15" description="Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." /> + <BitField start="16" size="1" name="EPRCLR16" description="Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." /> + <BitField start="17" size="1" name="EPRCLR17" description="Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." /> + <BitField start="18" size="1" name="EPRCLR18" description="Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." /> + <BitField start="19" size="1" name="EPRCLR19" description="Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." /> + <BitField start="20" size="1" name="EPRCLR20" description="Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." /> + <BitField start="21" size="1" name="EPRCLR21" description="Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." /> + <BitField start="22" size="1" name="EPRCLR22" description="Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." /> + <BitField start="23" size="1" name="EPRCLR23" description="Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." /> + <BitField start="24" size="1" name="EPRCLR24" description="Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." /> + <BitField start="25" size="1" name="EPRCLR25" description="Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." /> + <BitField start="26" size="1" name="EPRCLR26" description="Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." /> + <BitField start="27" size="1" name="EPRCLR27" description="Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." /> + <BitField start="28" size="1" name="EPRCLR28" description="Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." /> + <BitField start="29" size="1" name="EPRCLR29" description="Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." /> + <BitField start="30" size="1" name="EPRCLR30" description="Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." /> + <BitField start="31" size="1" name="EPRCLR31" description="Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." /> + </Register> + <Register start="+0x258" size="4" name="DMARSET" access="WriteOnly" description="USB DMA Request Set" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="EPRSET0" description="Control endpoint OUT (DMA cannot be enabled for this endpoint and the EP0 bit must be 0)." /> + <BitField start="1" size="1" name="EPRSET1" description="Control endpoint IN (DMA cannot be enabled for this endpoint and the EP1 bit must be 0)." /> + <BitField start="2" size="1" name="EPRSET2" description="Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." /> + <BitField start="3" size="1" name="EPRSET3" description="Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." /> + <BitField start="4" size="1" name="EPRSET4" description="Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." /> + <BitField start="5" size="1" name="EPRSET5" description="Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." /> + <BitField start="6" size="1" name="EPRSET6" description="Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." /> + <BitField start="7" size="1" name="EPRSET7" description="Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." /> + <BitField start="8" size="1" name="EPRSET8" description="Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." /> + <BitField start="9" size="1" name="EPRSET9" description="Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." /> + <BitField start="10" size="1" name="EPRSET10" description="Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." /> + <BitField start="11" size="1" name="EPRSET11" description="Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." /> + <BitField start="12" size="1" name="EPRSET12" description="Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." /> + <BitField start="13" size="1" name="EPRSET13" description="Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." /> + <BitField start="14" size="1" name="EPRSET14" description="Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." /> + <BitField start="15" size="1" name="EPRSET15" description="Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." /> + <BitField start="16" size="1" name="EPRSET16" description="Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." /> + <BitField start="17" size="1" name="EPRSET17" description="Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." /> + <BitField start="18" size="1" name="EPRSET18" description="Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." /> + <BitField start="19" size="1" name="EPRSET19" description="Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." /> + <BitField start="20" size="1" name="EPRSET20" description="Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." /> + <BitField start="21" size="1" name="EPRSET21" description="Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." /> + <BitField start="22" size="1" name="EPRSET22" description="Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." /> + <BitField start="23" size="1" name="EPRSET23" description="Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." /> + <BitField start="24" size="1" name="EPRSET24" description="Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." /> + <BitField start="25" size="1" name="EPRSET25" description="Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." /> + <BitField start="26" size="1" name="EPRSET26" description="Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." /> + <BitField start="27" size="1" name="EPRSET27" description="Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." /> + <BitField start="28" size="1" name="EPRSET28" description="Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." /> + <BitField start="29" size="1" name="EPRSET29" description="Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." /> + <BitField start="30" size="1" name="EPRSET30" description="Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." /> + <BitField start="31" size="1" name="EPRSET31" description="Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." /> + </Register> + <Register start="+0x280" size="4" name="UDCAH" access="Read/Write" description="USB UDCA Head" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="7" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written. The UDCA is aligned to 128-byte boundaries." /> + <BitField start="7" size="25" name="UDCA_ADDR" description="Start address of the UDCA." /> + </Register> + <Register start="+0x284" size="4" name="EPDMAST" access="ReadOnly" description="USB Endpoint DMA Status" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="EP_DMA_ST0" description="Control endpoint OUT (DMA cannot be enabled for this endpoint and the EP0_DMA_ENABLE bit must be 0)." /> + <BitField start="1" size="1" name="EP_DMA_ST1" description="Control endpoint IN (DMA cannot be enabled for this endpoint and the EP1_DMA_ENABLE bit must be 0)." /> + <BitField start="2" size="1" name="EP_DMA_ST2" description="Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." /> + <BitField start="3" size="1" name="EP_DMA_ST3" description="Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." /> + <BitField start="4" size="1" name="EP_DMA_ST4" description="Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." /> + <BitField start="5" size="1" name="EP_DMA_ST5" description="Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." /> + <BitField start="6" size="1" name="EP_DMA_ST6" description="Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." /> + <BitField start="7" size="1" name="EP_DMA_ST7" description="Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." /> + <BitField start="8" size="1" name="EP_DMA_ST8" description="Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." /> + <BitField start="9" size="1" name="EP_DMA_ST9" description="Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." /> + <BitField start="10" size="1" name="EP_DMA_ST10" description="Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." /> + <BitField start="11" size="1" name="EP_DMA_ST11" description="Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." /> + <BitField start="12" size="1" name="EP_DMA_ST12" description="Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." /> + <BitField start="13" size="1" name="EP_DMA_ST13" description="Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." /> + <BitField start="14" size="1" name="EP_DMA_ST14" description="Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." /> + <BitField start="15" size="1" name="EP_DMA_ST15" description="Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." /> + <BitField start="16" size="1" name="EP_DMA_ST16" description="Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." /> + <BitField start="17" size="1" name="EP_DMA_ST17" description="Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." /> + <BitField start="18" size="1" name="EP_DMA_ST18" description="Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." /> + <BitField start="19" size="1" name="EP_DMA_ST19" description="Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." /> + <BitField start="20" size="1" name="EP_DMA_ST20" description="Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." /> + <BitField start="21" size="1" name="EP_DMA_ST21" description="Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." /> + <BitField start="22" size="1" name="EP_DMA_ST22" description="Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." /> + <BitField start="23" size="1" name="EP_DMA_ST23" description="Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." /> + <BitField start="24" size="1" name="EP_DMA_ST24" description="Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." /> + <BitField start="25" size="1" name="EP_DMA_ST25" description="Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." /> + <BitField start="26" size="1" name="EP_DMA_ST26" description="Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." /> + <BitField start="27" size="1" name="EP_DMA_ST27" description="Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." /> + <BitField start="28" size="1" name="EP_DMA_ST28" description="Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." /> + <BitField start="29" size="1" name="EP_DMA_ST29" description="Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." /> + <BitField start="30" size="1" name="EP_DMA_ST30" description="Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." /> + <BitField start="31" size="1" name="EP_DMA_ST31" description="Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." /> + </Register> + <Register start="+0x288" size="4" name="EPDMAEN" access="WriteOnly" description="USB Endpoint DMA Enable" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="EP_DMA_EN0" description="Control endpoint OUT (DMA cannot be enabled for this endpoint and the EP0_DMA_ENABLE bit value must be 0)." /> + <BitField start="1" size="1" name="EP_DMA_EN1" description="Control endpoint IN (DMA cannot be enabled for this endpoint and the EP1_DMA_ENABLE bit must be 0)." /> + <BitField start="2" size="30" name="EP_DMA_EN" description="Endpoint xx(2 <= xx <= 31) DMA enable control bit. 0 = No effect. 1 = Enable the DMA operation for endpoint EPxx." /> + </Register> + <Register start="+0x28C" size="4" name="EPDMADIS" access="WriteOnly" description="USB Endpoint DMA Disable" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="EP_DMA_DIS0" description="Control endpoint OUT (DMA cannot be enabled for this endpoint and the EP0_DMA_DISABLE bit value must be 0)." /> + <BitField start="1" size="1" name="EP_DMA_DIS1" description="Control endpoint IN (DMA cannot be enabled for this endpoint and the EP1_DMA_DISABLE bit value must be 0)." /> + <BitField start="2" size="1" name="EP_DMA_DIS2" description="Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." /> + <BitField start="3" size="1" name="EP_DMA_DIS3" description="Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." /> + <BitField start="4" size="1" name="EP_DMA_DIS4" description="Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." /> + <BitField start="5" size="1" name="EP_DMA_DIS5" description="Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." /> + <BitField start="6" size="1" name="EP_DMA_DIS6" description="Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." /> + <BitField start="7" size="1" name="EP_DMA_DIS7" description="Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." /> + <BitField start="8" size="1" name="EP_DMA_DIS8" description="Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." /> + <BitField start="9" size="1" name="EP_DMA_DIS9" description="Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." /> + <BitField start="10" size="1" name="EP_DMA_DIS10" description="Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." /> + <BitField start="11" size="1" name="EP_DMA_DIS11" description="Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." /> + <BitField start="12" size="1" name="EP_DMA_DIS12" description="Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." /> + <BitField start="13" size="1" name="EP_DMA_DIS13" description="Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." /> + <BitField start="14" size="1" name="EP_DMA_DIS14" description="Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." /> + <BitField start="15" size="1" name="EP_DMA_DIS15" description="Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." /> + <BitField start="16" size="1" name="EP_DMA_DIS16" description="Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." /> + <BitField start="17" size="1" name="EP_DMA_DIS17" description="Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." /> + <BitField start="18" size="1" name="EP_DMA_DIS18" description="Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." /> + <BitField start="19" size="1" name="EP_DMA_DIS19" description="Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." /> + <BitField start="20" size="1" name="EP_DMA_DIS20" description="Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." /> + <BitField start="21" size="1" name="EP_DMA_DIS21" description="Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." /> + <BitField start="22" size="1" name="EP_DMA_DIS22" description="Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." /> + <BitField start="23" size="1" name="EP_DMA_DIS23" description="Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." /> + <BitField start="24" size="1" name="EP_DMA_DIS24" description="Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." /> + <BitField start="25" size="1" name="EP_DMA_DIS25" description="Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." /> + <BitField start="26" size="1" name="EP_DMA_DIS26" description="Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." /> + <BitField start="27" size="1" name="EP_DMA_DIS27" description="Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." /> + <BitField start="28" size="1" name="EP_DMA_DIS28" description="Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." /> + <BitField start="29" size="1" name="EP_DMA_DIS29" description="Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." /> + <BitField start="30" size="1" name="EP_DMA_DIS30" description="Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." /> + <BitField start="31" size="1" name="EP_DMA_DIS31" description="Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." /> + </Register> + <Register start="+0x290" size="4" name="DMAINTST" access="ReadOnly" description="USB DMA Interrupt Status" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="EOT" description="End of Transfer Interrupt bit."> + <Enum name="ALL_BITS_IN_THE_USBE" start="0" description="All bits in the USBEoTIntSt register are 0." /> + <Enum name="AT_LEAST_ONE_BIT_IN_" start="1" description="At least one bit in the USBEoTIntSt is set." /> + </BitField> + <BitField start="1" size="1" name="NDDR" description="New DD Request Interrupt bit."> + <Enum name="ALL_BITS_IN_THE_USBN" start="0" description="All bits in the USBNDDRIntSt register are 0." /> + <Enum name="AT_LEAST_ONE_BIT_IN_" start="1" description="At least one bit in the USBNDDRIntSt is set." /> + </BitField> + <BitField start="2" size="1" name="ERR" description="System Error Interrupt bit."> + <Enum name="ALL_BITS_IN_THE_USBS" start="0" description="All bits in the USBSysErrIntSt register are 0." /> + <Enum name="AT_LEAST_ONE_BIT_IN_" start="1" description="At least one bit in the USBSysErrIntSt is set." /> + </BitField> + <BitField start="3" size="29" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x294" size="4" name="DMAINTEN" access="Read/Write" description="USB DMA Interrupt Enable" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="EOT" description="End of Transfer Interrupt enable bit."> + <Enum name="DISABLED_" start="0" description="Disabled." /> + <Enum name="ENABLED_" start="1" description="Enabled." /> + </BitField> + <BitField start="1" size="1" name="NDDR" description="New DD Request Interrupt enable bit."> + <Enum name="DISABLED_" start="0" description="Disabled." /> + <Enum name="ENABLED_" start="1" description="Enabled." /> + </BitField> + <BitField start="2" size="1" name="ERR" description="System Error Interrupt enable bit."> + <Enum name="DISABLED_" start="0" description="Disabled." /> + <Enum name="ENABLED_" start="1" description="Enabled." /> + </BitField> + <BitField start="3" size="29" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x2A0" size="4" name="EOTINTST" access="ReadOnly" description="USB End of Transfer Interrupt Status" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="EPTXINTST0" description="Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." /> + <BitField start="1" size="1" name="EPTXINTST1" description="Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." /> + <BitField start="2" size="1" name="EPTXINTST2" description="Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." /> + <BitField start="3" size="1" name="EPTXINTST3" description="Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." /> + <BitField start="4" size="1" name="EPTXINTST4" description="Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." /> + <BitField start="5" size="1" name="EPTXINTST5" description="Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." /> + <BitField start="6" size="1" name="EPTXINTST6" description="Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." /> + <BitField start="7" size="1" name="EPTXINTST7" description="Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." /> + <BitField start="8" size="1" name="EPTXINTST8" description="Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." /> + <BitField start="9" size="1" name="EPTXINTST9" description="Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." /> + <BitField start="10" size="1" name="EPTXINTST10" description="Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." /> + <BitField start="11" size="1" name="EPTXINTST11" description="Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." /> + <BitField start="12" size="1" name="EPTXINTST12" description="Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." /> + <BitField start="13" size="1" name="EPTXINTST13" description="Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." /> + <BitField start="14" size="1" name="EPTXINTST14" description="Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." /> + <BitField start="15" size="1" name="EPTXINTST15" description="Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." /> + <BitField start="16" size="1" name="EPTXINTST16" description="Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." /> + <BitField start="17" size="1" name="EPTXINTST17" description="Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." /> + <BitField start="18" size="1" name="EPTXINTST18" description="Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." /> + <BitField start="19" size="1" name="EPTXINTST19" description="Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." /> + <BitField start="20" size="1" name="EPTXINTST20" description="Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." /> + <BitField start="21" size="1" name="EPTXINTST21" description="Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." /> + <BitField start="22" size="1" name="EPTXINTST22" description="Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." /> + <BitField start="23" size="1" name="EPTXINTST23" description="Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." /> + <BitField start="24" size="1" name="EPTXINTST24" description="Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." /> + <BitField start="25" size="1" name="EPTXINTST25" description="Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." /> + <BitField start="26" size="1" name="EPTXINTST26" description="Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." /> + <BitField start="27" size="1" name="EPTXINTST27" description="Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." /> + <BitField start="28" size="1" name="EPTXINTST28" description="Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." /> + <BitField start="29" size="1" name="EPTXINTST29" description="Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." /> + <BitField start="30" size="1" name="EPTXINTST30" description="Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." /> + <BitField start="31" size="1" name="EPTXINTST31" description="Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." /> + </Register> + <Register start="+0x2A4" size="4" name="EOTINTCLR" access="WriteOnly" description="USB End of Transfer Interrupt Clear" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="EPTXINTCLR0" description="Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." /> + <BitField start="1" size="1" name="EPTXINTCLR1" description="Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." /> + <BitField start="2" size="1" name="EPTXINTCLR2" description="Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." /> + <BitField start="3" size="1" name="EPTXINTCLR3" description="Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." /> + <BitField start="4" size="1" name="EPTXINTCLR4" description="Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." /> + <BitField start="5" size="1" name="EPTXINTCLR5" description="Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." /> + <BitField start="6" size="1" name="EPTXINTCLR6" description="Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." /> + <BitField start="7" size="1" name="EPTXINTCLR7" description="Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." /> + <BitField start="8" size="1" name="EPTXINTCLR8" description="Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." /> + <BitField start="9" size="1" name="EPTXINTCLR9" description="Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." /> + <BitField start="10" size="1" name="EPTXINTCLR10" description="Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." /> + <BitField start="11" size="1" name="EPTXINTCLR11" description="Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." /> + <BitField start="12" size="1" name="EPTXINTCLR12" description="Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." /> + <BitField start="13" size="1" name="EPTXINTCLR13" description="Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." /> + <BitField start="14" size="1" name="EPTXINTCLR14" description="Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." /> + <BitField start="15" size="1" name="EPTXINTCLR15" description="Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." /> + <BitField start="16" size="1" name="EPTXINTCLR16" description="Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." /> + <BitField start="17" size="1" name="EPTXINTCLR17" description="Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." /> + <BitField start="18" size="1" name="EPTXINTCLR18" description="Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." /> + <BitField start="19" size="1" name="EPTXINTCLR19" description="Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." /> + <BitField start="20" size="1" name="EPTXINTCLR20" description="Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." /> + <BitField start="21" size="1" name="EPTXINTCLR21" description="Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." /> + <BitField start="22" size="1" name="EPTXINTCLR22" description="Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." /> + <BitField start="23" size="1" name="EPTXINTCLR23" description="Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." /> + <BitField start="24" size="1" name="EPTXINTCLR24" description="Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." /> + <BitField start="25" size="1" name="EPTXINTCLR25" description="Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." /> + <BitField start="26" size="1" name="EPTXINTCLR26" description="Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." /> + <BitField start="27" size="1" name="EPTXINTCLR27" description="Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." /> + <BitField start="28" size="1" name="EPTXINTCLR28" description="Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." /> + <BitField start="29" size="1" name="EPTXINTCLR29" description="Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." /> + <BitField start="30" size="1" name="EPTXINTCLR30" description="Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." /> + <BitField start="31" size="1" name="EPTXINTCLR31" description="Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." /> + </Register> + <Register start="+0x2A8" size="4" name="EOTINTSET" access="WriteOnly" description="USB End of Transfer Interrupt Set" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="EPTXINTSET0" description="Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." /> + <BitField start="1" size="1" name="EPTXINTSET1" description="Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." /> + <BitField start="2" size="1" name="EPTXINTSET2" description="Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." /> + <BitField start="3" size="1" name="EPTXINTSET3" description="Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." /> + <BitField start="4" size="1" name="EPTXINTSET4" description="Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." /> + <BitField start="5" size="1" name="EPTXINTSET5" description="Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." /> + <BitField start="6" size="1" name="EPTXINTSET6" description="Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." /> + <BitField start="7" size="1" name="EPTXINTSET7" description="Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." /> + <BitField start="8" size="1" name="EPTXINTSET8" description="Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." /> + <BitField start="9" size="1" name="EPTXINTSET9" description="Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." /> + <BitField start="10" size="1" name="EPTXINTSET10" description="Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." /> + <BitField start="11" size="1" name="EPTXINTSET11" description="Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." /> + <BitField start="12" size="1" name="EPTXINTSET12" description="Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." /> + <BitField start="13" size="1" name="EPTXINTSET13" description="Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." /> + <BitField start="14" size="1" name="EPTXINTSET14" description="Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." /> + <BitField start="15" size="1" name="EPTXINTSET15" description="Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." /> + <BitField start="16" size="1" name="EPTXINTSET16" description="Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." /> + <BitField start="17" size="1" name="EPTXINTSET17" description="Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." /> + <BitField start="18" size="1" name="EPTXINTSET18" description="Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." /> + <BitField start="19" size="1" name="EPTXINTSET19" description="Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." /> + <BitField start="20" size="1" name="EPTXINTSET20" description="Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." /> + <BitField start="21" size="1" name="EPTXINTSET21" description="Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." /> + <BitField start="22" size="1" name="EPTXINTSET22" description="Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." /> + <BitField start="23" size="1" name="EPTXINTSET23" description="Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." /> + <BitField start="24" size="1" name="EPTXINTSET24" description="Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." /> + <BitField start="25" size="1" name="EPTXINTSET25" description="Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." /> + <BitField start="26" size="1" name="EPTXINTSET26" description="Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." /> + <BitField start="27" size="1" name="EPTXINTSET27" description="Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." /> + <BitField start="28" size="1" name="EPTXINTSET28" description="Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." /> + <BitField start="29" size="1" name="EPTXINTSET29" description="Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." /> + <BitField start="30" size="1" name="EPTXINTSET30" description="Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." /> + <BitField start="31" size="1" name="EPTXINTSET31" description="Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." /> + </Register> + <Register start="+0x2AC" size="4" name="NDDRINTST" access="ReadOnly" description="USB New DD Request Interrupt Status" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="EPNDDINTST0" description="Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." /> + <BitField start="1" size="1" name="EPNDDINTST1" description="Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." /> + <BitField start="2" size="1" name="EPNDDINTST2" description="Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." /> + <BitField start="3" size="1" name="EPNDDINTST3" description="Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." /> + <BitField start="4" size="1" name="EPNDDINTST4" description="Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." /> + <BitField start="5" size="1" name="EPNDDINTST5" description="Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." /> + <BitField start="6" size="1" name="EPNDDINTST6" description="Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." /> + <BitField start="7" size="1" name="EPNDDINTST7" description="Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." /> + <BitField start="8" size="1" name="EPNDDINTST8" description="Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." /> + <BitField start="9" size="1" name="EPNDDINTST9" description="Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." /> + <BitField start="10" size="1" name="EPNDDINTST10" description="Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." /> + <BitField start="11" size="1" name="EPNDDINTST11" description="Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." /> + <BitField start="12" size="1" name="EPNDDINTST12" description="Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." /> + <BitField start="13" size="1" name="EPNDDINTST13" description="Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." /> + <BitField start="14" size="1" name="EPNDDINTST14" description="Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." /> + <BitField start="15" size="1" name="EPNDDINTST15" description="Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." /> + <BitField start="16" size="1" name="EPNDDINTST16" description="Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." /> + <BitField start="17" size="1" name="EPNDDINTST17" description="Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." /> + <BitField start="18" size="1" name="EPNDDINTST18" description="Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." /> + <BitField start="19" size="1" name="EPNDDINTST19" description="Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." /> + <BitField start="20" size="1" name="EPNDDINTST20" description="Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." /> + <BitField start="21" size="1" name="EPNDDINTST21" description="Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." /> + <BitField start="22" size="1" name="EPNDDINTST22" description="Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." /> + <BitField start="23" size="1" name="EPNDDINTST23" description="Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." /> + <BitField start="24" size="1" name="EPNDDINTST24" description="Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." /> + <BitField start="25" size="1" name="EPNDDINTST25" description="Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." /> + <BitField start="26" size="1" name="EPNDDINTST26" description="Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." /> + <BitField start="27" size="1" name="EPNDDINTST27" description="Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." /> + <BitField start="28" size="1" name="EPNDDINTST28" description="Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." /> + <BitField start="29" size="1" name="EPNDDINTST29" description="Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." /> + <BitField start="30" size="1" name="EPNDDINTST30" description="Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." /> + <BitField start="31" size="1" name="EPNDDINTST31" description="Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." /> + </Register> + <Register start="+0x2B0" size="4" name="NDDRINTCLR" access="WriteOnly" description="USB New DD Request Interrupt Clear" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="EPNDDINTCLR0" description="Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." /> + <BitField start="1" size="1" name="EPNDDINTCLR1" description="Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." /> + <BitField start="2" size="1" name="EPNDDINTCLR2" description="Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." /> + <BitField start="3" size="1" name="EPNDDINTCLR3" description="Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." /> + <BitField start="4" size="1" name="EPNDDINTCLR4" description="Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." /> + <BitField start="5" size="1" name="EPNDDINTCLR5" description="Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." /> + <BitField start="6" size="1" name="EPNDDINTCLR6" description="Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." /> + <BitField start="7" size="1" name="EPNDDINTCLR7" description="Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." /> + <BitField start="8" size="1" name="EPNDDINTCLR8" description="Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." /> + <BitField start="9" size="1" name="EPNDDINTCLR9" description="Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." /> + <BitField start="10" size="1" name="EPNDDINTCLR10" description="Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." /> + <BitField start="11" size="1" name="EPNDDINTCLR11" description="Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." /> + <BitField start="12" size="1" name="EPNDDINTCLR12" description="Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." /> + <BitField start="13" size="1" name="EPNDDINTCLR13" description="Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." /> + <BitField start="14" size="1" name="EPNDDINTCLR14" description="Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." /> + <BitField start="15" size="1" name="EPNDDINTCLR15" description="Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." /> + <BitField start="16" size="1" name="EPNDDINTCLR16" description="Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." /> + <BitField start="17" size="1" name="EPNDDINTCLR17" description="Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." /> + <BitField start="18" size="1" name="EPNDDINTCLR18" description="Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." /> + <BitField start="19" size="1" name="EPNDDINTCLR19" description="Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." /> + <BitField start="20" size="1" name="EPNDDINTCLR20" description="Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." /> + <BitField start="21" size="1" name="EPNDDINTCLR21" description="Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." /> + <BitField start="22" size="1" name="EPNDDINTCLR22" description="Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." /> + <BitField start="23" size="1" name="EPNDDINTCLR23" description="Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." /> + <BitField start="24" size="1" name="EPNDDINTCLR24" description="Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." /> + <BitField start="25" size="1" name="EPNDDINTCLR25" description="Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." /> + <BitField start="26" size="1" name="EPNDDINTCLR26" description="Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." /> + <BitField start="27" size="1" name="EPNDDINTCLR27" description="Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." /> + <BitField start="28" size="1" name="EPNDDINTCLR28" description="Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." /> + <BitField start="29" size="1" name="EPNDDINTCLR29" description="Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." /> + <BitField start="30" size="1" name="EPNDDINTCLR30" description="Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." /> + <BitField start="31" size="1" name="EPNDDINTCLR31" description="Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." /> + </Register> + <Register start="+0x2B4" size="4" name="NDDRINTSET" access="WriteOnly" description="USB New DD Request Interrupt Set" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="EPNDDINTSET0" description="Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." /> + <BitField start="1" size="1" name="EPNDDINTSET1" description="Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." /> + <BitField start="2" size="1" name="EPNDDINTSET2" description="Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." /> + <BitField start="3" size="1" name="EPNDDINTSET3" description="Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." /> + <BitField start="4" size="1" name="EPNDDINTSET4" description="Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." /> + <BitField start="5" size="1" name="EPNDDINTSET5" description="Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." /> + <BitField start="6" size="1" name="EPNDDINTSET6" description="Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." /> + <BitField start="7" size="1" name="EPNDDINTSET7" description="Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." /> + <BitField start="8" size="1" name="EPNDDINTSET8" description="Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." /> + <BitField start="9" size="1" name="EPNDDINTSET9" description="Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." /> + <BitField start="10" size="1" name="EPNDDINTSET10" description="Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." /> + <BitField start="11" size="1" name="EPNDDINTSET11" description="Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." /> + <BitField start="12" size="1" name="EPNDDINTSET12" description="Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." /> + <BitField start="13" size="1" name="EPNDDINTSET13" description="Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." /> + <BitField start="14" size="1" name="EPNDDINTSET14" description="Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." /> + <BitField start="15" size="1" name="EPNDDINTSET15" description="Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." /> + <BitField start="16" size="1" name="EPNDDINTSET16" description="Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." /> + <BitField start="17" size="1" name="EPNDDINTSET17" description="Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." /> + <BitField start="18" size="1" name="EPNDDINTSET18" description="Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." /> + <BitField start="19" size="1" name="EPNDDINTSET19" description="Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." /> + <BitField start="20" size="1" name="EPNDDINTSET20" description="Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." /> + <BitField start="21" size="1" name="EPNDDINTSET21" description="Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." /> + <BitField start="22" size="1" name="EPNDDINTSET22" description="Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." /> + <BitField start="23" size="1" name="EPNDDINTSET23" description="Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." /> + <BitField start="24" size="1" name="EPNDDINTSET24" description="Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." /> + <BitField start="25" size="1" name="EPNDDINTSET25" description="Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." /> + <BitField start="26" size="1" name="EPNDDINTSET26" description="Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." /> + <BitField start="27" size="1" name="EPNDDINTSET27" description="Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." /> + <BitField start="28" size="1" name="EPNDDINTSET28" description="Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." /> + <BitField start="29" size="1" name="EPNDDINTSET29" description="Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." /> + <BitField start="30" size="1" name="EPNDDINTSET30" description="Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." /> + <BitField start="31" size="1" name="EPNDDINTSET31" description="Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." /> + </Register> + <Register start="+0x2B8" size="4" name="SYSERRINTST" access="ReadOnly" description="USB System Error Interrupt Status" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="EPERRINTST0" description="Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." /> + <BitField start="1" size="1" name="EPERRINTST1" description="Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." /> + <BitField start="2" size="1" name="EPERRINTST2" description="Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." /> + <BitField start="3" size="1" name="EPERRINTST3" description="Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." /> + <BitField start="4" size="1" name="EPERRINTST4" description="Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." /> + <BitField start="5" size="1" name="EPERRINTST5" description="Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." /> + <BitField start="6" size="1" name="EPERRINTST6" description="Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." /> + <BitField start="7" size="1" name="EPERRINTST7" description="Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." /> + <BitField start="8" size="1" name="EPERRINTST8" description="Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." /> + <BitField start="9" size="1" name="EPERRINTST9" description="Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." /> + <BitField start="10" size="1" name="EPERRINTST10" description="Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." /> + <BitField start="11" size="1" name="EPERRINTST11" description="Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." /> + <BitField start="12" size="1" name="EPERRINTST12" description="Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." /> + <BitField start="13" size="1" name="EPERRINTST13" description="Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." /> + <BitField start="14" size="1" name="EPERRINTST14" description="Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." /> + <BitField start="15" size="1" name="EPERRINTST15" description="Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." /> + <BitField start="16" size="1" name="EPERRINTST16" description="Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." /> + <BitField start="17" size="1" name="EPERRINTST17" description="Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." /> + <BitField start="18" size="1" name="EPERRINTST18" description="Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." /> + <BitField start="19" size="1" name="EPERRINTST19" description="Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." /> + <BitField start="20" size="1" name="EPERRINTST20" description="Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." /> + <BitField start="21" size="1" name="EPERRINTST21" description="Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." /> + <BitField start="22" size="1" name="EPERRINTST22" description="Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." /> + <BitField start="23" size="1" name="EPERRINTST23" description="Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." /> + <BitField start="24" size="1" name="EPERRINTST24" description="Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." /> + <BitField start="25" size="1" name="EPERRINTST25" description="Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." /> + <BitField start="26" size="1" name="EPERRINTST26" description="Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." /> + <BitField start="27" size="1" name="EPERRINTST27" description="Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." /> + <BitField start="28" size="1" name="EPERRINTST28" description="Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." /> + <BitField start="29" size="1" name="EPERRINTST29" description="Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." /> + <BitField start="30" size="1" name="EPERRINTST30" description="Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." /> + <BitField start="31" size="1" name="EPERRINTST31" description="Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." /> + </Register> + <Register start="+0x2BC" size="4" name="SYSERRINTCLR" access="WriteOnly" description="USB System Error Interrupt Clear" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="EPERRINTCLR0" description="Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." /> + <BitField start="1" size="1" name="EPERRINTCLR1" description="Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." /> + <BitField start="2" size="1" name="EPERRINTCLR2" description="Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." /> + <BitField start="3" size="1" name="EPERRINTCLR3" description="Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." /> + <BitField start="4" size="1" name="EPERRINTCLR4" description="Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." /> + <BitField start="5" size="1" name="EPERRINTCLR5" description="Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." /> + <BitField start="6" size="1" name="EPERRINTCLR6" description="Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." /> + <BitField start="7" size="1" name="EPERRINTCLR7" description="Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." /> + <BitField start="8" size="1" name="EPERRINTCLR8" description="Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." /> + <BitField start="9" size="1" name="EPERRINTCLR9" description="Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." /> + <BitField start="10" size="1" name="EPERRINTCLR10" description="Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." /> + <BitField start="11" size="1" name="EPERRINTCLR11" description="Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." /> + <BitField start="12" size="1" name="EPERRINTCLR12" description="Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." /> + <BitField start="13" size="1" name="EPERRINTCLR13" description="Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." /> + <BitField start="14" size="1" name="EPERRINTCLR14" description="Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." /> + <BitField start="15" size="1" name="EPERRINTCLR15" description="Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." /> + <BitField start="16" size="1" name="EPERRINTCLR16" description="Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." /> + <BitField start="17" size="1" name="EPERRINTCLR17" description="Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." /> + <BitField start="18" size="1" name="EPERRINTCLR18" description="Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." /> + <BitField start="19" size="1" name="EPERRINTCLR19" description="Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." /> + <BitField start="20" size="1" name="EPERRINTCLR20" description="Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." /> + <BitField start="21" size="1" name="EPERRINTCLR21" description="Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." /> + <BitField start="22" size="1" name="EPERRINTCLR22" description="Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." /> + <BitField start="23" size="1" name="EPERRINTCLR23" description="Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." /> + <BitField start="24" size="1" name="EPERRINTCLR24" description="Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." /> + <BitField start="25" size="1" name="EPERRINTCLR25" description="Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." /> + <BitField start="26" size="1" name="EPERRINTCLR26" description="Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." /> + <BitField start="27" size="1" name="EPERRINTCLR27" description="Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." /> + <BitField start="28" size="1" name="EPERRINTCLR28" description="Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." /> + <BitField start="29" size="1" name="EPERRINTCLR29" description="Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." /> + <BitField start="30" size="1" name="EPERRINTCLR30" description="Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." /> + <BitField start="31" size="1" name="EPERRINTCLR31" description="Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." /> + </Register> + <Register start="+0x2C0" size="4" name="SYSERRINTSET" access="WriteOnly" description="USB System Error Interrupt Set" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="EPERRINTSET0" description="Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." /> + <BitField start="1" size="1" name="EPERRINTSET1" description="Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." /> + <BitField start="2" size="1" name="EPERRINTSET2" description="Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." /> + <BitField start="3" size="1" name="EPERRINTSET3" description="Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." /> + <BitField start="4" size="1" name="EPERRINTSET4" description="Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." /> + <BitField start="5" size="1" name="EPERRINTSET5" description="Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." /> + <BitField start="6" size="1" name="EPERRINTSET6" description="Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." /> + <BitField start="7" size="1" name="EPERRINTSET7" description="Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." /> + <BitField start="8" size="1" name="EPERRINTSET8" description="Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." /> + <BitField start="9" size="1" name="EPERRINTSET9" description="Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." /> + <BitField start="10" size="1" name="EPERRINTSET10" description="Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." /> + <BitField start="11" size="1" name="EPERRINTSET11" description="Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." /> + <BitField start="12" size="1" name="EPERRINTSET12" description="Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." /> + <BitField start="13" size="1" name="EPERRINTSET13" description="Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." /> + <BitField start="14" size="1" name="EPERRINTSET14" description="Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." /> + <BitField start="15" size="1" name="EPERRINTSET15" description="Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." /> + <BitField start="16" size="1" name="EPERRINTSET16" description="Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." /> + <BitField start="17" size="1" name="EPERRINTSET17" description="Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." /> + <BitField start="18" size="1" name="EPERRINTSET18" description="Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." /> + <BitField start="19" size="1" name="EPERRINTSET19" description="Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." /> + <BitField start="20" size="1" name="EPERRINTSET20" description="Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." /> + <BitField start="21" size="1" name="EPERRINTSET21" description="Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." /> + <BitField start="22" size="1" name="EPERRINTSET22" description="Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." /> + <BitField start="23" size="1" name="EPERRINTSET23" description="Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." /> + <BitField start="24" size="1" name="EPERRINTSET24" description="Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." /> + <BitField start="25" size="1" name="EPERRINTSET25" description="Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." /> + <BitField start="26" size="1" name="EPERRINTSET26" description="Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." /> + <BitField start="27" size="1" name="EPERRINTSET27" description="Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." /> + <BitField start="28" size="1" name="EPERRINTSET28" description="Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." /> + <BitField start="29" size="1" name="EPERRINTSET29" description="Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." /> + <BitField start="30" size="1" name="EPERRINTSET30" description="Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." /> + <BitField start="31" size="1" name="EPERRINTSET31" description="Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." /> + </Register> + <Register start="+0x300" size="4" name="I2C_RX" access="ReadOnly" description="I2C Receive" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="8" name="RX_DATA" description="Receive data." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x300" size="4" name="I2C_TX" access="WriteOnly" description="I2C Transmit" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="8" name="TXDATA" description="Transmit data." /> + <BitField start="8" size="1" name="START" description="When 1, issue a START condition before transmitting this byte." /> + <BitField start="9" size="1" name="STOP" description="When 1, issue a STOP condition after transmitting this byte." /> + <BitField start="10" size="22" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x304" size="4" name="I2C_STS" access="ReadOnly" description="I2C Status" reset_value="0x0A00" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="TDI" description="Transaction Done Interrupt. This flag is set if a transaction completes successfully. It is cleared by writing a one to bit 0 of the status register. It is unaffected by slave transactions."> + <Enum name="TRANSACTION_HAS_NOT_" start="0" description="Transaction has not completed." /> + <Enum name="TRANSACTION_COMPLETE" start="1" description="Transaction completed." /> + </BitField> + <BitField start="1" size="1" name="AFI" description="Arbitration Failure Interrupt. When transmitting, if the SDA is low when SDAOUT is high, then this I2C has lost the arbitration to another device on the bus. The Arbitration Failure bit is set when this happens. It is cleared by writing a one to bit 1 of the status register."> + <Enum name="NO_ARBITRATION_FAILU" start="0" description="No arbitration failure on last transmission." /> + <Enum name="ARBITRATION_FAILURE_" start="1" description="Arbitration failure occurred on last transmission." /> + </BitField> + <BitField start="2" size="1" name="NAI" description="No Acknowledge Interrupt. After every byte of data is sent, the transmitter expects an acknowledge from the receiver. This bit is set if the acknowledge is not received. It is cleared when a byte is written to the master TX FIFO."> + <Enum name="LAST_TRANSMISSION_RE" start="0" description="Last transmission received an acknowledge." /> + <Enum name="LAST_TRANSMISSION_DI" start="1" description="Last transmission did not receive an acknowledge." /> + </BitField> + <BitField start="3" size="1" name="DRMI" description="Master Data Request Interrupt. Once a transmission is started, the transmitter must have data to transmit as long as it isn't followed by a stop condition or it will hold SCL low until more data is available. The Master Data Request bit is set when the master transmitter is data-starved. If the master TX FIFO is empty and the last byte did not have a STOP condition flag, then SCL is held low until the CPU writes another byte to transmit. This bit is cleared when a byte is written to the master TX FIFO."> + <Enum name="MASTER_TRANSMITTER_D" start="0" description="Master transmitter does not need data." /> + <Enum name="MASTER_TRANSMITTER_N" start="1" description="Master transmitter needs data." /> + </BitField> + <BitField start="4" size="1" name="DRSI" description="Slave Data Request Interrupt. Once a transmission is started, the transmitter must have data to transmit as long as it isn't followed by a STOP condition or it will hold SCL low until more data is available. The Slave Data Request bit is set when the slave transmitter is data-starved. If the slave TX FIFO is empty and the last byte transmitted was acknowledged, then SCL is held low until the CPU writes another byte to transmit. This bit is cleared when a byte is written to the slave Tx FIFO."> + <Enum name="SLAVE_TRANSMITTER_DO" start="0" description="Slave transmitter does not need data." /> + <Enum name="SLAVE_TRANSMITTER_NE" start="1" description="Slave transmitter needs data." /> + </BitField> + <BitField start="5" size="1" name="Active" description="Indicates whether the bus is busy. This bit is set when a START condition has been seen. It is cleared when a STOP condition is seen.." /> + <BitField start="6" size="1" name="SCL" description="The current value of the SCL signal." /> + <BitField start="7" size="1" name="SDA" description="The current value of the SDA signal." /> + <BitField start="8" size="1" name="RFF" description="Receive FIFO Full (RFF). This bit is set when the RX FIFO is full and cannot accept any more data. It is cleared when the RX FIFO is not full. If a byte arrives when the Receive FIFO is full, the SCL is held low until the CPU reads the RX FIFO and makes room for it."> + <Enum name="RX_FIFO_IS_NOT_FULL" start="0" description="RX FIFO is not full" /> + <Enum name="RX_FIFO_IS_FULL" start="1" description="RX FIFO is full" /> + </BitField> + <BitField start="9" size="1" name="RFE" description="Receive FIFO Empty. RFE is set when the RX FIFO is empty and is cleared when the RX FIFO contains valid data."> + <Enum name="RX_FIFO_CONTAINS_DAT" start="0" description="RX FIFO contains data." /> + <Enum name="RX_FIFO_IS_EMPTY" start="1" description="RX FIFO is empty" /> + </BitField> + <BitField start="10" size="1" name="TFF" description="Transmit FIFO Full. TFF is set when the TX FIFO is full and is cleared when the TX FIFO is not full."> + <Enum name="TX_FIFO_IS_NOT_FULL_" start="0" description="TX FIFO is not full." /> + <Enum name="TX_FIFO_IS_FULL" start="1" description="TX FIFO is full" /> + </BitField> + <BitField start="11" size="1" name="TFE" description="Transmit FIFO Empty. TFE is set when the TX FIFO is empty and is cleared when the TX FIFO contains valid data."> + <Enum name="TX_FIFO_CONTAINS_VAL" start="0" description="TX FIFO contains valid data." /> + <Enum name="TX_FIFO_IS_EMPTY" start="1" description="TX FIFO is empty" /> + </BitField> + <BitField start="12" size="20" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x308" size="4" name="I2C_CTL" access="Read/Write" description="I2C Control" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="TDIE" description="Transmit Done Interrupt Enable. This enables the TDI interrupt signalling that this I2C issued a STOP condition."> + <Enum name="DISABLE_THE_TDI_INTE" start="0" description="Disable the TDI interrupt." /> + <Enum name="ENABLE_THE_TDI_INTER" start="1" description="Enable the TDI interrupt." /> + </BitField> + <BitField start="1" size="1" name="AFIE" description="Transmitter Arbitration Failure Interrupt Enable. This enables the AFI interrupt which is asserted during transmission when trying to set SDA high, but the bus is driven low by another device."> + <Enum name="DISABLE_THE_AFI_" start="0" description="Disable the AFI." /> + <Enum name="ENABLE_THE_AFI_" start="1" description="Enable the AFI." /> + </BitField> + <BitField start="2" size="1" name="NAIE" description="Transmitter No Acknowledge Interrupt Enable. This enables the NAI interrupt signalling that transmitted byte was not acknowledged."> + <Enum name="DISABLE_THE_NAI_" start="0" description="Disable the NAI." /> + <Enum name="ENABLE_THE_NAI_" start="1" description="Enable the NAI." /> + </BitField> + <BitField start="3" size="1" name="DRMIE" description="Master Transmitter Data Request Interrupt Enable. This enables the DRMI interrupt which signals that the master transmitter has run out of data, has not issued a STOP, and is holding the SCL line low."> + <Enum name="DISABLE_THE_DRMI_INT" start="0" description="Disable the DRMI interrupt." /> + <Enum name="ENABLE_THE_DRMI_INTE" start="1" description="Enable the DRMI interrupt." /> + </BitField> + <BitField start="4" size="1" name="DRSIE" description="Slave Transmitter Data Request Interrupt Enable. This enables the DRSI interrupt which signals that the slave transmitter has run out of data and the last byte was acknowledged, so the SCL line is being held low."> + <Enum name="DISABLE_THE_DRSI_INT" start="0" description="Disable the DRSI interrupt." /> + <Enum name="ENABLE_THE_DRSI_INTE" start="1" description="Enable the DRSI interrupt." /> + </BitField> + <BitField start="5" size="1" name="REFIE" description="Receive FIFO Full Interrupt Enable. This enables the Receive FIFO Full interrupt to indicate that the receive FIFO cannot accept any more data."> + <Enum name="DISABLE_THE_RFFI_" start="0" description="Disable the RFFI." /> + <Enum name="ENABLE_THE_RFFI_" start="1" description="Enable the RFFI." /> + </BitField> + <BitField start="6" size="1" name="RFDAIE" description="Receive Data Available Interrupt Enable. This enables the DAI interrupt to indicate that data is available in the receive FIFO (i.e. not empty)."> + <Enum name="DISABLE_THE_DAI_" start="0" description="Disable the DAI." /> + <Enum name="ENABLE_THE_DAI_" start="1" description="Enable the DAI." /> + </BitField> + <BitField start="7" size="1" name="TFFIE" description="Transmit FIFO Not Full Interrupt Enable. This enables the Transmit FIFO Not Full interrupt to indicate that the more data can be written to the transmit FIFO. Note that this is not full. It is intended help the CPU to write to the I2C block only when there is room in the FIFO and do this without polling the status register."> + <Enum name="DISABLE_THE_TFFI_" start="0" description="Disable the TFFI." /> + <Enum name="ENABLE_THE_TFFI_" start="1" description="Enable the TFFI." /> + </BitField> + <BitField start="8" size="1" name="SRST" description="Soft reset. This is only needed in unusual circumstances. If a device issues a start condition without issuing a stop condition. A system timer may be used to reset the I2C if the bus remains busy longer than the time-out period. On a soft reset, the Tx and Rx FIFOs are flushed, I2C_STS register is cleared, and all internal state machines are reset to appear idle. The I2C_CLKHI, I2C_CLKLO and I2C_CTL (except Soft Reset Bit) are NOT modified by a soft reset."> + <Enum name="SEE_THE_TEXT_" start="0" description="See the text." /> + <Enum name="RESET_THE_I2C_TO_IDL" start="1" description="Reset the I2C to idle state. Self clearing." /> + </BitField> + <BitField start="9" size="23" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x30C" size="4" name="I2C_CLKHI" access="Read/Write" description="I2C Clock High" reset_value="0xB9" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="CDHI" description="Clock divisor high. This value is the number of 48 MHz clocks the serial clock (SCL) will be high." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x310" size="4" name="I2C_CLKLO" access="WriteOnly" description="I2C Clock Low" reset_value="0xB9" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="CDLO" description="Clock divisor low. This value is the number of 48 MHz clocks the serial clock (SCL) will be low." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0xFF4" size="4" name="CLKCTRL" access="Read/Write" description="OTG clock controller" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="HOST_CLK_EN" description="Host clock enable"> + <Enum name="DISABLE_THE_HOST_CLO" start="0" description="Disable the Host clock." /> + <Enum name="ENABLE_THE_HOST_CLOC" start="1" description="Enable the Host clock." /> + </BitField> + <BitField start="1" size="1" name="DEV_CLK_EN" description="Device clock enable"> + <Enum name="DISABLE_THE_DEVICE_C" start="0" description="Disable the Device clock." /> + <Enum name="ENABLE_THE_DEVICE_CL" start="1" description="Enable the Device clock." /> + </BitField> + <BitField start="2" size="1" name="I2C_CLK_EN" description="I2C clock enable"> + <Enum name="DISABLE_THE_I2C_CLOC" start="0" description="Disable the I2C clock." /> + <Enum name="ENABLE_THE_I2C_CLOCK" start="1" description="Enable the I2C clock." /> + </BitField> + <BitField start="3" size="1" name="OTG_CLK_EN" description="OTG clock enable. In device-only applications, this bit enables access to the PORTSEL register."> + <Enum name="DISABLE_THE_OTG_CLOC" start="0" description="Disable the OTG clock." /> + <Enum name="ENABLE_THE_OTG_CLOCK" start="1" description="Enable the OTG clock." /> + </BitField> + <BitField start="4" size="1" name="AHB_CLK_EN" description="AHB master clock enable"> + <Enum name="DISABLE_THE_AHB_CLOC" start="0" description="Disable the AHB clock." /> + <Enum name="ENABLE_THE_AHB_CLOCK" start="1" description="Enable the AHB clock." /> + </BitField> + <BitField start="5" size="27" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0xFF8" size="4" name="OTGClkSt" access="ReadOnly" description="OTG clock status" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="HOST_CLK_ON" description="Host clock status."> + <Enum name="HOST_CLOCK_IS_NOT_AV" start="0" description="Host clock is not available." /> + <Enum name="HOST_CLOCK_IS_AVAILA" start="1" description="Host clock is available." /> + </BitField> + <BitField start="1" size="1" name="DEV_CLK_ON" description="Device clock status."> + <Enum name="DEVICE_CLOCK_IS_NOT_" start="0" description="Device clock is not available." /> + <Enum name="DEVICE_CLOCK_IS_AVAI" start="1" description="Device clock is available." /> + </BitField> + <BitField start="2" size="1" name="I2C_CLK_ON" description="I2C clock status."> + <Enum name="I2C_CLOCK_IS_NOT_AVA" start="0" description="I2C clock is not available." /> + <Enum name="I2C_CLOCK_IS_AVAILAB" start="1" description="I2C clock is available." /> + </BitField> + <BitField start="3" size="1" name="OTG_CLK_ON" description="OTG clock status."> + <Enum name="OTG_CLOCK_IS_NOT_AVA" start="0" description="OTG clock is not available." /> + <Enum name="OTG_CLOCK_IS_AVAILAB" start="1" description="OTG clock is available." /> + </BitField> + <BitField start="4" size="1" name="AHB_CLK_ON" description="AHB master clock status."> + <Enum name="AHB_CLOCK_IS_NOT_AVA" start="0" description="AHB clock is not available." /> + <Enum name="AHB_CLOCK_IS_AVAILAB" start="1" description="AHB clock is available." /> + </BitField> + <BitField start="5" size="27" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + </RegisterGroup> + <RegisterGroup name="CRC" start="0x20090000" description="CRC engine "> + <Register start="+0x000" size="4" name="MODE" access="Read/Write" description="CRC mode register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="CRC_POLY" description="Select CRC polynomial"> + <Enum name="CRC_CCITT_POLYNOMIAL" start="0x0" description="CRC-CCITT polynomial" /> + <Enum name="CRC_16_POLYNOMIAL" start="0x1" description="CRC-16 polynomial" /> + <Enum name="CRC_32_POLYNOMIAL" start="0x2" description="CRC-32 polynomial" /> + </BitField> + <BitField start="2" size="1" name="BIT_RVS_WR" description="Select bit order for CRC_WR_DATA"> + <Enum name="NO_BIT_ORDER_REVERSE" start="0" description="No bit order reverse for CRC_WR_DATA (per byte)" /> + <Enum name="BIT_ORDER_REVERSE_FO" start="1" description="Bit order reverse for CRC_WR_DATA (per byte)" /> + </BitField> + <BitField start="3" size="1" name="CMPL_WR" description="Select one's complement for CRC_WR_DATA"> + <Enum name="NO_ONES_COMPLEMENT_" start="0" description="No one's complement for CRC_WR_DATA" /> + <Enum name="ONES_COMPLEMENT_FOR" start="1" description="One's complement for CRC_WR_DATA" /> + </BitField> + <BitField start="4" size="1" name="BIT_RVS_SUM" description="Select bit order revers for CRC_SUM"> + <Enum name="NO_BIT_ORDER_REVERSE" start="0" description="No bit order reverse for CRC_SUM" /> + <Enum name="BIT_ORDER_REVERSE_FO" start="1" description="Bit order reverse for CRC_SUM" /> + </BitField> + <BitField start="5" size="1" name="CMPL_SUM" description="Select one's complement for CRC_SUM"> + <Enum name="NO_ONES_COMPLEMENT_" start="0" description="No one's complement for CRC_SUM" /> + <Enum name="ONES_COMPLEMENT_FOR" start="1" description="One's complement for CRC_SUM" /> + </BitField> + <BitField start="6" size="26" name="Reserved" description="Always 0 when read" /> + </Register> + <Register start="+0x004" size="4" name="SEED" access="Read/Write" description="CRC seed register" reset_value="0xFFFF" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRC_SEED" description="A write access to this register will load CRC seed value to CRC_SUM register with selected bit order and 1's complement pre-processes. A write access to this register will overrule the CRC calculation in progresses." /> + </Register> + <Register start="+0x008" size="4" name="SUM" access="ReadOnly" description="CRC checksum register" reset_value="0xFFFF" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CRC_SUM" description="The most recent CRC sum can be read through this register with selected bit order and 1's complement post-processes." /> + </Register> + <Register start="+0x008" size="4" name="DATA" access="WriteOnly" description="CRC data register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="CRC_WR_DATA" description="Data written to this register will be taken to perform CRC calculation with selected bit order and 1's complement pre-process. Any write size 8, 16 or 32-bit are allowed and accept back-to-back transactions." /> + </Register> + </RegisterGroup> + <RegisterGroup name="GPIO" start="0x20098000" description="GPIO"> + <Register start="+0x000+0" size="4" name="DIR0" access="Read/Write" description="GPIO Port Direction control register." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="PDIR0" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="1" size="1" name="PDIR1" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="2" size="1" name="PDIR2" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="3" size="1" name="PDIR3" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="4" size="1" name="PDIR4" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="5" size="1" name="PDIR5" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="6" size="1" name="PDIR6" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="7" size="1" name="PDIR7" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="8" size="1" name="PDIR8" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="9" size="1" name="PDIR9" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="10" size="1" name="PDIR10" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="11" size="1" name="PDIR11" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="12" size="1" name="PDIR12" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="13" size="1" name="PDIR13" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="14" size="1" name="PDIR14" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="15" size="1" name="PDIR15" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="16" size="1" name="PDIR16" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="17" size="1" name="PDIR17" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="18" size="1" name="PDIR18" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="19" size="1" name="PDIR19" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="20" size="1" name="PDIR20" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="21" size="1" name="PDIR21" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="22" size="1" name="PDIR22" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="23" size="1" name="PDIR23" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="24" size="1" name="PDIR24" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="25" size="1" name="PDIR25" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="26" size="1" name="PDIR26" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="27" size="1" name="PDIR27" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="28" size="1" name="PDIR28" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="29" size="1" name="PDIR29" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="30" size="1" name="PDIR30" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="31" size="1" name="PDIR31" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + </Register> + <Register start="+0x000+32" size="4" name="DIR1" access="Read/Write" description="GPIO Port Direction control register." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="PDIR0" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="1" size="1" name="PDIR1" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="2" size="1" name="PDIR2" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="3" size="1" name="PDIR3" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="4" size="1" name="PDIR4" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="5" size="1" name="PDIR5" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="6" size="1" name="PDIR6" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="7" size="1" name="PDIR7" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="8" size="1" name="PDIR8" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="9" size="1" name="PDIR9" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="10" size="1" name="PDIR10" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="11" size="1" name="PDIR11" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="12" size="1" name="PDIR12" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="13" size="1" name="PDIR13" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="14" size="1" name="PDIR14" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="15" size="1" name="PDIR15" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="16" size="1" name="PDIR16" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="17" size="1" name="PDIR17" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="18" size="1" name="PDIR18" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="19" size="1" name="PDIR19" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="20" size="1" name="PDIR20" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="21" size="1" name="PDIR21" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="22" size="1" name="PDIR22" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="23" size="1" name="PDIR23" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="24" size="1" name="PDIR24" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="25" size="1" name="PDIR25" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="26" size="1" name="PDIR26" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="27" size="1" name="PDIR27" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="28" size="1" name="PDIR28" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="29" size="1" name="PDIR29" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="30" size="1" name="PDIR30" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="31" size="1" name="PDIR31" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + </Register> + <Register start="+0x000+64" size="4" name="DIR2" access="Read/Write" description="GPIO Port Direction control register." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="PDIR0" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="1" size="1" name="PDIR1" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="2" size="1" name="PDIR2" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="3" size="1" name="PDIR3" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="4" size="1" name="PDIR4" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="5" size="1" name="PDIR5" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="6" size="1" name="PDIR6" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="7" size="1" name="PDIR7" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="8" size="1" name="PDIR8" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="9" size="1" name="PDIR9" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="10" size="1" name="PDIR10" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="11" size="1" name="PDIR11" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="12" size="1" name="PDIR12" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="13" size="1" name="PDIR13" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="14" size="1" name="PDIR14" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="15" size="1" name="PDIR15" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="16" size="1" name="PDIR16" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="17" size="1" name="PDIR17" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="18" size="1" name="PDIR18" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="19" size="1" name="PDIR19" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="20" size="1" name="PDIR20" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="21" size="1" name="PDIR21" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="22" size="1" name="PDIR22" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="23" size="1" name="PDIR23" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="24" size="1" name="PDIR24" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="25" size="1" name="PDIR25" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="26" size="1" name="PDIR26" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="27" size="1" name="PDIR27" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="28" size="1" name="PDIR28" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="29" size="1" name="PDIR29" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="30" size="1" name="PDIR30" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="31" size="1" name="PDIR31" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + </Register> + <Register start="+0x000+96" size="4" name="DIR3" access="Read/Write" description="GPIO Port Direction control register." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="PDIR0" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="1" size="1" name="PDIR1" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="2" size="1" name="PDIR2" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="3" size="1" name="PDIR3" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="4" size="1" name="PDIR4" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="5" size="1" name="PDIR5" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="6" size="1" name="PDIR6" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="7" size="1" name="PDIR7" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="8" size="1" name="PDIR8" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="9" size="1" name="PDIR9" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="10" size="1" name="PDIR10" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="11" size="1" name="PDIR11" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="12" size="1" name="PDIR12" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="13" size="1" name="PDIR13" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="14" size="1" name="PDIR14" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="15" size="1" name="PDIR15" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="16" size="1" name="PDIR16" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="17" size="1" name="PDIR17" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="18" size="1" name="PDIR18" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="19" size="1" name="PDIR19" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="20" size="1" name="PDIR20" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="21" size="1" name="PDIR21" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="22" size="1" name="PDIR22" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="23" size="1" name="PDIR23" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="24" size="1" name="PDIR24" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="25" size="1" name="PDIR25" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="26" size="1" name="PDIR26" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="27" size="1" name="PDIR27" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="28" size="1" name="PDIR28" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="29" size="1" name="PDIR29" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="30" size="1" name="PDIR30" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="31" size="1" name="PDIR31" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + </Register> + <Register start="+0x000+128" size="4" name="DIR4" access="Read/Write" description="GPIO Port Direction control register." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="PDIR0" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="1" size="1" name="PDIR1" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="2" size="1" name="PDIR2" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="3" size="1" name="PDIR3" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="4" size="1" name="PDIR4" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="5" size="1" name="PDIR5" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="6" size="1" name="PDIR6" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="7" size="1" name="PDIR7" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="8" size="1" name="PDIR8" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="9" size="1" name="PDIR9" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="10" size="1" name="PDIR10" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="11" size="1" name="PDIR11" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="12" size="1" name="PDIR12" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="13" size="1" name="PDIR13" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="14" size="1" name="PDIR14" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="15" size="1" name="PDIR15" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="16" size="1" name="PDIR16" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="17" size="1" name="PDIR17" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="18" size="1" name="PDIR18" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="19" size="1" name="PDIR19" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="20" size="1" name="PDIR20" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="21" size="1" name="PDIR21" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="22" size="1" name="PDIR22" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="23" size="1" name="PDIR23" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="24" size="1" name="PDIR24" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="25" size="1" name="PDIR25" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="26" size="1" name="PDIR26" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="27" size="1" name="PDIR27" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="28" size="1" name="PDIR28" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="29" size="1" name="PDIR29" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="30" size="1" name="PDIR30" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="31" size="1" name="PDIR31" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + </Register> + <Register start="+0x000+160" size="4" name="DIR5" access="Read/Write" description="GPIO Port Direction control register." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="PDIR0" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="1" size="1" name="PDIR1" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="2" size="1" name="PDIR2" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="3" size="1" name="PDIR3" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="4" size="1" name="PDIR4" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="5" size="1" name="PDIR5" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="6" size="1" name="PDIR6" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="7" size="1" name="PDIR7" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="8" size="1" name="PDIR8" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="9" size="1" name="PDIR9" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="10" size="1" name="PDIR10" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="11" size="1" name="PDIR11" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="12" size="1" name="PDIR12" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="13" size="1" name="PDIR13" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="14" size="1" name="PDIR14" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="15" size="1" name="PDIR15" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="16" size="1" name="PDIR16" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="17" size="1" name="PDIR17" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="18" size="1" name="PDIR18" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="19" size="1" name="PDIR19" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="20" size="1" name="PDIR20" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="21" size="1" name="PDIR21" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="22" size="1" name="PDIR22" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="23" size="1" name="PDIR23" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="24" size="1" name="PDIR24" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="25" size="1" name="PDIR25" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="26" size="1" name="PDIR26" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="27" size="1" name="PDIR27" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="28" size="1" name="PDIR28" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="29" size="1" name="PDIR29" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="30" size="1" name="PDIR30" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="31" size="1" name="PDIR31" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + </Register> + <Register start="+0x010+0" size="4" name="MASK0" access="Read/Write" description="Mask register for Port." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="PMASK0" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="1" size="1" name="PMASK1" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="2" size="1" name="PMASK2" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="3" size="1" name="PMASK3" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="4" size="1" name="PMASK4" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="5" size="1" name="PMASK5" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="6" size="1" name="PMASK6" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="7" size="1" name="PMASK7" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="8" size="1" name="PMASK8" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="9" size="1" name="PMASK9" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="10" size="1" name="PMASK10" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="11" size="1" name="PMASK11" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="12" size="1" name="PMASK12" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="13" size="1" name="PMASK13" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="14" size="1" name="PMASK14" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="15" size="1" name="PMASK15" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="16" size="1" name="PMASK16" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="17" size="1" name="PMASK17" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="18" size="1" name="PMASK18" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="19" size="1" name="PMASK19" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="20" size="1" name="PMASK20" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="21" size="1" name="PMASK21" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="22" size="1" name="PMASK22" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="23" size="1" name="PMASK23" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="24" size="1" name="PMASK24" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="25" size="1" name="PMASK25" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="26" size="1" name="PMASK26" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="27" size="1" name="PMASK27" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="28" size="1" name="PMASK28" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="29" size="1" name="PMASK29" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="30" size="1" name="PMASK30" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="31" size="1" name="PMASK31" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." /> + </Register> + <Register start="+0x010+32" size="4" name="MASK1" access="Read/Write" description="Mask register for Port." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="PMASK0" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="1" size="1" name="PMASK1" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="2" size="1" name="PMASK2" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="3" size="1" name="PMASK3" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="4" size="1" name="PMASK4" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="5" size="1" name="PMASK5" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="6" size="1" name="PMASK6" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="7" size="1" name="PMASK7" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="8" size="1" name="PMASK8" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="9" size="1" name="PMASK9" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="10" size="1" name="PMASK10" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="11" size="1" name="PMASK11" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="12" size="1" name="PMASK12" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="13" size="1" name="PMASK13" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="14" size="1" name="PMASK14" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="15" size="1" name="PMASK15" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="16" size="1" name="PMASK16" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="17" size="1" name="PMASK17" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="18" size="1" name="PMASK18" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="19" size="1" name="PMASK19" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="20" size="1" name="PMASK20" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="21" size="1" name="PMASK21" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="22" size="1" name="PMASK22" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="23" size="1" name="PMASK23" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="24" size="1" name="PMASK24" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="25" size="1" name="PMASK25" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="26" size="1" name="PMASK26" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="27" size="1" name="PMASK27" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="28" size="1" name="PMASK28" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="29" size="1" name="PMASK29" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="30" size="1" name="PMASK30" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="31" size="1" name="PMASK31" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." /> + </Register> + <Register start="+0x010+64" size="4" name="MASK2" access="Read/Write" description="Mask register for Port." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="PMASK0" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="1" size="1" name="PMASK1" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="2" size="1" name="PMASK2" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="3" size="1" name="PMASK3" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="4" size="1" name="PMASK4" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="5" size="1" name="PMASK5" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="6" size="1" name="PMASK6" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="7" size="1" name="PMASK7" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="8" size="1" name="PMASK8" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="9" size="1" name="PMASK9" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="10" size="1" name="PMASK10" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="11" size="1" name="PMASK11" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="12" size="1" name="PMASK12" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="13" size="1" name="PMASK13" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="14" size="1" name="PMASK14" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="15" size="1" name="PMASK15" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="16" size="1" name="PMASK16" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="17" size="1" name="PMASK17" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="18" size="1" name="PMASK18" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="19" size="1" name="PMASK19" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="20" size="1" name="PMASK20" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="21" size="1" name="PMASK21" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="22" size="1" name="PMASK22" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="23" size="1" name="PMASK23" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="24" size="1" name="PMASK24" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="25" size="1" name="PMASK25" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="26" size="1" name="PMASK26" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="27" size="1" name="PMASK27" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="28" size="1" name="PMASK28" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="29" size="1" name="PMASK29" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="30" size="1" name="PMASK30" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="31" size="1" name="PMASK31" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." /> + </Register> + <Register start="+0x010+96" size="4" name="MASK3" access="Read/Write" description="Mask register for Port." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="PMASK0" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="1" size="1" name="PMASK1" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="2" size="1" name="PMASK2" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="3" size="1" name="PMASK3" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="4" size="1" name="PMASK4" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="5" size="1" name="PMASK5" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="6" size="1" name="PMASK6" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="7" size="1" name="PMASK7" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="8" size="1" name="PMASK8" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="9" size="1" name="PMASK9" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="10" size="1" name="PMASK10" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="11" size="1" name="PMASK11" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="12" size="1" name="PMASK12" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="13" size="1" name="PMASK13" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="14" size="1" name="PMASK14" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="15" size="1" name="PMASK15" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="16" size="1" name="PMASK16" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="17" size="1" name="PMASK17" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="18" size="1" name="PMASK18" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="19" size="1" name="PMASK19" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="20" size="1" name="PMASK20" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="21" size="1" name="PMASK21" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="22" size="1" name="PMASK22" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="23" size="1" name="PMASK23" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="24" size="1" name="PMASK24" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="25" size="1" name="PMASK25" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="26" size="1" name="PMASK26" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="27" size="1" name="PMASK27" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="28" size="1" name="PMASK28" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="29" size="1" name="PMASK29" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="30" size="1" name="PMASK30" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="31" size="1" name="PMASK31" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." /> + </Register> + <Register start="+0x010+128" size="4" name="MASK4" access="Read/Write" description="Mask register for Port." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="PMASK0" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="1" size="1" name="PMASK1" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="2" size="1" name="PMASK2" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="3" size="1" name="PMASK3" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="4" size="1" name="PMASK4" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="5" size="1" name="PMASK5" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="6" size="1" name="PMASK6" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="7" size="1" name="PMASK7" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="8" size="1" name="PMASK8" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="9" size="1" name="PMASK9" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="10" size="1" name="PMASK10" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="11" size="1" name="PMASK11" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="12" size="1" name="PMASK12" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="13" size="1" name="PMASK13" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="14" size="1" name="PMASK14" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="15" size="1" name="PMASK15" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="16" size="1" name="PMASK16" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="17" size="1" name="PMASK17" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="18" size="1" name="PMASK18" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="19" size="1" name="PMASK19" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="20" size="1" name="PMASK20" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="21" size="1" name="PMASK21" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="22" size="1" name="PMASK22" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="23" size="1" name="PMASK23" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="24" size="1" name="PMASK24" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="25" size="1" name="PMASK25" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="26" size="1" name="PMASK26" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="27" size="1" name="PMASK27" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="28" size="1" name="PMASK28" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="29" size="1" name="PMASK29" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="30" size="1" name="PMASK30" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="31" size="1" name="PMASK31" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." /> + </Register> + <Register start="+0x010+160" size="4" name="MASK5" access="Read/Write" description="Mask register for Port." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="PMASK0" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="1" size="1" name="PMASK1" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="2" size="1" name="PMASK2" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="3" size="1" name="PMASK3" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="4" size="1" name="PMASK4" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="5" size="1" name="PMASK5" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="6" size="1" name="PMASK6" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="7" size="1" name="PMASK7" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="8" size="1" name="PMASK8" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="9" size="1" name="PMASK9" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="10" size="1" name="PMASK10" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="11" size="1" name="PMASK11" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="12" size="1" name="PMASK12" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="13" size="1" name="PMASK13" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="14" size="1" name="PMASK14" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="15" size="1" name="PMASK15" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="16" size="1" name="PMASK16" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="17" size="1" name="PMASK17" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="18" size="1" name="PMASK18" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="19" size="1" name="PMASK19" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="20" size="1" name="PMASK20" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="21" size="1" name="PMASK21" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="22" size="1" name="PMASK22" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="23" size="1" name="PMASK23" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="24" size="1" name="PMASK24" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="25" size="1" name="PMASK25" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="26" size="1" name="PMASK26" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="27" size="1" name="PMASK27" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="28" size="1" name="PMASK28" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="29" size="1" name="PMASK29" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="30" size="1" name="PMASK30" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="31" size="1" name="PMASK31" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." /> + </Register> + <Register start="+0x014+0" size="4" name="PIN0" access="Read/Write" description="Port Pin value register using MASK." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="VAL0" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="1" size="1" name="VAL1" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="2" size="1" name="VAL2" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="3" size="1" name="VAL3" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="4" size="1" name="VAL4" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="5" size="1" name="VAL5" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="6" size="1" name="VAL6" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="7" size="1" name="VAL7" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="8" size="1" name="VAL8" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="9" size="1" name="VAL9" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="10" size="1" name="VAL10" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="11" size="1" name="VAL11" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="12" size="1" name="VAL12" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="13" size="1" name="VAL13" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="14" size="1" name="VAL14" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="15" size="1" name="VAL15" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="16" size="1" name="VAL16" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="17" size="1" name="VAL17" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="18" size="1" name="VAL18" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="19" size="1" name="VAL19" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="20" size="1" name="VAL20" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="21" size="1" name="VAL21" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="22" size="1" name="VAL22" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="23" size="1" name="VAL23" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="24" size="1" name="VAL24" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="25" size="1" name="VAL25" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="26" size="1" name="VAL26" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="27" size="1" name="VAL27" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="28" size="1" name="VAL28" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="29" size="1" name="VAL29" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="30" size="1" name="VAL30" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="31" size="1" name="VAL31" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + </Register> + <Register start="+0x014+32" size="4" name="PIN1" access="Read/Write" description="Port Pin value register using MASK." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="VAL0" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="1" size="1" name="VAL1" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="2" size="1" name="VAL2" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="3" size="1" name="VAL3" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="4" size="1" name="VAL4" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="5" size="1" name="VAL5" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="6" size="1" name="VAL6" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="7" size="1" name="VAL7" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="8" size="1" name="VAL8" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="9" size="1" name="VAL9" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="10" size="1" name="VAL10" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="11" size="1" name="VAL11" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="12" size="1" name="VAL12" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="13" size="1" name="VAL13" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="14" size="1" name="VAL14" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="15" size="1" name="VAL15" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="16" size="1" name="VAL16" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="17" size="1" name="VAL17" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="18" size="1" name="VAL18" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="19" size="1" name="VAL19" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="20" size="1" name="VAL20" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="21" size="1" name="VAL21" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="22" size="1" name="VAL22" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="23" size="1" name="VAL23" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="24" size="1" name="VAL24" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="25" size="1" name="VAL25" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="26" size="1" name="VAL26" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="27" size="1" name="VAL27" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="28" size="1" name="VAL28" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="29" size="1" name="VAL29" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="30" size="1" name="VAL30" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="31" size="1" name="VAL31" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + </Register> + <Register start="+0x014+64" size="4" name="PIN2" access="Read/Write" description="Port Pin value register using MASK." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="VAL0" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="1" size="1" name="VAL1" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="2" size="1" name="VAL2" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="3" size="1" name="VAL3" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="4" size="1" name="VAL4" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="5" size="1" name="VAL5" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="6" size="1" name="VAL6" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="7" size="1" name="VAL7" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="8" size="1" name="VAL8" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="9" size="1" name="VAL9" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="10" size="1" name="VAL10" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="11" size="1" name="VAL11" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="12" size="1" name="VAL12" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="13" size="1" name="VAL13" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="14" size="1" name="VAL14" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="15" size="1" name="VAL15" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="16" size="1" name="VAL16" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="17" size="1" name="VAL17" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="18" size="1" name="VAL18" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="19" size="1" name="VAL19" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="20" size="1" name="VAL20" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="21" size="1" name="VAL21" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="22" size="1" name="VAL22" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="23" size="1" name="VAL23" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="24" size="1" name="VAL24" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="25" size="1" name="VAL25" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="26" size="1" name="VAL26" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="27" size="1" name="VAL27" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="28" size="1" name="VAL28" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="29" size="1" name="VAL29" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="30" size="1" name="VAL30" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="31" size="1" name="VAL31" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + </Register> + <Register start="+0x014+96" size="4" name="PIN3" access="Read/Write" description="Port Pin value register using MASK." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="VAL0" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="1" size="1" name="VAL1" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="2" size="1" name="VAL2" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="3" size="1" name="VAL3" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="4" size="1" name="VAL4" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="5" size="1" name="VAL5" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="6" size="1" name="VAL6" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="7" size="1" name="VAL7" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="8" size="1" name="VAL8" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="9" size="1" name="VAL9" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="10" size="1" name="VAL10" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="11" size="1" name="VAL11" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="12" size="1" name="VAL12" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="13" size="1" name="VAL13" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="14" size="1" name="VAL14" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="15" size="1" name="VAL15" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="16" size="1" name="VAL16" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="17" size="1" name="VAL17" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="18" size="1" name="VAL18" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="19" size="1" name="VAL19" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="20" size="1" name="VAL20" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="21" size="1" name="VAL21" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="22" size="1" name="VAL22" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="23" size="1" name="VAL23" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="24" size="1" name="VAL24" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="25" size="1" name="VAL25" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="26" size="1" name="VAL26" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="27" size="1" name="VAL27" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="28" size="1" name="VAL28" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="29" size="1" name="VAL29" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="30" size="1" name="VAL30" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="31" size="1" name="VAL31" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + </Register> + <Register start="+0x014+128" size="4" name="PIN4" access="Read/Write" description="Port Pin value register using MASK." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="VAL0" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="1" size="1" name="VAL1" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="2" size="1" name="VAL2" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="3" size="1" name="VAL3" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="4" size="1" name="VAL4" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="5" size="1" name="VAL5" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="6" size="1" name="VAL6" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="7" size="1" name="VAL7" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="8" size="1" name="VAL8" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="9" size="1" name="VAL9" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="10" size="1" name="VAL10" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="11" size="1" name="VAL11" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="12" size="1" name="VAL12" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="13" size="1" name="VAL13" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="14" size="1" name="VAL14" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="15" size="1" name="VAL15" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="16" size="1" name="VAL16" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="17" size="1" name="VAL17" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="18" size="1" name="VAL18" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="19" size="1" name="VAL19" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="20" size="1" name="VAL20" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="21" size="1" name="VAL21" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="22" size="1" name="VAL22" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="23" size="1" name="VAL23" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="24" size="1" name="VAL24" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="25" size="1" name="VAL25" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="26" size="1" name="VAL26" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="27" size="1" name="VAL27" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="28" size="1" name="VAL28" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="29" size="1" name="VAL29" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="30" size="1" name="VAL30" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="31" size="1" name="VAL31" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + </Register> + <Register start="+0x014+160" size="4" name="PIN5" access="Read/Write" description="Port Pin value register using MASK." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="VAL0" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="1" size="1" name="VAL1" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="2" size="1" name="VAL2" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="3" size="1" name="VAL3" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="4" size="1" name="VAL4" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="5" size="1" name="VAL5" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="6" size="1" name="VAL6" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="7" size="1" name="VAL7" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="8" size="1" name="VAL8" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="9" size="1" name="VAL9" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="10" size="1" name="VAL10" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="11" size="1" name="VAL11" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="12" size="1" name="VAL12" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="13" size="1" name="VAL13" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="14" size="1" name="VAL14" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="15" size="1" name="VAL15" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="16" size="1" name="VAL16" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="17" size="1" name="VAL17" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="18" size="1" name="VAL18" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="19" size="1" name="VAL19" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="20" size="1" name="VAL20" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="21" size="1" name="VAL21" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="22" size="1" name="VAL22" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="23" size="1" name="VAL23" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="24" size="1" name="VAL24" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="25" size="1" name="VAL25" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="26" size="1" name="VAL26" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="27" size="1" name="VAL27" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="28" size="1" name="VAL28" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="29" size="1" name="VAL29" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="30" size="1" name="VAL30" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="31" size="1" name="VAL31" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + </Register> + <Register start="+0x018+0" size="4" name="SET0" access="Read/Write" description="Port Output Set register using MASK." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="PSET0" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="1" size="1" name="PSET1" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="2" size="1" name="PSET2" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="3" size="1" name="PSET3" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="4" size="1" name="PSET4" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="5" size="1" name="PSET5" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="6" size="1" name="PSET6" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="7" size="1" name="PSET7" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="8" size="1" name="PSET8" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="9" size="1" name="PSET9" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="10" size="1" name="PSET10" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="11" size="1" name="PSET11" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="12" size="1" name="PSET12" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="13" size="1" name="PSET13" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="14" size="1" name="PSET14" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="15" size="1" name="PSET15" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="16" size="1" name="PSET16" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="17" size="1" name="PSET17" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="18" size="1" name="PSET18" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="19" size="1" name="PSET19" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="20" size="1" name="PSET20" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="21" size="1" name="PSET21" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="22" size="1" name="PSET22" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="23" size="1" name="PSET23" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="24" size="1" name="PSET24" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="25" size="1" name="PSET25" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="26" size="1" name="PSET26" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="27" size="1" name="PSET27" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="28" size="1" name="PSET28" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="29" size="1" name="PSET29" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="30" size="1" name="PSET30" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="31" size="1" name="PSET31" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + </Register> + <Register start="+0x018+32" size="4" name="SET1" access="Read/Write" description="Port Output Set register using MASK." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="PSET0" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="1" size="1" name="PSET1" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="2" size="1" name="PSET2" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="3" size="1" name="PSET3" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="4" size="1" name="PSET4" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="5" size="1" name="PSET5" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="6" size="1" name="PSET6" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="7" size="1" name="PSET7" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="8" size="1" name="PSET8" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="9" size="1" name="PSET9" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="10" size="1" name="PSET10" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="11" size="1" name="PSET11" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="12" size="1" name="PSET12" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="13" size="1" name="PSET13" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="14" size="1" name="PSET14" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="15" size="1" name="PSET15" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="16" size="1" name="PSET16" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="17" size="1" name="PSET17" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="18" size="1" name="PSET18" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="19" size="1" name="PSET19" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="20" size="1" name="PSET20" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="21" size="1" name="PSET21" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="22" size="1" name="PSET22" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="23" size="1" name="PSET23" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="24" size="1" name="PSET24" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="25" size="1" name="PSET25" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="26" size="1" name="PSET26" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="27" size="1" name="PSET27" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="28" size="1" name="PSET28" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="29" size="1" name="PSET29" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="30" size="1" name="PSET30" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="31" size="1" name="PSET31" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + </Register> + <Register start="+0x018+64" size="4" name="SET2" access="Read/Write" description="Port Output Set register using MASK." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="PSET0" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="1" size="1" name="PSET1" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="2" size="1" name="PSET2" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="3" size="1" name="PSET3" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="4" size="1" name="PSET4" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="5" size="1" name="PSET5" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="6" size="1" name="PSET6" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="7" size="1" name="PSET7" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="8" size="1" name="PSET8" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="9" size="1" name="PSET9" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="10" size="1" name="PSET10" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="11" size="1" name="PSET11" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="12" size="1" name="PSET12" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="13" size="1" name="PSET13" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="14" size="1" name="PSET14" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="15" size="1" name="PSET15" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="16" size="1" name="PSET16" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="17" size="1" name="PSET17" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="18" size="1" name="PSET18" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="19" size="1" name="PSET19" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="20" size="1" name="PSET20" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="21" size="1" name="PSET21" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="22" size="1" name="PSET22" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="23" size="1" name="PSET23" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="24" size="1" name="PSET24" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="25" size="1" name="PSET25" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="26" size="1" name="PSET26" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="27" size="1" name="PSET27" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="28" size="1" name="PSET28" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="29" size="1" name="PSET29" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="30" size="1" name="PSET30" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="31" size="1" name="PSET31" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + </Register> + <Register start="+0x018+96" size="4" name="SET3" access="Read/Write" description="Port Output Set register using MASK." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="PSET0" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="1" size="1" name="PSET1" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="2" size="1" name="PSET2" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="3" size="1" name="PSET3" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="4" size="1" name="PSET4" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="5" size="1" name="PSET5" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="6" size="1" name="PSET6" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="7" size="1" name="PSET7" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="8" size="1" name="PSET8" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="9" size="1" name="PSET9" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="10" size="1" name="PSET10" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="11" size="1" name="PSET11" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="12" size="1" name="PSET12" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="13" size="1" name="PSET13" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="14" size="1" name="PSET14" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="15" size="1" name="PSET15" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="16" size="1" name="PSET16" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="17" size="1" name="PSET17" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="18" size="1" name="PSET18" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="19" size="1" name="PSET19" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="20" size="1" name="PSET20" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="21" size="1" name="PSET21" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="22" size="1" name="PSET22" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="23" size="1" name="PSET23" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="24" size="1" name="PSET24" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="25" size="1" name="PSET25" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="26" size="1" name="PSET26" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="27" size="1" name="PSET27" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="28" size="1" name="PSET28" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="29" size="1" name="PSET29" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="30" size="1" name="PSET30" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="31" size="1" name="PSET31" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + </Register> + <Register start="+0x018+128" size="4" name="SET4" access="Read/Write" description="Port Output Set register using MASK." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="PSET0" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="1" size="1" name="PSET1" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="2" size="1" name="PSET2" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="3" size="1" name="PSET3" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="4" size="1" name="PSET4" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="5" size="1" name="PSET5" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="6" size="1" name="PSET6" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="7" size="1" name="PSET7" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="8" size="1" name="PSET8" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="9" size="1" name="PSET9" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="10" size="1" name="PSET10" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="11" size="1" name="PSET11" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="12" size="1" name="PSET12" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="13" size="1" name="PSET13" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="14" size="1" name="PSET14" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="15" size="1" name="PSET15" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="16" size="1" name="PSET16" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="17" size="1" name="PSET17" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="18" size="1" name="PSET18" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="19" size="1" name="PSET19" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="20" size="1" name="PSET20" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="21" size="1" name="PSET21" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="22" size="1" name="PSET22" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="23" size="1" name="PSET23" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="24" size="1" name="PSET24" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="25" size="1" name="PSET25" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="26" size="1" name="PSET26" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="27" size="1" name="PSET27" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="28" size="1" name="PSET28" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="29" size="1" name="PSET29" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="30" size="1" name="PSET30" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="31" size="1" name="PSET31" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + </Register> + <Register start="+0x018+160" size="4" name="SET5" access="Read/Write" description="Port Output Set register using MASK." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="PSET0" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="1" size="1" name="PSET1" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="2" size="1" name="PSET2" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="3" size="1" name="PSET3" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="4" size="1" name="PSET4" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="5" size="1" name="PSET5" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="6" size="1" name="PSET6" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="7" size="1" name="PSET7" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="8" size="1" name="PSET8" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="9" size="1" name="PSET9" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="10" size="1" name="PSET10" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="11" size="1" name="PSET11" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="12" size="1" name="PSET12" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="13" size="1" name="PSET13" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="14" size="1" name="PSET14" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="15" size="1" name="PSET15" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="16" size="1" name="PSET16" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="17" size="1" name="PSET17" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="18" size="1" name="PSET18" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="19" size="1" name="PSET19" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="20" size="1" name="PSET20" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="21" size="1" name="PSET21" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="22" size="1" name="PSET22" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="23" size="1" name="PSET23" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="24" size="1" name="PSET24" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="25" size="1" name="PSET25" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="26" size="1" name="PSET26" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="27" size="1" name="PSET27" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="28" size="1" name="PSET28" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="29" size="1" name="PSET29" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="30" size="1" name="PSET30" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="31" size="1" name="PSET31" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + </Register> + <Register start="+0x01C+0" size="4" name="CLR0" access="WriteOnly" description="Port Output Clear register using MASK." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="PCLR0" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="1" size="1" name="PCLR1" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="2" size="1" name="PCLR2" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="3" size="1" name="PCLR3" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="4" size="1" name="PCLR4" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="5" size="1" name="PCLR5" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="6" size="1" name="PCLR6" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="7" size="1" name="PCLR7" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="8" size="1" name="PCLR8" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="9" size="1" name="PCLR9" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="10" size="1" name="PCLR10" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="11" size="1" name="PCLR11" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="12" size="1" name="PCLR12" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="13" size="1" name="PCLR13" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="14" size="1" name="PCLR14" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="15" size="1" name="PCLR15" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="16" size="1" name="PCLR16" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="17" size="1" name="PCLR17" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="18" size="1" name="PCLR18" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="19" size="1" name="PCLR19" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="20" size="1" name="PCLR20" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="21" size="1" name="PCLR21" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="22" size="1" name="PCLR22" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="23" size="1" name="PCLR23" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="24" size="1" name="PCLR24" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="25" size="1" name="PCLR25" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="26" size="1" name="PCLR26" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="27" size="1" name="PCLR27" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="28" size="1" name="PCLR28" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="29" size="1" name="PCLR29" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="30" size="1" name="PCLR30" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="31" size="1" name="PCLR31" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + </Register> + <Register start="+0x01C+32" size="4" name="CLR1" access="WriteOnly" description="Port Output Clear register using MASK." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="PCLR0" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="1" size="1" name="PCLR1" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="2" size="1" name="PCLR2" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="3" size="1" name="PCLR3" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="4" size="1" name="PCLR4" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="5" size="1" name="PCLR5" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="6" size="1" name="PCLR6" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="7" size="1" name="PCLR7" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="8" size="1" name="PCLR8" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="9" size="1" name="PCLR9" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="10" size="1" name="PCLR10" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="11" size="1" name="PCLR11" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="12" size="1" name="PCLR12" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="13" size="1" name="PCLR13" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="14" size="1" name="PCLR14" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="15" size="1" name="PCLR15" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="16" size="1" name="PCLR16" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="17" size="1" name="PCLR17" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="18" size="1" name="PCLR18" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="19" size="1" name="PCLR19" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="20" size="1" name="PCLR20" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="21" size="1" name="PCLR21" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="22" size="1" name="PCLR22" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="23" size="1" name="PCLR23" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="24" size="1" name="PCLR24" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="25" size="1" name="PCLR25" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="26" size="1" name="PCLR26" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="27" size="1" name="PCLR27" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="28" size="1" name="PCLR28" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="29" size="1" name="PCLR29" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="30" size="1" name="PCLR30" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="31" size="1" name="PCLR31" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + </Register> + <Register start="+0x01C+64" size="4" name="CLR2" access="WriteOnly" description="Port Output Clear register using MASK." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="PCLR0" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="1" size="1" name="PCLR1" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="2" size="1" name="PCLR2" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="3" size="1" name="PCLR3" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="4" size="1" name="PCLR4" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="5" size="1" name="PCLR5" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="6" size="1" name="PCLR6" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="7" size="1" name="PCLR7" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="8" size="1" name="PCLR8" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="9" size="1" name="PCLR9" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="10" size="1" name="PCLR10" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="11" size="1" name="PCLR11" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="12" size="1" name="PCLR12" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="13" size="1" name="PCLR13" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="14" size="1" name="PCLR14" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="15" size="1" name="PCLR15" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="16" size="1" name="PCLR16" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="17" size="1" name="PCLR17" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="18" size="1" name="PCLR18" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="19" size="1" name="PCLR19" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="20" size="1" name="PCLR20" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="21" size="1" name="PCLR21" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="22" size="1" name="PCLR22" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="23" size="1" name="PCLR23" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="24" size="1" name="PCLR24" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="25" size="1" name="PCLR25" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="26" size="1" name="PCLR26" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="27" size="1" name="PCLR27" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="28" size="1" name="PCLR28" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="29" size="1" name="PCLR29" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="30" size="1" name="PCLR30" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="31" size="1" name="PCLR31" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + </Register> + <Register start="+0x01C+96" size="4" name="CLR3" access="WriteOnly" description="Port Output Clear register using MASK." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="PCLR0" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="1" size="1" name="PCLR1" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="2" size="1" name="PCLR2" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="3" size="1" name="PCLR3" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="4" size="1" name="PCLR4" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="5" size="1" name="PCLR5" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="6" size="1" name="PCLR6" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="7" size="1" name="PCLR7" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="8" size="1" name="PCLR8" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="9" size="1" name="PCLR9" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="10" size="1" name="PCLR10" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="11" size="1" name="PCLR11" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="12" size="1" name="PCLR12" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="13" size="1" name="PCLR13" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="14" size="1" name="PCLR14" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="15" size="1" name="PCLR15" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="16" size="1" name="PCLR16" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="17" size="1" name="PCLR17" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="18" size="1" name="PCLR18" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="19" size="1" name="PCLR19" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="20" size="1" name="PCLR20" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="21" size="1" name="PCLR21" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="22" size="1" name="PCLR22" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="23" size="1" name="PCLR23" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="24" size="1" name="PCLR24" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="25" size="1" name="PCLR25" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="26" size="1" name="PCLR26" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="27" size="1" name="PCLR27" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="28" size="1" name="PCLR28" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="29" size="1" name="PCLR29" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="30" size="1" name="PCLR30" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="31" size="1" name="PCLR31" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + </Register> + <Register start="+0x01C+128" size="4" name="CLR4" access="WriteOnly" description="Port Output Clear register using MASK." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="PCLR0" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="1" size="1" name="PCLR1" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="2" size="1" name="PCLR2" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="3" size="1" name="PCLR3" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="4" size="1" name="PCLR4" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="5" size="1" name="PCLR5" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="6" size="1" name="PCLR6" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="7" size="1" name="PCLR7" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="8" size="1" name="PCLR8" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="9" size="1" name="PCLR9" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="10" size="1" name="PCLR10" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="11" size="1" name="PCLR11" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="12" size="1" name="PCLR12" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="13" size="1" name="PCLR13" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="14" size="1" name="PCLR14" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="15" size="1" name="PCLR15" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="16" size="1" name="PCLR16" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="17" size="1" name="PCLR17" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="18" size="1" name="PCLR18" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="19" size="1" name="PCLR19" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="20" size="1" name="PCLR20" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="21" size="1" name="PCLR21" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="22" size="1" name="PCLR22" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="23" size="1" name="PCLR23" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="24" size="1" name="PCLR24" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="25" size="1" name="PCLR25" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="26" size="1" name="PCLR26" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="27" size="1" name="PCLR27" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="28" size="1" name="PCLR28" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="29" size="1" name="PCLR29" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="30" size="1" name="PCLR30" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="31" size="1" name="PCLR31" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + </Register> + <Register start="+0x01C+160" size="4" name="CLR5" access="WriteOnly" description="Port Output Clear register using MASK." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="PCLR0" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="1" size="1" name="PCLR1" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="2" size="1" name="PCLR2" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="3" size="1" name="PCLR3" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="4" size="1" name="PCLR4" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="5" size="1" name="PCLR5" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="6" size="1" name="PCLR6" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="7" size="1" name="PCLR7" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="8" size="1" name="PCLR8" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="9" size="1" name="PCLR9" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="10" size="1" name="PCLR10" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="11" size="1" name="PCLR11" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="12" size="1" name="PCLR12" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="13" size="1" name="PCLR13" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="14" size="1" name="PCLR14" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="15" size="1" name="PCLR15" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="16" size="1" name="PCLR16" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="17" size="1" name="PCLR17" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="18" size="1" name="PCLR18" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="19" size="1" name="PCLR19" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="20" size="1" name="PCLR20" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="21" size="1" name="PCLR21" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="22" size="1" name="PCLR22" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="23" size="1" name="PCLR23" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="24" size="1" name="PCLR24" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="25" size="1" name="PCLR25" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="26" size="1" name="PCLR26" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="27" size="1" name="PCLR27" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="28" size="1" name="PCLR28" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="29" size="1" name="PCLR29" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="30" size="1" name="PCLR30" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="31" size="1" name="PCLR31" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + </Register> + </RegisterGroup> + <RegisterGroup name="EMC" start="0x2009C000" description="External Memory Controller (EMC)"> + <Register start="+0x000" size="4" name="CONTROL" access="Read/Write" description="Controls operation of the memory controller." reset_value="0x3" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="E" description="EMC Enable. Indicates if the EMC is enabled or disabled:"> + <Enum name="DISABLED" start="0" description="Disabled" /> + <Enum name="ENABLED" start="1" description="Enabled
(POR and warm reset value)." /> + </BitField> + <BitField start="1" size="1" name="M" description="Address mirror. Indicates normal or reset memory map:"> + <Enum name="NORMAL" start="0" description="Normal memory map." /> + <Enum name="RESET" start="1" description="Reset memory map. Static memory EMC_CS1 is
mirrored onto EMC_CS0 and EMC_DYCS0 (POR reset value)." /> + </BitField> + <BitField start="2" size="1" name="L" description="Low-power mode. Indicates normal, or low-power mode:"> + <Enum name="WARMRESET" start="0" description="Normal mode (warm
reset value)." /> + <Enum name="LOWPOWER" start="1" description="Low-power
mode. Entering low-power mode reduces memory controller power consumption.
Dynamic memory is refreshed as necessary. The memory controller
returns to normal functional mode by clearing the low-power mode
bit (L), or by POR. This bit must only be modified when the EMC
is in idle state.[1]" /> + </BitField> + <BitField start="3" size="29" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x004" size="4" name="STATUS" access="ReadOnly" description="Provides EMC status information." reset_value="0x5" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="B" description="Busy. This bit is used to ensure that the memory controller enters the low-power or disabled mode cleanly by determining if the memory controller is busy or not."> + <Enum name="IDLE" start="0" description="EMC
is idle (warm reset value)." /> + <Enum name="BUSY" start="1" description="EMC
is busy performing memory transactions, commands, auto-refresh cycles,
or is in self-refresh mode (POR reset value)." /> + </BitField> + <BitField start="1" size="1" name="S" description="Write buffer status.This bit enables the EMC to enter low-power mode or disabled mode cleanly."> + <Enum name="EMPTY" start="0" description="Write buffers
empty (POR reset value)" /> + <Enum name="DATA" start="1" description="Write
buffers contain data." /> + </BitField> + <BitField start="2" size="1" name="SA" description="Self-refresh acknowledge. This bit indicates the operating mode of the EMC."> + <Enum name="NORMAL" start="0" description="Normal mode" /> + <Enum name="SELFREFRESH" start="1" description="Self-refresh mode (POR reset value)." /> + </BitField> + <BitField start="3" size="29" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x008" size="4" name="CONFIG" access="Read/Write" description="Configures operation of the memory controller" reset_value="0x0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="EM" description="Endian mode. On power-on reset, the value of the endian bit is 0. All data must be flushed in the EMC before switching between little-endian and big-endian modes."> + <Enum name="LITTLEENDIAN" start="0" description="Little-endian
mode (POR reset value)." /> + <Enum name="BIGENDIAN" start="1" description="Big-endian
mode." /> + </BitField> + <BitField start="1" size="7" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="8" size="1" name="CLKR" description="CCLK: CLKOUT ratio. This bit must contain 0 for proper operation of the EMC."> + <Enum name="PORRESET" start="0" description="1:1(POR reset value)" /> + <Enum name="DONOTUSE" start="1" description="1:2 (this option is not available on the LPC178x/177x)" /> + </BitField> + <BitField start="9" size="23" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x020" size="4" name="DYNAMICCONTROL" access="Read/Write" description="Controls dynamic memory operation." reset_value="0x006" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="CE" description="Dynamic memory clock enable."> + <Enum name="POWERSAVE" start="0" description="Clock enable of idle devices are deasserted to save power (POR reset value)." /> + <Enum name="HIGH" start="1" description="All clock enables are driven HIGH continuously.[1]" /> + </BitField> + <BitField start="1" size="1" name="CS" description="Dynamic memory clock control. When clock control is LOW the output clock CLKOUT is stopped when there are no SDRAM transactions. The clock is also stopped during self-refresh mode."> + <Enum name="STOP" start="0" description="CLKOUT stops when all SDRAMs are idle and during self-refresh mode." /> + <Enum name="RUN" start="1" description="CLKOUT runs continuously (POR reset value)." /> + </BitField> + <BitField start="2" size="1" name="SR" description="Self-refresh request, EMCSREFREQ. By writing 1 to this bit self-refresh can be entered under software control. Writing 0 to this bit returns the EMC to normal mode. The self-refresh acknowledge bit in the Status register must be polled to discover the current operating mode of the EMC.[2]"> + <Enum name="NORMAL_MODE_" start="0" description="Normal mode." /> + <Enum name="ENTER_SELF_REFRESH_M" start="1" description="Enter self-refresh mode (POR reset value)." /> + </BitField> + <BitField start="3" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + <BitField start="5" size="1" name="MMC" description="Memory clock control."> + <Enum name="CLKOUT_ENABLED_POR_" start="0" description="CLKOUT enabled (POR reset value)." /> + <Enum name="CLKOUT_DISABLED" start="1" description="CLKOUT disabled.[3]" /> + </BitField> + <BitField start="6" size="1" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + <BitField start="7" size="2" name="I" description="SDRAM initialization."> + <Enum name="NORMAL" start="0x0" description="Issue SDRAM NORMAL operation command (POR reset value)." /> + <Enum name="MODE" start="0x1" description="Issue SDRAM MODE command." /> + <Enum name="PALL" start="0x2" description="Issue SDRAM PALL (precharge all) command." /> + <Enum name="NOP" start="0x3" description="Issue SDRAM NOP (no operation) command)" /> + </BitField> + <BitField start="9" size="5" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + <BitField start="14" size="18" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x024" size="4" name="DYNAMICREFRESH" access="Read/Write" description="Configures dynamic memory refresh." reset_value="0x0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="11" name="REFRESH" description="Refresh timer. Indicates the multiple of 16 CCLKs between SDRAM refresh cycles. 0x0 = Refresh disabled (POR reset value). 0x1 - 0x7FF = n x16 = 16n CCLKs between SDRAM refresh cycles. For example: 0x1 = 1 x 16 = 16 CCLKs between SDRAM refresh cycles. 0x8 = 8 x 16 = 128 CCLKs between SDRAM refresh cycles" /> + <BitField start="11" size="21" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x028" size="4" name="DYNAMICREADCONFIG" access="Read/Write" description="Configures dynamic memory read strategy." reset_value="0x0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="RD" description="Read data strategy"> + <Enum name="CLOCK_OUT_DELAYED_ST" start="0x0" description="Clock out delayed strategy, using CLKOUT (command not delayed, clock out delayed). POR reset value." /> + <Enum name="COMMAND_DELAYED_STRA" start="0x1" description="Command delayed strategy, using EMCCLKDELAY (command delayed, clock out not delayed)." /> + <Enum name="COMMAND_DELAYED_STRA" start="0x2" description="Command delayed strategy plus one clock cycle, using EMCCLKDELAY (command delayed, clock out not delayed)." /> + <Enum name="COMMAND_DELAYED_STRA" start="0x3" description="Command delayed strategy plus two clock cycles, using EMCCLKDELAY (command delayed, clock out not delayed)." /> + </BitField> + <BitField start="2" size="30" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x030" size="4" name="DYNAMICRP" access="Read/Write" description="Precharge command period." reset_value="0x0F" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="4" name="TRP" description="Precharge command period. 0x0 - 0xE = n + 1 clock cycles. The delay is in CCLK cycles. 0xF = 16 clock cycles (POR reset value)." /> + <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x034" size="4" name="DYNAMICRAS" access="Read/Write" description="Active to precharge command period." reset_value="0xF" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="4" name="TRAS" description="Active to precharge command period. 0x0 - 0xE = n + 1 clock cycles. The delay is in CCLK cycles. 0xF = 16 clock cycles (POR reset value)." /> + <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x038" size="4" name="DYNAMICSREX" access="Read/Write" description="Self-refresh exit time." reset_value="0xF" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="4" name="TSREX" description="Self-refresh exit time. 0x0 - 0xE = n + 1 clock cycles. The delay is in CCLK cycles. 0xF = 16 clock cycles (POR reset value)." /> + <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x03C" size="4" name="DYNAMICAPR" access="Read/Write" description="Last-data-out to active command time." reset_value="0xF" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="4" name="TAPR" description="Last-data-out to active command time. 0x0 - 0xE = n + 1 clock cycles. The delay is in CCLK cycles. 0xF = 16 clock cycles (POR reset value)." /> + <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x040" size="4" name="DYNAMICDAL" access="Read/Write" description="Data-in to active command time." reset_value="0xF" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="4" name="TDAL" description="Data-in to active command. 0x0 - 0xE = n clock cycles. The delay is in CCLK cycles. 0xF = 15 clock cycles (POR reset value)." /> + <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x044" size="4" name="DYNAMICWR" access="Read/Write" description="Write recovery time." reset_value="0xF" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="4" name="TWR" description="Write recovery time. 0x0 - 0xE = n + 1 clock cycles. The delay is in CCLK cycles. 0xF = 16 clock cycles (POR reset value)." /> + <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x048" size="4" name="DYNAMICRC" access="Read/Write" description="Selects the active to active command period." reset_value="0x1F" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="TRC" description="Active to active command period. 0x0 - 0x1E = n + 1 clock cycles. The delay is in CCLK cycles. 0x1F = 32 clock cycles (POR reset value)." /> + <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x04C" size="4" name="DYNAMICRFC" access="Read/Write" description="Selects the auto-refresh period." reset_value="0x1F" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="TRFC" description="Auto-refresh period and auto-refresh to active command period. 0x0 - 0x1E = n + 1 clock cycles. The delay is in CCLK cycles. 0x1F = 32 clock cycles (POR reset value)." /> + <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x050" size="4" name="DYNAMICXSR" access="Read/Write" description="Time for exit self-refresh to active command." reset_value="0x1F" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="TXSR" description="Exit self-refresh to active command time. 0x0 - 0x1E = n + 1 clock cycles. The delay is in CCLK cycles. 0x1F = 32 clock cycles (POR reset value)." /> + <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x054" size="4" name="DYNAMICRRD" access="Read/Write" description="Latency for active bank A to active bank B." reset_value="0xF" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="4" name="TRRD" description="Active bank A to active bank B latency 0x0 - 0xE = n + 1 clock cycles. The delay is in CCLK cycles. 0xF = 16 clock cycles (POR reset value)." /> + <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x058" size="4" name="DYNAMICMRD" access="Read/Write" description="Time for load mode register to active command." reset_value="0xF" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="4" name="TMRD" description="Load mode register to active command time. 0x0 - 0xE = n + 1 clock cycles. The delay is in CCLK cycles. 0xF = 16 clock cycles (POR reset value)." /> + <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x080" size="4" name="STATICEXTENDEDWAIT" access="Read/Write" description="Time for long static memory read and write transfers." reset_value="0x0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="10" name="EXTENDEDWAIT" description="Extended wait time out. 16 clock cycles (POR reset value). The delay is in CCLK cycles. 0x0 = 16 clock cycles. 0x1 - 0x3FF = (n+1) x16 clock cycles." /> + <BitField start="10" size="22" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x100+0" size="4" name="DYNAMICCONFIG0" access="Read/Write" description="Configuration information for EMC_DYCS0." reset_value="0x0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="3" size="2" name="MD" description="Memory device."> + <Enum name="SDRAM_POR_RESET_VAL" start="0x0" description="SDRAM (POR reset value)." /> + <Enum name="LOW_POWER_SDRAM_" start="0x1" description="Low-power SDRAM." /> + </BitField> + <BitField start="5" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="7" size="6" name="AM0" description="See Table 133. 000000 = reset value.[1]" /> + <BitField start="13" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="14" size="1" name="AM1" description="See Table 133. 0 = reset value." /> + <BitField start="15" size="4" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="19" size="1" name="B" description="Buffer enable."> + <Enum name="BUFFER_DISABLED_FOR_" start="0" description="Buffer disabled for accesses to this chip select (POR reset value)." /> + <Enum name="BUFFER_ENABLED_FOR_A" start="1" description="Buffer enabled for accesses to this chip select.[2]" /> + </BitField> + <BitField start="20" size="1" name="P" description="Write protect."> + <Enum name="WRITES_NOT_PROTECTED" start="0" description="Writes not protected (POR reset value)." /> + <Enum name="WRITES_PROTECTED_" start="1" description="Writes protected." /> + </BitField> + <BitField start="21" size="11" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x100+32" size="4" name="DYNAMICCONFIG1" access="Read/Write" description="Configuration information for EMC_DYCS0." reset_value="0x0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="3" size="2" name="MD" description="Memory device."> + <Enum name="SDRAM_POR_RESET_VAL" start="0x0" description="SDRAM (POR reset value)." /> + <Enum name="LOW_POWER_SDRAM_" start="0x1" description="Low-power SDRAM." /> + </BitField> + <BitField start="5" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="7" size="6" name="AM0" description="See Table 133. 000000 = reset value.[1]" /> + <BitField start="13" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="14" size="1" name="AM1" description="See Table 133. 0 = reset value." /> + <BitField start="15" size="4" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="19" size="1" name="B" description="Buffer enable."> + <Enum name="BUFFER_DISABLED_FOR_" start="0" description="Buffer disabled for accesses to this chip select (POR reset value)." /> + <Enum name="BUFFER_ENABLED_FOR_A" start="1" description="Buffer enabled for accesses to this chip select.[2]" /> + </BitField> + <BitField start="20" size="1" name="P" description="Write protect."> + <Enum name="WRITES_NOT_PROTECTED" start="0" description="Writes not protected (POR reset value)." /> + <Enum name="WRITES_PROTECTED_" start="1" description="Writes protected." /> + </BitField> + <BitField start="21" size="11" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x100+64" size="4" name="DYNAMICCONFIG2" access="Read/Write" description="Configuration information for EMC_DYCS0." reset_value="0x0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="3" size="2" name="MD" description="Memory device."> + <Enum name="SDRAM_POR_RESET_VAL" start="0x0" description="SDRAM (POR reset value)." /> + <Enum name="LOW_POWER_SDRAM_" start="0x1" description="Low-power SDRAM." /> + </BitField> + <BitField start="5" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="7" size="6" name="AM0" description="See Table 133. 000000 = reset value.[1]" /> + <BitField start="13" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="14" size="1" name="AM1" description="See Table 133. 0 = reset value." /> + <BitField start="15" size="4" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="19" size="1" name="B" description="Buffer enable."> + <Enum name="BUFFER_DISABLED_FOR_" start="0" description="Buffer disabled for accesses to this chip select (POR reset value)." /> + <Enum name="BUFFER_ENABLED_FOR_A" start="1" description="Buffer enabled for accesses to this chip select.[2]" /> + </BitField> + <BitField start="20" size="1" name="P" description="Write protect."> + <Enum name="WRITES_NOT_PROTECTED" start="0" description="Writes not protected (POR reset value)." /> + <Enum name="WRITES_PROTECTED_" start="1" description="Writes protected." /> + </BitField> + <BitField start="21" size="11" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x100+96" size="4" name="DYNAMICCONFIG3" access="Read/Write" description="Configuration information for EMC_DYCS0." reset_value="0x0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="3" size="2" name="MD" description="Memory device."> + <Enum name="SDRAM_POR_RESET_VAL" start="0x0" description="SDRAM (POR reset value)." /> + <Enum name="LOW_POWER_SDRAM_" start="0x1" description="Low-power SDRAM." /> + </BitField> + <BitField start="5" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="7" size="6" name="AM0" description="See Table 133. 000000 = reset value.[1]" /> + <BitField start="13" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="14" size="1" name="AM1" description="See Table 133. 0 = reset value." /> + <BitField start="15" size="4" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="19" size="1" name="B" description="Buffer enable."> + <Enum name="BUFFER_DISABLED_FOR_" start="0" description="Buffer disabled for accesses to this chip select (POR reset value)." /> + <Enum name="BUFFER_ENABLED_FOR_A" start="1" description="Buffer enabled for accesses to this chip select.[2]" /> + </BitField> + <BitField start="20" size="1" name="P" description="Write protect."> + <Enum name="WRITES_NOT_PROTECTED" start="0" description="Writes not protected (POR reset value)." /> + <Enum name="WRITES_PROTECTED_" start="1" description="Writes protected." /> + </BitField> + <BitField start="21" size="11" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x104+0" size="4" name="DYNAMICRASCAS0" access="Read/Write" description="RAS and CAS latencies for EMC_DYCS0." reset_value="0x303" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="RAS" description="RAS latency (active to read/write delay)."> + <Enum name="ONE_CCLK_CYCLE_" start="0x1" description="One CCLK cycle." /> + <Enum name="TWO_CCLK_CYCLES_" start="0x2" description="Two CCLK cycles." /> + <Enum name="THREE_CCLK_CYCLES_P" start="0x3" description="Three CCLK cycles (POR reset value)." /> + </BitField> + <BitField start="2" size="6" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + <BitField start="8" size="2" name="CAS" description="CAS latency."> + <Enum name="ONE_CCLK_CYCLE_" start="0x1" description="One CCLK cycle." /> + <Enum name="TWO_CCLK_CYCLES_" start="0x2" description="Two CCLK cycles." /> + <Enum name="THREE_CCLK_CYCLES_P" start="0x3" description="Three CCLK cycles (POR reset value)." /> + </BitField> + <BitField start="10" size="22" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x104+32" size="4" name="DYNAMICRASCAS1" access="Read/Write" description="RAS and CAS latencies for EMC_DYCS0." reset_value="0x303" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="RAS" description="RAS latency (active to read/write delay)."> + <Enum name="ONE_CCLK_CYCLE_" start="0x1" description="One CCLK cycle." /> + <Enum name="TWO_CCLK_CYCLES_" start="0x2" description="Two CCLK cycles." /> + <Enum name="THREE_CCLK_CYCLES_P" start="0x3" description="Three CCLK cycles (POR reset value)." /> + </BitField> + <BitField start="2" size="6" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + <BitField start="8" size="2" name="CAS" description="CAS latency."> + <Enum name="ONE_CCLK_CYCLE_" start="0x1" description="One CCLK cycle." /> + <Enum name="TWO_CCLK_CYCLES_" start="0x2" description="Two CCLK cycles." /> + <Enum name="THREE_CCLK_CYCLES_P" start="0x3" description="Three CCLK cycles (POR reset value)." /> + </BitField> + <BitField start="10" size="22" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x104+64" size="4" name="DYNAMICRASCAS2" access="Read/Write" description="RAS and CAS latencies for EMC_DYCS0." reset_value="0x303" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="RAS" description="RAS latency (active to read/write delay)."> + <Enum name="ONE_CCLK_CYCLE_" start="0x1" description="One CCLK cycle." /> + <Enum name="TWO_CCLK_CYCLES_" start="0x2" description="Two CCLK cycles." /> + <Enum name="THREE_CCLK_CYCLES_P" start="0x3" description="Three CCLK cycles (POR reset value)." /> + </BitField> + <BitField start="2" size="6" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + <BitField start="8" size="2" name="CAS" description="CAS latency."> + <Enum name="ONE_CCLK_CYCLE_" start="0x1" description="One CCLK cycle." /> + <Enum name="TWO_CCLK_CYCLES_" start="0x2" description="Two CCLK cycles." /> + <Enum name="THREE_CCLK_CYCLES_P" start="0x3" description="Three CCLK cycles (POR reset value)." /> + </BitField> + <BitField start="10" size="22" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x104+96" size="4" name="DYNAMICRASCAS3" access="Read/Write" description="RAS and CAS latencies for EMC_DYCS0." reset_value="0x303" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="RAS" description="RAS latency (active to read/write delay)."> + <Enum name="ONE_CCLK_CYCLE_" start="0x1" description="One CCLK cycle." /> + <Enum name="TWO_CCLK_CYCLES_" start="0x2" description="Two CCLK cycles." /> + <Enum name="THREE_CCLK_CYCLES_P" start="0x3" description="Three CCLK cycles (POR reset value)." /> + </BitField> + <BitField start="2" size="6" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + <BitField start="8" size="2" name="CAS" description="CAS latency."> + <Enum name="ONE_CCLK_CYCLE_" start="0x1" description="One CCLK cycle." /> + <Enum name="TWO_CCLK_CYCLES_" start="0x2" description="Two CCLK cycles." /> + <Enum name="THREE_CCLK_CYCLES_P" start="0x3" description="Three CCLK cycles (POR reset value)." /> + </BitField> + <BitField start="10" size="22" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x200+0" size="4" name="STATICCONFIG0" access="Read/Write" description="Configuration for EMC_CS0." reset_value="0x0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="MW" description="Memory width."> + <Enum name="8_BIT_POR_RESET_VAL" start="0x0" description="8 bit (POR reset value)." /> + <Enum name="16_BIT_" start="0x1" description="16 bit." /> + <Enum name="32_BIT_" start="0x2" description="32 bit." /> + </BitField> + <BitField start="2" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="3" size="1" name="PM" description="Page mode. In page mode the EMC can burst up to four external accesses. Therefore devices with asynchronous page mode burst four or higher devices are supported. Asynchronous page mode burst two devices are not supported and must be accessed normally."> + <Enum name="DISABLED_POR_RESET_" start="0" description="Disabled (POR reset value)." /> + <Enum name="ASYNCHRONOUS_PAGE_MO" start="1" description="Asynchronous page mode enabled (page length four)." /> + </BitField> + <BitField start="4" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="6" size="1" name="PC" description="Chip select polarity. The value of the chip select polarity on power-on reset is 0."> + <Enum name="ACTIVE_LOW_CHIP_SELE" start="0" description="Active LOW chip select." /> + <Enum name="ACTIVE_HIGH_CHIP_SEL" start="1" description="Active HIGH chip select." /> + </BitField> + <BitField start="7" size="1" name="PB" description="Byte lane state. The byte lane state bit, PB, enables different types of memory to be connected. For byte-wide static memories the BLS3:0 signal from the EMC is usually connected to WE (write enable). In this case for reads all the BLS3:0 bits must be HIGH. This means that the byte lane state (PB) bit must be LOW. 16 bit wide static memory devices usually have the BLS3:0 signals connected to the UBn and LBn (upper byte and lower byte) signals in the static memory. In this case a write to a particular byte must assert the appropriate UBn or LBn signal LOW. For reads, all the UB and LB signals must be asserted LOW so that the bus is driven. In this case the byte lane state (PB) bit must be HIGH."> + <Enum name="BLSHIGH" start="0" description="For reads all the bits in BLS3:0 are HIGH. For writes the respective active bits in BLS3:0 are LOW (POR reset value)." /> + <Enum name="BLSLOW" start="1" description="For reads the respective active bits in BLS3:0 are LOW. For writes the respective active bits in BLS3:0 are LOW." /> + </BitField> + <BitField start="8" size="1" name="EW" description="Extended wait (EW) uses the EMCStaticExtendedWait register to time both the read and write transfers rather than the EMCStaticWaitRd and EMCStaticWaitWr registers. This enables much longer transactions. [1]"> + <Enum name="EXTENDED_WAIT_DISABL" start="0" description="Extended wait disabled (POR reset value)." /> + <Enum name="EXTENDED_WAIT_ENABLE" start="1" description="Extended wait enabled." /> + </BitField> + <BitField start="9" size="10" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="19" size="1" name="B" description="Buffer enable [2]"> + <Enum name="BUFFER_DISABLED_POR" start="0" description="Buffer disabled (POR reset value)." /> + <Enum name="BUFFER_ENABLED_" start="1" description="Buffer enabled." /> + </BitField> + <BitField start="20" size="1" name="P" description="Write protect"> + <Enum name="WRITES_NOT_PROTECTED" start="0" description="Writes not protected (POR reset value)." /> + <Enum name="WRITE_PROTECTED_" start="1" description="Write protected." /> + </BitField> + <BitField start="21" size="11" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x200+32" size="4" name="STATICCONFIG1" access="Read/Write" description="Configuration for EMC_CS0." reset_value="0x0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="MW" description="Memory width."> + <Enum name="8_BIT_POR_RESET_VAL" start="0x0" description="8 bit (POR reset value)." /> + <Enum name="16_BIT_" start="0x1" description="16 bit." /> + <Enum name="32_BIT_" start="0x2" description="32 bit." /> + </BitField> + <BitField start="2" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="3" size="1" name="PM" description="Page mode. In page mode the EMC can burst up to four external accesses. Therefore devices with asynchronous page mode burst four or higher devices are supported. Asynchronous page mode burst two devices are not supported and must be accessed normally."> + <Enum name="DISABLED_POR_RESET_" start="0" description="Disabled (POR reset value)." /> + <Enum name="ASYNCHRONOUS_PAGE_MO" start="1" description="Asynchronous page mode enabled (page length four)." /> + </BitField> + <BitField start="4" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="6" size="1" name="PC" description="Chip select polarity. The value of the chip select polarity on power-on reset is 0."> + <Enum name="ACTIVE_LOW_CHIP_SELE" start="0" description="Active LOW chip select." /> + <Enum name="ACTIVE_HIGH_CHIP_SEL" start="1" description="Active HIGH chip select." /> + </BitField> + <BitField start="7" size="1" name="PB" description="Byte lane state. The byte lane state bit, PB, enables different types of memory to be connected. For byte-wide static memories the BLS3:0 signal from the EMC is usually connected to WE (write enable). In this case for reads all the BLS3:0 bits must be HIGH. This means that the byte lane state (PB) bit must be LOW. 16 bit wide static memory devices usually have the BLS3:0 signals connected to the UBn and LBn (upper byte and lower byte) signals in the static memory. In this case a write to a particular byte must assert the appropriate UBn or LBn signal LOW. For reads, all the UB and LB signals must be asserted LOW so that the bus is driven. In this case the byte lane state (PB) bit must be HIGH."> + <Enum name="BLSHIGH" start="0" description="For reads all the bits in BLS3:0 are HIGH. For writes the respective active bits in BLS3:0 are LOW (POR reset value)." /> + <Enum name="BLSLOW" start="1" description="For reads the respective active bits in BLS3:0 are LOW. For writes the respective active bits in BLS3:0 are LOW." /> + </BitField> + <BitField start="8" size="1" name="EW" description="Extended wait (EW) uses the EMCStaticExtendedWait register to time both the read and write transfers rather than the EMCStaticWaitRd and EMCStaticWaitWr registers. This enables much longer transactions. [1]"> + <Enum name="EXTENDED_WAIT_DISABL" start="0" description="Extended wait disabled (POR reset value)." /> + <Enum name="EXTENDED_WAIT_ENABLE" start="1" description="Extended wait enabled." /> + </BitField> + <BitField start="9" size="10" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="19" size="1" name="B" description="Buffer enable [2]"> + <Enum name="BUFFER_DISABLED_POR" start="0" description="Buffer disabled (POR reset value)." /> + <Enum name="BUFFER_ENABLED_" start="1" description="Buffer enabled." /> + </BitField> + <BitField start="20" size="1" name="P" description="Write protect"> + <Enum name="WRITES_NOT_PROTECTED" start="0" description="Writes not protected (POR reset value)." /> + <Enum name="WRITE_PROTECTED_" start="1" description="Write protected." /> + </BitField> + <BitField start="21" size="11" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x200+64" size="4" name="STATICCONFIG2" access="Read/Write" description="Configuration for EMC_CS0." reset_value="0x0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="MW" description="Memory width."> + <Enum name="8_BIT_POR_RESET_VAL" start="0x0" description="8 bit (POR reset value)." /> + <Enum name="16_BIT_" start="0x1" description="16 bit." /> + <Enum name="32_BIT_" start="0x2" description="32 bit." /> + </BitField> + <BitField start="2" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="3" size="1" name="PM" description="Page mode. In page mode the EMC can burst up to four external accesses. Therefore devices with asynchronous page mode burst four or higher devices are supported. Asynchronous page mode burst two devices are not supported and must be accessed normally."> + <Enum name="DISABLED_POR_RESET_" start="0" description="Disabled (POR reset value)." /> + <Enum name="ASYNCHRONOUS_PAGE_MO" start="1" description="Asynchronous page mode enabled (page length four)." /> + </BitField> + <BitField start="4" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="6" size="1" name="PC" description="Chip select polarity. The value of the chip select polarity on power-on reset is 0."> + <Enum name="ACTIVE_LOW_CHIP_SELE" start="0" description="Active LOW chip select." /> + <Enum name="ACTIVE_HIGH_CHIP_SEL" start="1" description="Active HIGH chip select." /> + </BitField> + <BitField start="7" size="1" name="PB" description="Byte lane state. The byte lane state bit, PB, enables different types of memory to be connected. For byte-wide static memories the BLS3:0 signal from the EMC is usually connected to WE (write enable). In this case for reads all the BLS3:0 bits must be HIGH. This means that the byte lane state (PB) bit must be LOW. 16 bit wide static memory devices usually have the BLS3:0 signals connected to the UBn and LBn (upper byte and lower byte) signals in the static memory. In this case a write to a particular byte must assert the appropriate UBn or LBn signal LOW. For reads, all the UB and LB signals must be asserted LOW so that the bus is driven. In this case the byte lane state (PB) bit must be HIGH."> + <Enum name="BLSHIGH" start="0" description="For reads all the bits in BLS3:0 are HIGH. For writes the respective active bits in BLS3:0 are LOW (POR reset value)." /> + <Enum name="BLSLOW" start="1" description="For reads the respective active bits in BLS3:0 are LOW. For writes the respective active bits in BLS3:0 are LOW." /> + </BitField> + <BitField start="8" size="1" name="EW" description="Extended wait (EW) uses the EMCStaticExtendedWait register to time both the read and write transfers rather than the EMCStaticWaitRd and EMCStaticWaitWr registers. This enables much longer transactions. [1]"> + <Enum name="EXTENDED_WAIT_DISABL" start="0" description="Extended wait disabled (POR reset value)." /> + <Enum name="EXTENDED_WAIT_ENABLE" start="1" description="Extended wait enabled." /> + </BitField> + <BitField start="9" size="10" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="19" size="1" name="B" description="Buffer enable [2]"> + <Enum name="BUFFER_DISABLED_POR" start="0" description="Buffer disabled (POR reset value)." /> + <Enum name="BUFFER_ENABLED_" start="1" description="Buffer enabled." /> + </BitField> + <BitField start="20" size="1" name="P" description="Write protect"> + <Enum name="WRITES_NOT_PROTECTED" start="0" description="Writes not protected (POR reset value)." /> + <Enum name="WRITE_PROTECTED_" start="1" description="Write protected." /> + </BitField> + <BitField start="21" size="11" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x200+96" size="4" name="STATICCONFIG3" access="Read/Write" description="Configuration for EMC_CS0." reset_value="0x0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="MW" description="Memory width."> + <Enum name="8_BIT_POR_RESET_VAL" start="0x0" description="8 bit (POR reset value)." /> + <Enum name="16_BIT_" start="0x1" description="16 bit." /> + <Enum name="32_BIT_" start="0x2" description="32 bit." /> + </BitField> + <BitField start="2" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="3" size="1" name="PM" description="Page mode. In page mode the EMC can burst up to four external accesses. Therefore devices with asynchronous page mode burst four or higher devices are supported. Asynchronous page mode burst two devices are not supported and must be accessed normally."> + <Enum name="DISABLED_POR_RESET_" start="0" description="Disabled (POR reset value)." /> + <Enum name="ASYNCHRONOUS_PAGE_MO" start="1" description="Asynchronous page mode enabled (page length four)." /> + </BitField> + <BitField start="4" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="6" size="1" name="PC" description="Chip select polarity. The value of the chip select polarity on power-on reset is 0."> + <Enum name="ACTIVE_LOW_CHIP_SELE" start="0" description="Active LOW chip select." /> + <Enum name="ACTIVE_HIGH_CHIP_SEL" start="1" description="Active HIGH chip select." /> + </BitField> + <BitField start="7" size="1" name="PB" description="Byte lane state. The byte lane state bit, PB, enables different types of memory to be connected. For byte-wide static memories the BLS3:0 signal from the EMC is usually connected to WE (write enable). In this case for reads all the BLS3:0 bits must be HIGH. This means that the byte lane state (PB) bit must be LOW. 16 bit wide static memory devices usually have the BLS3:0 signals connected to the UBn and LBn (upper byte and lower byte) signals in the static memory. In this case a write to a particular byte must assert the appropriate UBn or LBn signal LOW. For reads, all the UB and LB signals must be asserted LOW so that the bus is driven. In this case the byte lane state (PB) bit must be HIGH."> + <Enum name="BLSHIGH" start="0" description="For reads all the bits in BLS3:0 are HIGH. For writes the respective active bits in BLS3:0 are LOW (POR reset value)." /> + <Enum name="BLSLOW" start="1" description="For reads the respective active bits in BLS3:0 are LOW. For writes the respective active bits in BLS3:0 are LOW." /> + </BitField> + <BitField start="8" size="1" name="EW" description="Extended wait (EW) uses the EMCStaticExtendedWait register to time both the read and write transfers rather than the EMCStaticWaitRd and EMCStaticWaitWr registers. This enables much longer transactions. [1]"> + <Enum name="EXTENDED_WAIT_DISABL" start="0" description="Extended wait disabled (POR reset value)." /> + <Enum name="EXTENDED_WAIT_ENABLE" start="1" description="Extended wait enabled." /> + </BitField> + <BitField start="9" size="10" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="19" size="1" name="B" description="Buffer enable [2]"> + <Enum name="BUFFER_DISABLED_POR" start="0" description="Buffer disabled (POR reset value)." /> + <Enum name="BUFFER_ENABLED_" start="1" description="Buffer enabled." /> + </BitField> + <BitField start="20" size="1" name="P" description="Write protect"> + <Enum name="WRITES_NOT_PROTECTED" start="0" description="Writes not protected (POR reset value)." /> + <Enum name="WRITE_PROTECTED_" start="1" description="Write protected." /> + </BitField> + <BitField start="21" size="11" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x204+0" size="4" name="STATICWAITWEN0" access="Read/Write" description="Delay from EMC_CS0 to write enable." reset_value="0x0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="4" name="WAITWEN" description="Wait write enable. Delay from chip select assertion to write enable. 0x0 = One CCLK cycle delay between assertion of chip select and write enable (POR reset value). 0x1 - 0xF = (n + 1) CCLK cycle delay. The delay is (WAITWEN +1) x tCCLK." /> + <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x204+32" size="4" name="STATICWAITWEN1" access="Read/Write" description="Delay from EMC_CS0 to write enable." reset_value="0x0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="4" name="WAITWEN" description="Wait write enable. Delay from chip select assertion to write enable. 0x0 = One CCLK cycle delay between assertion of chip select and write enable (POR reset value). 0x1 - 0xF = (n + 1) CCLK cycle delay. The delay is (WAITWEN +1) x tCCLK." /> + <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x204+64" size="4" name="STATICWAITWEN2" access="Read/Write" description="Delay from EMC_CS0 to write enable." reset_value="0x0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="4" name="WAITWEN" description="Wait write enable. Delay from chip select assertion to write enable. 0x0 = One CCLK cycle delay between assertion of chip select and write enable (POR reset value). 0x1 - 0xF = (n + 1) CCLK cycle delay. The delay is (WAITWEN +1) x tCCLK." /> + <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x204+96" size="4" name="STATICWAITWEN3" access="Read/Write" description="Delay from EMC_CS0 to write enable." reset_value="0x0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="4" name="WAITWEN" description="Wait write enable. Delay from chip select assertion to write enable. 0x0 = One CCLK cycle delay between assertion of chip select and write enable (POR reset value). 0x1 - 0xF = (n + 1) CCLK cycle delay. The delay is (WAITWEN +1) x tCCLK." /> + <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x208+0" size="4" name="STATICWAITOEN0" access="Read/Write" description="Delay from EMC_CS0 or address change, whichever is later, to output enable." reset_value="0x0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="4" name="WAITOEN" description="Wait output enable. Delay from chip select assertion to output enable. 0x0 = No delay (POR reset value). 0x1 - 0xF = n cycle delay. The delay is WAITOEN x tCCLK." /> + <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x208+32" size="4" name="STATICWAITOEN1" access="Read/Write" description="Delay from EMC_CS0 or address change, whichever is later, to output enable." reset_value="0x0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="4" name="WAITOEN" description="Wait output enable. Delay from chip select assertion to output enable. 0x0 = No delay (POR reset value). 0x1 - 0xF = n cycle delay. The delay is WAITOEN x tCCLK." /> + <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x208+64" size="4" name="STATICWAITOEN2" access="Read/Write" description="Delay from EMC_CS0 or address change, whichever is later, to output enable." reset_value="0x0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="4" name="WAITOEN" description="Wait output enable. Delay from chip select assertion to output enable. 0x0 = No delay (POR reset value). 0x1 - 0xF = n cycle delay. The delay is WAITOEN x tCCLK." /> + <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x208+96" size="4" name="STATICWAITOEN3" access="Read/Write" description="Delay from EMC_CS0 or address change, whichever is later, to output enable." reset_value="0x0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="4" name="WAITOEN" description="Wait output enable. Delay from chip select assertion to output enable. 0x0 = No delay (POR reset value). 0x1 - 0xF = n cycle delay. The delay is WAITOEN x tCCLK." /> + <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x20C+0" size="4" name="STATICWAITRD0" access="Read/Write" description="Delay from EMC_CS0 to a read access." reset_value="0x1F" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="WAITRD" description="Non-page mode read wait states or asynchronous page mode read first access wait state. Non-page mode read or asynchronous page mode read, first read only: 0x0 - 0x1E = (n + 1) CCLK cycles for read accesses. For non-sequential reads, the wait state time is (WAITRD + 1) x tCCLK. 0x1F = 32 CCLK cycles for read accesses (POR reset value)." /> + <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x20C+32" size="4" name="STATICWAITRD1" access="Read/Write" description="Delay from EMC_CS0 to a read access." reset_value="0x1F" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="WAITRD" description="Non-page mode read wait states or asynchronous page mode read first access wait state. Non-page mode read or asynchronous page mode read, first read only: 0x0 - 0x1E = (n + 1) CCLK cycles for read accesses. For non-sequential reads, the wait state time is (WAITRD + 1) x tCCLK. 0x1F = 32 CCLK cycles for read accesses (POR reset value)." /> + <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x20C+64" size="4" name="STATICWAITRD2" access="Read/Write" description="Delay from EMC_CS0 to a read access." reset_value="0x1F" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="WAITRD" description="Non-page mode read wait states or asynchronous page mode read first access wait state. Non-page mode read or asynchronous page mode read, first read only: 0x0 - 0x1E = (n + 1) CCLK cycles for read accesses. For non-sequential reads, the wait state time is (WAITRD + 1) x tCCLK. 0x1F = 32 CCLK cycles for read accesses (POR reset value)." /> + <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x20C+96" size="4" name="STATICWAITRD3" access="Read/Write" description="Delay from EMC_CS0 to a read access." reset_value="0x1F" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="WAITRD" description="Non-page mode read wait states or asynchronous page mode read first access wait state. Non-page mode read or asynchronous page mode read, first read only: 0x0 - 0x1E = (n + 1) CCLK cycles for read accesses. For non-sequential reads, the wait state time is (WAITRD + 1) x tCCLK. 0x1F = 32 CCLK cycles for read accesses (POR reset value)." /> + <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x210+0" size="4" name="STATICWAITPAGE0" access="Read/Write" description="Delay for asynchronous page mode sequential accesses for EMC_CS0." reset_value="0x1F" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="WAITPAGE" description="Asynchronous page mode read after the first read wait states. Number of wait states for asynchronous page mode read accesses after the first read: 0x0 - 0x1E = (n+ 1) CCLK cycle read access time. For asynchronous page mode read for sequential reads, the wait state time for page mode accesses after the first read is (WAITPAGE + 1) x tCCLK. 0x1F = 32 CCLK cycle read access time (POR reset value)." /> + <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x210+32" size="4" name="STATICWAITPAGE1" access="Read/Write" description="Delay for asynchronous page mode sequential accesses for EMC_CS0." reset_value="0x1F" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="WAITPAGE" description="Asynchronous page mode read after the first read wait states. Number of wait states for asynchronous page mode read accesses after the first read: 0x0 - 0x1E = (n+ 1) CCLK cycle read access time. For asynchronous page mode read for sequential reads, the wait state time for page mode accesses after the first read is (WAITPAGE + 1) x tCCLK. 0x1F = 32 CCLK cycle read access time (POR reset value)." /> + <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x210+64" size="4" name="STATICWAITPAGE2" access="Read/Write" description="Delay for asynchronous page mode sequential accesses for EMC_CS0." reset_value="0x1F" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="WAITPAGE" description="Asynchronous page mode read after the first read wait states. Number of wait states for asynchronous page mode read accesses after the first read: 0x0 - 0x1E = (n+ 1) CCLK cycle read access time. For asynchronous page mode read for sequential reads, the wait state time for page mode accesses after the first read is (WAITPAGE + 1) x tCCLK. 0x1F = 32 CCLK cycle read access time (POR reset value)." /> + <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x210+96" size="4" name="STATICWAITPAGE3" access="Read/Write" description="Delay for asynchronous page mode sequential accesses for EMC_CS0." reset_value="0x1F" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="WAITPAGE" description="Asynchronous page mode read after the first read wait states. Number of wait states for asynchronous page mode read accesses after the first read: 0x0 - 0x1E = (n+ 1) CCLK cycle read access time. For asynchronous page mode read for sequential reads, the wait state time for page mode accesses after the first read is (WAITPAGE + 1) x tCCLK. 0x1F = 32 CCLK cycle read access time (POR reset value)." /> + <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x214+0" size="4" name="STATICWAITWR0" access="Read/Write" description="Delay from EMC_CS0 to a write access." reset_value="0x1F" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="WAITWR" description="Write wait states. SRAM wait state time for write accesses after the first read: 0x0 - 0x1E = (n + 2) CCLK cycle write access time. The wait state time for write accesses after the first read is WAITWR (n + 2) x tCCLK. 0x1F = 33 CCLK cycle write access time (POR reset value)." /> + <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x214+32" size="4" name="STATICWAITWR1" access="Read/Write" description="Delay from EMC_CS0 to a write access." reset_value="0x1F" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="WAITWR" description="Write wait states. SRAM wait state time for write accesses after the first read: 0x0 - 0x1E = (n + 2) CCLK cycle write access time. The wait state time for write accesses after the first read is WAITWR (n + 2) x tCCLK. 0x1F = 33 CCLK cycle write access time (POR reset value)." /> + <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x214+64" size="4" name="STATICWAITWR2" access="Read/Write" description="Delay from EMC_CS0 to a write access." reset_value="0x1F" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="WAITWR" description="Write wait states. SRAM wait state time for write accesses after the first read: 0x0 - 0x1E = (n + 2) CCLK cycle write access time. The wait state time for write accesses after the first read is WAITWR (n + 2) x tCCLK. 0x1F = 33 CCLK cycle write access time (POR reset value)." /> + <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x214+96" size="4" name="STATICWAITWR3" access="Read/Write" description="Delay from EMC_CS0 to a write access." reset_value="0x1F" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="WAITWR" description="Write wait states. SRAM wait state time for write accesses after the first read: 0x0 - 0x1E = (n + 2) CCLK cycle write access time. The wait state time for write accesses after the first read is WAITWR (n + 2) x tCCLK. 0x1F = 33 CCLK cycle write access time (POR reset value)." /> + <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x218+0" size="4" name="STATICWAITTURN0" access="Read/Write" description="Number of bus turnaround cycles EMC_CS0." reset_value="0xF" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="4" name="WAITTURN" description="Bus turn-around cycles. 0x0 - 0xE = (n + 1) CCLK turn-around cycles. Bus turn-around time is (WAITTURN + 1) x tCCLK. 0xF = 16 CCLK turn-around cycles (POR reset value)." /> + <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x218+32" size="4" name="STATICWAITTURN1" access="Read/Write" description="Number of bus turnaround cycles EMC_CS0." reset_value="0xF" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="4" name="WAITTURN" description="Bus turn-around cycles. 0x0 - 0xE = (n + 1) CCLK turn-around cycles. Bus turn-around time is (WAITTURN + 1) x tCCLK. 0xF = 16 CCLK turn-around cycles (POR reset value)." /> + <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x218+64" size="4" name="STATICWAITTURN2" access="Read/Write" description="Number of bus turnaround cycles EMC_CS0." reset_value="0xF" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="4" name="WAITTURN" description="Bus turn-around cycles. 0x0 - 0xE = (n + 1) CCLK turn-around cycles. Bus turn-around time is (WAITTURN + 1) x tCCLK. 0xF = 16 CCLK turn-around cycles (POR reset value)." /> + <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x218+96" size="4" name="STATICWAITTURN3" access="Read/Write" description="Number of bus turnaround cycles EMC_CS0." reset_value="0xF" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="4" name="WAITTURN" description="Bus turn-around cycles. 0x0 - 0xE = (n + 1) CCLK turn-around cycles. Bus turn-around time is (WAITTURN + 1) x tCCLK. 0xF = 16 CCLK turn-around cycles (POR reset value)." /> + <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + </RegisterGroup> + <RegisterGroup name="WWDT" start="0x40000000" description=" Windowed Watchdog Timer (WWDT) "> + <Register start="+0x000" size="4" name="MOD" access="Read/Write" description="Watchdog mode register. This register determines the basic mode and status of the Watchdog Timer." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="WDEN" description="Watchdog enable bit. This bit is Set Only. See Table 652."> + <Enum name="STOP" start="0" description="The watchdog timer is stopped." /> + <Enum name="RUN" start="1" description="The watchdog timer is running." /> + </BitField> + <BitField start="1" size="1" name="WDRESET" description="Watchdog reset enable bit. This bit is Set Only. See Table 652."> + <Enum name="NORESET" start="0" description="A watchdog timeout will not cause a chip reset." /> + <Enum name="RESET" start="1" description="A watchdog timeout will cause a chip reset." /> + </BitField> + <BitField start="2" size="1" name="WDTOF" description="Watchdog time-out flag. Set when the watchdog timer times out, by a feed error, or by events associated with WDPROTECT, cleared by software. Causes a chip reset if WDRESET = 1. See Section WDTOF." /> + <BitField start="3" size="1" name="WDINT" description="Watchdog interrupt flag. Set when the timer reaches the value in WDWARNINT. Cleared by software. See Section WDINT." /> + <BitField start="4" size="1" name="WDPROTECT" description="Watchdog update mode. This bit is Set Only. See Section WDPROTECT."> + <Enum name="CHANGE" start="0" description="The watchdog reload value (WDTC) can be changed at any time." /> + <Enum name="CHANGE_W_CNT" start="1" description="The watchdog reload value (WDTC) can be changed only after the counter is below the value of WDWARNINT and WDWINDOW. Note: this mode is intended for use only when WDRESET =1." /> + </BitField> + <BitField start="5" size="3" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x004" size="4" name="TC" access="Read/Write" description="Watchdog timer constant register. The value in this register determines the time-out value." reset_value="0xFF" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="24" name="Count" description="Watchdog time-out interval." /> + <BitField start="24" size="8" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x008" size="4" name="FEED" access="WriteOnly" description="Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in WDTC." reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="8" name="Feed" description="Feed value should be 0xAA followed by 0x55." /> + </Register> + <Register start="+0x00C" size="4" name="TV" access="ReadOnly" description="Watchdog timer value register. This register reads out the current value of the Watchdog timer." reset_value="0xFF" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="24" name="Count" description="Counter timer value." /> + <BitField start="24" size="8" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x014" size="4" name="WARNINT" access="Read/Write" description="Watchdog Warning Interrupt compare value." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="10" name="WARNINT" description="Watchdog warning interrupt compare value." /> + <BitField start="10" size="22" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x018" size="4" name="WINDOW" access="Read/Write" description="Watchdog Window compare value." reset_value="0xFFFFFF" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="24" name="WINDOW" description="Watchdog window value." /> + <BitField start="24" size="8" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + </RegisterGroup> + <RegisterGroup name="TIMER0" start="0x40004000" description=" Timer0/1/2/3 "> + <Register start="+0x000" size="4" name="IR" access="Read/Write" description="Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="MR0INT" description="Interrupt flag for match channel 0." /> + <BitField start="1" size="1" name="MR1INT" description="Interrupt flag for match channel 1." /> + <BitField start="2" size="1" name="MR2INT" description="Interrupt flag for match channel 2." /> + <BitField start="3" size="1" name="MR3INT" description="Interrupt flag for match channel 3." /> + <BitField start="4" size="1" name="CR0INT" description="Interrupt flag for capture channel 0 event." /> + <BitField start="5" size="1" name="CR1INT" description="Interrupt flag for capture channel 1 event." /> + <BitField start="6" size="26" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x004" size="4" name="TCR" access="Read/Write" description="Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="CEN" description="When one, the Timer Counter and Prescale Counter are enabled for counting. When zero, the counters are disabled." /> + <BitField start="1" size="1" name="CRST" description="When one, the Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero." /> + <BitField start="2" size="30" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x008" size="4" name="TC" access="Read/Write" description="Timer Counter. The 32 bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="TC" description="Timer counter value." /> + </Register> + <Register start="+0x00C" size="4" name="PR" access="Read/Write" description="Prescale Register. When the Prescale Counter (PC) is equal to this value, the next clock increments the TC and clears the PC." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="PM" description="Prescale counter maximum value." /> + </Register> + <Register start="+0x010" size="4" name="PC" access="Read/Write" description="Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="PC" description="Prescale counter value." /> + </Register> + <Register start="+0x014" size="4" name="MCR" access="Read/Write" description="Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="MR0I" description="Interrupt on MR0"> + <Enum name="INTERRUPT_IS_GENERAT" start="1" description="Interrupt is generated when MR0 matches the value in the TC." /> + <Enum name="INTERRUPT_IS_DISABLE" start="0" description="Interrupt is disabled" /> + </BitField> + <BitField start="1" size="1" name="MR0R" description="Reset on MR0"> + <Enum name="TC_WILL_BE_RESET_IF_" start="1" description="TC will be reset if MR0 matches it." /> + <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." /> + </BitField> + <BitField start="2" size="1" name="MR0S" description="Stop on MR0"> + <Enum name="TC_AND_PC_WILL_BE_ST" start="1" description="TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC." /> + <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." /> + </BitField> + <BitField start="3" size="1" name="MR1I" description="Interrupt on MR1"> + <Enum name="INTERRUPT_IS_GENERAT" start="1" description="Interrupt is generated when MR1 matches the value in the TC." /> + <Enum name="INTERRUPT_IS_DISABLE" start="0" description="Interrupt is disabled." /> + </BitField> + <BitField start="4" size="1" name="MR1R" description="Reset on MR1"> + <Enum name="TC_WILL_BE_RESET_IF_" start="1" description="TC will be reset if MR1 matches it." /> + <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." /> + </BitField> + <BitField start="5" size="1" name="MR1S" description="Stop on MR1"> + <Enum name="TC_AND_PC_WILL_BE_ST" start="1" description="TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC." /> + <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." /> + </BitField> + <BitField start="6" size="1" name="MR2I" description="Interrupt on MR2"> + <Enum name="INTERRUPT_IS_GENERAT" start="1" description="Interrupt is generated when MR2 matches the value in the TC." /> + <Enum name="INTERRUPT_IS_DISABLE" start="0" description="Interrupt is disabled" /> + </BitField> + <BitField start="7" size="1" name="MR2R" description="Reset on MR2"> + <Enum name="TC_WILL_BE_RESET_IF_" start="1" description="TC will be reset if MR2 matches it." /> + <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." /> + </BitField> + <BitField start="8" size="1" name="MR2S" description="Stop on MR2."> + <Enum name="TC_AND_PC_WILL_BE_ST" start="1" description="TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC" /> + <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." /> + </BitField> + <BitField start="9" size="1" name="MR3I" description="Interrupt on MR3"> + <Enum name="INTERRUPT_IS_GENERAT" start="1" description="Interrupt is generated when MR3 matches the value in the TC." /> + <Enum name="THIS_INTERRUPT_IS_DI" start="0" description="This interrupt is disabled" /> + </BitField> + <BitField start="10" size="1" name="MR3R" description="Reset on MR3"> + <Enum name="TC_WILL_BE_RESET_IF_" start="1" description="TC will be reset if MR3 matches it." /> + <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." /> + </BitField> + <BitField start="11" size="1" name="MR3S" description="Stop on MR3"> + <Enum name="TC_AND_PC_WILL_BE_ST" start="1" description="TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC." /> + <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." /> + </BitField> + <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x018+0" size="4" name="MR[0]" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="MATCH" description="Timer counter match value." /> + </Register> + <Register start="+0x018+4" size="4" name="MR[1]" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="MATCH" description="Timer counter match value." /> + </Register> + <Register start="+0x018+8" size="4" name="MR[2]" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="MATCH" description="Timer counter match value." /> + </Register> + <Register start="+0x018+12" size="4" name="MR[3]" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="MATCH" description="Timer counter match value." /> + </Register> + <Register start="+0x028" size="4" name="CCR" access="Read/Write" description="Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="CAP0RE" description="Capture on CAPn.0 rising edge"> + <Enum name="ENABLE" start="1" description="A sequence of 0 then 1 on CAPn.0 will cause CR0 to be loaded with the contents of TC." /> + <Enum name="DISABLE" start="0" description="This feature is disabled." /> + </BitField> + <BitField start="1" size="1" name="CAP0FE" description="Capture on CAPn.0 falling edge"> + <Enum name="ENABLE" start="1" description="A sequence of 1 then 0 on CAPn.0 will cause CR0 to be loaded with the contents of TC." /> + <Enum name="DISABLE" start="0" description="This feature is disabled." /> + </BitField> + <BitField start="2" size="1" name="CAP0I" description="Interrupt on CAPn.0 event"> + <Enum name="ENABLE" start="1" description="A CR0 load due to a CAPn.0 event will generate an interrupt." /> + <Enum name="DISABLE" start="0" description="This feature is disabled." /> + </BitField> + <BitField start="3" size="1" name="CAP1RE" description="Capture on CAPn.1 rising edge"> + <Enum name="ENABLE" start="1" description="A sequence of 0 then 1 on CAPn.1 will cause CR1 to be loaded with the contents of TC." /> + <Enum name="DISABLE" start="0" description="This feature is disabled." /> + </BitField> + <BitField start="4" size="1" name="CAP1FE" description="Capture on CAPn.1 falling edge"> + <Enum name="ENABLE" start="1" description="A sequence of 1 then 0 on CAPn.1 will cause CR1 to be loaded with the contents of TC." /> + <Enum name="DISABLE" start="0" description="This feature is disabled." /> + </BitField> + <BitField start="5" size="1" name="CAP1I" description="Interrupt on CAPn.1 event"> + <Enum name="ENABLE" start="1" description="A CR1 load due to a CAPn.1 event will generate an interrupt." /> + <Enum name="DISABLE" start="0" description="This feature is disabled." /> + </BitField> + <BitField start="6" size="26" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x02C+0" size="4" name="CR[0]" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CAP" description="Timer counter capture value." /> + </Register> + <Register start="+0x02C+4" size="4" name="CR[1]" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CAP" description="Timer counter capture value." /> + </Register> + <Register start="+0x03C" size="4" name="EMR" access="Read/Write" description="External Match Register. The EMR controls the external match pins." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="EM0" description="External Match 0. When a match occurs between the TC and MR0, this bit can either toggle, go low, go high, or do nothing, depending on bits 5:4 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." /> + <BitField start="1" size="1" name="EM1" description="External Match 1. When a match occurs between the TC and MR1, this bit can either toggle, go low, go high, or do nothing, depending on bits 7:6 of this register. This bit can be driven onto a MATn.1 pin, in a positive-logic manner (0 = low, 1 = high)." /> + <BitField start="2" size="1" name="EM2" description="External Match 2. When a match occurs between the TC and MR2, this bit can either toggle, go low, go high, or do nothing, depending on bits 9:8 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." /> + <BitField start="3" size="1" name="EM3" description="External Match 3. When a match occurs between the TC and MR3, this bit can either toggle, go low, go high, or do nothing, depending on bits 11:10 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." /> + <BitField start="4" size="2" name="EMC0" description="External Match Control 0. Determines the functionality of External Match 0."> + <Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." /> + <Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." /> + <Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." /> + <Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." /> + </BitField> + <BitField start="6" size="2" name="EMC1" description="External Match Control 1. Determines the functionality of External Match 1."> + <Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." /> + <Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." /> + <Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." /> + <Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." /> + </BitField> + <BitField start="8" size="2" name="EMC2" description="External Match Control 2. Determines the functionality of External Match 2."> + <Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." /> + <Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." /> + <Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." /> + <Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." /> + </BitField> + <BitField start="10" size="2" name="EMC3" description="External Match Control 3. Determines the functionality of External Match 3."> + <Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." /> + <Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." /> + <Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." /> + <Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." /> + </BitField> + <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x070" size="4" name="CTCR" access="Read/Write" description="Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="CTMODE" description="Counter/Timer Mode This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale Register."> + <Enum name="TIMER_MODE_EVERY_RI" start="0x0" description="Timer Mode: every rising PCLK edge" /> + <Enum name="RISING" start="0x1" description="Counter Mode: TC is incremented on rising edges on the CAP input selected by bits 3:2." /> + <Enum name="FALLING" start="0x2" description="Counter Mode: TC is incremented on falling edges on the CAP input selected by bits 3:2." /> + <Enum name="DUALEDGE" start="0x3" description="Counter Mode: TC is incremented on both edges on the CAP input selected by bits 3:2." /> + </BitField> + <BitField start="2" size="2" name="CINSEL" description="Count Input Select When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the TnCTCR, the 3 bits for that input in the Capture Control Register (TnCCR) must be programmed as 000. However, capture and/or interrupt can be selected for the other 3 CAPn inputs in the same timer."> + <Enum name="CAPN_0_FOR_TIMERN" start="0x0" description="CAPn.0 for TIMERn" /> + <Enum name="CAPN_1_FOR_TIMERN" start="0x1" description="CAPn.1 for TIMERn" /> + </BitField> + <BitField start="4" size="28" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + </RegisterGroup> + <RegisterGroup name="TIMER1" start="0x40008000" description=" Timer0/1/2/3 "> + <Register start="+0x000" size="4" name="IR" access="Read/Write" description="Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="MR0INT" description="Interrupt flag for match channel 0." /> + <BitField start="1" size="1" name="MR1INT" description="Interrupt flag for match channel 1." /> + <BitField start="2" size="1" name="MR2INT" description="Interrupt flag for match channel 2." /> + <BitField start="3" size="1" name="MR3INT" description="Interrupt flag for match channel 3." /> + <BitField start="4" size="1" name="CR0INT" description="Interrupt flag for capture channel 0 event." /> + <BitField start="5" size="1" name="CR1INT" description="Interrupt flag for capture channel 1 event." /> + <BitField start="6" size="26" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x004" size="4" name="TCR" access="Read/Write" description="Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="CEN" description="When one, the Timer Counter and Prescale Counter are enabled for counting. When zero, the counters are disabled." /> + <BitField start="1" size="1" name="CRST" description="When one, the Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero." /> + <BitField start="2" size="30" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x008" size="4" name="TC" access="Read/Write" description="Timer Counter. The 32 bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="TC" description="Timer counter value." /> + </Register> + <Register start="+0x00C" size="4" name="PR" access="Read/Write" description="Prescale Register. When the Prescale Counter (PC) is equal to this value, the next clock increments the TC and clears the PC." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="PM" description="Prescale counter maximum value." /> + </Register> + <Register start="+0x010" size="4" name="PC" access="Read/Write" description="Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="PC" description="Prescale counter value." /> + </Register> + <Register start="+0x014" size="4" name="MCR" access="Read/Write" description="Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="MR0I" description="Interrupt on MR0"> + <Enum name="INTERRUPT_IS_GENERAT" start="1" description="Interrupt is generated when MR0 matches the value in the TC." /> + <Enum name="INTERRUPT_IS_DISABLE" start="0" description="Interrupt is disabled" /> + </BitField> + <BitField start="1" size="1" name="MR0R" description="Reset on MR0"> + <Enum name="TC_WILL_BE_RESET_IF_" start="1" description="TC will be reset if MR0 matches it." /> + <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." /> + </BitField> + <BitField start="2" size="1" name="MR0S" description="Stop on MR0"> + <Enum name="TC_AND_PC_WILL_BE_ST" start="1" description="TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC." /> + <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." /> + </BitField> + <BitField start="3" size="1" name="MR1I" description="Interrupt on MR1"> + <Enum name="INTERRUPT_IS_GENERAT" start="1" description="Interrupt is generated when MR1 matches the value in the TC." /> + <Enum name="INTERRUPT_IS_DISABLE" start="0" description="Interrupt is disabled." /> + </BitField> + <BitField start="4" size="1" name="MR1R" description="Reset on MR1"> + <Enum name="TC_WILL_BE_RESET_IF_" start="1" description="TC will be reset if MR1 matches it." /> + <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." /> + </BitField> + <BitField start="5" size="1" name="MR1S" description="Stop on MR1"> + <Enum name="TC_AND_PC_WILL_BE_ST" start="1" description="TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC." /> + <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." /> + </BitField> + <BitField start="6" size="1" name="MR2I" description="Interrupt on MR2"> + <Enum name="INTERRUPT_IS_GENERAT" start="1" description="Interrupt is generated when MR2 matches the value in the TC." /> + <Enum name="INTERRUPT_IS_DISABLE" start="0" description="Interrupt is disabled" /> + </BitField> + <BitField start="7" size="1" name="MR2R" description="Reset on MR2"> + <Enum name="TC_WILL_BE_RESET_IF_" start="1" description="TC will be reset if MR2 matches it." /> + <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." /> + </BitField> + <BitField start="8" size="1" name="MR2S" description="Stop on MR2."> + <Enum name="TC_AND_PC_WILL_BE_ST" start="1" description="TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC" /> + <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." /> + </BitField> + <BitField start="9" size="1" name="MR3I" description="Interrupt on MR3"> + <Enum name="INTERRUPT_IS_GENERAT" start="1" description="Interrupt is generated when MR3 matches the value in the TC." /> + <Enum name="THIS_INTERRUPT_IS_DI" start="0" description="This interrupt is disabled" /> + </BitField> + <BitField start="10" size="1" name="MR3R" description="Reset on MR3"> + <Enum name="TC_WILL_BE_RESET_IF_" start="1" description="TC will be reset if MR3 matches it." /> + <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." /> + </BitField> + <BitField start="11" size="1" name="MR3S" description="Stop on MR3"> + <Enum name="TC_AND_PC_WILL_BE_ST" start="1" description="TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC." /> + <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." /> + </BitField> + <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x018+0" size="4" name="MR[0]" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="MATCH" description="Timer counter match value." /> + </Register> + <Register start="+0x018+4" size="4" name="MR[1]" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="MATCH" description="Timer counter match value." /> + </Register> + <Register start="+0x018+8" size="4" name="MR[2]" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="MATCH" description="Timer counter match value." /> + </Register> + <Register start="+0x018+12" size="4" name="MR[3]" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="MATCH" description="Timer counter match value." /> + </Register> + <Register start="+0x028" size="4" name="CCR" access="Read/Write" description="Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="CAP0RE" description="Capture on CAPn.0 rising edge"> + <Enum name="ENABLE" start="1" description="A sequence of 0 then 1 on CAPn.0 will cause CR0 to be loaded with the contents of TC." /> + <Enum name="DISABLE" start="0" description="This feature is disabled." /> + </BitField> + <BitField start="1" size="1" name="CAP0FE" description="Capture on CAPn.0 falling edge"> + <Enum name="ENABLE" start="1" description="A sequence of 1 then 0 on CAPn.0 will cause CR0 to be loaded with the contents of TC." /> + <Enum name="DISABLE" start="0" description="This feature is disabled." /> + </BitField> + <BitField start="2" size="1" name="CAP0I" description="Interrupt on CAPn.0 event"> + <Enum name="ENABLE" start="1" description="A CR0 load due to a CAPn.0 event will generate an interrupt." /> + <Enum name="DISABLE" start="0" description="This feature is disabled." /> + </BitField> + <BitField start="3" size="1" name="CAP1RE" description="Capture on CAPn.1 rising edge"> + <Enum name="ENABLE" start="1" description="A sequence of 0 then 1 on CAPn.1 will cause CR1 to be loaded with the contents of TC." /> + <Enum name="DISABLE" start="0" description="This feature is disabled." /> + </BitField> + <BitField start="4" size="1" name="CAP1FE" description="Capture on CAPn.1 falling edge"> + <Enum name="ENABLE" start="1" description="A sequence of 1 then 0 on CAPn.1 will cause CR1 to be loaded with the contents of TC." /> + <Enum name="DISABLE" start="0" description="This feature is disabled." /> + </BitField> + <BitField start="5" size="1" name="CAP1I" description="Interrupt on CAPn.1 event"> + <Enum name="ENABLE" start="1" description="A CR1 load due to a CAPn.1 event will generate an interrupt." /> + <Enum name="DISABLE" start="0" description="This feature is disabled." /> + </BitField> + <BitField start="6" size="26" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x02C+0" size="4" name="CR[0]" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CAP" description="Timer counter capture value." /> + </Register> + <Register start="+0x02C+4" size="4" name="CR[1]" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CAP" description="Timer counter capture value." /> + </Register> + <Register start="+0x03C" size="4" name="EMR" access="Read/Write" description="External Match Register. The EMR controls the external match pins." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="EM0" description="External Match 0. When a match occurs between the TC and MR0, this bit can either toggle, go low, go high, or do nothing, depending on bits 5:4 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." /> + <BitField start="1" size="1" name="EM1" description="External Match 1. When a match occurs between the TC and MR1, this bit can either toggle, go low, go high, or do nothing, depending on bits 7:6 of this register. This bit can be driven onto a MATn.1 pin, in a positive-logic manner (0 = low, 1 = high)." /> + <BitField start="2" size="1" name="EM2" description="External Match 2. When a match occurs between the TC and MR2, this bit can either toggle, go low, go high, or do nothing, depending on bits 9:8 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." /> + <BitField start="3" size="1" name="EM3" description="External Match 3. When a match occurs between the TC and MR3, this bit can either toggle, go low, go high, or do nothing, depending on bits 11:10 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." /> + <BitField start="4" size="2" name="EMC0" description="External Match Control 0. Determines the functionality of External Match 0."> + <Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." /> + <Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." /> + <Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." /> + <Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." /> + </BitField> + <BitField start="6" size="2" name="EMC1" description="External Match Control 1. Determines the functionality of External Match 1."> + <Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." /> + <Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." /> + <Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." /> + <Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." /> + </BitField> + <BitField start="8" size="2" name="EMC2" description="External Match Control 2. Determines the functionality of External Match 2."> + <Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." /> + <Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." /> + <Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." /> + <Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." /> + </BitField> + <BitField start="10" size="2" name="EMC3" description="External Match Control 3. Determines the functionality of External Match 3."> + <Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." /> + <Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." /> + <Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." /> + <Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." /> + </BitField> + <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x070" size="4" name="CTCR" access="Read/Write" description="Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="CTMODE" description="Counter/Timer Mode This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale Register."> + <Enum name="TIMER_MODE_EVERY_RI" start="0x0" description="Timer Mode: every rising PCLK edge" /> + <Enum name="RISING" start="0x1" description="Counter Mode: TC is incremented on rising edges on the CAP input selected by bits 3:2." /> + <Enum name="FALLING" start="0x2" description="Counter Mode: TC is incremented on falling edges on the CAP input selected by bits 3:2." /> + <Enum name="DUALEDGE" start="0x3" description="Counter Mode: TC is incremented on both edges on the CAP input selected by bits 3:2." /> + </BitField> + <BitField start="2" size="2" name="CINSEL" description="Count Input Select When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the TnCTCR, the 3 bits for that input in the Capture Control Register (TnCCR) must be programmed as 000. However, capture and/or interrupt can be selected for the other 3 CAPn inputs in the same timer."> + <Enum name="CAPN_0_FOR_TIMERN" start="0x0" description="CAPn.0 for TIMERn" /> + <Enum name="CAPN_1_FOR_TIMERN" start="0x1" description="CAPn.1 for TIMERn" /> + </BitField> + <BitField start="4" size="28" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + </RegisterGroup> + <RegisterGroup name="UART0" start="0x4000C000" description="UART0/2/3 "> + <Register start="+0x000" size="4" name="RBR" access="None" description="Receiver Buffer Register. Contains the next received character to be read (DLAB =0)." reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="8" name="RBR" description="The UARTn Receiver Buffer Register contains the oldest received byte in the UARTn Rx FIFO." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x000" size="4" name="THR" access="WriteOnly" description="Transmit Holding Regiter. The next character to be transmitted is written here (DLAB =0)." reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="8" name="THR" description="Writing to the UARTn Transmit Holding Register causes the data to be stored in the UARTn transmit FIFO. The byte will be sent when it reaches the bottom of the FIFO and the transmitter is available." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x000" size="4" name="DLL" access="Read/Write" description="Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB =1)." reset_value="0x01" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="DLLSB" description="The UARTn Divisor Latch LSB Register, along with the UnDLM register, determines the baud rate of the UARTn." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x004" size="4" name="DLM" access="Read/Write" description="Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB =1)." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="DLMSB" description="The UARTn Divisor Latch MSB Register, along with the U0DLL register, determines the baud rate of the UARTn." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x004" size="4" name="IER" access="Read/Write" description="Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential UART interrupts (DLAB =0)." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RBRIE" description="RBR Interrupt Enable. Enables the Receive Data Available interrupt for UARTn. It also controls the Character Receive Time-out interrupt."> + <Enum name="DISABLE_THE_RDA_INTE" start="0" description="Disable the RDA interrupts." /> + <Enum name="ENABLE_THE_RDA_INTER" start="1" description="Enable the RDA interrupts." /> + </BitField> + <BitField start="1" size="1" name="THREIE" description="THRE Interrupt Enable. Enables the THRE interrupt for UARTn. The status of this can be read from UnLSR[5]."> + <Enum name="DISABLE_THE_THRE_INT" start="0" description="Disable the THRE interrupts." /> + <Enum name="ENABLE_THE_THRE_INTE" start="1" description="Enable the THRE interrupts." /> + </BitField> + <BitField start="2" size="1" name="RXIE" description="RX Line Status Interrupt Enable. Enables the UARTn RX line status interrupts. The status of this interrupt can be read from UnLSR[4:1]."> + <Enum name="DISABLE_THE_RX_LINE_" start="0" description="Disable the RX line status interrupts." /> + <Enum name="ENABLE_THE_RX_LINE_S" start="1" description="Enable the RX line status interrupts." /> + </BitField> + <BitField start="3" size="5" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="8" size="1" name="ABEOINTEN" description="Enables the end of auto-baud interrupt."> + <Enum name="DISABLE_END_OF_AUTO_" start="0" description="Disable end of auto-baud Interrupt." /> + <Enum name="ENABLE_END_OF_AUTO_B" start="1" description="Enable end of auto-baud Interrupt." /> + </BitField> + <BitField start="9" size="1" name="ABTOINTEN" description="Enables the auto-baud time-out interrupt."> + <Enum name="DISABLE_AUTO_BAUD_TI" start="0" description="Disable auto-baud time-out Interrupt." /> + <Enum name="ENABLE_AUTO_BAUD_TIM" start="1" description="Enable auto-baud time-out Interrupt." /> + </BitField> + <BitField start="10" size="22" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x008" size="4" name="IIR" access="ReadOnly" description="Interrupt ID Register. Identifies which interrupt(s) are pending." reset_value="0x01" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="INTSTATUS" description="Interrupt status. Note that UnIIR[0] is active low. The pending interrupt can be determined by evaluating UnIIR[3:1]."> + <Enum name="AT_LEAST_ONE_INTERRU" start="0" description="At least one interrupt is pending." /> + <Enum name="NO_INTERRUPT_IS_PEND" start="1" description="No interrupt is pending." /> + </BitField> + <BitField start="1" size="3" name="INTID" description="Interrupt identification. UnIER[3:1] identifies an interrupt corresponding to the UARTn Rx or TX FIFO. All other combinations of UnIER[3:1] not listed below are reserved (000,100,101,111)."> + <Enum name="1_RECEIVE_LINE_S" start="0x3" description="1 - Receive Line Status (RLS)." /> + <Enum name="2A__RECEIVE_DATA_AV" start="0x2" description="2a - Receive Data Available (RDA)." /> + <Enum name="2B__CHARACTER_TIME_" start="0x6" description="2b - Character Time-out Indicator (CTI)." /> + <Enum name="3_THRE_INTERRUPT" start="0x1" description="3 - THRE Interrupt" /> + </BitField> + <BitField start="4" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="6" size="2" name="FIFOENABLE" description="Copies of UnFCR[0]." /> + <BitField start="8" size="1" name="ABEOINT" description="End of auto-baud interrupt. True if auto-baud has finished successfully and interrupt is enabled." /> + <BitField start="9" size="1" name="ABTOINT" description="Auto-baud time-out interrupt. True if auto-baud has timed out and interrupt is enabled." /> + <BitField start="10" size="22" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x008" size="4" name="FCR" access="WriteOnly" description="FIFO Control Register. Controls UART FIFO usage and modes." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="FIFOEN" description="FIFO Enable."> + <Enum name="UARTN_FIFOS_ARE_DISA" start="0" description="UARTn FIFOs are disabled. Must not be used in the application." /> + <Enum name="ACTIVE_HIGH_ENABLE_F" start="1" description="Active high enable for both UARTn Rx and TX FIFOs and UnFCR[7:1] access. This bit must be set for proper UART operation. Any transition on this bit will automatically clear the related UART FIFOs." /> + </BitField> + <BitField start="1" size="1" name="RXFIFORES" description="RX FIFO Reset."> + <Enum name="NO_IMPACT_ON_EITHER_" start="0" description="No impact on either of UARTn FIFOs." /> + <Enum name="WRITING_A_LOGIC_1_TO" start="1" description="Writing a logic 1 to UnFCR[1] will clear all bytes in UARTn Rx FIFO, reset the pointer logic. This bit is self-clearing." /> + </BitField> + <BitField start="2" size="1" name="TXFIFORES" description="TX FIFO Reset."> + <Enum name="NO_IMPACT_ON_EITHER_" start="0" description="No impact on either of UARTn FIFOs." /> + <Enum name="WRITING_A_LOGIC_1_TO" start="1" description="Writing a logic 1 to UnFCR[2] will clear all bytes in UARTn TX FIFO, reset the pointer logic. This bit is self-clearing." /> + </BitField> + <BitField start="3" size="1" name="DMAMODE" description="DMA Mode Select. When the FIFO enable (bit 0 of this register) is set, this bit selects the DMA mode. See Section 18.6.6.1." /> + <BitField start="4" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="6" size="2" name="RXTRIGLVL" description="RX Trigger Level. These two bits determine how many receiver UARTn FIFO characters must be written before an interrupt or DMA request is activated."> + <Enum name="TRIGGER_LEVEL_0_1_C" start="0x0" description="Trigger level 0 (1 character or 0x01)." /> + <Enum name="TRIGGER_LEVEL_1_4_C" start="0x1" description="Trigger level 1 (4 characters or 0x04)." /> + <Enum name="TRIGGER_LEVEL_2_8_C" start="0x2" description="Trigger level 2 (8 characters or 0x08)." /> + <Enum name="TRIGGER_LEVEL_3_14_" start="0x3" description="Trigger level 3 (14 characters or 0x0E)." /> + </BitField> + <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x00C" size="4" name="LCR" access="Read/Write" description="Line Control Register. Contains controls for frame formatting and break generation." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="WLS" description="Word Length Select."> + <Enum name="5_BIT_CHARACTER_LENG" start="0x0" description="5-bit character length" /> + <Enum name="6_BIT_CHARACTER_LENG" start="0x1" description="6-bit character length" /> + <Enum name="7_BIT_CHARACTER_LENG" start="0x2" description="7-bit character length" /> + <Enum name="8_BIT_CHARACTER_LENG" start="0x3" description="8-bit character length" /> + </BitField> + <BitField start="2" size="1" name="SBS" description="Stop Bit Select"> + <Enum name="1_STOP_BIT_" start="0" description="1 stop bit." /> + <Enum name="2_STOP_BITS_1_5_IF_" start="1" description="2 stop bits (1.5 if UnLCR[1:0]=00)." /> + </BitField> + <BitField start="3" size="1" name="PE" description="Parity Enable."> + <Enum name="DISABLE_PARITY_GENER" start="0" description="Disable parity generation and checking." /> + <Enum name="ENABLE_PARITY_GENERA" start="1" description="Enable parity generation and checking." /> + </BitField> + <BitField start="4" size="2" name="PS" description="Parity Select"> + <Enum name="ODD_PARITY_NUMBER_O" start="0x0" description="Odd parity. Number of 1s in the transmitted character and the attached parity bit will be odd." /> + <Enum name="EVEN_PARITY_NUMBER_" start="0x1" description="Even Parity. Number of 1s in the transmitted character and the attached parity bit will be even." /> + <Enum name="FORCED_1_STICK_PARIT" start="0x2" description="Forced 1 stick parity." /> + <Enum name="FORCED_0_STICK_PARIT" start="0x3" description="Forced 0 stick parity." /> + </BitField> + <BitField start="6" size="1" name="BC" description="Break Control"> + <Enum name="DISABLE_BREAK_TRANSM" start="0" description="Disable break transmission." /> + <Enum name="ENABLE_BREAK_TRANSMI" start="1" description="Enable break transmission. Output pin UARTn TXD is forced to logic 0 when UnLCR[6] is active high." /> + </BitField> + <BitField start="7" size="1" name="DLAB" description="Divisor Latch Access Bit"> + <Enum name="DISABLE_ACCESS_TO_DI" start="0" description="Disable access to Divisor Latches." /> + <Enum name="ENABLE_ACCESS_TO_DIV" start="1" description="Enable access to Divisor Latches." /> + </BitField> + <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x014" size="4" name="LSR" access="None" description="Line Status Register. Contains flags for transmit and receive status, including line errors." reset_value="0x60" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RDR" description="Receiver Data Ready. UnLSR[0] is set when the UnRBR holds an unread character and is cleared when the UARTn RBR FIFO is empty."> + <Enum name="EMPTY" start="0" description="The UARTn receiver FIFO is empty." /> + <Enum name="NOTEMPTY" start="1" description="The UARTn receiver FIFO is not empty." /> + </BitField> + <BitField start="1" size="1" name="OE" description="Overrun Error. The overrun error condition is set as soon as it occurs. An UnLSR read clears UnLSR[1]. UnLSR[1] is set when UARTn RSR has a new character assembled and the UARTn RBR FIFO is full. In this case, the UARTn RBR FIFO will not be overwritten and the character in the UARTn RSR will be lost."> + <Enum name="INACTIVE" start="0" description="Overrun error status is inactive." /> + <Enum name="ACTIVE" start="1" description="Overrun error status is active." /> + </BitField> + <BitField start="2" size="1" name="PE" description="Parity Error. When the parity bit of a received character is in the wrong state, a parity error occurs. An UnLSR read clears UnLSR[2]. Time of parity error detection is dependent on UnFCR[0]. Note: A parity error is associated with the character at the top of the UARTn RBR FIFO."> + <Enum name="INACTIVE" start="0" description="Parity error status is inactive." /> + <Enum name="ACTIVE" start="1" description="Parity error status is active." /> + </BitField> + <BitField start="3" size="1" name="FE" description="Framing Error. When the stop bit of a received character is a logic 0, a framing error occurs. An UnLSR read clears UnLSR[3]. The time of the framing error detection is dependent on UnFCR[0]. Upon detection of a framing error, the Rx will attempt to resynchronize to the data and assume that the bad stop bit is actually an early start bit. However, it cannot be assumed that the next received byte will be correct even if there is no Framing Error. Note: A framing error is associated with the character at the top of the UARTn RBR FIFO."> + <Enum name="INACTIVE" start="0" description="Framing error status is inactive." /> + <Enum name="ACTIVE" start="1" description="Framing error status is active." /> + </BitField> + <BitField start="4" size="1" name="BI" description="Break Interrupt. When RXDn is held in the spacing state (all zeroes) for one full character transmission (start, data, parity, stop), a break interrupt occurs. Once the break condition has been detected, the receiver goes idle until RXDn goes to marking state (all ones). An UnLSR read clears this status bit. The time of break detection is dependent on UnFCR[0]. Note: The break interrupt is associated with the character at the top of the UARTn RBR FIFO."> + <Enum name="INACTIVE" start="0" description="Break interrupt status is inactive." /> + <Enum name="ACTIVE" start="1" description="Break interrupt status is active." /> + </BitField> + <BitField start="5" size="1" name="THRE" description="Transmitter Holding Register Empty. THRE is set immediately upon detection of an empty UARTn THR and is cleared on a UnTHR write."> + <Enum name="VALIDDATA" start="0" description="UnTHR contains valid data." /> + <Enum name="EMPTY" start="1" description="UnTHR is empty." /> + </BitField> + <BitField start="6" size="1" name="TEMT" description="Transmitter Empty. TEMT is set when both UnTHR and UnTSR are empty; TEMT is cleared when either the UnTSR or the UnTHR contain valid data."> + <Enum name="VALIDDATA" start="0" description="UnTHR and/or the UnTSR contains valid data." /> + <Enum name="EMPTY" start="1" description="UnTHR and the UnTSR are empty." /> + </BitField> + <BitField start="7" size="1" name="RXFE" description="Error in RX FIFO . UnLSR[7] is set when a character with a Rx error such as framing error, parity error or break interrupt, is loaded into the UnRBR. This bit is cleared when the UnLSR register is read and there are no subsequent errors in the UARTn FIFO."> + <Enum name="NOERROR" start="0" description="UnRBR contains no UARTn RX errors or UnFCR[0]=0." /> + <Enum name="ERRORS" start="1" description="UARTn RBR contains at least one UARTn RX error." /> + </BitField> + <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x01C" size="4" name="SCR" access="Read/Write" description="Scratch Pad Register. 8-bit temporary storage for software." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="PAD" description="A readable, writable byte." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x020" size="4" name="ACR" access="Read/Write" description="Auto-baud Control Register. Contains controls for the auto-baud feature." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="START" description="Start bit. This bit is automatically cleared after auto-baud completion."> + <Enum name="AUTO_BAUD_STOP_AUTO" start="0" description="Auto-baud stop (auto-baud is not running)." /> + <Enum name="AUTO_BAUD_START_AUT" start="1" description="Auto-baud start (auto-baud is running). Auto-baud run bit. This bit is automatically cleared after auto-baud completion." /> + </BitField> + <BitField start="1" size="1" name="MODE" description="Auto-baud mode select bit."> + <Enum name="MODE_0_" start="0" description="Mode 0." /> + <Enum name="MODE_1_" start="1" description="Mode 1." /> + </BitField> + <BitField start="2" size="1" name="AUTORESTART" description="Restart bit."> + <Enum name="NO_RESTART_" start="0" description="No restart." /> + <Enum name="RESTART_IN_CASE_OF_T" start="1" description="Restart in case of time-out (counter restarts at next UARTn Rx falling edge)" /> + </BitField> + <BitField start="3" size="5" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="8" size="1" name="ABEOINTCLR" description="End of auto-baud interrupt clear bit (write-only accessible). Writing a 1 will clear the corresponding interrupt in the UnIIR. Writing a 0 has no impact."> + <Enum name="NO_IMPACT_" start="0" description="No impact." /> + <Enum name="CLEAR_THE_CORRESPOND" start="1" description="Clear the corresponding interrupt in the IIR." /> + </BitField> + <BitField start="9" size="1" name="ABTOINTCLR" description="Auto-baud time-out interrupt clear bit (write-only accessible). Writing a 1 will clear the corresponding interrupt in the UnIIR. Writing a 0 has no impact."> + <Enum name="NO_IMPACT_" start="0" description="No impact." /> + <Enum name="CLEAR_THE_CORRESPOND" start="1" description="Clear the corresponding interrupt in the IIR." /> + </BitField> + <BitField start="10" size="22" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x028" size="4" name="FDR" access="Read/Write" description="Fractional Divider Register. Generates a clock input for the baud rate divider." reset_value="0x10" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="4" name="DIVADDVAL" description="Baud-rate generation pre-scaler divisor value. If this field is 0, fractional baud-rate generator will not impact the UARTn baudrate." /> + <BitField start="4" size="4" name="MULVAL" description="Baud-rate pre-scaler multiplier value. This field must be greater or equal 1 for UARTn to operate properly, regardless of whether the fractional baud-rate generator is used or not." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x030" size="4" name="TER" access="Read/Write" description="Transmit Enable Register. Turns off UART transmitter for use with software flow control." reset_value="0x80" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="7" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="7" size="1" name="TXEN" description="When this bit is 1, as it is after a Reset, data written to the THR is output on the TXD pin as soon as any preceding data has been sent. If this bit is cleared to 0 while a character is being sent, the transmission of that character is completed, but no further characters are sent until this bit is set again. In other words, a 0 in this bit blocks the transfer of characters from the THR or TX FIFO into the transmit shift register. Software implementing software-handshaking can clear this bit when it receives an XOFF character (DC3). Software can set this bit again when it receives an XON (DC1) character." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x04C" size="4" name="RS485CTRL" access="Read/Write" description="RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="NMMEN" description="NMM enable."> + <Enum name="DISABLED" start="0" description="RS-485/EIA-485 Normal Multidrop Mode (NMM) is disabled." /> + <Enum name="ENABLED" start="1" description="RS-485/EIA-485 Normal Multidrop Mode (NMM) is enabled. In this mode, an address is detected when a received byte has the parity bit = 1, generating a received data interrupt. See Section 18.6.16 RS-485/EIA-485 modes of operation." /> + </BitField> + <BitField start="1" size="1" name="RXDIS" description="Receiver enable."> + <Enum name="ENABLED" start="0" description="The receiver is enabled." /> + <Enum name="DISABLED" start="1" description="The receiver is disabled." /> + </BitField> + <BitField start="2" size="1" name="AADEN" description="AAD enable."> + <Enum name="DISABLED" start="0" description="Auto Address Detect (AAD) is disabled." /> + <Enum name="ENABLED" start="1" description="Auto Address Detect (AAD) is enabled." /> + </BitField> + <BitField start="3" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="4" size="1" name="DCTRL" description="Direction control enable."> + <Enum name="DISABLE_AUTO_DIRECTI" start="0" description="Disable Auto Direction Control." /> + <Enum name="ENABLE_AUTO_DIRECTIO" start="1" description="Enable Auto Direction Control." /> + </BitField> + <BitField start="5" size="1" name="OINV" description="Direction control pin polarity. This bit reverses the polarity of the direction control signal on the Un_OE pin."> + <Enum name="DIRLOW" start="0" description="The direction control pin will be driven to logic 0 when the transmitter has data to be sent. It will be driven to logic 1 after the last bit of data has been transmitted." /> + <Enum name="DIRHIGH" start="1" description="The direction control pin will be driven to logic 1 when the transmitter has data to be sent. It will be driven to logic 0 after the last bit of data has been transmitted." /> + </BitField> + <BitField start="6" size="26" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x050" size="4" name="RS485ADRMATCH" access="Read/Write" description="RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="ADRMATCH" description="Contains the address match value." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x054" size="4" name="RS485DLY" access="Read/Write" description="RS-485/EIA-485 direction control delay." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="DLY" description="Contains the direction control (UnOE) delay value. This register works in conjunction with an 8-bit counter." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + </RegisterGroup> + <RegisterGroup name="UART1" start="0x40010000" description="UART1"> + <Register start="+0x000" size="4" name="RBR" access="None" description="DLAB =0 Receiver Buffer Register. Contains the next received character to be read." reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="8" name="RBR" description="The UART1 Receiver Buffer Register contains the oldest received byte in the UART1 RX FIFO." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x000" size="4" name="THR" access="WriteOnly" description="DLAB =0. Transmit Holding Register. The next character to be transmitted is written here." reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="8" name="THR" description="Writing to the UART1 Transmit Holding Register causes the data to be stored in the UART1 transmit FIFO. The byte will be sent when it reaches the bottom of the FIFO and the transmitter is available." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x000" size="4" name="DLL" access="Read/Write" description="DLAB =1. Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider." reset_value="0x01" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="DLLSB" description="The UART1 Divisor Latch LSB Register, along with the U1DLM register, determines the baud rate of the UART1." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x004" size="4" name="DLM" access="Read/Write" description="DLAB =1. Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="DLMSB" description="The UART1 Divisor Latch MSB Register, along with the U1DLL register, determines the baud rate of the UART1." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x004" size="4" name="IER" access="Read/Write" description="DLAB =0. Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential UART1 interrupts." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RBRIE" description="RBR Interrupt Enable. Enables the Receive Data Available interrupt for UART1. It also controls the Character Receive Time-out interrupt."> + <Enum name="DISABLE_THE_RDA_INTE" start="0" description="Disable the RDA interrupts." /> + <Enum name="ENABLE_THE_RDA_INTER" start="1" description="Enable the RDA interrupts." /> + </BitField> + <BitField start="1" size="1" name="THREIE" description="THRE Interrupt Enable. Enables the THRE interrupt for UART1. The status of this interrupt can be read from LSR[5]."> + <Enum name="DISABLE_THE_THRE_INT" start="0" description="Disable the THRE interrupts." /> + <Enum name="ENABLE_THE_THRE_INTE" start="1" description="Enable the THRE interrupts." /> + </BitField> + <BitField start="2" size="1" name="RXIE" description="RX Line Interrupt Enable. Enables the UART1 RX line status interrupts. The status of this interrupt can be read from LSR[4:1]."> + <Enum name="DISABLE_THE_RX_LINE_" start="0" description="Disable the RX line status interrupts." /> + <Enum name="ENABLE_THE_RX_LINE_S" start="1" description="Enable the RX line status interrupts." /> + </BitField> + <BitField start="3" size="1" name="MSIE" description="Modem Status Interrupt Enable. Enables the modem interrupt. The status of this interrupt can be read from MSR[3:0]."> + <Enum name="DISABLE_THE_MODEM_IN" start="0" description="Disable the modem interrupt." /> + <Enum name="ENABLE_THE_MODEM_INT" start="1" description="Enable the modem interrupt." /> + </BitField> + <BitField start="4" size="3" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + <BitField start="7" size="1" name="CTSIE" description="CTS Interrupt Enable. If auto-cts mode is enabled this bit enables/disables the modem status interrupt generation on a CTS1 signal transition. If auto-cts mode is disabled a CTS1 transition will generate an interrupt if Modem Status Interrupt Enable (IER[3]) is set. In normal operation a CTS1 signal transition will generate a Modem Status Interrupt unless the interrupt has been disabled by clearing the IER[3] bit in the IER register. In auto-cts mode a transition on the CTS1 bit will trigger an interrupt only if both the IER[3] and IER[7] bits are set."> + <Enum name="DISABLE_THE_CTS_INTE" start="0" description="Disable the CTS interrupt." /> + <Enum name="ENABLE_THE_CTS_INTER" start="1" description="Enable the CTS interrupt." /> + </BitField> + <BitField start="8" size="1" name="ABEOIE" description="Enables the end of auto-baud interrupt."> + <Enum name="DISABLE_END_OF_AUTO_" start="0" description="Disable end of auto-baud Interrupt." /> + <Enum name="ENABLE_END_OF_AUTO_B" start="1" description="Enable end of auto-baud Interrupt." /> + </BitField> + <BitField start="9" size="1" name="ABTOIE" description="Enables the auto-baud time-out interrupt."> + <Enum name="DISABLE_AUTO_BAUD_TI" start="0" description="Disable auto-baud time-out Interrupt." /> + <Enum name="ENABLE_AUTO_BAUD_TIM" start="1" description="Enable auto-baud time-out Interrupt." /> + </BitField> + <BitField start="10" size="22" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x008" size="4" name="IIR" access="ReadOnly" description="Interrupt ID Register. Identifies which interrupt(s) are pending." reset_value="0x01" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="INTSTATUS" description="Interrupt status. Note that IIR[0] is active low. The pending interrupt can be determined by evaluating IIR[3:1]."> + <Enum name="AT_LEAST_ONE_INTERRU" start="0" description="At least one interrupt is pending." /> + <Enum name="NO_INTERRUPT_IS_PEND" start="1" description="No interrupt is pending." /> + </BitField> + <BitField start="1" size="3" name="INTID" description="Interrupt identification. IER[3:1] identifies an interrupt corresponding to the UART1 Rx or TX FIFO. All other combinations of IER[3:1] not listed below are reserved (100,101,111)."> + <Enum name="RLS" start="0x3" description="1 - Receive Line Status (RLS)." /> + <Enum name="RDA" start="0x2" description="2a - Receive Data Available (RDA)." /> + <Enum name="CTI" start="0x6" description="2b - Character Time-out Indicator (CTI)." /> + <Enum name="THRE" start="0x1" description="3 - THRE Interrupt." /> + <Enum name="MODEM" start="0x0" description="4 - Modem Interrupt." /> + </BitField> + <BitField start="4" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + <BitField start="6" size="2" name="FIFOENABLE" description="Copies of FCR[0]." /> + <BitField start="8" size="1" name="ABEOINT" description="End of auto-baud interrupt. True if auto-baud has finished successfully and interrupt is enabled." /> + <BitField start="9" size="1" name="ABTOINT" description="Auto-baud time-out interrupt. True if auto-baud has timed out and interrupt is enabled." /> + <BitField start="10" size="22" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x008" size="4" name="FCR" access="WriteOnly" description="FIFO Control Register. Controls UART1 FIFO usage and modes." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="FIFOEN" description="FIFO enable."> + <Enum name="MUST_NOT_BE_USED_IN_" start="0" description="Must not be used in the application." /> + <Enum name="ACTIVE_HIGH_ENABLE_F" start="1" description="Active high enable for both UART1 Rx and TX FIFOs and FCR[7:1] access. This bit must be set for proper UART1 operation. Any transition on this bit will automatically clear the UART1 FIFOs." /> + </BitField> + <BitField start="1" size="1" name="RXFIFORES" description="RX FIFO Reset."> + <Enum name="NO_IMPACT_ON_EITHER_" start="0" description="No impact on either of UART1 FIFOs." /> + <Enum name="WRITING_A_LOGIC_1_TO" start="1" description="Writing a logic 1 to FCR[1] will clear all bytes in UART1 Rx FIFO, reset the pointer logic. This bit is self-clearing." /> + </BitField> + <BitField start="2" size="1" name="TXFIFORES" description="TX FIFO Reset."> + <Enum name="NO_IMPACT_ON_EITHER_" start="0" description="No impact on either of UART1 FIFOs." /> + <Enum name="WRITING_A_LOGIC_1_TO" start="1" description="Writing a logic 1 to FCR[2] will clear all bytes in UART1 TX FIFO, reset the pointer logic. This bit is self-clearing." /> + </BitField> + <BitField start="3" size="1" name="DMAMODE" description="DMA Mode Select. When the FIFO enable bit (bit 0 of this register) is set, this bit selects the DMA mode. See Section 36.6.6.1." /> + <BitField start="4" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + <BitField start="6" size="2" name="RXTRIGLVL" description="RX Trigger Level. These two bits determine how many receiver UART1 FIFO characters must be written before an interrupt is activated."> + <Enum name="TRIGGER_LEVEL_0_1_C" start="0x0" description="Trigger level 0 (1 character or 0x01)." /> + <Enum name="TRIGGER_LEVEL_1_4_C" start="0x1" description="Trigger level 1 (4 characters or 0x04)." /> + <Enum name="TRIGGER_LEVEL_2_8_C" start="0x2" description="Trigger level 2 (8 characters or 0x08)." /> + <Enum name="TRIGGER_LEVEL_3_14_" start="0x3" description="Trigger level 3 (14 characters or 0x0E)." /> + </BitField> + <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits." /> + </Register> + <Register start="+0x00C" size="4" name="LCR" access="Read/Write" description="Line Control Register. Contains controls for frame formatting and break generation." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="WLS" description="Word Length Select."> + <Enum name="5_BIT_CHARACTER_LENG" start="0x0" description="5-bit character length." /> + <Enum name="6_BIT_CHARACTER_LENG" start="0x1" description="6-bit character length." /> + <Enum name="7_BIT_CHARACTER_LENG" start="0x2" description="7-bit character length." /> + <Enum name="8_BIT_CHARACTER_LENG" start="0x3" description="8-bit character length." /> + </BitField> + <BitField start="2" size="1" name="SBS" description="Stop Bit Select."> + <Enum name="1_STOP_BIT_" start="0" description="1 stop bit." /> + <Enum name="2_STOP_BITS_1_5_IF_" start="1" description="2 stop bits (1.5 if LCR[1:0]=00)." /> + </BitField> + <BitField start="3" size="1" name="PE" description="Parity Enable."> + <Enum name="DISABLE_PARITY_GENER" start="0" description="Disable parity generation and checking." /> + <Enum name="ENABLE_PARITY_GENERA" start="1" description="Enable parity generation and checking." /> + </BitField> + <BitField start="4" size="2" name="PS" description="Parity Select."> + <Enum name="ODD_PARITY_NUMBER_O" start="0x0" description="Odd parity. Number of 1s in the transmitted character and the attached parity bit will be odd." /> + <Enum name="EVEN_PARITY_NUMBER_" start="0x1" description="Even Parity. Number of 1s in the transmitted character and the attached parity bit will be even." /> + <Enum name="FORCED1STICK_PAR" start="0x2" description="Forced 1 stick parity." /> + <Enum name="FORCED0STICK_PAR" start="0x3" description="Forced 0 stick parity." /> + </BitField> + <BitField start="6" size="1" name="BC" description="Break Control."> + <Enum name="DISABLE_BREAK_TRANSM" start="0" description="Disable break transmission." /> + <Enum name="ENABLE_BREAK_TRANSMI" start="1" description="Enable break transmission. Output pin UART1 TXD is forced to logic 0 when LCR[6] is active high." /> + </BitField> + <BitField start="7" size="1" name="DLAB" description="Divisor Latch Access Bit (DLAB)"> + <Enum name="DISABLE_ACCESS_TO_DI" start="0" description="Disable access to Divisor Latches." /> + <Enum name="ENABLE_ACCESS_TO_DIV" start="1" description="Enable access to Divisor Latches." /> + </BitField> + <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x010" size="4" name="MCR" access="Read/Write" description="Modem Control Register. Contains controls for flow control handshaking and loopback mode." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="DTRCTRL" description="DTR Control. Source for modem output pin, DTR. This bit reads as 0 when modem loopback mode is active." /> + <BitField start="1" size="1" name="RTSCTRL" description="RTS Control. Source for modem output pin RTS. This bit reads as 0 when modem loopback mode is active." /> + <BitField start="2" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + <BitField start="4" size="1" name="LMS" description="Loopback Mode Select. The modem loopback mode provides a mechanism to perform diagnostic loopback testing. Serial data from the transmitter is connected internally to serial input of the receiver. Input pin, RXD1, has no effect on loopback and output pin, TXD1 is held in marking state. The 4 modem inputs (CTS, DSR, RI and DCD) are disconnected externally. Externally, the modem outputs (RTS, DTR) are set inactive. Internally, the 4 modem outputs are connected to the 4 modem inputs. As a result of these connections, the upper 4 bits of the MSR will be driven by the lower 4 bits of the MCR rather than the 4 modem inputs in normal mode. This permits modem status interrupts to be generated in loopback mode by writing the lower 4 bits of MCR."> + <Enum name="DISABLE_MODEM_LOOPBA" start="0" description="Disable modem loopback mode." /> + <Enum name="ENABLE_MODEM_LOOPBAC" start="1" description="Enable modem loopback mode." /> + </BitField> + <BitField start="5" size="1" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + <BitField start="6" size="1" name="RTSEN" description="RTS enable."> + <Enum name="DISABLE_AUTO_RTS_FLO" start="0" description="Disable auto-rts flow control." /> + <Enum name="ENABLE_AUTO_RTS_FLOW" start="1" description="Enable auto-rts flow control." /> + </BitField> + <BitField start="7" size="1" name="CTSEN" description="CTS enable."> + <Enum name="DISABLE_AUTO_CTS_FLO" start="0" description="Disable auto-cts flow control." /> + <Enum name="ENABLE_AUTO_CTS_FLOW" start="1" description="Enable auto-cts flow control." /> + </BitField> + <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x014" size="4" name="LSR" access="None" description="Line Status Register. Contains flags for transmit and receive status, including line errors." reset_value="0x60" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RDR" description="Receiver Data Ready. LSR[0] is set when the RBR holds an unread character and is cleared when the UART1 RBR FIFO is empty."> + <Enum name="EMPTY" start="0" description="The UART1 receiver FIFO is empty." /> + <Enum name="NOTEMPTY" start="1" description="The UART1 receiver FIFO is not empty." /> + </BitField> + <BitField start="1" size="1" name="OE" description="Overrun Error. The overrun error condition is set as soon as it occurs. An LSR read clears LSR[1]. LSR[1] is set when UART1 RSR has a new character assembled and the UART1 RBR FIFO is full. In this case, the UART1 RBR FIFO will not be overwritten and the character in the UART1 RSR will be lost."> + <Enum name="INACTIVE" start="0" description="Overrun error status is inactive." /> + <Enum name="ACTIVE" start="1" description="Overrun error status is active." /> + </BitField> + <BitField start="2" size="1" name="PE" description="Parity Error. When the parity bit of a received character is in the wrong state, a parity error occurs. An LSR read clears LSR[2]. Time of parity error detection is dependent on FCR[0]. Note: A parity error is associated with the character at the top of the UART1 RBR FIFO."> + <Enum name="INACTIVE" start="0" description="Parity error status is inactive." /> + <Enum name="ACTIVE" start="1" description="Parity error status is active." /> + </BitField> + <BitField start="3" size="1" name="FE" description="Framing Error. When the stop bit of a received character is a logic 0, a framing error occurs. An LSR read clears LSR[3]. The time of the framing error detection is dependent on FCR0. Upon detection of a framing error, the RX will attempt to resynchronize to the data and assume that the bad stop bit is actually an early start bit. However, it cannot be assumed that the next received byte will be correct even if there is no Framing Error. Note: A framing error is associated with the character at the top of the UART1 RBR FIFO."> + <Enum name="INACTIVE" start="0" description="Framing error status is inactive." /> + <Enum name="ACTIVE" start="1" description="Framing error status is active." /> + </BitField> + <BitField start="4" size="1" name="BI" description="Break Interrupt. When RXD1 is held in the spacing state (all zeroes) for one full character transmission (start, data, parity, stop), a break interrupt occurs. Once the break condition has been detected, the receiver goes idle until RXD1 goes to marking state (all ones). An LSR read clears this status bit. The time of break detection is dependent on FCR[0]. Note: The break interrupt is associated with the character at the top of the UART1 RBR FIFO."> + <Enum name="INACTIVE" start="0" description="Break interrupt status is inactive." /> + <Enum name="ACTIVE" start="1" description="Break interrupt status is active." /> + </BitField> + <BitField start="5" size="1" name="THRE" description="Transmitter Holding Register Empty. THRE is set immediately upon detection of an empty UART1 THR and is cleared on a THR write."> + <Enum name="VALID" start="0" description="THR contains valid data." /> + <Enum name="THR_IS_EMPTY_" start="1" description="THR is empty." /> + </BitField> + <BitField start="6" size="1" name="TEMT" description="Transmitter Empty. TEMT is set when both THR and TSR are empty; TEMT is cleared when either the TSR or the THR contain valid data."> + <Enum name="VALID" start="0" description="THR and/or the TSR contains valid data." /> + <Enum name="EMPTY" start="1" description="THR and the TSR are empty." /> + </BitField> + <BitField start="7" size="1" name="RXFE" description="Error in RX FIFO. LSR[7] is set when a character with a RX error such as framing error, parity error or break interrupt, is loaded into the RBR. This bit is cleared when the LSR register is read and there are no subsequent errors in the UART1 FIFO."> + <Enum name="NOERROR" start="0" description="RBR contains no UART1 RX errors or FCR[0]=0." /> + <Enum name="ERRORS" start="1" description="UART1 RBR contains at least one UART1 RX error." /> + </BitField> + <BitField start="8" size="24" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x018" size="4" name="MSR" access="None" description="Modem Status Register. Contains handshake signal status flags." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="DCTS" description="Delta CTS. Set upon state change of input CTS. Cleared on an MSR read."> + <Enum name="NO_CHANGE_DETECTED_O" start="0" description="No change detected on modem input, CTS." /> + <Enum name="STATE_CHANGE_DETECTE" start="1" description="State change detected on modem input, CTS." /> + </BitField> + <BitField start="1" size="1" name="DDSR" description="Delta DSR. Set upon state change of input DSR. Cleared on an MSR read."> + <Enum name="NO_CHANGE_DETECTED_O" start="0" description="No change detected on modem input, DSR." /> + <Enum name="STATE_CHANGE_DETECTE" start="1" description="State change detected on modem input, DSR." /> + </BitField> + <BitField start="2" size="1" name="TERI" description="Trailing Edge RI. Set upon low to high transition of input RI. Cleared on an MSR read."> + <Enum name="NO_CHANGE_DETECTED_O" start="0" description="No change detected on modem input, RI." /> + <Enum name="LOW_TO_HIGH_TRANSITI" start="1" description="Low-to-high transition detected on RI." /> + </BitField> + <BitField start="3" size="1" name="DDCD" description="Delta DCD. Set upon state change of input DCD. Cleared on an MSR read."> + <Enum name="NO_CHANGE_DETECTED_O" start="0" description="No change detected on modem input, DCD." /> + <Enum name="STATE_CHANGE_DETECTE" start="1" description="State change detected on modem input, DCD." /> + </BitField> + <BitField start="4" size="1" name="CTS" description="Clear To Send State. Complement of input signal CTS. This bit is connected to MCR[1] in modem loopback mode." /> + <BitField start="5" size="1" name="DSR" description="Data Set Ready State. Complement of input signal DSR. This bit is connected to MCR[0] in modem loopback mode." /> + <BitField start="6" size="1" name="RI" description="Ring Indicator State. Complement of input RI. This bit is connected to MCR[2] in modem loopback mode." /> + <BitField start="7" size="1" name="DCD" description="Data Carrier Detect State. Complement of input DCD. This bit is connected to MCR[3] in modem loopback mode." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x01C" size="4" name="SCR" access="Read/Write" description="Scratch Pad Register. 8-bit temporary storage for software." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="Pad" description="A readable, writable byte." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x020" size="4" name="ACR" access="Read/Write" description="Auto-baud Control Register. Contains controls for the auto-baud feature." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="START" description="Auto-baud start bit. This bit is automatically cleared after auto-baud completion."> + <Enum name="STOP" start="0" description="Auto-baud stop (auto-baud is not running)." /> + <Enum name="START" start="1" description="Auto-baud start (auto-baud is running). Auto-baud run bit. This bit is automatically cleared after auto-baud completion." /> + </BitField> + <BitField start="1" size="1" name="MODE" description="Auto-baud mode select bit."> + <Enum name="MODE_0_" start="0" description="Mode 0." /> + <Enum name="MODE_1_" start="1" description="Mode 1." /> + </BitField> + <BitField start="2" size="1" name="AUTORESTART" description="Auto-baud restart bit."> + <Enum name="NO_RESTART" start="0" description="No restart" /> + <Enum name="RESTART_IN_CASE_OF_T" start="1" description="Restart in case of time-out (counter restarts at next UART1 Rx falling edge)" /> + </BitField> + <BitField start="3" size="5" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + <BitField start="8" size="1" name="ABEOINTCLR" description="End of auto-baud interrupt clear bit (write-only)."> + <Enum name="WRITING_A_0_HAS_NO_I" start="0" description="Writing a 0 has no impact." /> + <Enum name="WRITING_A_1_WILL_CLE" start="1" description="Writing a 1 will clear the corresponding interrupt in the IIR." /> + </BitField> + <BitField start="9" size="1" name="ABTOINTCLR" description="Auto-baud time-out interrupt clear bit (write-only)."> + <Enum name="WRITING_A_0_HAS_NO_I" start="0" description="Writing a 0 has no impact." /> + <Enum name="WRITING_A_1_WILL_CLE" start="1" description="Writing a 1 will clear the corresponding interrupt in the IIR." /> + </BitField> + <BitField start="10" size="22" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x028" size="4" name="FDR" access="Read/Write" description="Fractional Divider Register. Generates a clock input for the baud rate divider." reset_value="0x10" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="4" name="DIVADDVAL" description="Baud rate generation pre-scaler divisor value. If this field is 0, fractional baud rate generator will not impact the UART1 baud rate." /> + <BitField start="4" size="4" name="MULVAL" description="Baud rate pre-scaler multiplier value. This field must be greater or equal 1 for UART1 to operate properly, regardless of whether the fractional baud rate generator is used or not." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x030" size="4" name="TER" access="Read/Write" description="Transmit Enable Register. Turns off UART transmitter for use with software flow control." reset_value="0x80" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="7" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="7" size="1" name="TXEN" description="When this bit is 1, as it is after a Reset, data written to the THR is output on the TXD pin as soon as any preceding data has been sent. If this bit cleared to 0 while a character is being sent, the transmission of that character is completed, but no further characters are sent until this bit is set again. In other words, a 0 in this bit blocks the transfer of characters from the THR or TX FIFO into the transmit shift register. Software can clear this bit when it detects that the a hardware-handshaking TX-permit signal (CTS) has gone false, or with software handshaking, when it receives an XOFF character (DC3). Software can set this bit again when it detects that the TX-permit signal has gone true, or when it receives an XON (DC1) character." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x04C" size="4" name="RS485CTRL" access="Read/Write" description="RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="NMMEN" description="RS-485/EIA-485 Normal Multidrop Mode (NMM) mode select."> + <Enum name="DISABLED_" start="0" description="Disabled." /> + <Enum name="ENABLED_IN_THIS_MOD" start="1" description="Enabled. In this mode, an address is detected when a received byte causes the UART to set the parity error and generate an interrupt." /> + </BitField> + <BitField start="1" size="1" name="RXDIS" description="Receive enable."> + <Enum name="ENABLED_" start="0" description="Enabled." /> + <Enum name="DISABLED_" start="1" description="Disabled." /> + </BitField> + <BitField start="2" size="1" name="AADEN" description="Auto Address Detect (AAD) enable."> + <Enum name="DISABLED_" start="0" description="Disabled." /> + <Enum name="ENABLED_" start="1" description="Enabled." /> + </BitField> + <BitField start="3" size="1" name="SEL" description="Direction control."> + <Enum name="RTS_IF_DIRECTION_CO" start="0" description="RTS. If direction control is enabled (bit DCTRL = 1), pin RTS is used for direction control." /> + <Enum name="DTR_IF_DIRECTION_CO" start="1" description="DTR. If direction control is enabled (bit DCTRL = 1), pin DTR is used for direction control." /> + </BitField> + <BitField start="4" size="1" name="DCTRL" description="Direction control enable."> + <Enum name="DISABLE_AUTO_DIRECTI" start="0" description="Disable Auto Direction Control." /> + <Enum name="ENABLE_AUTO_DIRECTIO" start="1" description="Enable Auto Direction Control." /> + </BitField> + <BitField start="5" size="1" name="OINV" description="Polarity. This bit reverses the polarity of the direction control signal on the RTS (or DTR) pin."> + <Enum name="LOW_THE_DIRECTION_C" start="0" description="LOW. The direction control pin will be driven to logic 0 when the transmitter has data to be sent. It will be driven to logic 1 after the last bit of data has been transmitted." /> + <Enum name="HIGH_THE_DIRECTION_" start="1" description="HIGH. The direction control pin will be driven to logic 1 when the transmitter has data to be sent. It will be driven to logic 0 after the last bit of data has been transmitted." /> + </BitField> + <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x050" size="4" name="RS485ADRMATCH" access="Read/Write" description="RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="ADRMATCH" description="Contains the address match value." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x054" size="4" name="RS485DLY" access="Read/Write" description="RS-485/EIA-485 direction control delay." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="DLY" description="Contains the direction control (RTS or DTR) delay value. This register works in conjunction with an 8-bit counter." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + </RegisterGroup> + <RegisterGroup name="PWM0" start="0x40014000" description="Pulse Width Modulators (PWM0/1)"> + <Register start="+0x000" size="4" name="IR" access="Read/Write" description="Interrupt Register. The IR can be written to clear interrupts, or read to identify which PWM interrupt sources are pending." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="PWMMR0INT" description="Interrupt flag for PWM match channel 0." /> + <BitField start="1" size="1" name="PWMMR1INT" description="Interrupt flag for PWM match channel 1." /> + <BitField start="2" size="1" name="PWMMR2INT" description="Interrupt flag for PWM match channel 2." /> + <BitField start="3" size="1" name="PWMMR3INT" description="Interrupt flag for PWM match channel 3." /> + <BitField start="4" size="1" name="PWMCAP0INT" description="Interrupt flag for capture input 0" /> + <BitField start="5" size="1" name="PWMCAP1INT" description="Interrupt flag for capture input 1 (available in PWM1IR only; this bit is reserved in PWM0IR)." /> + <BitField start="6" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="8" size="1" name="PWMMR4INT" description="Interrupt flag for PWM match channel 4." /> + <BitField start="9" size="1" name="PWMMR5INT" description="Interrupt flag for PWM match channel 5." /> + <BitField start="10" size="1" name="PWMMR6INT" description="Interrupt flag for PWM match channel 6." /> + <BitField start="11" size="21" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x004" size="4" name="TCR" access="Read/Write" description="Timer Control Register. The TCR is used to control the Timer Counter functions." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="CE" description="Counter Enable"> + <Enum name="THE_PWM_TIMER_COUNTE" start="1" description="The PWM Timer Counter and PWM Prescale Counter are enabled for counting." /> + <Enum name="THE_COUNTERS_ARE_DIS" start="0" description="The counters are disabled." /> + </BitField> + <BitField start="1" size="1" name="CR" description="Counter Reset"> + <Enum name="THE_PWM_TIMER_COUNTE" start="1" description="The PWM Timer Counter and the PWM Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until this bit is returned to zero." /> + <Enum name="CLEAR_RESET_" start="0" description="Clear reset." /> + </BitField> + <BitField start="2" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="3" size="1" name="PWMEN" description="PWM Enable"> + <Enum name="PWM_MODE_IS_ENABLED_" start="1" description="PWM mode is enabled (counter resets to 1). PWM mode causes the shadow registers to operate in connection with the Match registers. A program write to a Match register will not have an effect on the Match result until the corresponding bit in PWMLER has been set, followed by the occurrence of a PWM Match 0 event. Note that the PWM Match register that determines the PWM rate (PWM Match Register 0 - MR0) must be set up prior to the PWM being enabled. Otherwise a Match event will not occur to cause shadow register contents to become effective." /> + <Enum name="TIMER_MODE_IS_ENABLE" start="0" description="Timer mode is enabled (counter resets to 0)." /> + </BitField> + <BitField start="4" size="1" name="MDIS" description="Master Disable (PWM0 only). The two PWMs may be synchronized using the Master Disable control bit. The Master disable bit of the Master PWM (PWM0 module) controls a secondary enable input to both PWMs, as shown in Figure 141. This bit has no function in the Slave PWM (PWM1)."> + <Enum name="MASTER_USE_PWM0_IS_" start="1" description="Master use. PWM0 is the master, and both PWMs are enabled for counting." /> + <Enum name="INDIVIDUAL_USE_THE_" start="0" description="Individual use. The PWMs are used independently, and the individual Counter Enable bits are used to control the PWMs." /> + </BitField> + <BitField start="5" size="27" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x008" size="4" name="TC" access="Read/Write" description="Timer Counter. The 32 bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="TC" description="Timer counter value." /> + </Register> + <Register start="+0x00C" size="4" name="PR" access="Read/Write" description="Prescale Register. Determines how often the PWM counter is incremented." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="PM" description="Prescale counter maximum value." /> + </Register> + <Register start="+0x010" size="4" name="PC" access="Read/Write" description="Prescale Counter. Prescaler for the main PWM counter." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="PC" description="Prescale counter value." /> + </Register> + <Register start="+0x014" size="4" name="MCR" access="Read/Write" description="Match Control Register. The MCR is used to control whether an interrupt is generated and if the PWM counter is reset when a Match occurs." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="PWMMR0I" description="Interrupt PWM0"> + <Enum name="DISABLED_" start="0" description="Disabled." /> + <Enum name="INTERRUPT_ON_PWMMR0" start="1" description="Interrupt on PWMMR0: an interrupt is generated when PWMMR0 matches the value in the PWMTC." /> + </BitField> + <BitField start="1" size="1" name="PWMMR0R" description="Reset PWM0"> + <Enum name="DISABLED_" start="0" description="Disabled." /> + <Enum name="RESET_ON_PWMMR0_THE" start="1" description="Reset on PWMMR0: the PWMTC will be reset if PWMMR0 matches it." /> + </BitField> + <BitField start="2" size="1" name="PWMMR0S" description="Stop PWM0"> + <Enum name="DISABLED" start="0" description="Disabled" /> + <Enum name="STOP_ON_PWMMR0_THE_" start="1" description="Stop on PWMMR0: the PWMTC and PWMPC will be stopped and PWMTCR bit 0 will be set to 0 if PWMMR0 matches the PWMTC." /> + </BitField> + <BitField start="3" size="1" name="PWMMR1I" description="Interrupt PWM1"> + <Enum name="DISABLED_" start="0" description="Disabled." /> + <Enum name="INTERRUPT_ON_PWMMR1" start="1" description="Interrupt on PWMMR1: an interrupt is generated when PWMMR1 matches the value in the PWMTC." /> + </BitField> + <BitField start="4" size="1" name="PWMMR1R" description="Reset PWM1"> + <Enum name="DISABLED_" start="0" description="Disabled." /> + <Enum name="RESET_ON_PWMMR1_THE" start="1" description="Reset on PWMMR1: the PWMTC will be reset if PWMMR1 matches it." /> + </BitField> + <BitField start="5" size="1" name="PWMMR1S" description="Stop PWM1"> + <Enum name="DISABLED" start="0" description="Disabled" /> + <Enum name="STOP_ON_PWMMR1_THE_" start="1" description="Stop on PWMMR1: the PWMTC and PWMPC will be stopped and PWMTCR bit 0 will be set to 0 if PWMMR1 matches the PWMTC." /> + </BitField> + <BitField start="6" size="1" name="PWMMR2I" description="Interrupt PWM0"> + <Enum name="DISABLED_" start="0" description="Disabled." /> + <Enum name="INTERRUPT_ON_PWMMR2" start="1" description="Interrupt on PWMMR2: an interrupt is generated when PWMMR2 matches the value in the PWMTC." /> + </BitField> + <BitField start="7" size="1" name="PWMMR2R" description="Reset PWM0"> + <Enum name="DISABLED_" start="0" description="Disabled." /> + <Enum name="RESET_ON_PWMMR2_THE" start="1" description="Reset on PWMMR2: the PWMTC will be reset if PWMMR2 matches it." /> + </BitField> + <BitField start="8" size="1" name="PWMMR2S" description="Stop PWM0"> + <Enum name="DISABLED" start="0" description="Disabled" /> + <Enum name="STOP_ON_PWMMR2_THE_" start="1" description="Stop on PWMMR2: the PWMTC and PWMPC will be stopped and PWMTCR bit 0 will be set to 0 if PWMMR0 matches the PWMTC." /> + </BitField> + <BitField start="9" size="1" name="PWMMR3I" description="Interrupt PWM3"> + <Enum name="DISABLED_" start="0" description="Disabled." /> + <Enum name="INTERRUPT_ON_PWMMR3" start="1" description="Interrupt on PWMMR3: an interrupt is generated when PWMMR3 matches the value in the PWMTC." /> + </BitField> + <BitField start="10" size="1" name="PWMMR3R" description="Reset PWM3"> + <Enum name="DISABLED_" start="0" description="Disabled." /> + <Enum name="RESET_ON_PWMMR3_THE" start="1" description="Reset on PWMMR3: the PWMTC will be reset if PWMMR3 matches it." /> + </BitField> + <BitField start="11" size="1" name="PWMMR3S" description="Stop PWM0"> + <Enum name="DISABLED" start="0" description="Disabled" /> + <Enum name="STOP_ON_PWMMR3_THE_" start="1" description="Stop on PWMMR3: the PWMTC and PWMPC will be stopped and PWMTCR bit 0 will be set to 0 if PWMMR0 matches the PWMTC." /> + </BitField> + <BitField start="12" size="1" name="PWMMR4I" description="Interrupt PWM4"> + <Enum name="DISABLED_" start="0" description="Disabled." /> + <Enum name="INTERRUPT_ON_PWMMR4" start="1" description="Interrupt on PWMMR4: an interrupt is generated when PWMMR4 matches the value in the PWMTC." /> + </BitField> + <BitField start="13" size="1" name="PWMMR4R" description="Reset PWM4"> + <Enum name="DISABLED_" start="0" description="Disabled." /> + <Enum name="RESET_ON_PWMMR4_THE" start="1" description="Reset on PWMMR4: the PWMTC will be reset if PWMMR4 matches it." /> + </BitField> + <BitField start="14" size="1" name="PWMMR4S" description="Stop PWM4"> + <Enum name="DISABLED" start="0" description="Disabled" /> + <Enum name="STOP_ON_PWMMR4_THE_" start="1" description="Stop on PWMMR4: the PWMTC and PWMPC will be stopped and PWMTCR bit 0 will be set to 0 if PWMMR4 matches the PWMTC." /> + </BitField> + <BitField start="15" size="1" name="PWMMR5I" description="Interrupt PWM5"> + <Enum name="DISABLED_" start="0" description="Disabled." /> + <Enum name="INTERRUPT_ON_PWMMR5" start="1" description="Interrupt on PWMMR5: an interrupt is generated when PWMMR5 matches the value in the PWMTC." /> + </BitField> + <BitField start="16" size="1" name="PWMMR5R" description="Reset PWM5"> + <Enum name="DISABLED_" start="0" description="Disabled." /> + <Enum name="RESET_ON_PWMMR5_THE" start="1" description="Reset on PWMMR5: the PWMTC will be reset if PWMMR5 matches it." /> + </BitField> + <BitField start="17" size="1" name="PWMMR5S" description="Stop PWM5"> + <Enum name="DISABLED" start="0" description="Disabled" /> + <Enum name="STOP_ON_PWMMR5_THE_" start="1" description="Stop on PWMMR5: the PWMTC and PWMPC will be stopped and PWMTCR bit 0 will be set to 0 if PWMMR5 matches the PWMTC." /> + </BitField> + <BitField start="18" size="1" name="PWMMR6I" description="Interrupt PWM6"> + <Enum name="DISABLED_" start="0" description="Disabled." /> + <Enum name="INTERRUPT_ON_PWMMR6" start="1" description="Interrupt on PWMMR6: an interrupt is generated when PWMMR6 matches the value in the PWMTC." /> + </BitField> + <BitField start="19" size="1" name="PWMMR6R" description="Reset PWM6"> + <Enum name="DISABLED_" start="0" description="Disabled." /> + <Enum name="RESET_ON_PWMMR6_THE" start="1" description="Reset on PWMMR6: the PWMTC will be reset if PWMMR6 matches it." /> + </BitField> + <BitField start="20" size="1" name="PWMMR6S" description="Stop PWM6"> + <Enum name="DISABLED" start="0" description="Disabled" /> + <Enum name="STOP_ON_PWMMR6_THE_" start="1" description="Stop on PWMMR6: the PWMTC and PWMPC will be stopped and PWMTCR bit 0 will be set to 0 if PWMMR6 matches the PWMTC." /> + </BitField> + <BitField start="21" size="11" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x018+0" size="4" name="MR0" access="Read/Write" description="Match Register. Match registers
are continuously compared to the PWM counter in order to control PWM
output edges." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="MATCH" description="Timer counter match value." /> + </Register> + <Register start="+0x018+4" size="4" name="MR1" access="Read/Write" description="Match Register. Match registers
are continuously compared to the PWM counter in order to control PWM
output edges." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="MATCH" description="Timer counter match value." /> + </Register> + <Register start="+0x018+8" size="4" name="MR2" access="Read/Write" description="Match Register. Match registers
are continuously compared to the PWM counter in order to control PWM
output edges." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="MATCH" description="Timer counter match value." /> + </Register> + <Register start="+0x018+12" size="4" name="MR3" access="Read/Write" description="Match Register. Match registers
are continuously compared to the PWM counter in order to control PWM
output edges." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="MATCH" description="Timer counter match value." /> + </Register> + <Register start="+0x028" size="4" name="CCR" access="Read/Write" description="Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated for a capture event." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="CAP0_R" description="Capture on PWMn_CAP0 rising edge"> + <Enum name="DISABLED_THIS_FEATU" start="0" description="Disabled. This feature is disabled." /> + <Enum name="RISING_EDGE_A_SYNCH" start="1" description="Rising edge. A synchronously sampled rising edge on PWMn_CAP0 will cause CR0 to be loaded with the contents of the TC." /> + </BitField> + <BitField start="1" size="1" name="CAP0_F" description="Capture on PWMn_CAP0 falling edge"> + <Enum name="DISABLED_THIS_FEATU" start="0" description="Disabled. This feature is disabled." /> + <Enum name="FALLING_EDGE_A_SYNC" start="1" description="Falling edge. A synchronously sampled falling edge on PWMn_CAP0 will cause CR0 to be loaded with the contents of TC." /> + </BitField> + <BitField start="2" size="1" name="CAP0_I" description="Interrupt on PWMn_CAP0 event"> + <Enum name="DISABLED_THIS_FEATU" start="0" description="Disabled. This feature is disabled." /> + <Enum name="INTERRUPT_A_CR0_LOA" start="1" description="Interrupt. A CR0 load due to a PWMn_CAP0 event will generate an interrupt." /> + </BitField> + <BitField start="3" size="1" name="CAP1_R" description="Capture on PWMn_CAP1 rising edge. Reserved for PWM0."> + <Enum name="DISABLED_THIS_FEATU" start="0" description="Disabled. This feature is disabled." /> + <Enum name="RISING_EDGE_A_SYNCH" start="1" description="Rising edge. A synchronously sampled rising edge on PWMn_CAP1 will cause CR1 to be loaded with the contents of the TC." /> + </BitField> + <BitField start="4" size="1" name="CAP1_F" description="Capture on PWMn_CAP1 falling edge. Reserved for PWM0."> + <Enum name="DISABLED_THIS_FEATU" start="0" description="Disabled. This feature is disabled." /> + <Enum name="FALLING_EDGE_A_SYNC" start="1" description="Falling edge. A synchronously sampled falling edge on PWMn_CAP1 will cause CR1 to be loaded with the contents of TC." /> + </BitField> + <BitField start="5" size="1" name="CAP1_I" description="Interrupt on PWMn_CAP1 event. Reserved for PWM0."> + <Enum name="DISABLED_THIS_FEATU" start="0" description="Disabled. This feature is disabled." /> + <Enum name="INTERRUPT_A_CR1_LOA" start="1" description="Interrupt. A CR1 load due to a PWMn_CAP1 event will generate an interrupt." /> + </BitField> + <BitField start="6" size="26" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x02C+0" size="4" name="CR[0]" access="Read/Write" description="PWM Control Register. Enables PWM outputs and selects either single edge or double edge controlled PWM outputs." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="RESERVED" description="Reserved." /> + <BitField start="2" size="1" name="PWMSEL2" description="PWM[2] output single/double edge mode control."> + <Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." /> + <Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." /> + </BitField> + <BitField start="3" size="1" name="PWMSEL3" description="PWM[3] output edge control."> + <Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." /> + <Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." /> + </BitField> + <BitField start="4" size="1" name="PWMSEL4" description="PWM[4] output edge control."> + <Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." /> + <Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." /> + </BitField> + <BitField start="5" size="1" name="PWMSEL5" description="PWM[5] output edge control."> + <Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." /> + <Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." /> + </BitField> + <BitField start="6" size="1" name="PWMSEL6" description="PWM[6] output edge control."> + <Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." /> + <Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." /> + </BitField> + <BitField start="7" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="9" size="1" name="PWMENA1" description="PWM[1] output enable control."> + <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." /> + <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." /> + </BitField> + <BitField start="10" size="1" name="PWMENA2" description="PWM[2] output enable control."> + <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." /> + <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." /> + </BitField> + <BitField start="11" size="1" name="PWMENA3" description="PWM[3] output enable control."> + <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." /> + <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." /> + </BitField> + <BitField start="12" size="1" name="PWMENA4" description="PWM[4] output enable control."> + <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." /> + <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." /> + </BitField> + <BitField start="13" size="1" name="PWMENA5" description="PWM[5] output enable control."> + <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." /> + <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." /> + </BitField> + <BitField start="14" size="1" name="PWMENA6" description="PWM[6] output enable control. See PWMENA1 for details."> + <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." /> + <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." /> + </BitField> + <BitField start="15" size="17" name="RESERVED" description="Unused, always zero." /> + </Register> + <Register start="+0x02C+4" size="4" name="CR[1]" access="Read/Write" description="PWM Control Register. Enables PWM outputs and selects either single edge or double edge controlled PWM outputs." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="RESERVED" description="Reserved." /> + <BitField start="2" size="1" name="PWMSEL2" description="PWM[2] output single/double edge mode control."> + <Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." /> + <Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." /> + </BitField> + <BitField start="3" size="1" name="PWMSEL3" description="PWM[3] output edge control."> + <Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." /> + <Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." /> + </BitField> + <BitField start="4" size="1" name="PWMSEL4" description="PWM[4] output edge control."> + <Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." /> + <Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." /> + </BitField> + <BitField start="5" size="1" name="PWMSEL5" description="PWM[5] output edge control."> + <Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." /> + <Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." /> + </BitField> + <BitField start="6" size="1" name="PWMSEL6" description="PWM[6] output edge control."> + <Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." /> + <Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." /> + </BitField> + <BitField start="7" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="9" size="1" name="PWMENA1" description="PWM[1] output enable control."> + <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." /> + <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." /> + </BitField> + <BitField start="10" size="1" name="PWMENA2" description="PWM[2] output enable control."> + <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." /> + <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." /> + </BitField> + <BitField start="11" size="1" name="PWMENA3" description="PWM[3] output enable control."> + <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." /> + <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." /> + </BitField> + <BitField start="12" size="1" name="PWMENA4" description="PWM[4] output enable control."> + <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." /> + <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." /> + </BitField> + <BitField start="13" size="1" name="PWMENA5" description="PWM[5] output enable control."> + <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." /> + <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." /> + </BitField> + <BitField start="14" size="1" name="PWMENA6" description="PWM[6] output enable control. See PWMENA1 for details."> + <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." /> + <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." /> + </BitField> + <BitField start="15" size="17" name="RESERVED" description="Unused, always zero." /> + </Register> + <Register start="+0x040" size="4" name="MR4" access="Read/Write" description="Match Register. Match registers
are continuously compared to the PWM counter in order to control PWM
output edges." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="MATCH" description="Timer counter match value." /> + </Register> + <Register start="+0x044" size="4" name="MR5" access="Read/Write" description="Match Register. Match registers
				are continuously compared to the PWM counter in order to control PWM
				output edges." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="MATCH" description="Timer counter match value." /> + </Register> + <Register start="+0x048" size="4" name="MR6" access="Read/Write" description="Match Register. Match registers
				are continuously compared to the PWM counter in order to control PWM
				output edges." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="MATCH" description="Timer counter match value." /> + </Register> + <Register start="+0x04C" size="4" name="PCR" access="Read/Write" description="PWM Control Register. Enables PWM outputs and selects either single edge or double edge controlled PWM outputs." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="RESERVED" description="Reserved." /> + <BitField start="2" size="1" name="PWMSEL2" description="PWM[2] output single/double edge mode control."> + <Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." /> + <Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." /> + </BitField> + <BitField start="3" size="1" name="PWMSEL3" description="PWM[3] output edge control."> + <Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." /> + <Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." /> + </BitField> + <BitField start="4" size="1" name="PWMSEL4" description="PWM[4] output edge control."> + <Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." /> + <Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." /> + </BitField> + <BitField start="5" size="1" name="PWMSEL5" description="PWM[5] output edge control."> + <Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." /> + <Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." /> + </BitField> + <BitField start="6" size="1" name="PWMSEL6" description="PWM[6] output edge control."> + <Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." /> + <Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." /> + </BitField> + <BitField start="7" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="9" size="1" name="PWMENA1" description="PWM[1] output enable control."> + <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." /> + <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." /> + </BitField> + <BitField start="10" size="1" name="PWMENA2" description="PWM[2] output enable control."> + <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." /> + <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." /> + </BitField> + <BitField start="11" size="1" name="PWMENA3" description="PWM[3] output enable control."> + <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." /> + <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." /> + </BitField> + <BitField start="12" size="1" name="PWMENA4" description="PWM[4] output enable control."> + <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." /> + <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." /> + </BitField> + <BitField start="13" size="1" name="PWMENA5" description="PWM[5] output enable control."> + <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." /> + <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." /> + </BitField> + <BitField start="14" size="1" name="PWMENA6" description="PWM[6] output enable control. See PWMENA1 for details."> + <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." /> + <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." /> + </BitField> + <BitField start="15" size="17" name="RESERVED" description="Unused, always zero." /> + </Register> + <Register start="+0x050" size="4" name="LER" access="Read/Write" description="Load Enable Register. Enables use of updated PWM match values." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="MAT0LATCHEN" description="Enable PWM Match 0 Latch. PWM MR0 register update control. Writing a one to this bit allows the last value written to the PWM Match Register 0 to be become effective when the timer is next reset by a PWM Match event. See Section 27.6.7." /> + <BitField start="1" size="1" name="MAT1LATCHEN" description="Enable PWM Match 1 Latch. PWM MR1 register update control. See bit 0 for details." /> + <BitField start="2" size="1" name="MAT2LATCHEN" description="Enable PWM Match 2 Latch. PWM MR2 register update control. See bit 0 for details." /> + <BitField start="3" size="1" name="MAT3LATCHEN" description="Enable PWM Match 3 Latch. PWM MR3 register update control. See bit 0 for details." /> + <BitField start="4" size="1" name="MAT4LATCHEN" description="Enable PWM Match 4 Latch. PWM MR4 register update control. See bit 0 for details." /> + <BitField start="5" size="1" name="MAT5LATCHEN" description="Enable PWM Match 5 Latch. PWM MR5 register update control. See bit 0 for details." /> + <BitField start="6" size="1" name="MAT6LATCHEN" description="Enable PWM Match 6 Latch. PWM MR6 register update control. See bit 0 for details." /> + <BitField start="7" size="25" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x070" size="4" name="CTCR" access="Read/Write" description="Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="MOD" description="Counter/ Timer Mode"> + <Enum name="TIMER_MODE_THE_TC_I" start="0x0" description="Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale register." /> + <Enum name="RISING_EDGE_COUNTER_" start="0x1" description="Rising edge counter Mode: the TC is incremented on rising edges of the PWM_CAP input selected by bits 3:2." /> + <Enum name="FALLING_EDGE_COUNTER" start="0x2" description="Falling edge counter Mode: the TC is incremented on falling edges of the PWM_CAP input selected by bits 3:2." /> + <Enum name="DUAL_EDGE_COUNTER_MO" start="0x3" description="Dual edge counter Mode: the TC is incremented on both edges of the PWM_CAP input selected by bits 3:2." /> + </BitField> + <BitField start="2" size="2" name="CIS" description="Count Input Select. When bits 1:0 are not 00, these bits select which PWM_CAP pin carries the signal used to increment the TC. Other combinations are reserved."> + <Enum name="FOR_PWM0_00_EQ_PWM0_" start="0x0" description="For PWM0: 00 = PWM0_CAP0 (Other combinations are reserved) For PWM1: 00 = PWM1_CAP0, 01 = PWM1_CAP1 (Other combinations are reserved)" /> + </BitField> + <BitField start="4" size="28" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + </RegisterGroup> + <RegisterGroup name="PWM1" start="0x40018000" description="Pulse Width Modulators (PWM0/1)"> + <Register start="+0x000" size="4" name="IR" access="Read/Write" description="Interrupt Register. The IR can be written to clear interrupts, or read to identify which PWM interrupt sources are pending." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="PWMMR0INT" description="Interrupt flag for PWM match channel 0." /> + <BitField start="1" size="1" name="PWMMR1INT" description="Interrupt flag for PWM match channel 1." /> + <BitField start="2" size="1" name="PWMMR2INT" description="Interrupt flag for PWM match channel 2." /> + <BitField start="3" size="1" name="PWMMR3INT" description="Interrupt flag for PWM match channel 3." /> + <BitField start="4" size="1" name="PWMCAP0INT" description="Interrupt flag for capture input 0" /> + <BitField start="5" size="1" name="PWMCAP1INT" description="Interrupt flag for capture input 1 (available in PWM1IR only; this bit is reserved in PWM0IR)." /> + <BitField start="6" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="8" size="1" name="PWMMR4INT" description="Interrupt flag for PWM match channel 4." /> + <BitField start="9" size="1" name="PWMMR5INT" description="Interrupt flag for PWM match channel 5." /> + <BitField start="10" size="1" name="PWMMR6INT" description="Interrupt flag for PWM match channel 6." /> + <BitField start="11" size="21" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x004" size="4" name="TCR" access="Read/Write" description="Timer Control Register. The TCR is used to control the Timer Counter functions." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="CE" description="Counter Enable"> + <Enum name="THE_PWM_TIMER_COUNTE" start="1" description="The PWM Timer Counter and PWM Prescale Counter are enabled for counting." /> + <Enum name="THE_COUNTERS_ARE_DIS" start="0" description="The counters are disabled." /> + </BitField> + <BitField start="1" size="1" name="CR" description="Counter Reset"> + <Enum name="THE_PWM_TIMER_COUNTE" start="1" description="The PWM Timer Counter and the PWM Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until this bit is returned to zero." /> + <Enum name="CLEAR_RESET_" start="0" description="Clear reset." /> + </BitField> + <BitField start="2" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="3" size="1" name="PWMEN" description="PWM Enable"> + <Enum name="PWM_MODE_IS_ENABLED_" start="1" description="PWM mode is enabled (counter resets to 1). PWM mode causes the shadow registers to operate in connection with the Match registers. A program write to a Match register will not have an effect on the Match result until the corresponding bit in PWMLER has been set, followed by the occurrence of a PWM Match 0 event. Note that the PWM Match register that determines the PWM rate (PWM Match Register 0 - MR0) must be set up prior to the PWM being enabled. Otherwise a Match event will not occur to cause shadow register contents to become effective." /> + <Enum name="TIMER_MODE_IS_ENABLE" start="0" description="Timer mode is enabled (counter resets to 0)." /> + </BitField> + <BitField start="4" size="1" name="MDIS" description="Master Disable (PWM0 only). The two PWMs may be synchronized using the Master Disable control bit. The Master disable bit of the Master PWM (PWM0 module) controls a secondary enable input to both PWMs, as shown in Figure 141. This bit has no function in the Slave PWM (PWM1)."> + <Enum name="MASTER_USE_PWM0_IS_" start="1" description="Master use. PWM0 is the master, and both PWMs are enabled for counting." /> + <Enum name="INDIVIDUAL_USE_THE_" start="0" description="Individual use. The PWMs are used independently, and the individual Counter Enable bits are used to control the PWMs." /> + </BitField> + <BitField start="5" size="27" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x008" size="4" name="TC" access="Read/Write" description="Timer Counter. The 32 bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="TC" description="Timer counter value." /> + </Register> + <Register start="+0x00C" size="4" name="PR" access="Read/Write" description="Prescale Register. Determines how often the PWM counter is incremented." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="PM" description="Prescale counter maximum value." /> + </Register> + <Register start="+0x010" size="4" name="PC" access="Read/Write" description="Prescale Counter. Prescaler for the main PWM counter." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="PC" description="Prescale counter value." /> + </Register> + <Register start="+0x014" size="4" name="MCR" access="Read/Write" description="Match Control Register. The MCR is used to control whether an interrupt is generated and if the PWM counter is reset when a Match occurs." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="PWMMR0I" description="Interrupt PWM0"> + <Enum name="DISABLED_" start="0" description="Disabled." /> + <Enum name="INTERRUPT_ON_PWMMR0" start="1" description="Interrupt on PWMMR0: an interrupt is generated when PWMMR0 matches the value in the PWMTC." /> + </BitField> + <BitField start="1" size="1" name="PWMMR0R" description="Reset PWM0"> + <Enum name="DISABLED_" start="0" description="Disabled." /> + <Enum name="RESET_ON_PWMMR0_THE" start="1" description="Reset on PWMMR0: the PWMTC will be reset if PWMMR0 matches it." /> + </BitField> + <BitField start="2" size="1" name="PWMMR0S" description="Stop PWM0"> + <Enum name="DISABLED" start="0" description="Disabled" /> + <Enum name="STOP_ON_PWMMR0_THE_" start="1" description="Stop on PWMMR0: the PWMTC and PWMPC will be stopped and PWMTCR bit 0 will be set to 0 if PWMMR0 matches the PWMTC." /> + </BitField> + <BitField start="3" size="1" name="PWMMR1I" description="Interrupt PWM1"> + <Enum name="DISABLED_" start="0" description="Disabled." /> + <Enum name="INTERRUPT_ON_PWMMR1" start="1" description="Interrupt on PWMMR1: an interrupt is generated when PWMMR1 matches the value in the PWMTC." /> + </BitField> + <BitField start="4" size="1" name="PWMMR1R" description="Reset PWM1"> + <Enum name="DISABLED_" start="0" description="Disabled." /> + <Enum name="RESET_ON_PWMMR1_THE" start="1" description="Reset on PWMMR1: the PWMTC will be reset if PWMMR1 matches it." /> + </BitField> + <BitField start="5" size="1" name="PWMMR1S" description="Stop PWM1"> + <Enum name="DISABLED" start="0" description="Disabled" /> + <Enum name="STOP_ON_PWMMR1_THE_" start="1" description="Stop on PWMMR1: the PWMTC and PWMPC will be stopped and PWMTCR bit 0 will be set to 0 if PWMMR1 matches the PWMTC." /> + </BitField> + <BitField start="6" size="1" name="PWMMR2I" description="Interrupt PWM0"> + <Enum name="DISABLED_" start="0" description="Disabled." /> + <Enum name="INTERRUPT_ON_PWMMR2" start="1" description="Interrupt on PWMMR2: an interrupt is generated when PWMMR2 matches the value in the PWMTC." /> + </BitField> + <BitField start="7" size="1" name="PWMMR2R" description="Reset PWM0"> + <Enum name="DISABLED_" start="0" description="Disabled." /> + <Enum name="RESET_ON_PWMMR2_THE" start="1" description="Reset on PWMMR2: the PWMTC will be reset if PWMMR2 matches it." /> + </BitField> + <BitField start="8" size="1" name="PWMMR2S" description="Stop PWM0"> + <Enum name="DISABLED" start="0" description="Disabled" /> + <Enum name="STOP_ON_PWMMR2_THE_" start="1" description="Stop on PWMMR2: the PWMTC and PWMPC will be stopped and PWMTCR bit 0 will be set to 0 if PWMMR0 matches the PWMTC." /> + </BitField> + <BitField start="9" size="1" name="PWMMR3I" description="Interrupt PWM3"> + <Enum name="DISABLED_" start="0" description="Disabled." /> + <Enum name="INTERRUPT_ON_PWMMR3" start="1" description="Interrupt on PWMMR3: an interrupt is generated when PWMMR3 matches the value in the PWMTC." /> + </BitField> + <BitField start="10" size="1" name="PWMMR3R" description="Reset PWM3"> + <Enum name="DISABLED_" start="0" description="Disabled." /> + <Enum name="RESET_ON_PWMMR3_THE" start="1" description="Reset on PWMMR3: the PWMTC will be reset if PWMMR3 matches it." /> + </BitField> + <BitField start="11" size="1" name="PWMMR3S" description="Stop PWM0"> + <Enum name="DISABLED" start="0" description="Disabled" /> + <Enum name="STOP_ON_PWMMR3_THE_" start="1" description="Stop on PWMMR3: the PWMTC and PWMPC will be stopped and PWMTCR bit 0 will be set to 0 if PWMMR0 matches the PWMTC." /> + </BitField> + <BitField start="12" size="1" name="PWMMR4I" description="Interrupt PWM4"> + <Enum name="DISABLED_" start="0" description="Disabled." /> + <Enum name="INTERRUPT_ON_PWMMR4" start="1" description="Interrupt on PWMMR4: an interrupt is generated when PWMMR4 matches the value in the PWMTC." /> + </BitField> + <BitField start="13" size="1" name="PWMMR4R" description="Reset PWM4"> + <Enum name="DISABLED_" start="0" description="Disabled." /> + <Enum name="RESET_ON_PWMMR4_THE" start="1" description="Reset on PWMMR4: the PWMTC will be reset if PWMMR4 matches it." /> + </BitField> + <BitField start="14" size="1" name="PWMMR4S" description="Stop PWM4"> + <Enum name="DISABLED" start="0" description="Disabled" /> + <Enum name="STOP_ON_PWMMR4_THE_" start="1" description="Stop on PWMMR4: the PWMTC and PWMPC will be stopped and PWMTCR bit 0 will be set to 0 if PWMMR4 matches the PWMTC." /> + </BitField> + <BitField start="15" size="1" name="PWMMR5I" description="Interrupt PWM5"> + <Enum name="DISABLED_" start="0" description="Disabled." /> + <Enum name="INTERRUPT_ON_PWMMR5" start="1" description="Interrupt on PWMMR5: an interrupt is generated when PWMMR5 matches the value in the PWMTC." /> + </BitField> + <BitField start="16" size="1" name="PWMMR5R" description="Reset PWM5"> + <Enum name="DISABLED_" start="0" description="Disabled." /> + <Enum name="RESET_ON_PWMMR5_THE" start="1" description="Reset on PWMMR5: the PWMTC will be reset if PWMMR5 matches it." /> + </BitField> + <BitField start="17" size="1" name="PWMMR5S" description="Stop PWM5"> + <Enum name="DISABLED" start="0" description="Disabled" /> + <Enum name="STOP_ON_PWMMR5_THE_" start="1" description="Stop on PWMMR5: the PWMTC and PWMPC will be stopped and PWMTCR bit 0 will be set to 0 if PWMMR5 matches the PWMTC." /> + </BitField> + <BitField start="18" size="1" name="PWMMR6I" description="Interrupt PWM6"> + <Enum name="DISABLED_" start="0" description="Disabled." /> + <Enum name="INTERRUPT_ON_PWMMR6" start="1" description="Interrupt on PWMMR6: an interrupt is generated when PWMMR6 matches the value in the PWMTC." /> + </BitField> + <BitField start="19" size="1" name="PWMMR6R" description="Reset PWM6"> + <Enum name="DISABLED_" start="0" description="Disabled." /> + <Enum name="RESET_ON_PWMMR6_THE" start="1" description="Reset on PWMMR6: the PWMTC will be reset if PWMMR6 matches it." /> + </BitField> + <BitField start="20" size="1" name="PWMMR6S" description="Stop PWM6"> + <Enum name="DISABLED" start="0" description="Disabled" /> + <Enum name="STOP_ON_PWMMR6_THE_" start="1" description="Stop on PWMMR6: the PWMTC and PWMPC will be stopped and PWMTCR bit 0 will be set to 0 if PWMMR6 matches the PWMTC." /> + </BitField> + <BitField start="21" size="11" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x018+0" size="4" name="MR0" access="Read/Write" description="Match Register. Match registers
are continuously compared to the PWM counter in order to control PWM
output edges." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="MATCH" description="Timer counter match value." /> + </Register> + <Register start="+0x018+4" size="4" name="MR1" access="Read/Write" description="Match Register. Match registers
are continuously compared to the PWM counter in order to control PWM
output edges." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="MATCH" description="Timer counter match value." /> + </Register> + <Register start="+0x018+8" size="4" name="MR2" access="Read/Write" description="Match Register. Match registers
are continuously compared to the PWM counter in order to control PWM
output edges." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="MATCH" description="Timer counter match value." /> + </Register> + <Register start="+0x018+12" size="4" name="MR3" access="Read/Write" description="Match Register. Match registers
are continuously compared to the PWM counter in order to control PWM
output edges." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="MATCH" description="Timer counter match value." /> + </Register> + <Register start="+0x028" size="4" name="CCR" access="Read/Write" description="Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated for a capture event." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="CAP0_R" description="Capture on PWMn_CAP0 rising edge"> + <Enum name="DISABLED_THIS_FEATU" start="0" description="Disabled. This feature is disabled." /> + <Enum name="RISING_EDGE_A_SYNCH" start="1" description="Rising edge. A synchronously sampled rising edge on PWMn_CAP0 will cause CR0 to be loaded with the contents of the TC." /> + </BitField> + <BitField start="1" size="1" name="CAP0_F" description="Capture on PWMn_CAP0 falling edge"> + <Enum name="DISABLED_THIS_FEATU" start="0" description="Disabled. This feature is disabled." /> + <Enum name="FALLING_EDGE_A_SYNC" start="1" description="Falling edge. A synchronously sampled falling edge on PWMn_CAP0 will cause CR0 to be loaded with the contents of TC." /> + </BitField> + <BitField start="2" size="1" name="CAP0_I" description="Interrupt on PWMn_CAP0 event"> + <Enum name="DISABLED_THIS_FEATU" start="0" description="Disabled. This feature is disabled." /> + <Enum name="INTERRUPT_A_CR0_LOA" start="1" description="Interrupt. A CR0 load due to a PWMn_CAP0 event will generate an interrupt." /> + </BitField> + <BitField start="3" size="1" name="CAP1_R" description="Capture on PWMn_CAP1 rising edge. Reserved for PWM0."> + <Enum name="DISABLED_THIS_FEATU" start="0" description="Disabled. This feature is disabled." /> + <Enum name="RISING_EDGE_A_SYNCH" start="1" description="Rising edge. A synchronously sampled rising edge on PWMn_CAP1 will cause CR1 to be loaded with the contents of the TC." /> + </BitField> + <BitField start="4" size="1" name="CAP1_F" description="Capture on PWMn_CAP1 falling edge. Reserved for PWM0."> + <Enum name="DISABLED_THIS_FEATU" start="0" description="Disabled. This feature is disabled." /> + <Enum name="FALLING_EDGE_A_SYNC" start="1" description="Falling edge. A synchronously sampled falling edge on PWMn_CAP1 will cause CR1 to be loaded with the contents of TC." /> + </BitField> + <BitField start="5" size="1" name="CAP1_I" description="Interrupt on PWMn_CAP1 event. Reserved for PWM0."> + <Enum name="DISABLED_THIS_FEATU" start="0" description="Disabled. This feature is disabled." /> + <Enum name="INTERRUPT_A_CR1_LOA" start="1" description="Interrupt. A CR1 load due to a PWMn_CAP1 event will generate an interrupt." /> + </BitField> + <BitField start="6" size="26" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x02C+0" size="4" name="CR[0]" access="Read/Write" description="PWM Control Register. Enables PWM outputs and selects either single edge or double edge controlled PWM outputs." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="RESERVED" description="Reserved." /> + <BitField start="2" size="1" name="PWMSEL2" description="PWM[2] output single/double edge mode control."> + <Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." /> + <Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." /> + </BitField> + <BitField start="3" size="1" name="PWMSEL3" description="PWM[3] output edge control."> + <Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." /> + <Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." /> + </BitField> + <BitField start="4" size="1" name="PWMSEL4" description="PWM[4] output edge control."> + <Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." /> + <Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." /> + </BitField> + <BitField start="5" size="1" name="PWMSEL5" description="PWM[5] output edge control."> + <Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." /> + <Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." /> + </BitField> + <BitField start="6" size="1" name="PWMSEL6" description="PWM[6] output edge control."> + <Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." /> + <Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." /> + </BitField> + <BitField start="7" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="9" size="1" name="PWMENA1" description="PWM[1] output enable control."> + <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." /> + <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." /> + </BitField> + <BitField start="10" size="1" name="PWMENA2" description="PWM[2] output enable control."> + <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." /> + <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." /> + </BitField> + <BitField start="11" size="1" name="PWMENA3" description="PWM[3] output enable control."> + <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." /> + <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." /> + </BitField> + <BitField start="12" size="1" name="PWMENA4" description="PWM[4] output enable control."> + <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." /> + <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." /> + </BitField> + <BitField start="13" size="1" name="PWMENA5" description="PWM[5] output enable control."> + <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." /> + <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." /> + </BitField> + <BitField start="14" size="1" name="PWMENA6" description="PWM[6] output enable control. See PWMENA1 for details."> + <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." /> + <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." /> + </BitField> + <BitField start="15" size="17" name="RESERVED" description="Unused, always zero." /> + </Register> + <Register start="+0x02C+4" size="4" name="CR[1]" access="Read/Write" description="PWM Control Register. Enables PWM outputs and selects either single edge or double edge controlled PWM outputs." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="RESERVED" description="Reserved." /> + <BitField start="2" size="1" name="PWMSEL2" description="PWM[2] output single/double edge mode control."> + <Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." /> + <Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." /> + </BitField> + <BitField start="3" size="1" name="PWMSEL3" description="PWM[3] output edge control."> + <Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." /> + <Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." /> + </BitField> + <BitField start="4" size="1" name="PWMSEL4" description="PWM[4] output edge control."> + <Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." /> + <Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." /> + </BitField> + <BitField start="5" size="1" name="PWMSEL5" description="PWM[5] output edge control."> + <Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." /> + <Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." /> + </BitField> + <BitField start="6" size="1" name="PWMSEL6" description="PWM[6] output edge control."> + <Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." /> + <Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." /> + </BitField> + <BitField start="7" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="9" size="1" name="PWMENA1" description="PWM[1] output enable control."> + <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." /> + <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." /> + </BitField> + <BitField start="10" size="1" name="PWMENA2" description="PWM[2] output enable control."> + <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." /> + <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." /> + </BitField> + <BitField start="11" size="1" name="PWMENA3" description="PWM[3] output enable control."> + <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." /> + <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." /> + </BitField> + <BitField start="12" size="1" name="PWMENA4" description="PWM[4] output enable control."> + <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." /> + <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." /> + </BitField> + <BitField start="13" size="1" name="PWMENA5" description="PWM[5] output enable control."> + <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." /> + <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." /> + </BitField> + <BitField start="14" size="1" name="PWMENA6" description="PWM[6] output enable control. See PWMENA1 for details."> + <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." /> + <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." /> + </BitField> + <BitField start="15" size="17" name="RESERVED" description="Unused, always zero." /> + </Register> + <Register start="+0x040" size="4" name="MR4" access="Read/Write" description="Match Register. Match registers
are continuously compared to the PWM counter in order to control PWM
output edges." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="MATCH" description="Timer counter match value." /> + </Register> + <Register start="+0x044" size="4" name="MR5" access="Read/Write" description="Match Register. Match registers
				are continuously compared to the PWM counter in order to control PWM
				output edges." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="MATCH" description="Timer counter match value." /> + </Register> + <Register start="+0x048" size="4" name="MR6" access="Read/Write" description="Match Register. Match registers
				are continuously compared to the PWM counter in order to control PWM
				output edges." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="MATCH" description="Timer counter match value." /> + </Register> + <Register start="+0x04C" size="4" name="PCR" access="Read/Write" description="PWM Control Register. Enables PWM outputs and selects either single edge or double edge controlled PWM outputs." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="RESERVED" description="Reserved." /> + <BitField start="2" size="1" name="PWMSEL2" description="PWM[2] output single/double edge mode control."> + <Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." /> + <Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." /> + </BitField> + <BitField start="3" size="1" name="PWMSEL3" description="PWM[3] output edge control."> + <Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." /> + <Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." /> + </BitField> + <BitField start="4" size="1" name="PWMSEL4" description="PWM[4] output edge control."> + <Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." /> + <Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." /> + </BitField> + <BitField start="5" size="1" name="PWMSEL5" description="PWM[5] output edge control."> + <Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." /> + <Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." /> + </BitField> + <BitField start="6" size="1" name="PWMSEL6" description="PWM[6] output edge control."> + <Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." /> + <Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." /> + </BitField> + <BitField start="7" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="9" size="1" name="PWMENA1" description="PWM[1] output enable control."> + <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." /> + <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." /> + </BitField> + <BitField start="10" size="1" name="PWMENA2" description="PWM[2] output enable control."> + <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." /> + <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." /> + </BitField> + <BitField start="11" size="1" name="PWMENA3" description="PWM[3] output enable control."> + <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." /> + <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." /> + </BitField> + <BitField start="12" size="1" name="PWMENA4" description="PWM[4] output enable control."> + <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." /> + <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." /> + </BitField> + <BitField start="13" size="1" name="PWMENA5" description="PWM[5] output enable control."> + <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." /> + <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." /> + </BitField> + <BitField start="14" size="1" name="PWMENA6" description="PWM[6] output enable control. See PWMENA1 for details."> + <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." /> + <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." /> + </BitField> + <BitField start="15" size="17" name="RESERVED" description="Unused, always zero." /> + </Register> + <Register start="+0x050" size="4" name="LER" access="Read/Write" description="Load Enable Register. Enables use of updated PWM match values." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="MAT0LATCHEN" description="Enable PWM Match 0 Latch. PWM MR0 register update control. Writing a one to this bit allows the last value written to the PWM Match Register 0 to be become effective when the timer is next reset by a PWM Match event. See Section 27.6.7." /> + <BitField start="1" size="1" name="MAT1LATCHEN" description="Enable PWM Match 1 Latch. PWM MR1 register update control. See bit 0 for details." /> + <BitField start="2" size="1" name="MAT2LATCHEN" description="Enable PWM Match 2 Latch. PWM MR2 register update control. See bit 0 for details." /> + <BitField start="3" size="1" name="MAT3LATCHEN" description="Enable PWM Match 3 Latch. PWM MR3 register update control. See bit 0 for details." /> + <BitField start="4" size="1" name="MAT4LATCHEN" description="Enable PWM Match 4 Latch. PWM MR4 register update control. See bit 0 for details." /> + <BitField start="5" size="1" name="MAT5LATCHEN" description="Enable PWM Match 5 Latch. PWM MR5 register update control. See bit 0 for details." /> + <BitField start="6" size="1" name="MAT6LATCHEN" description="Enable PWM Match 6 Latch. PWM MR6 register update control. See bit 0 for details." /> + <BitField start="7" size="25" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x070" size="4" name="CTCR" access="Read/Write" description="Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="MOD" description="Counter/ Timer Mode"> + <Enum name="TIMER_MODE_THE_TC_I" start="0x0" description="Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale register." /> + <Enum name="RISING_EDGE_COUNTER_" start="0x1" description="Rising edge counter Mode: the TC is incremented on rising edges of the PWM_CAP input selected by bits 3:2." /> + <Enum name="FALLING_EDGE_COUNTER" start="0x2" description="Falling edge counter Mode: the TC is incremented on falling edges of the PWM_CAP input selected by bits 3:2." /> + <Enum name="DUAL_EDGE_COUNTER_MO" start="0x3" description="Dual edge counter Mode: the TC is incremented on both edges of the PWM_CAP input selected by bits 3:2." /> + </BitField> + <BitField start="2" size="2" name="CIS" description="Count Input Select. When bits 1:0 are not 00, these bits select which PWM_CAP pin carries the signal used to increment the TC. Other combinations are reserved."> + <Enum name="FOR_PWM0_00_EQ_PWM0_" start="0x0" description="For PWM0: 00 = PWM0_CAP0 (Other combinations are reserved) For PWM1: 00 = PWM1_CAP0, 01 = PWM1_CAP1 (Other combinations are reserved)" /> + </BitField> + <BitField start="4" size="28" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + </RegisterGroup> + <RegisterGroup name="I2C0" start="0x4001C000" description="I2C bus interface"> + <Register start="+0x000" size="4" name="CONSET" access="Read/Write" description="I2C Control Set Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is set. Writing a zero has no effect on the corresponding bit in the I2C control register." reset_value="0x00" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + <BitField start="2" size="1" name="AA" description="Assert acknowledge flag." /> + <BitField start="3" size="1" name="SI" description="I2C interrupt flag." /> + <BitField start="4" size="1" name="STO" description="STOP flag." /> + <BitField start="5" size="1" name="STA" description="START flag." /> + <BitField start="6" size="1" name="I2EN" description="I2C interface enable." /> + <BitField start="7" size="25" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x004" size="4" name="STAT" access="ReadOnly" description="I2C Status Register. During I2C operation, this register provides detailed status codes that allow software to determine the next action needed." reset_value="0xF8" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="RESERVED" description="These bits are unused and are always 0." /> + <BitField start="3" size="5" name="Status" description="These bits give the actual status information about the I 2C interface." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x008" size="4" name="DAT" access="Read/Write" description="I2C Data Register. During master or slave transmit mode, data to be transmitted is written to this register. During master or slave receive mode, data that has been received may be read from this register." reset_value="0x00" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="Data" description="This register holds data values that have been received or are to be transmitted." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x00C" size="4" name="ADR0" access="Read/Write" description="I2C Slave Address Register 0. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="GC" description="General Call enable bit." /> + <BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x010" size="4" name="SCLH" access="Read/Write" description="SCH Duty Cycle Register High Half Word. Determines the high time of the I2C clock." reset_value="0x04" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="16" name="SCLH" description="Count for SCL HIGH time period selection." /> + <BitField start="16" size="16" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x014" size="4" name="SCLL" access="Read/Write" description="SCL Duty Cycle Register Low Half Word. Determines the low time of the I2C clock. SCLL and SCLH together determine the clock frequency generated by an I2C master and certain times used in slave mode." reset_value="0x04" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="16" name="SCLL" description="Count for SCL low time period selection." /> + <BitField start="16" size="16" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x018" size="4" name="CONCLR" access="WriteOnly" description="I2C Control Clear Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is cleared. Writing a zero has no effect on the corresponding bit in the I2C control register." reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="2" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + <BitField start="2" size="1" name="AAC" description="Assert acknowledge Clear bit." /> + <BitField start="3" size="1" name="SIC" description="I2C interrupt Clear bit." /> + <BitField start="4" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + <BitField start="5" size="1" name="STAC" description="START flag Clear bit." /> + <BitField start="6" size="1" name="I2ENC" description="I2C interface Disable bit." /> + <BitField start="7" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x01C" size="4" name="MMCTRL" access="Read/Write" description="Monitor mode control register." reset_value="0x00" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="MM_ENA" description="Monitor mode enable."> + <Enum name="MONITOR_MODE_DISABLE" start="0" description="Monitor mode disabled." /> + <Enum name="THE_I_2C_MODULE_WILL" start="1" description="The I 2C module will enter monitor mode. In this mode the SDA output will be forced high. This will prevent the I2C module from outputting data of any kind (including ACK) onto the I2C data bus. Depending on the state of the ENA_SCL bit, the output may be also forced high, preventing the module from having control over the I2C clock line." /> + </BitField> + <BitField start="1" size="1" name="ENA_SCL" description="SCL output enable."> + <Enum name="WHEN_THIS_BIT_IS_CLE" start="0" description="When this bit is cleared to 0, the SCL output will be forced high when the module is in monitor mode. As described above, this will prevent the module from having any control over the I2C clock line." /> + <Enum name="WHEN_THIS_BIT_IS_SET" start="1" description="When this bit is set, the I2C module may exercise the same control over the clock line that it would in normal operation. This means that, acting as a slave peripheral, the I2C module can stretch the clock line (hold it low) until it has had time to respond to an I2C interrupt.[1]" /> + </BitField> + <BitField start="2" size="1" name="MATCH_ALL" description="Select interrupt register match."> + <Enum name="WHEN_THIS_BIT_IS_CLE" start="0" description="When this bit is cleared, an interrupt will only be generated when a match occurs to one of the (up-to) four address registers described above. That is, the module will respond as a normal slave as far as address-recognition is concerned." /> + <Enum name="WHEN_THIS_BIT_IS_SET" start="1" description="When this bit is set to 1 and the I2C is in monitor mode, an interrupt will be generated on ANY address received. This will enable the part to monitor all traffic on the bus." /> + </BitField> + <BitField start="3" size="29" name="RESERVED" description="Reserved. The value read from reserved bits is not defined." /> + </Register> + <Register start="+0x020+0" size="4" name="ADR1" access="Read/Write" description="I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="GC" description="General Call enable bit." /> + <BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x020+4" size="4" name="ADR2" access="Read/Write" description="I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="GC" description="General Call enable bit." /> + <BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x020+8" size="4" name="ADR3" access="Read/Write" description="I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="GC" description="General Call enable bit." /> + <BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x02C" size="4" name="DATA_BUFFER" access="ReadOnly" description="Data buffer register. The contents of the 8 MSBs of the DAT shift register will be transferred to the DATA_BUFFER automatically after every nine bits (8 bits of data plus ACK or NACK) has been received on the bus." reset_value="0x00" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="Data" description="This register holds contents of the 8 MSBs of the DAT shift register." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x030+0" size="4" name="MASK[0]" access="Read/Write" description="I2C Slave address mask register" reset_value="0x00" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." /> + <BitField start="1" size="7" name="MASK" description="Mask bits." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x030+4" size="4" name="MASK[1]" access="Read/Write" description="I2C Slave address mask register" reset_value="0x00" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." /> + <BitField start="1" size="7" name="MASK" description="Mask bits." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x030+8" size="4" name="MASK[2]" access="Read/Write" description="I2C Slave address mask register" reset_value="0x00" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." /> + <BitField start="1" size="7" name="MASK" description="Mask bits." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x030+12" size="4" name="MASK[3]" access="Read/Write" description="I2C Slave address mask register" reset_value="0x00" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." /> + <BitField start="1" size="7" name="MASK" description="Mask bits." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + </RegisterGroup> + <RegisterGroup name="COMPARATOR" start="0x40020000" description="Comparators"> + <Register start="+0x000" size="4" name="CTRL" access="Read/Write" description="Comparator block control register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="CMP_PD_IREF" description="Controls the current source used by the comparators. These bits must be set when either comparator is used."> + <Enum name="DISABLED" start="0x0" description="The comparator current source is disabled." /> + <Enum name="DIS_DEEPSLP_PWRDWN" start="0x1" description="The comparator current source is disabled in Deep Sleep and Power-down modes and restored automatically when exiting those modes." /> + <Enum name="DIS_PWRDWN" start="0x2" description="The comparator current source is disabled in Power-down mode and restored automatically when exiting Power-down." /> + <Enum name="ENABLED" start="0x3" description="The comparator current source is powered up." /> + </BitField> + <BitField start="2" size="2" name="CMP_PD_VBG" description="Controls the bandgap reference source that is used by the comparators. These bits must be set when either comparator is used."> + <Enum name="DISABLED" start="0x0" description="The comparator bandgap reference is disabled." /> + <Enum name="DIS_DEEPSLP_PWRDWN" start="0x1" description="The comparator bandgap reference is disabled in Deep Sleep and Power-down modes and restored automatically when exiting those modes." /> + <Enum name="DIS_PWRDWN" start="0x2" description="The comparator bandgap reference is disabled in Power-down mode and restored automatically when exiting Power-down." /> + <Enum name="ENABLED" start="0x3" description="The comparator bandgap reference is powered up." /> + </BitField> + <BitField start="4" size="2" name="CMP_VTEMP" description="Controls the voltage reference of the temperature sensor. These bits must be set when the temperature sensor is used."> + <Enum name="DISABLED" start="0x0" description="The temperature sensor voltage reference is disabled." /> + <Enum name="DIS_DEEPSLP_PWRDWN" start="0x1" description="The temperature sensor voltage reference is disabled in Deep Sleep and Power-down modes and restored automatically when exiting those modes." /> + <Enum name="DIS_PWRDWN" start="0x2" description="The temperature sensor voltage reference is disabled in Power-down mode and restored automatically when exiting Power-down." /> + <Enum name="ENABLED" start="0x3" description="The temperature sensor voltage reference is powered up." /> + </BitField> + <BitField start="6" size="2" name="CMP_TEMPSEN" description="Enables the temperature sensor. These bits must be set when the temperature sensor is used."> + <Enum name="DISABLED" start="0x0" description="Temperature sensor is disabled." /> + <Enum name="DIS_DEEPSLP_PWRDWN" start="0x1" description="The temperature sensor is disabled in Deep Sleep and Power-down modes and restored automatically when exiting those modes." /> + <Enum name="DIS_PWRDWN" start="0x2" description="The temperature sensor is disabled in Power-down mode and restored automatically when exiting Power-down." /> + <Enum name="ENABLED" start="0x3" description="Temperature sensor is enabled." /> + </BitField> + <BitField start="8" size="1" name="CMP_ROSCCTL" description="Selects the inputs for the flip/flops that provide the CMP_ROSC output."> + <Enum name="CMP1" start="0" description="The CMP_ROSC output is set by CMP1 and reset by CMP0." /> + <Enum name="CMP0" start="1" description="The CMP_ROSC output is set by CMP0 and reset by CMP1." /> + </BitField> + <BitField start="9" size="1" name="CMP_EXT_RESET" description="Selects the reset source for the CMP_ROSC output."> + <Enum name="INTRESET" start="0" description="The CMP_ROSC output is reset by the internal chip reset." /> + <Enum name="CMP_RESETIN" start="1" description="The CMP_ROSC output is reset by the CMP_RESET input." /> + </BitField> + <BitField start="10" size="2" name="RESERVED" description="Reserved." /> + <BitField start="12" size="1" name="CMP_T0CAP2" description="Selects the input for Timer 0 capture input 2."> + <Enum name="COMP0" start="0" description="T0CAP2 is connected to comparator 0 level output." /> + <Enum name="COMP1" start="1" description="T0CAP2 is connected to comparator 1 level output." /> + </BitField> + <BitField start="13" size="1" name="CMP_T0CAP3" description="Selects the input for Timer 0 capture input 3."> + <Enum name="COMP0" start="0" description="T0CAP3 is connected to comparator 0 edge output." /> + <Enum name="COMP1" start="1" description="T0CAP3 is connected to comparator 1 edge output." /> + </BitField> + <BitField start="14" size="1" name="CMP_T1CAP2" description="Selects the input for Timer 1 capture input 2."> + <Enum name="COMP1" start="0" description="T1CAP2 is connected to comparator 1 edge output." /> + <Enum name="COMP0" start="1" description="T1CAP2 is connected to comparator 0 level output." /> + </BitField> + <BitField start="15" size="1" name="CMP_T1CAP3" description="Selects the input for Timer 1 capture input 3."> + <Enum name="COMP1" start="0" description="T1CAP3 is connected to comparator 1 level output." /> + <Enum name="COMP0" start="1" description="T1CAP3 is connected to comparator 0 edge output." /> + </BitField> + <BitField start="16" size="16" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x004" size="4" name="CTRL0" access="Read/Write" description="Comparator 0 control register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="CMP0_EN" description="Comparator 0 enable control."> + <Enum name="DISABLED" start="0x0" description="Comparator 0 disabled." /> + <Enum name="DIS_DEEPSLP_PWRDWN" start="0x1" description="Comparator 0 is disabled in Deep Sleep and Power-down modes and re-enabled automatically when exiting those modes." /> + <Enum name="DIS_PWRDWN" start="0x2" description="Comparator 0 is disabled in Power-down mode and re-enabled automatically when exiting Power-down." /> + <Enum name="ENABLED" start="0x3" description="Comparator 0 is enabled." /> + </BitField> + <BitField start="2" size="1" name="CMP0_OE" description="Comparator 0 output enable."> + <Enum name="DISABLED" start="0" description="Comparator 0 output is disabled." /> + <Enum name="ENABLED" start="1" description="Comparator 0 output is enabled." /> + </BitField> + <BitField start="3" size="1" name="CMP0_STAT" description="Comparator 0 status. This bit reflects the comparator 0 output, and is not affected by CMP0_OE." /> + <BitField start="4" size="3" name="CMP0_VM" description="Comparator 0 VM input select."> + <Enum name="VREF_DIVIDER_0_" start="0x0" description="Vref divider 0." /> + <Enum name="CMP0_IN0" start="0x1" description="CMP0_IN[0]." /> + <Enum name="CMP0_IN1" start="0x2" description="CMP0_IN[1]." /> + <Enum name="CMP0_IN2" start="0x3" description="CMP0_IN[2]." /> + <Enum name="CMP0_IN3" start="0x4" description="CMP0_IN[3]." /> + <Enum name="CMP1_IN0" start="0x5" description="CMP1_IN[0]." /> + <Enum name="INTERNAL_0_9_V_BAND_" start="0x6" description="internal 0.9 V band gap reference." /> + <Enum name="TEMPERATURE_SENSOR_" start="0x7" description="temperature sensor." /> + </BitField> + <BitField start="7" size="1" name="RESERVED" description="Reserved." /> + <BitField start="8" size="3" name="CMP0_VP" description="Comparator 0 VP input select."> + <Enum name="VREF_DIVIDER_0_" start="0x0" description="Vref divider 0." /> + <Enum name="CMP0_IN0" start="0x1" description="CMP0_IN[0]." /> + <Enum name="CMP0_IN1" start="0x2" description="CMP0_IN[1]." /> + <Enum name="CMP0_IN2" start="0x3" description="CMP0_IN[2]." /> + <Enum name="CMP0_IN3" start="0x4" description="CMP0_IN[3]." /> + <Enum name="CMP1_IN0" start="0x5" description="CMP1_IN[0]." /> + <Enum name="INTERNAL_0_9_V_BAND_" start="0x6" description="internal 0.9 V band gap reference." /> + <Enum name="TEMPERATURE_SENSOR_" start="0x7" description="temperature sensor." /> + </BitField> + <BitField start="11" size="1" name="RESERVED" description="Reserved." /> + <BitField start="12" size="1" name="CMP0_SYNC" description="Comparator 0 output synchronization control."> + <Enum name="DIRECT" start="0" description="The comparator 0 output is used directly." /> + <Enum name="SYNCH" start="1" description="The comparator 0 output is synchronized with the internal bus clock for output to other peripherals." /> + </BitField> + <BitField start="13" size="2" name="CMP0_HYS" description="Comparator 0 hysteresis control. When enabled, hysteresis determines the difference required between the comparator inputs before the comparator output switches. The difference must be in the direction opposite of the current comparator output."> + <Enum name="HYSTERESISOFF" start="0x0" description="Hysteresis is turned off, comparator output will change as the input voltages cross." /> + <Enum name="HYSTERESIS_EQ_5_MV_" start="0x1" description="Hysteresis = 5 mV." /> + <Enum name="HYSTERESIS_EQ_10_MV_" start="0x2" description="Hysteresis = 10 mV." /> + <Enum name="HYSTERESIS_EQ_15_MV_" start="0x3" description="Hysteresis = 15 mV." /> + </BitField> + <BitField start="15" size="1" name="CMP0_INTPOL" description="Selects the polarity of the CMP0 output for purposes of generating level interrupts. See Table 412."> + <Enum name="NOTINVERTED" start="0" description="The CMP0 output is used as-is for generating interrupts." /> + <Enum name="INVERTED" start="1" description="The CMP0 output is used inverted for generating interrupts." /> + </BitField> + <BitField start="16" size="1" name="CMP0_INTTYPE" description="Select comparator 0 interrupt type. See Table 412."> + <Enum name="EDGE" start="0" description="Comparator 0 interrupt is edge triggered." /> + <Enum name="LEVEL" start="1" description="Comparator 0 interrupt is level triggered." /> + </BitField> + <BitField start="17" size="2" name="CMP0_INTEDGE" description="Select edge triggered interrupt to be active on either high or low transitions, when CMP0_IntType = 0. See Table 412."> + <Enum name="FALLING" start="0x0" description="Comparator 0 interrupt is active on falling edges." /> + <Enum name="RISING" start="0x1" description="Comparator 0 interrupt is active on rising edges." /> + <Enum name="DUALEDGE" start="0x2" description="Comparator 0 Interrupt is active on both edges." /> + </BitField> + <BitField start="19" size="1" name="CMP0_INTFLAG" description="Comparator 0 interrupt flag."> + <Enum name="NOTPENDING" start="0" description="The Comparator 0 interrupt is not pending." /> + <Enum name="PENDING" start="1" description="The Comparator 0 interrupt is pending. Writing a 1 to this bit clears the flag." /> + </BitField> + <BitField start="20" size="2" name="CMP0_VLADEN" description="Voltage ladder enable for comparator 0."> + <Enum name="DISABLED" start="0x0" description="The Comparator 0 voltage ladder is disabled." /> + <Enum name="DIS_DEEPSLP_PWRDWN" start="0x1" description="The Comparator 0 voltage ladder is disabled in Deep Sleep and Power-down modes and re-enabled automatically when exiting those modes." /> + <Enum name="DIS_PWRDWN" start="0x2" description="The Comparator 0 voltage ladder is disabled in Power-down mode and re-enabled automatically when exiting Power-down." /> + <Enum name="ENABLED" start="0x3" description="The Comparator 0 voltage ladder is enabled." /> + </BitField> + <BitField start="22" size="1" name="CMP0_VLADREF" description="Voltage reference select for comparator 0 voltage ladder."> + <Enum name="VREF_CMP_PIN_" start="0" description="VREF_CMP pin." /> + <Enum name="VDDA_PIN_" start="1" description="VDDA pin." /> + </BitField> + <BitField start="23" size="1" name="RESERVED" description="Reserved." /> + <BitField start="24" size="5" name="CMP0_VSEL" description="Voltage ladder value for comparator 0. The reference voltage Vref depends on the setting of CMP0_VLADREF (either VDD(3V3) or voltage on pin VREF_CMP). 00000 = Vss. 00001 = 1 x Vref0 / 31. 00010 = 2 x Vref0 / 31. ... 11111 = Vref0" /> + <BitField start="29" size="3" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x008" size="4" name="CTRL1" access="Read/Write" description="Comparator 1 control register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="CMP1_EN" description="Comparator 1 enable control."> + <Enum name="DISABLED" start="0x0" description="Comparator 1 disabled." /> + <Enum name="DIS_DEEPSLP_PWRDWN" start="0x1" description="Comparator 1 is disabled in Deep Sleep and Power-down modes and re-enabled automatically when exiting those modes." /> + <Enum name="DIS_PWRDWN" start="0x2" description="Comparator 1 is disabled in Power-down mode and re-enabled automatically when exiting Power-down." /> + <Enum name="ENABLED" start="0x3" description="Comparator 1 is enabled." /> + </BitField> + <BitField start="2" size="1" name="CMP1_OE" description="Comparator 1 output enable."> + <Enum name="DISABLED" start="0" description="Comparator 1 output is disabled." /> + <Enum name="ENABLED" start="1" description="Comparator 1 output is enabled." /> + </BitField> + <BitField start="3" size="1" name="CMP1_STAT" description="Comparator 1 status. This bit reflects the comparator 1 output, and is not affected by CMP1_OE." /> + <BitField start="4" size="3" name="CMP1_VM" description="Comparator 1 VM input select."> + <Enum name="VREF_DIVIDER_1_" start="0x0" description="Vref divider 1." /> + <Enum name="CMP1_IN0" start="0x1" description="CMP1_IN[0]." /> + <Enum name="CMP1_IN1" start="0x2" description="CMP1_IN[1]." /> + <Enum name="CMP1_IN2" start="0x3" description="CMP1_IN[2]." /> + <Enum name="CMP1_IN3" start="0x4" description="CMP1_IN[3]." /> + <Enum name="CMP0_IN0" start="0x5" description="CMP0_IN[0]." /> + <Enum name="INTERNAL_0_9_V_BAND_" start="0x6" description="internal 0.9 V band gap reference." /> + <Enum name="TEMPERATURE_SENSOR_" start="0x7" description="temperature sensor." /> + </BitField> + <BitField start="7" size="1" name="RESERVED" description="Reserved." /> + <BitField start="8" size="3" name="CMP1_VP" description="Comparator 1 VP input select."> + <Enum name="VREF_DIVIDER_0_" start="0x0" description="Vref divider 0." /> + <Enum name="CMP1_IN0" start="0x1" description="CMP1_IN[0]." /> + <Enum name="CMP1_IN1" start="0x2" description="CMP1_IN[1]." /> + <Enum name="CMP1_IN2" start="0x3" description="CMP1_IN[2]." /> + <Enum name="CMP1_IN3" start="0x4" description="CMP1_IN[3]." /> + <Enum name="CMP0_IN0" start="0x5" description="CMP0_IN[0]." /> + <Enum name="INTERNAL_0_9_V_BAND_" start="0x6" description="internal 0.9 V band gap reference." /> + <Enum name="TEMPERATURE_SENSOR_" start="0x7" description="temperature sensor." /> + </BitField> + <BitField start="11" size="1" name="RESERVED" description="Reserved." /> + <BitField start="12" size="1" name="CMP1_SYNC" description="Comparator 1 output synchronization control."> + <Enum name="DIRECT" start="0" description="The comparator 1 output is used directly." /> + <Enum name="SYNCH" start="1" description="The comparator 1 output is synchronized with the internal bus clock for output to other peripherals." /> + </BitField> + <BitField start="13" size="2" name="CMP1_HYS" description="Comparator 1 hysteresis control. When enabled, hysteresis determines the difference required between the comparator inputs before the comparator output switches. The difference must be in the direction opposite of the current comparator output."> + <Enum name="HYSTERESISOFF" start="0x0" description="Hysteresis is turned off, comparator output will change as the input voltages cross." /> + <Enum name="HYSTERESIS_EQ_5_MV_" start="0x1" description="Hysteresis = 5 mV." /> + <Enum name="HYSTERESIS_EQ_10_MV_" start="0x2" description="Hysteresis = 10 mV." /> + <Enum name="HYSTERESIS_EQ_15_MV_" start="0x3" description="Hysteresis = 15 mV." /> + </BitField> + <BitField start="15" size="1" name="CMP1_INTPOL" description="Selects the polarity of the CMP1 output for purposes of generating level interrupts. See Table 412."> + <Enum name="NOTINVERTED" start="0" description="The CMP1 output is used as-is for generating interrupts." /> + <Enum name="INVERTED" start="1" description="The CMP1 output is used inverted for generating interrupts." /> + </BitField> + <BitField start="16" size="1" name="CMP1_INTTYPE" description="Select comparator 1 interrupt type. See Table 412."> + <Enum name="EDGE" start="0" description="Comparator 1 interrupt is edge triggered." /> + <Enum name="LEVEL" start="1" description="Comparator 1 interrupt is level triggered." /> + </BitField> + <BitField start="17" size="2" name="CMP1_INTEDGE" description="Select edge triggered interrupt to be active on either high or low transitions, when CMP1_IntType = 0. See Table 412."> + <Enum name="FALLING" start="0x0" description="Comparator 1 interrupt is active on falling edges." /> + <Enum name="RISING" start="0x1" description="Comparator 1 interrupt is active on rising edges." /> + <Enum name="DUALEDGE" start="0x2" description="Comparator 1 Interrupt is active on both edges." /> + </BitField> + <BitField start="19" size="1" name="CMP1_INTFLAG" description="Comparator 1 interrupt flag."> + <Enum name="NOTPENDING" start="0" description="The Comparator 1 interrupt is not pending." /> + <Enum name="PENDING" start="1" description="The Comparator 1 interrupt is pending. Writing a 1 to this bit clears the flag." /> + </BitField> + <BitField start="20" size="2" name="CMP1_VLADEN" description="Voltage ladder enable for comparator 1."> + <Enum name="DISABLED" start="0x0" description="The Comparator 1 voltage ladder is disabled." /> + <Enum name="DIS_DEEPSLP_PWRDWN" start="0x1" description="The Comparator 1 voltage ladder is disabled in Deep Sleep and Power-down modes and re-enabled automatically when exiting those modes." /> + <Enum name="DIS_PWRDWN" start="0x2" description="The Comparator 1 voltage ladder is disabled in Power-down mode and re-enabled automatically when exiting Power-down." /> + <Enum name="ENABLED" start="0x3" description="The Comparator 1 voltage ladder is enabled." /> + </BitField> + <BitField start="22" size="1" name="CMP1_VLADREF" description="Voltage reference select for comparator 1 voltage ladder."> + <Enum name="VREF_CMP_PIN_" start="0" description="VREF_CMP pin." /> + <Enum name="VDDA_PIN_" start="1" description="VDDA pin." /> + </BitField> + <BitField start="23" size="1" name="RESERVED" description="Reserved." /> + <BitField start="24" size="5" name="CMP1_VSel" description="Voltage ladder value for comparator 1. The reference voltage Vref depends on the setting of CMP1_VLADREF (either VDD(3V3) or voltage on pin VREF_CMP). 00000 = Vss. 00001 = 1 x Vref1 / 31. 00010 = 2 x Vref1 / 31. ... 11111 = Vref1." /> + <BitField start="29" size="3" name="RESERVED" description="Reserved." /> + </Register> + </RegisterGroup> + <RegisterGroup name="RTC" start="0x40024000" description=" Real Time Clock (RTC) "> + <Register start="+0x000" size="4" name="ILR" access="Read/Write" description="Interrupt Location Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RTCCIF" description="When one, the Counter Increment Interrupt block generated an interrupt. Writing a one to this bit location clears the counter increment interrupt." /> + <BitField start="1" size="1" name="RTCALF" description="When one, the alarm registers generated an interrupt. Writing a one to this bit location clears the alarm interrupt." /> + <BitField start="21" size="11" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x008" size="4" name="CCR" access="Read/Write" description="Clock Control Register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="CLKEN" description="Clock Enable."> + <Enum name="THE_TIME_COUNTERS_AR" start="1" description="The time counters are enabled." /> + <Enum name="THE_TIME_COUNTERS_AR" start="0" description="The time counters are disabled so that they may be initialized." /> + </BitField> + <BitField start="1" size="1" name="CTCRST" description="CTC Reset."> + <Enum name="RESET" start="1" description="When one, the elements in the internal oscillator divider are reset, and remain reset until CCR[1] is changed to zero. This is the divider that generates the 1 Hz clock from the 32.768 kHz crystal. The state of the divider is not visible to software." /> + <Enum name="NO_EFFECT_" start="0" description="No effect." /> + </BitField> + <BitField start="2" size="2" name="RESERVED" description="Internal test mode controls. These bits must be 0 for normal RTC operation." /> + <BitField start="4" size="1" name="CCALEN" description="Calibration counter enable."> + <Enum name="THE_CALIBRATION_COUN" start="1" description="The calibration counter is disabled and reset to zero." /> + <Enum name="THE_CALIBRATION_COUN" start="0" description="The calibration counter is enabled and counting, using the 1 Hz clock. When the calibration counter is equal to the value of the CALIBRATION register, the counter resets and repeats counting up to the value of the CALIBRATION register. See Section 30.6.4.2 and Section 30.6.5." /> + </BitField> + <BitField start="5" size="27" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x00C" size="4" name="CIIR" access="Read/Write" description="Counter Increment Interrupt Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="IMSEC" description="When 1, an increment of the Second value generates an interrupt." /> + <BitField start="1" size="1" name="IMMIN" description="When 1, an increment of the Minute value generates an interrupt." /> + <BitField start="2" size="1" name="IMHOUR" description="When 1, an increment of the Hour value generates an interrupt." /> + <BitField start="3" size="1" name="IMDOM" description="When 1, an increment of the Day of Month value generates an interrupt." /> + <BitField start="4" size="1" name="IMDOW" description="When 1, an increment of the Day of Week value generates an interrupt." /> + <BitField start="5" size="1" name="IMDOY" description="When 1, an increment of the Day of Year value generates an interrupt." /> + <BitField start="6" size="1" name="IMMON" description="When 1, an increment of the Month value generates an interrupt." /> + <BitField start="7" size="1" name="IMYEAR" description="When 1, an increment of the Year value generates an interrupt." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x010" size="4" name="AMR" access="Read/Write" description="Alarm Mask Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="AMRSEC" description="When 1, the Second value is not compared for the alarm." /> + <BitField start="1" size="1" name="AMRMIN" description="When 1, the Minutes value is not compared for the alarm." /> + <BitField start="2" size="1" name="AMRHOUR" description="When 1, the Hour value is not compared for the alarm." /> + <BitField start="3" size="1" name="AMRDOM" description="When 1, the Day of Month value is not compared for the alarm." /> + <BitField start="4" size="1" name="AMRDOW" description="When 1, the Day of Week value is not compared for the alarm." /> + <BitField start="5" size="1" name="AMRDOY" description="When 1, the Day of Year value is not compared for the alarm." /> + <BitField start="6" size="1" name="AMRMON" description="When 1, the Month value is not compared for the alarm." /> + <BitField start="7" size="1" name="AMRYEAR" description="When 1, the Year value is not compared for the alarm." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x014" size="4" name="CTIME0" access="ReadOnly" description="Consolidated Time Register 0" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="6" name="SECONDS" description="Seconds value in the range of 0 to 59" /> + <BitField start="6" size="2" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + <BitField start="8" size="6" name="MINUTES" description="Minutes value in the range of 0 to 59" /> + <BitField start="14" size="2" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + <BitField start="16" size="5" name="HOURS" description="Hours value in the range of 0 to 23" /> + <BitField start="21" size="3" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + <BitField start="24" size="3" name="DOW" description="Day of week value in the range of 0 to 6" /> + <BitField start="27" size="5" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x018" size="4" name="CTIME1" access="ReadOnly" description="Consolidated Time Register 1" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="5" name="DOM" description="Day of month value in the range of 1 to 28, 29, 30, or 31 (depending on the month and whether it is a leap year)." /> + <BitField start="5" size="3" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + <BitField start="8" size="4" name="MONTH" description="Month value in the range of 1 to 12." /> + <BitField start="12" size="4" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + <BitField start="16" size="12" name="YEAR" description="Year value in the range of 0 to 4095." /> + <BitField start="28" size="4" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x01C" size="4" name="CTIME2" access="ReadOnly" description="Consolidated Time Register 2" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="12" name="DOY" description="Day of year value in the range of 1 to 365 (366 for leap years)." /> + <BitField start="12" size="20" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x020" size="4" name="SEC" access="Read/Write" description="Seconds Counter" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="6" name="SECONDS" description="Seconds value in the range of 0 to 59" /> + <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x024" size="4" name="MIN" access="Read/Write" description="Minutes Register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="6" name="MINUTES" description="Minutes value in the range of 0 to 59" /> + <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x028" size="4" name="HRS" access="Read/Write" description="Hours Register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="5" name="HOURS" description="Hours value in the range of 0 to 23" /> + <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x02C" size="4" name="DOM" access="Read/Write" description="Day of Month Register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="5" name="DOM" description="Day of month value in the range of 1 to 28, 29, 30, or 31 (depending on the month and whether it is a leap year)." /> + <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x030" size="4" name="DOW" access="Read/Write" description="Day of Week Register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="3" name="DOW" description="Day of week value in the range of 0 to 6." /> + <BitField start="3" size="29" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x034" size="4" name="DOY" access="Read/Write" description="Day of Year Register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="9" name="DOY" description="Day of year value in the range of 1 to 365 (366 for leap years)." /> + <BitField start="9" size="23" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x038" size="4" name="MONTH" access="Read/Write" description="Months Register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="4" name="MONTH" description="Month value in the range of 1 to 12." /> + <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x03C" size="4" name="YEAR" access="Read/Write" description="Years Register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="12" name="YEAR" description="Year value in the range of 0 to 4095." /> + <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x040" size="4" name="CALIBRATION" access="Read/Write" description="Calibration Value Register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="17" name="CALVAL" description="If enabled, the calibration counter counts up to this value. The maximum value is 131, 072 corresponding to about 36.4 hours. Calibration is disabled if CALVAL = 0." /> + <BitField start="17" size="1" name="CALDIR" description="Calibration direction"> + <Enum name="BACKWARD_CALIBRATION" start="1" description="Backward calibration. When CALVAL is equal to the calibration counter, the RTC timers will stop incrementing for 1 second." /> + <Enum name="FORWARD_CALIBRATION_" start="0" description="Forward calibration. When CALVAL is equal to the calibration counter, the RTC timers will jump by 2 seconds." /> + </BitField> + </Register> + <Register start="+0x044+0" size="4" name="GPREG0" access="Read/Write" description="General Purpose Register 0" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="GP" description="General purpose storage." /> + </Register> + <Register start="+0x044+4" size="4" name="GPREG1" access="Read/Write" description="General Purpose Register 0" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="GP" description="General purpose storage." /> + </Register> + <Register start="+0x044+8" size="4" name="GPREG2" access="Read/Write" description="General Purpose Register 0" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="GP" description="General purpose storage." /> + </Register> + <Register start="+0x044+12" size="4" name="GPREG3" access="Read/Write" description="General Purpose Register 0" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="GP" description="General purpose storage." /> + </Register> + <Register start="+0x044+16" size="4" name="GPREG4" access="Read/Write" description="General Purpose Register 0" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="GP" description="General purpose storage." /> + </Register> + <Register start="+0x05C" size="4" name="RTC_AUX" access="Read/Write" description="RTC Auxiliary control register" reset_value="0x10" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="4" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="4" size="1" name="RTC_OSCF" description="RTC Oscillator Fail detect flag. Read: this bit is set if the RTC oscillator stops, and when RTC power is first turned on. An interrupt will occur when this bit is set, the RTC_OSCFEN bit in RTC_AUXEN is a 1, and the RTC interrupt is enabled in the NVIC. Write: writing a 1 to this bit clears the flag." /> + <BitField start="5" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="6" size="1" name="RTC_PDOUT" description="When 0: the RTC_ALARM pin reflects the RTC alarm status. When 1: the RTC_ALARM pin indicates Deep Power-down mode." /> + <BitField start="7" size="25" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x058" size="4" name="RTC_AUXEN" access="Read/Write" description="RTC Auxiliary Enable register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="4" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="4" size="1" name="RTC_OSCFEN" description="Oscillator Fail Detect interrupt enable. When 0: the RTC Oscillator Fail detect interrupt is disabled. When 1: the RTC Oscillator Fail detect interrupt is enabled. See Section 30.6.2.5." /> + <BitField start="5" size="27" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x060" size="4" name="ASEC" access="Read/Write" description="Alarm value for Seconds" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="6" name="SECONDS" description="Seconds value in the range of 0 to 59" /> + <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x64" size="4" name="AMIN" access="Read/Write" description="Alarm value for Minutes" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="6" name="MINUTES" description="Minutes value in the range of 0 to 59" /> + <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x068" size="4" name="AHRS" access="Read/Write" description="Alarm value for Hours" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="5" name="HOURS" description="Hours value in the range of 0 to 23" /> + <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x06C" size="4" name="ADOM" access="Read/Write" description="Alarm value for Day of Month" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="5" name="DOM" description="Day of month value in the range of 1 to 28, 29, 30, or 31 (depending on the month and whether it is a leap year)." /> + <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x070" size="4" name="ADOW" access="Read/Write" description="Alarm value for Day of Week" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="3" name="DOW" description="Day of week value in the range of 0 to 6." /> + <BitField start="3" size="29" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x074" size="4" name="ADOY" access="Read/Write" description="Alarm value for Day of Year" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="9" name="DOY" description="Day of year value in the range of 1 to 365 (366 for leap years)." /> + <BitField start="9" size="23" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x078" size="4" name="AMON" access="Read/Write" description="Alarm value for Months" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="4" name="MONTH" description="Month value in the range of 1 to 12." /> + <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x07C" size="4" name="AYRS" access="Read/Write" description="Alarm value for Year" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="12" name="YEAR" description="Year value in the range of 0 to 4095." /> + <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x084" size="4" name="ERCONTROL" access="Read/Write" description="Event Monitor/Recorder Control register. Contains bits that control actions for the event channels as well as for Event Monitor/Recorder setup." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="INTWAKE_EN0" description="Interrupt and wakeup enable for channel 0."> + <Enum name="NO_INTERRUPT_OR_WAKE" start="0" description="No interrupt or wakeup will be generated by event channel 0." /> + <Enum name="AN_EVENT_IN_CHANNEL_" start="1" description="An event in channel 0 will trigger an (RTC) interrupt and a wake-up request." /> + </BitField> + <BitField start="1" size="1" name="GPCLEAR_EN0" description="Enables automatically clearing the RTC general purpose registers when an event occurs on channel 0."> + <Enum name="NOGPREG" start="0" description="Channel 0 has no influence on the general purpose registers." /> + <Enum name="CLRGPREG" start="1" description="An event in channel 0 will clear the general purpose registers asynchronously." /> + </BitField> + <BitField start="2" size="1" name="POL0" description="Selects the polarity of an event on input pin RTC_EV0."> + <Enum name="NEG" start="0" description="A channel 0 event is defined as a negative edge on RTC_EV0." /> + <Enum name="POS" start="1" description="A channel 0 event is defined as a positive edge on RTC_EV0." /> + </BitField> + <BitField start="3" size="1" name="EV0_INPUT_EN" description="Event enable control for channel 0.[1]"> + <Enum name="DISABLED" start="0" description="Event 0 input is disabled and forced high internally." /> + <Enum name="ENABLED" start="1" description="Event 0 input is enabled." /> + </BitField> + <BitField start="4" size="6" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="10" size="1" name="INTWAKE_EN1" description="Interrupt and wakeup enable for channel 1."> + <Enum name="NO_INTERRUPT_OR_WAKE" start="0" description="No interrupt or wakeup will be generated by event channel 1." /> + <Enum name="WAKEUP" start="1" description="An event in channel 1 will trigger an (RTC) interrupt and a wake-up request." /> + </BitField> + <BitField start="11" size="1" name="GPCLEAR_EN1" description="Enables automatically clearing the RTC general purpose registers when an event occurs on channel 1."> + <Enum name="NOGPREG" start="0" description="Channel 1 has no influence on the general purpose registers." /> + <Enum name="CLRGPREG" start="1" description="A n event in channel 1 will clear the general purpose registers asynchronously." /> + </BitField> + <BitField start="12" size="1" name="POL1" description="Selects the polarity of an event on input pin RTC_EV1."> + <Enum name="NEG" start="0" description="A channel 1 event is defined as a negative edge on RTC_EV1." /> + <Enum name="POS" start="1" description="A channel 1 event is defined as a positive edge on RTC_EV1." /> + </BitField> + <BitField start="13" size="1" name="EV1_INPUT_EN" description="Event enable control for channel 1.[1]"> + <Enum name="DISABLED" start="0" description="Event 1 input is disabled and forced high internally." /> + <Enum name="ENABLED" start="1" description="Event 1 input is enabled." /> + </BitField> + <BitField start="14" size="6" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="20" size="1" name="INTWAKE_EN2" description="Interrupt and wakeup enable for channel 2."> + <Enum name="NO_INTERRUPT_OR_WAKE" start="0" description="No interrupt or wakeup will be generated by event channel 2." /> + <Enum name="WAKEUP" start="1" description="An event in channel 2 will trigger an (RTC) interrupt and a wake-up request." /> + </BitField> + <BitField start="21" size="1" name="GPCLEAR_EN2" description="Enables automatically clearing the RTC general purpose registers when an event occurs on channel 2."> + <Enum name="NOGPREG" start="0" description="Channel 2 has no influence on the general purpose registers." /> + <Enum name="CLRGPREG" start="1" description="An event in channel 2 will clear the general purpose registers asynchronously." /> + </BitField> + <BitField start="22" size="1" name="POL2" description="Selects the polarity of an event on input pin RTC_EV2."> + <Enum name="NEG" start="0" description="A channel 2 event is defined as a negative edge on RTC_EV2." /> + <Enum name="POS" start="1" description="A channel 2 event is defined as a positive edge on RTC_EV2." /> + </BitField> + <BitField start="23" size="1" name="EV2_INPUT_EN" description="Event enable control for channel 2.[1]"> + <Enum name="DISABLED" start="0" description="Event 2 input is disabled and forced high internally." /> + <Enum name="ENABLED" start="1" description="Event 2 input is enabled." /> + </BitField> + <BitField start="24" size="6" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="30" size="2" name="ERMODE" description="Controls enabling the Event Monitor/Recorder and selecting its operating frequency.[2]"> + <Enum name="DISABLED" start="0x0" description="Event Monitor/Recorder clocks are disabled. Operation of the Event Monitor/Recorder is disabled except for asynchronous clearing of GP registers if selected." /> + <Enum name="ENABLE_EVENT_MONITOR16HZ" start="0x1" description="Enable Event Monitor/Recorder and select a 16 Hz sample clock for event input edge detection and glitch suppression. Pulses (in either direction) shorter than 62.5 ms to 125 ms will be filtered out." /> + <Enum name="ENABLE_EVENT_MONITOR64HZ" start="0x2" description="Enable Event Monitor/Recorder and select a 64 Hz sample clock for event input edge detection and glitch suppression. Pulses (in either direction) shorter than 15.6 ms to 31.2 ms will be filtered out." /> + <Enum name="ENABLE_EVENT_MONITOR1KHZ" start="0x3" description="Enable Event Monitor/Recorder and select a 1 kHz sample clock for event input edge detection and glitch suppression. Pulses (in either direction) shorter than 1 ms to 2 ms will be filtered out." /> + </BitField> + </Register> + <Register start="+0x080" size="4" name="ERSTATUS" access="Read/Write" description="Event Monitor/Recorder Status register. Contains status flags for event channels and other Event Monitor/Recorder conditions." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="EV0" description="Event flag for channel 0 (RTC_EV0 pin). Set at the end of any second if there has been an event during the preceding second. This bit is cleared by writing a 1 to it. Writing 0 has no effect."> + <Enum name="NO_EVENT_CHANGE_ON_C" start="0" description="No event change on channel 0." /> + <Enum name="AT_LEAST_ONE_EVENT_H" start="1" description="At least one event has occurred on channel 0." /> + </BitField> + <BitField start="1" size="1" name="EV1" description="Event flag for channel 1 (RTC_EV1 pin). Set at the end of any second if there has been an event during the preceding second. This bit is cleared by writing a 1 to it. Writing 0 has no effect."> + <Enum name="NO_EVENT_CHANGE_ON_C" start="0" description="No event change on channel 1." /> + <Enum name="AT_LEAST_ONE_EVENT_H" start="1" description="At least one event has occurred on channel 1." /> + </BitField> + <BitField start="2" size="1" name="EV2" description="Event flag for channel 2 (RTC_EV2 pin). Set at the end of any second if there has been an event during the preceding second. This bit is cleared by writing a 1 to it. Writing 0 has no effect."> + <Enum name="NO_EVENT_CHANGE_ON_C" start="0" description="No event change on channel 2." /> + <Enum name="AT_LEAST_ONE_EVENT_H" start="1" description="At least one event has occurred on channel 2." /> + </BitField> + <BitField start="3" size="1" name="GP_CLEARED" description="General purpose register asynchronous clear flag. This bit is cleared by writing a 1 to it. Writing 0 has no effect."> + <Enum name="NOGPCLR" start="0" description="General purpose registers have not been asynchronous cleared." /> + <Enum name="GPCLR" start="1" description="General purpose registers have been asynchronous cleared." /> + </BitField> + <BitField start="4" size="27" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="31" size="1" name="WAKEUP" description="Interrupt/wakeup request flag (Read-only). This bit is cleared by writing a 1 to it. Writing 0 has no effect."> + <Enum name="NO_INTERRUPTWAKEUP_" start="0" description="No interrupt/wakeup request is pending" /> + <Enum name="INTWAKEUP_PEND" start="1" description="An interrupt/wakeup request is pending." /> + </BitField> + </Register> + <Register start="+0x088" size="4" name="ERCOUNTERS" access="ReadOnly" description="Event Monitor/Recorder Counters register. Allows reading the counters associated with the event channels." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="COUNTER0" description="Value of the counter for event 0. If the counter reaches full count (the value 7), it remains there if additional events occur. This counter is cleared when the corresponding EVx bit in the ERSTATUS register is cleared by software." /> + <BitField start="3" size="5" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + <BitField start="8" size="3" name="COUNTER1" description="Value of the counter for event 1. See description for COUNTER0." /> + <BitField start="11" size="5" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + <BitField start="16" size="3" name="COUNTER2" description="Value of the counter for event 2. See description for COUNTER0." /> + <BitField start="19" size="13" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x090+0" size="4" name="ERFIRSTSTAMP0" access="ReadOnly" description="Event Monitor/Recorder First Stamp register for channel 0. Retains the time stamp for the first event on channel 0." reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="6" name="SEC" description="Seconds value in the range of 0 to 59." /> + <BitField start="6" size="6" name="MIN" description="Minutes value in the range of 0 to 59." /> + <BitField start="12" size="5" name="HOUR" description="Hours value in the range of 0 to 23." /> + <BitField start="17" size="9" name="DOY" description="Day of Year value in the range of 1 to 366." /> + <BitField start="26" size="6" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x090+4" size="4" name="ERFIRSTSTAMP1" access="ReadOnly" description="Event Monitor/Recorder First Stamp register for channel 0. Retains the time stamp for the first event on channel 0." reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="6" name="SEC" description="Seconds value in the range of 0 to 59." /> + <BitField start="6" size="6" name="MIN" description="Minutes value in the range of 0 to 59." /> + <BitField start="12" size="5" name="HOUR" description="Hours value in the range of 0 to 23." /> + <BitField start="17" size="9" name="DOY" description="Day of Year value in the range of 1 to 366." /> + <BitField start="26" size="6" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x090+8" size="4" name="ERFIRSTSTAMP2" access="ReadOnly" description="Event Monitor/Recorder First Stamp register for channel 0. Retains the time stamp for the first event on channel 0." reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="6" name="SEC" description="Seconds value in the range of 0 to 59." /> + <BitField start="6" size="6" name="MIN" description="Minutes value in the range of 0 to 59." /> + <BitField start="12" size="5" name="HOUR" description="Hours value in the range of 0 to 23." /> + <BitField start="17" size="9" name="DOY" description="Day of Year value in the range of 1 to 366." /> + <BitField start="26" size="6" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x0A0+0" size="4" name="ERLASTSTAMP0" access="ReadOnly" description="Event Monitor/Recorder Last Stamp register for channel 0. Retains the time stamp for the last (i.e. most recent) event on channel 0." reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="6" name="SEC" description="Seconds value in the range of 0 to 59." /> + <BitField start="6" size="6" name="MIN" description="Minutes value in the range of 0 to 59." /> + <BitField start="12" size="5" name="HOUR" description="Hours value in the range of 0 to 23." /> + <BitField start="17" size="9" name="DOY" description="Day of Year value in the range of 1 to 366." /> + <BitField start="26" size="6" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x0A0+4" size="4" name="ERLASTSTAMP1" access="ReadOnly" description="Event Monitor/Recorder Last Stamp register for channel 0. Retains the time stamp for the last (i.e. most recent) event on channel 0." reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="6" name="SEC" description="Seconds value in the range of 0 to 59." /> + <BitField start="6" size="6" name="MIN" description="Minutes value in the range of 0 to 59." /> + <BitField start="12" size="5" name="HOUR" description="Hours value in the range of 0 to 23." /> + <BitField start="17" size="9" name="DOY" description="Day of Year value in the range of 1 to 366." /> + <BitField start="26" size="6" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x0A0+8" size="4" name="ERLASTSTAMP2" access="ReadOnly" description="Event Monitor/Recorder Last Stamp register for channel 0. Retains the time stamp for the last (i.e. most recent) event on channel 0." reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="6" name="SEC" description="Seconds value in the range of 0 to 59." /> + <BitField start="6" size="6" name="MIN" description="Minutes value in the range of 0 to 59." /> + <BitField start="12" size="5" name="HOUR" description="Hours value in the range of 0 to 23." /> + <BitField start="17" size="9" name="DOY" description="Day of Year value in the range of 1 to 366." /> + <BitField start="26" size="6" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + </RegisterGroup> + <RegisterGroup name="GPIOINT" start="0x40028080" description="GPIO"> + <Register start="+0x000" size="4" name="STATUS" access="ReadOnly" description="GPIO overall Interrupt Status." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="P0Int" description="Port 0 GPIO interrupt pending."> + <Enum name="NO_PENDING_INTERRUPT" start="0" description="No pending interrupts on Port 0." /> + <Enum name="AT_LEAST_ONE_PENDING" start="1" description="At least one pending interrupt on Port 0." /> + </BitField> + <BitField start="1" size="1" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + <BitField start="2" size="1" name="P2Int" description="Port 2 GPIO interrupt pending."> + <Enum name="NO_PENDING_INTERRUPT" start="0" description="No pending interrupts on Port 2." /> + <Enum name="AT_LEAST_ONE_PENDING" start="1" description="At least one pending interrupt on Port 2." /> + </BitField> + <BitField start="2" size="30" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x004" size="4" name="STATR0" access="ReadOnly" description="GPIO Interrupt Status for Rising edge for Port 0." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="P0_0REI" description="Status of Rising Edge Interrupt for P0[0]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." /> + <BitField start="1" size="1" name="P0_1REI" description="Status of Rising Edge Interrupt for P0[1]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." /> + <BitField start="2" size="1" name="P0_2REI" description="Status of Rising Edge Interrupt for P0[2]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." /> + <BitField start="3" size="1" name="P0_3REI" description="Status of Rising Edge Interrupt for P0[3]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." /> + <BitField start="4" size="1" name="P0_4REI" description="Status of Rising Edge Interrupt for P0[4]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." /> + <BitField start="5" size="1" name="P0_5REI" description="Status of Rising Edge Interrupt for P0[5]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." /> + <BitField start="6" size="1" name="P0_6REI" description="Status of Rising Edge Interrupt for P0[6]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." /> + <BitField start="7" size="1" name="P0_7REI" description="Status of Rising Edge Interrupt for P0[7]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." /> + <BitField start="8" size="1" name="P0_8REI" description="Status of Rising Edge Interrupt for P0[8]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." /> + <BitField start="9" size="1" name="P0_9REI" description="Status of Rising Edge Interrupt for P0[9]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." /> + <BitField start="10" size="1" name="P0_10REI" description="Status of Rising Edge Interrupt for P0[10]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." /> + <BitField start="11" size="1" name="P0_11REI" description="Status of Rising Edge Interrupt for P0[11]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." /> + <BitField start="12" size="1" name="P0_12REI" description="Status of Rising Edge Interrupt for P0[12]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." /> + <BitField start="13" size="1" name="P0_13REI" description="Status of Rising Edge Interrupt for P0[13]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." /> + <BitField start="14" size="1" name="P0_14REI" description="Status of Rising Edge Interrupt for P0[14]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." /> + <BitField start="15" size="1" name="P0_15REI" description="Status of Rising Edge Interrupt for P0[15]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." /> + <BitField start="16" size="1" name="P0_16REI" description="Status of Rising Edge Interrupt for P0[16]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." /> + <BitField start="17" size="1" name="P0_17REI" description="Status of Rising Edge Interrupt for P0[17]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." /> + <BitField start="18" size="1" name="P0_18REI" description="Status of Rising Edge Interrupt for P0[18]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." /> + <BitField start="19" size="1" name="P0_19REI" description="Status of Rising Edge Interrupt for P0[19]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." /> + <BitField start="20" size="1" name="P0_20REI" description="Status of Rising Edge Interrupt for P0[20]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." /> + <BitField start="21" size="1" name="P0_21REI" description="Status of Rising Edge Interrupt for P0[21]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." /> + <BitField start="22" size="1" name="P0_22REI" description="Status of Rising Edge Interrupt for P0[22]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." /> + <BitField start="23" size="1" name="P0_23REI" description="Status of Rising Edge Interrupt for P0[23]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." /> + <BitField start="24" size="1" name="P0_24REI" description="Status of Rising Edge Interrupt for P0[24]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." /> + <BitField start="25" size="1" name="P0_25REI" description="Status of Rising Edge Interrupt for P0[25]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." /> + <BitField start="26" size="1" name="P0_26REI" description="Status of Rising Edge Interrupt for P0[26]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." /> + <BitField start="27" size="1" name="P0_27REI" description="Status of Rising Edge Interrupt for P0[27]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." /> + <BitField start="28" size="1" name="P0_28REI" description="Status of Rising Edge Interrupt for P0[28]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." /> + <BitField start="29" size="1" name="P0_29REI" description="Status of Rising Edge Interrupt for P0[29]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." /> + <BitField start="30" size="1" name="P0_30REI" description="Status of Rising Edge Interrupt for P0[30]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." /> + <BitField start="31" size="1" name="P0_31REI" description="Status of Rising Edge Interrupt for P0[31]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." /> + </Register> + <Register start="+0x008" size="4" name="STATF0" access="ReadOnly" description="GPIO Interrupt Status for Falling edge for Port 0." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="P0_0FEI" description="Status of Falling Edge Interrupt for P0[0]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." /> + <BitField start="1" size="1" name="P0_1FEI" description="Status of Falling Edge Interrupt for P0[1]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." /> + <BitField start="2" size="1" name="P0_2FEI" description="Status of Falling Edge Interrupt for P0[2]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." /> + <BitField start="3" size="1" name="P0_3FEI" description="Status of Falling Edge Interrupt for P0[3]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." /> + <BitField start="4" size="1" name="P0_4FEI" description="Status of Falling Edge Interrupt for P0[4]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." /> + <BitField start="5" size="1" name="P0_5FEI" description="Status of Falling Edge Interrupt for P0[5]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." /> + <BitField start="6" size="1" name="P0_6FEI" description="Status of Falling Edge Interrupt for P0[6]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." /> + <BitField start="7" size="1" name="P0_7FEI" description="Status of Falling Edge Interrupt for P0[7]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." /> + <BitField start="8" size="1" name="P0_8FEI" description="Status of Falling Edge Interrupt for P0[8]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." /> + <BitField start="9" size="1" name="P0_9FEI" description="Status of Falling Edge Interrupt for P0[9]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." /> + <BitField start="10" size="1" name="P0_10FEI" description="Status of Falling Edge Interrupt for P0[10]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." /> + <BitField start="11" size="1" name="P0_11FEI" description="Status of Falling Edge Interrupt for P0[11]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." /> + <BitField start="12" size="1" name="P0_12FEI" description="Status of Falling Edge Interrupt for P0[12]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." /> + <BitField start="13" size="1" name="P0_13FEI" description="Status of Falling Edge Interrupt for P0[13]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." /> + <BitField start="14" size="1" name="P0_14FEI" description="Status of Falling Edge Interrupt for P0[14]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." /> + <BitField start="15" size="1" name="P0_15FEI" description="Status of Falling Edge Interrupt for P0[15]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." /> + <BitField start="16" size="1" name="P0_16FEI" description="Status of Falling Edge Interrupt for P0[16]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." /> + <BitField start="17" size="1" name="P0_17FEI" description="Status of Falling Edge Interrupt for P0[17]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." /> + <BitField start="18" size="1" name="P0_18FEI" description="Status of Falling Edge Interrupt for P0[18]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." /> + <BitField start="19" size="1" name="P0_19FEI" description="Status of Falling Edge Interrupt for P0[19]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." /> + <BitField start="20" size="1" name="P0_20FEI" description="Status of Falling Edge Interrupt for P0[20]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." /> + <BitField start="21" size="1" name="P0_21FEI" description="Status of Falling Edge Interrupt for P0[21]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." /> + <BitField start="22" size="1" name="P0_22FEI" description="Status of Falling Edge Interrupt for P0[22]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." /> + <BitField start="23" size="1" name="P0_23FEI" description="Status of Falling Edge Interrupt for P0[23]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." /> + <BitField start="24" size="1" name="P0_24FEI" description="Status of Falling Edge Interrupt for P0[24]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." /> + <BitField start="25" size="1" name="P0_25FEI" description="Status of Falling Edge Interrupt for P0[25]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." /> + <BitField start="26" size="1" name="P0_26FEI" description="Status of Falling Edge Interrupt for P0[26]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." /> + <BitField start="27" size="1" name="P0_27FEI" description="Status of Falling Edge Interrupt for P0[27]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." /> + <BitField start="28" size="1" name="P0_28FEI" description="Status of Falling Edge Interrupt for P0[28]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." /> + <BitField start="29" size="1" name="P0_29FEI" description="Status of Falling Edge Interrupt for P0[29]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." /> + <BitField start="30" size="1" name="P0_30FEI" description="Status of Falling Edge Interrupt for P0[30]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." /> + <BitField start="31" size="1" name="P0_31FEI" description="Status of Falling Edge Interrupt for P0[31]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." /> + </Register> + <Register start="+0x00C" size="4" name="CLR0" access="WriteOnly" description="GPIO Interrupt Clear." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="P0_0CI" description="Clear GPIO port Interrupts for P0[0]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." /> + <BitField start="1" size="1" name="P0_1CI" description="Clear GPIO port Interrupts for P0[1]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." /> + <BitField start="2" size="1" name="P0_2CI" description="Clear GPIO port Interrupts for P0[2]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." /> + <BitField start="3" size="1" name="P0_3CI" description="Clear GPIO port Interrupts for P0[3]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." /> + <BitField start="4" size="1" name="P0_4CI" description="Clear GPIO port Interrupts for P0[4]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." /> + <BitField start="5" size="1" name="P0_5CI" description="Clear GPIO port Interrupts for P0[5]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." /> + <BitField start="6" size="1" name="P0_6CI" description="Clear GPIO port Interrupts for P0[6]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." /> + <BitField start="7" size="1" name="P0_7CI" description="Clear GPIO port Interrupts for P0[7]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." /> + <BitField start="8" size="1" name="P0_8CI" description="Clear GPIO port Interrupts for P0[8]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." /> + <BitField start="9" size="1" name="P0_9CI" description="Clear GPIO port Interrupts for P0[9]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." /> + <BitField start="10" size="1" name="P0_10CI" description="Clear GPIO port Interrupts for P0[10]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." /> + <BitField start="11" size="1" name="P0_11CI" description="Clear GPIO port Interrupts for P0[11]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." /> + <BitField start="12" size="1" name="P0_12CI" description="Clear GPIO port Interrupts for P0[12]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." /> + <BitField start="13" size="1" name="P0_13CI" description="Clear GPIO port Interrupts for P0[13]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." /> + <BitField start="14" size="1" name="P0_14CI" description="Clear GPIO port Interrupts for P0[14]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." /> + <BitField start="15" size="1" name="P0_15CI" description="Clear GPIO port Interrupts for P0[15]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." /> + <BitField start="16" size="1" name="P0_16CI" description="Clear GPIO port Interrupts for P0[16]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." /> + <BitField start="17" size="1" name="P0_17CI" description="Clear GPIO port Interrupts for P0[17]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." /> + <BitField start="18" size="1" name="P0_18CI" description="Clear GPIO port Interrupts for P0[18]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." /> + <BitField start="19" size="1" name="P0_19CI" description="Clear GPIO port Interrupts for P0[19]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." /> + <BitField start="20" size="1" name="P0_20CI" description="Clear GPIO port Interrupts for P0[20]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." /> + <BitField start="21" size="1" name="P0_21CI" description="Clear GPIO port Interrupts for P0[21]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." /> + <BitField start="22" size="1" name="P0_22CI" description="Clear GPIO port Interrupts for P0[22]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." /> + <BitField start="23" size="1" name="P0_23CI" description="Clear GPIO port Interrupts for P0[23]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." /> + <BitField start="24" size="1" name="P0_24CI" description="Clear GPIO port Interrupts for P0[24]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." /> + <BitField start="25" size="1" name="P0_25CI" description="Clear GPIO port Interrupts for P0[25]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." /> + <BitField start="26" size="1" name="P0_26CI" description="Clear GPIO port Interrupts for P0[26]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." /> + <BitField start="27" size="1" name="P0_27CI" description="Clear GPIO port Interrupts for P0[27]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." /> + <BitField start="28" size="1" name="P0_28CI" description="Clear GPIO port Interrupts for P0[28]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." /> + <BitField start="29" size="1" name="P0_29CI" description="Clear GPIO port Interrupts for P0[29]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." /> + <BitField start="30" size="1" name="P0_30CI" description="Clear GPIO port Interrupts for P0[30]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." /> + <BitField start="31" size="1" name="P0_31CI" description="Clear GPIO port Interrupts for P0[31]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." /> + </Register> + <Register start="+0x010" size="4" name="ENR0" access="Read/Write" description="GPIO Interrupt Enable for Rising edge for Port 0." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="P0_0ER" description="Enable rising edge interrupt for P0[0]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." /> + <BitField start="1" size="1" name="P0_1ER" description="Enable rising edge interrupt for P0[1]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." /> + <BitField start="2" size="1" name="P0_2ER" description="Enable rising edge interrupt for P0[2]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." /> + <BitField start="3" size="1" name="P0_3ER" description="Enable rising edge interrupt for P0[3]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." /> + <BitField start="4" size="1" name="P0_4ER" description="Enable rising edge interrupt for P0[4]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." /> + <BitField start="5" size="1" name="P0_5ER" description="Enable rising edge interrupt for P0[5]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." /> + <BitField start="6" size="1" name="P0_6ER" description="Enable rising edge interrupt for P0[6]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." /> + <BitField start="7" size="1" name="P0_7ER" description="Enable rising edge interrupt for P0[7]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." /> + <BitField start="8" size="1" name="P0_8ER" description="Enable rising edge interrupt for P0[8]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." /> + <BitField start="9" size="1" name="P0_9ER" description="Enable rising edge interrupt for P0[9]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." /> + <BitField start="10" size="1" name="P0_10ER" description="Enable rising edge interrupt for P0[10]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." /> + <BitField start="11" size="1" name="P0_11ER" description="Enable rising edge interrupt for P0[11]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." /> + <BitField start="12" size="1" name="P0_12ER" description="Enable rising edge interrupt for P0[12]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." /> + <BitField start="13" size="1" name="P0_13ER" description="Enable rising edge interrupt for P0[13]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." /> + <BitField start="14" size="1" name="P0_14ER" description="Enable rising edge interrupt for P0[14]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." /> + <BitField start="15" size="1" name="P0_15ER" description="Enable rising edge interrupt for P0[15]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." /> + <BitField start="16" size="1" name="P0_16ER" description="Enable rising edge interrupt for P0[16]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." /> + <BitField start="17" size="1" name="P0_17ER" description="Enable rising edge interrupt for P0[17]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." /> + <BitField start="18" size="1" name="P0_18ER" description="Enable rising edge interrupt for P0[18]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." /> + <BitField start="19" size="1" name="P0_19ER" description="Enable rising edge interrupt for P0[19]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." /> + <BitField start="20" size="1" name="P0_20ER" description="Enable rising edge interrupt for P0[20]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." /> + <BitField start="21" size="1" name="P0_21ER" description="Enable rising edge interrupt for P0[21]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." /> + <BitField start="22" size="1" name="P0_22ER" description="Enable rising edge interrupt for P0[22]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." /> + <BitField start="23" size="1" name="P0_23ER" description="Enable rising edge interrupt for P0[23]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." /> + <BitField start="24" size="1" name="P0_24ER" description="Enable rising edge interrupt for P0[24]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." /> + <BitField start="25" size="1" name="P0_25ER" description="Enable rising edge interrupt for P0[25]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." /> + <BitField start="26" size="1" name="P0_26ER" description="Enable rising edge interrupt for P0[26]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." /> + <BitField start="27" size="1" name="P0_27ER" description="Enable rising edge interrupt for P0[27]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." /> + <BitField start="28" size="1" name="P0_28ER" description="Enable rising edge interrupt for P0[28]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." /> + <BitField start="29" size="1" name="P0_29ER" description="Enable rising edge interrupt for P0[29]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." /> + <BitField start="30" size="1" name="P0_30ER" description="Enable rising edge interrupt for P0[30]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." /> + <BitField start="31" size="1" name="P0_31ER" description="Enable rising edge interrupt for P0[31]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." /> + </Register> + <Register start="+0x014" size="4" name="ENF0" access="Read/Write" description="GPIO Interrupt Enable for Falling edge for Port 0." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="P0_0EF" description="Enable falling edge interrupt for P0[0]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." /> + <BitField start="1" size="1" name="P0_1EF" description="Enable falling edge interrupt for P0[1]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." /> + <BitField start="2" size="1" name="P0_2EF" description="Enable falling edge interrupt for P0[2]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." /> + <BitField start="3" size="1" name="P0_3EF" description="Enable falling edge interrupt for P0[3]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." /> + <BitField start="4" size="1" name="P0_4EF" description="Enable falling edge interrupt for P0[4]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." /> + <BitField start="5" size="1" name="P0_5EF" description="Enable falling edge interrupt for P0[5]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." /> + <BitField start="6" size="1" name="P0_6EF" description="Enable falling edge interrupt for P0[6]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." /> + <BitField start="7" size="1" name="P0_7EF" description="Enable falling edge interrupt for P0[7]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." /> + <BitField start="8" size="1" name="P0_8EF" description="Enable falling edge interrupt for P0[8]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." /> + <BitField start="9" size="1" name="P0_9EF" description="Enable falling edge interrupt for P0[9]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." /> + <BitField start="10" size="1" name="P0_10EF" description="Enable falling edge interrupt for P0[10]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." /> + <BitField start="11" size="1" name="P0_11EF" description="Enable falling edge interrupt for P0[11]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." /> + <BitField start="12" size="1" name="P0_12EF" description="Enable falling edge interrupt for P0[12]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." /> + <BitField start="13" size="1" name="P0_13EF" description="Enable falling edge interrupt for P0[13]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." /> + <BitField start="14" size="1" name="P0_14EF" description="Enable falling edge interrupt for P0[14]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." /> + <BitField start="15" size="1" name="P0_15EF" description="Enable falling edge interrupt for P0[15]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." /> + <BitField start="16" size="1" name="P0_16EF" description="Enable falling edge interrupt for P0[16]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." /> + <BitField start="17" size="1" name="P0_17EF" description="Enable falling edge interrupt for P0[17]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." /> + <BitField start="18" size="1" name="P0_18EF" description="Enable falling edge interrupt for P0[18]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." /> + <BitField start="19" size="1" name="P0_19EF" description="Enable falling edge interrupt for P0[19]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." /> + <BitField start="20" size="1" name="P0_20EF" description="Enable falling edge interrupt for P0[20]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." /> + <BitField start="21" size="1" name="P0_21EF" description="Enable falling edge interrupt for P0[21]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." /> + <BitField start="22" size="1" name="P0_22EF" description="Enable falling edge interrupt for P0[22]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." /> + <BitField start="23" size="1" name="P0_23EF" description="Enable falling edge interrupt for P0[23]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." /> + <BitField start="24" size="1" name="P0_24EF" description="Enable falling edge interrupt for P0[24]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." /> + <BitField start="25" size="1" name="P0_25EF" description="Enable falling edge interrupt for P0[25]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." /> + <BitField start="26" size="1" name="P0_26EF" description="Enable falling edge interrupt for P0[26]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." /> + <BitField start="27" size="1" name="P0_27EF" description="Enable falling edge interrupt for P0[27]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." /> + <BitField start="28" size="1" name="P0_28EF" description="Enable falling edge interrupt for P0[28]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." /> + <BitField start="29" size="1" name="P0_29EF" description="Enable falling edge interrupt for P0[29]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." /> + <BitField start="30" size="1" name="P0_30EF" description="Enable falling edge interrupt for P0[30]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." /> + <BitField start="31" size="1" name="P0_31EF" description="Enable falling edge interrupt for P0[31]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." /> + </Register> + <Register start="+0x024" size="4" name="STATR2" access="ReadOnly" description="GPIO Interrupt Status for Rising edge for Port 0." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="P2_0REI" description="Status of Rising Edge Interrupt for P2[0]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." /> + <BitField start="1" size="1" name="P2_1REI" description="Status of Rising Edge Interrupt for P2[1]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." /> + <BitField start="2" size="1" name="P2_2REI" description="Status of Rising Edge Interrupt for P2[2]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." /> + <BitField start="3" size="1" name="P2_3REI" description="Status of Rising Edge Interrupt for P2[3]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." /> + <BitField start="4" size="1" name="P2_4REI" description="Status of Rising Edge Interrupt for P2[4]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." /> + <BitField start="5" size="1" name="P2_5REI" description="Status of Rising Edge Interrupt for P2[5]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." /> + <BitField start="6" size="1" name="P2_6REI" description="Status of Rising Edge Interrupt for P2[6]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." /> + <BitField start="7" size="1" name="P2_7REI" description="Status of Rising Edge Interrupt for P2[7]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." /> + <BitField start="8" size="1" name="P2_8REI" description="Status of Rising Edge Interrupt for P2[8]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." /> + <BitField start="9" size="1" name="P2_9REI" description="Status of Rising Edge Interrupt for P2[9]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." /> + <BitField start="10" size="1" name="P2_10REI" description="Status of Rising Edge Interrupt for P2[10]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." /> + <BitField start="11" size="1" name="P2_11REI" description="Status of Rising Edge Interrupt for P2[11]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." /> + <BitField start="12" size="1" name="P2_12REI" description="Status of Rising Edge Interrupt for P2[12]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." /> + <BitField start="13" size="1" name="P2_13REI" description="Status of Rising Edge Interrupt for P2[13]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." /> + <BitField start="14" size="1" name="P2_14REI" description="Status of Rising Edge Interrupt for P2[14]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." /> + <BitField start="15" size="1" name="P2_15REI" description="Status of Rising Edge Interrupt for P2[15]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." /> + <BitField start="16" size="1" name="P2_16REI" description="Status of Rising Edge Interrupt for P2[16]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." /> + <BitField start="17" size="1" name="P2_17REI" description="Status of Rising Edge Interrupt for P2[17]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." /> + <BitField start="18" size="1" name="P2_18REI" description="Status of Rising Edge Interrupt for P2[18]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." /> + <BitField start="19" size="1" name="P2_19REI" description="Status of Rising Edge Interrupt for P2[19]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." /> + <BitField start="20" size="1" name="P2_20REI" description="Status of Rising Edge Interrupt for P2[20]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." /> + <BitField start="21" size="1" name="P2_21REI" description="Status of Rising Edge Interrupt for P2[21]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." /> + <BitField start="22" size="1" name="P2_22REI" description="Status of Rising Edge Interrupt for P2[22]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." /> + <BitField start="23" size="1" name="P2_23REI" description="Status of Rising Edge Interrupt for P2[23]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." /> + <BitField start="24" size="1" name="P2_24REI" description="Status of Rising Edge Interrupt for P2[24]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." /> + <BitField start="25" size="1" name="P2_25REI" description="Status of Rising Edge Interrupt for P2[25]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." /> + <BitField start="26" size="1" name="P2_26REI" description="Status of Rising Edge Interrupt for P2[26]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." /> + <BitField start="27" size="1" name="P2_27REI" description="Status of Rising Edge Interrupt for P2[27]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." /> + <BitField start="28" size="1" name="P2_28REI" description="Status of Rising Edge Interrupt for P2[28]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." /> + <BitField start="29" size="1" name="P2_29REI" description="Status of Rising Edge Interrupt for P2[29]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." /> + <BitField start="30" size="1" name="P2_30REI" description="Status of Rising Edge Interrupt for P2[30]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." /> + <BitField start="31" size="1" name="P2_31REI" description="Status of Rising Edge Interrupt for P2[31]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." /> + </Register> + <Register start="+0x028" size="4" name="STATF2" access="ReadOnly" description="GPIO Interrupt Status for Falling edge for Port 0." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="P2_0FEI" description="Status of Falling Edge Interrupt for P2[0]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." /> + <BitField start="1" size="1" name="P2_1FEI" description="Status of Falling Edge Interrupt for P2[1]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." /> + <BitField start="2" size="1" name="P2_2FEI" description="Status of Falling Edge Interrupt for P2[2]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." /> + <BitField start="3" size="1" name="P2_3FEI" description="Status of Falling Edge Interrupt for P2[3]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." /> + <BitField start="4" size="1" name="P2_4FEI" description="Status of Falling Edge Interrupt for P2[4]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." /> + <BitField start="5" size="1" name="P2_5FEI" description="Status of Falling Edge Interrupt for P2[5]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." /> + <BitField start="6" size="1" name="P2_6FEI" description="Status of Falling Edge Interrupt for P2[6]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." /> + <BitField start="7" size="1" name="P2_7FEI" description="Status of Falling Edge Interrupt for P2[7]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." /> + <BitField start="8" size="1" name="P2_8FEI" description="Status of Falling Edge Interrupt for P2[8]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." /> + <BitField start="9" size="1" name="P2_9FEI" description="Status of Falling Edge Interrupt for P2[9]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." /> + <BitField start="10" size="1" name="P2_10FEI" description="Status of Falling Edge Interrupt for P2[10]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." /> + <BitField start="11" size="1" name="P2_11FEI" description="Status of Falling Edge Interrupt for P2[11]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." /> + <BitField start="12" size="1" name="P2_12FEI" description="Status of Falling Edge Interrupt for P2[12]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." /> + <BitField start="13" size="1" name="P2_13FEI" description="Status of Falling Edge Interrupt for P2[13]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." /> + <BitField start="14" size="1" name="P2_14FEI" description="Status of Falling Edge Interrupt for P2[14]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." /> + <BitField start="15" size="1" name="P2_15FEI" description="Status of Falling Edge Interrupt for P2[15]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." /> + <BitField start="16" size="1" name="P2_16FEI" description="Status of Falling Edge Interrupt for P2[16]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." /> + <BitField start="17" size="1" name="P2_17FEI" description="Status of Falling Edge Interrupt for P2[17]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." /> + <BitField start="18" size="1" name="P2_18FEI" description="Status of Falling Edge Interrupt for P2[18]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." /> + <BitField start="19" size="1" name="P2_19FEI" description="Status of Falling Edge Interrupt for P2[19]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." /> + <BitField start="20" size="1" name="P2_20FEI" description="Status of Falling Edge Interrupt for P2[20]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." /> + <BitField start="21" size="1" name="P2_21FEI" description="Status of Falling Edge Interrupt for P2[21]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." /> + <BitField start="22" size="1" name="P2_22FEI" description="Status of Falling Edge Interrupt for P2[22]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." /> + <BitField start="23" size="1" name="P2_23FEI" description="Status of Falling Edge Interrupt for P2[23]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." /> + <BitField start="24" size="1" name="P2_24FEI" description="Status of Falling Edge Interrupt for P2[24]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." /> + <BitField start="25" size="1" name="P2_25FEI" description="Status of Falling Edge Interrupt for P2[25]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." /> + <BitField start="26" size="1" name="P2_26FEI" description="Status of Falling Edge Interrupt for P2[26]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." /> + <BitField start="27" size="1" name="P2_27FEI" description="Status of Falling Edge Interrupt for P2[27]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." /> + <BitField start="28" size="1" name="P2_28FEI" description="Status of Falling Edge Interrupt for P2[28]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." /> + <BitField start="29" size="1" name="P2_29FEI" description="Status of Falling Edge Interrupt for P2[29]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." /> + <BitField start="30" size="1" name="P2_30FEI" description="Status of Falling Edge Interrupt for P2[30]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." /> + <BitField start="31" size="1" name="P2_31FEI" description="Status of Falling Edge Interrupt for P2[31]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." /> + </Register> + <Register start="+0x02C" size="4" name="CLR2" access="WriteOnly" description="GPIO Interrupt Clear." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="P2_0CI" description="Clear GPIO port Interrupts for P2[0]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." /> + <BitField start="1" size="1" name="P2_1CI" description="Clear GPIO port Interrupts for P2[1]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." /> + <BitField start="2" size="1" name="P2_2CI" description="Clear GPIO port Interrupts for P2[2]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." /> + <BitField start="3" size="1" name="P2_3CI" description="Clear GPIO port Interrupts for P2[3]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." /> + <BitField start="4" size="1" name="P2_4CI" description="Clear GPIO port Interrupts for P2[4]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." /> + <BitField start="5" size="1" name="P2_5CI" description="Clear GPIO port Interrupts for P2[5]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." /> + <BitField start="6" size="1" name="P2_6CI" description="Clear GPIO port Interrupts for P2[6]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." /> + <BitField start="7" size="1" name="P2_7CI" description="Clear GPIO port Interrupts for P2[7]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." /> + <BitField start="8" size="1" name="P2_8CI" description="Clear GPIO port Interrupts for P2[8]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." /> + <BitField start="9" size="1" name="P2_9CI" description="Clear GPIO port Interrupts for P2[9]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." /> + <BitField start="10" size="1" name="P2_10CI" description="Clear GPIO port Interrupts for P2[10]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." /> + <BitField start="11" size="1" name="P2_11CI" description="Clear GPIO port Interrupts for P2[11]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." /> + <BitField start="12" size="1" name="P2_12CI" description="Clear GPIO port Interrupts for P2[12]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." /> + <BitField start="13" size="1" name="P2_13CI" description="Clear GPIO port Interrupts for P2[13]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." /> + <BitField start="14" size="1" name="P2_14CI" description="Clear GPIO port Interrupts for P2[14]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." /> + <BitField start="15" size="1" name="P2_15CI" description="Clear GPIO port Interrupts for P2[15]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." /> + <BitField start="16" size="1" name="P2_16CI" description="Clear GPIO port Interrupts for P2[16]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." /> + <BitField start="17" size="1" name="P2_17CI" description="Clear GPIO port Interrupts for P2[17]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." /> + <BitField start="18" size="1" name="P2_18CI" description="Clear GPIO port Interrupts for P2[18]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." /> + <BitField start="19" size="1" name="P2_19CI" description="Clear GPIO port Interrupts for P2[19]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." /> + <BitField start="20" size="1" name="P2_20CI" description="Clear GPIO port Interrupts for P2[20]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." /> + <BitField start="21" size="1" name="P2_21CI" description="Clear GPIO port Interrupts for P2[21]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." /> + <BitField start="22" size="1" name="P2_22CI" description="Clear GPIO port Interrupts for P2[22]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." /> + <BitField start="23" size="1" name="P2_23CI" description="Clear GPIO port Interrupts for P2[23]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." /> + <BitField start="24" size="1" name="P2_24CI" description="Clear GPIO port Interrupts for P2[24]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." /> + <BitField start="25" size="1" name="P2_25CI" description="Clear GPIO port Interrupts for P2[25]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." /> + <BitField start="26" size="1" name="P2_26CI" description="Clear GPIO port Interrupts for P2[26]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." /> + <BitField start="27" size="1" name="P2_27CI" description="Clear GPIO port Interrupts for P2[27]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." /> + <BitField start="28" size="1" name="P2_28CI" description="Clear GPIO port Interrupts for P2[28]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." /> + <BitField start="29" size="1" name="P2_29CI" description="Clear GPIO port Interrupts for P2[29]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." /> + <BitField start="30" size="1" name="P2_30CI" description="Clear GPIO port Interrupts for P2[30]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." /> + <BitField start="31" size="1" name="P2_31CI" description="Clear GPIO port Interrupts for P2[31]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." /> + </Register> + <Register start="+0x030" size="4" name="ENR2" access="Read/Write" description="GPIO Interrupt Enable for Rising edge for Port 0." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="P2_0ER" description="Enable rising edge interrupt for P2[0]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." /> + <BitField start="1" size="1" name="P2_1ER" description="Enable rising edge interrupt for P2[1]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." /> + <BitField start="2" size="1" name="P2_2ER" description="Enable rising edge interrupt for P2[2]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." /> + <BitField start="3" size="1" name="P2_3ER" description="Enable rising edge interrupt for P2[3]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." /> + <BitField start="4" size="1" name="P2_4ER" description="Enable rising edge interrupt for P2[4]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." /> + <BitField start="5" size="1" name="P2_5ER" description="Enable rising edge interrupt for P2[5]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." /> + <BitField start="6" size="1" name="P2_6ER" description="Enable rising edge interrupt for P2[6]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." /> + <BitField start="7" size="1" name="P2_7ER" description="Enable rising edge interrupt for P2[7]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." /> + <BitField start="8" size="1" name="P2_8ER" description="Enable rising edge interrupt for P2[8]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." /> + <BitField start="9" size="1" name="P2_9ER" description="Enable rising edge interrupt for P2[9]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." /> + <BitField start="10" size="1" name="P2_10ER" description="Enable rising edge interrupt for P2[10]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." /> + <BitField start="11" size="1" name="P2_11ER" description="Enable rising edge interrupt for P2[11]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." /> + <BitField start="12" size="1" name="P2_12ER" description="Enable rising edge interrupt for P2[12]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." /> + <BitField start="13" size="1" name="P2_13ER" description="Enable rising edge interrupt for P2[13]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." /> + <BitField start="14" size="1" name="P2_14ER" description="Enable rising edge interrupt for P2[14]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." /> + <BitField start="15" size="1" name="P2_15ER" description="Enable rising edge interrupt for P2[15]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." /> + <BitField start="16" size="1" name="P2_16ER" description="Enable rising edge interrupt for P2[16]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." /> + <BitField start="17" size="1" name="P2_17ER" description="Enable rising edge interrupt for P2[17]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." /> + <BitField start="18" size="1" name="P2_18ER" description="Enable rising edge interrupt for P2[18]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." /> + <BitField start="19" size="1" name="P2_19ER" description="Enable rising edge interrupt for P2[19]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." /> + <BitField start="20" size="1" name="P2_20ER" description="Enable rising edge interrupt for P2[20]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." /> + <BitField start="21" size="1" name="P2_21ER" description="Enable rising edge interrupt for P2[21]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." /> + <BitField start="22" size="1" name="P2_22ER" description="Enable rising edge interrupt for P2[22]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." /> + <BitField start="23" size="1" name="P2_23ER" description="Enable rising edge interrupt for P2[23]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." /> + <BitField start="24" size="1" name="P2_24ER" description="Enable rising edge interrupt for P2[24]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." /> + <BitField start="25" size="1" name="P2_25ER" description="Enable rising edge interrupt for P2[25]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." /> + <BitField start="26" size="1" name="P2_26ER" description="Enable rising edge interrupt for P2[26]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." /> + <BitField start="27" size="1" name="P2_27ER" description="Enable rising edge interrupt for P2[27]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." /> + <BitField start="28" size="1" name="P2_28ER" description="Enable rising edge interrupt for P2[28]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." /> + <BitField start="29" size="1" name="P2_29ER" description="Enable rising edge interrupt for P2[29]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." /> + <BitField start="30" size="1" name="P2_30ER" description="Enable rising edge interrupt for P2[30]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." /> + <BitField start="31" size="1" name="P2_31ER" description="Enable rising edge interrupt for P2[31]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." /> + </Register> + <Register start="+0x034" size="4" name="ENF2" access="Read/Write" description="GPIO Interrupt Enable for Falling edge for Port 0." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="P2_0EF" description="Enable falling edge interrupt for P2[0]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." /> + <BitField start="1" size="1" name="P2_1EF" description="Enable falling edge interrupt for P2[1]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." /> + <BitField start="2" size="1" name="P2_2EF" description="Enable falling edge interrupt for P2[2]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." /> + <BitField start="3" size="1" name="P2_3EF" description="Enable falling edge interrupt for P2[3]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." /> + <BitField start="4" size="1" name="P2_4EF" description="Enable falling edge interrupt for P2[4]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." /> + <BitField start="5" size="1" name="P2_5EF" description="Enable falling edge interrupt for P2[5]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." /> + <BitField start="6" size="1" name="P2_6EF" description="Enable falling edge interrupt for P2[6]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." /> + <BitField start="7" size="1" name="P2_7EF" description="Enable falling edge interrupt for P2[7]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." /> + <BitField start="8" size="1" name="P2_8EF" description="Enable falling edge interrupt for P2[8]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." /> + <BitField start="9" size="1" name="P2_9EF" description="Enable falling edge interrupt for P2[9]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." /> + <BitField start="10" size="1" name="P2_10EF" description="Enable falling edge interrupt for P2[10]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." /> + <BitField start="11" size="1" name="P2_11EF" description="Enable falling edge interrupt for P2[11]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." /> + <BitField start="12" size="1" name="P2_12EF" description="Enable falling edge interrupt for P2[12]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." /> + <BitField start="13" size="1" name="P2_13EF" description="Enable falling edge interrupt for P2[13]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." /> + <BitField start="14" size="1" name="P2_14EF" description="Enable falling edge interrupt for P2[14]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." /> + <BitField start="15" size="1" name="P2_15EF" description="Enable falling edge interrupt for P2[15]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." /> + <BitField start="16" size="1" name="P2_16EF" description="Enable falling edge interrupt for P2[16]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." /> + <BitField start="17" size="1" name="P2_17EF" description="Enable falling edge interrupt for P2[17]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." /> + <BitField start="18" size="1" name="P2_18EF" description="Enable falling edge interrupt for P2[18]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." /> + <BitField start="19" size="1" name="P2_19EF" description="Enable falling edge interrupt for P2[19]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." /> + <BitField start="20" size="1" name="P2_20EF" description="Enable falling edge interrupt for P2[20]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." /> + <BitField start="21" size="1" name="P2_21EF" description="Enable falling edge interrupt for P2[21]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." /> + <BitField start="22" size="1" name="P2_22EF" description="Enable falling edge interrupt for P2[22]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." /> + <BitField start="23" size="1" name="P2_23EF" description="Enable falling edge interrupt for P2[23]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." /> + <BitField start="24" size="1" name="P2_24EF" description="Enable falling edge interrupt for P2[24]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." /> + <BitField start="25" size="1" name="P2_25EF" description="Enable falling edge interrupt for P2[25]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." /> + <BitField start="26" size="1" name="P2_26EF" description="Enable falling edge interrupt for P2[26]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." /> + <BitField start="27" size="1" name="P2_27EF" description="Enable falling edge interrupt for P2[27]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." /> + <BitField start="28" size="1" name="P2_28EF" description="Enable falling edge interrupt for P2[28]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." /> + <BitField start="29" size="1" name="P2_29EF" description="Enable falling edge interrupt for P2[29]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." /> + <BitField start="30" size="1" name="P2_30EF" description="Enable falling edge interrupt for P2[30]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." /> + <BitField start="31" size="1" name="P2_31EF" description="Enable falling edge interrupt for P2[31]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." /> + </Register> + </RegisterGroup> + <RegisterGroup name="IOCON" start="0x4002C000" description="IOCON pin configuration"> + <Register start="+0x0" size="4" name="P0_0" access="Read/Write" description="I/O configuration register for pin P0[0]" reset_value="0x00000030" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P0[0]"> + <Enum name="P0_0" start="0x0" description="General purpose digital input/output pin." /> + <Enum name="CAN_RD1" start="0x1" description="CAN1 receiver input." /> + <Enum name="U3_TXD" start="0x2" description="Transmitter output for UART3." /> + <Enum name="I2C1_SDA" start="0x3" description="I2C1 data input/output (this pin does not use a specialized I2C pad)." /> + <Enum name="U0_TXD" start="0x4" description="Transmitter output for UART0." /> + </BitField> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor
 control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor
 enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin
 reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as
 1)." /> + </BitField> + <BitField start="7" size="2" name="RESERVED" description="Reserved." /> + <BitField start="9" size="1" name="SLEW" description="Driver slew rate"> + <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More
 outputs can be switched simultaneously." /> + <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the
 appropriate specific device data sheet for details." /> + </BitField> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain
 mode. Input cannot be pulled up above VDD." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x4" size="4" name="P0_1" access="Read/Write" description="I/O configuration register for pin P0[1]" reset_value="0x00000030" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P0[1]"> + <Enum name="P0_1" start="0x0" description="General purpose digital input/output pin." /> + <Enum name="CAN_TD1" start="0x1" description="CAN1 transmitter output." /> + <Enum name="U3_RXD" start="0x2" description="Receiver input for UART3." /> + <Enum name="I2C1_SCL" start="0x3" description="I2C1 clock input/output (this pin does not use a specialized I2C pad)." /> + <Enum name="U0_RXD" start="0x4" description="Receiver input for UART0." /> + </BitField> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor
 control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor
 enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin
 reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as
 1)." /> + </BitField> + <BitField start="7" size="2" name="RESERVED" description="Reserved." /> + <BitField start="9" size="1" name="SLEW" description="Driver slew rate"> + <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More
 outputs can be switched simultaneously." /> + <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the
 appropriate specific device data sheet for details." /> + </BitField> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain
 mode. Input cannot be pulled up above VDD." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x8" size="4" name="P0_2" access="Read/Write" description="I/O configuration register for pin P0[2]" reset_value="0x00000030" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P0[2]"> + <Enum name="P0_2" start="0x0" description="General purpose digital input/output pin." /> + <Enum name="U0_TXD" start="0x1" description="Transmitter output for UART0." /> + <Enum name="U3_TXD" start="0x2" description="Transmitter output for UART3." /> + </BitField> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor
 control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor
 enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin
 reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as
 1)." /> + </BitField> + <BitField start="7" size="2" name="RESERVED" description="Reserved." /> + <BitField start="9" size="1" name="SLEW" description="Driver slew rate"> + <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More
 outputs can be switched simultaneously." /> + <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the
 appropriate specific device data sheet for details." /> + </BitField> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain
 mode. Input cannot be pulled up above VDD." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0xC" size="4" name="P0_3" access="Read/Write" description="I/O configuration register for pin P0[3]" reset_value="0x00000030" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P0[3]"> + <Enum name="P0_3" start="0x0" description="General purpose digital input/output pin." /> + <Enum name="U0_RXD" start="0x1" description="Receiver input for UART0." /> + <Enum name="U3_RXD" start="0x2" description="Receiver input for UART3." /> + </BitField> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor
 control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor
 enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin
 reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as
 1)." /> + </BitField> + <BitField start="7" size="2" name="RESERVED" description="Reserved." /> + <BitField start="9" size="1" name="SLEW" description="Driver slew rate"> + <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More
 outputs can be switched simultaneously." /> + <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the
 appropriate specific device data sheet for details." /> + </BitField> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain
 mode. Input cannot be pulled up above VDD." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x10" size="4" name="P0_4" access="Read/Write" description="I/O configuration register for pin P0[4]" reset_value="0x00000030" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P0[4]"> + <Enum name="P0_4" start="0x0" description="General purpose digital input/output pin." /> + <Enum name="I2S_RX_SCK" start="0x1" description="I2S Receive clock. It is driven by the master and received by the slave. Corresponds to the signal SCK in the I2S-bus specification." /> + <Enum name="CAN_RD2" start="0x2" description="CAN2 receiver input." /> + <Enum name="T2_CAP0" start="0x3" description="Capture input for Timer 2, channel 0." /> + <Enum name="CMP_ROSC" start="0x5" description="Comparator relaxation oscillator for 555 timer applications." /> + <Enum name="LCD_VD_0" start="0x7" description="LCD data." /> + </BitField> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor
 control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor
 enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin
 reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as
 1)." /> + </BitField> + <BitField start="7" size="2" name="RESERVED" description="Reserved." /> + <BitField start="9" size="1" name="SLEW" description="Driver slew rate"> + <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More
 outputs can be switched simultaneously." /> + <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the
 appropriate specific device data sheet for details." /> + </BitField> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain
 mode. Input cannot be pulled up above VDD." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x14" size="4" name="P0_5" access="Read/Write" description="I/O configuration register for pin P0[5]" reset_value="0x00000030" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P0[5]"> + <Enum name="P0_5" start="0x0" description="General purpose digital input/output pin." /> + <Enum name="I2S_RX_WS" start="0x1" description="I2S Receive word select. It is driven by the master and received by the slave. Corresponds to the signal WS in the I2S-bus specification." /> + <Enum name="CAN_TD2" start="0x2" description="CAN2 transmitter output." /> + <Enum name="T2_CAP1" start="0x3" description="Capture input for Timer 2, channel 1." /> + <Enum name="CMP_RESET" start="0x5" description="Comparator reset." /> + <Enum name="LCD_VD_1" start="0x7" description="LCD data." /> + </BitField> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor
 control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor
 enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin
 reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as
 1)." /> + </BitField> + <BitField start="7" size="2" name="RESERVED" description="Reserved." /> + <BitField start="9" size="1" name="SLEW" description="Driver slew rate"> + <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More
 outputs can be switched simultaneously." /> + <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the
 appropriate specific device data sheet for details." /> + </BitField> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain
 mode. Input cannot be pulled up above VDD." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x18" size="4" name="P0_6" access="Read/Write" description="I/O configuration register for pin P0[6]" reset_value="0x00000030" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P0[6]"> + <Enum name="P0_6" start="0x0" description="General purpose digital input/output pin." /> + <Enum name="I2S_RX_SDA" start="0x1" description="I2S Receive data. It is driven by the transmitter and read by the receiver. Corresponds to the signal SD in the I2S-bus specification." /> + <Enum name="SSP1_SSEL" start="0x2" description="Slave Select for SSP1." /> + <Enum name="T2_MAT0" start="0x3" description="Match output for Timer 2, channel 0." /> + <Enum name="U1_RTS" start="0x4" description="Request to Send output for UART1. Can also be configured to be an RS-485/EIA-485 output enable signal for UART1." /> + <Enum name="CMP_ROSC" start="0x5" description="Comparator relaxation oscillator for 555 timer applications." /> + <Enum name="LCD_VD_8" start="0x7" description="LCD data." /> + </BitField> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor
 control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor
 enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin
 reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as
 1)." /> + </BitField> + <BitField start="7" size="2" name="RESERVED" description="Reserved." /> + <BitField start="9" size="1" name="SLEW" description="Driver slew rate"> + <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More
 outputs can be switched simultaneously." /> + <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the
 appropriate specific device data sheet for details." /> + </BitField> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain
 mode. Input cannot be pulled up above VDD." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x1C" size="4" name="P0_7" access="Read/Write" description="I/O configuration register for pin P0[7] " reset_value="0x000000A0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P0[7] "> + <Enum name="P0_7" start="0x0" description="General purpose digital input/output pin." /> + <Enum name="I2S_TX_SCK" start="0x1" description="I2S transmit clock. It is driven by the master and received by the slave. Corresponds to the signal SCK in the I2S-bus specification." /> + <Enum name="SSP1_SCK" start="0x2" description="Serial Clock for SSP1." /> + <Enum name="T2_MAT1" start="0x3" description="Match output for Timer 2, channel 1." /> + <Enum name="RTC_EV0" start="0x4" description="Event input 0 to Event Monitor/Recorder." /> + <Enum name="CMP_VREF" start="0x5" description="Comparator reference voltage." /> + <Enum name="LCD_VD_9" start="0x7" description="LCD data." /> + </BitField> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor
 control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor
 enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin
 reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as
 1)." /> + </BitField> + <BitField start="7" size="1" name="RESERVED" description="Reserved." /> + <BitField start="8" size="1" name="FILTER" description="Glitch filter control"> + <Enum name="ENABLED" start="0" description="Noise pulses below approximately 10 ns are filtered
 out." /> + <Enum name="DISABLED" start="1" description="No input filtering is done." /> + </BitField> + <BitField start="9" size="1" name="SLEW" description="Driver slew rate"> + <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More
 outputs can be switched simultaneously." /> + <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the
 appropriate specific device data sheet for details." /> + </BitField> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain
 mode. Input cannot be pulled up above VDD." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x20" size="4" name="P0_8" access="Read/Write" description="I/O configuration register for pin P0[8] " reset_value="0x000000A0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P0[8] "> + <Enum name="P0_8" start="0x0" description="General purpose digital input/output pin." /> + <Enum name="I2S_TX_WS" start="0x1" description="I2S Transmit word select. It is driven by the master and received by the slave. Corresponds to the signal WS in the I2S-bus specification." /> + <Enum name="SSP1_MISO" start="0x2" description="Master In Slave Out for SSP1." /> + <Enum name="T2_MAT2" start="0x3" description="Match output for Timer 2, channel 2." /> + <Enum name="RTC_EV1" start="0x4" description="Event input 1 to Event Monitor/Recorder." /> + <Enum name="CMP1_IN_3" start="0x5" description="Comparator 1, input 3." /> + <Enum name="LCD_VD_16" start="0x7" description="LCD data." /> + </BitField> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor
 control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor
 enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin
 reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as
 1)." /> + </BitField> + <BitField start="7" size="1" name="RESERVED" description="Reserved." /> + <BitField start="8" size="1" name="FILTER" description="Glitch filter control"> + <Enum name="ENABLED" start="0" description="Noise pulses below approximately 10 ns are filtered
 out." /> + <Enum name="DISABLED" start="1" description="No input filtering is done." /> + </BitField> + <BitField start="9" size="1" name="SLEW" description="Driver slew rate"> + <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More
 outputs can be switched simultaneously." /> + <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the
 appropriate specific device data sheet for details." /> + </BitField> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain
 mode. Input cannot be pulled up above VDD." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x24" size="4" name="P0_9" access="Read/Write" description="I/O configuration register for pin P0[9]" reset_value="0x000000A0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P0[9]"> + <Enum name="P0_9" start="0x0" description="General purpose digital input/output pin." /> + <Enum name="I2S_TX_SDA" start="0x1" description="I2S transmit data. It is driven by the transmitter and read by the receiver. Corresponds to the signal SD in the I2S-bus specification." /> + <Enum name="SSP1_MOSI" start="0x2" description="Master Out Slave In for SSP1." /> + <Enum name="T2_MAT3" start="0x3" description="Match output for Timer 2, channel 3." /> + <Enum name="RTC_EV2" start="0x4" description="Event input 2 to Event Monitor/Recorder." /> + <Enum name="CMP1_IN_2" start="0x5" description="Comparator 1, input 2." /> + <Enum name="LCD_VD_17" start="0x7" description="LCD data." /> + </BitField> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor
 control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor
 enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin
 reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as
 1)." /> + </BitField> + <BitField start="7" size="1" name="RESERVED" description="Reserved." /> + <BitField start="8" size="1" name="FILTER" description="Glitch filter control"> + <Enum name="ENABLED" start="0" description="Noise pulses below approximately 10 ns are filtered
 out." /> + <Enum name="DISABLED" start="1" description="No input filtering is done." /> + </BitField> + <BitField start="9" size="1" name="SLEW" description="Driver slew rate"> + <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More
 outputs can be switched simultaneously." /> + <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the
 appropriate specific device data sheet for details." /> + </BitField> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain
 mode. Input cannot be pulled up above VDD." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x28" size="4" name="P0_10" access="Read/Write" description="I/O configuration register for pin P0[10]" reset_value="0x00000030" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P0[10]"> + <Enum name="P0_10" start="0x0" description="General purpose digital input/output pin." /> + <Enum name="U2_TXD" start="0x1" description="Transmitter output for UART2." /> + <Enum name="I2C2_SDA" start="0x2" description="I2C2 data input/output (this pin does not use a specialized I2C pad)." /> + <Enum name="T3_MAT0" start="0x3" description="Match output for Timer 3, channel 0." /> + <Enum name="LCD_VD_5" start="0x7" description="LCD data." /> + </BitField> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor
 control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor
 enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin
 reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as
 1)." /> + </BitField> + <BitField start="7" size="2" name="RESERVED" description="Reserved." /> + <BitField start="9" size="1" name="SLEW" description="Driver slew rate"> + <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More
 outputs can be switched simultaneously." /> + <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the
 appropriate specific device data sheet for details." /> + </BitField> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain
 mode. Input cannot be pulled up above VDD." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x2C" size="4" name="P0_11" access="Read/Write" description="I/O configuration register for pin P0[11]" reset_value="0x00000030" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P0[11]"> + <Enum name="P0_11" start="0x0" description="General purpose digital input/output pin." /> + <Enum name="U2_RXD" start="0x1" description="Receiver input for UART2." /> + <Enum name="I2C2_SCL" start="0x2" description="I2C2 clock input/output (this pin does not use a specialized I2C pad)." /> + <Enum name="T3_MAT1" start="0x3" description="Match output for Timer 3, channel 1." /> + <Enum name="LCD_VD_10" start="0x7" description="LCD data." /> + </BitField> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor
 control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor
 enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin
 reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as
 1)." /> + </BitField> + <BitField start="7" size="2" name="RESERVED" description="Reserved." /> + <BitField start="9" size="1" name="SLEW" description="Driver slew rate"> + <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More
 outputs can be switched simultaneously." /> + <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the
 appropriate specific device data sheet for details." /> + </BitField> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain
 mode. Input cannot be pulled up above VDD." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x30" size="4" name="P0_12" access="Read/Write" description="I/O configuration register for pin P0[12]" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P0[12]"> + <Enum name="P0_12" start="0x0" description="General purpose digital input/output pin." /> + <Enum name="USB_PPWR2" start="0x1" description="Port Power enable signal for USB port 2." /> + <Enum name="SSP1_MISO" start="0x2" description="Master In Slave Out for SSP1." /> + <Enum name="ADC0_IN_6" start="0x3" description="A/D converter 0, input 6. When configured as an ADC input, the digital function of the pin must be disabled." /> + </BitField> + </Register> + <Register start="+0x34" size="4" name="P0_13" access="Read/Write" description="I/O configuration register for pin P0[13]" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P0[13]"> + <Enum name="P0_13" start="0x0" description="General purpose digital input/output pin." /> + <Enum name="USB_UP_LED2" start="0x1" description="USB port 2 GoodLink LED indicator. It is LOW when the device is configured (non-control endpoints enabled), or when the host is enabled and has detected a device on the bus. It is HIGH when the device is not configured, or when host is enabled and has not detected a device on the bus, or during global suspend. It transitions between LOW and HIGH (flashes) when the host is enabled and detects activity on the bus." /> + <Enum name="SSP1_MOSI" start="0x2" description="Master Out Slave In for SSP1." /> + <Enum name="ADC0_IN_7" start="0x3" description="A/D converter 0, input 7. When configured as an ADC input, the digital function of the pin must be disabled." /> + </BitField> + </Register> + <Register start="+0x38" size="4" name="P0_14" access="Read/Write" description="I/O configuration register for pin P0[14]" reset_value="0x00000030" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P0[14]"> + <Enum name="P0_14" start="0x0" description="General purpose digital input/output pin." /> + <Enum name="USB_HSTEN2" start="0x1" description="Host Enabled status for USB port 2." /> + <Enum name="SSP1_SSEL" start="0x2" description="Slave Select for SSP1." /> + <Enum name="USB_CONNECT2" start="0x3" description="SoftConnect control for USB port 2. Signal used to switch an external 1.5 kW resistor under software control. Used with the SoftConnect USB feature." /> + </BitField> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor
 control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor
 enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin
 reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as
 1)." /> + </BitField> + <BitField start="7" size="2" name="RESERVED" description="Reserved." /> + <BitField start="9" size="1" name="SLEW" description="Driver slew rate"> + <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More
 outputs can be switched simultaneously." /> + <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the
 appropriate specific device data sheet for details." /> + </BitField> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain
 mode. Input cannot be pulled up above VDD." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x3C" size="4" name="P0_15" access="Read/Write" description="I/O configuration register for pin P0[15]" reset_value="0x00000030" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P0[15]"> + <Enum name="P0_15" start="0x0" description="General purpose digital input/output pin." /> + <Enum name="U1_TXD" start="0x1" description="Transmitter output for UART1." /> + <Enum name="SSP0_SCK" start="0x2" description="Serial clock for SSP0." /> + <Enum name="SPIFI_IO_2" start="0x5" description="Data bit 0 for SPIFI." /> + </BitField> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor
 control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor
 enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin
 reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as
 1)." /> + </BitField> + <BitField start="7" size="2" name="RESERVED" description="Reserved." /> + <BitField start="9" size="1" name="SLEW" description="Driver slew rate"> + <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More
 outputs can be switched simultaneously." /> + <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the
 appropriate specific device data sheet for details." /> + </BitField> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain
 mode. Input cannot be pulled up above VDD." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x40" size="4" name="P0_16" access="Read/Write" description="I/O configuration register for pin P0[16]" reset_value="0x00000030" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P0[16]"> + <Enum name="P0_16" start="0x0" description="General purpose digital input/output pin." /> + <Enum name="U1_RXD" start="0x1" description="Receiver input for UART1." /> + <Enum name="SSP0_SSEL" start="0x2" description="Slave Select for SSP0." /> + <Enum name="SPIFI_IO_3" start="0x5" description="Data bit 0 for SPIFI." /> + </BitField> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor
 control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor
 enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin
 reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as
 1)." /> + </BitField> + <BitField start="7" size="2" name="RESERVED" description="Reserved." /> + <BitField start="9" size="1" name="SLEW" description="Driver slew rate"> + <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More
 outputs can be switched simultaneously." /> + <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the
 appropriate specific device data sheet for details." /> + </BitField> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain
 mode. Input cannot be pulled up above VDD." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x44" size="4" name="P0_17" access="Read/Write" description="I/O configuration register for pin P0[17]" reset_value="0x00000030" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P0[17]"> + <Enum name="P0_17" start="0x0" description="General purpose digital input/output pin." /> + <Enum name="U1_CTS" start="0x1" description="Clear to Send input for UART1." /> + <Enum name="SSP0_MISO" start="0x2" description="Master In Slave Out for SSP0." /> + <Enum name="SPIFI_IO_1" start="0x5" description="Data bit 0 for SPIFI." /> + </BitField> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor
 control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor
 enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin
 reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as
 1)." /> + </BitField> + <BitField start="7" size="2" name="RESERVED" description="Reserved." /> + <BitField start="9" size="1" name="SLEW" description="Driver slew rate"> + <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More
 outputs can be switched simultaneously." /> + <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the
 appropriate specific device data sheet for details." /> + </BitField> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain
 mode. Input cannot be pulled up above VDD." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x48" size="4" name="P0_18" access="Read/Write" description="I/O configuration register for pin P0[18]" reset_value="0x00000030" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P0[18]"> + <Enum name="P0_18" start="0x0" description="General purpose digital input/output pin." /> + <Enum name="U1_DCD" start="0x1" description="Data Carrier Detect input for UART1." /> + <Enum name="SSP0_MOSI" start="0x2" description="Master Out Slave In for SSP0." /> + <Enum name="SPIFI_IO_0" start="0x5" description="Data bit 0 for SPIFI." /> + </BitField> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor
 control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor
 enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin
 reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as
 1)." /> + </BitField> + <BitField start="7" size="2" name="RESERVED" description="Reserved." /> + <BitField start="9" size="1" name="SLEW" description="Driver slew rate"> + <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More
 outputs can be switched simultaneously." /> + <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the
 appropriate specific device data sheet for details." /> + </BitField> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain
 mode. Input cannot be pulled up above VDD." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x4C" size="4" name="P0_19" access="Read/Write" description="I/O configuration register for pin P0[19]" reset_value="0x00000030" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P0[19]"> + <Enum name="P0_19" start="0x0" description="General purpose digital input/output pin." /> + <Enum name="U1_DSR" start="0x1" description="Data Set Ready input for UART1." /> + <Enum name="SD_CLK" start="0x2" description="Clock output line for SD card interface." /> + <Enum name="I2C1_SDA" start="0x3" description="I2C1 data input/output (this pin does not use a specialized I2C pad)." /> + <Enum name="LCD_VD_13" start="0x7" description="LCD data." /> + </BitField> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor
 control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor
 enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin
 reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as
 1)." /> + </BitField> + <BitField start="7" size="2" name="RESERVED" description="Reserved." /> + <BitField start="9" size="1" name="SLEW" description="Driver slew rate"> + <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More
 outputs can be switched simultaneously." /> + <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the
 appropriate specific device data sheet for details." /> + </BitField> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain
 mode. Input cannot be pulled up above VDD." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x50" size="4" name="P0_20" access="Read/Write" description="I/O configuration register for pin P0[20]" reset_value="0x00000030" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P0[20]"> + <Enum name="P0_20" start="0x0" description="General purpose digital input/output pin." /> + <Enum name="U1_DTR" start="0x1" description="Data Terminal Ready output for UART1. Can also be configured to be an RS-485/EIA-485 output enable signal for UART1." /> + <Enum name="SD_CMD" start="0x2" description="Command line for SD card interface." /> + <Enum name="I2C1_SCL" start="0x3" description="I2C1 clock input/output (this pin does not use a specialized I2C pad)." /> + <Enum name="LCD_VD_14" start="0x7" description="LCD data." /> + </BitField> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor
 control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor
 enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin
 reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as
 1)." /> + </BitField> + <BitField start="7" size="2" name="RESERVED" description="Reserved." /> + <BitField start="9" size="1" name="SLEW" description="Driver slew rate"> + <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More
 outputs can be switched simultaneously." /> + <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the
 appropriate specific device data sheet for details." /> + </BitField> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain
 mode. Input cannot be pulled up above VDD." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x54" size="4" name="P0_21" access="Read/Write" description="I/O configuration register for pin P0[21]" reset_value="0x00000030" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P0[21]"> + <Enum name="P0_21" start="0x0" description="General purpose digital input/output pin." /> + <Enum name="U1_RI" start="0x1" description="Ring Indicator input for UART1." /> + <Enum name="SD_PWR" start="0x2" description="Power Supply Enable for external SD card power supply." /> + <Enum name="U4_OE" start="0x3" description="RS-485/EIA-485 output enable signal for UART4." /> + <Enum name="CAN_RD1" start="0x4" description="CAN1 receiver input." /> + <Enum name="U4_SCLK" start="0x5" description="USART 4 clock input or output in synchronous mode." /> + </BitField> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor
 control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor
 enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin
 reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as
 1)." /> + </BitField> + <BitField start="7" size="2" name="RESERVED" description="Reserved." /> + <BitField start="9" size="1" name="SLEW" description="Driver slew rate"> + <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More
 outputs can be switched simultaneously." /> + <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the
 appropriate specific device data sheet for details." /> + </BitField> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain
 mode. Input cannot be pulled up above VDD." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x58" size="4" name="P0_22" access="Read/Write" description="I/O configuration register for pin P0[22]" reset_value="0x000001B0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P0[22]"> + <Enum name="P0_22" start="0x0" description="General purpose digital input/output pin." /> + <Enum name="U1_RTS" start="0x1" description="Request to Send output for UART1. Can also be configured to be an RS-485/EIA-485 output enable signal for UART1." /> + <Enum name="SD_DAT_0" start="0x2" description="Data line 0 for SD card interface." /> + <Enum name="U4_TXD" start="0x3" description="Transmitter output for USART4 (input/output in smart card mode)." /> + <Enum name="CAN_TD1" start="0x4" description="CAN1 transmitter output." /> + <Enum name="SPIFI_CLK" start="0x5" description="Clock output for SPIFI." /> + </BitField> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor
 control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor
 enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin
 reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as
 1)." /> + </BitField> + <BitField start="7" size="1" name="ADMODE" description="Selects Analog/Digital mode."> + <Enum name="ANALOG_INPUT_MODE_" start="0" description="Analog input mode." /> + <Enum name="DIGITAL_FUNCTIONAL_M" start="1" description="Digital functional mode." /> + </BitField> + <BitField start="8" size="1" name="FILTR" description="Selects 10 ns input glitch filter."> + <Enum name="FILTER_DISABLED_" start="0" description="Filter disabled." /> + <Enum name="FILTER_ENABLED_" start="1" description="Filter enabled." /> + </BitField> + <BitField start="9" size="1" name="RESERVED" description="Reserved." /> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain
 mode." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x5C" size="4" name="P0_23" access="Read/Write" description="I/O configuration register for pin P0[23]" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P0[23]"> + <Enum name="P0_23" start="0x0" description="General purpose digital input/output pin." /> + <Enum name="ADC0_IN_0" start="0x1" description="A/D converter 0, input 0. When configured as an ADC input, the digital function of the pin must be disabled." /> + <Enum name="I2S_RX_SCK" start="0x2" description="Receive Clock. It is driven by the master and received by the slave. Corresponds to the signal SCK in the I2S-bus specification." /> + <Enum name="T3_CAP0" start="0x3" description="Capture input for Timer 3, channel 0." /> + </BitField> + </Register> + <Register start="+0x60" size="4" name="P0_24" access="Read/Write" description="I/O configuration register for pin P0[24]" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P0[24]"> + <Enum name="P0_24" start="0x0" description="General purpose digital input/output pin." /> + <Enum name="ADC0_IN_1" start="0x1" description="A/D converter 0, input 1. When configured as an ADC input, the digital function of the pin must be disabled." /> + <Enum name="I2S_RX_WS" start="0x2" description="Receive Word Select. It is driven by the master and received by the slave. Corresponds to the signal WS in the I2S-bus specification." /> + <Enum name="T3_CAP1" start="0x3" description="Capture input for Timer 3, channel 1." /> + </BitField> + </Register> + <Register start="+0x64" size="4" name="P0_25" access="Read/Write" description="I/O configuration register for pin P0[25]" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P0[25]"> + <Enum name="P0_25" start="0x0" description="General purpose digital input/output pin." /> + <Enum name="ADC0_IN_2" start="0x1" description="A/D converter 0, input 2. When configured as an ADC input, the digital function of the pin must be disabled." /> + <Enum name="I2S_RX_SDA" start="0x2" description="Receive data. It is driven by the transmitter and read by the receiver. Corresponds to the signal SD in the I2S-bus specification." /> + <Enum name="U3_TXD" start="0x3" description="Transmitter output for UART3." /> + </BitField> + </Register> + <Register start="+0x68" size="4" name="P0_26" access="Read/Write" description="I/O configuration register for pin P0[26]" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P0[26]"> + <Enum name="P0_26" start="0x0" description="General purpose digital input/output pin." /> + <Enum name="ADC0_IN_3" start="0x1" description="A/D converter 0, input 3. When configured as an ADC input, the digital function of the pin must be disabled." /> + <Enum name="DAC_OUT" start="0x2" description="D/A converter output. When configured as the DAC output, the digital function of the pin must be disabled." /> + <Enum name="U3_RXD" start="0x3" description="Receiver input for UART3." /> + </BitField> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor
 control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor
 enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin
 reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as
 1)." /> + </BitField> + <BitField start="7" size="1" name="ADMODE" description="Selects Analog/Digital mode."> + <Enum name="ANALOG_INPUT_MODE_" start="0" description="Analog input mode." /> + <Enum name="DIGITAL_FUNCTIONAL_M" start="1" description="Digital functional mode." /> + </BitField> + <BitField start="8" size="1" name="FILTR" description="Selects 10 ns input glitch filter."> + <Enum name="FILTER_DISABLED_" start="0" description="Filter disabled." /> + <Enum name="FILTER_ENABLED_" start="1" description="Filter enabled." /> + </BitField> + <BitField start="9" size="1" name="RESERVED" description="Reserved." /> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain
 mode." /> + </BitField> + <BitField start="11" size="5" name="RESERVED" description="Reserved." /> + <BitField start="16" size="1" name="DACEN" description="DAC output enable."> + <Enum name="DISABLE" start="0" description="DAC disable." /> + <Enum name="ENABLE" start="1" description="DAC enable." /> + </BitField> + <BitField start="17" size="15" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x6C" size="4" name="P0_27" access="Read/Write" description="I/O configuration register for pin P0[27]" reset_value="0x00000080" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P0[27]"> + <Enum name="P0_27" start="0x0" description="General purpose digital input/output pin." /> + <Enum name="I2C0_SDA" start="0x1" description="I2C0 data input/output. (This pin uses a specialized I2C pad)." /> + <Enum name="USB_SDA1" start="0x2" description="I2C serial data for communication with an external USB transceiver." /> + </BitField> + <BitField start="3" size="3" name="RESERVED" description="Reserved." /> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin
 reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as
 1)." /> + </BitField> + <BitField start="7" size="1" name="RESERVED" description="Reserved." /> + <BitField start="8" size="1" name="HS" description="Configures I2C features for standard mode, fast mode, and Fast Mode
 Plus operation."> + <Enum name="ENABLED" start="0" description="I2C 50ns glitch filter and slew rate control
 enabled." /> + <Enum name="DISABLED" start="1" description="I2C 50ns glitch filter and slew rate control
 disabled." /> + </BitField> + <BitField start="9" size="1" name="HIDRIVE" description="Controls sink current capability of the pin, only for P5[2] and
 P5[3]."> + <Enum name="LOWDRIVE" start="0" description="Output drive sink is 4 mA. This is sufficient for standard
 and fast mode I2C." /> + <Enum name="HIGHDRIVE" start="1" description="Output drive sink is 20 mA. This is needed for Fast Mode
 Plus I2C. Refer to the appropriate specific device data sheet for
 details." /> + </BitField> + <BitField start="10" size="22" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x70" size="4" name="P0_28" access="Read/Write" description="I/O configuration register for pin P0[28]" reset_value="0x00000080" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P0[28]"> + <Enum name="P0_28" start="0x0" description="General purpose digital input/output pin." /> + <Enum name="I2C0_SCL" start="0x1" description="I2C0 clock input/output (this pin uses a specialized I2C pad." /> + <Enum name="USB_SCL1" start="0x2" description="I2C serial clock for communication with an external USB transceiver." /> + </BitField> + <BitField start="3" size="3" name="RESERVED" description="Reserved." /> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin
 reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as
 1)." /> + </BitField> + <BitField start="7" size="1" name="RESERVED" description="Reserved." /> + <BitField start="8" size="1" name="HS" description="Configures I2C features for standard mode, fast mode, and Fast Mode
 Plus operation."> + <Enum name="ENABLED" start="0" description="I2C 50ns glitch filter and slew rate control
 enabled." /> + <Enum name="DISABLED" start="1" description="I2C 50ns glitch filter and slew rate control
 disabled." /> + </BitField> + <BitField start="9" size="1" name="HIDRIVE" description="Controls sink current capability of the pin, only for P5[2] and
 P5[3]."> + <Enum name="LOWDRIVE" start="0" description="Output drive sink is 4 mA. This is sufficient for standard
 and fast mode I2C." /> + <Enum name="HIGHDRIVE" start="1" description="Output drive sink is 20 mA. This is needed for Fast Mode
 Plus I2C. Refer to the appropriate specific device data sheet for
 details." /> + </BitField> + <BitField start="10" size="22" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x74" size="4" name="P0_29" access="Read/Write" description="I/O configuration register for pin P0[29]" reset_value="0x00000000" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P0[29]"> + <Enum name="P0_29" start="0x0" description="General purpose digital input/output pin." /> + <Enum name="USB_DP1" start="0x1" description="USB port 1 bidirectional D+ line." /> + <Enum name="EINT0" start="0x2" description="External interrupt 0 input." /> + </BitField> + <BitField start="3" size="29" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x78" size="4" name="P0_30" access="Read/Write" description="I/O configuration register for pin P0[30]" reset_value="0x00000000" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P0[30]"> + <Enum name="P0_30" start="0x0" description="General purpose digital input/output pin." /> + <Enum name="USB_DM1" start="0x1" description="USB port 1 bidirectional D- line." /> + <Enum name="EINT1" start="0x2" description="External interrupt 1 input." /> + </BitField> + <BitField start="3" size="29" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x7C" size="4" name="P0_31" access="Read/Write" description="I/O configuration register for pin P0[31]" reset_value="0x00000000" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P0[31]"> + <Enum name="P0_31" start="0x0" description="General purpose digital input/output pin." /> + <Enum name="USB_DP2" start="0x1" description="USB port 2 bidirectional D+ line." /> + </BitField> + <BitField start="3" size="29" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x80" size="4" name="P1_0" access="Read/Write" description="I/O configuration register for pin P1[0]" reset_value="0x00000030" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P1[0]"> + <Enum name="P1_0" start="0x0" description="General purpose digital input/output pin." /> + <Enum name="ENET_TXD0" start="0x1" description="Ethernet transmit data 0 (RMII/MII interface)." /> + <Enum name="T3_CAP1" start="0x3" description="Capture input for Timer 3, channel 1." /> + <Enum name="SSP2_SCK" start="0x4" description="Serial clock for SSP2." /> + </BitField> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor
 control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor
 enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin
 reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as
 1)." /> + </BitField> + <BitField start="7" size="2" name="RESERVED" description="Reserved." /> + <BitField start="9" size="1" name="SLEW" description="Driver slew rate"> + <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More
 outputs can be switched simultaneously." /> + <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the
 appropriate specific device data sheet for details." /> + </BitField> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain
 mode. Input cannot be pulled up above VDD." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x84" size="4" name="P1_1" access="Read/Write" description="I/O configuration register for pin P1[1]" reset_value="0x00000030" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P1[1]"> + <Enum name="P1_1" start="0x0" description="General purpose digital input/output pin." /> + <Enum name="ENET_TXD1" start="0x1" description="Ethernet transmit data 1 (RMII/MII interface)." /> + <Enum name="T3_MAT3" start="0x3" description="Match output for Timer 3, channel 3." /> + <Enum name="SSP2_MOSI" start="0x4" description="Master Out Slave In for SSP2." /> + </BitField> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor
 control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor
 enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin
 reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as
 1)." /> + </BitField> + <BitField start="7" size="2" name="RESERVED" description="Reserved." /> + <BitField start="9" size="1" name="SLEW" description="Driver slew rate"> + <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More
 outputs can be switched simultaneously." /> + <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the
 appropriate specific device data sheet for details." /> + </BitField> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain
 mode. Input cannot be pulled up above VDD." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x88" size="4" name="P1_2" access="Read/Write" description="I/O configuration register for pin P1[2]" reset_value="0x00000030" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P1[2]"> + <Enum name="P1_2" start="0x0" description="General purpose digital input/output pin." /> + <Enum name="ENET_TXD2" start="0x1" description="Ethernet transmit data 2 (MII interface)." /> + <Enum name="SD_CLK" start="0x2" description="Clock output line for SD card interface." /> + <Enum name="PWM0_1" start="0x3" description="Pulse Width Modulator 0, output 1." /> + </BitField> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor
 control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor
 enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin
 reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as
 1)." /> + </BitField> + <BitField start="7" size="2" name="RESERVED" description="Reserved." /> + <BitField start="9" size="1" name="SLEW" description="Driver slew rate"> + <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More
 outputs can be switched simultaneously." /> + <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the
 appropriate specific device data sheet for details." /> + </BitField> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain
 mode. Input cannot be pulled up above VDD." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x8C" size="4" name="P1_3" access="Read/Write" description="I/O configuration register for pin P1[3]" reset_value="0x00000030" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P1[3]"> + <Enum name="P1_3" start="0x0" description="General purpose digital input/output pin." /> + <Enum name="ENET_TXD3" start="0x1" description="Ethernet transmit data 3 (MII interface)." /> + <Enum name="SD_CMD" start="0x2" description="Command line for SD card interface." /> + <Enum name="PWM0_2" start="0x3" description="Pulse Width Modulator 0, output 2." /> + </BitField> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor
 control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor
 enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin
 reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as
 1)." /> + </BitField> + <BitField start="7" size="2" name="RESERVED" description="Reserved." /> + <BitField start="9" size="1" name="SLEW" description="Driver slew rate"> + <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More
 outputs can be switched simultaneously." /> + <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the
 appropriate specific device data sheet for details." /> + </BitField> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain
 mode. Input cannot be pulled up above VDD." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x90" size="4" name="P1_4" access="Read/Write" description="I/O configuration register for pin P1[4] " reset_value="0x00000030" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P1[4] "> + <Enum name="P1_4" start="0x0" description="General purpose digital input/output pin." /> + <Enum name="ENET_TX_EN" start="0x1" description="Ethernet transmit data enable (RMII/MII interface)." /> + <Enum name="T3_MAT2" start="0x3" description="Match output for Timer 3, channel 2." /> + <Enum name="SSP2_MISO" start="0x4" description="Master In Slave Out for SSP2." /> + </BitField> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor
 control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor
 enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin
 reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as
 1)." /> + </BitField> + <BitField start="7" size="2" name="RESERVED" description="Reserved." /> + <BitField start="9" size="1" name="SLEW" description="Driver slew rate"> + <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More
 outputs can be switched simultaneously." /> + <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the
 appropriate specific device data sheet for details." /> + </BitField> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain
 mode. Input cannot be pulled up above VDD." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x94" size="4" name="P1_5" access="Read/Write" description="I/O configuration register for pin P1[5]" reset_value="0x00000030" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P1[5]"> + <Enum name="P1_5" start="0x0" description="General purpose digital input/output pin." /> + <Enum name="ENET_TX_ER" start="0x1" description="Ethernet Transmit Error (MII interface)." /> + <Enum name="SD_PWR" start="0x2" description="Power Supply Enable for external SD card power supply." /> + <Enum name="PWM0_3" start="0x3" description="Pulse Width Modulator 0, output 3." /> + <Enum name="CMP1_IN_1" start="0x5" description="Comparator 1, input 1." /> + </BitField> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor
 control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor
 enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin
 reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as
 1)." /> + </BitField> + <BitField start="7" size="2" name="RESERVED" description="Reserved." /> + <BitField start="9" size="1" name="SLEW" description="Driver slew rate"> + <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More
 outputs can be switched simultaneously." /> + <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the
 appropriate specific device data sheet for details." /> + </BitField> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain
 mode. Input cannot be pulled up above VDD." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x98" size="4" name="P1_6" access="Read/Write" description="I/O configuration register for pin P1[6]" reset_value="0x00000030" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P1[6]"> + <Enum name="P1_6" start="0x0" description="General purpose digital input/output pin." /> + <Enum name="ENET_TX_CLK" start="0x1" description="Ethernet Transmit Clock (MII interface)." /> + <Enum name="SD_DAT_0" start="0x2" description="Data line 0 for SD card interface." /> + <Enum name="PWM0_4" start="0x3" description="Pulse Width Modulator 0, output 4." /> + <Enum name="CMP0_IN_3" start="0x5" description="Comparator 0, input 3." /> + </BitField> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor
 control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor
 enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin
 reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as
 1)." /> + </BitField> + <BitField start="7" size="2" name="RESERVED" description="Reserved." /> + <BitField start="9" size="1" name="SLEW" description="Driver slew rate"> + <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More
 outputs can be switched simultaneously." /> + <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the
 appropriate specific device data sheet for details." /> + </BitField> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain
 mode. Input cannot be pulled up above VDD." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x9C" size="4" name="P1_7" access="Read/Write" description="I/O configuration register for pin P1[7]" reset_value="0x00000030" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P1[7]"> + <Enum name="P1_7" start="0x0" description="General purpose digital input/output pin." /> + <Enum name="ENET_COL" start="0x1" description="Ethernet Collision detect (MII interface)." /> + <Enum name="SD_DAT_1" start="0x2" description="Data line 1 for SD card interface." /> + <Enum name="PWM0_5" start="0x3" description="Pulse Width Modulator 0, output 5." /> + <Enum name="CMP1_IN_0" start="0x5" description="Comparator 1, input 0." /> + </BitField> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor
 control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor
 enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin
 reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as
 1)." /> + </BitField> + <BitField start="7" size="2" name="RESERVED" description="Reserved." /> + <BitField start="9" size="1" name="SLEW" description="Driver slew rate"> + <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More
 outputs can be switched simultaneously." /> + <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the
 appropriate specific device data sheet for details." /> + </BitField> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain
 mode. Input cannot be pulled up above VDD." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0xA0" size="4" name="P1_8" access="Read/Write" description="I/O configuration register for pin P1[8]" reset_value="0x00000030" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P1[8]"> + <Enum name="P1_8" start="0x0" description="General purpose digital input/output pin." /> + <Enum name="ENET_CRS_CRS_DV" start="0x1" description="Ethernet Carrier Sense (MII interface) or Ethernet Carrier Sense/Data Valid (RMII interface)." /> + <Enum name="T3_MAT1" start="0x3" description="Match output for Timer 3, channel 1." /> + <Enum name="SSP2_SSEL" start="0x4" description="Slave Select for SSP2." /> + </BitField> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor
 control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor
 enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin
 reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as
 1)." /> + </BitField> + <BitField start="7" size="2" name="RESERVED" description="Reserved." /> + <BitField start="9" size="1" name="SLEW" description="Driver slew rate"> + <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More
 outputs can be switched simultaneously." /> + <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the
 appropriate specific device data sheet for details." /> + </BitField> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain
 mode. Input cannot be pulled up above VDD." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0xA4" size="4" name="P1_9" access="Read/Write" description="I/O configuration register for pin P1[9]" reset_value="0x00000030" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P1[9]"> + <Enum name="P1_9" start="0x0" description="General purpose digital input/output pin." /> + <Enum name="ENET_RXD0" start="0x1" description="Ethernet receive data 0 (RMII/MII interface)." /> + <Enum name="T3_MAT0" start="0x3" description="Match output for Timer 3, channel 0." /> + </BitField> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor
 control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor
 enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin
 reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as
 1)." /> + </BitField> + <BitField start="7" size="2" name="RESERVED" description="Reserved." /> + <BitField start="9" size="1" name="SLEW" description="Driver slew rate"> + <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More
 outputs can be switched simultaneously." /> + <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the
 appropriate specific device data sheet for details." /> + </BitField> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain
 mode. Input cannot be pulled up above VDD." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0xA8" size="4" name="P1_10" access="Read/Write" description="I/O configuration register for pin P1[10]" reset_value="0x00000030" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P1[10]"> + <Enum name="P1_10" start="0x0" description="General purpose digital input/output pin." /> + <Enum name="ENET_RXD1" start="0x1" description="Ethernet receive data 1 (RMII/MII interface)." /> + <Enum name="T3_CAP0" start="0x3" description="Capture input for Timer 3, channel 0." /> + </BitField> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor
 control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor
 enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin
 reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as
 1)." /> + </BitField> + <BitField start="7" size="2" name="RESERVED" description="Reserved." /> + <BitField start="9" size="1" name="SLEW" description="Driver slew rate"> + <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More
 outputs can be switched simultaneously." /> + <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the
 appropriate specific device data sheet for details." /> + </BitField> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain
 mode. Input cannot be pulled up above VDD." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0xAC" size="4" name="P1_11" access="Read/Write" description="I/O configuration register for pin P1[11]" reset_value="0x00000030" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P1[11]"> + <Enum name="P1_11" start="0x0" description="General purpose digital input/output pin." /> + <Enum name="ENET_RXD2" start="0x1" description="Ethernet Receive Data 2 (MII interface)." /> + <Enum name="SD_DAT_2" start="0x2" description="Data line 2 for SD card interface." /> + <Enum name="PWM0_6" start="0x3" description="Pulse Width Modulator 0, output 6." /> + </BitField> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor
 control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor
 enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin
 reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as
 1)." /> + </BitField> + <BitField start="7" size="2" name="RESERVED" description="Reserved." /> + <BitField start="9" size="1" name="SLEW" description="Driver slew rate"> + <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More
 outputs can be switched simultaneously." /> + <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the
 appropriate specific device data sheet for details." /> + </BitField> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain
 mode. Input cannot be pulled up above VDD." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0xB0" size="4" name="P1_12" access="Read/Write" description="I/O configuration register for pin P1[12]" reset_value="0x00000030" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P1[12]"> + <Enum name="P1_12" start="0x0" description="General purpose digital input/output pin." /> + <Enum name="ENET_RXD3" start="0x1" description="Ethernet Receive Data (MII interface)." /> + <Enum name="SD_DAT_3" start="0x2" description="Data line 3 for SD card interface." /> + <Enum name="PWM0_CAP0" start="0x3" description="Capture input for PWM0, channel 0." /> + <Enum name="CMP1_OUT" start="0x5" description="Comparator 1, output." /> + </BitField> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor
 control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor
 enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin
 reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as
 1)." /> + </BitField> + <BitField start="7" size="2" name="RESERVED" description="Reserved." /> + <BitField start="9" size="1" name="SLEW" description="Driver slew rate"> + <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More
 outputs can be switched simultaneously." /> + <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the
 appropriate specific device data sheet for details." /> + </BitField> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain
 mode. Input cannot be pulled up above VDD." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0xB4" size="4" name="P1_13" access="Read/Write" description="I/O configuration register for pin P1[13]" reset_value="0x00000030" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P1[13]"> + <Enum name="P1_13" start="0x0" description="General purpose digital input/output pin." /> + <Enum name="ENET_RX_DV" start="0x1" description="Ethernet Receive Data Valid (MII interface)." /> + </BitField> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor
 control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor
 enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin
 reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as
 1)." /> + </BitField> + <BitField start="7" size="2" name="RESERVED" description="Reserved." /> + <BitField start="9" size="1" name="SLEW" description="Driver slew rate"> + <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More
 outputs can be switched simultaneously." /> + <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the
 appropriate specific device data sheet for details." /> + </BitField> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain
 mode. Input cannot be pulled up above VDD." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0xB8" size="4" name="P1_14" access="Read/Write" description="I/O configuration register for pin P1[14]" reset_value="0x00000030" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P1[14]"> + <Enum name="P1_14" start="0x0" description="General purpose digital input/output pin." /> + <Enum name="ENET_RX_ER" start="0x1" description="Ethernet receive error (RMII/MII interface)." /> + <Enum name="T2_CAP0" start="0x3" description="Capture input for Timer 2, channel 0." /> + <Enum name="CMP0_IN_0" start="0x5" description="Comparator 0, input 0." /> + </BitField> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor
 control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor
 enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin
 reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as
 1)." /> + </BitField> + <BitField start="7" size="2" name="RESERVED" description="Reserved." /> + <BitField start="9" size="1" name="SLEW" description="Driver slew rate"> + <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More
 outputs can be switched simultaneously." /> + <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the
 appropriate specific device data sheet for details." /> + </BitField> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain
 mode. Input cannot be pulled up above VDD." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0xBC" size="4" name="P1_15" access="Read/Write" description="I/O configuration register for pin P1[15]" reset_value="0x00000030" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P1[15]"> + <Enum name="P1_15" start="0x0" description="General purpose digital input/output pin." /> + <Enum name="ENET_RX_CLK_REF_CLK" start="0x1" description="Ethernet Receive Clock (MII interface) or Ethernet Reference Clock (RMII interface)." /> + <Enum name="I2C2_SDA" start="0x3" description="I2C2 data input/output (this pin does not use a specialized I2C pad)." /> + </BitField> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor
 control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor
 enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin
 reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as
 1)." /> + </BitField> + <BitField start="7" size="2" name="RESERVED" description="Reserved." /> + <BitField start="9" size="1" name="SLEW" description="Driver slew rate"> + <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More
 outputs can be switched simultaneously." /> + <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the
 appropriate specific device data sheet for details." /> + </BitField> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain
 mode. Input cannot be pulled up above VDD." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0xC0" size="4" name="P1_16" access="Read/Write" description="I/O configuration register for pin P1[16]" reset_value="0x00000030" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P1[16]"> + <Enum name="P1_16" start="0x0" description="General purpose digital input/output pin." /> + <Enum name="ENET_MDC" start="0x1" description="Ethernet MIIM clock." /> + <Enum name="I2S_TX_MCLK" start="0x2" description="I2S transmit master clock." /> + <Enum name="CMP0_IN_1" start="0x5" description="Comparator 0, input 1." /> + </BitField> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor
 control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor
 enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin
 reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as
 1)." /> + </BitField> + <BitField start="7" size="2" name="RESERVED" description="Reserved." /> + <BitField start="9" size="1" name="SLEW" description="Driver slew rate"> + <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More
 outputs can be switched simultaneously." /> + <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the
 appropriate specific device data sheet for details." /> + </BitField> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain
 mode. Input cannot be pulled up above VDD." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0xC4" size="4" name="P1_17" access="Read/Write" description="I/O configuration register for pin P1[17]" reset_value="0x00000030" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P1[17]"> + <Enum name="P1_17" start="0x0" description="General purpose digital input/output pin." /> + <Enum name="ENET_MDIO" start="0x1" description="Ethernet MIIM data input and output." /> + <Enum name="I2S_RX_MCLK" start="0x2" description="I2S receive master clock." /> + <Enum name="CMP0_IN_2" start="0x5" description="Comparator 0, input 2." /> + </BitField> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor
 control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor
 enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin
 reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as
 1)." /> + </BitField> + <BitField start="7" size="2" name="RESERVED" description="Reserved." /> + <BitField start="9" size="1" name="SLEW" description="Driver slew rate"> + <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More
 outputs can be switched simultaneously." /> + <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the
 appropriate specific device data sheet for details." /> + </BitField> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain
 mode. Input cannot be pulled up above VDD." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0xC8" size="4" name="P1_18" access="Read/Write" description="I/O configuration register for pin P1[18]" reset_value="0x00000030" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P1[18]"> + <Enum name="P1_18" start="0x0" description="General purpose digital input/output pin." /> + <Enum name="USB_UP_LED1" start="0x1" description="It is LOW when the device is configured (non-control endpoints enabled), or when the host is enabled and has detected a device on the bus. It is HIGH when the device is not configured, or when host is enabled and has not detected a device on the bus, or during global suspend. It transitions between LOW and HIGH (flashes) when the host is enabled and detects activity on the bus." /> + <Enum name="PWM1_1" start="0x2" description="Pulse Width Modulator 1, channel 1 output." /> + <Enum name="T1_CAP0" start="0x3" description="Capture input for Timer 1, channel 0." /> + <Enum name="SSP1_MISO" start="0x5" description="Master In Slave Out for SSP1." /> + </BitField> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor
 control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor
 enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin
 reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as
 1)." /> + </BitField> + <BitField start="7" size="2" name="RESERVED" description="Reserved." /> + <BitField start="9" size="1" name="SLEW" description="Driver slew rate"> + <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More
 outputs can be switched simultaneously." /> + <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the
 appropriate specific device data sheet for details." /> + </BitField> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain
 mode. Input cannot be pulled up above VDD." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0xCC" size="4" name="P1_19" access="Read/Write" description="I/O configuration register for pin P1[19]" reset_value="0x00000030" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P1[19]"> + <Enum name="P1_19" start="0x0" description="General purpose digital input/output pin." /> + <Enum name="USB_TX_E1" start="0x1" description="Transmit Enable signal for USB port 1 (OTG transceiver)." /> + <Enum name="USB_PPWR1" start="0x2" description="Port Power enable signal for USB port 1." /> + <Enum name="T1_CAP1" start="0x3" description="Capture input for Timer 1, channel 1." /> + <Enum name="MC_0A" start="0x4" description="Motor control PWM channel 0, output A." /> + <Enum name="SSP1_SCK" start="0x5" description="Serial clock for SSP1." /> + <Enum name="U2_OE" start="0x6" description="RS-485/EIA-485 output enable signal for UART2." /> + </BitField> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor
 control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor
 enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin
 reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as
 1)." /> + </BitField> + <BitField start="7" size="2" name="RESERVED" description="Reserved." /> + <BitField start="9" size="1" name="SLEW" description="Driver slew rate"> + <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More
 outputs can be switched simultaneously." /> + <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the
 appropriate specific device data sheet for details." /> + </BitField> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain
 mode. Input cannot be pulled up above VDD." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0xD0" size="4" name="P1_20" access="Read/Write" description="I/O configuration register for pin P1[20]" reset_value="0x00000030" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P1[20]"> + <Enum name="P1_20" start="0x0" description="General purpose digital input/output pin." /> + <Enum name="USB_TX_DP1" start="0x1" description="D+ transmit data for USB port 1 (OTG transceiver)." /> + <Enum name="PWM1_2" start="0x2" description="Pulse Width Modulator 1, channel 2 output." /> + <Enum name="QEI_PHA" start="0x3" description="Quadrature Encoder Interface PHA input." /> + <Enum name="MC_FB0" start="0x4" description="Motor control PWM channel 0 feedback input." /> + <Enum name="SSP0_SCK" start="0x5" description="Serial clock for SSP0." /> + <Enum name="LCD_VD_6" start="0x6" description="LCD data." /> + <Enum name="LCD_VD_10" start="0x7" description="LCD data." /> + </BitField> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor
 control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor
 enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin
 reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as
 1)." /> + </BitField> + <BitField start="7" size="2" name="RESERVED" description="Reserved." /> + <BitField start="9" size="1" name="SLEW" description="Driver slew rate"> + <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More
 outputs can be switched simultaneously." /> + <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the
 appropriate specific device data sheet for details." /> + </BitField> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain
 mode. Input cannot be pulled up above VDD." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0xD4" size="4" name="P1_21" access="Read/Write" description="I/O configuration register for pin P1[21]" reset_value="0x00000030" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P1[21]"> + <Enum name="P1_21" start="0x0" description="General purpose digital input/output pin." /> + <Enum name="USB_TX_DM1" start="0x1" description="D- transmit data for USB port 1 (OTG transceiver)." /> + <Enum name="PWM1_3" start="0x2" description="Pulse Width Modulator 1, channel 3 output." /> + <Enum name="SSP0_SSEL" start="0x3" description="Slave Select for SSP0." /> + <Enum name="MC_ABORT" start="0x4" description="Motor control PWM, active low fast abort." /> + <Enum name="LCD_VD_7" start="0x6" description="LCD data." /> + <Enum name="LCD_VD_11" start="0x7" description="LCD data." /> + </BitField> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor
 control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor
 enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin
 reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as
 1)." /> + </BitField> + <BitField start="7" size="2" name="RESERVED" description="Reserved." /> + <BitField start="9" size="1" name="SLEW" description="Driver slew rate"> + <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More
 outputs can be switched simultaneously." /> + <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the
 appropriate specific device data sheet for details." /> + </BitField> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain
 mode. Input cannot be pulled up above VDD." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0xD8" size="4" name="P1_22" access="Read/Write" description="I/O configuration register for pin P1[22]" reset_value="0x00000030" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P1[22]"> + <Enum name="P1_22" start="0x0" description="General purpose digital input/output pin." /> + <Enum name="USB_RCV1" start="0x1" description="Differential receive data for USB port 1 (OTG transceiver)." /> + <Enum name="USB_PWRD1" start="0x2" description="Power Status for USB port 1 (host power switch)." /> + <Enum name="T1_MAT0" start="0x3" description="Match output for Timer 1, channel 0." /> + <Enum name="MC_0B" start="0x4" description="Motor control PWM channel 0, output B." /> + <Enum name="SSP1_MOSI" start="0x5" description="Master Out Slave In for SSP1." /> + <Enum name="LCD_VD_8" start="0x6" description="LCD data." /> + <Enum name="LCD_VD_12" start="0x7" description="LCD data." /> + </BitField> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor
 control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor
 enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin
 reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as
 1)." /> + </BitField> + <BitField start="7" size="2" name="RESERVED" description="Reserved." /> + <BitField start="9" size="1" name="SLEW" description="Driver slew rate"> + <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More
 outputs can be switched simultaneously." /> + <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the
 appropriate specific device data sheet for details." /> + </BitField> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain
 mode. Input cannot be pulled up above VDD." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0xDC" size="4" name="P1_23" access="Read/Write" description="I/O configuration register for pin P1[23]" reset_value="0x00000030" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P1[23]"> + <Enum name="P1_23" start="0x0" description="General purpose digital input/output pin." /> + <Enum name="USB_RX_DP1" start="0x1" description="D+ receive data for USB port 1 (OTG transceiver)." /> + <Enum name="PWM1_4" start="0x2" description="Pulse Width Modulator 1, channel 4 output." /> + <Enum name="QEI_PHB" start="0x3" description="Quadrature Encoder Interface PHB input." /> + <Enum name="MC_FB1" start="0x4" description="Motor control PWM channel 1 feedback input." /> + <Enum name="SSP0_MISO" start="0x5" description="Master In Slave Out for SSP0." /> + <Enum name="LCD_VD_9" start="0x6" description="LCD data." /> + <Enum name="LCD_VD_13" start="0x7" description="LCD data." /> + </BitField> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor
 control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor
 enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin
 reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as
 1)." /> + </BitField> + <BitField start="7" size="2" name="RESERVED" description="Reserved." /> + <BitField start="9" size="1" name="SLEW" description="Driver slew rate"> + <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More
 outputs can be switched simultaneously." /> + <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the
 appropriate specific device data sheet for details." /> + </BitField> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain
 mode. Input cannot be pulled up above VDD." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0xE0" size="4" name="P1_24" access="Read/Write" description="I/O configuration register for pin P1[24]" reset_value="0x00000030" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P1[24]"> + <Enum name="P1_24" start="0x0" description="General purpose digital input/output pin." /> + <Enum name="USB_RX_DM1" start="0x1" description="D- receive data for USB port 1 (OTG transceiver)." /> + <Enum name="PWM1_5" start="0x2" description="Pulse Width Modulator 1, channel 5 output." /> + <Enum name="QEI_IDX" start="0x3" description="Quadrature Encoder Interface INDEX input." /> + <Enum name="MC_FB2" start="0x4" description="Motor control PWM channel 2 feedback input." /> + <Enum name="SSP0_MOSI" start="0x5" description="Master Out Slave in for SSP0." /> + <Enum name="LCD_VD_10" start="0x6" description="LCD data." /> + <Enum name="LCD_VD_14" start="0x7" description="LCD data." /> + </BitField> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor
 control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor
 enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin
 reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as
 1)." /> + </BitField> + <BitField start="7" size="2" name="RESERVED" description="Reserved." /> + <BitField start="9" size="1" name="SLEW" description="Driver slew rate"> + <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More
 outputs can be switched simultaneously." /> + <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the
 appropriate specific device data sheet for details." /> + </BitField> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain
 mode. Input cannot be pulled up above VDD." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0xE4" size="4" name="P1_25" access="Read/Write" description="I/O configuration register for pin P1[25]" reset_value="0x00000030" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P1[25]"> + <Enum name="P1_25" start="0x0" description="General purpose digital input/output pin." /> + <Enum name="USB_LS1" start="0x1" description="Low Speed status for USB port 1 (OTG transceiver)." /> + <Enum name="USB_HSTEN1" start="0x2" description="Host Enabled status for USB port 1." /> + <Enum name="T1_MAT1" start="0x3" description="Match output for Timer 1, channel 1." /> + <Enum name="MC_1A" start="0x4" description="Motor control PWM channel 1, output A." /> + <Enum name="CLKOUT" start="0x5" description="Selectable clock output." /> + <Enum name="LCD_VD_11" start="0x6" description="LCD data." /> + <Enum name="LCD_VD_15" start="0x7" description="LCD data." /> + </BitField> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor
 control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor
 enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin
 reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as
 1)." /> + </BitField> + <BitField start="7" size="2" name="RESERVED" description="Reserved." /> + <BitField start="9" size="1" name="SLEW" description="Driver slew rate"> + <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More
 outputs can be switched simultaneously." /> + <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the
 appropriate specific device data sheet for details." /> + </BitField> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain
 mode. Input cannot be pulled up above VDD." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0xE8" size="4" name="P1_26" access="Read/Write" description="I/O configuration register for pin P1[26]" reset_value="0x00000030" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P1[26]"> + <Enum name="P1_26" start="0x0" description="General purpose digital input/output pin." /> + <Enum name="USB_SSPND1" start="0x1" description="USB port 1 Bus Suspend status (OTG transceiver)." /> + <Enum name="PWM1_6" start="0x2" description="Pulse Width Modulator 1, channel 6 output." /> + <Enum name="T0_CAP0" start="0x3" description="Capture input for Timer 0, channel 0." /> + <Enum name="MC_1B" start="0x4" description="Motor control PWM channel 1, output B." /> + <Enum name="SSP1_SSEL" start="0x5" description="Slave Select for SSP1." /> + <Enum name="LCD_VD_12" start="0x6" description="LCD data." /> + <Enum name="LCD_VD_20" start="0x7" description="LCD data." /> + </BitField> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor
 control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor
 enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin
 reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as
 1)." /> + </BitField> + <BitField start="7" size="2" name="RESERVED" description="Reserved." /> + <BitField start="9" size="1" name="SLEW" description="Driver slew rate"> + <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More
 outputs can be switched simultaneously." /> + <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the
 appropriate specific device data sheet for details." /> + </BitField> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain
 mode. Input cannot be pulled up above VDD." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0xEC" size="4" name="P1_27" access="Read/Write" description="I/O configuration register for pin P1[27]" reset_value="0x00000030" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P1[27]"> + <Enum name="P1_27" start="0x0" description="General purpose digital input/output pin." /> + <Enum name="USB_INT1" start="0x1" description="USB port 1 OTG transceiver interrupt (OTG transceiver)." /> + <Enum name="USB_OVRCR1" start="0x2" description="USB port 1 Over-Current status." /> + <Enum name="T0_CAP1" start="0x3" description="Capture input for Timer 0, channel 1." /> + <Enum name="CLKOUT" start="0x4" description="Selectable clock output." /> + <Enum name="LCD_VD_13" start="0x6" description="LCD data." /> + <Enum name="LCD_VD_21" start="0x7" description="LCD data." /> + </BitField> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor
 control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor
 enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin
 reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as
 1)." /> + </BitField> + <BitField start="7" size="2" name="RESERVED" description="Reserved." /> + <BitField start="9" size="1" name="SLEW" description="Driver slew rate"> + <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More
 outputs can be switched simultaneously." /> + <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the
 appropriate specific device data sheet for details." /> + </BitField> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain
 mode. Input cannot be pulled up above VDD." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0xF0" size="4" name="P1_28" access="Read/Write" description="I/O configuration register for pin P1[28]" reset_value="0x00000030" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P1[28]"> + <Enum name="P1_28" start="0x0" description="General purpose digital input/output pin." /> + <Enum name="USB_SCL1" start="0x1" description="USB port 1 I2C serial clock (OTG transceiver)." /> + <Enum name="PWM1_CAP0" start="0x2" description="Capture input for PWM1, channel 0." /> + <Enum name="T0_MAT0" start="0x3" description="Match output for Timer 0, channel 0." /> + <Enum name="MC_2A" start="0x4" description="Motor control PWM channel 2, output A." /> + <Enum name="SSP0_SSEL" start="0x5" description="Slave Select for SSP0." /> + <Enum name="LCD_VD_14" start="0x6" description="LCD data." /> + <Enum name="LCD_VD_22" start="0x7" description="LCD data." /> + </BitField> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor
 control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor
 enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin
 reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as
 1)." /> + </BitField> + <BitField start="7" size="2" name="RESERVED" description="Reserved." /> + <BitField start="9" size="1" name="SLEW" description="Driver slew rate"> + <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More
 outputs can be switched simultaneously." /> + <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the
 appropriate specific device data sheet for details." /> + </BitField> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain
 mode. Input cannot be pulled up above VDD." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0xF4" size="4" name="P1_29" access="Read/Write" description="I/O configuration register for pin P1[29]" reset_value="0x00000030" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P1[29]"> + <Enum name="P1_29" start="0x0" description="General purpose digital input/output pin." /> + <Enum name="USB_SDA1" start="0x1" description="USB port 1 I2C serial data (OTG transceiver)." /> + <Enum name="PWM1_CAP1" start="0x2" description="Capture input for PWM1, channel 1." /> + <Enum name="T0_MAT1" start="0x3" description="Match output for Timer 0, channel 1." /> + <Enum name="MC_2B" start="0x4" description="Motor control PWM channel 2, output B." /> + <Enum name="U4_TXD" start="0x5" description="Transmitter output for USART4 (input/output in smart card mode)." /> + <Enum name="LCD_VD_15" start="0x6" description="LCD data." /> + <Enum name="LCD_VD_23" start="0x7" description="LCD data." /> + </BitField> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor
 control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor
 enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin
 reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as
 1)." /> + </BitField> + <BitField start="7" size="2" name="RESERVED" description="Reserved." /> + <BitField start="9" size="1" name="SLEW" description="Driver slew rate"> + <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More
 outputs can be switched simultaneously." /> + <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the
 appropriate specific device data sheet for details." /> + </BitField> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain
 mode. Input cannot be pulled up above VDD." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0xF8" size="4" name="P1_30" access="Read/Write" description="I/O configuration register for pin P1[30]" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P1[30]"> + <Enum name="P1_30" start="0x0" description="General purpose digital input/output pin." /> + <Enum name="USB_PWRD2" start="0x1" description="Power Status for USB port 2." /> + <Enum name="USB_VBUS" start="0x2" description="Monitors the presence of USB bus power.This signal must be HIGH for USB reset to occur." /> + <Enum name="ADC0_IN_4" start="0x3" description="A/D converter 0, input 4. When configured as an ADC input, the digital function of the pin must be disabled." /> + <Enum name="I2C0_SDA" start="0x4" description="I2C0 data input/output (this pin does not use a specialized I2C pad." /> + <Enum name="U3_OE" start="0x5" description="RS-485/EIA-485 output enable signal for UART3." /> + </BitField> + </Register> + <Register start="+0xFC" size="4" name="P1_31" access="Read/Write" description="I/O configuration register for pin P1[31]" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P1[31]"> + <Enum name="P1_31" start="0x0" description="General purpose digital input/output pin." /> + <Enum name="USB_OVRCR2" start="0x1" description="Over-Current status for USB port 2." /> + <Enum name="SSP1_SCK" start="0x2" description="Serial Clock for SSP1." /> + <Enum name="ADC0_IN_5" start="0x3" description="A/D converter 0, input 5. When configured as an ADC input, the digital function of the pin must be disabled." /> + <Enum name="I2C0_SCL" start="0x4" description="I2C0 clock input/output (this pin does not use a specialized I2C pad." /> + </BitField> + </Register> + <Register start="+0x100" size="4" name="P2_0" access="Read/Write" description="I/O configuration register for pin P2[0]" reset_value="0x00000030" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P2[0]"> + <Enum name="P2_0" start="0x0" description="General purpose digital input/output pin." /> + <Enum name="PWM1_1" start="0x1" description="Pulse Width Modulator 1, channel 1 output." /> + <Enum name="U1_TXD" start="0x2" description="Transmitter output for UART1." /> + <Enum name="LCD_PWR" start="0x7" description="LCD panel power enable." /> + </BitField> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor
 control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor
 enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin
 reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as
 1)." /> + </BitField> + <BitField start="7" size="2" name="RESERVED" description="Reserved." /> + <BitField start="9" size="1" name="SLEW" description="Driver slew rate"> + <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More
 outputs can be switched simultaneously." /> + <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the
 appropriate specific device data sheet for details." /> + </BitField> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain
 mode. Input cannot be pulled up above VDD." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x104" size="4" name="P2_1" access="Read/Write" description="I/O configuration register for pin P2[1]" reset_value="0x00000030" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P2[1]"> + <Enum name="P2_1" start="0x0" description="General purpose digital input/output pin." /> + <Enum name="PWM1_2" start="0x1" description="Pulse Width Modulator 1, channel 2 output." /> + <Enum name="U1_RXD" start="0x2" description="Receiver input for UART1." /> + <Enum name="LCD_LE" start="0x7" description="Line end signal." /> + </BitField> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor
 control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor
 enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin
 reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as
 1)." /> + </BitField> + <BitField start="7" size="2" name="RESERVED" description="Reserved." /> + <BitField start="9" size="1" name="SLEW" description="Driver slew rate"> + <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More
 outputs can be switched simultaneously." /> + <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the
 appropriate specific device data sheet for details." /> + </BitField> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain
 mode. Input cannot be pulled up above VDD." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x108" size="4" name="P2_2" access="Read/Write" description="I/O configuration register for pin P2[2]" reset_value="0x00000030" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P2[2]"> + <Enum name="P2_2" start="0x0" description="General purpose digital input/output pin." /> + <Enum name="PWM1_3" start="0x1" description="Pulse Width Modulator 1, channel 3 output." /> + <Enum name="U1_CTS" start="0x2" description="Clear to Send input for UART1." /> + <Enum name="T2_MAT3" start="0x3" description="Match output for Timer 2, channel 3." /> + <Enum name="TRACEDATA_3" start="0x5" description="Trace data, bit 3." /> + <Enum name="LCD_DCLK" start="0x7" description="LCD panel clock." /> + </BitField> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor
 control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor
 enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin
 reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as
 1)." /> + </BitField> + <BitField start="7" size="2" name="RESERVED" description="Reserved." /> + <BitField start="9" size="1" name="SLEW" description="Driver slew rate"> + <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More
 outputs can be switched simultaneously." /> + <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the
 appropriate specific device data sheet for details." /> + </BitField> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain
 mode. Input cannot be pulled up above VDD." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x10C" size="4" name="P2_3" access="Read/Write" description="I/O configuration register for pin P2[3]" reset_value="0x00000030" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P2[3]"> + <Enum name="P2_3" start="0x0" description="General purpose digital input/output pin." /> + <Enum name="PWM1_4" start="0x1" description="Pulse Width Modulator 1, channel 4 output." /> + <Enum name="U1_DCD" start="0x2" description="Data Carrier Detect input for UART1." /> + <Enum name="T2_MAT2" start="0x3" description="Match output for Timer 2, channel 2." /> + <Enum name="TRACEDATA_2" start="0x5" description="Trace data, bit 2." /> + <Enum name="LCD_FP" start="0x7" description="Frame pulse (STN). Vertical synchronization pulse (TFT)." /> + </BitField> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor
 control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor
 enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin
 reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as
 1)." /> + </BitField> + <BitField start="7" size="2" name="RESERVED" description="Reserved." /> + <BitField start="9" size="1" name="SLEW" description="Driver slew rate"> + <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More
 outputs can be switched simultaneously." /> + <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the
 appropriate specific device data sheet for details." /> + </BitField> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain
 mode. Input cannot be pulled up above VDD." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x110" size="4" name="P2_4" access="Read/Write" description="I/O configuration register for pin P2[4]" reset_value="0x00000030" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P2[4]"> + <Enum name="P2_4" start="0x0" description="General purpose digital input/output pin." /> + <Enum name="PWM1_5" start="0x1" description="Pulse Width Modulator 1, channel 5 output." /> + <Enum name="U1_DSR" start="0x2" description="Data Set Ready input for UART1." /> + <Enum name="T2_MAT1" start="0x3" description="Match output for Timer 2, channel 1." /> + <Enum name="TRACEDATA_1" start="0x5" description="Trace data, bit 1." /> + <Enum name="LCD_ENAB_M" start="0x7" description="STN AC bias drive or TFT data enable output." /> + </BitField> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor
 control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor
 enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin
 reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as
 1)." /> + </BitField> + <BitField start="7" size="2" name="RESERVED" description="Reserved." /> + <BitField start="9" size="1" name="SLEW" description="Driver slew rate"> + <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More
 outputs can be switched simultaneously." /> + <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the
 appropriate specific device data sheet for details." /> + </BitField> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain
 mode. Input cannot be pulled up above VDD." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x114" size="4" name="P2_5" access="Read/Write" description="I/O configuration register for pin P2[5]" reset_value="0x00000030" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P2[5]"> + <Enum name="P2_5" start="0x0" description="General purpose digital input/output pin." /> + <Enum name="PWM1_6" start="0x1" description="Pulse Width Modulator 1, channel 6 output." /> + <Enum name="U1_DTR" start="0x2" description="Data Terminal Ready output for UART1. Can also be configured to be an RS-485/EIA-485 output enable signal for UART1." /> + <Enum name="T2_MAT0" start="0x3" description="Match output for Timer 2, channel 0." /> + <Enum name="TRACEDATA_0" start="0x5" description="Trace data, bit 0." /> + <Enum name="LCD_LP" start="0x7" description="Line synchronization pulse (STN). Horizontal synchronization pulse (TFT)." /> + </BitField> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor
 control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor
 enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin
 reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as
 1)." /> + </BitField> + <BitField start="7" size="2" name="RESERVED" description="Reserved." /> + <BitField start="9" size="1" name="SLEW" description="Driver slew rate"> + <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More
 outputs can be switched simultaneously." /> + <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the
 appropriate specific device data sheet for details." /> + </BitField> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain
 mode. Input cannot be pulled up above VDD." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x118" size="4" name="P2_6" access="Read/Write" description="I/O configuration register for pin P2[6]" reset_value="0x00000030" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P2[6]"> + <Enum name="P2_6" start="0x0" description="General purpose digital input/output pin." /> + <Enum name="PWM1_CAP0" start="0x1" description="Capture input for PWM1, channel 0." /> + <Enum name="U1_RI" start="0x2" description="Ring Indicator input for UART1." /> + <Enum name="T2_CAP0" start="0x3" description="Capture input for Timer 2, channel 0." /> + <Enum name="U2_OE" start="0x4" description="RS-485/EIA-485 output enable signal for UART2." /> + <Enum name="TRACECLK" start="0x5" description="Trace clock." /> + <Enum name="LCD_VD_0" start="0x6" description="LCD data." /> + <Enum name="LCD_VD_4" start="0x7" description="LCD data." /> + </BitField> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor
 control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor
 enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin
 reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as
 1)." /> + </BitField> + <BitField start="7" size="2" name="RESERVED" description="Reserved." /> + <BitField start="9" size="1" name="SLEW" description="Driver slew rate"> + <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More
 outputs can be switched simultaneously." /> + <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the
 appropriate specific device data sheet for details." /> + </BitField> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain
 mode. Input cannot be pulled up above VDD." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x11C" size="4" name="P2_7" access="Read/Write" description="I/O configuration register for pin P2[7]" reset_value="0x00000030" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P2[7]"> + <Enum name="P2_7" start="0x0" description="General purpose digital input/output pin." /> + <Enum name="CAN_RD2" start="0x1" description="CAN2 receiver input." /> + <Enum name="U1_RTS" start="0x2" description="Request to Send output for UART1. Can also be configured to be an RS-485/EIA-485 output enable signal for UART1." /> + <Enum name="SPIFI_CS" start="0x5" description="Chip select output for SPIFI." /> + <Enum name="LCD_VD_1" start="0x6" description="LCD data." /> + <Enum name="LCD_VD_5" start="0x7" description="LCD data." /> + </BitField> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor
 control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor
 enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin
 reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as
 1)." /> + </BitField> + <BitField start="7" size="2" name="RESERVED" description="Reserved." /> + <BitField start="9" size="1" name="SLEW" description="Driver slew rate"> + <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More
 outputs can be switched simultaneously." /> + <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the
 appropriate specific device data sheet for details." /> + </BitField> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain
 mode. Input cannot be pulled up above VDD." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x120" size="4" name="P2_8" access="Read/Write" description="I/O configuration register for pin P2[8]" reset_value="0x00000030" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P2[8]"> + <Enum name="P2_8" start="0x0" description="General purpose digital input/output pin." /> + <Enum name="CAN_TD2" start="0x1" description="CAN2 transmitter output." /> + <Enum name="U2_TXD" start="0x2" description="Transmitter output for UART2." /> + <Enum name="U1_CTS" start="0x3" description="Clear to Send input for UART1." /> + <Enum name="ENET_MDC" start="0x4" description="Ethernet MIIM clock." /> + <Enum name="LCD_VD_2" start="0x6" description="LCD data." /> + <Enum name="LCD_VD_6" start="0x7" description="LCD data." /> + </BitField> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor
 control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor
 enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin
 reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as
 1)." /> + </BitField> + <BitField start="7" size="2" name="RESERVED" description="Reserved." /> + <BitField start="9" size="1" name="SLEW" description="Driver slew rate"> + <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More
 outputs can be switched simultaneously." /> + <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the
 appropriate specific device data sheet for details." /> + </BitField> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain
 mode. Input cannot be pulled up above VDD." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x124" size="4" name="P2_9" access="Read/Write" description="I/O configuration register for pin P2[9]" reset_value="0x00000030" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P2[9]"> + <Enum name="P2_9" start="0x0" description="General purpose digital input/output pin." /> + <Enum name="USB_CONNECT1" start="0x1" description="USB1 SoftConnect control. Signal used to switch an external 1.5 kW resistor under the software control. Used with the SoftConnect USB feature." /> + <Enum name="U2_RXD" start="0x2" description="Receiver input for UART2." /> + <Enum name="U4_RXD" start="0x3" description="Receiver input for USART4." /> + <Enum name="ENET_MDIO" start="0x4" description="Ethernet MIIM data input and output." /> + <Enum name="LCD_VD_3" start="0x6" description="LCD data." /> + <Enum name="LCD_VD_7" start="0x7" description="LCD data." /> + </BitField> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor
 control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor
 enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin
 reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as
 1)." /> + </BitField> + <BitField start="7" size="2" name="RESERVED" description="Reserved." /> + <BitField start="9" size="1" name="SLEW" description="Driver slew rate"> + <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More
 outputs can be switched simultaneously." /> + <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the
 appropriate specific device data sheet for details." /> + </BitField> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain
 mode. Input cannot be pulled up above VDD." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x128" size="4" name="P2_10" access="Read/Write" description="I/O configuration register for pin P2[10]" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P2[10]"> + <Enum name="P2_10" start="0x0" description="General purpose digital input/output pin. This pin
 includes a 5 ns input glitch filter.A LOW on this pin while RESET is LOW forces the on-chip
 boot loader to take over control of the part after a reset and
 go into ISP mode. " /> + <Enum name="EINT0" start="0x1" description="External interrupt 0 input." /> + <Enum name="NMI" start="0x2" description="Non-maskable interrupt input." /> + </BitField> + </Register> + <Register start="+0x12C" size="4" name="P2_11" access="Read/Write" description="I/O configuration register for pin P2[11]" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P2[11]"> + <Enum name="P2_11" start="0x0" description="General purpose digital input/output pin. This pin
 includes a 5 ns input glitch filter." /> + <Enum name="EINT1" start="0x1" description="External interrupt 1 input." /> + <Enum name="SD_DAT_1" start="0x2" description="Data line 1 for SD card interface." /> + <Enum name="I2S_TX_SCK" start="0x3" description="Transmit Clock. It is driven by the master and received by the slave. Corresponds to the signal SCK in the I2S-bus specification." /> + <Enum name="LCD_CLKIN" start="0x7" description="LCD clock." /> + </BitField> + </Register> + <Register start="+0x130" size="4" name="P2_12" access="Read/Write" description="I/O configuration register for pin P2[12]" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P2[12]"> + <Enum name="P2_12" start="0x0" description="General purpose digital input/output pin. This pin
 includes a 5 ns input glitch filter." /> + <Enum name="EINT2" start="0x1" description="External interrupt 2 input." /> + <Enum name="SD_DAT_2" start="0x2" description="Data line 2 for SD card interface." /> + <Enum name="I2S_TX_WS" start="0x3" description="Transmit Word Select. It is driven by the master and received by the slave. Corresponds to the signal WS in the I2S-bus specification." /> + <Enum name="LCD_VD_4" start="0x4" description="LCD data." /> + <Enum name="LCD_VD_3" start="0x5" description="LCD data." /> + <Enum name="LCD_VD_8" start="0x6" description="LCD data." /> + <Enum name="LCD_VD_18" start="0x7" description="LCD data." /> + </BitField> + </Register> + <Register start="+0x134" size="4" name="P2_13" access="Read/Write" description="I/O configuration register for pin P2[13]" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P2[13]"> + <Enum name="P2_13" start="0x0" description="General purpose digital input/output pin. This pin
 includes a 5 ns input glitch filter." /> + <Enum name="EINT3" start="0x1" description="External interrupt 3 input." /> + <Enum name="SD_DAT_3" start="0x2" description="Data line 3 for SD card interface." /> + <Enum name="I2S_TX_SDA" start="0x3" description="Transmit data. It is driven by the transmitter and read by the receiver. Corresponds to the signal SD in the I2S-bus specification." /> + <Enum name="LCD_VD_5" start="0x5" description="LCD data." /> + <Enum name="LCD_VD_9" start="0x6" description="LCD data." /> + <Enum name="LCD_VD_19" start="0x7" description="LCD data." /> + </BitField> + </Register> + <Register start="+0x138" size="4" name="P2_14" access="Read/Write" description="I/O configuration register for pin P2[14]" reset_value="0x00000030" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P2[14]"> + <Enum name="P2_14" start="0x0" description="General purpose digital input/output pin." /> + <Enum name="EMC_CS2" start="0x1" description="LOW active Chip Select 2 signal." /> + <Enum name="I2C1_SDA" start="0x2" description="I2C1 data input/output (this pin does not use a specialized I2C pad)." /> + <Enum name="T2_CAP0" start="0x3" description="Capture input for Timer 2, channel 0." /> + </BitField> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor
 control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor
 enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin
 reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as
 1)." /> + </BitField> + <BitField start="7" size="2" name="RESERVED" description="Reserved." /> + <BitField start="9" size="1" name="SLEW" description="Driver slew rate"> + <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More
 outputs can be switched simultaneously." /> + <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the
 appropriate specific device data sheet for details." /> + </BitField> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain
 mode. Input cannot be pulled up above VDD." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x13C" size="4" name="P2_15" access="Read/Write" description="I/O configuration register for pin P2[15]" reset_value="0x00000030" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P2[15]"> + <Enum name="P2_15" start="0x0" description="General purpose digital input/output pin." /> + <Enum name="EMC_CS3" start="0x1" description="LOW active Chip Select 3 signal." /> + <Enum name="I2C1_SCL" start="0x2" description="I2C1 clock input/output (this pin does not use a specialized I2C pad)." /> + <Enum name="T2_CAP1" start="0x3" description="Capture input for Timer 2, channel 1." /> + </BitField> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor
 control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor
 enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin
 reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as
 1)." /> + </BitField> + <BitField start="7" size="2" name="RESERVED" description="Reserved." /> + <BitField start="9" size="1" name="SLEW" description="Driver slew rate"> + <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More
 outputs can be switched simultaneously." /> + <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the
 appropriate specific device data sheet for details." /> + </BitField> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain
 mode. Input cannot be pulled up above VDD." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x140" size="4" name="P2_16" access="Read/Write" description="I/O configuration register for pin P2[16]" reset_value="0x00000030" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P2[16]"> + <Enum name="P2_16" start="0x0" description="General purpose digital input/output pin." /> + <Enum name="EMC_CAS" start="0x1" description="LOW active SDRAM Column Address Strobe." /> + </BitField> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor
 control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor
 enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin
 reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as
 1)." /> + </BitField> + <BitField start="7" size="2" name="RESERVED" description="Reserved." /> + <BitField start="9" size="1" name="SLEW" description="Driver slew rate"> + <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More
 outputs can be switched simultaneously." /> + <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the
 appropriate specific device data sheet for details." /> + </BitField> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain
 mode. Input cannot be pulled up above VDD." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x144" size="4" name="P2_17" access="Read/Write" description="I/O configuration register for pin P2[17]" reset_value="0x00000030" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P2[17]"> + <Enum name="P2_17" start="0x0" description="General purpose digital input/output pin." /> + <Enum name="EMC_RAS" start="0x1" description="LOW active SDRAM Row Address Strobe." /> + </BitField> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor
 control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor
 enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin
 reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as
 1)." /> + </BitField> + <BitField start="7" size="2" name="RESERVED" description="Reserved." /> + <BitField start="9" size="1" name="SLEW" description="Driver slew rate"> + <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More
 outputs can be switched simultaneously." /> + <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the
 appropriate specific device data sheet for details." /> + </BitField> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain
 mode. Input cannot be pulled up above VDD." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x148" size="4" name="P2_18" access="Read/Write" description="I/O configuration register for pin P2[18]" reset_value="0x000001B0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P2[18]"> + <Enum name="P2_18" start="0x0" description="General purpose digital input/output pin." /> + <Enum name="EMC_CLK_0" start="0x1" description="SDRAM clock 0." /> + </BitField> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor
 control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor
 enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin
 reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as
 1)." /> + </BitField> + <BitField start="7" size="1" name="ADMODE" description="Selects Analog/Digital mode."> + <Enum name="ANALOG_INPUT_MODE_" start="0" description="Analog input mode." /> + <Enum name="DIGITAL_FUNCTIONAL_M" start="1" description="Digital functional mode." /> + </BitField> + <BitField start="8" size="1" name="FILTR" description="Selects 10 ns input glitch filter."> + <Enum name="FILTER_DISABLED_" start="0" description="Filter disabled." /> + <Enum name="FILTER_ENABLED_" start="1" description="Filter enabled." /> + </BitField> + <BitField start="9" size="1" name="RESERVED" description="Reserved." /> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain
 mode." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x14C" size="4" name="P2_19" access="Read/Write" description="I/O configuration register for pin P2[19]" reset_value="0x000001B0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P2[19]"> + <Enum name="P2_19" start="0x0" description="General purpose digital input/output pin." /> + <Enum name="EMC_CLK_1" start="0x1" description="SDRAM clock 1." /> + </BitField> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor
 control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor
 enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin
 reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as
 1)." /> + </BitField> + <BitField start="7" size="1" name="ADMODE" description="Selects Analog/Digital mode."> + <Enum name="ANALOG_INPUT_MODE_" start="0" description="Analog input mode." /> + <Enum name="DIGITAL_FUNCTIONAL_M" start="1" description="Digital functional mode." /> + </BitField> + <BitField start="8" size="1" name="FILTR" description="Selects 10 ns input glitch filter."> + <Enum name="FILTER_DISABLED_" start="0" description="Filter disabled." /> + <Enum name="FILTER_ENABLED_" start="1" description="Filter enabled." /> + </BitField> + <BitField start="9" size="1" name="RESERVED" description="Reserved." /> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain
 mode." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x150" size="4" name="P2_20" access="Read/Write" description="I/O configuration register for pin P2[20]" reset_value="0x00000030" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P2[20]"> + <Enum name="P2_20" start="0x0" description="General purpose digital input/output pin." /> + <Enum name="EMC_DYCS0" start="0x1" description="SDRAM chip select 0." /> + </BitField> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor
 control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor
 enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin
 reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as
 1)." /> + </BitField> + <BitField start="7" size="2" name="RESERVED" description="Reserved." /> + <BitField start="9" size="1" name="SLEW" description="Driver slew rate"> + <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More
 outputs can be switched simultaneously." /> + <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the
 appropriate specific device data sheet for details." /> + </BitField> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain
 mode. Input cannot be pulled up above VDD." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x154" size="4" name="P2_21" access="Read/Write" description="I/O configuration register for pin P2[21]" reset_value="0x00000030" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P2[21]"> + <Enum name="P2_21" start="0x0" description="General purpose digital input/output pin." /> + <Enum name="EMC_DYCS1" start="0x1" description="SDRAM chip select 1." /> + </BitField> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor
 control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor
 enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin
 reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as
 1)." /> + </BitField> + <BitField start="7" size="2" name="RESERVED" description="Reserved." /> + <BitField start="9" size="1" name="SLEW" description="Driver slew rate"> + <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More
 outputs can be switched simultaneously." /> + <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the
 appropriate specific device data sheet for details." /> + </BitField> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain
 mode. Input cannot be pulled up above VDD." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x158" size="4" name="P2_22" access="Read/Write" description="I/O configuration register for pin P2[22]" reset_value="0x00000030" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P2[22]"> + <Enum name="P2_22" start="0x0" description="General purpose digital input/output pin." /> + <Enum name="EMC_DYCS2" start="0x1" description="SDRAM chip select 2." /> + <Enum name="SSP0_SCK" start="0x2" description="Serial clock for SSP0." /> + <Enum name="T3_CAP0" start="0x3" description="Capture input for Timer 3, channel 0." /> + </BitField> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor
 control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor
 enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin
 reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as
 1)." /> + </BitField> + <BitField start="7" size="2" name="RESERVED" description="Reserved." /> + <BitField start="9" size="1" name="SLEW" description="Driver slew rate"> + <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More
 outputs can be switched simultaneously." /> + <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the
 appropriate specific device data sheet for details." /> + </BitField> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain
 mode. Input cannot be pulled up above VDD." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x15C" size="4" name="P2_23" access="Read/Write" description="I/O configuration register for pin P2[23]" reset_value="0x00000030" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P2[23]"> + <Enum name="P2_23" start="0x0" description="General purpose digital input/output pin." /> + <Enum name="EMC_DYCS3" start="0x1" description="SDRAM chip select 3." /> + <Enum name="SSP0_SSEL" start="0x2" description="Slave Select for SSP0." /> + <Enum name="T3_CAP1" start="0x3" description="Capture input for Timer 3, channel 1." /> + </BitField> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor
 control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor
 enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin
 reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as
 1)." /> + </BitField> + <BitField start="7" size="2" name="RESERVED" description="Reserved." /> + <BitField start="9" size="1" name="SLEW" description="Driver slew rate"> + <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More
 outputs can be switched simultaneously." /> + <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the
 appropriate specific device data sheet for details." /> + </BitField> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain
 mode. Input cannot be pulled up above VDD." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x160" size="4" name="P2_24" access="Read/Write" description="I/O configuration register for pin P2[24]" reset_value="0x00000030" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P2[24]"> + <Enum name="P2_24" start="0x0" description="General purpose digital input/output pin." /> + <Enum name="EMC_CKE0" start="0x1" description="SDRAM clock enable 0." /> + </BitField> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor
 control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor
 enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin
 reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as
 1)." /> + </BitField> + <BitField start="7" size="2" name="RESERVED" description="Reserved." /> + <BitField start="9" size="1" name="SLEW" description="Driver slew rate"> + <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More
 outputs can be switched simultaneously." /> + <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the
 appropriate specific device data sheet for details." /> + </BitField> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain
 mode. Input cannot be pulled up above VDD." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x164" size="4" name="P2_25" access="Read/Write" description="I/O configuration register for pin P2[25]" reset_value="0x00000030" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P2[25]"> + <Enum name="P2_25" start="0x0" description="General purpose digital input/output pin." /> + <Enum name="EMC_CKE1" start="0x1" description="SDRAM clock enable 1." /> + </BitField> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor
 control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor
 enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin
 reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as
 1)." /> + </BitField> + <BitField start="7" size="2" name="RESERVED" description="Reserved." /> + <BitField start="9" size="1" name="SLEW" description="Driver slew rate"> + <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More
 outputs can be switched simultaneously." /> + <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the
 appropriate specific device data sheet for details." /> + </BitField> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain
 mode. Input cannot be pulled up above VDD." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x168" size="4" name="P2_26" access="Read/Write" description="I/O configuration register for pin P2[26]" reset_value="0x00000030" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P2[26]"> + <Enum name="P2_26" start="0x0" description="General purpose digital input/output pin." /> + <Enum name="EMC_CKE2" start="0x1" description="SDRAM clock enable 2." /> + <Enum name="SSP0_MISO" start="0x2" description="Master In Slave Out for SSP0." /> + <Enum name="T3_MAT0" start="0x3" description="Match output for Timer 3, channel 0." /> + </BitField> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor
 control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor
 enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin
 reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as
 1)." /> + </BitField> + <BitField start="7" size="2" name="RESERVED" description="Reserved." /> + <BitField start="9" size="1" name="SLEW" description="Driver slew rate"> + <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More
 outputs can be switched simultaneously." /> + <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the
 appropriate specific device data sheet for details." /> + </BitField> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain
 mode. Input cannot be pulled up above VDD." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x16C" size="4" name="P2_27" access="Read/Write" description="I/O configuration register for pin P2[27]" reset_value="0x00000030" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P2[27]"> + <Enum name="P2_27" start="0x0" description="General purpose digital input/output pin." /> + <Enum name="EMC_CKE3" start="0x1" description="SDRAM clock enable 3." /> + <Enum name="SSP0_MOSI" start="0x2" description="Master Out Slave In for SSP0." /> + <Enum name="T3_MAT1" start="0x3" description="Match output for Timer 3, channel 1." /> + </BitField> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor
 control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor
 enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin
 reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as
 1)." /> + </BitField> + <BitField start="7" size="2" name="RESERVED" description="Reserved." /> + <BitField start="9" size="1" name="SLEW" description="Driver slew rate"> + <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More
 outputs can be switched simultaneously." /> + <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the
 appropriate specific device data sheet for details." /> + </BitField> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain
 mode. Input cannot be pulled up above VDD." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x170" size="4" name="P2_28" access="Read/Write" description="I/O configuration register for pin P2[28]" reset_value="0x00000030" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P2[28]"> + <Enum name="P2_28" start="0x0" description="General purpose digital input/output pin." /> + <Enum name="EMC_DQM0" start="0x1" description="Data mask 0 used with SDRAM and static devices." /> + </BitField> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor
 control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor
 enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin
 reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as
 1)." /> + </BitField> + <BitField start="7" size="2" name="RESERVED" description="Reserved." /> + <BitField start="9" size="1" name="SLEW" description="Driver slew rate"> + <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More
 outputs can be switched simultaneously." /> + <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the
 appropriate specific device data sheet for details." /> + </BitField> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain
 mode. Input cannot be pulled up above VDD." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x174" size="4" name="P2_29" access="Read/Write" description="I/O configuration register for pin P2[29]" reset_value="0x00000030" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P2[29]"> + <Enum name="P2_29" start="0x0" description="General purpose digital input/output pin." /> + <Enum name="EMC_DQM1" start="0x1" description="Data mask 1 used with SDRAM and static devices." /> + </BitField> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor
 control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor
 enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin
 reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as
 1)." /> + </BitField> + <BitField start="7" size="2" name="RESERVED" description="Reserved." /> + <BitField start="9" size="1" name="SLEW" description="Driver slew rate"> + <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More
 outputs can be switched simultaneously." /> + <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the
 appropriate specific device data sheet for details." /> + </BitField> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain
 mode. Input cannot be pulled up above VDD." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x178" size="4" name="P2_30" access="Read/Write" description="I/O configuration register for pin P2[30]" reset_value="0x00000030" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P2[30]"> + <Enum name="P2_30" start="0x0" description="General purpose digital input/output pin." /> + <Enum name="EMC_DQM2" start="0x1" description="Data mask 2 used with SDRAM and static devices." /> + <Enum name="I2C2_SDA" start="0x2" description="I2C2 data input/output (this pin does not use a specialized I2C pad)." /> + <Enum name="T3_MAT2" start="0x3" description="Match output for Timer 3, channel 2." /> + </BitField> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor
 control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor
 enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin
 reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as
 1)." /> + </BitField> + <BitField start="7" size="2" name="RESERVED" description="Reserved." /> + <BitField start="9" size="1" name="SLEW" description="Driver slew rate"> + <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More
 outputs can be switched simultaneously." /> + <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the
 appropriate specific device data sheet for details." /> + </BitField> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain
 mode. Input cannot be pulled up above VDD." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x17C" size="4" name="P2_31" access="Read/Write" description="I/O configuration register for pin P2[31]" reset_value="0x00000030" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P2[31]"> + <Enum name="P2_31" start="0x0" description="General purpose digital input/output pin." /> + <Enum name="EMC_DQM3" start="0x1" description="Data mask 3 used with SDRAM and static devices." /> + <Enum name="I2C2_SCL" start="0x2" description="I2C2 clock input/output (this pin does not use a specialized I2C pad)." /> + <Enum name="T3_MAT3" start="0x3" description="Match output for Timer 3, channel 3." /> + </BitField> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor
 control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor
 enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin
 reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as
 1)." /> + </BitField> + <BitField start="7" size="2" name="RESERVED" description="Reserved." /> + <BitField start="9" size="1" name="SLEW" description="Driver slew rate"> + <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More
 outputs can be switched simultaneously." /> + <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the
 appropriate specific device data sheet for details." /> + </BitField> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain
 mode. Input cannot be pulled up above VDD." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x180" size="4" name="P3_0" access="Read/Write" description="I/O configuration register for pin P3[0]" reset_value="0x00000030" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P3[0]"> + <Enum name="P3_0" start="0x0" description="General purpose digital input/output pin." /> + <Enum name="EMC_D_0" start="0x1" description="External memory data line 0." /> + </BitField> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor
 control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor
 enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin
 reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as
 1)." /> + </BitField> + <BitField start="7" size="2" name="RESERVED" description="Reserved." /> + <BitField start="9" size="1" name="SLEW" description="Driver slew rate"> + <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More
 outputs can be switched simultaneously." /> + <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the
 appropriate specific device data sheet for details." /> + </BitField> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain
 mode. Input cannot be pulled up above VDD." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x184" size="4" name="P3_1" access="Read/Write" description="I/O configuration register for pin P3[1]" reset_value="0x00000030" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P3[1]"> + <Enum name="P3_1" start="0x0" description="General purpose digital input/output pin." /> + <Enum name="EMC_D_1" start="0x1" description="External memory data line 1." /> + </BitField> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor
 control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor
 enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin
 reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as
 1)." /> + </BitField> + <BitField start="7" size="2" name="RESERVED" description="Reserved." /> + <BitField start="9" size="1" name="SLEW" description="Driver slew rate"> + <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More
 outputs can be switched simultaneously." /> + <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the
 appropriate specific device data sheet for details." /> + </BitField> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain
 mode. Input cannot be pulled up above VDD." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x188" size="4" name="P3_2" access="Read/Write" description="I/O configuration register for pin P3[2]" reset_value="0x00000030" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P3[2]"> + <Enum name="P3_2" start="0x0" description="General purpose digital input/output pin." /> + <Enum name="EMC_D_2" start="0x1" description="External memory data line 2." /> + </BitField> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor
 control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor
 enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin
 reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as
 1)." /> + </BitField> + <BitField start="7" size="2" name="RESERVED" description="Reserved." /> + <BitField start="9" size="1" name="SLEW" description="Driver slew rate"> + <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More
 outputs can be switched simultaneously." /> + <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the
 appropriate specific device data sheet for details." /> + </BitField> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain
 mode. Input cannot be pulled up above VDD." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x18C" size="4" name="P3_3" access="Read/Write" description="I/O configuration register for pin P3[3]" reset_value="0x00000030" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P3[3]"> + <Enum name="P3_3" start="0x0" description="General purpose digital input/output pin." /> + <Enum name="EMC_D_3" start="0x1" description="External memory data line 3." /> + </BitField> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor
 control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor
 enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin
 reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as
 1)." /> + </BitField> + <BitField start="7" size="2" name="RESERVED" description="Reserved." /> + <BitField start="9" size="1" name="SLEW" description="Driver slew rate"> + <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More
 outputs can be switched simultaneously." /> + <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the
 appropriate specific device data sheet for details." /> + </BitField> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain
 mode. Input cannot be pulled up above VDD." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x190" size="4" name="P3_4" access="Read/Write" description="I/O configuration register for pin P3[4]" reset_value="0x00000030" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P3[4]"> + <Enum name="P3_4" start="0x0" description="General purpose digital input/output pin." /> + <Enum name="EMC_D_4" start="0x1" description="External memory data line 4." /> + </BitField> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor
 control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor
 enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin
 reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as
 1)." /> + </BitField> + <BitField start="7" size="2" name="RESERVED" description="Reserved." /> + <BitField start="9" size="1" name="SLEW" description="Driver slew rate"> + <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More
 outputs can be switched simultaneously." /> + <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the
 appropriate specific device data sheet for details." /> + </BitField> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain
 mode. Input cannot be pulled up above VDD." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x194" size="4" name="P3_5" access="Read/Write" description="I/O configuration register for pin P3[5]" reset_value="0x00000030" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P3[5]"> + <Enum name="P3_5" start="0x0" description="General purpose digital input/output pin." /> + <Enum name="EMC_D_5" start="0x1" description="External memory data line 5." /> + </BitField> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor
 control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor
 enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin
 reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as
 1)." /> + </BitField> + <BitField start="7" size="2" name="RESERVED" description="Reserved." /> + <BitField start="9" size="1" name="SLEW" description="Driver slew rate"> + <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More
 outputs can be switched simultaneously." /> + <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the
 appropriate specific device data sheet for details." /> + </BitField> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain
 mode. Input cannot be pulled up above VDD." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x198" size="4" name="P3_6" access="Read/Write" description="I/O configuration register for pin P3[6]" reset_value="0x00000030" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P3[6]"> + <Enum name="P3_6" start="0x0" description="General purpose digital input/output pin." /> + <Enum name="EMC_D_6" start="0x1" description="External memory data line 6." /> + </BitField> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor
 control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor
 enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin
 reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as
 1)." /> + </BitField> + <BitField start="7" size="2" name="RESERVED" description="Reserved." /> + <BitField start="9" size="1" name="SLEW" description="Driver slew rate"> + <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More
 outputs can be switched simultaneously." /> + <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the
 appropriate specific device data sheet for details." /> + </BitField> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain
 mode. Input cannot be pulled up above VDD." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x19C" size="4" name="P3_7" access="Read/Write" description="I/O configuration register for pin P3[7]" reset_value="0x00000030" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P3[7]"> + <Enum name="P3_7" start="0x0" description="General purpose digital input/output pin." /> + <Enum name="EMC_D_7" start="0x1" description="External memory data line 7." /> + </BitField> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor
 control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor
 enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin
 reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as
 1)." /> + </BitField> + <BitField start="7" size="2" name="RESERVED" description="Reserved." /> + <BitField start="9" size="1" name="SLEW" description="Driver slew rate"> + <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More
 outputs can be switched simultaneously." /> + <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the
 appropriate specific device data sheet for details." /> + </BitField> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain
 mode. Input cannot be pulled up above VDD." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x1A0" size="4" name="P3_8" access="Read/Write" description="I/O configuration register for pin P3[8]" reset_value="0x00000030" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P3[8]"> + <Enum name="P3_8" start="0x0" description="General purpose digital input/output pin." /> + <Enum name="EMC_D_8" start="0x1" description="External memory data line 8." /> + </BitField> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor
 control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor
 enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin
 reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as
 1)." /> + </BitField> + <BitField start="7" size="2" name="RESERVED" description="Reserved." /> + <BitField start="9" size="1" name="SLEW" description="Driver slew rate"> + <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More
 outputs can be switched simultaneously." /> + <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the
 appropriate specific device data sheet for details." /> + </BitField> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain
 mode. Input cannot be pulled up above VDD." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x1A4" size="4" name="P3_9" access="Read/Write" description="I/O configuration register for pin P3[9]" reset_value="0x00000030" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P3[9]"> + <Enum name="P3_9" start="0x0" description="General purpose digital input/output pin." /> + <Enum name="EMC_D_9" start="0x1" description="External memory data line 9." /> + </BitField> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor
 control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor
 enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin
 reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as
 1)." /> + </BitField> + <BitField start="7" size="2" name="RESERVED" description="Reserved." /> + <BitField start="9" size="1" name="SLEW" description="Driver slew rate"> + <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More
 outputs can be switched simultaneously." /> + <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the
 appropriate specific device data sheet for details." /> + </BitField> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain
 mode. Input cannot be pulled up above VDD." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x1A8" size="4" name="P3_10" access="Read/Write" description="I/O configuration register for pin P3[10]" reset_value="0x00000030" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P3[10]"> + <Enum name="P3_10" start="0x0" description="General purpose digital input/output pin." /> + <Enum name="EMC_D_10" start="0x1" description="External memory data line 10." /> + </BitField> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor
 control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor
 enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin
 reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as
 1)." /> + </BitField> + <BitField start="7" size="2" name="RESERVED" description="Reserved." /> + <BitField start="9" size="1" name="SLEW" description="Driver slew rate"> + <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More
 outputs can be switched simultaneously." /> + <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the
 appropriate specific device data sheet for details." /> + </BitField> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain
 mode. Input cannot be pulled up above VDD." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x1AC" size="4" name="P3_11" access="Read/Write" description="I/O configuration register for pin P3[11]" reset_value="0x00000030" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P3[11]"> + <Enum name="P3_11" start="0x0" description="General purpose digital input/output pin." /> + <Enum name="EMC_D_11" start="0x1" description="External memory data line 11." /> + </BitField> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor
 control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor
 enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin
 reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as
 1)." /> + </BitField> + <BitField start="7" size="2" name="RESERVED" description="Reserved." /> + <BitField start="9" size="1" name="SLEW" description="Driver slew rate"> + <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More
 outputs can be switched simultaneously." /> + <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the
 appropriate specific device data sheet for details." /> + </BitField> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain
 mode. Input cannot be pulled up above VDD." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x1B0" size="4" name="P3_12" access="Read/Write" description="I/O configuration register for pin P3[12]" reset_value="0x00000030" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P3[12]"> + <Enum name="P3_12" start="0x0" description="General purpose digital input/output pin." /> + <Enum name="EMC_D_12" start="0x1" description="External memory data line 12." /> + </BitField> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor
 control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor
 enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin
 reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as
 1)." /> + </BitField> + <BitField start="7" size="2" name="RESERVED" description="Reserved." /> + <BitField start="9" size="1" name="SLEW" description="Driver slew rate"> + <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More
 outputs can be switched simultaneously." /> + <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the
 appropriate specific device data sheet for details." /> + </BitField> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain
 mode. Input cannot be pulled up above VDD." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x1B4" size="4" name="P3_13" access="Read/Write" description="I/O configuration register for pin P3[13]" reset_value="0x00000030" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P3[13]"> + <Enum name="P3_13" start="0x0" description="General purpose digital input/output pin." /> + <Enum name="EMC_D_13" start="0x1" description="External memory data line 13." /> + </BitField> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor
 control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor
 enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin
 reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as
 1)." /> + </BitField> + <BitField start="7" size="2" name="RESERVED" description="Reserved." /> + <BitField start="9" size="1" name="SLEW" description="Driver slew rate"> + <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More
 outputs can be switched simultaneously." /> + <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the
 appropriate specific device data sheet for details." /> + </BitField> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain
 mode. Input cannot be pulled up above VDD." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x1B8" size="4" name="P3_14" access="Read/Write" description="I/O configuration register for pin P3[14]" reset_value="0x00000030" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P3[14]"> + <Enum name="P3_14" start="0x0" description="General purpose digital input/output pin." /> + <Enum name="EMC_D_14" start="0x1" description="External memory data line 14. " /> + </BitField> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor
 control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor
 enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin
 reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as
 1)." /> + </BitField> + <BitField start="7" size="2" name="RESERVED" description="Reserved." /> + <BitField start="9" size="1" name="SLEW" description="Driver slew rate"> + <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More
 outputs can be switched simultaneously." /> + <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the
 appropriate specific device data sheet for details." /> + </BitField> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain
 mode. Input cannot be pulled up above VDD." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x1BC" size="4" name="P3_15" access="Read/Write" description="I/O configuration register for pin P3[15]" reset_value="0x00000030" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P3[15]"> + <Enum name="P3_15" start="0x0" description="General purpose digital input/output pin." /> + <Enum name="EMC_D_15" start="0x1" description="External memory data line 15. " /> + </BitField> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor
 control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor
 enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin
 reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as
 1)." /> + </BitField> + <BitField start="7" size="2" name="RESERVED" description="Reserved." /> + <BitField start="9" size="1" name="SLEW" description="Driver slew rate"> + <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More
 outputs can be switched simultaneously." /> + <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the
 appropriate specific device data sheet for details." /> + </BitField> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain
 mode. Input cannot be pulled up above VDD." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x1C0" size="4" name="P3_16" access="Read/Write" description="I/O configuration register for pin P3[16]" reset_value="0x00000030" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P3[16]"> + <Enum name="P3_16" start="0x0" description="General purpose digital input/output pin." /> + <Enum name="EMC_D_16" start="0x1" description="External memory data line 16." /> + <Enum name="PWM0_1" start="0x2" description="Pulse Width Modulator 0, output 1." /> + <Enum name="U1_TXD" start="0x3" description="Transmitter output for UART1." /> + </BitField> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor
 control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor
 enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin
 reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as
 1)." /> + </BitField> + <BitField start="7" size="2" name="RESERVED" description="Reserved." /> + <BitField start="9" size="1" name="SLEW" description="Driver slew rate"> + <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More
 outputs can be switched simultaneously." /> + <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the
 appropriate specific device data sheet for details." /> + </BitField> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain
 mode. Input cannot be pulled up above VDD." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x1C4" size="4" name="P3_17" access="Read/Write" description="I/O configuration register for pin P3[17]" reset_value="0x00000030" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P3[17]"> + <Enum name="P3_17" start="0x0" description="General purpose digital input/output pin." /> + <Enum name="EMC_D_17" start="0x1" description="External memory data line 17." /> + <Enum name="PWM0_2" start="0x2" description="Pulse Width Modulator 0, output 2." /> + <Enum name="U1_RXD" start="0x3" description="Receiver input for UART1." /> + </BitField> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor
 control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor
 enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin
 reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as
 1)." /> + </BitField> + <BitField start="7" size="2" name="RESERVED" description="Reserved." /> + <BitField start="9" size="1" name="SLEW" description="Driver slew rate"> + <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More
 outputs can be switched simultaneously." /> + <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the
 appropriate specific device data sheet for details." /> + </BitField> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain
 mode. Input cannot be pulled up above VDD." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x1C8" size="4" name="P3_18" access="Read/Write" description="I/O configuration register for pin P3[18]" reset_value="0x00000030" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P3[18]"> + <Enum name="P3_18" start="0x0" description="General purpose digital input/output pin." /> + <Enum name="EMC_D_18" start="0x1" description="External memory data line 18." /> + <Enum name="PWM0_3" start="0x2" description="Pulse Width Modulator 0, output 3." /> + <Enum name="U1_CTS" start="0x3" description="Clear to Send input for UART1." /> + </BitField> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor
 control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor
 enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin
 reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as
 1)." /> + </BitField> + <BitField start="7" size="2" name="RESERVED" description="Reserved." /> + <BitField start="9" size="1" name="SLEW" description="Driver slew rate"> + <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More
 outputs can be switched simultaneously." /> + <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the
 appropriate specific device data sheet for details." /> + </BitField> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain
 mode. Input cannot be pulled up above VDD." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x1CC" size="4" name="P3_19" access="Read/Write" description="I/O configuration register for pin P3[19]" reset_value="0x00000030" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P3[19]"> + <Enum name="P3_19" start="0x0" description="General purpose digital input/output pin." /> + <Enum name="EMC_D_19" start="0x1" description="External memory data line 19." /> + <Enum name="PWM0_4" start="0x2" description="Pulse Width Modulator 0, output 4." /> + <Enum name="U1_DCD" start="0x3" description="Data Carrier Detect input for UART1." /> + </BitField> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor
 control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor
 enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin
 reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as
 1)." /> + </BitField> + <BitField start="7" size="2" name="RESERVED" description="Reserved." /> + <BitField start="9" size="1" name="SLEW" description="Driver slew rate"> + <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More
 outputs can be switched simultaneously." /> + <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the
 appropriate specific device data sheet for details." /> + </BitField> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain
 mode. Input cannot be pulled up above VDD." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x1D0" size="4" name="P3_20" access="Read/Write" description="I/O configuration register for pin P3[20]" reset_value="0x00000030" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P3[20]"> + <Enum name="P3_20" start="0x0" description="General purpose digital input/output pin." /> + <Enum name="EMC_D_20" start="0x1" description="External memory data line 20." /> + <Enum name="PWM0_5" start="0x2" description="Pulse Width Modulator 0, output 5." /> + <Enum name="U1_DSR" start="0x3" description="Data Set Ready input for UART1." /> + </BitField> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor
 control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor
 enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin
 reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as
 1)." /> + </BitField> + <BitField start="7" size="2" name="RESERVED" description="Reserved." /> + <BitField start="9" size="1" name="SLEW" description="Driver slew rate"> + <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More
 outputs can be switched simultaneously." /> + <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the
 appropriate specific device data sheet for details." /> + </BitField> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain
 mode. Input cannot be pulled up above VDD." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x1D4" size="4" name="P3_21" access="Read/Write" description="I/O configuration register for pin P3[21]" reset_value="0x00000030" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P3[21]"> + <Enum name="P3_21" start="0x0" description="General purpose digital input/output pin." /> + <Enum name="EMC_D_21" start="0x1" description="External memory data line 21." /> + <Enum name="PWM0_6" start="0x2" description="Pulse Width Modulator 0, output 6." /> + <Enum name="U1_DTR" start="0x3" description="Data Terminal Ready output for UART1. Can also be configured to be an RS-485/EIA-485 output enable signal for UART1." /> + </BitField> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor
 control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor
 enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin
 reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as
 1)." /> + </BitField> + <BitField start="7" size="2" name="RESERVED" description="Reserved." /> + <BitField start="9" size="1" name="SLEW" description="Driver slew rate"> + <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More
 outputs can be switched simultaneously." /> + <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the
 appropriate specific device data sheet for details." /> + </BitField> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain
 mode. Input cannot be pulled up above VDD." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x1D8" size="4" name="P3_22" access="Read/Write" description="I/O configuration register for pin P3[22]" reset_value="0x00000030" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P3[22]"> + <Enum name="P3_22" start="0x0" description="General purpose digital input/output pin." /> + <Enum name="EMC_D_22" start="0x1" description="External memory data line 22." /> + <Enum name="PWM0_CAP0" start="0x2" description="Capture input for PWM0, channel 0." /> + <Enum name="U1_RI" start="0x3" description="Ring Indicator input for UART1." /> + </BitField> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor
 control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor
 enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin
 reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as
 1)." /> + </BitField> + <BitField start="7" size="2" name="RESERVED" description="Reserved." /> + <BitField start="9" size="1" name="SLEW" description="Driver slew rate"> + <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More
 outputs can be switched simultaneously." /> + <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the
 appropriate specific device data sheet for details." /> + </BitField> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain
 mode. Input cannot be pulled up above VDD." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x1DC" size="4" name="P3_23" access="Read/Write" description="I/O configuration register for pin P3[23]" reset_value="0x00000030" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P3[23]"> + <Enum name="P3_23" start="0x0" description="General purpose digital input/output pin." /> + <Enum name="EMC_D_23" start="0x1" description="External memory data line 23." /> + <Enum name="PWM1_CAP0" start="0x2" description="Capture input for PWM1, channel 0." /> + <Enum name="T0_CAP0" start="0x3" description="Capture input for Timer 0, channel 0." /> + </BitField> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor
 control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor
 enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin
 reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as
 1)." /> + </BitField> + <BitField start="7" size="2" name="RESERVED" description="Reserved." /> + <BitField start="9" size="1" name="SLEW" description="Driver slew rate"> + <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More
 outputs can be switched simultaneously." /> + <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the
 appropriate specific device data sheet for details." /> + </BitField> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain
 mode. Input cannot be pulled up above VDD." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x1E0" size="4" name="P3_24" access="Read/Write" description="I/O configuration register for pin P3[24]" reset_value="0x00000030" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P3[24]"> + <Enum name="P3_24" start="0x0" description="General purpose digital input/output pin." /> + <Enum name="EMC_D_24" start="0x1" description="External memory data line 24." /> + <Enum name="PWM1_1" start="0x2" description="Pulse Width Modulator 1, output 1." /> + <Enum name="T0_CAP1" start="0x3" description="Capture input for Timer 0, channel 1." /> + </BitField> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor
 control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor
 enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin
 reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as
 1)." /> + </BitField> + <BitField start="7" size="2" name="RESERVED" description="Reserved." /> + <BitField start="9" size="1" name="SLEW" description="Driver slew rate"> + <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More
 outputs can be switched simultaneously." /> + <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the
 appropriate specific device data sheet for details." /> + </BitField> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain
 mode. Input cannot be pulled up above VDD." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x1E4" size="4" name="P3_25" access="Read/Write" description="I/O configuration register for pin P3[25]" reset_value="0x00000030" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P3[25]"> + <Enum name="P3_25" start="0x0" description="General purpose digital input/output pin." /> + <Enum name="EMC_D_25" start="0x1" description="External memory data line 25." /> + <Enum name="PWM1_2" start="0x2" description="Pulse Width Modulator 1, output 2." /> + <Enum name="T0_MAT0" start="0x3" description="Match output for Timer 0, channel 0." /> + </BitField> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor
 control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor
 enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin
 reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as
 1)." /> + </BitField> + <BitField start="7" size="2" name="RESERVED" description="Reserved." /> + <BitField start="9" size="1" name="SLEW" description="Driver slew rate"> + <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More
 outputs can be switched simultaneously." /> + <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the
 appropriate specific device data sheet for details." /> + </BitField> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain
 mode. Input cannot be pulled up above VDD." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x1E8" size="4" name="P3_26" access="Read/Write" description="I/O configuration register for pin P3[26]" reset_value="0x00000030" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P3[26]"> + <Enum name="P3_26" start="0x0" description="General purpose digital input/output pin." /> + <Enum name="EMC_D_26" start="0x1" description="External memory data line 26." /> + <Enum name="PWM1_3" start="0x2" description="Pulse Width Modulator 1, output 3." /> + <Enum name="T0_MAT1" start="0x3" description="Match output for Timer 0, channel 1." /> + <Enum name="STCLK" start="0x4" description="System tick timer clock input." /> + </BitField> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor
 control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor
 enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin
 reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as
 1)." /> + </BitField> + <BitField start="7" size="2" name="RESERVED" description="Reserved." /> + <BitField start="9" size="1" name="SLEW" description="Driver slew rate"> + <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More
 outputs can be switched simultaneously." /> + <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the
 appropriate specific device data sheet for details." /> + </BitField> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain
 mode. Input cannot be pulled up above VDD." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x1EC" size="4" name="P3_27" access="Read/Write" description="I/O configuration register for pin P3[27]" reset_value="0x00000030" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P3[27]"> + <Enum name="P3_27" start="0x0" description="General purpose digital input/output pin." /> + <Enum name="EMC_D_27" start="0x1" description="External memory data line 27." /> + <Enum name="PWM1_4" start="0x2" description="Pulse Width Modulator 1, output 4." /> + <Enum name="T1_CAP0" start="0x3" description="Capture input for Timer 1, channel 0." /> + </BitField> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor
 control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor
 enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin
 reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as
 1)." /> + </BitField> + <BitField start="7" size="2" name="RESERVED" description="Reserved." /> + <BitField start="9" size="1" name="SLEW" description="Driver slew rate"> + <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More
 outputs can be switched simultaneously." /> + <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the
 appropriate specific device data sheet for details." /> + </BitField> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain
 mode. Input cannot be pulled up above VDD." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x1F0" size="4" name="P3_28" access="Read/Write" description="I/O configuration register for pin P3[28]" reset_value="0x00000030" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P3[28]"> + <Enum name="P3_28" start="0x0" description="General purpose digital input/output pin." /> + <Enum name="EMC_D_28" start="0x1" description="External memory data line 28." /> + <Enum name="PWM1_5" start="0x2" description="Pulse Width Modulator 1, output 5." /> + <Enum name="T1_CAP1" start="0x3" description="Capture input for Timer 1, channel 1." /> + </BitField> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor
 control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor
 enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin
 reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as
 1)." /> + </BitField> + <BitField start="7" size="2" name="RESERVED" description="Reserved." /> + <BitField start="9" size="1" name="SLEW" description="Driver slew rate"> + <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More
 outputs can be switched simultaneously." /> + <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the
 appropriate specific device data sheet for details." /> + </BitField> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain
 mode. Input cannot be pulled up above VDD." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x1F4" size="4" name="P3_29" access="Read/Write" description="I/O configuration register for pin P3[29]" reset_value="0x00000030" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P3[29]"> + <Enum name="P3_29" start="0x0" description="General purpose digital input/output pin." /> + <Enum name="EMC_D_29" start="0x1" description="External memory data line 29." /> + <Enum name="PWM1_6" start="0x2" description="Pulse Width Modulator 1, output 6." /> + <Enum name="T1_MAT0" start="0x3" description="Match output for Timer 1, channel 0." /> + </BitField> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor
 control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor
 enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin
 reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as
 1)." /> + </BitField> + <BitField start="7" size="2" name="RESERVED" description="Reserved." /> + <BitField start="9" size="1" name="SLEW" description="Driver slew rate"> + <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More
 outputs can be switched simultaneously." /> + <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the
 appropriate specific device data sheet for details." /> + </BitField> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain
 mode. Input cannot be pulled up above VDD." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x1F8" size="4" name="P3_30" access="Read/Write" description="I/O configuration register for pin P3[30]" reset_value="0x00000030" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P3[30]"> + <Enum name="P3_30" start="0x0" description="General purpose digital input/output pin." /> + <Enum name="EMC_D_30" start="0x1" description="External memory data line 30." /> + <Enum name="U1_RTS" start="0x2" description="Request to Send output for UART1. Can also be configured to be an RS-485/EIA-485 output enable signal for UART1." /> + <Enum name="T1_MAT1" start="0x3" description="Match output for Timer 1, channel 1." /> + </BitField> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor
 control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor
 enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin
 reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as
 1)." /> + </BitField> + <BitField start="7" size="2" name="RESERVED" description="Reserved." /> + <BitField start="9" size="1" name="SLEW" description="Driver slew rate"> + <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More
 outputs can be switched simultaneously." /> + <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the
 appropriate specific device data sheet for details." /> + </BitField> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain
 mode. Input cannot be pulled up above VDD." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x1FC" size="4" name="P3_31" access="Read/Write" description="I/O configuration register for pin P3[31]" reset_value="0x00000030" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P3[31]"> + <Enum name="P3_31" start="0x0" description="General purpose digital input/output pin." /> + <Enum name="EMC_D_31" start="0x1" description="External memory data line 31." /> + <Enum name="T1_MAT2" start="0x3" description="Match output for Timer 1, channel 2." /> + </BitField> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor
 control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor
 enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin
 reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as
 1)." /> + </BitField> + <BitField start="7" size="2" name="RESERVED" description="Reserved." /> + <BitField start="9" size="1" name="SLEW" description="Driver slew rate"> + <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More
 outputs can be switched simultaneously." /> + <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the
 appropriate specific device data sheet for details." /> + </BitField> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain
 mode. Input cannot be pulled up above VDD." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x200" size="4" name="P4_0" access="Read/Write" description="I/O configuration register for pin P4[0]" reset_value="0x00000030" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P4[0]"> + <Enum name="P4_0" start="0x0" description="General purpose digital input/output pin." /> + <Enum name="EMC_A_0" start="0x1" description="External memory address line 0." /> + </BitField> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor
 control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor
 enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin
 reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as
 1)." /> + </BitField> + <BitField start="7" size="2" name="RESERVED" description="Reserved." /> + <BitField start="9" size="1" name="SLEW" description="Driver slew rate"> + <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More
 outputs can be switched simultaneously." /> + <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the
 appropriate specific device data sheet for details." /> + </BitField> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain
 mode. Input cannot be pulled up above VDD." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x204" size="4" name="P4_1" access="Read/Write" description="I/O configuration register for pin P4[1]" reset_value="0x00000030" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P4[1]"> + <Enum name="P4_1" start="0x0" description="General purpose digital input/output pin." /> + <Enum name="EMC_A_1" start="0x1" description="External memory address line 1." /> + </BitField> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor
 control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor
 enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin
 reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as
 1)." /> + </BitField> + <BitField start="7" size="2" name="RESERVED" description="Reserved." /> + <BitField start="9" size="1" name="SLEW" description="Driver slew rate"> + <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More
 outputs can be switched simultaneously." /> + <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the
 appropriate specific device data sheet for details." /> + </BitField> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain
 mode. Input cannot be pulled up above VDD." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x208" size="4" name="P4_2" access="Read/Write" description="I/O configuration register for pin P4[2]" reset_value="0x00000030" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P4[2]"> + <Enum name="P4_2" start="0x0" description="General purpose digital input/output pin." /> + <Enum name="EMC_A_2" start="0x1" description="External memory address line 2." /> + </BitField> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor
 control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor
 enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin
 reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as
 1)." /> + </BitField> + <BitField start="7" size="2" name="RESERVED" description="Reserved." /> + <BitField start="9" size="1" name="SLEW" description="Driver slew rate"> + <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More
 outputs can be switched simultaneously." /> + <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the
 appropriate specific device data sheet for details." /> + </BitField> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain
 mode. Input cannot be pulled up above VDD." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x20C" size="4" name="P4_3" access="Read/Write" description="I/O configuration register for pin P4[3]" reset_value="0x00000030" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P4[3]"> + <Enum name="P4_3" start="0x0" description="General purpose digital input/output pin." /> + <Enum name="EMC_A_3" start="0x1" description="External memory address line 3." /> + </BitField> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor
 control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor
 enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin
 reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as
 1)." /> + </BitField> + <BitField start="7" size="2" name="RESERVED" description="Reserved." /> + <BitField start="9" size="1" name="SLEW" description="Driver slew rate"> + <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More
 outputs can be switched simultaneously." /> + <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the
 appropriate specific device data sheet for details." /> + </BitField> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain
 mode. Input cannot be pulled up above VDD." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x210" size="4" name="P4_4" access="Read/Write" description="I/O configuration register for pin P4[4]" reset_value="0x00000030" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P4[4]"> + <Enum name="P4_4" start="0x0" description="General purpose digital input/output pin." /> + <Enum name="EMC_A_4" start="0x1" description="External memory address line 4." /> + </BitField> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor
 control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor
 enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin
 reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as
 1)." /> + </BitField> + <BitField start="7" size="2" name="RESERVED" description="Reserved." /> + <BitField start="9" size="1" name="SLEW" description="Driver slew rate"> + <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More
 outputs can be switched simultaneously." /> + <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the
 appropriate specific device data sheet for details." /> + </BitField> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain
 mode. Input cannot be pulled up above VDD." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x214" size="4" name="P4_5" access="Read/Write" description="I/O configuration register for pin P4[5]" reset_value="0x00000030" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P4[5]"> + <Enum name="P4_5" start="0x0" description="General purpose digital input/output pin." /> + <Enum name="EMC_A_5" start="0x1" description="External memory address line 5." /> + </BitField> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor
 control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor
 enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin
 reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as
 1)." /> + </BitField> + <BitField start="7" size="2" name="RESERVED" description="Reserved." /> + <BitField start="9" size="1" name="SLEW" description="Driver slew rate"> + <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More
 outputs can be switched simultaneously." /> + <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the
 appropriate specific device data sheet for details." /> + </BitField> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain
 mode. Input cannot be pulled up above VDD." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x218" size="4" name="P4_6" access="Read/Write" description="I/O configuration register for pin P4[6]" reset_value="0x00000030" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P4[6]"> + <Enum name="P4_6" start="0x0" description="General purpose digital input/output pin." /> + <Enum name="EMC_A_6" start="0x1" description="External memory address line 6." /> + </BitField> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor
 control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor
 enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin
 reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as
 1)." /> + </BitField> + <BitField start="7" size="2" name="RESERVED" description="Reserved." /> + <BitField start="9" size="1" name="SLEW" description="Driver slew rate"> + <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More
 outputs can be switched simultaneously." /> + <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the
 appropriate specific device data sheet for details." /> + </BitField> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain
 mode. Input cannot be pulled up above VDD." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x21C" size="4" name="P4_7" access="Read/Write" description="I/O configuration register for pin P4[7]" reset_value="0x00000030" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P4[7]"> + <Enum name="P4_7" start="0x0" description="General purpose digital input/output pin." /> + <Enum name="EMC_A_7" start="0x1" description="External memory address line 7." /> + </BitField> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor
 control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor
 enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin
 reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as
 1)." /> + </BitField> + <BitField start="7" size="2" name="RESERVED" description="Reserved." /> + <BitField start="9" size="1" name="SLEW" description="Driver slew rate"> + <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More
 outputs can be switched simultaneously." /> + <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the
 appropriate specific device data sheet for details." /> + </BitField> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain
 mode. Input cannot be pulled up above VDD." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x220" size="4" name="P4_8" access="Read/Write" description="I/O configuration register for pin P4[8]" reset_value="0x00000030" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P4[8]"> + <Enum name="P4_8" start="0x0" description="General purpose digital input/output pin." /> + <Enum name="EMC_A_8" start="0x1" description="External memory address line 8." /> + </BitField> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor
 control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor
 enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin
 reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as
 1)." /> + </BitField> + <BitField start="7" size="2" name="RESERVED" description="Reserved." /> + <BitField start="9" size="1" name="SLEW" description="Driver slew rate"> + <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More
 outputs can be switched simultaneously." /> + <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the
 appropriate specific device data sheet for details." /> + </BitField> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain
 mode. Input cannot be pulled up above VDD." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x224" size="4" name="P4_9" access="Read/Write" description="I/O configuration register for pin P4[9]" reset_value="0x00000030" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P4[9]"> + <Enum name="P4_9" start="0x0" description="General purpose digital input/output pin." /> + <Enum name="EMC_A_9" start="0x1" description="External memory address line 9." /> + </BitField> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor
 control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor
 enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin
 reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as
 1)." /> + </BitField> + <BitField start="7" size="2" name="RESERVED" description="Reserved." /> + <BitField start="9" size="1" name="SLEW" description="Driver slew rate"> + <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More
 outputs can be switched simultaneously." /> + <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the
 appropriate specific device data sheet for details." /> + </BitField> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain
 mode. Input cannot be pulled up above VDD." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x228" size="4" name="P4_10" access="Read/Write" description="I/O configuration register for pin P4[10]" reset_value="0x00000030" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P4[10]"> + <Enum name="P4_10" start="0x0" description="General purpose digital input/output pin." /> + <Enum name="EMC_A_10" start="0x1" description="External memory address line 10." /> + </BitField> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor
 control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor
 enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin
 reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as
 1)." /> + </BitField> + <BitField start="7" size="2" name="RESERVED" description="Reserved." /> + <BitField start="9" size="1" name="SLEW" description="Driver slew rate"> + <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More
 outputs can be switched simultaneously." /> + <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the
 appropriate specific device data sheet for details." /> + </BitField> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain
 mode. Input cannot be pulled up above VDD." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x22C" size="4" name="P4_11" access="Read/Write" description="I/O configuration register for pin P4[11]" reset_value="0x00000030" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P4[11]"> + <Enum name="P4_11" start="0x0" description="General purpose digital input/output pin." /> + <Enum name="EMC_A_11" start="0x1" description="External memory address line 11." /> + </BitField> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor
 control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor
 enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin
 reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as
 1)." /> + </BitField> + <BitField start="7" size="2" name="RESERVED" description="Reserved." /> + <BitField start="9" size="1" name="SLEW" description="Driver slew rate"> + <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More
 outputs can be switched simultaneously." /> + <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the
 appropriate specific device data sheet for details." /> + </BitField> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain
 mode. Input cannot be pulled up above VDD." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x230" size="4" name="P4_12" access="Read/Write" description="I/O configuration register for pin P4[12]" reset_value="0x00000030" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P4[12]"> + <Enum name="P4_12" start="0x0" description="General purpose digital input/output pin." /> + <Enum name="EMC_A_12" start="0x1" description="External memory address line 12." /> + </BitField> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor
 control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor
 enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin
 reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as
 1)." /> + </BitField> + <BitField start="7" size="2" name="RESERVED" description="Reserved." /> + <BitField start="9" size="1" name="SLEW" description="Driver slew rate"> + <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More
 outputs can be switched simultaneously." /> + <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the
 appropriate specific device data sheet for details." /> + </BitField> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain
 mode. Input cannot be pulled up above VDD." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x234" size="4" name="P4_13" access="Read/Write" description="I/O configuration register for pin P4[13]" reset_value="0x00000030" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P4[13]"> + <Enum name="P4_13" start="0x0" description="General purpose digital input/output pin." /> + <Enum name="EMC_A_13" start="0x1" description="External memory address line 13." /> + </BitField> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor
 control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor
 enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin
 reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as
 1)." /> + </BitField> + <BitField start="7" size="2" name="RESERVED" description="Reserved." /> + <BitField start="9" size="1" name="SLEW" description="Driver slew rate"> + <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More
 outputs can be switched simultaneously." /> + <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the
 appropriate specific device data sheet for details." /> + </BitField> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain
 mode. Input cannot be pulled up above VDD." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x238" size="4" name="P4_14" access="Read/Write" description="I/O configuration register for pin P4[14]" reset_value="0x00000030" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P4[14]"> + <Enum name="P4_14" start="0x0" description="General purpose digital input/output pin." /> + <Enum name="EMC_A_14" start="0x1" description="External memory address line 14." /> + </BitField> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor
 control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor
 enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin
 reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as
 1)." /> + </BitField> + <BitField start="7" size="2" name="RESERVED" description="Reserved." /> + <BitField start="9" size="1" name="SLEW" description="Driver slew rate"> + <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More
 outputs can be switched simultaneously." /> + <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the
 appropriate specific device data sheet for details." /> + </BitField> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain
 mode. Input cannot be pulled up above VDD." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x23C" size="4" name="P4_15" access="Read/Write" description="I/O configuration register for pin P4[15]" reset_value="0x00000030" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P4[15]"> + <Enum name="P4_15" start="0x0" description="General purpose digital input/output pin." /> + <Enum name="EMC_A_15" start="0x1" description="External memory address line 15." /> + </BitField> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor
 control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor
 enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin
 reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as
 1)." /> + </BitField> + <BitField start="7" size="2" name="RESERVED" description="Reserved." /> + <BitField start="9" size="1" name="SLEW" description="Driver slew rate"> + <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More
 outputs can be switched simultaneously." /> + <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the
 appropriate specific device data sheet for details." /> + </BitField> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain
 mode. Input cannot be pulled up above VDD." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x240" size="4" name="P4_16" access="Read/Write" description="I/O configuration register for pin P4[16]" reset_value="0x00000030" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P4[16]"> + <Enum name="P4_16" start="0x0" description="General purpose digital input/output pin." /> + <Enum name="EMC_A_16" start="0x1" description="External memory address line 16." /> + </BitField> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor
 control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor
 enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin
 reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as
 1)." /> + </BitField> + <BitField start="7" size="2" name="RESERVED" description="Reserved." /> + <BitField start="9" size="1" name="SLEW" description="Driver slew rate"> + <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More
 outputs can be switched simultaneously." /> + <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the
 appropriate specific device data sheet for details." /> + </BitField> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain
 mode. Input cannot be pulled up above VDD." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x244" size="4" name="P4_17" access="Read/Write" description="I/O configuration register for pin P4[17]" reset_value="0x00000030" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P4[17]"> + <Enum name="P4_17" start="0x0" description="General purpose digital input/output pin." /> + <Enum name="EMC_A_17" start="0x1" description="External memory address line 17." /> + </BitField> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor
 control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor
 enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin
 reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as
 1)." /> + </BitField> + <BitField start="7" size="2" name="RESERVED" description="Reserved." /> + <BitField start="9" size="1" name="SLEW" description="Driver slew rate"> + <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More
 outputs can be switched simultaneously." /> + <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the
 appropriate specific device data sheet for details." /> + </BitField> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain
 mode. Input cannot be pulled up above VDD." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x248" size="4" name="P4_18" access="Read/Write" description="I/O configuration register for pin P4[18]" reset_value="0x00000030" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P4[18]"> + <Enum name="P4_18" start="0x0" description="General purpose digital input/output pin." /> + <Enum name="EMC_A_18" start="0x1" description="External memory address line 18." /> + </BitField> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor
 control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor
 enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin
 reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as
 1)." /> + </BitField> + <BitField start="7" size="2" name="RESERVED" description="Reserved." /> + <BitField start="9" size="1" name="SLEW" description="Driver slew rate"> + <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More
 outputs can be switched simultaneously." /> + <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the
 appropriate specific device data sheet for details." /> + </BitField> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain
 mode. Input cannot be pulled up above VDD." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x24C" size="4" name="P4_19" access="Read/Write" description="I/O configuration register for pin P4[19]" reset_value="0x00000030" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P4[19]"> + <Enum name="P4_19" start="0x0" description="General purpose digital input/output pin." /> + <Enum name="EMC_A_19" start="0x1" description="External memory address line 19." /> + </BitField> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor
 control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor
 enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin
 reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as
 1)." /> + </BitField> + <BitField start="7" size="2" name="RESERVED" description="Reserved." /> + <BitField start="9" size="1" name="SLEW" description="Driver slew rate"> + <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More
 outputs can be switched simultaneously." /> + <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the
 appropriate specific device data sheet for details." /> + </BitField> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain
 mode. Input cannot be pulled up above VDD." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x250" size="4" name="P4_20" access="Read/Write" description="I/O configuration register for pin P4[20]" reset_value="0x00000030" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P4[20]"> + <Enum name="P4_20" start="0x0" description="General purpose digital input/output pin." /> + <Enum name="EMC_A_20" start="0x1" description="External memory address line 20." /> + <Enum name="I2C2_SDA" start="0x2" description="I2C2 data input/output (this pin does not use a specialized I2C pad)." /> + <Enum name="SSP1_SCK" start="0x3" description="Serial Clock for SSP1." /> + </BitField> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor
 control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor
 enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin
 reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as
 1)." /> + </BitField> + <BitField start="7" size="2" name="RESERVED" description="Reserved." /> + <BitField start="9" size="1" name="SLEW" description="Driver slew rate"> + <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More
 outputs can be switched simultaneously." /> + <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the
 appropriate specific device data sheet for details." /> + </BitField> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain
 mode. Input cannot be pulled up above VDD." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x254" size="4" name="P4_21" access="Read/Write" description="I/O configuration register for pin P4[21]" reset_value="0x00000030" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P4[21]"> + <Enum name="P4_21" start="0x0" description="General purpose digital input/output pin." /> + <Enum name="EMC_A_21" start="0x1" description="External memory address line 21." /> + <Enum name="I2C2_SCL" start="0x2" description="I2C2 clock input/output (this pin does not use a specialized I2C pad)." /> + <Enum name="SSP1_SSEL" start="0x3" description="Slave Select for SSP1." /> + </BitField> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor
 control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor
 enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin
 reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as
 1)." /> + </BitField> + <BitField start="7" size="2" name="RESERVED" description="Reserved." /> + <BitField start="9" size="1" name="SLEW" description="Driver slew rate"> + <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More
 outputs can be switched simultaneously." /> + <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the
 appropriate specific device data sheet for details." /> + </BitField> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain
 mode. Input cannot be pulled up above VDD." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x258" size="4" name="P4_22" access="Read/Write" description="I/O configuration register for pin P4[22]" reset_value="0x00000030" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P4[22]"> + <Enum name="P4_22" start="0x0" description="General purpose digital input/output pin." /> + <Enum name="EMC_A_22" start="0x1" description="External memory address line 22." /> + <Enum name="U2_TXD" start="0x2" description="Transmitter output for UART2." /> + <Enum name="SSP1_MISO" start="0x3" description="Master In Slave Out for SSP1." /> + </BitField> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor
 control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor
 enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin
 reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as
 1)." /> + </BitField> + <BitField start="7" size="2" name="RESERVED" description="Reserved." /> + <BitField start="9" size="1" name="SLEW" description="Driver slew rate"> + <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More
 outputs can be switched simultaneously." /> + <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the
 appropriate specific device data sheet for details." /> + </BitField> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain
 mode. Input cannot be pulled up above VDD." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x25C" size="4" name="P4_23" access="Read/Write" description="I/O configuration register for pin P4[23]" reset_value="0x00000030" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P4[23]"> + <Enum name="P4_23" start="0x0" description="General purpose digital input/output pin." /> + <Enum name="EMC_A_23" start="0x1" description="External memory address line 23." /> + <Enum name="U2_RXD" start="0x2" description="Receiver input for UART2." /> + <Enum name="SSP1_MOSI" start="0x3" description="Master Out Slave In for SSP1." /> + </BitField> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor
 control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor
 enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin
 reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as
 1)." /> + </BitField> + <BitField start="7" size="2" name="RESERVED" description="Reserved." /> + <BitField start="9" size="1" name="SLEW" description="Driver slew rate"> + <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More
 outputs can be switched simultaneously." /> + <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the
 appropriate specific device data sheet for details." /> + </BitField> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain
 mode. Input cannot be pulled up above VDD." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x260" size="4" name="P4_24" access="Read/Write" description="I/O configuration register for pin P4[24]" reset_value="0x00000030" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P4[24]"> + <Enum name="P4_24" start="0x0" description="General purpose digital input/output pin." /> + <Enum name="EMC_OE" start="0x1" description="LOW active Output Enable signal." /> + </BitField> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor
 control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor
 enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin
 reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as
 1)." /> + </BitField> + <BitField start="7" size="2" name="RESERVED" description="Reserved." /> + <BitField start="9" size="1" name="SLEW" description="Driver slew rate"> + <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More
 outputs can be switched simultaneously." /> + <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the
 appropriate specific device data sheet for details." /> + </BitField> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain
 mode. Input cannot be pulled up above VDD." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x264" size="4" name="P4_25" access="Read/Write" description="I/O configuration register for pin P4[25]" reset_value="0x00000030" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P4[25]"> + <Enum name="P4_25" start="0x0" description="General purpose digital input/output pin." /> + <Enum name="EMC_WE" start="0x1" description="LOW active Write Enable signal." /> + </BitField> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor
 control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor
 enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin
 reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as
 1)." /> + </BitField> + <BitField start="7" size="2" name="RESERVED" description="Reserved." /> + <BitField start="9" size="1" name="SLEW" description="Driver slew rate"> + <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More
 outputs can be switched simultaneously." /> + <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the
 appropriate specific device data sheet for details." /> + </BitField> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain
 mode. Input cannot be pulled up above VDD." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x268" size="4" name="P4_26" access="Read/Write" description="I/O configuration register for pin P4[26]" reset_value="0x00000030" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P4[26]"> + <Enum name="P4_26" start="0x0" description="General purpose digital input/output pin." /> + <Enum name="EMC_BLS0" start="0x1" description="LOW active Byte Lane select signal 0." /> + </BitField> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor
 control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor
 enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin
 reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as
 1)." /> + </BitField> + <BitField start="7" size="2" name="RESERVED" description="Reserved." /> + <BitField start="9" size="1" name="SLEW" description="Driver slew rate"> + <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More
 outputs can be switched simultaneously." /> + <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the
 appropriate specific device data sheet for details." /> + </BitField> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain
 mode. Input cannot be pulled up above VDD." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x26C" size="4" name="P4_27" access="Read/Write" description="I/O configuration register for pin P4[27]" reset_value="0x00000030" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P4[27]"> + <Enum name="P4_27" start="0x0" description="General purpose digital input/output pin." /> + <Enum name="EMC_BLS1" start="0x1" description="LOW active Byte Lane select signal 1." /> + </BitField> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor
 control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor
 enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin
 reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as
 1)." /> + </BitField> + <BitField start="7" size="2" name="RESERVED" description="Reserved." /> + <BitField start="9" size="1" name="SLEW" description="Driver slew rate"> + <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More
 outputs can be switched simultaneously." /> + <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the
 appropriate specific device data sheet for details." /> + </BitField> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain
 mode. Input cannot be pulled up above VDD." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x270" size="4" name="P4_28" access="Read/Write" description="I/O configuration register for pin P4[28]" reset_value="0x00000030" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P4[28]"> + <Enum name="P4_28" start="0x0" description="General purpose digital input/output pin." /> + <Enum name="EMC_BLS2" start="0x1" description="LOW active Byte Lane select signal 2." /> + <Enum name="U3_TXD" start="0x2" description="Transmitter output for UART3." /> + <Enum name="T2_MAT0" start="0x3" description="Match output for Timer 2, channel 0." /> + <Enum name="LCD_VD_6" start="0x5" description="LCD data." /> + <Enum name="LCD_VD_10" start="0x6" description="LCD data." /> + <Enum name="LCD_VD_2" start="0x7" description="LCD data." /> + </BitField> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor
 control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor
 enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin
 reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as
 1)." /> + </BitField> + <BitField start="7" size="2" name="RESERVED" description="Reserved." /> + <BitField start="9" size="1" name="SLEW" description="Driver slew rate"> + <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More
 outputs can be switched simultaneously." /> + <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the
 appropriate specific device data sheet for details." /> + </BitField> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain
 mode. Input cannot be pulled up above VDD." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x274" size="4" name="P4_29" access="Read/Write" description="I/O configuration register for pin P4[29]" reset_value="0x00000030" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P4[29]"> + <Enum name="P4_29" start="0x0" description="General purpose digital input/output pin." /> + <Enum name="EMC_BLS3" start="0x1" description="LOW active Byte Lane select signal 3." /> + <Enum name="U3_RXD" start="0x2" description="Receiver input for UART3." /> + <Enum name="T2_MAT1" start="0x3" description="Match output for Timer 2, channel 1." /> + <Enum name="I2C2_SCL" start="0x4" description="I2C2 clock input/output (this pin does not use a specialized I2C pad)." /> + <Enum name="LCD_VD_7" start="0x5" description="LCD data." /> + <Enum name="LCD_VD_11" start="0x6" description="LCD data." /> + <Enum name="LCD_VD_3" start="0x7" description="LCD data." /> + </BitField> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor
 control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor
 enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin
 reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as
 1)." /> + </BitField> + <BitField start="7" size="2" name="RESERVED" description="Reserved." /> + <BitField start="9" size="1" name="SLEW" description="Driver slew rate"> + <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More
 outputs can be switched simultaneously." /> + <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the
 appropriate specific device data sheet for details." /> + </BitField> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain
 mode. Input cannot be pulled up above VDD." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x278" size="4" name="P4_30" access="Read/Write" description="I/O configuration register for pin P4[30]" reset_value="0x00000030" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P4[30]"> + <Enum name="P4_30" start="0x0" description="General purpose digital input/output pin." /> + <Enum name="EMC_CS0" start="0x1" description="LOW active Chip Select 0 signal." /> + <Enum name="CMP0_OUT" start="0x5" description="Comparator 0, output." /> + </BitField> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor
 control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor
 enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin
 reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as
 1)." /> + </BitField> + <BitField start="7" size="2" name="RESERVED" description="Reserved." /> + <BitField start="9" size="1" name="SLEW" description="Driver slew rate"> + <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More
 outputs can be switched simultaneously." /> + <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the
 appropriate specific device data sheet for details." /> + </BitField> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain
 mode. Input cannot be pulled up above VDD." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x27C" size="4" name="P4_31" access="Read/Write" description="I/O configuration register for pin P4[31]" reset_value="0x00000030" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P4[31]"> + <Enum name="P4_31" start="0x0" description="General purpose digital input/output pin." /> + <Enum name="EMC_CS1" start="0x1" description="LOW active Chip Select 1 signal." /> + </BitField> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor
 control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor
 enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin
 reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as
 1)." /> + </BitField> + <BitField start="7" size="2" name="RESERVED" description="Reserved." /> + <BitField start="9" size="1" name="SLEW" description="Driver slew rate"> + <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More
 outputs can be switched simultaneously." /> + <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the
 appropriate specific device data sheet for details." /> + </BitField> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain
 mode. Input cannot be pulled up above VDD." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x280" size="4" name="P5_0" access="Read/Write" description="I/O configuration register for pin P5[0]" reset_value="0x00000030" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P5[0]"> + <Enum name="P5_0" start="0x0" description="General purpose digital input/output pin." /> + <Enum name="EMC_A_24" start="0x1" description="External memory address line 24." /> + <Enum name="SSP2_MOSI" start="0x2" description="Master Out Slave In for SSP2." /> + <Enum name="T2_MAT2" start="0x3" description="Match output for Timer 2, channel 2." /> + </BitField> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor
 control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor
 enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin
 reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as
 1)." /> + </BitField> + <BitField start="7" size="2" name="RESERVED" description="Reserved." /> + <BitField start="9" size="1" name="SLEW" description="Driver slew rate"> + <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More
 outputs can be switched simultaneously." /> + <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the
 appropriate specific device data sheet for details." /> + </BitField> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain
 mode. Input cannot be pulled up above VDD." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x284" size="4" name="P5_1" access="Read/Write" description="I/O configuration register for pin P5[1]" reset_value="0x00000030" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P5[1]"> + <Enum name="P5_1" start="0x0" description="General purpose digital input/output pin." /> + <Enum name="EMC_A_25" start="0x1" description="External memory address line 25." /> + <Enum name="SSP2_MISO" start="0x2" description="Master In Slave Out for SSP2." /> + <Enum name="T2_MAT3" start="0x3" description="Match output for Timer 2, channel 3." /> + </BitField> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor
 control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor
 enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin
 reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as
 1)." /> + </BitField> + <BitField start="7" size="2" name="RESERVED" description="Reserved." /> + <BitField start="9" size="1" name="SLEW" description="Driver slew rate"> + <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More
 outputs can be switched simultaneously." /> + <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the
 appropriate specific device data sheet for details." /> + </BitField> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain
 mode. Input cannot be pulled up above VDD." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x288" size="4" name="P5_2" access="Read/Write" description="I/O configuration register for pin P5[2]" reset_value="0x00000080" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P5[2]"> + <Enum name="P5_2" start="0x0" description="General purpose digital input/output pin." /> + <Enum name="T3_MAT2" start="0x3" description="Match output for Timer 3, channel 2." /> + <Enum name="I2C0_SDA" start="0x5" description="I2C0 data input/output (this pin uses a specialized I2C pad that supports I2C Fast Mode Plus)." /> + </BitField> + <BitField start="3" size="3" name="RESERVED" description="Reserved." /> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin
 reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as
 1)." /> + </BitField> + <BitField start="7" size="1" name="RESERVED" description="Reserved." /> + <BitField start="8" size="1" name="HS" description="Configures I2C features for standard mode, fast mode, and Fast Mode
 Plus operation."> + <Enum name="ENABLED" start="0" description="I2C 50ns glitch filter and slew rate control
 enabled." /> + <Enum name="DISABLED" start="1" description="I2C 50ns glitch filter and slew rate control
 disabled." /> + </BitField> + <BitField start="9" size="1" name="HIDRIVE" description="Controls sink current capability of the pin, only for P5[2] and
 P5[3]."> + <Enum name="LOWDRIVE" start="0" description="Output drive sink is 4 mA. This is sufficient for standard
 and fast mode I2C." /> + <Enum name="HIGHDRIVE" start="1" description="Output drive sink is 20 mA. This is needed for Fast Mode
 Plus I2C. Refer to the appropriate specific device data sheet for
 details." /> + </BitField> + <BitField start="10" size="22" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x28C" size="4" name="P5_3" access="Read/Write" description="I/O configuration register for pin P5[3]" reset_value="0x00000080" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P5[3]"> + <Enum name="P5_3" start="0x0" description="General purpose digital input/output pin." /> + <Enum name="U4_RXD" start="0x4" description="Receiver input for USART4." /> + <Enum name="I2C0_SCL" start="0x5" description="I2C0 clock input/output (this pin uses a specialized I2C pad that supports I2C Fast Mode Plus." /> + </BitField> + <BitField start="3" size="3" name="RESERVED" description="Reserved." /> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin
 reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as
 1)." /> + </BitField> + <BitField start="7" size="1" name="RESERVED" description="Reserved." /> + <BitField start="8" size="1" name="HS" description="Configures I2C features for standard mode, fast mode, and Fast Mode
 Plus operation."> + <Enum name="ENABLED" start="0" description="I2C 50ns glitch filter and slew rate control
 enabled." /> + <Enum name="DISABLED" start="1" description="I2C 50ns glitch filter and slew rate control
 disabled." /> + </BitField> + <BitField start="9" size="1" name="HIDRIVE" description="Controls sink current capability of the pin, only for P5[2] and
 P5[3]."> + <Enum name="LOWDRIVE" start="0" description="Output drive sink is 4 mA. This is sufficient for standard
 and fast mode I2C." /> + <Enum name="HIGHDRIVE" start="1" description="Output drive sink is 20 mA. This is needed for Fast Mode
 Plus I2C. Refer to the appropriate specific device data sheet for
 details." /> + </BitField> + <BitField start="10" size="22" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x290" size="4" name="P5_4" access="Read/Write" description="I/O configuration register for pin P5[4]" reset_value="0x00000030" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P5[4]"> + <Enum name="P5_4" start="0x0" description="General purpose digital input/output pin." /> + <Enum name="U0_OE" start="0x1" description="RS-485/EIA-485 output enable signal for UART0." /> + <Enum name="T3_MAT3" start="0x3" description="Match output for Timer 3, channel 3." /> + <Enum name="U4_TXD" start="0x4" description="Transmitter output for USART4 (input/output in smart card mode)." /> + </BitField> + <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor
 control)."> + <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor
 enabled)." /> + <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." /> + <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." /> + <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." /> + </BitField> + <BitField start="5" size="1" name="HYS" description="Hysteresis."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="ENABLE_" start="1" description="Enable." /> + </BitField> + <BitField start="6" size="1" name="INV" description="Invert input"> + <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin
 reads as 0)." /> + <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as
 1)." /> + </BitField> + <BitField start="7" size="2" name="RESERVED" description="Reserved." /> + <BitField start="9" size="1" name="SLEW" description="Driver slew rate"> + <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More
 outputs can be switched simultaneously." /> + <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the
 appropriate specific device data sheet for details." /> + </BitField> + <BitField start="10" size="1" name="OD" description="Open-drain mode."> + <Enum name="DISABLE_" start="0" description="Disable." /> + <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain
 mode. Input cannot be pulled up above VDD." /> + </BitField> + <BitField start="11" size="21" name="RESERVED" description="Reserved." /> + </Register> + </RegisterGroup> + <RegisterGroup name="SSP1" start="0x40030000" description="SSP1 controller"> + <Register start="+0x000" size="4" name="CR0" access="Read/Write" description="Control Register 0. Selects the serial clock rate, bus type, and data size." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="4" name="DSS" description="Data Size Select. This field controls the number of bits transferred in each frame. Values 0000-0010 are not supported and should not be used."> + <Enum name="4_BIT_TRANSFER" start="0x3" description="4-bit transfer" /> + <Enum name="5_BIT_TRANSFER" start="0x4" description="5-bit transfer" /> + <Enum name="6_BIT_TRANSFER" start="0x5" description="6-bit transfer" /> + <Enum name="7_BIT_TRANSFER" start="0x6" description="7-bit transfer" /> + <Enum name="8_BIT_TRANSFER" start="0x7" description="8-bit transfer" /> + <Enum name="9_BIT_TRANSFER" start="0x8" description="9-bit transfer" /> + <Enum name="10_BIT_TRANSFER" start="0x9" description="10-bit transfer" /> + <Enum name="11_BIT_TRANSFER" start="0xA" description="11-bit transfer" /> + <Enum name="12_BIT_TRANSFER" start="0xB" description="12-bit transfer" /> + <Enum name="13_BIT_TRANSFER" start="0xC" description="13-bit transfer" /> + <Enum name="14_BIT_TRANSFER" start="0xD" description="14-bit transfer" /> + <Enum name="15_BIT_TRANSFER" start="0xE" description="15-bit transfer" /> + <Enum name="16_BIT_TRANSFER" start="0xF" description="16-bit transfer" /> + </BitField> + <BitField start="4" size="2" name="FRF" description="Frame Format."> + <Enum name="SPI" start="0x0" description="SPI" /> + <Enum name="TI" start="0x1" description="TI" /> + <Enum name="MICROWIRE" start="0x2" description="Microwire" /> + <Enum name="THIS_COMBINATION_IS_" start="0x3" description="This combination is not supported and should not be used." /> + </BitField> + <BitField start="6" size="1" name="CPOL" description="Clock Out Polarity. This bit is only used in SPI mode."> + <Enum name="BUS_LOW" start="0" description="SSP controller maintains the bus clock low between frames." /> + <Enum name="BUS_HIGH" start="1" description="SSP controller maintains the bus clock high between frames." /> + </BitField> + <BitField start="7" size="1" name="CPHA" description="Clock Out Phase. This bit is only used in SPI mode."> + <Enum name="FIRST_CLOCK" start="0" description="SSP controller captures serial data on the first clock transition of the frame, that is, the transition away from the inter-frame state of the clock line." /> + <Enum name="SECOND_CLOCK" start="1" description="SSP controller captures serial data on the second clock transition of the frame, that is, the transition back to the inter-frame state of the clock line." /> + </BitField> + <BitField start="8" size="8" name="SCR" description="Serial Clock Rate. The number of prescaler-output clocks per bit on the bus, minus one. Given that CPSDVSR is the prescale divider, and the APB clock PCLK clocks the prescaler, the bit frequency is PCLK / (CPSDVSR X [SCR+1])." /> + <BitField start="16" size="16" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x004" size="4" name="CR1" access="Read/Write" description="Control Register 1. Selects master/slave and other modes." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="LBM" description="Loop Back Mode."> + <Enum name="NORMAL" start="0" description="During normal operation." /> + <Enum name="OUPTU" start="1" description="Serial input is taken from the serial output (MOSI or MISO) rather than the serial input pin (MISO or MOSI respectively)." /> + </BitField> + <BitField start="1" size="1" name="SSE" description="SSP Enable."> + <Enum name="DISABLED" start="0" description="The SSP controller is disabled." /> + <Enum name="ENABLED" start="1" description="The SSP controller will interact with other devices on the serial bus. Software should write the appropriate control information to the other SSP registers and interrupt controller registers, before setting this bit." /> + </BitField> + <BitField start="2" size="1" name="MS" description="Master/Slave Mode.This bit can only be written when the SSE bit is 0."> + <Enum name="MASTER" start="0" description="The SSP controller acts as a master on the bus, driving the SCLK, MOSI, and SSEL lines and receiving the MISO line." /> + <Enum name="SLAVE" start="1" description="The SSP controller acts as a slave on the bus, driving MISO line and receiving SCLK, MOSI, and SSEL lines." /> + </BitField> + <BitField start="3" size="1" name="SOD" description="Slave Output Disable. This bit is relevant only in slave mode (MS = 1). If it is 1, this blocks this SSP controller from driving the transmit data line (MISO)." /> + <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x008" size="4" name="DR" access="None" description="Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="16" name="DATA" description="Write: software can write data to be sent in a future frame to this register whenever the TNF bit in the Status register is 1, indicating that the Tx FIFO is not full. If the Tx FIFO was previously empty and the SSP controller is not busy on the bus, transmission of the data will begin immediately. Otherwise the data written to this register will be sent as soon as all previous data has been sent (and received). If the data length is less than 16 bits, software must right-justify the data written to this register. Read: software can read data from this register whenever the RNE bit in the Status register is 1, indicating that the Rx FIFO is not empty. When software reads this register, the SSP controller returns data from the least recent frame in the Rx FIFO. If the data length is less than 16 bits, the data is right-justified in this field with higher order bits filled with 0s." /> + <BitField start="16" size="16" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x00C" size="4" name="SR" access="ReadOnly" description="Status Register" reset_value="0x00000003" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="TFE" description="Transmit FIFO Empty. This bit is 1 is the Transmit FIFO is empty, 0 if not." /> + <BitField start="1" size="1" name="TNF" description="Transmit FIFO Not Full. This bit is 0 if the Tx FIFO is full, 1 if not." /> + <BitField start="2" size="1" name="RNE" description="Receive FIFO Not Empty. This bit is 0 if the Receive FIFO is empty, 1 if not." /> + <BitField start="3" size="1" name="RFF" description="Receive FIFO Full. This bit is 1 if the Receive FIFO is full, 0 if not." /> + <BitField start="4" size="1" name="BSY" description="Busy. This bit is 0 if the SSPn controller is idle, or 1 if it is currently sending/receiving a frame and/or the Tx FIFO is not empty." /> + <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x010" size="4" name="CPSR" access="Read/Write" description="Clock Prescale Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="CPSDVSR" description="This even value between 2 and 254, by which PCLK is divided to yield the prescaler output clock. Bit 0 always reads as 0." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x014" size="4" name="IMSC" access="Read/Write" description="Interrupt Mask Set and Clear Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RORIM" description="Software should set this bit to enable interrupt when a Receive Overrun occurs, that is, when the Rx FIFO is full and another frame is completely received. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs." /> + <BitField start="1" size="1" name="RTIM" description="Software should set this bit to enable interrupt when a Receive Time-out condition occurs. A Receive Time-out occurs when the Rx FIFO is not empty, and no has not been read for a time-out period. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1])." /> + <BitField start="2" size="1" name="RXIM" description="Software should set this bit to enable interrupt when the Rx FIFO is at least half full." /> + <BitField start="3" size="1" name="TXIM" description="Software should set this bit to enable interrupt when the Tx FIFO is at least half empty." /> + <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x018" size="4" name="RIS" access="ReadOnly" description="Raw Interrupt Status Register" reset_value="0x00000008" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RORRIS" description="This bit is 1 if another frame was completely received while the RxFIFO was full. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs." /> + <BitField start="1" size="1" name="RTRIS" description="This bit is 1 if the Rx FIFO is not empty, and has not been read for a time-out period. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1])." /> + <BitField start="2" size="1" name="RXRIS" description="This bit is 1 if the Rx FIFO is at least half full." /> + <BitField start="3" size="1" name="TXRIS" description="This bit is 1 if the Tx FIFO is at least half empty." /> + <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x01C" size="4" name="MIS" access="ReadOnly" description="Masked Interrupt Status Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RORMIS" description="This bit is 1 if another frame was completely received while the RxFIFO was full, and this interrupt is enabled." /> + <BitField start="1" size="1" name="RTMIS" description="This bit is 1 if the Rx FIFO is not empty, has not been read for a time-out period, and this interrupt is enabled. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1])." /> + <BitField start="2" size="1" name="RXMIS" description="This bit is 1 if the Rx FIFO is at least half full, and this interrupt is enabled." /> + <BitField start="3" size="1" name="TXMIS" description="This bit is 1 if the Tx FIFO is at least half empty, and this interrupt is enabled." /> + <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x020" size="4" name="ICR" access="WriteOnly" description="SSPICR Interrupt Clear Register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="RORIC" description="Writing a 1 to this bit clears the frame was received when RxFIFO was full interrupt." /> + <BitField start="1" size="1" name="RTIC" description="Writing a 1 to this bit clears the Rx FIFO was not empty and has not been read for a time-out period interrupt. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR / [SCR+1])." /> + <BitField start="2" size="30" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x024" size="4" name="DMACR" access="Read/Write" description="SSP0 DMA control register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RXDMAE" description="Receive DMA Enable. When this bit is set to one 1, DMA for the receive FIFO is enabled, otherwise receive DMA is disabled." /> + <BitField start="1" size="1" name="TXDMAE" description="Transmit DMA Enable. When this bit is set to one 1, DMA for the transmit FIFO is enabled, otherwise transmit DMA is disabled" /> + <BitField start="2" size="30" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + </RegisterGroup> + <RegisterGroup name="ADC" start="0x40034000" description="Analog-to-Digital Converter (ADC)"> + <Register start="+0x000" size="4" name="CR" access="Read/Write" description="A/D Control Register. The ADCR register must be written to select the operating mode before A/D conversion can occur." reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="8" name="SEL" description="Selects which of the AD0[7:0] pins is (are) to be sampled and converted. For AD0, bit 0 selects Pin AD0[0], and bit 7 selects pin AD0[7]. In software-controlled mode, only one of these bits should be 1. In hardware scan mode, any value containing 1 to 8 ones is allowed. All zeroes is equivalent to 0x01." /> + <BitField start="8" size="8" name="CLKDIV" description="The APB clock (PCLK) is divided by (this value plus one) to produce the clock for the A/D converter, which should be less than or equal to 12.4 MHz. Typically, software should program the smallest value in this field that yields a clock of 12.4 MHz or slightly less, but in certain cases (such as a high-impedance analog source) a slower clock may be desirable." /> + <BitField start="16" size="1" name="BURST" description="Burst mode"> + <Enum name="BURST" start="1" description="The AD converter does repeated conversions at up to 400 kHz, scanning (if necessary) through the pins selected by bits set to ones in the SEL field. The first conversion after the start corresponds to the least-significant 1 in the SEL field, then higher numbered 1-bits (pins) if applicable. Repeated conversions can be terminated by clearing this bit, but the conversion that's in progress when this bit is cleared will be completed. START bits must be 000 when BURST = 1 or conversions will not start." /> + <Enum name="SW" start="0" description="Conversions are software controlled and require 31 clocks." /> + </BitField> + <BitField start="17" size="4" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="21" size="1" name="PDN" description="Power down mode"> + <Enum name="POWERED" start="1" description="The A/D converter is operational." /> + <Enum name="POWERDOWN" start="0" description="The A/D converter is in power-down mode." /> + </BitField> + <BitField start="22" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="24" size="3" name="START" description="When the BURST bit is 0, these bits control whether and when an A/D conversion is started:"> + <Enum name="NO_START_THIS_VALUE" start="0x0" description="No start (this value should be used when clearing PDN to 0)." /> + <Enum name="START_CONVERSION_NOW" start="0x1" description="Start conversion now." /> + <Enum name="P2_10" start="0x2" description="Start conversion when the edge selected by bit 27 occurs on the P2[10] pin." /> + <Enum name="P1_27" start="0x3" description="Start conversion when the edge selected by bit 27 occurs on the P1[27] pin." /> + <Enum name="MAT0_1" start="0x4" description="Start conversion when the edge selected by bit 27 occurs on MAT0.1. Note that this does not require that the MAT0.1 function appear on a device pin." /> + <Enum name="MAT0_3" start="0x5" description="Start conversion when the edge selected by bit 27 occurs on MAT0.3. Note that it is not possible to cause the MAT0.3 function to appear on a device pin." /> + <Enum name="MAT1_0" start="0x6" description="Start conversion when the edge selected by bit 27 occurs on MAT1.0. Note that this does not require that the MAT1.0 function appear on a device pin." /> + <Enum name="MAT1_1" start="0x7" description="Start conversion when the edge selected by bit 27 occurs on MAT1.1. Note that this does not require that the MAT1.1 function appear on a device pin." /> + </BitField> + <BitField start="27" size="1" name="EDGE" description="This bit is significant only when the START field contains 010-111. In these cases:"> + <Enum name="FALLLING" start="1" description="Start conversion on a falling edge on the selected CAP/MAT signal." /> + <Enum name="RISING" start="0" description="Start conversion on a rising edge on the selected CAP/MAT signal." /> + </BitField> + <BitField start="28" size="4" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x004" size="4" name="GDR" access="Read/Write" description="A/D Global Data Register. This register contains the ADC's DONE bit and the result of the most recent A/D conversion." reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="4" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="4" size="12" name="RESULT" description="When DONE is 1, this field contains a binary fraction representing the voltage on the AD0[n] pin selected by the SEL field, as it falls within the range of VREFP to VSS. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VSS, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP." /> + <BitField start="16" size="8" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="24" size="3" name="CHN" description="These bits contain the channel from which the RESULT bits were converted (e.g. 000 identifies channel 0, 001 channel 1...)." /> + <BitField start="27" size="3" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the RESULT bits. This bit is cleared by reading this register." /> + <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read and when the ADCR is written. If the ADCR is written while a conversion is still in progress, this bit is set and a new conversion is started." /> + </Register> + <Register start="+0x00C" size="4" name="INTEN" access="Read/Write" description="A/D Interrupt Enable Register. This register contains enable bits that allow the DONE flag of each A/D channel to be included or excluded from contributing to the generation of an A/D interrupt." reset_value="0x100" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="ADINTEN0" description="Interrupt enable"> + <Enum name="DISABLE" start="0" description="Completion of a conversion on ADC channel 0 will not generate an interrupt." /> + <Enum name="ENABLE" start="1" description="Completion of a conversion on ADC channel 0 will generate an interrupt." /> + </BitField> + <BitField start="1" size="1" name="ADINTEN1" description="Interrupt enable"> + <Enum name="DISABLE" start="0" description="Completion of a conversion on ADC channel 1 will not generate an interrupt." /> + <Enum name="ENABLE" start="1" description="Completion of a conversion on ADC channel 1 will generate an interrupt." /> + </BitField> + <BitField start="2" size="1" name="ADINTEN2" description="Interrupt enable"> + <Enum name="DISABLE" start="0" description="Completion of a conversion on ADC channel 2 will not generate an interrupt." /> + <Enum name="ENABLE" start="1" description="Completion of a conversion on ADC channel 2 will generate an interrupt." /> + </BitField> + <BitField start="3" size="1" name="ADINTEN3" description="Interrupt enable"> + <Enum name="DISABLE" start="0" description="Completion of a conversion on ADC channel 3 will not generate an interrupt." /> + <Enum name="ENABLE" start="1" description="Completion of a conversion on ADC channel 3 will generate an interrupt." /> + </BitField> + <BitField start="4" size="1" name="ADINTEN4" description="Interrupt enable"> + <Enum name="DISABLE" start="0" description="Completion of a conversion on ADC channel 4 will not generate an interrupt." /> + <Enum name="ENABLE" start="1" description="Completion of a conversion on ADC channel 4 will generate an interrupt." /> + </BitField> + <BitField start="5" size="1" name="ADINTEN5" description="Interrupt enable"> + <Enum name="DISABLE" start="0" description="Completion of a conversion on ADC channel 5 will not generate an interrupt." /> + <Enum name="ENABLE" start="1" description="Completion of a conversion on ADC channel 5 will generate an interrupt." /> + </BitField> + <BitField start="6" size="1" name="ADINTEN6" description="Interrupt enable"> + <Enum name="DISABLE" start="0" description="Completion of a conversion on ADC channel 6 will not generate an interrupt." /> + <Enum name="ENABLE" start="1" description="Completion of a conversion on ADC channel 6 will generate an interrupt." /> + </BitField> + <BitField start="7" size="1" name="ADINTEN7" description="Interrupt enable"> + <Enum name="DISABLE" start="0" description="Completion of a conversion on ADC channel 7 will not generate an interrupt." /> + <Enum name="ENABLE" start="1" description="Completion of a conversion on ADC channel 7 will generate an interrupt." /> + </BitField> + <BitField start="8" size="1" name="ADGINTEN" description="Interrupt enable"> + <Enum name="CHANNELS" start="0" description="Only the individual ADC channels enabled by ADINTEN7:0 will generate interrupts." /> + <Enum name="GLOBAL" start="1" description="The global DONE flag in ADDR is enabled to generate an interrupt in addition to any individual ADC channels that are enabled to generate interrupts." /> + </BitField> + <BitField start="9" size="23" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x010+0" size="4" name="DR[0]" access="ReadOnly" description="A/D Channel 0 Data Register. This register contains the result of the most recent conversion completed on channel 0." reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="4" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="4" size="12" name="RESULT" description="When DONE is 1, this field contains a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to V SS. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VSS, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP." /> + <BitField start="16" size="14" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the RESULT bits.This bit is cleared by reading this register." /> + <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." /> + </Register> + <Register start="+0x010+4" size="4" name="DR[1]" access="ReadOnly" description="A/D Channel 0 Data Register. This register contains the result of the most recent conversion completed on channel 0." reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="4" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="4" size="12" name="RESULT" description="When DONE is 1, this field contains a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to V SS. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VSS, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP." /> + <BitField start="16" size="14" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the RESULT bits.This bit is cleared by reading this register." /> + <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." /> + </Register> + <Register start="+0x010+8" size="4" name="DR[2]" access="ReadOnly" description="A/D Channel 0 Data Register. This register contains the result of the most recent conversion completed on channel 0." reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="4" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="4" size="12" name="RESULT" description="When DONE is 1, this field contains a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to V SS. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VSS, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP." /> + <BitField start="16" size="14" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the RESULT bits.This bit is cleared by reading this register." /> + <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." /> + </Register> + <Register start="+0x010+12" size="4" name="DR[3]" access="ReadOnly" description="A/D Channel 0 Data Register. This register contains the result of the most recent conversion completed on channel 0." reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="4" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="4" size="12" name="RESULT" description="When DONE is 1, this field contains a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to V SS. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VSS, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP." /> + <BitField start="16" size="14" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the RESULT bits.This bit is cleared by reading this register." /> + <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." /> + </Register> + <Register start="+0x010+16" size="4" name="DR[4]" access="ReadOnly" description="A/D Channel 0 Data Register. This register contains the result of the most recent conversion completed on channel 0." reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="4" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="4" size="12" name="RESULT" description="When DONE is 1, this field contains a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to V SS. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VSS, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP." /> + <BitField start="16" size="14" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the RESULT bits.This bit is cleared by reading this register." /> + <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." /> + </Register> + <Register start="+0x010+20" size="4" name="DR[5]" access="ReadOnly" description="A/D Channel 0 Data Register. This register contains the result of the most recent conversion completed on channel 0." reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="4" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="4" size="12" name="RESULT" description="When DONE is 1, this field contains a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to V SS. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VSS, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP." /> + <BitField start="16" size="14" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the RESULT bits.This bit is cleared by reading this register." /> + <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." /> + </Register> + <Register start="+0x010+24" size="4" name="DR[6]" access="ReadOnly" description="A/D Channel 0 Data Register. This register contains the result of the most recent conversion completed on channel 0." reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="4" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="4" size="12" name="RESULT" description="When DONE is 1, this field contains a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to V SS. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VSS, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP." /> + <BitField start="16" size="14" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the RESULT bits.This bit is cleared by reading this register." /> + <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." /> + </Register> + <Register start="+0x010+28" size="4" name="DR[7]" access="ReadOnly" description="A/D Channel 0 Data Register. This register contains the result of the most recent conversion completed on channel 0." reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="4" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="4" size="12" name="RESULT" description="When DONE is 1, this field contains a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to V SS. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VSS, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP." /> + <BitField start="16" size="14" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the RESULT bits.This bit is cleared by reading this register." /> + <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." /> + </Register> + <Register start="+0x030" size="4" name="STAT" access="ReadOnly" description="A/D Status Register. This register contains DONE and OVERRUN flags for all of the A/D channels, as well as the A/D interrupt/DMA flag." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="DONE0" description="This bit mirrors the DONE status flag from the result register for A/D channel 0." /> + <BitField start="1" size="1" name="DONE1" description="This bit mirrors the DONE status flag from the result register for A/D channel 1." /> + <BitField start="2" size="1" name="DONE2" description="This bit mirrors the DONE status flag from the result register for A/D channel 2." /> + <BitField start="3" size="1" name="DONE3" description="This bit mirrors the DONE status flag from the result register for A/D channel 3." /> + <BitField start="4" size="1" name="DONE4" description="This bit mirrors the DONE status flag from the result register for A/D channel 4." /> + <BitField start="5" size="1" name="DONE5" description="This bit mirrors the DONE status flag from the result register for A/D channel 5." /> + <BitField start="6" size="1" name="DONE6" description="This bit mirrors the DONE status flag from the result register for A/D channel 6." /> + <BitField start="7" size="1" name="DONE7" description="This bit mirrors the DONE status flag from the result register for A/D channel 7." /> + <BitField start="8" size="1" name="OVERRUN0" description="This bit mirrors the OVERRRUN status flag from the result register for A/D channel 0." /> + <BitField start="9" size="1" name="OVERRUN1" description="This bit mirrors the OVERRRUN status flag from the result register for A/D channel 1." /> + <BitField start="10" size="1" name="OVERRUN2" description="This bit mirrors the OVERRRUN status flag from the result register for A/D channel 2." /> + <BitField start="11" size="1" name="OVERRUN3" description="This bit mirrors the OVERRRUN status flag from the result register for A/D channel 3." /> + <BitField start="12" size="1" name="OVERRUN4" description="This bit mirrors the OVERRRUN status flag from the result register for A/D channel 4." /> + <BitField start="13" size="1" name="OVERRUN5" description="This bit mirrors the OVERRRUN status flag from the result register for A/D channel 5." /> + <BitField start="14" size="1" name="OVERRUN6" description="This bit mirrors the OVERRRUN status flag from the result register for A/D channel 6." /> + <BitField start="15" size="1" name="OVERRUN7" description="This bit mirrors the OVERRRUN status flag from the result register for A/D channel 7." /> + <BitField start="16" size="1" name="ADINT" description="This bit is the A/D interrupt flag. It is one when any of the individual A/D channel Done flags is asserted and enabled to contribute to the A/D interrupt via the ADINTEN register." /> + <BitField start="17" size="15" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x034" size="4" name="TRM" access="Read/Write" description="ADC trim register." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="4" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="4" size="4" name="ADCOFFS" description="Offset trim bits for ADC operation. Initialized by the boot code. Can be overwritten by the user." /> + <BitField start="8" size="4" name="TRIM" description="written-to by boot code. Can not be overwritten by the user. These bits are locked after boot code write." /> + <BitField start="12" size="20" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + </RegisterGroup> + <RegisterGroup name="CANAFRAM" start="0x40038000" description="CAN acceptance filter RAM"> + <Register start="+0x000+0" size="4" name="MASK[0]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+4" size="4" name="MASK[1]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+8" size="4" name="MASK[2]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+12" size="4" name="MASK[3]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+16" size="4" name="MASK[4]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+20" size="4" name="MASK[5]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+24" size="4" name="MASK[6]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+28" size="4" name="MASK[7]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+32" size="4" name="MASK[8]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+36" size="4" name="MASK[9]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+40" size="4" name="MASK[10]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+44" size="4" name="MASK[11]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+48" size="4" name="MASK[12]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+52" size="4" name="MASK[13]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+56" size="4" name="MASK[14]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+60" size="4" name="MASK[15]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+64" size="4" name="MASK[16]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+68" size="4" name="MASK[17]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+72" size="4" name="MASK[18]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+76" size="4" name="MASK[19]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+80" size="4" name="MASK[20]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+84" size="4" name="MASK[21]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+88" size="4" name="MASK[22]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+92" size="4" name="MASK[23]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+96" size="4" name="MASK[24]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+100" size="4" name="MASK[25]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+104" size="4" name="MASK[26]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+108" size="4" name="MASK[27]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+112" size="4" name="MASK[28]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+116" size="4" name="MASK[29]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+120" size="4" name="MASK[30]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+124" size="4" name="MASK[31]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+128" size="4" name="MASK[32]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+132" size="4" name="MASK[33]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+136" size="4" name="MASK[34]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+140" size="4" name="MASK[35]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+144" size="4" name="MASK[36]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+148" size="4" name="MASK[37]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+152" size="4" name="MASK[38]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+156" size="4" name="MASK[39]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+160" size="4" name="MASK[40]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+164" size="4" name="MASK[41]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+168" size="4" name="MASK[42]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+172" size="4" name="MASK[43]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+176" size="4" name="MASK[44]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+180" size="4" name="MASK[45]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+184" size="4" name="MASK[46]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+188" size="4" name="MASK[47]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+192" size="4" name="MASK[48]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+196" size="4" name="MASK[49]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+200" size="4" name="MASK[50]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+204" size="4" name="MASK[51]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+208" size="4" name="MASK[52]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+212" size="4" name="MASK[53]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+216" size="4" name="MASK[54]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+220" size="4" name="MASK[55]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+224" size="4" name="MASK[56]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+228" size="4" name="MASK[57]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+232" size="4" name="MASK[58]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+236" size="4" name="MASK[59]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+240" size="4" name="MASK[60]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+244" size="4" name="MASK[61]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+248" size="4" name="MASK[62]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+252" size="4" name="MASK[63]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+256" size="4" name="MASK[64]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+260" size="4" name="MASK[65]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+264" size="4" name="MASK[66]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+268" size="4" name="MASK[67]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+272" size="4" name="MASK[68]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+276" size="4" name="MASK[69]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+280" size="4" name="MASK[70]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+284" size="4" name="MASK[71]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+288" size="4" name="MASK[72]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+292" size="4" name="MASK[73]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+296" size="4" name="MASK[74]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+300" size="4" name="MASK[75]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+304" size="4" name="MASK[76]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+308" size="4" name="MASK[77]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+312" size="4" name="MASK[78]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+316" size="4" name="MASK[79]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+320" size="4" name="MASK[80]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+324" size="4" name="MASK[81]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+328" size="4" name="MASK[82]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+332" size="4" name="MASK[83]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+336" size="4" name="MASK[84]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+340" size="4" name="MASK[85]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+344" size="4" name="MASK[86]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+348" size="4" name="MASK[87]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+352" size="4" name="MASK[88]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+356" size="4" name="MASK[89]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+360" size="4" name="MASK[90]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+364" size="4" name="MASK[91]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+368" size="4" name="MASK[92]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+372" size="4" name="MASK[93]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+376" size="4" name="MASK[94]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+380" size="4" name="MASK[95]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+384" size="4" name="MASK[96]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+388" size="4" name="MASK[97]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+392" size="4" name="MASK[98]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+396" size="4" name="MASK[99]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+400" size="4" name="MASK[100]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+404" size="4" name="MASK[101]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+408" size="4" name="MASK[102]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+412" size="4" name="MASK[103]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+416" size="4" name="MASK[104]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+420" size="4" name="MASK[105]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+424" size="4" name="MASK[106]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+428" size="4" name="MASK[107]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+432" size="4" name="MASK[108]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+436" size="4" name="MASK[109]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+440" size="4" name="MASK[110]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+444" size="4" name="MASK[111]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+448" size="4" name="MASK[112]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+452" size="4" name="MASK[113]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+456" size="4" name="MASK[114]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+460" size="4" name="MASK[115]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+464" size="4" name="MASK[116]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+468" size="4" name="MASK[117]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+472" size="4" name="MASK[118]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+476" size="4" name="MASK[119]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+480" size="4" name="MASK[120]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+484" size="4" name="MASK[121]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+488" size="4" name="MASK[122]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+492" size="4" name="MASK[123]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+496" size="4" name="MASK[124]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+500" size="4" name="MASK[125]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+504" size="4" name="MASK[126]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+508" size="4" name="MASK[127]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+512" size="4" name="MASK[128]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+516" size="4" name="MASK[129]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+520" size="4" name="MASK[130]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+524" size="4" name="MASK[131]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+528" size="4" name="MASK[132]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+532" size="4" name="MASK[133]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+536" size="4" name="MASK[134]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+540" size="4" name="MASK[135]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+544" size="4" name="MASK[136]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+548" size="4" name="MASK[137]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+552" size="4" name="MASK[138]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+556" size="4" name="MASK[139]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+560" size="4" name="MASK[140]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+564" size="4" name="MASK[141]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+568" size="4" name="MASK[142]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+572" size="4" name="MASK[143]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+576" size="4" name="MASK[144]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+580" size="4" name="MASK[145]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+584" size="4" name="MASK[146]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+588" size="4" name="MASK[147]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+592" size="4" name="MASK[148]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+596" size="4" name="MASK[149]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+600" size="4" name="MASK[150]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+604" size="4" name="MASK[151]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+608" size="4" name="MASK[152]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+612" size="4" name="MASK[153]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+616" size="4" name="MASK[154]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+620" size="4" name="MASK[155]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+624" size="4" name="MASK[156]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+628" size="4" name="MASK[157]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+632" size="4" name="MASK[158]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+636" size="4" name="MASK[159]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+640" size="4" name="MASK[160]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+644" size="4" name="MASK[161]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+648" size="4" name="MASK[162]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+652" size="4" name="MASK[163]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+656" size="4" name="MASK[164]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+660" size="4" name="MASK[165]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+664" size="4" name="MASK[166]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+668" size="4" name="MASK[167]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+672" size="4" name="MASK[168]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+676" size="4" name="MASK[169]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+680" size="4" name="MASK[170]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+684" size="4" name="MASK[171]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+688" size="4" name="MASK[172]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+692" size="4" name="MASK[173]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+696" size="4" name="MASK[174]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+700" size="4" name="MASK[175]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+704" size="4" name="MASK[176]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+708" size="4" name="MASK[177]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+712" size="4" name="MASK[178]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+716" size="4" name="MASK[179]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+720" size="4" name="MASK[180]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+724" size="4" name="MASK[181]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+728" size="4" name="MASK[182]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+732" size="4" name="MASK[183]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+736" size="4" name="MASK[184]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+740" size="4" name="MASK[185]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+744" size="4" name="MASK[186]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+748" size="4" name="MASK[187]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+752" size="4" name="MASK[188]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+756" size="4" name="MASK[189]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+760" size="4" name="MASK[190]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+764" size="4" name="MASK[191]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+768" size="4" name="MASK[192]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+772" size="4" name="MASK[193]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+776" size="4" name="MASK[194]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+780" size="4" name="MASK[195]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+784" size="4" name="MASK[196]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+788" size="4" name="MASK[197]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+792" size="4" name="MASK[198]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+796" size="4" name="MASK[199]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+800" size="4" name="MASK[200]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+804" size="4" name="MASK[201]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+808" size="4" name="MASK[202]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+812" size="4" name="MASK[203]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+816" size="4" name="MASK[204]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+820" size="4" name="MASK[205]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+824" size="4" name="MASK[206]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+828" size="4" name="MASK[207]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+832" size="4" name="MASK[208]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+836" size="4" name="MASK[209]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+840" size="4" name="MASK[210]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+844" size="4" name="MASK[211]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+848" size="4" name="MASK[212]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+852" size="4" name="MASK[213]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+856" size="4" name="MASK[214]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+860" size="4" name="MASK[215]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+864" size="4" name="MASK[216]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+868" size="4" name="MASK[217]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+872" size="4" name="MASK[218]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+876" size="4" name="MASK[219]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+880" size="4" name="MASK[220]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+884" size="4" name="MASK[221]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+888" size="4" name="MASK[222]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+892" size="4" name="MASK[223]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+896" size="4" name="MASK[224]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+900" size="4" name="MASK[225]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+904" size="4" name="MASK[226]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+908" size="4" name="MASK[227]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+912" size="4" name="MASK[228]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+916" size="4" name="MASK[229]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+920" size="4" name="MASK[230]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+924" size="4" name="MASK[231]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+928" size="4" name="MASK[232]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+932" size="4" name="MASK[233]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+936" size="4" name="MASK[234]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+940" size="4" name="MASK[235]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+944" size="4" name="MASK[236]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+948" size="4" name="MASK[237]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+952" size="4" name="MASK[238]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+956" size="4" name="MASK[239]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+960" size="4" name="MASK[240]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+964" size="4" name="MASK[241]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+968" size="4" name="MASK[242]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+972" size="4" name="MASK[243]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+976" size="4" name="MASK[244]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+980" size="4" name="MASK[245]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+984" size="4" name="MASK[246]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+988" size="4" name="MASK[247]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+992" size="4" name="MASK[248]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+996" size="4" name="MASK[249]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1000" size="4" name="MASK[250]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1004" size="4" name="MASK[251]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1008" size="4" name="MASK[252]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1012" size="4" name="MASK[253]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1016" size="4" name="MASK[254]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1020" size="4" name="MASK[255]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1024" size="4" name="MASK[256]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1028" size="4" name="MASK[257]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1032" size="4" name="MASK[258]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1036" size="4" name="MASK[259]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1040" size="4" name="MASK[260]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1044" size="4" name="MASK[261]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1048" size="4" name="MASK[262]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1052" size="4" name="MASK[263]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1056" size="4" name="MASK[264]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1060" size="4" name="MASK[265]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1064" size="4" name="MASK[266]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1068" size="4" name="MASK[267]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1072" size="4" name="MASK[268]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1076" size="4" name="MASK[269]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1080" size="4" name="MASK[270]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1084" size="4" name="MASK[271]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1088" size="4" name="MASK[272]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1092" size="4" name="MASK[273]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1096" size="4" name="MASK[274]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1100" size="4" name="MASK[275]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1104" size="4" name="MASK[276]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1108" size="4" name="MASK[277]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1112" size="4" name="MASK[278]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1116" size="4" name="MASK[279]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1120" size="4" name="MASK[280]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1124" size="4" name="MASK[281]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1128" size="4" name="MASK[282]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1132" size="4" name="MASK[283]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1136" size="4" name="MASK[284]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1140" size="4" name="MASK[285]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1144" size="4" name="MASK[286]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1148" size="4" name="MASK[287]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1152" size="4" name="MASK[288]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1156" size="4" name="MASK[289]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1160" size="4" name="MASK[290]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1164" size="4" name="MASK[291]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1168" size="4" name="MASK[292]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1172" size="4" name="MASK[293]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1176" size="4" name="MASK[294]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1180" size="4" name="MASK[295]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1184" size="4" name="MASK[296]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1188" size="4" name="MASK[297]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1192" size="4" name="MASK[298]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1196" size="4" name="MASK[299]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1200" size="4" name="MASK[300]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1204" size="4" name="MASK[301]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1208" size="4" name="MASK[302]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1212" size="4" name="MASK[303]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1216" size="4" name="MASK[304]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1220" size="4" name="MASK[305]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1224" size="4" name="MASK[306]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1228" size="4" name="MASK[307]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1232" size="4" name="MASK[308]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1236" size="4" name="MASK[309]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1240" size="4" name="MASK[310]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1244" size="4" name="MASK[311]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1248" size="4" name="MASK[312]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1252" size="4" name="MASK[313]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1256" size="4" name="MASK[314]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1260" size="4" name="MASK[315]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1264" size="4" name="MASK[316]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1268" size="4" name="MASK[317]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1272" size="4" name="MASK[318]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1276" size="4" name="MASK[319]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1280" size="4" name="MASK[320]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1284" size="4" name="MASK[321]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1288" size="4" name="MASK[322]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1292" size="4" name="MASK[323]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1296" size="4" name="MASK[324]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1300" size="4" name="MASK[325]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1304" size="4" name="MASK[326]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1308" size="4" name="MASK[327]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1312" size="4" name="MASK[328]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1316" size="4" name="MASK[329]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1320" size="4" name="MASK[330]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1324" size="4" name="MASK[331]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1328" size="4" name="MASK[332]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1332" size="4" name="MASK[333]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1336" size="4" name="MASK[334]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1340" size="4" name="MASK[335]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1344" size="4" name="MASK[336]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1348" size="4" name="MASK[337]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1352" size="4" name="MASK[338]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1356" size="4" name="MASK[339]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1360" size="4" name="MASK[340]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1364" size="4" name="MASK[341]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1368" size="4" name="MASK[342]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1372" size="4" name="MASK[343]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1376" size="4" name="MASK[344]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1380" size="4" name="MASK[345]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1384" size="4" name="MASK[346]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1388" size="4" name="MASK[347]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1392" size="4" name="MASK[348]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1396" size="4" name="MASK[349]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1400" size="4" name="MASK[350]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1404" size="4" name="MASK[351]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1408" size="4" name="MASK[352]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1412" size="4" name="MASK[353]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1416" size="4" name="MASK[354]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1420" size="4" name="MASK[355]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1424" size="4" name="MASK[356]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1428" size="4" name="MASK[357]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1432" size="4" name="MASK[358]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1436" size="4" name="MASK[359]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1440" size="4" name="MASK[360]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1444" size="4" name="MASK[361]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1448" size="4" name="MASK[362]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1452" size="4" name="MASK[363]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1456" size="4" name="MASK[364]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1460" size="4" name="MASK[365]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1464" size="4" name="MASK[366]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1468" size="4" name="MASK[367]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1472" size="4" name="MASK[368]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1476" size="4" name="MASK[369]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1480" size="4" name="MASK[370]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1484" size="4" name="MASK[371]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1488" size="4" name="MASK[372]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1492" size="4" name="MASK[373]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1496" size="4" name="MASK[374]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1500" size="4" name="MASK[375]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1504" size="4" name="MASK[376]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1508" size="4" name="MASK[377]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1512" size="4" name="MASK[378]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1516" size="4" name="MASK[379]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1520" size="4" name="MASK[380]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1524" size="4" name="MASK[381]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1528" size="4" name="MASK[382]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1532" size="4" name="MASK[383]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1536" size="4" name="MASK[384]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1540" size="4" name="MASK[385]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1544" size="4" name="MASK[386]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1548" size="4" name="MASK[387]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1552" size="4" name="MASK[388]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1556" size="4" name="MASK[389]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1560" size="4" name="MASK[390]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1564" size="4" name="MASK[391]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1568" size="4" name="MASK[392]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1572" size="4" name="MASK[393]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1576" size="4" name="MASK[394]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1580" size="4" name="MASK[395]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1584" size="4" name="MASK[396]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1588" size="4" name="MASK[397]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1592" size="4" name="MASK[398]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1596" size="4" name="MASK[399]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1600" size="4" name="MASK[400]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1604" size="4" name="MASK[401]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1608" size="4" name="MASK[402]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1612" size="4" name="MASK[403]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1616" size="4" name="MASK[404]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1620" size="4" name="MASK[405]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1624" size="4" name="MASK[406]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1628" size="4" name="MASK[407]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1632" size="4" name="MASK[408]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1636" size="4" name="MASK[409]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1640" size="4" name="MASK[410]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1644" size="4" name="MASK[411]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1648" size="4" name="MASK[412]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1652" size="4" name="MASK[413]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1656" size="4" name="MASK[414]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1660" size="4" name="MASK[415]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1664" size="4" name="MASK[416]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1668" size="4" name="MASK[417]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1672" size="4" name="MASK[418]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1676" size="4" name="MASK[419]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1680" size="4" name="MASK[420]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1684" size="4" name="MASK[421]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1688" size="4" name="MASK[422]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1692" size="4" name="MASK[423]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1696" size="4" name="MASK[424]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1700" size="4" name="MASK[425]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1704" size="4" name="MASK[426]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1708" size="4" name="MASK[427]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1712" size="4" name="MASK[428]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1716" size="4" name="MASK[429]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1720" size="4" name="MASK[430]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1724" size="4" name="MASK[431]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1728" size="4" name="MASK[432]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1732" size="4" name="MASK[433]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1736" size="4" name="MASK[434]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1740" size="4" name="MASK[435]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1744" size="4" name="MASK[436]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1748" size="4" name="MASK[437]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1752" size="4" name="MASK[438]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1756" size="4" name="MASK[439]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1760" size="4" name="MASK[440]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1764" size="4" name="MASK[441]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1768" size="4" name="MASK[442]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1772" size="4" name="MASK[443]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1776" size="4" name="MASK[444]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1780" size="4" name="MASK[445]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1784" size="4" name="MASK[446]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1788" size="4" name="MASK[447]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1792" size="4" name="MASK[448]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1796" size="4" name="MASK[449]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1800" size="4" name="MASK[450]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1804" size="4" name="MASK[451]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1808" size="4" name="MASK[452]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1812" size="4" name="MASK[453]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1816" size="4" name="MASK[454]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1820" size="4" name="MASK[455]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1824" size="4" name="MASK[456]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1828" size="4" name="MASK[457]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1832" size="4" name="MASK[458]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1836" size="4" name="MASK[459]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1840" size="4" name="MASK[460]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1844" size="4" name="MASK[461]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1848" size="4" name="MASK[462]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1852" size="4" name="MASK[463]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1856" size="4" name="MASK[464]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1860" size="4" name="MASK[465]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1864" size="4" name="MASK[466]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1868" size="4" name="MASK[467]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1872" size="4" name="MASK[468]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1876" size="4" name="MASK[469]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1880" size="4" name="MASK[470]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1884" size="4" name="MASK[471]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1888" size="4" name="MASK[472]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1892" size="4" name="MASK[473]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1896" size="4" name="MASK[474]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1900" size="4" name="MASK[475]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1904" size="4" name="MASK[476]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1908" size="4" name="MASK[477]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1912" size="4" name="MASK[478]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1916" size="4" name="MASK[479]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1920" size="4" name="MASK[480]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1924" size="4" name="MASK[481]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1928" size="4" name="MASK[482]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1932" size="4" name="MASK[483]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1936" size="4" name="MASK[484]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1940" size="4" name="MASK[485]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1944" size="4" name="MASK[486]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1948" size="4" name="MASK[487]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1952" size="4" name="MASK[488]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1956" size="4" name="MASK[489]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1960" size="4" name="MASK[490]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1964" size="4" name="MASK[491]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1968" size="4" name="MASK[492]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1972" size="4" name="MASK[493]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1976" size="4" name="MASK[494]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1980" size="4" name="MASK[495]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1984" size="4" name="MASK[496]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1988" size="4" name="MASK[497]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1992" size="4" name="MASK[498]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1996" size="4" name="MASK[499]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+2000" size="4" name="MASK[500]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+2004" size="4" name="MASK[501]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+2008" size="4" name="MASK[502]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+2012" size="4" name="MASK[503]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+2016" size="4" name="MASK[504]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+2020" size="4" name="MASK[505]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+2024" size="4" name="MASK[506]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+2028" size="4" name="MASK[507]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+2032" size="4" name="MASK[508]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+2036" size="4" name="MASK[509]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+2040" size="4" name="MASK[510]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+2044" size="4" name="MASK[511]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + </RegisterGroup> + <RegisterGroup name="CANAF" start="0x4003C000" description="CAN controller"> + <Register start="+0x000" size="4" name="AFMR" access="Read/Write" description="Acceptance Filter Register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="ACCOFF" description="if AccBP is 0, the Acceptance Filter is not operational. All Rx messages on all CAN buses are ignored." /> + <BitField start="1" size="1" name="ACCBP" description="All Rx messages are accepted on enabled CAN controllers. Software must set this bit before modifying the contents of any of the registers described below, and before modifying the contents of Lookup Table RAM in any way other than setting or clearing Disable bits in Standard Identifier entries. When both this bit and AccOff are 0, the Acceptance filter operates to screen received CAN Identifiers." /> + <BitField start="2" size="1" name="EFCAN" description="FullCAN mode"> + <Enum name="SOFTWARE_MUST_READ_A" start="0" description="Software must read all messages for all enabled IDs on all enabled CAN buses, from the receiving CAN controllers." /> + <Enum name="THE_ACCEPTANCE_FILTE" start="1" description="The Acceptance Filter itself will take care of receiving and storing messages for selected Standard ID values on selected CAN buses. See Section 21.16 FullCAN mode on page 576." /> + </BitField> + <BitField start="3" size="29" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x004" size="4" name="SFF_SA" access="Read/Write" description="Standard Frame Individual Start Address Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="2" size="9" name="SFF_SA" description="The start address of the table of individual Standard Identifiers in AF Lookup RAM. If the table is empty, write the same value in this register and the SFF_GRP_sa register described below. For compatibility with possible future devices, write zeroes in bits 31:11 and 1:0 of this register. If the eFCAN bit in the AFMR is 1, this value also indicates the size of the table of Standard IDs which the Acceptance Filter will search and (if found) automatically store received messages in Acceptance Filter RAM." /> + <BitField start="11" size="21" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x008" size="4" name="SFF_GRP_SA" access="Read/Write" description="Standard Frame Group Start Address Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="2" size="10" name="SFF_GRP_SA" description="The start address of the table of grouped Standard Identifiers in AF Lookup RAM. If the table is empty, write the same value in this register and the EFF_sa register described below. The largest value that should be written to this register is 0x800, when only the Standard Individual table is used, and the last word (address 0x7FC) in AF Lookup Table RAM is used. For compatibility with possible future devices, please write zeroes in bits 31:12 and 1:0 of this register." /> + <BitField start="12" size="20" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x00C" size="4" name="EFF_SA" access="Read/Write" description="Extended Frame Start Address Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="2" size="9" name="EFF_SA" description="The start address of the table of individual Extended Identifiers in AF Lookup RAM. If the table is empty, write the same value in this register and the EFF_GRP_sa register described below. The largest value that should be written to this register is 0x800, when both Extended Tables are empty and the last word (address 0x7FC) in AF Lookup Table RAM is used. For compatibility with possible future devices, please write zeroes in bits 31:11 and 1:0 of this register." /> + <BitField start="11" size="21" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x010" size="4" name="EFF_GRP_SA" access="Read/Write" description="Extended Frame Group Start Address Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="2" size="10" name="EFF_GRP_SA" description="The start address of the table of grouped Extended Identifiers in AF Lookup RAM. If the table is empty, write the same value in this register and the ENDofTable register described below. The largest value that should be written to this register is 0x800, when this table is empty and the last word (address 0x7FC) in AF Lookup Table RAM is used. For compatibility with possible future devices, please write zeroes in bits 31:12 and 1:0 of this register." /> + <BitField start="12" size="20" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x014" size="4" name="ENDOFTABLE" access="Read/Write" description="End of AF Tables register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="2" size="10" name="ENDOFTABLE" description="The address above the last active address in the last active AF table. For compatibility with possible future devices, please write zeroes in bits 31:12 and 1:0 of this register. If the eFCAN bit in the AFMR is 0, the largest value that should be written to this register is 0x800, which allows the last word (address 0x7FC) in AF Lookup Table RAM to be used. If the eFCAN bit in the AFMR is 1, this value marks the start of the area of Acceptance Filter RAM, into which the Acceptance Filter will automatically receive messages for selected IDs on selected CAN buses. In this case, the maximum value that should be written to this register is 0x800 minus 6 times the value in SFF_sa. This allows 12 bytes of message storage between this address and the end of Acceptance Filter RAM, for each Standard ID that is specified between the start of Acceptance Filter RAM, and the next active AF table." /> + <BitField start="12" size="20" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x018" size="4" name="LUTERRAD" access="ReadOnly" description="LUT Error Address register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="2" size="9" name="LUTERRAD" description="It the LUT Error bit (below) is 1, this read-only field contains the address in AF Lookup Table RAM, at which the Acceptance Filter encountered an error in the content of the tables." /> + <BitField start="11" size="21" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x01C" size="4" name="LUTERR" access="ReadOnly" description="LUT Error Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="LUTERR" description="This read-only bit is set to 1 if the Acceptance Filter encounters an error in the content of the tables in AF RAM. It is cleared when software reads the LUTerrAd register. This condition is ORed with the other CAN interrupts from the CAN controllers, to produce the request that is connected to the NVIC." /> + <BitField start="1" size="31" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x020" size="4" name="FCANIE" access="Read/Write" description="FullCAN interrupt enable register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="FCANIE" description="Global FullCAN Interrupt Enable. When 1, this interrupt is enabled." /> + <BitField start="1" size="31" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x024" size="4" name="FCANIC0" access="Read/Write" description="FullCAN interrupt and capture register0" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="INTPND" description="FullCan Interrupt Pending 0 = FullCan Interrupt Pending bit 0. 1 = FullCan Interrupt Pending bit 1. ... 31 = FullCan Interrupt Pending bit 31." /> + </Register> + <Register start="+0x028" size="4" name="FCANIC1" access="Read/Write" description="FullCAN interrupt and capture register1" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="IntPnd32" description="FullCan Interrupt Pending bit 32. 0 = FullCan Interrupt Pending bit 32. 1 = FullCan Interrupt Pending bit 33. ... 31 = FullCan Interrupt Pending bit 63." /> + </Register> + </RegisterGroup> + <RegisterGroup name="CCAN" start="0x40040000" description=" CAN controller"> + <Register start="+0x000" size="4" name="TXSR" access="ReadOnly" description="CAN Central Transmit Status Register" reset_value="0x00030300" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="TS1" description="When 1, the CAN controller 1 is sending a message (same as TS in the CAN1GSR)." /> + <BitField start="1" size="1" name="TS2" description="When 1, the CAN controller 2 is sending a message (same as TS in the CAN2GSR)" /> + <BitField start="2" size="6" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." /> + <BitField start="8" size="1" name="TBS1" description="When 1, all 3 Tx Buffers of the CAN1 controller are available to the CPU (same as TBS in CAN1GSR)." /> + <BitField start="9" size="1" name="TBS2" description="When 1, all 3 Tx Buffers of the CAN2 controller are available to the CPU (same as TBS in CAN2GSR)." /> + <BitField start="10" size="6" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." /> + <BitField start="16" size="1" name="TCS1" description="When 1, all requested transmissions have been completed successfully by the CAN1 controller (same as TCS in CAN1GSR)." /> + <BitField start="17" size="1" name="TCS2" description="When 1, all requested transmissions have been completed successfully by the CAN2 controller (same as TCS in CAN2GSR)." /> + <BitField start="18" size="14" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x004" size="4" name="RXSR" access="ReadOnly" description="CAN Central Receive Status Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RS1" description="When 1, CAN1 is receiving a message (same as RS in CAN1GSR)." /> + <BitField start="1" size="1" name="RS2" description="When 1, CAN2 is receiving a message (same as RS in CAN2GSR)." /> + <BitField start="2" size="6" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." /> + <BitField start="8" size="1" name="RB1" description="When 1, a received message is available in the CAN1 controller (same as RBS in CAN1GSR)." /> + <BitField start="9" size="1" name="RB2" description="When 1, a received message is available in the CAN2 controller (same as RBS in CAN2GSR)." /> + <BitField start="10" size="6" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." /> + <BitField start="16" size="1" name="DOS1" description="When 1, a message was lost because the preceding message to CAN1 controller was not read out quickly enough (same as DOS in CAN1GSR)." /> + <BitField start="17" size="1" name="DOS2" description="When 1, a message was lost because the preceding message to CAN2 controller was not read out quickly enough (same as DOS in CAN2GSR)." /> + <BitField start="18" size="14" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x008" size="4" name="MSR" access="ReadOnly" description="CAN Central Miscellaneous Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="E1" description="When 1, one or both of the CAN1 Tx and Rx Error Counters has reached the limit set in the CAN1EWL register (same as ES in CAN1GSR)" /> + <BitField start="1" size="1" name="E2" description="When 1, one or both of the CAN2 Tx and Rx Error Counters has reached the limit set in the CAN2EWL register (same as ES in CAN2GSR)" /> + <BitField start="2" size="6" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." /> + <BitField start="8" size="1" name="BS1" description="When 1, the CAN1 controller is currently involved in bus activities (same as BS in CAN1GSR)." /> + <BitField start="9" size="1" name="BS2" description="When 1, the CAN2 controller is currently involved in bus activities (same as BS in CAN2GSR)." /> + <BitField start="10" size="22" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." /> + </Register> + </RegisterGroup> + <RegisterGroup name="CAN1" start="0x40044000" description="CAN controller "> + <Register start="+0x000" size="4" name="MOD" access="Read/Write" description="Controls the operating mode of the CAN Controller." reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="RM" description="Reset Mode."> + <Enum name="NORMAL_THE_CAN_CONTR" start="0" description="Normal.The CAN Controller is in the Operating Mode, and certain registers can not be written." /> + <Enum name="RESET_CAN_OPERATION" start="1" description="Reset. CAN operation is disabled, writable registers can be written and the current transmission/reception of a message is aborted." /> + </BitField> + <BitField start="1" size="1" name="LOM" description="Listen Only Mode."> + <Enum name="NORMAL_THE_CAN_CONT" start="0" description="Normal. The CAN controller acknowledges a successfully received message on the CAN bus. The error counters are stopped at the current value." /> + <Enum name="LISTEN_ONLY_THE_CON" start="1" description="Listen only. The controller gives no acknowledgment, even if a message is successfully received. Messages cannot be sent, and the controller operates in error passive mode. This mode is intended for software bit rate detection and hot plugging." /> + </BitField> + <BitField start="2" size="1" name="STM" description="Self Test Mode."> + <Enum name="NORMAL_A_TRANSMITTE" start="0" description="Normal. A transmitted message must be acknowledged to be considered successful." /> + <Enum name="SELF_TEST_THE_CONTR" start="1" description="Self test. The controller will consider a Tx message successful even if there is no acknowledgment received. In this mode a full node test is possible without any other active node on the bus using the SRR bit in CANxCMR." /> + </BitField> + <BitField start="3" size="1" name="TPM" description="Transmit Priority Mode."> + <Enum name="CAN_ID_THE_TRANSMIT" start="0" description="CAN ID. The transmit priority for 3 Transmit Buffers depends on the CAN Identifier." /> + <Enum name="LOCAL_PRIORITY_THE_" start="1" description="Local priority. The transmit priority for 3 Transmit Buffers depends on the contents of the Tx Priority register within the Transmit Buffer." /> + </BitField> + <BitField start="4" size="1" name="SM" description="Sleep Mode."> + <Enum name="WAKE_UP_NORMAL_OPER" start="0" description="Wake-up. Normal operation." /> + <Enum name="SLEEP_THE_CAN_CONTR" start="1" description="Sleep. The CAN controller enters Sleep Mode if no CAN interrupt is pending and there is no bus activity. See the Sleep Mode description Section 21.8.2 on page 565." /> + </BitField> + <BitField start="5" size="1" name="RPM" description="Receive Polarity Mode."> + <Enum name="LOW_ACTIVE_RD_INPUT" start="0" description="Low active. RD input is active Low (dominant bit = 0)." /> + <Enum name="HIGH_ACTIVE_RD_INPU" start="1" description="High active. RD input is active High (dominant bit = 1) -- reverse polarity." /> + </BitField> + <BitField start="6" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="7" size="1" name="TM" description="Test Mode."> + <Enum name="DISABLED_NORMAL_OPE" start="0" description="Disabled. Normal operation." /> + <Enum name="ENABLED_THE_TD_PIN_" start="1" description="Enabled. The TD pin will reflect the bit, detected on RD pin, with the next positive edge of the system clock." /> + </BitField> + <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x004" size="4" name="CMR" access="WriteOnly" description="Command bits that affect the state of the CAN Controller" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="TR" description="Transmission Request."> + <Enum name="ABSENT_NO_TRANSMISSI" start="0" description="Absent.No transmission request." /> + <Enum name="PRESENT_THE_MESSAGE" start="1" description="Present. The message, previously written to the CANxTFI, CANxTID, and optionally the CANxTDA and CANxTDB registers, is queued for transmission from the selected Transmit Buffer. If at two or all three of STB1, STB2 and STB3 bits are selected when TR=1 is written, Transmit Buffer will be selected based on the chosen priority scheme (for details see Section 21.5.3 Transmit Buffers (TXB))" /> + </BitField> + <BitField start="1" size="1" name="AT" description="Abort Transmission."> + <Enum name="NO_ACTION_DO_NOT_AB" start="0" description="No action. Do not abort the transmission." /> + <Enum name="PRESENT_IF_NOT_ALRE" start="1" description="Present. if not already in progress, a pending Transmission Request for the selected Transmit Buffer is cancelled." /> + </BitField> + <BitField start="2" size="1" name="RRB" description="Release Receive Buffer."> + <Enum name="NO_ACTION_DO_NOT_RE" start="0" description="No action. Do not release the receive buffer." /> + <Enum name="RELEASED_THE_INFORM" start="1" description="Released. The information in the Receive Buffer (consisting of CANxRFS, CANxRID, and if applicable the CANxRDA and CANxRDB registers) is released, and becomes eligible for replacement by the next received frame. If the next received frame is not available, writing this command clears the RBS bit in the Status Register(s)." /> + </BitField> + <BitField start="3" size="1" name="CDO" description="Clear Data Overrun."> + <Enum name="NO_ACTION_DO_NOT_CL" start="0" description="No action. Do not clear the data overrun bit." /> + <Enum name="CLEAR_THE_DATA_OVER" start="1" description="Clear. The Data Overrun bit in Status Register(s) is cleared." /> + </BitField> + <BitField start="4" size="1" name="SRR" description="Self Reception Request."> + <Enum name="ABSENT_NO_SELF_RECE" start="0" description="Absent. No self reception request." /> + <Enum name="PRESENT_THE_MESSAGE" start="1" description="Present. The message, previously written to the CANxTFS, CANxTID, and optionally the CANxTDA and CANxTDB registers, is queued for transmission from the selected Transmit Buffer and received simultaneously. This differs from the TR bit above in that the receiver is not disabled during the transmission, so that it receives the message if its Identifier is recognized by the Acceptance Filter." /> + </BitField> + <BitField start="5" size="1" name="STB1" description="Select Tx Buffer 1."> + <Enum name="NOT_SELECTED_TX_BUF" start="0" description="Not selected. Tx Buffer 1 is not selected for transmission." /> + <Enum name="SELECTED_TX_BUFFER_" start="1" description="Selected. Tx Buffer 1 is selected for transmission." /> + </BitField> + <BitField start="6" size="1" name="STB2" description="Select Tx Buffer 2."> + <Enum name="NOT_SELECTED_TX_BUF" start="0" description="Not selected. Tx Buffer 2 is not selected for transmission." /> + <Enum name="SELECTED_TX_BUFFER_" start="1" description="Selected. Tx Buffer 2 is selected for transmission." /> + </BitField> + <BitField start="7" size="1" name="STB3" description="Select Tx Buffer 3."> + <Enum name="NOT_SELECTED_TX_BUF" start="0" description="Not selected. Tx Buffer 3 is not selected for transmission." /> + <Enum name="SELECTED_TX_BUFFER_" start="1" description="Selected. Tx Buffer 3 is selected for transmission." /> + </BitField> + <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x008" size="4" name="GSR" access="ReadOnly" description="Global Controller Status and Error Counters. The error counters can only be written when RM in CANMOD is 1." reset_value="0x3C" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RBS" description="Receive Buffer Status. After reading all messages and releasing their memory space with the command 'Release Receive Buffer,' this bit is cleared."> + <Enum name="EMPTY_NO_MESSAGE_IS" start="0" description="Empty. No message is available." /> + <Enum name="FULL_AT_LEAST_ONE_C" start="1" description="Full. At least one complete message is received by the Double Receive Buffer and available in the CANxRFS, CANxRID, and if applicable the CANxRDA and CANxRDB registers. This bit is cleared by the Release Receive Buffer command in CANxCMR, if no subsequent received message is available." /> + </BitField> + <BitField start="1" size="1" name="DOS" description="Data Overrun Status. If there is not enough space to store the message within the Receive Buffer, that message is dropped and the Data Overrun condition is signalled to the CPU in the moment this message becomes valid. If this message is not completed successfully (e.g. because of an error), no overrun condition is signalled."> + <Enum name="ABSENT_NO_DATA_OVER" start="0" description="Absent. No data overrun has occurred since the last Clear Data Overrun command was given/written to CANxCMR (or since Reset)." /> + <Enum name="OVERRUN_A_MESSAGE_W" start="1" description="Overrun. A message was lost because the preceding message to this CAN controller was not read and released quickly enough (there was not enough space for a new message in the Double Receive Buffer)." /> + </BitField> + <BitField start="2" size="1" name="TBS" description="Transmit Buffer Status."> + <Enum name="LOCKED_AT_LEAST_ONE" start="0" description="Locked. At least one of the Transmit Buffers is not available for the CPU, i.e. at least one previously queued message for this CAN controller has not yet been sent, and therefore software should not write to the CANxTFI, CANxTID, CANxTDA, nor CANxTDB registers of that (those) Tx buffer(s)." /> + <Enum name="RELEASED_ALL_THREE_" start="1" description="Released. All three Transmit Buffers are available for the CPU. No transmit message is pending for this CAN controller (in any of the 3 Tx buffers), and software may write to any of the CANxTFI, CANxTID, CANxTDA, and CANxTDB registers." /> + </BitField> + <BitField start="3" size="1" name="TCS" description="Transmit Complete Status. The Transmission Complete Status bit is set '0' (incomplete) whenever the Transmission Request bit or the Self Reception Request bit is set '1' at least for one of the three Transmit Buffers. The Transmission Complete Status bit will remain '0' until all messages are transmitted successfully."> + <Enum name="INCOMPLETE_AT_LEAST" start="0" description="Incomplete. At least one requested transmission has not been successfully completed yet." /> + <Enum name="COMPLETE_ALL_REQUES" start="1" description="Complete. All requested transmission(s) has (have) been successfully completed." /> + </BitField> + <BitField start="4" size="1" name="RS" description="Receive Status. If both the Receive Status and the Transmit Status bits are '0' (idle), the CAN-Bus is idle. If both bits are set, the controller is waiting to become idle again. After hardware reset 11 consecutive recessive bits have to be detected until idle status is reached. After Bus-off this will take 128 times of 11 consecutive recessive bits."> + <Enum name="IDLE_THE_CAN_CONTRO" start="0" description="Idle. The CAN controller is idle." /> + <Enum name="RECEIVE_THE_CAN_CON" start="1" description="Receive. The CAN controller is receiving a message." /> + </BitField> + <BitField start="5" size="1" name="TS" description="Transmit Status. If both the Receive Status and the Transmit Status bits are '0' (idle), the CAN-Bus is idle. If both bits are set, the controller is waiting to become idle again. After hardware reset 11 consecutive recessive bits have to be detected until idle status is reached. After Bus-off this will take 128 times of 11 consecutive recessive bits."> + <Enum name="IDLE_THE_CAN_CONTRO" start="0" description="Idle. The CAN controller is idle." /> + <Enum name="TRANSMIT_THE_CAN_CO" start="1" description="Transmit. The CAN controller is sending a message." /> + </BitField> + <BitField start="6" size="1" name="ES" description="Error Status. Errors detected during reception or transmission will effect the error counters according to the CAN specification. The Error Status bit is set when at least one of the error counters has reached or exceeded the Error Warning Limit. An Error Warning Interrupt is generated, if enabled. The default value of the Error Warning Limit after hardware reset is 96 decimal, see also Section 21.7.7 CAN Error Warning Limit register (CAN1EWL - 0x4004 4018, CAN2EWL - 0x4004 8018)."> + <Enum name="OK_BOTH_ERROR_COUNT" start="0" description="OK. Both error counters are below the Error Warning Limit." /> + <Enum name="ERROR_ONE_OR_BOTH_O" start="1" description="Error. One or both of the Transmit and Receive Error Counters has reached the limit set in the Error Warning Limit register." /> + </BitField> + <BitField start="7" size="1" name="BS" description="Bus Status. Mode bit '1' (present) and an Error Warning Interrupt is generated, if enabled. Afterwards the Transmit Error Counter is set to '127', and the Receive Error Counter is cleared. It will stay in this mode until the CPU clears the Reset Mode bit. Once this is completed the CAN Controller will wait the minimum protocol-defined time (128 occurrences of the Bus-Free signal) counting down the Transmit Error Counter. After that, the Bus Status bit is cleared (Bus-On), the Error Status bit is set '0' (ok), the Error Counters are reset, and an Error Warning Interrupt is generated, if enabled. Reading the TX Error Counter during this time gives information about the status of the Bus-Off recovery."> + <Enum name="BUS_ON_THE_CAN_CONT" start="0" description="Bus-on. The CAN Controller is involved in bus activities" /> + <Enum name="BUS_OFF_THE_CAN_CON" start="1" description="Bus-off. The CAN controller is currently not involved/prohibited from bus activity because the Transmit Error Counter reached its limiting value of 255." /> + </BitField> + <BitField start="8" size="8" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="16" size="8" name="RXERR" description="The current value of the Rx Error Counter (an 8-bit value)." /> + <BitField start="24" size="8" name="TXERR" description="The current value of the Tx Error Counter (an 8-bit value)." /> + </Register> + <Register start="+0x00C" size="4" name="ICR" access="ReadOnly" description="Interrupt status, Arbitration Lost Capture, Error Code Capture" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RI" description="Receive Interrupt. This bit is set whenever the RBS bit in CANxSR and the RIE bit in CANxIER are both 1, indicating that a new message was received and stored in the Receive Buffer. The Receive Interrupt Bit is not cleared upon a read access to the Interrupt Register. Giving the Command Release Receive Buffer will clear RI temporarily. If there is another message available within the Receive Buffer after the release command, RI is set again. Otherwise RI remains cleared."> + <Enum name="RESET" start="0" description="Reset" /> + <Enum name="SET" start="1" description="Set" /> + </BitField> + <BitField start="1" size="1" name="TI1" description="Transmit Interrupt 1. This bit is set when the TBS1 bit in CANxSR goes from 0 to 1 (whenever a message out of TXB1 was successfully transmitted or aborted), indicating that Transmit buffer 1 is available, and the TIE1 bit in CANxIER is 1."> + <Enum name="RESET" start="0" description="Reset" /> + <Enum name="SET" start="1" description="Set" /> + </BitField> + <BitField start="2" size="1" name="EI" description="Error Warning Interrupt. This bit is set on every change (set or clear) of either the Error Status or Bus Status bit in CANxSR and the EIE bit bit is set within the Interrupt Enable Register at the time of the change."> + <Enum name="RESET" start="0" description="Reset" /> + <Enum name="SET" start="1" description="Set" /> + </BitField> + <BitField start="3" size="1" name="DOI" description="Data Overrun Interrupt. This bit is set when the DOS bit in CANxSR goes from 0 to 1 and the DOIE bit in CANxIER is 1."> + <Enum name="RESET" start="0" description="Reset" /> + <Enum name="SET" start="1" description="Set" /> + </BitField> + <BitField start="4" size="1" name="WUI" description="Wake-Up Interrupt. This bit is set if the CAN controller is sleeping and bus activity is detected and the WUIE bit in CANxIER is 1. A Wake-Up Interrupt is also generated if the CPU tries to set the Sleep bit while the CAN controller is involved in bus activities or a CAN Interrupt is pending. The WUI flag can also get asserted when the according enable bit WUIE is not set. In this case a Wake-Up Interrupt does not get asserted."> + <Enum name="RESET" start="0" description="Reset" /> + <Enum name="SET" start="1" description="Set" /> + </BitField> + <BitField start="5" size="1" name="EPI" description="Error Passive Interrupt. This bit is set if the EPIE bit in CANxIER is 1, and the CAN controller switches between Error Passive and Error Active mode in either direction. This is the case when the CAN Controller has reached the Error Passive Status (at least one error counter exceeds the CAN protocol defined level of 127) or if the CAN Controller is in Error Passive Status and enters the Error Active Status again."> + <Enum name="RESET" start="0" description="Reset" /> + <Enum name="SET" start="1" description="Set" /> + </BitField> + <BitField start="6" size="1" name="ALI" description="Arbitration Lost Interrupt. This bit is set if the ALIE bit in CANxIER is 1, and the CAN controller loses arbitration while attempting to transmit. In this case the CAN node becomes a receiver."> + <Enum name="RESET" start="0" description="Reset" /> + <Enum name="SET" start="1" description="Set" /> + </BitField> + <BitField start="7" size="1" name="BEI" description="Bus Error Interrupt -- this bit is set if the BEIE bit in CANxIER is 1, and the CAN controller detects an error on the bus."> + <Enum name="RESET" start="0" description="Reset" /> + <Enum name="SET" start="1" description="Set" /> + </BitField> + <BitField start="8" size="1" name="IDI" description="ID Ready Interrupt -- this bit is set if the IDIE bit in CANxIER is 1, and a CAN Identifier has been received (a message was successfully transmitted or aborted). This bit is set whenever a message was successfully transmitted or aborted and the IDIE bit is set in the IER register."> + <Enum name="RESET" start="0" description="Reset" /> + <Enum name="SET" start="1" description="Set" /> + </BitField> + <BitField start="9" size="1" name="TI2" description="Transmit Interrupt 2. This bit is set when the TBS2 bit in CANxSR goes from 0 to 1 (whenever a message out of TXB2 was successfully transmitted or aborted), indicating that Transmit buffer 2 is available, and the TIE2 bit in CANxIER is 1."> + <Enum name="RESET" start="0" description="Reset" /> + <Enum name="SET" start="1" description="Set" /> + </BitField> + <BitField start="10" size="1" name="TI3" description="Transmit Interrupt 3. This bit is set when the TBS3 bit in CANxSR goes from 0 to 1 (whenever a message out of TXB3 was successfully transmitted or aborted), indicating that Transmit buffer 3 is available, and the TIE3 bit in CANxIER is 1."> + <Enum name="RESET" start="0" description="Reset" /> + <Enum name="SET" start="1" description="Set" /> + </BitField> + <BitField start="11" size="5" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + <BitField start="16" size="5" name="ERRBIT4_0" description="Error Code Capture: when the CAN controller detects a bus error, the location of the error within the frame is captured in this field. The value reflects an internal state variable, and as a result is not very linear: 00011 = Start of Frame 00010 = ID28 ... ID21 00110 = ID20 ... ID18 00100 = SRTR Bit 00101 = IDE bit 00111 = ID17 ... 13 01111 = ID12 ... ID5 01110 = ID4 ... ID0 01100 = RTR Bit 01101 = Reserved Bit 1 01001 = Reserved Bit 0 01011 = Data Length Code 01010 = Data Field 01000 = CRC Sequence 11000 = CRC Delimiter 11001 = Acknowledge Slot 11011 = Acknowledge Delimiter 11010 = End of Frame 10010 = Intermission Whenever a bus error occurs, the corresponding bus error interrupt is forced, if enabled. At the same time, the current position of the Bit Stream Processor is captured into the Error Code Capture Register. The content within this register is fixed until the user software has read out its content once. From now on, the capture mechanism is activated again, i.e. reading the CANxICR enables another Bus Error Interrupt." /> + <BitField start="21" size="1" name="ERRDIR" description="When the CAN controller detects a bus error, the direction of the current bit is captured in this bit."> + <Enum name="ERROR_OCCURRED_DURIN" start="0" description="Error occurred during transmitting." /> + <Enum name="ERROR_OCCURRED_DURIN" start="1" description="Error occurred during receiving." /> + </BitField> + <BitField start="22" size="2" name="ERRC1_0" description="When the CAN controller detects a bus error, the type of error is captured in this field:"> + <Enum name="BIT_ERROR" start="0x0" description="Bit error" /> + <Enum name="FORM_ERROR" start="0x1" description="Form error" /> + <Enum name="STUFF_ERROR" start="0x2" description="Stuff error" /> + <Enum name="OTHER_ERROR" start="0x3" description="Other error" /> + </BitField> + <BitField start="24" size="8" name="ALCBIT" description="Each time arbitration is lost while trying to send on the CAN, the bit number within the frame is captured into this field. After the content of ALCBIT is read, the ALI bit is cleared and a new Arbitration Lost interrupt can occur. 00 = arbitration lost in the first bit (MS) of identifier ... 11 = arbitration lost in SRTS bit (RTR bit for standard frame messages) 12 = arbitration lost in IDE bit 13 = arbitration lost in 12th bit of identifier (extended frame only) ... 30 = arbitration lost in last bit of identifier (extended frame only) 31 = arbitration lost in RTR bit (extended frame only) On arbitration lost, the corresponding arbitration lost interrupt is forced, if enabled. At that time, the current bit position of the Bit Stream Processor is captured into the Arbitration Lost Capture Register. The content within this register is fixed until the user application has read out its contents once. From now on, the capture mechanism is activated again." /> + </Register> + <Register start="+0x010" size="4" name="IER" access="Read/Write" description="Interrupt Enable" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RIE" description="Receiver Interrupt Enable. When the Receive Buffer Status is 'full', the CAN Controller requests the respective interrupt." /> + <BitField start="1" size="1" name="TIE1" description="Transmit Interrupt Enable for Buffer1. When a message has been successfully transmitted out of TXB1 or Transmit Buffer 1 is accessible again (e.g. after an Abort Transmission command), the CAN Controller requests the respective interrupt." /> + <BitField start="2" size="1" name="EIE" description="Error Warning Interrupt Enable. If the Error or Bus Status change (see Status Register), the CAN Controller requests the respective interrupt." /> + <BitField start="3" size="1" name="DOIE" description="Data Overrun Interrupt Enable. If the Data Overrun Status bit is set (see Status Register), the CAN Controller requests the respective interrupt." /> + <BitField start="4" size="1" name="WUIE" description="Wake-Up Interrupt Enable. If the sleeping CAN controller wakes up, the respective interrupt is requested." /> + <BitField start="5" size="1" name="EPIE" description="Error Passive Interrupt Enable. If the error status of the CAN Controller changes from error active to error passive or vice versa, the respective interrupt is requested." /> + <BitField start="6" size="1" name="ALIE" description="Arbitration Lost Interrupt Enable. If the CAN Controller has lost arbitration, the respective interrupt is requested." /> + <BitField start="7" size="1" name="BEIE" description="Bus Error Interrupt Enable. If a bus error has been detected, the CAN Controller requests the respective interrupt." /> + <BitField start="8" size="1" name="IDIE" description="ID Ready Interrupt Enable. When a CAN identifier has been received, the CAN Controller requests the respective interrupt." /> + <BitField start="9" size="1" name="TIE2" description="Transmit Interrupt Enable for Buffer2. When a message has been successfully transmitted out of TXB2 or Transmit Buffer 2 is accessible again (e.g. after an Abort Transmission command), the CAN Controller requests the respective interrupt." /> + <BitField start="10" size="1" name="TIE3" description="Transmit Interrupt Enable for Buffer3. When a message has been successfully transmitted out of TXB3 or Transmit Buffer 3 is accessible again (e.g. after an Abort Transmission command), the CAN Controller requests the respective interrupt." /> + <BitField start="11" size="21" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x014" size="4" name="BTR" access="Read/Write" description="Bus Timing. Can only be written when RM in CANMOD is 1." reset_value="0x1C0000" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="10" name="BRP" description="Baud Rate Prescaler. The APB clock is divided by (this value plus one) to produce the CAN clock." /> + <BitField start="10" size="4" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="14" size="2" name="SJW" description="The Synchronization Jump Width is (this value plus one) CAN clocks." /> + <BitField start="16" size="4" name="TESG1" description="The delay from the nominal Sync point to the sample point is (this value plus one) CAN clocks." /> + <BitField start="20" size="3" name="TESG2" description="The delay from the sample point to the next nominal sync point is (this value plus one) CAN clocks. The nominal CAN bit time is (this value plus the value in TSEG1 plus 3) CAN clocks." /> + <BitField start="23" size="1" name="SAM" description="Sampling"> + <Enum name="THE_BUS_IS_SAMPLED_O" start="0" description="The bus is sampled once (recommended for high speed buses)" /> + <Enum name="THE_BUS_IS_SAMPLED_3" start="1" description="The bus is sampled 3 times (recommended for low to medium speed buses to filter spikes on the bus-line)" /> + </BitField> + <BitField start="24" size="8" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x018" size="4" name="EWL" access="Read/Write" description="Error Warning Limit. Can only be written when RM in CANMOD is 1." reset_value="0x60" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="EWL" description="During CAN operation, this value is compared to both the Tx and Rx Error Counters. If either of these counter matches this value, the Error Status (ES) bit in CANSR is set." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x01C" size="4" name="SR" access="ReadOnly" description="Status Register" reset_value="0x3C3C3C" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RBS_1" description="Receive Buffer Status. This bit is identical to the RBS bit in the CANxGSR." /> + <BitField start="1" size="1" name="DOS_1" description="Data Overrun Status. This bit is identical to the DOS bit in the CANxGSR." /> + <BitField start="2" size="1" name="TBS1_1" description="Transmit Buffer Status 1."> + <Enum name="LOCKED_SOFTWARE_CAN" start="0" description="Locked. Software cannot access the Tx Buffer 1 nor write to the corresponding CANxTFI, CANxTID, CANxTDA, and CANxTDB registers because a message is either waiting for transmission or is in transmitting process." /> + <Enum name="RELEASED_SOFTWARE_M" start="1" description="Released. Software may write a message into the Transmit Buffer 1 and its CANxTFI, CANxTID, CANxTDA, and CANxTDB registers." /> + </BitField> + <BitField start="3" size="1" name="TCS1_1" description="Transmission Complete Status."> + <Enum name="INCOMPLETE_THE_PREV" start="0" description="Incomplete. The previously requested transmission for Tx Buffer 1 is not complete." /> + <Enum name="COMPLETE_THE_PREVIO" start="1" description="Complete. The previously requested transmission for Tx Buffer 1 has been successfully completed." /> + </BitField> + <BitField start="4" size="1" name="RS_1" description="Receive Status. This bit is identical to the RS bit in the GSR." /> + <BitField start="5" size="1" name="TS1_1" description="Transmit Status 1."> + <Enum name="IDLE_THERE_IS_NO_TR" start="0" description="Idle. There is no transmission from Tx Buffer 1." /> + <Enum name="TRANSMIT_THE_CAN_CO" start="1" description="Transmit. The CAN Controller is transmitting a message from Tx Buffer 1." /> + </BitField> + <BitField start="6" size="1" name="ES_1" description="Error Status. This bit is identical to the ES bit in the CANxGSR." /> + <BitField start="7" size="1" name="BS_1" description="Bus Status. This bit is identical to the BS bit in the CANxGSR." /> + <BitField start="8" size="1" name="RBS_2" description="Receive Buffer Status. This bit is identical to the RBS bit in the CANxGSR." /> + <BitField start="9" size="1" name="DOS_2" description="Data Overrun Status. This bit is identical to the DOS bit in the CANxGSR." /> + <BitField start="10" size="1" name="TBS2_2" description="Transmit Buffer Status 2."> + <Enum name="LOCKED_SOFTWARE_CAN" start="0" description="Locked. Software cannot access the Tx Buffer 2 nor write to the corresponding CANxTFI, CANxTID, CANxTDA, and CANxTDB registers because a message is either waiting for transmission or is in transmitting process." /> + <Enum name="RELEASED_SOFTWARE_M" start="1" description="Released. Software may write a message into the Transmit Buffer 2 and its CANxTFI, CANxTID, CANxTDA, and CANxTDB registers." /> + </BitField> + <BitField start="11" size="1" name="TCS2_2" description="Transmission Complete Status."> + <Enum name="INCOMPLETE_THE_PREV" start="0" description="Incomplete. The previously requested transmission for Tx Buffer 2 is not complete." /> + <Enum name="COMPLETE_THE_PREVIO" start="1" description="Complete. The previously requested transmission for Tx Buffer 2 has been successfully completed." /> + </BitField> + <BitField start="12" size="1" name="RS_2" description="Receive Status. This bit is identical to the RS bit in the GSR." /> + <BitField start="13" size="1" name="TS2_2" description="Transmit Status 2."> + <Enum name="IDLE_THERE_IS_NO_TR" start="0" description="Idle. There is no transmission from Tx Buffer 2." /> + <Enum name="TRANSMIT_THE_CAN_CO" start="1" description="Transmit. The CAN Controller is transmitting a message from Tx Buffer 2." /> + </BitField> + <BitField start="14" size="1" name="ES_2" description="Error Status. This bit is identical to the ES bit in the CANxGSR." /> + <BitField start="15" size="1" name="BS_2" description="Bus Status. This bit is identical to the BS bit in the CANxGSR." /> + <BitField start="16" size="1" name="RBS_3" description="Receive Buffer Status. This bit is identical to the RBS bit in the CANxGSR." /> + <BitField start="17" size="1" name="DOS_3" description="Data Overrun Status. This bit is identical to the DOS bit in the CANxGSR." /> + <BitField start="18" size="1" name="TBS3_3" description="Transmit Buffer Status 3."> + <Enum name="LOCKED_SOFTWARE_CAN" start="0" description="Locked. Software cannot access the Tx Buffer 3 nor write to the corresponding CANxTFI, CANxTID, CANxTDA, and CANxTDB registers because a message is either waiting for transmission or is in transmitting process." /> + <Enum name="RELEASED_SOFTWARE_M" start="1" description="Released. Software may write a message into the Transmit Buffer 3 and its CANxTFI, CANxTID, CANxTDA, and CANxTDB registers." /> + </BitField> + <BitField start="19" size="1" name="TCS3_3" description="Transmission Complete Status."> + <Enum name="INCOMPLETE_THE_PREV" start="0" description="Incomplete. The previously requested transmission for Tx Buffer 3 is not complete." /> + <Enum name="COMPLETE_THE_PREVIO" start="1" description="Complete. The previously requested transmission for Tx Buffer 3 has been successfully completed." /> + </BitField> + <BitField start="20" size="1" name="RS_3" description="Receive Status. This bit is identical to the RS bit in the GSR." /> + <BitField start="21" size="1" name="TS3_3" description="Transmit Status 3."> + <Enum name="IDLE_THERE_IS_NO_TR" start="0" description="Idle. There is no transmission from Tx Buffer 3." /> + <Enum name="TRANSMIT_THE_CAN_CO" start="1" description="Transmit. The CAN Controller is transmitting a message from Tx Buffer 3." /> + </BitField> + <BitField start="22" size="1" name="ES_3" description="Error Status. This bit is identical to the ES bit in the CANxGSR." /> + <BitField start="23" size="1" name="BS_3" description="Bus Status. This bit is identical to the BS bit in the CANxGSR." /> + <BitField start="24" size="8" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x020" size="4" name="RFS" access="Read/Write" description="Receive frame status. Can only be written when RM in CANMOD is 1." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="10" name="IDINDEX" description="ID Index. If the BP bit (below) is 0, this value is the zero-based number of the Lookup Table RAM entry at which the Acceptance Filter matched the received Identifier. Disabled entries in the Standard tables are included in this numbering, but will not be matched. See Section 21.17 Examples of acceptance filter tables and ID index values on page 587 for examples of ID Index values." /> + <BitField start="10" size="1" name="BP" description="If this bit is 1, the current message was received in AF Bypass mode, and the ID Index field (above) is meaningless." /> + <BitField start="11" size="5" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + <BitField start="16" size="4" name="DLC" description="The field contains the Data Length Code (DLC) field of the current received message. When RTR = 0, this is related to the number of data bytes available in the CANRDA and CANRDB registers as follows: 0000-0111 = 0 to 7 bytes1000-1111 = 8 bytes With RTR = 1, this value indicates the number of data bytes requested to be sent back, with the same encoding." /> + <BitField start="20" size="10" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="30" size="1" name="RTR" description="This bit contains the Remote Transmission Request bit of the current received message. 0 indicates a Data Frame, in which (if DLC is non-zero) data can be read from the CANRDA and possibly the CANRDB registers. 1 indicates a Remote frame, in which case the DLC value identifies the number of data bytes requested to be sent using the same Identifier." /> + <BitField start="31" size="1" name="FF" description="A 0 in this bit indicates that the current received message included an 11-bit Identifier, while a 1 indicates a 29-bit Identifier. This affects the contents of the CANid register described below." /> + </Register> + <Register start="+0x024" size="4" name="RID" access="Read/Write" description="Received Identifier. Can only be written when RM in CANMOD is 1." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="11" name="ID" description="The 11-bit Identifier field of the current received message. In CAN 2.0A, these bits are called ID10-0, while in CAN 2.0B they're called ID29-18." /> + <BitField start="11" size="21" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x028" size="4" name="RDA" access="Read/Write" description="Received data bytes 1-4. Can only be written when RM in CANMOD is 1." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="DATA1" description="Data 1. If the DLC field in CANRFS >= 0001, this contains the first Data byte of the current received message." /> + <BitField start="8" size="8" name="DATA2" description="Data 2. If the DLC field in CANRFS >= 0010, this contains the first Data byte of the current received message." /> + <BitField start="16" size="8" name="DATA3" description="Data 3. If the DLC field in CANRFS >= 0011, this contains the first Data byte of the current received message." /> + <BitField start="24" size="8" name="DATA4" description="Data 4. If the DLC field in CANRFS >= 0100, this contains the first Data byte of the current received message." /> + </Register> + <Register start="+0x02C" size="4" name="RDB" access="Read/Write" description="Received data bytes 5-8. Can only be written when RM in CANMOD is 1." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="DATA5" description="Data 5. If the DLC field in CANRFS >= 0101, this contains the first Data byte of the current received message." /> + <BitField start="8" size="8" name="DATA6" description="Data 6. If the DLC field in CANRFS >= 0110, this contains the first Data byte of the current received message." /> + <BitField start="16" size="8" name="DATA7" description="Data 7. If the DLC field in CANRFS >= 0111, this contains the first Data byte of the current received message." /> + <BitField start="24" size="8" name="DATA8" description="Data 8. If the DLC field in CANRFS >= 1000, this contains the first Data byte of the current received message." /> + </Register> + <Register start="+0x030+0" size="4" name="TFI1" access="Read/Write" description="Transmit frame info (Tx Buffer )" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="PRIO" description="If the TPM (Transmit Priority Mode) bit in the CANxMOD register is set to 1, enabled Tx Buffers contend for the right to send their messages based on this field. The buffer with the lowest TX Priority value wins the prioritization and is sent first." /> + <BitField start="8" size="8" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="16" size="4" name="DLC" description="Data Length Code. This value is sent in the DLC field of the next transmit message. In addition, if RTR = 0, this value controls the number of Data bytes sent in the next transmit message, from the CANxTDA and CANxTDB registers: 0000-0111 = 0-7 bytes 1xxx = 8 bytes" /> + <BitField start="20" size="10" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="30" size="1" name="RTR" description="This value is sent in the RTR bit of the next transmit message. If this bit is 0, the number of data bytes called out by the DLC field are sent from the CANxTDA and CANxTDB registers. If this bit is 1, a Remote Frame is sent, containing a request for that number of bytes." /> + <BitField start="31" size="1" name="FF" description="If this bit is 0, the next transmit message will be sent with an 11-bit Identifier (standard frame format), while if it's 1, the message will be sent with a 29-bit Identifier (extended frame format)." /> + </Register> + <Register start="+0x030+16" size="4" name="TFI2" access="Read/Write" description="Transmit frame info (Tx Buffer )" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="PRIO" description="If the TPM (Transmit Priority Mode) bit in the CANxMOD register is set to 1, enabled Tx Buffers contend for the right to send their messages based on this field. The buffer with the lowest TX Priority value wins the prioritization and is sent first." /> + <BitField start="8" size="8" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="16" size="4" name="DLC" description="Data Length Code. This value is sent in the DLC field of the next transmit message. In addition, if RTR = 0, this value controls the number of Data bytes sent in the next transmit message, from the CANxTDA and CANxTDB registers: 0000-0111 = 0-7 bytes 1xxx = 8 bytes" /> + <BitField start="20" size="10" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="30" size="1" name="RTR" description="This value is sent in the RTR bit of the next transmit message. If this bit is 0, the number of data bytes called out by the DLC field are sent from the CANxTDA and CANxTDB registers. If this bit is 1, a Remote Frame is sent, containing a request for that number of bytes." /> + <BitField start="31" size="1" name="FF" description="If this bit is 0, the next transmit message will be sent with an 11-bit Identifier (standard frame format), while if it's 1, the message will be sent with a 29-bit Identifier (extended frame format)." /> + </Register> + <Register start="+0x030+32" size="4" name="TFI3" access="Read/Write" description="Transmit frame info (Tx Buffer )" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="PRIO" description="If the TPM (Transmit Priority Mode) bit in the CANxMOD register is set to 1, enabled Tx Buffers contend for the right to send their messages based on this field. The buffer with the lowest TX Priority value wins the prioritization and is sent first." /> + <BitField start="8" size="8" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="16" size="4" name="DLC" description="Data Length Code. This value is sent in the DLC field of the next transmit message. In addition, if RTR = 0, this value controls the number of Data bytes sent in the next transmit message, from the CANxTDA and CANxTDB registers: 0000-0111 = 0-7 bytes 1xxx = 8 bytes" /> + <BitField start="20" size="10" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="30" size="1" name="RTR" description="This value is sent in the RTR bit of the next transmit message. If this bit is 0, the number of data bytes called out by the DLC field are sent from the CANxTDA and CANxTDB registers. If this bit is 1, a Remote Frame is sent, containing a request for that number of bytes." /> + <BitField start="31" size="1" name="FF" description="If this bit is 0, the next transmit message will be sent with an 11-bit Identifier (standard frame format), while if it's 1, the message will be sent with a 29-bit Identifier (extended frame format)." /> + </Register> + <Register start="+0x034+0" size="4" name="TID1" access="Read/Write" description="Transmit
Identifier (Tx Buffer)" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="11" name="ID" description="The 11-bit Identifier to be sent in the next transmit message." /> + <BitField start="11" size="21" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x034+16" size="4" name="TID2" access="Read/Write" description="Transmit
Identifier (Tx Buffer)" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="11" name="ID" description="The 11-bit Identifier to be sent in the next transmit message." /> + <BitField start="11" size="21" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x034+32" size="4" name="TID3" access="Read/Write" description="Transmit
Identifier (Tx Buffer)" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="11" name="ID" description="The 11-bit Identifier to be sent in the next transmit message." /> + <BitField start="11" size="21" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x038+0" size="4" name="TDA1" access="Read/Write" description="Transmit
data bytes 1-4 (Tx Buffer)" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="8" name="DATA1" description="Data 1. If RTR = 0 and DLC >= 0001 in the corresponding CANxTFI, this byte is sent as the first Data byte of the next transmit message." /> + <BitField start="8" size="8" name="DATA2" description="Data 2. If RTR = 0 and DLC >= 0010 in the corresponding CANxTFI, this byte is sent as the 2nd Data byte of the next transmit message." /> + <BitField start="16" size="8" name="DATA3" description="Data 3. If RTR = 0 and DLC >= 0011 in the corresponding CANxTFI, this byte is sent as the 3rd Data byte of the next transmit message." /> + <BitField start="24" size="8" name="DATA4" description="Data 4. If RTR = 0 and DLC >= 0100 in the corresponding CANxTFI, this byte is sent as the 4th Data byte of the next transmit message." /> + </Register> + <Register start="+0x038+16" size="4" name="TDA2" access="Read/Write" description="Transmit
data bytes 1-4 (Tx Buffer)" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="8" name="DATA1" description="Data 1. If RTR = 0 and DLC >= 0001 in the corresponding CANxTFI, this byte is sent as the first Data byte of the next transmit message." /> + <BitField start="8" size="8" name="DATA2" description="Data 2. If RTR = 0 and DLC >= 0010 in the corresponding CANxTFI, this byte is sent as the 2nd Data byte of the next transmit message." /> + <BitField start="16" size="8" name="DATA3" description="Data 3. If RTR = 0 and DLC >= 0011 in the corresponding CANxTFI, this byte is sent as the 3rd Data byte of the next transmit message." /> + <BitField start="24" size="8" name="DATA4" description="Data 4. If RTR = 0 and DLC >= 0100 in the corresponding CANxTFI, this byte is sent as the 4th Data byte of the next transmit message." /> + </Register> + <Register start="+0x038+32" size="4" name="TDA3" access="Read/Write" description="Transmit
data bytes 1-4 (Tx Buffer)" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="8" name="DATA1" description="Data 1. If RTR = 0 and DLC >= 0001 in the corresponding CANxTFI, this byte is sent as the first Data byte of the next transmit message." /> + <BitField start="8" size="8" name="DATA2" description="Data 2. If RTR = 0 and DLC >= 0010 in the corresponding CANxTFI, this byte is sent as the 2nd Data byte of the next transmit message." /> + <BitField start="16" size="8" name="DATA3" description="Data 3. If RTR = 0 and DLC >= 0011 in the corresponding CANxTFI, this byte is sent as the 3rd Data byte of the next transmit message." /> + <BitField start="24" size="8" name="DATA4" description="Data 4. If RTR = 0 and DLC >= 0100 in the corresponding CANxTFI, this byte is sent as the 4th Data byte of the next transmit message." /> + </Register> + <Register start="+0x03C+0" size="4" name="TDB1" access="Read/Write" description="Transmit
data bytes 5-8 (Tx Buffer )" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="8" name="DATA5" description="Data 5. If RTR = 0 and DLC >= 0101 in the corresponding CANTFI, this byte is sent as the 5th Data byte of the next transmit message." /> + <BitField start="8" size="8" name="DATA6" description="Data 6. If RTR = 0 and DLC >= 0110 in the corresponding CANTFI, this byte is sent as the 6th Data byte of the next transmit message." /> + <BitField start="16" size="8" name="DATA7" description="Data 7. If RTR = 0 and DLC >= 0111 in the corresponding CANTFI, this byte is sent as the 7th Data byte of the next transmit message." /> + <BitField start="24" size="8" name="DATA8" description="Data 8. If RTR = 0 and DLC >= 1000 in the corresponding CANTFI, this byte is sent as the 8th Data byte of the next transmit message." /> + </Register> + <Register start="+0x03C+16" size="4" name="TDB2" access="Read/Write" description="Transmit
data bytes 5-8 (Tx Buffer )" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="8" name="DATA5" description="Data 5. If RTR = 0 and DLC >= 0101 in the corresponding CANTFI, this byte is sent as the 5th Data byte of the next transmit message." /> + <BitField start="8" size="8" name="DATA6" description="Data 6. If RTR = 0 and DLC >= 0110 in the corresponding CANTFI, this byte is sent as the 6th Data byte of the next transmit message." /> + <BitField start="16" size="8" name="DATA7" description="Data 7. If RTR = 0 and DLC >= 0111 in the corresponding CANTFI, this byte is sent as the 7th Data byte of the next transmit message." /> + <BitField start="24" size="8" name="DATA8" description="Data 8. If RTR = 0 and DLC >= 1000 in the corresponding CANTFI, this byte is sent as the 8th Data byte of the next transmit message." /> + </Register> + <Register start="+0x03C+32" size="4" name="TDB3" access="Read/Write" description="Transmit
data bytes 5-8 (Tx Buffer )" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="8" name="DATA5" description="Data 5. If RTR = 0 and DLC >= 0101 in the corresponding CANTFI, this byte is sent as the 5th Data byte of the next transmit message." /> + <BitField start="8" size="8" name="DATA6" description="Data 6. If RTR = 0 and DLC >= 0110 in the corresponding CANTFI, this byte is sent as the 6th Data byte of the next transmit message." /> + <BitField start="16" size="8" name="DATA7" description="Data 7. If RTR = 0 and DLC >= 0111 in the corresponding CANTFI, this byte is sent as the 7th Data byte of the next transmit message." /> + <BitField start="24" size="8" name="DATA8" description="Data 8. If RTR = 0 and DLC >= 1000 in the corresponding CANTFI, this byte is sent as the 8th Data byte of the next transmit message." /> + </Register> + </RegisterGroup> + <RegisterGroup name="CAN2" start="0x40048000" description="CAN controller "> + <Register start="+0x000" size="4" name="MOD" access="Read/Write" description="Controls the operating mode of the CAN Controller." reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="RM" description="Reset Mode."> + <Enum name="NORMAL_THE_CAN_CONTR" start="0" description="Normal.The CAN Controller is in the Operating Mode, and certain registers can not be written." /> + <Enum name="RESET_CAN_OPERATION" start="1" description="Reset. CAN operation is disabled, writable registers can be written and the current transmission/reception of a message is aborted." /> + </BitField> + <BitField start="1" size="1" name="LOM" description="Listen Only Mode."> + <Enum name="NORMAL_THE_CAN_CONT" start="0" description="Normal. The CAN controller acknowledges a successfully received message on the CAN bus. The error counters are stopped at the current value." /> + <Enum name="LISTEN_ONLY_THE_CON" start="1" description="Listen only. The controller gives no acknowledgment, even if a message is successfully received. Messages cannot be sent, and the controller operates in error passive mode. This mode is intended for software bit rate detection and hot plugging." /> + </BitField> + <BitField start="2" size="1" name="STM" description="Self Test Mode."> + <Enum name="NORMAL_A_TRANSMITTE" start="0" description="Normal. A transmitted message must be acknowledged to be considered successful." /> + <Enum name="SELF_TEST_THE_CONTR" start="1" description="Self test. The controller will consider a Tx message successful even if there is no acknowledgment received. In this mode a full node test is possible without any other active node on the bus using the SRR bit in CANxCMR." /> + </BitField> + <BitField start="3" size="1" name="TPM" description="Transmit Priority Mode."> + <Enum name="CAN_ID_THE_TRANSMIT" start="0" description="CAN ID. The transmit priority for 3 Transmit Buffers depends on the CAN Identifier." /> + <Enum name="LOCAL_PRIORITY_THE_" start="1" description="Local priority. The transmit priority for 3 Transmit Buffers depends on the contents of the Tx Priority register within the Transmit Buffer." /> + </BitField> + <BitField start="4" size="1" name="SM" description="Sleep Mode."> + <Enum name="WAKE_UP_NORMAL_OPER" start="0" description="Wake-up. Normal operation." /> + <Enum name="SLEEP_THE_CAN_CONTR" start="1" description="Sleep. The CAN controller enters Sleep Mode if no CAN interrupt is pending and there is no bus activity. See the Sleep Mode description Section 21.8.2 on page 565." /> + </BitField> + <BitField start="5" size="1" name="RPM" description="Receive Polarity Mode."> + <Enum name="LOW_ACTIVE_RD_INPUT" start="0" description="Low active. RD input is active Low (dominant bit = 0)." /> + <Enum name="HIGH_ACTIVE_RD_INPU" start="1" description="High active. RD input is active High (dominant bit = 1) -- reverse polarity." /> + </BitField> + <BitField start="6" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="7" size="1" name="TM" description="Test Mode."> + <Enum name="DISABLED_NORMAL_OPE" start="0" description="Disabled. Normal operation." /> + <Enum name="ENABLED_THE_TD_PIN_" start="1" description="Enabled. The TD pin will reflect the bit, detected on RD pin, with the next positive edge of the system clock." /> + </BitField> + <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x004" size="4" name="CMR" access="WriteOnly" description="Command bits that affect the state of the CAN Controller" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="TR" description="Transmission Request."> + <Enum name="ABSENT_NO_TRANSMISSI" start="0" description="Absent.No transmission request." /> + <Enum name="PRESENT_THE_MESSAGE" start="1" description="Present. The message, previously written to the CANxTFI, CANxTID, and optionally the CANxTDA and CANxTDB registers, is queued for transmission from the selected Transmit Buffer. If at two or all three of STB1, STB2 and STB3 bits are selected when TR=1 is written, Transmit Buffer will be selected based on the chosen priority scheme (for details see Section 21.5.3 Transmit Buffers (TXB))" /> + </BitField> + <BitField start="1" size="1" name="AT" description="Abort Transmission."> + <Enum name="NO_ACTION_DO_NOT_AB" start="0" description="No action. Do not abort the transmission." /> + <Enum name="PRESENT_IF_NOT_ALRE" start="1" description="Present. if not already in progress, a pending Transmission Request for the selected Transmit Buffer is cancelled." /> + </BitField> + <BitField start="2" size="1" name="RRB" description="Release Receive Buffer."> + <Enum name="NO_ACTION_DO_NOT_RE" start="0" description="No action. Do not release the receive buffer." /> + <Enum name="RELEASED_THE_INFORM" start="1" description="Released. The information in the Receive Buffer (consisting of CANxRFS, CANxRID, and if applicable the CANxRDA and CANxRDB registers) is released, and becomes eligible for replacement by the next received frame. If the next received frame is not available, writing this command clears the RBS bit in the Status Register(s)." /> + </BitField> + <BitField start="3" size="1" name="CDO" description="Clear Data Overrun."> + <Enum name="NO_ACTION_DO_NOT_CL" start="0" description="No action. Do not clear the data overrun bit." /> + <Enum name="CLEAR_THE_DATA_OVER" start="1" description="Clear. The Data Overrun bit in Status Register(s) is cleared." /> + </BitField> + <BitField start="4" size="1" name="SRR" description="Self Reception Request."> + <Enum name="ABSENT_NO_SELF_RECE" start="0" description="Absent. No self reception request." /> + <Enum name="PRESENT_THE_MESSAGE" start="1" description="Present. The message, previously written to the CANxTFS, CANxTID, and optionally the CANxTDA and CANxTDB registers, is queued for transmission from the selected Transmit Buffer and received simultaneously. This differs from the TR bit above in that the receiver is not disabled during the transmission, so that it receives the message if its Identifier is recognized by the Acceptance Filter." /> + </BitField> + <BitField start="5" size="1" name="STB1" description="Select Tx Buffer 1."> + <Enum name="NOT_SELECTED_TX_BUF" start="0" description="Not selected. Tx Buffer 1 is not selected for transmission." /> + <Enum name="SELECTED_TX_BUFFER_" start="1" description="Selected. Tx Buffer 1 is selected for transmission." /> + </BitField> + <BitField start="6" size="1" name="STB2" description="Select Tx Buffer 2."> + <Enum name="NOT_SELECTED_TX_BUF" start="0" description="Not selected. Tx Buffer 2 is not selected for transmission." /> + <Enum name="SELECTED_TX_BUFFER_" start="1" description="Selected. Tx Buffer 2 is selected for transmission." /> + </BitField> + <BitField start="7" size="1" name="STB3" description="Select Tx Buffer 3."> + <Enum name="NOT_SELECTED_TX_BUF" start="0" description="Not selected. Tx Buffer 3 is not selected for transmission." /> + <Enum name="SELECTED_TX_BUFFER_" start="1" description="Selected. Tx Buffer 3 is selected for transmission." /> + </BitField> + <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x008" size="4" name="GSR" access="ReadOnly" description="Global Controller Status and Error Counters. The error counters can only be written when RM in CANMOD is 1." reset_value="0x3C" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RBS" description="Receive Buffer Status. After reading all messages and releasing their memory space with the command 'Release Receive Buffer,' this bit is cleared."> + <Enum name="EMPTY_NO_MESSAGE_IS" start="0" description="Empty. No message is available." /> + <Enum name="FULL_AT_LEAST_ONE_C" start="1" description="Full. At least one complete message is received by the Double Receive Buffer and available in the CANxRFS, CANxRID, and if applicable the CANxRDA and CANxRDB registers. This bit is cleared by the Release Receive Buffer command in CANxCMR, if no subsequent received message is available." /> + </BitField> + <BitField start="1" size="1" name="DOS" description="Data Overrun Status. If there is not enough space to store the message within the Receive Buffer, that message is dropped and the Data Overrun condition is signalled to the CPU in the moment this message becomes valid. If this message is not completed successfully (e.g. because of an error), no overrun condition is signalled."> + <Enum name="ABSENT_NO_DATA_OVER" start="0" description="Absent. No data overrun has occurred since the last Clear Data Overrun command was given/written to CANxCMR (or since Reset)." /> + <Enum name="OVERRUN_A_MESSAGE_W" start="1" description="Overrun. A message was lost because the preceding message to this CAN controller was not read and released quickly enough (there was not enough space for a new message in the Double Receive Buffer)." /> + </BitField> + <BitField start="2" size="1" name="TBS" description="Transmit Buffer Status."> + <Enum name="LOCKED_AT_LEAST_ONE" start="0" description="Locked. At least one of the Transmit Buffers is not available for the CPU, i.e. at least one previously queued message for this CAN controller has not yet been sent, and therefore software should not write to the CANxTFI, CANxTID, CANxTDA, nor CANxTDB registers of that (those) Tx buffer(s)." /> + <Enum name="RELEASED_ALL_THREE_" start="1" description="Released. All three Transmit Buffers are available for the CPU. No transmit message is pending for this CAN controller (in any of the 3 Tx buffers), and software may write to any of the CANxTFI, CANxTID, CANxTDA, and CANxTDB registers." /> + </BitField> + <BitField start="3" size="1" name="TCS" description="Transmit Complete Status. The Transmission Complete Status bit is set '0' (incomplete) whenever the Transmission Request bit or the Self Reception Request bit is set '1' at least for one of the three Transmit Buffers. The Transmission Complete Status bit will remain '0' until all messages are transmitted successfully."> + <Enum name="INCOMPLETE_AT_LEAST" start="0" description="Incomplete. At least one requested transmission has not been successfully completed yet." /> + <Enum name="COMPLETE_ALL_REQUES" start="1" description="Complete. All requested transmission(s) has (have) been successfully completed." /> + </BitField> + <BitField start="4" size="1" name="RS" description="Receive Status. If both the Receive Status and the Transmit Status bits are '0' (idle), the CAN-Bus is idle. If both bits are set, the controller is waiting to become idle again. After hardware reset 11 consecutive recessive bits have to be detected until idle status is reached. After Bus-off this will take 128 times of 11 consecutive recessive bits."> + <Enum name="IDLE_THE_CAN_CONTRO" start="0" description="Idle. The CAN controller is idle." /> + <Enum name="RECEIVE_THE_CAN_CON" start="1" description="Receive. The CAN controller is receiving a message." /> + </BitField> + <BitField start="5" size="1" name="TS" description="Transmit Status. If both the Receive Status and the Transmit Status bits are '0' (idle), the CAN-Bus is idle. If both bits are set, the controller is waiting to become idle again. After hardware reset 11 consecutive recessive bits have to be detected until idle status is reached. After Bus-off this will take 128 times of 11 consecutive recessive bits."> + <Enum name="IDLE_THE_CAN_CONTRO" start="0" description="Idle. The CAN controller is idle." /> + <Enum name="TRANSMIT_THE_CAN_CO" start="1" description="Transmit. The CAN controller is sending a message." /> + </BitField> + <BitField start="6" size="1" name="ES" description="Error Status. Errors detected during reception or transmission will effect the error counters according to the CAN specification. The Error Status bit is set when at least one of the error counters has reached or exceeded the Error Warning Limit. An Error Warning Interrupt is generated, if enabled. The default value of the Error Warning Limit after hardware reset is 96 decimal, see also Section 21.7.7 CAN Error Warning Limit register (CAN1EWL - 0x4004 4018, CAN2EWL - 0x4004 8018)."> + <Enum name="OK_BOTH_ERROR_COUNT" start="0" description="OK. Both error counters are below the Error Warning Limit." /> + <Enum name="ERROR_ONE_OR_BOTH_O" start="1" description="Error. One or both of the Transmit and Receive Error Counters has reached the limit set in the Error Warning Limit register." /> + </BitField> + <BitField start="7" size="1" name="BS" description="Bus Status. Mode bit '1' (present) and an Error Warning Interrupt is generated, if enabled. Afterwards the Transmit Error Counter is set to '127', and the Receive Error Counter is cleared. It will stay in this mode until the CPU clears the Reset Mode bit. Once this is completed the CAN Controller will wait the minimum protocol-defined time (128 occurrences of the Bus-Free signal) counting down the Transmit Error Counter. After that, the Bus Status bit is cleared (Bus-On), the Error Status bit is set '0' (ok), the Error Counters are reset, and an Error Warning Interrupt is generated, if enabled. Reading the TX Error Counter during this time gives information about the status of the Bus-Off recovery."> + <Enum name="BUS_ON_THE_CAN_CONT" start="0" description="Bus-on. The CAN Controller is involved in bus activities" /> + <Enum name="BUS_OFF_THE_CAN_CON" start="1" description="Bus-off. The CAN controller is currently not involved/prohibited from bus activity because the Transmit Error Counter reached its limiting value of 255." /> + </BitField> + <BitField start="8" size="8" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="16" size="8" name="RXERR" description="The current value of the Rx Error Counter (an 8-bit value)." /> + <BitField start="24" size="8" name="TXERR" description="The current value of the Tx Error Counter (an 8-bit value)." /> + </Register> + <Register start="+0x00C" size="4" name="ICR" access="ReadOnly" description="Interrupt status, Arbitration Lost Capture, Error Code Capture" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RI" description="Receive Interrupt. This bit is set whenever the RBS bit in CANxSR and the RIE bit in CANxIER are both 1, indicating that a new message was received and stored in the Receive Buffer. The Receive Interrupt Bit is not cleared upon a read access to the Interrupt Register. Giving the Command Release Receive Buffer will clear RI temporarily. If there is another message available within the Receive Buffer after the release command, RI is set again. Otherwise RI remains cleared."> + <Enum name="RESET" start="0" description="Reset" /> + <Enum name="SET" start="1" description="Set" /> + </BitField> + <BitField start="1" size="1" name="TI1" description="Transmit Interrupt 1. This bit is set when the TBS1 bit in CANxSR goes from 0 to 1 (whenever a message out of TXB1 was successfully transmitted or aborted), indicating that Transmit buffer 1 is available, and the TIE1 bit in CANxIER is 1."> + <Enum name="RESET" start="0" description="Reset" /> + <Enum name="SET" start="1" description="Set" /> + </BitField> + <BitField start="2" size="1" name="EI" description="Error Warning Interrupt. This bit is set on every change (set or clear) of either the Error Status or Bus Status bit in CANxSR and the EIE bit bit is set within the Interrupt Enable Register at the time of the change."> + <Enum name="RESET" start="0" description="Reset" /> + <Enum name="SET" start="1" description="Set" /> + </BitField> + <BitField start="3" size="1" name="DOI" description="Data Overrun Interrupt. This bit is set when the DOS bit in CANxSR goes from 0 to 1 and the DOIE bit in CANxIER is 1."> + <Enum name="RESET" start="0" description="Reset" /> + <Enum name="SET" start="1" description="Set" /> + </BitField> + <BitField start="4" size="1" name="WUI" description="Wake-Up Interrupt. This bit is set if the CAN controller is sleeping and bus activity is detected and the WUIE bit in CANxIER is 1. A Wake-Up Interrupt is also generated if the CPU tries to set the Sleep bit while the CAN controller is involved in bus activities or a CAN Interrupt is pending. The WUI flag can also get asserted when the according enable bit WUIE is not set. In this case a Wake-Up Interrupt does not get asserted."> + <Enum name="RESET" start="0" description="Reset" /> + <Enum name="SET" start="1" description="Set" /> + </BitField> + <BitField start="5" size="1" name="EPI" description="Error Passive Interrupt. This bit is set if the EPIE bit in CANxIER is 1, and the CAN controller switches between Error Passive and Error Active mode in either direction. This is the case when the CAN Controller has reached the Error Passive Status (at least one error counter exceeds the CAN protocol defined level of 127) or if the CAN Controller is in Error Passive Status and enters the Error Active Status again."> + <Enum name="RESET" start="0" description="Reset" /> + <Enum name="SET" start="1" description="Set" /> + </BitField> + <BitField start="6" size="1" name="ALI" description="Arbitration Lost Interrupt. This bit is set if the ALIE bit in CANxIER is 1, and the CAN controller loses arbitration while attempting to transmit. In this case the CAN node becomes a receiver."> + <Enum name="RESET" start="0" description="Reset" /> + <Enum name="SET" start="1" description="Set" /> + </BitField> + <BitField start="7" size="1" name="BEI" description="Bus Error Interrupt -- this bit is set if the BEIE bit in CANxIER is 1, and the CAN controller detects an error on the bus."> + <Enum name="RESET" start="0" description="Reset" /> + <Enum name="SET" start="1" description="Set" /> + </BitField> + <BitField start="8" size="1" name="IDI" description="ID Ready Interrupt -- this bit is set if the IDIE bit in CANxIER is 1, and a CAN Identifier has been received (a message was successfully transmitted or aborted). This bit is set whenever a message was successfully transmitted or aborted and the IDIE bit is set in the IER register."> + <Enum name="RESET" start="0" description="Reset" /> + <Enum name="SET" start="1" description="Set" /> + </BitField> + <BitField start="9" size="1" name="TI2" description="Transmit Interrupt 2. This bit is set when the TBS2 bit in CANxSR goes from 0 to 1 (whenever a message out of TXB2 was successfully transmitted or aborted), indicating that Transmit buffer 2 is available, and the TIE2 bit in CANxIER is 1."> + <Enum name="RESET" start="0" description="Reset" /> + <Enum name="SET" start="1" description="Set" /> + </BitField> + <BitField start="10" size="1" name="TI3" description="Transmit Interrupt 3. This bit is set when the TBS3 bit in CANxSR goes from 0 to 1 (whenever a message out of TXB3 was successfully transmitted or aborted), indicating that Transmit buffer 3 is available, and the TIE3 bit in CANxIER is 1."> + <Enum name="RESET" start="0" description="Reset" /> + <Enum name="SET" start="1" description="Set" /> + </BitField> + <BitField start="11" size="5" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + <BitField start="16" size="5" name="ERRBIT4_0" description="Error Code Capture: when the CAN controller detects a bus error, the location of the error within the frame is captured in this field. The value reflects an internal state variable, and as a result is not very linear: 00011 = Start of Frame 00010 = ID28 ... ID21 00110 = ID20 ... ID18 00100 = SRTR Bit 00101 = IDE bit 00111 = ID17 ... 13 01111 = ID12 ... ID5 01110 = ID4 ... ID0 01100 = RTR Bit 01101 = Reserved Bit 1 01001 = Reserved Bit 0 01011 = Data Length Code 01010 = Data Field 01000 = CRC Sequence 11000 = CRC Delimiter 11001 = Acknowledge Slot 11011 = Acknowledge Delimiter 11010 = End of Frame 10010 = Intermission Whenever a bus error occurs, the corresponding bus error interrupt is forced, if enabled. At the same time, the current position of the Bit Stream Processor is captured into the Error Code Capture Register. The content within this register is fixed until the user software has read out its content once. From now on, the capture mechanism is activated again, i.e. reading the CANxICR enables another Bus Error Interrupt." /> + <BitField start="21" size="1" name="ERRDIR" description="When the CAN controller detects a bus error, the direction of the current bit is captured in this bit."> + <Enum name="ERROR_OCCURRED_DURIN" start="0" description="Error occurred during transmitting." /> + <Enum name="ERROR_OCCURRED_DURIN" start="1" description="Error occurred during receiving." /> + </BitField> + <BitField start="22" size="2" name="ERRC1_0" description="When the CAN controller detects a bus error, the type of error is captured in this field:"> + <Enum name="BIT_ERROR" start="0x0" description="Bit error" /> + <Enum name="FORM_ERROR" start="0x1" description="Form error" /> + <Enum name="STUFF_ERROR" start="0x2" description="Stuff error" /> + <Enum name="OTHER_ERROR" start="0x3" description="Other error" /> + </BitField> + <BitField start="24" size="8" name="ALCBIT" description="Each time arbitration is lost while trying to send on the CAN, the bit number within the frame is captured into this field. After the content of ALCBIT is read, the ALI bit is cleared and a new Arbitration Lost interrupt can occur. 00 = arbitration lost in the first bit (MS) of identifier ... 11 = arbitration lost in SRTS bit (RTR bit for standard frame messages) 12 = arbitration lost in IDE bit 13 = arbitration lost in 12th bit of identifier (extended frame only) ... 30 = arbitration lost in last bit of identifier (extended frame only) 31 = arbitration lost in RTR bit (extended frame only) On arbitration lost, the corresponding arbitration lost interrupt is forced, if enabled. At that time, the current bit position of the Bit Stream Processor is captured into the Arbitration Lost Capture Register. The content within this register is fixed until the user application has read out its contents once. From now on, the capture mechanism is activated again." /> + </Register> + <Register start="+0x010" size="4" name="IER" access="Read/Write" description="Interrupt Enable" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RIE" description="Receiver Interrupt Enable. When the Receive Buffer Status is 'full', the CAN Controller requests the respective interrupt." /> + <BitField start="1" size="1" name="TIE1" description="Transmit Interrupt Enable for Buffer1. When a message has been successfully transmitted out of TXB1 or Transmit Buffer 1 is accessible again (e.g. after an Abort Transmission command), the CAN Controller requests the respective interrupt." /> + <BitField start="2" size="1" name="EIE" description="Error Warning Interrupt Enable. If the Error or Bus Status change (see Status Register), the CAN Controller requests the respective interrupt." /> + <BitField start="3" size="1" name="DOIE" description="Data Overrun Interrupt Enable. If the Data Overrun Status bit is set (see Status Register), the CAN Controller requests the respective interrupt." /> + <BitField start="4" size="1" name="WUIE" description="Wake-Up Interrupt Enable. If the sleeping CAN controller wakes up, the respective interrupt is requested." /> + <BitField start="5" size="1" name="EPIE" description="Error Passive Interrupt Enable. If the error status of the CAN Controller changes from error active to error passive or vice versa, the respective interrupt is requested." /> + <BitField start="6" size="1" name="ALIE" description="Arbitration Lost Interrupt Enable. If the CAN Controller has lost arbitration, the respective interrupt is requested." /> + <BitField start="7" size="1" name="BEIE" description="Bus Error Interrupt Enable. If a bus error has been detected, the CAN Controller requests the respective interrupt." /> + <BitField start="8" size="1" name="IDIE" description="ID Ready Interrupt Enable. When a CAN identifier has been received, the CAN Controller requests the respective interrupt." /> + <BitField start="9" size="1" name="TIE2" description="Transmit Interrupt Enable for Buffer2. When a message has been successfully transmitted out of TXB2 or Transmit Buffer 2 is accessible again (e.g. after an Abort Transmission command), the CAN Controller requests the respective interrupt." /> + <BitField start="10" size="1" name="TIE3" description="Transmit Interrupt Enable for Buffer3. When a message has been successfully transmitted out of TXB3 or Transmit Buffer 3 is accessible again (e.g. after an Abort Transmission command), the CAN Controller requests the respective interrupt." /> + <BitField start="11" size="21" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x014" size="4" name="BTR" access="Read/Write" description="Bus Timing. Can only be written when RM in CANMOD is 1." reset_value="0x1C0000" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="10" name="BRP" description="Baud Rate Prescaler. The APB clock is divided by (this value plus one) to produce the CAN clock." /> + <BitField start="10" size="4" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="14" size="2" name="SJW" description="The Synchronization Jump Width is (this value plus one) CAN clocks." /> + <BitField start="16" size="4" name="TESG1" description="The delay from the nominal Sync point to the sample point is (this value plus one) CAN clocks." /> + <BitField start="20" size="3" name="TESG2" description="The delay from the sample point to the next nominal sync point is (this value plus one) CAN clocks. The nominal CAN bit time is (this value plus the value in TSEG1 plus 3) CAN clocks." /> + <BitField start="23" size="1" name="SAM" description="Sampling"> + <Enum name="THE_BUS_IS_SAMPLED_O" start="0" description="The bus is sampled once (recommended for high speed buses)" /> + <Enum name="THE_BUS_IS_SAMPLED_3" start="1" description="The bus is sampled 3 times (recommended for low to medium speed buses to filter spikes on the bus-line)" /> + </BitField> + <BitField start="24" size="8" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x018" size="4" name="EWL" access="Read/Write" description="Error Warning Limit. Can only be written when RM in CANMOD is 1." reset_value="0x60" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="EWL" description="During CAN operation, this value is compared to both the Tx and Rx Error Counters. If either of these counter matches this value, the Error Status (ES) bit in CANSR is set." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x01C" size="4" name="SR" access="ReadOnly" description="Status Register" reset_value="0x3C3C3C" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RBS_1" description="Receive Buffer Status. This bit is identical to the RBS bit in the CANxGSR." /> + <BitField start="1" size="1" name="DOS_1" description="Data Overrun Status. This bit is identical to the DOS bit in the CANxGSR." /> + <BitField start="2" size="1" name="TBS1_1" description="Transmit Buffer Status 1."> + <Enum name="LOCKED_SOFTWARE_CAN" start="0" description="Locked. Software cannot access the Tx Buffer 1 nor write to the corresponding CANxTFI, CANxTID, CANxTDA, and CANxTDB registers because a message is either waiting for transmission or is in transmitting process." /> + <Enum name="RELEASED_SOFTWARE_M" start="1" description="Released. Software may write a message into the Transmit Buffer 1 and its CANxTFI, CANxTID, CANxTDA, and CANxTDB registers." /> + </BitField> + <BitField start="3" size="1" name="TCS1_1" description="Transmission Complete Status."> + <Enum name="INCOMPLETE_THE_PREV" start="0" description="Incomplete. The previously requested transmission for Tx Buffer 1 is not complete." /> + <Enum name="COMPLETE_THE_PREVIO" start="1" description="Complete. The previously requested transmission for Tx Buffer 1 has been successfully completed." /> + </BitField> + <BitField start="4" size="1" name="RS_1" description="Receive Status. This bit is identical to the RS bit in the GSR." /> + <BitField start="5" size="1" name="TS1_1" description="Transmit Status 1."> + <Enum name="IDLE_THERE_IS_NO_TR" start="0" description="Idle. There is no transmission from Tx Buffer 1." /> + <Enum name="TRANSMIT_THE_CAN_CO" start="1" description="Transmit. The CAN Controller is transmitting a message from Tx Buffer 1." /> + </BitField> + <BitField start="6" size="1" name="ES_1" description="Error Status. This bit is identical to the ES bit in the CANxGSR." /> + <BitField start="7" size="1" name="BS_1" description="Bus Status. This bit is identical to the BS bit in the CANxGSR." /> + <BitField start="8" size="1" name="RBS_2" description="Receive Buffer Status. This bit is identical to the RBS bit in the CANxGSR." /> + <BitField start="9" size="1" name="DOS_2" description="Data Overrun Status. This bit is identical to the DOS bit in the CANxGSR." /> + <BitField start="10" size="1" name="TBS2_2" description="Transmit Buffer Status 2."> + <Enum name="LOCKED_SOFTWARE_CAN" start="0" description="Locked. Software cannot access the Tx Buffer 2 nor write to the corresponding CANxTFI, CANxTID, CANxTDA, and CANxTDB registers because a message is either waiting for transmission or is in transmitting process." /> + <Enum name="RELEASED_SOFTWARE_M" start="1" description="Released. Software may write a message into the Transmit Buffer 2 and its CANxTFI, CANxTID, CANxTDA, and CANxTDB registers." /> + </BitField> + <BitField start="11" size="1" name="TCS2_2" description="Transmission Complete Status."> + <Enum name="INCOMPLETE_THE_PREV" start="0" description="Incomplete. The previously requested transmission for Tx Buffer 2 is not complete." /> + <Enum name="COMPLETE_THE_PREVIO" start="1" description="Complete. The previously requested transmission for Tx Buffer 2 has been successfully completed." /> + </BitField> + <BitField start="12" size="1" name="RS_2" description="Receive Status. This bit is identical to the RS bit in the GSR." /> + <BitField start="13" size="1" name="TS2_2" description="Transmit Status 2."> + <Enum name="IDLE_THERE_IS_NO_TR" start="0" description="Idle. There is no transmission from Tx Buffer 2." /> + <Enum name="TRANSMIT_THE_CAN_CO" start="1" description="Transmit. The CAN Controller is transmitting a message from Tx Buffer 2." /> + </BitField> + <BitField start="14" size="1" name="ES_2" description="Error Status. This bit is identical to the ES bit in the CANxGSR." /> + <BitField start="15" size="1" name="BS_2" description="Bus Status. This bit is identical to the BS bit in the CANxGSR." /> + <BitField start="16" size="1" name="RBS_3" description="Receive Buffer Status. This bit is identical to the RBS bit in the CANxGSR." /> + <BitField start="17" size="1" name="DOS_3" description="Data Overrun Status. This bit is identical to the DOS bit in the CANxGSR." /> + <BitField start="18" size="1" name="TBS3_3" description="Transmit Buffer Status 3."> + <Enum name="LOCKED_SOFTWARE_CAN" start="0" description="Locked. Software cannot access the Tx Buffer 3 nor write to the corresponding CANxTFI, CANxTID, CANxTDA, and CANxTDB registers because a message is either waiting for transmission or is in transmitting process." /> + <Enum name="RELEASED_SOFTWARE_M" start="1" description="Released. Software may write a message into the Transmit Buffer 3 and its CANxTFI, CANxTID, CANxTDA, and CANxTDB registers." /> + </BitField> + <BitField start="19" size="1" name="TCS3_3" description="Transmission Complete Status."> + <Enum name="INCOMPLETE_THE_PREV" start="0" description="Incomplete. The previously requested transmission for Tx Buffer 3 is not complete." /> + <Enum name="COMPLETE_THE_PREVIO" start="1" description="Complete. The previously requested transmission for Tx Buffer 3 has been successfully completed." /> + </BitField> + <BitField start="20" size="1" name="RS_3" description="Receive Status. This bit is identical to the RS bit in the GSR." /> + <BitField start="21" size="1" name="TS3_3" description="Transmit Status 3."> + <Enum name="IDLE_THERE_IS_NO_TR" start="0" description="Idle. There is no transmission from Tx Buffer 3." /> + <Enum name="TRANSMIT_THE_CAN_CO" start="1" description="Transmit. The CAN Controller is transmitting a message from Tx Buffer 3." /> + </BitField> + <BitField start="22" size="1" name="ES_3" description="Error Status. This bit is identical to the ES bit in the CANxGSR." /> + <BitField start="23" size="1" name="BS_3" description="Bus Status. This bit is identical to the BS bit in the CANxGSR." /> + <BitField start="24" size="8" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x020" size="4" name="RFS" access="Read/Write" description="Receive frame status. Can only be written when RM in CANMOD is 1." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="10" name="IDINDEX" description="ID Index. If the BP bit (below) is 0, this value is the zero-based number of the Lookup Table RAM entry at which the Acceptance Filter matched the received Identifier. Disabled entries in the Standard tables are included in this numbering, but will not be matched. See Section 21.17 Examples of acceptance filter tables and ID index values on page 587 for examples of ID Index values." /> + <BitField start="10" size="1" name="BP" description="If this bit is 1, the current message was received in AF Bypass mode, and the ID Index field (above) is meaningless." /> + <BitField start="11" size="5" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + <BitField start="16" size="4" name="DLC" description="The field contains the Data Length Code (DLC) field of the current received message. When RTR = 0, this is related to the number of data bytes available in the CANRDA and CANRDB registers as follows: 0000-0111 = 0 to 7 bytes1000-1111 = 8 bytes With RTR = 1, this value indicates the number of data bytes requested to be sent back, with the same encoding." /> + <BitField start="20" size="10" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="30" size="1" name="RTR" description="This bit contains the Remote Transmission Request bit of the current received message. 0 indicates a Data Frame, in which (if DLC is non-zero) data can be read from the CANRDA and possibly the CANRDB registers. 1 indicates a Remote frame, in which case the DLC value identifies the number of data bytes requested to be sent using the same Identifier." /> + <BitField start="31" size="1" name="FF" description="A 0 in this bit indicates that the current received message included an 11-bit Identifier, while a 1 indicates a 29-bit Identifier. This affects the contents of the CANid register described below." /> + </Register> + <Register start="+0x024" size="4" name="RID" access="Read/Write" description="Received Identifier. Can only be written when RM in CANMOD is 1." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="11" name="ID" description="The 11-bit Identifier field of the current received message. In CAN 2.0A, these bits are called ID10-0, while in CAN 2.0B they're called ID29-18." /> + <BitField start="11" size="21" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x028" size="4" name="RDA" access="Read/Write" description="Received data bytes 1-4. Can only be written when RM in CANMOD is 1." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="DATA1" description="Data 1. If the DLC field in CANRFS >= 0001, this contains the first Data byte of the current received message." /> + <BitField start="8" size="8" name="DATA2" description="Data 2. If the DLC field in CANRFS >= 0010, this contains the first Data byte of the current received message." /> + <BitField start="16" size="8" name="DATA3" description="Data 3. If the DLC field in CANRFS >= 0011, this contains the first Data byte of the current received message." /> + <BitField start="24" size="8" name="DATA4" description="Data 4. If the DLC field in CANRFS >= 0100, this contains the first Data byte of the current received message." /> + </Register> + <Register start="+0x02C" size="4" name="RDB" access="Read/Write" description="Received data bytes 5-8. Can only be written when RM in CANMOD is 1." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="DATA5" description="Data 5. If the DLC field in CANRFS >= 0101, this contains the first Data byte of the current received message." /> + <BitField start="8" size="8" name="DATA6" description="Data 6. If the DLC field in CANRFS >= 0110, this contains the first Data byte of the current received message." /> + <BitField start="16" size="8" name="DATA7" description="Data 7. If the DLC field in CANRFS >= 0111, this contains the first Data byte of the current received message." /> + <BitField start="24" size="8" name="DATA8" description="Data 8. If the DLC field in CANRFS >= 1000, this contains the first Data byte of the current received message." /> + </Register> + <Register start="+0x030+0" size="4" name="TFI1" access="Read/Write" description="Transmit frame info (Tx Buffer )" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="PRIO" description="If the TPM (Transmit Priority Mode) bit in the CANxMOD register is set to 1, enabled Tx Buffers contend for the right to send their messages based on this field. The buffer with the lowest TX Priority value wins the prioritization and is sent first." /> + <BitField start="8" size="8" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="16" size="4" name="DLC" description="Data Length Code. This value is sent in the DLC field of the next transmit message. In addition, if RTR = 0, this value controls the number of Data bytes sent in the next transmit message, from the CANxTDA and CANxTDB registers: 0000-0111 = 0-7 bytes 1xxx = 8 bytes" /> + <BitField start="20" size="10" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="30" size="1" name="RTR" description="This value is sent in the RTR bit of the next transmit message. If this bit is 0, the number of data bytes called out by the DLC field are sent from the CANxTDA and CANxTDB registers. If this bit is 1, a Remote Frame is sent, containing a request for that number of bytes." /> + <BitField start="31" size="1" name="FF" description="If this bit is 0, the next transmit message will be sent with an 11-bit Identifier (standard frame format), while if it's 1, the message will be sent with a 29-bit Identifier (extended frame format)." /> + </Register> + <Register start="+0x030+16" size="4" name="TFI2" access="Read/Write" description="Transmit frame info (Tx Buffer )" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="PRIO" description="If the TPM (Transmit Priority Mode) bit in the CANxMOD register is set to 1, enabled Tx Buffers contend for the right to send their messages based on this field. The buffer with the lowest TX Priority value wins the prioritization and is sent first." /> + <BitField start="8" size="8" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="16" size="4" name="DLC" description="Data Length Code. This value is sent in the DLC field of the next transmit message. In addition, if RTR = 0, this value controls the number of Data bytes sent in the next transmit message, from the CANxTDA and CANxTDB registers: 0000-0111 = 0-7 bytes 1xxx = 8 bytes" /> + <BitField start="20" size="10" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="30" size="1" name="RTR" description="This value is sent in the RTR bit of the next transmit message. If this bit is 0, the number of data bytes called out by the DLC field are sent from the CANxTDA and CANxTDB registers. If this bit is 1, a Remote Frame is sent, containing a request for that number of bytes." /> + <BitField start="31" size="1" name="FF" description="If this bit is 0, the next transmit message will be sent with an 11-bit Identifier (standard frame format), while if it's 1, the message will be sent with a 29-bit Identifier (extended frame format)." /> + </Register> + <Register start="+0x030+32" size="4" name="TFI3" access="Read/Write" description="Transmit frame info (Tx Buffer )" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="PRIO" description="If the TPM (Transmit Priority Mode) bit in the CANxMOD register is set to 1, enabled Tx Buffers contend for the right to send their messages based on this field. The buffer with the lowest TX Priority value wins the prioritization and is sent first." /> + <BitField start="8" size="8" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="16" size="4" name="DLC" description="Data Length Code. This value is sent in the DLC field of the next transmit message. In addition, if RTR = 0, this value controls the number of Data bytes sent in the next transmit message, from the CANxTDA and CANxTDB registers: 0000-0111 = 0-7 bytes 1xxx = 8 bytes" /> + <BitField start="20" size="10" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="30" size="1" name="RTR" description="This value is sent in the RTR bit of the next transmit message. If this bit is 0, the number of data bytes called out by the DLC field are sent from the CANxTDA and CANxTDB registers. If this bit is 1, a Remote Frame is sent, containing a request for that number of bytes." /> + <BitField start="31" size="1" name="FF" description="If this bit is 0, the next transmit message will be sent with an 11-bit Identifier (standard frame format), while if it's 1, the message will be sent with a 29-bit Identifier (extended frame format)." /> + </Register> + <Register start="+0x034+0" size="4" name="TID1" access="Read/Write" description="Transmit
Identifier (Tx Buffer)" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="11" name="ID" description="The 11-bit Identifier to be sent in the next transmit message." /> + <BitField start="11" size="21" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x034+16" size="4" name="TID2" access="Read/Write" description="Transmit
Identifier (Tx Buffer)" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="11" name="ID" description="The 11-bit Identifier to be sent in the next transmit message." /> + <BitField start="11" size="21" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x034+32" size="4" name="TID3" access="Read/Write" description="Transmit
Identifier (Tx Buffer)" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="11" name="ID" description="The 11-bit Identifier to be sent in the next transmit message." /> + <BitField start="11" size="21" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x038+0" size="4" name="TDA1" access="Read/Write" description="Transmit
data bytes 1-4 (Tx Buffer)" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="8" name="DATA1" description="Data 1. If RTR = 0 and DLC >= 0001 in the corresponding CANxTFI, this byte is sent as the first Data byte of the next transmit message." /> + <BitField start="8" size="8" name="DATA2" description="Data 2. If RTR = 0 and DLC >= 0010 in the corresponding CANxTFI, this byte is sent as the 2nd Data byte of the next transmit message." /> + <BitField start="16" size="8" name="DATA3" description="Data 3. If RTR = 0 and DLC >= 0011 in the corresponding CANxTFI, this byte is sent as the 3rd Data byte of the next transmit message." /> + <BitField start="24" size="8" name="DATA4" description="Data 4. If RTR = 0 and DLC >= 0100 in the corresponding CANxTFI, this byte is sent as the 4th Data byte of the next transmit message." /> + </Register> + <Register start="+0x038+16" size="4" name="TDA2" access="Read/Write" description="Transmit
data bytes 1-4 (Tx Buffer)" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="8" name="DATA1" description="Data 1. If RTR = 0 and DLC >= 0001 in the corresponding CANxTFI, this byte is sent as the first Data byte of the next transmit message." /> + <BitField start="8" size="8" name="DATA2" description="Data 2. If RTR = 0 and DLC >= 0010 in the corresponding CANxTFI, this byte is sent as the 2nd Data byte of the next transmit message." /> + <BitField start="16" size="8" name="DATA3" description="Data 3. If RTR = 0 and DLC >= 0011 in the corresponding CANxTFI, this byte is sent as the 3rd Data byte of the next transmit message." /> + <BitField start="24" size="8" name="DATA4" description="Data 4. If RTR = 0 and DLC >= 0100 in the corresponding CANxTFI, this byte is sent as the 4th Data byte of the next transmit message." /> + </Register> + <Register start="+0x038+32" size="4" name="TDA3" access="Read/Write" description="Transmit
data bytes 1-4 (Tx Buffer)" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="8" name="DATA1" description="Data 1. If RTR = 0 and DLC >= 0001 in the corresponding CANxTFI, this byte is sent as the first Data byte of the next transmit message." /> + <BitField start="8" size="8" name="DATA2" description="Data 2. If RTR = 0 and DLC >= 0010 in the corresponding CANxTFI, this byte is sent as the 2nd Data byte of the next transmit message." /> + <BitField start="16" size="8" name="DATA3" description="Data 3. If RTR = 0 and DLC >= 0011 in the corresponding CANxTFI, this byte is sent as the 3rd Data byte of the next transmit message." /> + <BitField start="24" size="8" name="DATA4" description="Data 4. If RTR = 0 and DLC >= 0100 in the corresponding CANxTFI, this byte is sent as the 4th Data byte of the next transmit message." /> + </Register> + <Register start="+0x03C+0" size="4" name="TDB1" access="Read/Write" description="Transmit
data bytes 5-8 (Tx Buffer )" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="8" name="DATA5" description="Data 5. If RTR = 0 and DLC >= 0101 in the corresponding CANTFI, this byte is sent as the 5th Data byte of the next transmit message." /> + <BitField start="8" size="8" name="DATA6" description="Data 6. If RTR = 0 and DLC >= 0110 in the corresponding CANTFI, this byte is sent as the 6th Data byte of the next transmit message." /> + <BitField start="16" size="8" name="DATA7" description="Data 7. If RTR = 0 and DLC >= 0111 in the corresponding CANTFI, this byte is sent as the 7th Data byte of the next transmit message." /> + <BitField start="24" size="8" name="DATA8" description="Data 8. If RTR = 0 and DLC >= 1000 in the corresponding CANTFI, this byte is sent as the 8th Data byte of the next transmit message." /> + </Register> + <Register start="+0x03C+16" size="4" name="TDB2" access="Read/Write" description="Transmit
data bytes 5-8 (Tx Buffer )" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="8" name="DATA5" description="Data 5. If RTR = 0 and DLC >= 0101 in the corresponding CANTFI, this byte is sent as the 5th Data byte of the next transmit message." /> + <BitField start="8" size="8" name="DATA6" description="Data 6. If RTR = 0 and DLC >= 0110 in the corresponding CANTFI, this byte is sent as the 6th Data byte of the next transmit message." /> + <BitField start="16" size="8" name="DATA7" description="Data 7. If RTR = 0 and DLC >= 0111 in the corresponding CANTFI, this byte is sent as the 7th Data byte of the next transmit message." /> + <BitField start="24" size="8" name="DATA8" description="Data 8. If RTR = 0 and DLC >= 1000 in the corresponding CANTFI, this byte is sent as the 8th Data byte of the next transmit message." /> + </Register> + <Register start="+0x03C+32" size="4" name="TDB3" access="Read/Write" description="Transmit
data bytes 5-8 (Tx Buffer )" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="8" name="DATA5" description="Data 5. If RTR = 0 and DLC >= 0101 in the corresponding CANTFI, this byte is sent as the 5th Data byte of the next transmit message." /> + <BitField start="8" size="8" name="DATA6" description="Data 6. If RTR = 0 and DLC >= 0110 in the corresponding CANTFI, this byte is sent as the 6th Data byte of the next transmit message." /> + <BitField start="16" size="8" name="DATA7" description="Data 7. If RTR = 0 and DLC >= 0111 in the corresponding CANTFI, this byte is sent as the 7th Data byte of the next transmit message." /> + <BitField start="24" size="8" name="DATA8" description="Data 8. If RTR = 0 and DLC >= 1000 in the corresponding CANTFI, this byte is sent as the 8th Data byte of the next transmit message." /> + </Register> + </RegisterGroup> + <RegisterGroup name="I2C1" start="0x4005C000" description="I2C bus interface"> + <Register start="+0x000" size="4" name="CONSET" access="Read/Write" description="I2C Control Set Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is set. Writing a zero has no effect on the corresponding bit in the I2C control register." reset_value="0x00" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + <BitField start="2" size="1" name="AA" description="Assert acknowledge flag." /> + <BitField start="3" size="1" name="SI" description="I2C interrupt flag." /> + <BitField start="4" size="1" name="STO" description="STOP flag." /> + <BitField start="5" size="1" name="STA" description="START flag." /> + <BitField start="6" size="1" name="I2EN" description="I2C interface enable." /> + <BitField start="7" size="25" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x004" size="4" name="STAT" access="ReadOnly" description="I2C Status Register. During I2C operation, this register provides detailed status codes that allow software to determine the next action needed." reset_value="0xF8" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="RESERVED" description="These bits are unused and are always 0." /> + <BitField start="3" size="5" name="Status" description="These bits give the actual status information about the I 2C interface." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x008" size="4" name="DAT" access="Read/Write" description="I2C Data Register. During master or slave transmit mode, data to be transmitted is written to this register. During master or slave receive mode, data that has been received may be read from this register." reset_value="0x00" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="Data" description="This register holds data values that have been received or are to be transmitted." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x00C" size="4" name="ADR0" access="Read/Write" description="I2C Slave Address Register 0. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="GC" description="General Call enable bit." /> + <BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x010" size="4" name="SCLH" access="Read/Write" description="SCH Duty Cycle Register High Half Word. Determines the high time of the I2C clock." reset_value="0x04" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="16" name="SCLH" description="Count for SCL HIGH time period selection." /> + <BitField start="16" size="16" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x014" size="4" name="SCLL" access="Read/Write" description="SCL Duty Cycle Register Low Half Word. Determines the low time of the I2C clock. SCLL and SCLH together determine the clock frequency generated by an I2C master and certain times used in slave mode." reset_value="0x04" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="16" name="SCLL" description="Count for SCL low time period selection." /> + <BitField start="16" size="16" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x018" size="4" name="CONCLR" access="WriteOnly" description="I2C Control Clear Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is cleared. Writing a zero has no effect on the corresponding bit in the I2C control register." reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="2" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + <BitField start="2" size="1" name="AAC" description="Assert acknowledge Clear bit." /> + <BitField start="3" size="1" name="SIC" description="I2C interrupt Clear bit." /> + <BitField start="4" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + <BitField start="5" size="1" name="STAC" description="START flag Clear bit." /> + <BitField start="6" size="1" name="I2ENC" description="I2C interface Disable bit." /> + <BitField start="7" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x01C" size="4" name="MMCTRL" access="Read/Write" description="Monitor mode control register." reset_value="0x00" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="MM_ENA" description="Monitor mode enable."> + <Enum name="MONITOR_MODE_DISABLE" start="0" description="Monitor mode disabled." /> + <Enum name="THE_I_2C_MODULE_WILL" start="1" description="The I 2C module will enter monitor mode. In this mode the SDA output will be forced high. This will prevent the I2C module from outputting data of any kind (including ACK) onto the I2C data bus. Depending on the state of the ENA_SCL bit, the output may be also forced high, preventing the module from having control over the I2C clock line." /> + </BitField> + <BitField start="1" size="1" name="ENA_SCL" description="SCL output enable."> + <Enum name="WHEN_THIS_BIT_IS_CLE" start="0" description="When this bit is cleared to 0, the SCL output will be forced high when the module is in monitor mode. As described above, this will prevent the module from having any control over the I2C clock line." /> + <Enum name="WHEN_THIS_BIT_IS_SET" start="1" description="When this bit is set, the I2C module may exercise the same control over the clock line that it would in normal operation. This means that, acting as a slave peripheral, the I2C module can stretch the clock line (hold it low) until it has had time to respond to an I2C interrupt.[1]" /> + </BitField> + <BitField start="2" size="1" name="MATCH_ALL" description="Select interrupt register match."> + <Enum name="WHEN_THIS_BIT_IS_CLE" start="0" description="When this bit is cleared, an interrupt will only be generated when a match occurs to one of the (up-to) four address registers described above. That is, the module will respond as a normal slave as far as address-recognition is concerned." /> + <Enum name="WHEN_THIS_BIT_IS_SET" start="1" description="When this bit is set to 1 and the I2C is in monitor mode, an interrupt will be generated on ANY address received. This will enable the part to monitor all traffic on the bus." /> + </BitField> + <BitField start="3" size="29" name="RESERVED" description="Reserved. The value read from reserved bits is not defined." /> + </Register> + <Register start="+0x020+0" size="4" name="ADR1" access="Read/Write" description="I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="GC" description="General Call enable bit." /> + <BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x020+4" size="4" name="ADR2" access="Read/Write" description="I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="GC" description="General Call enable bit." /> + <BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x020+8" size="4" name="ADR3" access="Read/Write" description="I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="GC" description="General Call enable bit." /> + <BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x02C" size="4" name="DATA_BUFFER" access="ReadOnly" description="Data buffer register. The contents of the 8 MSBs of the DAT shift register will be transferred to the DATA_BUFFER automatically after every nine bits (8 bits of data plus ACK or NACK) has been received on the bus." reset_value="0x00" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="Data" description="This register holds contents of the 8 MSBs of the DAT shift register." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x030+0" size="4" name="MASK[0]" access="Read/Write" description="I2C Slave address mask register" reset_value="0x00" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." /> + <BitField start="1" size="7" name="MASK" description="Mask bits." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x030+4" size="4" name="MASK[1]" access="Read/Write" description="I2C Slave address mask register" reset_value="0x00" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." /> + <BitField start="1" size="7" name="MASK" description="Mask bits." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x030+8" size="4" name="MASK[2]" access="Read/Write" description="I2C Slave address mask register" reset_value="0x00" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." /> + <BitField start="1" size="7" name="MASK" description="Mask bits." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x030+12" size="4" name="MASK[3]" access="Read/Write" description="I2C Slave address mask register" reset_value="0x00" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." /> + <BitField start="1" size="7" name="MASK" description="Mask bits." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + </RegisterGroup> + <RegisterGroup name="SSP0" start="0x40088000" description="SSP controller"> + <Register start="+0x000" size="4" name="CR0" access="Read/Write" description="Control Register 0. Selects the serial clock rate, bus type, and data size." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="4" name="DSS" description="Data Size Select. This field controls the number of bits transferred in each frame. Values 0000-0010 are not supported and should not be used."> + <Enum name="4_BIT_TRANSFER" start="0x3" description="4-bit transfer" /> + <Enum name="5_BIT_TRANSFER" start="0x4" description="5-bit transfer" /> + <Enum name="6_BIT_TRANSFER" start="0x5" description="6-bit transfer" /> + <Enum name="7_BIT_TRANSFER" start="0x6" description="7-bit transfer" /> + <Enum name="8_BIT_TRANSFER" start="0x7" description="8-bit transfer" /> + <Enum name="9_BIT_TRANSFER" start="0x8" description="9-bit transfer" /> + <Enum name="10_BIT_TRANSFER" start="0x9" description="10-bit transfer" /> + <Enum name="11_BIT_TRANSFER" start="0xA" description="11-bit transfer" /> + <Enum name="12_BIT_TRANSFER" start="0xB" description="12-bit transfer" /> + <Enum name="13_BIT_TRANSFER" start="0xC" description="13-bit transfer" /> + <Enum name="14_BIT_TRANSFER" start="0xD" description="14-bit transfer" /> + <Enum name="15_BIT_TRANSFER" start="0xE" description="15-bit transfer" /> + <Enum name="16_BIT_TRANSFER" start="0xF" description="16-bit transfer" /> + </BitField> + <BitField start="4" size="2" name="FRF" description="Frame Format."> + <Enum name="SPI" start="0x0" description="SPI" /> + <Enum name="TI" start="0x1" description="TI" /> + <Enum name="MICROWIRE" start="0x2" description="Microwire" /> + <Enum name="THIS_COMBINATION_IS_" start="0x3" description="This combination is not supported and should not be used." /> + </BitField> + <BitField start="6" size="1" name="CPOL" description="Clock Out Polarity. This bit is only used in SPI mode."> + <Enum name="BUS_LOW" start="0" description="SSP controller maintains the bus clock low between frames." /> + <Enum name="BUS_HIGH" start="1" description="SSP controller maintains the bus clock high between frames." /> + </BitField> + <BitField start="7" size="1" name="CPHA" description="Clock Out Phase. This bit is only used in SPI mode."> + <Enum name="FIRST_CLOCK" start="0" description="SSP controller captures serial data on the first clock transition of the frame, that is, the transition away from the inter-frame state of the clock line." /> + <Enum name="SECOND_CLOCK" start="1" description="SSP controller captures serial data on the second clock transition of the frame, that is, the transition back to the inter-frame state of the clock line." /> + </BitField> + <BitField start="8" size="8" name="SCR" description="Serial Clock Rate. The number of prescaler-output clocks per bit on the bus, minus one. Given that CPSDVSR is the prescale divider, and the APB clock PCLK clocks the prescaler, the bit frequency is PCLK / (CPSDVSR X [SCR+1])." /> + <BitField start="16" size="16" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x004" size="4" name="CR1" access="Read/Write" description="Control Register 1. Selects master/slave and other modes." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="LBM" description="Loop Back Mode."> + <Enum name="NORMAL" start="0" description="During normal operation." /> + <Enum name="OUPTU" start="1" description="Serial input is taken from the serial output (MOSI or MISO) rather than the serial input pin (MISO or MOSI respectively)." /> + </BitField> + <BitField start="1" size="1" name="SSE" description="SSP Enable."> + <Enum name="DISABLED" start="0" description="The SSP controller is disabled." /> + <Enum name="ENABLED" start="1" description="The SSP controller will interact with other devices on the serial bus. Software should write the appropriate control information to the other SSP registers and interrupt controller registers, before setting this bit." /> + </BitField> + <BitField start="2" size="1" name="MS" description="Master/Slave Mode.This bit can only be written when the SSE bit is 0."> + <Enum name="MASTER" start="0" description="The SSP controller acts as a master on the bus, driving the SCLK, MOSI, and SSEL lines and receiving the MISO line." /> + <Enum name="SLAVE" start="1" description="The SSP controller acts as a slave on the bus, driving MISO line and receiving SCLK, MOSI, and SSEL lines." /> + </BitField> + <BitField start="3" size="1" name="SOD" description="Slave Output Disable. This bit is relevant only in slave mode (MS = 1). If it is 1, this blocks this SSP controller from driving the transmit data line (MISO)." /> + <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x008" size="4" name="DR" access="None" description="Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="16" name="DATA" description="Write: software can write data to be sent in a future frame to this register whenever the TNF bit in the Status register is 1, indicating that the Tx FIFO is not full. If the Tx FIFO was previously empty and the SSP controller is not busy on the bus, transmission of the data will begin immediately. Otherwise the data written to this register will be sent as soon as all previous data has been sent (and received). If the data length is less than 16 bits, software must right-justify the data written to this register. Read: software can read data from this register whenever the RNE bit in the Status register is 1, indicating that the Rx FIFO is not empty. When software reads this register, the SSP controller returns data from the least recent frame in the Rx FIFO. If the data length is less than 16 bits, the data is right-justified in this field with higher order bits filled with 0s." /> + <BitField start="16" size="16" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x00C" size="4" name="SR" access="ReadOnly" description="Status Register" reset_value="0x00000003" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="TFE" description="Transmit FIFO Empty. This bit is 1 is the Transmit FIFO is empty, 0 if not." /> + <BitField start="1" size="1" name="TNF" description="Transmit FIFO Not Full. This bit is 0 if the Tx FIFO is full, 1 if not." /> + <BitField start="2" size="1" name="RNE" description="Receive FIFO Not Empty. This bit is 0 if the Receive FIFO is empty, 1 if not." /> + <BitField start="3" size="1" name="RFF" description="Receive FIFO Full. This bit is 1 if the Receive FIFO is full, 0 if not." /> + <BitField start="4" size="1" name="BSY" description="Busy. This bit is 0 if the SSPn controller is idle, or 1 if it is currently sending/receiving a frame and/or the Tx FIFO is not empty." /> + <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x010" size="4" name="CPSR" access="Read/Write" description="Clock Prescale Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="CPSDVSR" description="This even value between 2 and 254, by which PCLK is divided to yield the prescaler output clock. Bit 0 always reads as 0." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x014" size="4" name="IMSC" access="Read/Write" description="Interrupt Mask Set and Clear Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RORIM" description="Software should set this bit to enable interrupt when a Receive Overrun occurs, that is, when the Rx FIFO is full and another frame is completely received. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs." /> + <BitField start="1" size="1" name="RTIM" description="Software should set this bit to enable interrupt when a Receive Time-out condition occurs. A Receive Time-out occurs when the Rx FIFO is not empty, and no has not been read for a time-out period. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1])." /> + <BitField start="2" size="1" name="RXIM" description="Software should set this bit to enable interrupt when the Rx FIFO is at least half full." /> + <BitField start="3" size="1" name="TXIM" description="Software should set this bit to enable interrupt when the Tx FIFO is at least half empty." /> + <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x018" size="4" name="RIS" access="ReadOnly" description="Raw Interrupt Status Register" reset_value="0x00000008" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RORRIS" description="This bit is 1 if another frame was completely received while the RxFIFO was full. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs." /> + <BitField start="1" size="1" name="RTRIS" description="This bit is 1 if the Rx FIFO is not empty, and has not been read for a time-out period. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1])." /> + <BitField start="2" size="1" name="RXRIS" description="This bit is 1 if the Rx FIFO is at least half full." /> + <BitField start="3" size="1" name="TXRIS" description="This bit is 1 if the Tx FIFO is at least half empty." /> + <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x01C" size="4" name="MIS" access="ReadOnly" description="Masked Interrupt Status Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RORMIS" description="This bit is 1 if another frame was completely received while the RxFIFO was full, and this interrupt is enabled." /> + <BitField start="1" size="1" name="RTMIS" description="This bit is 1 if the Rx FIFO is not empty, has not been read for a time-out period, and this interrupt is enabled. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1])." /> + <BitField start="2" size="1" name="RXMIS" description="This bit is 1 if the Rx FIFO is at least half full, and this interrupt is enabled." /> + <BitField start="3" size="1" name="TXMIS" description="This bit is 1 if the Tx FIFO is at least half empty, and this interrupt is enabled." /> + <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x020" size="4" name="ICR" access="WriteOnly" description="SSPICR Interrupt Clear Register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="RORIC" description="Writing a 1 to this bit clears the frame was received when RxFIFO was full interrupt." /> + <BitField start="1" size="1" name="RTIC" description="Writing a 1 to this bit clears the Rx FIFO was not empty and has not been read for a time-out period interrupt. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR / [SCR+1])." /> + <BitField start="2" size="30" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x024" size="4" name="DMACR" access="Read/Write" description="SSP0 DMA control register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RXDMAE" description="Receive DMA Enable. When this bit is set to one 1, DMA for the receive FIFO is enabled, otherwise receive DMA is disabled." /> + <BitField start="1" size="1" name="TXDMAE" description="Transmit DMA Enable. When this bit is set to one 1, DMA for the transmit FIFO is enabled, otherwise transmit DMA is disabled" /> + <BitField start="2" size="30" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + </RegisterGroup> + <RegisterGroup name="DAC" start="0x4008C000" description="Digital-to-Analog Converter (DAC) Modification"> + <Register start="+0x000" size="4" name="CR" access="Read/Write" description="D/A Converter Register. This register contains the digital value to be converted to analog and a power control bit." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="6" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="6" size="10" name="VALUE" description="After the selected settling time after this field is written with a new VALUE, the voltage on the DAC_OUT pin (with respect to VSSA) is VALUE x ((VREFP - V REFN)/1024) + VREFN." /> + <BitField start="16" size="1" name="BIAS" description="Settling time The settling times noted in the description of the BIAS bit are valid for a capacitance load on the DAC_OUT pin not exceeding 100 pF. A load impedance value greater than that value will cause settling time longer than the specified time. One or more graphs of load impedance vs. settling time will be included in the final data sheet."> + <Enum name="FAST" start="0" description="The settling time of the DAC is 1 us max, and the maximum current is 700 uA. This allows a maximum update rate of 1 MHz." /> + <Enum name="SLOW" start="1" description="The settling time of the DAC is 2.5 us and the maximum current is 350 uA. This allows a maximum update rate of 400 kHz." /> + </BitField> + <BitField start="17" size="15" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x004" size="4" name="CTRL" access="Read/Write" description="DAC Control register. This register controls DMA and timer operation." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="INT_DMA_REQ" description="DMA interrupt request"> + <Enum name="CLEAR_ON_ANY_WRITE_T" start="0" description="Clear on any write to the DACR register." /> + <Enum name="SET_BY_HARDWARE_WHEN" start="1" description="Set by hardware when the timer times out." /> + </BitField> + <BitField start="1" size="1" name="DBLBUF_ENA" description="Double buffering"> + <Enum name="DISABLE" start="0" description="Disable" /> + <Enum name="ENABLE_WHEN_THIS_BI" start="1" description="Enable. When this bit and the CNT_ENA bit are both set, the double-buffering feature in the DACR register will be enabled. Writes to the DACR register are written to a pre-buffer and then transferred to the DACR on the next time-out of the counter." /> + </BitField> + <BitField start="2" size="1" name="CNT_ENA" description="Time-out counter operation"> + <Enum name="DISABLE" start="0" description="Disable" /> + <Enum name="ENABLE" start="1" description="Enable" /> + </BitField> + <BitField start="3" size="1" name="DMA_ENA" description="DMA access"> + <Enum name="DISABLE" start="0" description="Disable" /> + <Enum name="ENABLE_DMA_BURST_RE" start="1" description="Enable. DMA Burst Request Input 7 is enabled for the DAC (see Table 672)." /> + </BitField> + <BitField start="4" size="28" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x008" size="4" name="CNTVAL" access="Read/Write" description="DAC Counter Value register. This register contains the reload value for the DAC DMA/Interrupt timer." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="16" name="VALUE" description="16-bit reload value for the DAC interrupt/DMA timer." /> + <BitField start="16" size="16" name="RESERVED" description="Reserved" /> + </Register> + </RegisterGroup> + <RegisterGroup name="TIMER2" start="0x40090000" description=" Timer0/1/2/3 "> + <Register start="+0x000" size="4" name="IR" access="Read/Write" description="Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="MR0INT" description="Interrupt flag for match channel 0." /> + <BitField start="1" size="1" name="MR1INT" description="Interrupt flag for match channel 1." /> + <BitField start="2" size="1" name="MR2INT" description="Interrupt flag for match channel 2." /> + <BitField start="3" size="1" name="MR3INT" description="Interrupt flag for match channel 3." /> + <BitField start="4" size="1" name="CR0INT" description="Interrupt flag for capture channel 0 event." /> + <BitField start="5" size="1" name="CR1INT" description="Interrupt flag for capture channel 1 event." /> + <BitField start="6" size="26" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x004" size="4" name="TCR" access="Read/Write" description="Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="CEN" description="When one, the Timer Counter and Prescale Counter are enabled for counting. When zero, the counters are disabled." /> + <BitField start="1" size="1" name="CRST" description="When one, the Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero." /> + <BitField start="2" size="30" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x008" size="4" name="TC" access="Read/Write" description="Timer Counter. The 32 bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="TC" description="Timer counter value." /> + </Register> + <Register start="+0x00C" size="4" name="PR" access="Read/Write" description="Prescale Register. When the Prescale Counter (PC) is equal to this value, the next clock increments the TC and clears the PC." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="PM" description="Prescale counter maximum value." /> + </Register> + <Register start="+0x010" size="4" name="PC" access="Read/Write" description="Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="PC" description="Prescale counter value." /> + </Register> + <Register start="+0x014" size="4" name="MCR" access="Read/Write" description="Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="MR0I" description="Interrupt on MR0"> + <Enum name="INTERRUPT_IS_GENERAT" start="1" description="Interrupt is generated when MR0 matches the value in the TC." /> + <Enum name="INTERRUPT_IS_DISABLE" start="0" description="Interrupt is disabled" /> + </BitField> + <BitField start="1" size="1" name="MR0R" description="Reset on MR0"> + <Enum name="TC_WILL_BE_RESET_IF_" start="1" description="TC will be reset if MR0 matches it." /> + <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." /> + </BitField> + <BitField start="2" size="1" name="MR0S" description="Stop on MR0"> + <Enum name="TC_AND_PC_WILL_BE_ST" start="1" description="TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC." /> + <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." /> + </BitField> + <BitField start="3" size="1" name="MR1I" description="Interrupt on MR1"> + <Enum name="INTERRUPT_IS_GENERAT" start="1" description="Interrupt is generated when MR1 matches the value in the TC." /> + <Enum name="INTERRUPT_IS_DISABLE" start="0" description="Interrupt is disabled." /> + </BitField> + <BitField start="4" size="1" name="MR1R" description="Reset on MR1"> + <Enum name="TC_WILL_BE_RESET_IF_" start="1" description="TC will be reset if MR1 matches it." /> + <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." /> + </BitField> + <BitField start="5" size="1" name="MR1S" description="Stop on MR1"> + <Enum name="TC_AND_PC_WILL_BE_ST" start="1" description="TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC." /> + <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." /> + </BitField> + <BitField start="6" size="1" name="MR2I" description="Interrupt on MR2"> + <Enum name="INTERRUPT_IS_GENERAT" start="1" description="Interrupt is generated when MR2 matches the value in the TC." /> + <Enum name="INTERRUPT_IS_DISABLE" start="0" description="Interrupt is disabled" /> + </BitField> + <BitField start="7" size="1" name="MR2R" description="Reset on MR2"> + <Enum name="TC_WILL_BE_RESET_IF_" start="1" description="TC will be reset if MR2 matches it." /> + <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." /> + </BitField> + <BitField start="8" size="1" name="MR2S" description="Stop on MR2."> + <Enum name="TC_AND_PC_WILL_BE_ST" start="1" description="TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC" /> + <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." /> + </BitField> + <BitField start="9" size="1" name="MR3I" description="Interrupt on MR3"> + <Enum name="INTERRUPT_IS_GENERAT" start="1" description="Interrupt is generated when MR3 matches the value in the TC." /> + <Enum name="THIS_INTERRUPT_IS_DI" start="0" description="This interrupt is disabled" /> + </BitField> + <BitField start="10" size="1" name="MR3R" description="Reset on MR3"> + <Enum name="TC_WILL_BE_RESET_IF_" start="1" description="TC will be reset if MR3 matches it." /> + <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." /> + </BitField> + <BitField start="11" size="1" name="MR3S" description="Stop on MR3"> + <Enum name="TC_AND_PC_WILL_BE_ST" start="1" description="TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC." /> + <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." /> + </BitField> + <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x018+0" size="4" name="MR[0]" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="MATCH" description="Timer counter match value." /> + </Register> + <Register start="+0x018+4" size="4" name="MR[1]" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="MATCH" description="Timer counter match value." /> + </Register> + <Register start="+0x018+8" size="4" name="MR[2]" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="MATCH" description="Timer counter match value." /> + </Register> + <Register start="+0x018+12" size="4" name="MR[3]" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="MATCH" description="Timer counter match value." /> + </Register> + <Register start="+0x028" size="4" name="CCR" access="Read/Write" description="Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="CAP0RE" description="Capture on CAPn.0 rising edge"> + <Enum name="ENABLE" start="1" description="A sequence of 0 then 1 on CAPn.0 will cause CR0 to be loaded with the contents of TC." /> + <Enum name="DISABLE" start="0" description="This feature is disabled." /> + </BitField> + <BitField start="1" size="1" name="CAP0FE" description="Capture on CAPn.0 falling edge"> + <Enum name="ENABLE" start="1" description="A sequence of 1 then 0 on CAPn.0 will cause CR0 to be loaded with the contents of TC." /> + <Enum name="DISABLE" start="0" description="This feature is disabled." /> + </BitField> + <BitField start="2" size="1" name="CAP0I" description="Interrupt on CAPn.0 event"> + <Enum name="ENABLE" start="1" description="A CR0 load due to a CAPn.0 event will generate an interrupt." /> + <Enum name="DISABLE" start="0" description="This feature is disabled." /> + </BitField> + <BitField start="3" size="1" name="CAP1RE" description="Capture on CAPn.1 rising edge"> + <Enum name="ENABLE" start="1" description="A sequence of 0 then 1 on CAPn.1 will cause CR1 to be loaded with the contents of TC." /> + <Enum name="DISABLE" start="0" description="This feature is disabled." /> + </BitField> + <BitField start="4" size="1" name="CAP1FE" description="Capture on CAPn.1 falling edge"> + <Enum name="ENABLE" start="1" description="A sequence of 1 then 0 on CAPn.1 will cause CR1 to be loaded with the contents of TC." /> + <Enum name="DISABLE" start="0" description="This feature is disabled." /> + </BitField> + <BitField start="5" size="1" name="CAP1I" description="Interrupt on CAPn.1 event"> + <Enum name="ENABLE" start="1" description="A CR1 load due to a CAPn.1 event will generate an interrupt." /> + <Enum name="DISABLE" start="0" description="This feature is disabled." /> + </BitField> + <BitField start="6" size="26" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x02C+0" size="4" name="CR[0]" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CAP" description="Timer counter capture value." /> + </Register> + <Register start="+0x02C+4" size="4" name="CR[1]" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CAP" description="Timer counter capture value." /> + </Register> + <Register start="+0x03C" size="4" name="EMR" access="Read/Write" description="External Match Register. The EMR controls the external match pins." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="EM0" description="External Match 0. When a match occurs between the TC and MR0, this bit can either toggle, go low, go high, or do nothing, depending on bits 5:4 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." /> + <BitField start="1" size="1" name="EM1" description="External Match 1. When a match occurs between the TC and MR1, this bit can either toggle, go low, go high, or do nothing, depending on bits 7:6 of this register. This bit can be driven onto a MATn.1 pin, in a positive-logic manner (0 = low, 1 = high)." /> + <BitField start="2" size="1" name="EM2" description="External Match 2. When a match occurs between the TC and MR2, this bit can either toggle, go low, go high, or do nothing, depending on bits 9:8 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." /> + <BitField start="3" size="1" name="EM3" description="External Match 3. When a match occurs between the TC and MR3, this bit can either toggle, go low, go high, or do nothing, depending on bits 11:10 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." /> + <BitField start="4" size="2" name="EMC0" description="External Match Control 0. Determines the functionality of External Match 0."> + <Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." /> + <Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." /> + <Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." /> + <Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." /> + </BitField> + <BitField start="6" size="2" name="EMC1" description="External Match Control 1. Determines the functionality of External Match 1."> + <Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." /> + <Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." /> + <Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." /> + <Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." /> + </BitField> + <BitField start="8" size="2" name="EMC2" description="External Match Control 2. Determines the functionality of External Match 2."> + <Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." /> + <Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." /> + <Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." /> + <Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." /> + </BitField> + <BitField start="10" size="2" name="EMC3" description="External Match Control 3. Determines the functionality of External Match 3."> + <Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." /> + <Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." /> + <Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." /> + <Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." /> + </BitField> + <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x070" size="4" name="CTCR" access="Read/Write" description="Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="CTMODE" description="Counter/Timer Mode This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale Register."> + <Enum name="TIMER_MODE_EVERY_RI" start="0x0" description="Timer Mode: every rising PCLK edge" /> + <Enum name="RISING" start="0x1" description="Counter Mode: TC is incremented on rising edges on the CAP input selected by bits 3:2." /> + <Enum name="FALLING" start="0x2" description="Counter Mode: TC is incremented on falling edges on the CAP input selected by bits 3:2." /> + <Enum name="DUALEDGE" start="0x3" description="Counter Mode: TC is incremented on both edges on the CAP input selected by bits 3:2." /> + </BitField> + <BitField start="2" size="2" name="CINSEL" description="Count Input Select When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the TnCTCR, the 3 bits for that input in the Capture Control Register (TnCCR) must be programmed as 000. However, capture and/or interrupt can be selected for the other 3 CAPn inputs in the same timer."> + <Enum name="CAPN_0_FOR_TIMERN" start="0x0" description="CAPn.0 for TIMERn" /> + <Enum name="CAPN_1_FOR_TIMERN" start="0x1" description="CAPn.1 for TIMERn" /> + </BitField> + <BitField start="4" size="28" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + </RegisterGroup> + <RegisterGroup name="TIMER3" start="0x40094000" description=" Timer0/1/2/3 "> + <Register start="+0x000" size="4" name="IR" access="Read/Write" description="Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="MR0INT" description="Interrupt flag for match channel 0." /> + <BitField start="1" size="1" name="MR1INT" description="Interrupt flag for match channel 1." /> + <BitField start="2" size="1" name="MR2INT" description="Interrupt flag for match channel 2." /> + <BitField start="3" size="1" name="MR3INT" description="Interrupt flag for match channel 3." /> + <BitField start="4" size="1" name="CR0INT" description="Interrupt flag for capture channel 0 event." /> + <BitField start="5" size="1" name="CR1INT" description="Interrupt flag for capture channel 1 event." /> + <BitField start="6" size="26" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x004" size="4" name="TCR" access="Read/Write" description="Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="CEN" description="When one, the Timer Counter and Prescale Counter are enabled for counting. When zero, the counters are disabled." /> + <BitField start="1" size="1" name="CRST" description="When one, the Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero." /> + <BitField start="2" size="30" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x008" size="4" name="TC" access="Read/Write" description="Timer Counter. The 32 bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="TC" description="Timer counter value." /> + </Register> + <Register start="+0x00C" size="4" name="PR" access="Read/Write" description="Prescale Register. When the Prescale Counter (PC) is equal to this value, the next clock increments the TC and clears the PC." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="PM" description="Prescale counter maximum value." /> + </Register> + <Register start="+0x010" size="4" name="PC" access="Read/Write" description="Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="PC" description="Prescale counter value." /> + </Register> + <Register start="+0x014" size="4" name="MCR" access="Read/Write" description="Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="MR0I" description="Interrupt on MR0"> + <Enum name="INTERRUPT_IS_GENERAT" start="1" description="Interrupt is generated when MR0 matches the value in the TC." /> + <Enum name="INTERRUPT_IS_DISABLE" start="0" description="Interrupt is disabled" /> + </BitField> + <BitField start="1" size="1" name="MR0R" description="Reset on MR0"> + <Enum name="TC_WILL_BE_RESET_IF_" start="1" description="TC will be reset if MR0 matches it." /> + <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." /> + </BitField> + <BitField start="2" size="1" name="MR0S" description="Stop on MR0"> + <Enum name="TC_AND_PC_WILL_BE_ST" start="1" description="TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC." /> + <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." /> + </BitField> + <BitField start="3" size="1" name="MR1I" description="Interrupt on MR1"> + <Enum name="INTERRUPT_IS_GENERAT" start="1" description="Interrupt is generated when MR1 matches the value in the TC." /> + <Enum name="INTERRUPT_IS_DISABLE" start="0" description="Interrupt is disabled." /> + </BitField> + <BitField start="4" size="1" name="MR1R" description="Reset on MR1"> + <Enum name="TC_WILL_BE_RESET_IF_" start="1" description="TC will be reset if MR1 matches it." /> + <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." /> + </BitField> + <BitField start="5" size="1" name="MR1S" description="Stop on MR1"> + <Enum name="TC_AND_PC_WILL_BE_ST" start="1" description="TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC." /> + <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." /> + </BitField> + <BitField start="6" size="1" name="MR2I" description="Interrupt on MR2"> + <Enum name="INTERRUPT_IS_GENERAT" start="1" description="Interrupt is generated when MR2 matches the value in the TC." /> + <Enum name="INTERRUPT_IS_DISABLE" start="0" description="Interrupt is disabled" /> + </BitField> + <BitField start="7" size="1" name="MR2R" description="Reset on MR2"> + <Enum name="TC_WILL_BE_RESET_IF_" start="1" description="TC will be reset if MR2 matches it." /> + <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." /> + </BitField> + <BitField start="8" size="1" name="MR2S" description="Stop on MR2."> + <Enum name="TC_AND_PC_WILL_BE_ST" start="1" description="TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC" /> + <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." /> + </BitField> + <BitField start="9" size="1" name="MR3I" description="Interrupt on MR3"> + <Enum name="INTERRUPT_IS_GENERAT" start="1" description="Interrupt is generated when MR3 matches the value in the TC." /> + <Enum name="THIS_INTERRUPT_IS_DI" start="0" description="This interrupt is disabled" /> + </BitField> + <BitField start="10" size="1" name="MR3R" description="Reset on MR3"> + <Enum name="TC_WILL_BE_RESET_IF_" start="1" description="TC will be reset if MR3 matches it." /> + <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." /> + </BitField> + <BitField start="11" size="1" name="MR3S" description="Stop on MR3"> + <Enum name="TC_AND_PC_WILL_BE_ST" start="1" description="TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC." /> + <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." /> + </BitField> + <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x018+0" size="4" name="MR[0]" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="MATCH" description="Timer counter match value." /> + </Register> + <Register start="+0x018+4" size="4" name="MR[1]" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="MATCH" description="Timer counter match value." /> + </Register> + <Register start="+0x018+8" size="4" name="MR[2]" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="MATCH" description="Timer counter match value." /> + </Register> + <Register start="+0x018+12" size="4" name="MR[3]" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="MATCH" description="Timer counter match value." /> + </Register> + <Register start="+0x028" size="4" name="CCR" access="Read/Write" description="Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="CAP0RE" description="Capture on CAPn.0 rising edge"> + <Enum name="ENABLE" start="1" description="A sequence of 0 then 1 on CAPn.0 will cause CR0 to be loaded with the contents of TC." /> + <Enum name="DISABLE" start="0" description="This feature is disabled." /> + </BitField> + <BitField start="1" size="1" name="CAP0FE" description="Capture on CAPn.0 falling edge"> + <Enum name="ENABLE" start="1" description="A sequence of 1 then 0 on CAPn.0 will cause CR0 to be loaded with the contents of TC." /> + <Enum name="DISABLE" start="0" description="This feature is disabled." /> + </BitField> + <BitField start="2" size="1" name="CAP0I" description="Interrupt on CAPn.0 event"> + <Enum name="ENABLE" start="1" description="A CR0 load due to a CAPn.0 event will generate an interrupt." /> + <Enum name="DISABLE" start="0" description="This feature is disabled." /> + </BitField> + <BitField start="3" size="1" name="CAP1RE" description="Capture on CAPn.1 rising edge"> + <Enum name="ENABLE" start="1" description="A sequence of 0 then 1 on CAPn.1 will cause CR1 to be loaded with the contents of TC." /> + <Enum name="DISABLE" start="0" description="This feature is disabled." /> + </BitField> + <BitField start="4" size="1" name="CAP1FE" description="Capture on CAPn.1 falling edge"> + <Enum name="ENABLE" start="1" description="A sequence of 1 then 0 on CAPn.1 will cause CR1 to be loaded with the contents of TC." /> + <Enum name="DISABLE" start="0" description="This feature is disabled." /> + </BitField> + <BitField start="5" size="1" name="CAP1I" description="Interrupt on CAPn.1 event"> + <Enum name="ENABLE" start="1" description="A CR1 load due to a CAPn.1 event will generate an interrupt." /> + <Enum name="DISABLE" start="0" description="This feature is disabled." /> + </BitField> + <BitField start="6" size="26" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x02C+0" size="4" name="CR[0]" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CAP" description="Timer counter capture value." /> + </Register> + <Register start="+0x02C+4" size="4" name="CR[1]" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CAP" description="Timer counter capture value." /> + </Register> + <Register start="+0x03C" size="4" name="EMR" access="Read/Write" description="External Match Register. The EMR controls the external match pins." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="EM0" description="External Match 0. When a match occurs between the TC and MR0, this bit can either toggle, go low, go high, or do nothing, depending on bits 5:4 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." /> + <BitField start="1" size="1" name="EM1" description="External Match 1. When a match occurs between the TC and MR1, this bit can either toggle, go low, go high, or do nothing, depending on bits 7:6 of this register. This bit can be driven onto a MATn.1 pin, in a positive-logic manner (0 = low, 1 = high)." /> + <BitField start="2" size="1" name="EM2" description="External Match 2. When a match occurs between the TC and MR2, this bit can either toggle, go low, go high, or do nothing, depending on bits 9:8 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." /> + <BitField start="3" size="1" name="EM3" description="External Match 3. When a match occurs between the TC and MR3, this bit can either toggle, go low, go high, or do nothing, depending on bits 11:10 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." /> + <BitField start="4" size="2" name="EMC0" description="External Match Control 0. Determines the functionality of External Match 0."> + <Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." /> + <Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." /> + <Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." /> + <Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." /> + </BitField> + <BitField start="6" size="2" name="EMC1" description="External Match Control 1. Determines the functionality of External Match 1."> + <Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." /> + <Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." /> + <Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." /> + <Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." /> + </BitField> + <BitField start="8" size="2" name="EMC2" description="External Match Control 2. Determines the functionality of External Match 2."> + <Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." /> + <Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." /> + <Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." /> + <Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." /> + </BitField> + <BitField start="10" size="2" name="EMC3" description="External Match Control 3. Determines the functionality of External Match 3."> + <Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." /> + <Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." /> + <Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." /> + <Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." /> + </BitField> + <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x070" size="4" name="CTCR" access="Read/Write" description="Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="CTMODE" description="Counter/Timer Mode This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale Register."> + <Enum name="TIMER_MODE_EVERY_RI" start="0x0" description="Timer Mode: every rising PCLK edge" /> + <Enum name="RISING" start="0x1" description="Counter Mode: TC is incremented on rising edges on the CAP input selected by bits 3:2." /> + <Enum name="FALLING" start="0x2" description="Counter Mode: TC is incremented on falling edges on the CAP input selected by bits 3:2." /> + <Enum name="DUALEDGE" start="0x3" description="Counter Mode: TC is incremented on both edges on the CAP input selected by bits 3:2." /> + </BitField> + <BitField start="2" size="2" name="CINSEL" description="Count Input Select When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the TnCTCR, the 3 bits for that input in the Capture Control Register (TnCCR) must be programmed as 000. However, capture and/or interrupt can be selected for the other 3 CAPn inputs in the same timer."> + <Enum name="CAPN_0_FOR_TIMERN" start="0x0" description="CAPn.0 for TIMERn" /> + <Enum name="CAPN_1_FOR_TIMERN" start="0x1" description="CAPn.1 for TIMERn" /> + </BitField> + <BitField start="4" size="28" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + </RegisterGroup> + <RegisterGroup name="UART2" start="0x40098000" description="UART0/2/3 "> + <Register start="+0x000" size="4" name="RBR" access="None" description="Receiver Buffer Register. Contains the next received character to be read (DLAB =0)." reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="8" name="RBR" description="The UARTn Receiver Buffer Register contains the oldest received byte in the UARTn Rx FIFO." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x000" size="4" name="THR" access="WriteOnly" description="Transmit Holding Regiter. The next character to be transmitted is written here (DLAB =0)." reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="8" name="THR" description="Writing to the UARTn Transmit Holding Register causes the data to be stored in the UARTn transmit FIFO. The byte will be sent when it reaches the bottom of the FIFO and the transmitter is available." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x000" size="4" name="DLL" access="Read/Write" description="Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB =1)." reset_value="0x01" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="DLLSB" description="The UARTn Divisor Latch LSB Register, along with the UnDLM register, determines the baud rate of the UARTn." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x004" size="4" name="DLM" access="Read/Write" description="Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB =1)." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="DLMSB" description="The UARTn Divisor Latch MSB Register, along with the U0DLL register, determines the baud rate of the UARTn." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x004" size="4" name="IER" access="Read/Write" description="Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential UART interrupts (DLAB =0)." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RBRIE" description="RBR Interrupt Enable. Enables the Receive Data Available interrupt for UARTn. It also controls the Character Receive Time-out interrupt."> + <Enum name="DISABLE_THE_RDA_INTE" start="0" description="Disable the RDA interrupts." /> + <Enum name="ENABLE_THE_RDA_INTER" start="1" description="Enable the RDA interrupts." /> + </BitField> + <BitField start="1" size="1" name="THREIE" description="THRE Interrupt Enable. Enables the THRE interrupt for UARTn. The status of this can be read from UnLSR[5]."> + <Enum name="DISABLE_THE_THRE_INT" start="0" description="Disable the THRE interrupts." /> + <Enum name="ENABLE_THE_THRE_INTE" start="1" description="Enable the THRE interrupts." /> + </BitField> + <BitField start="2" size="1" name="RXIE" description="RX Line Status Interrupt Enable. Enables the UARTn RX line status interrupts. The status of this interrupt can be read from UnLSR[4:1]."> + <Enum name="DISABLE_THE_RX_LINE_" start="0" description="Disable the RX line status interrupts." /> + <Enum name="ENABLE_THE_RX_LINE_S" start="1" description="Enable the RX line status interrupts." /> + </BitField> + <BitField start="3" size="5" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="8" size="1" name="ABEOINTEN" description="Enables the end of auto-baud interrupt."> + <Enum name="DISABLE_END_OF_AUTO_" start="0" description="Disable end of auto-baud Interrupt." /> + <Enum name="ENABLE_END_OF_AUTO_B" start="1" description="Enable end of auto-baud Interrupt." /> + </BitField> + <BitField start="9" size="1" name="ABTOINTEN" description="Enables the auto-baud time-out interrupt."> + <Enum name="DISABLE_AUTO_BAUD_TI" start="0" description="Disable auto-baud time-out Interrupt." /> + <Enum name="ENABLE_AUTO_BAUD_TIM" start="1" description="Enable auto-baud time-out Interrupt." /> + </BitField> + <BitField start="10" size="22" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x008" size="4" name="IIR" access="ReadOnly" description="Interrupt ID Register. Identifies which interrupt(s) are pending." reset_value="0x01" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="INTSTATUS" description="Interrupt status. Note that UnIIR[0] is active low. The pending interrupt can be determined by evaluating UnIIR[3:1]."> + <Enum name="AT_LEAST_ONE_INTERRU" start="0" description="At least one interrupt is pending." /> + <Enum name="NO_INTERRUPT_IS_PEND" start="1" description="No interrupt is pending." /> + </BitField> + <BitField start="1" size="3" name="INTID" description="Interrupt identification. UnIER[3:1] identifies an interrupt corresponding to the UARTn Rx or TX FIFO. All other combinations of UnIER[3:1] not listed below are reserved (000,100,101,111)."> + <Enum name="1_RECEIVE_LINE_S" start="0x3" description="1 - Receive Line Status (RLS)." /> + <Enum name="2A__RECEIVE_DATA_AV" start="0x2" description="2a - Receive Data Available (RDA)." /> + <Enum name="2B__CHARACTER_TIME_" start="0x6" description="2b - Character Time-out Indicator (CTI)." /> + <Enum name="3_THRE_INTERRUPT" start="0x1" description="3 - THRE Interrupt" /> + </BitField> + <BitField start="4" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="6" size="2" name="FIFOENABLE" description="Copies of UnFCR[0]." /> + <BitField start="8" size="1" name="ABEOINT" description="End of auto-baud interrupt. True if auto-baud has finished successfully and interrupt is enabled." /> + <BitField start="9" size="1" name="ABTOINT" description="Auto-baud time-out interrupt. True if auto-baud has timed out and interrupt is enabled." /> + <BitField start="10" size="22" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x008" size="4" name="FCR" access="WriteOnly" description="FIFO Control Register. Controls UART FIFO usage and modes." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="FIFOEN" description="FIFO Enable."> + <Enum name="UARTN_FIFOS_ARE_DISA" start="0" description="UARTn FIFOs are disabled. Must not be used in the application." /> + <Enum name="ACTIVE_HIGH_ENABLE_F" start="1" description="Active high enable for both UARTn Rx and TX FIFOs and UnFCR[7:1] access. This bit must be set for proper UART operation. Any transition on this bit will automatically clear the related UART FIFOs." /> + </BitField> + <BitField start="1" size="1" name="RXFIFORES" description="RX FIFO Reset."> + <Enum name="NO_IMPACT_ON_EITHER_" start="0" description="No impact on either of UARTn FIFOs." /> + <Enum name="WRITING_A_LOGIC_1_TO" start="1" description="Writing a logic 1 to UnFCR[1] will clear all bytes in UARTn Rx FIFO, reset the pointer logic. This bit is self-clearing." /> + </BitField> + <BitField start="2" size="1" name="TXFIFORES" description="TX FIFO Reset."> + <Enum name="NO_IMPACT_ON_EITHER_" start="0" description="No impact on either of UARTn FIFOs." /> + <Enum name="WRITING_A_LOGIC_1_TO" start="1" description="Writing a logic 1 to UnFCR[2] will clear all bytes in UARTn TX FIFO, reset the pointer logic. This bit is self-clearing." /> + </BitField> + <BitField start="3" size="1" name="DMAMODE" description="DMA Mode Select. When the FIFO enable (bit 0 of this register) is set, this bit selects the DMA mode. See Section 18.6.6.1." /> + <BitField start="4" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="6" size="2" name="RXTRIGLVL" description="RX Trigger Level. These two bits determine how many receiver UARTn FIFO characters must be written before an interrupt or DMA request is activated."> + <Enum name="TRIGGER_LEVEL_0_1_C" start="0x0" description="Trigger level 0 (1 character or 0x01)." /> + <Enum name="TRIGGER_LEVEL_1_4_C" start="0x1" description="Trigger level 1 (4 characters or 0x04)." /> + <Enum name="TRIGGER_LEVEL_2_8_C" start="0x2" description="Trigger level 2 (8 characters or 0x08)." /> + <Enum name="TRIGGER_LEVEL_3_14_" start="0x3" description="Trigger level 3 (14 characters or 0x0E)." /> + </BitField> + <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x00C" size="4" name="LCR" access="Read/Write" description="Line Control Register. Contains controls for frame formatting and break generation." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="WLS" description="Word Length Select."> + <Enum name="5_BIT_CHARACTER_LENG" start="0x0" description="5-bit character length" /> + <Enum name="6_BIT_CHARACTER_LENG" start="0x1" description="6-bit character length" /> + <Enum name="7_BIT_CHARACTER_LENG" start="0x2" description="7-bit character length" /> + <Enum name="8_BIT_CHARACTER_LENG" start="0x3" description="8-bit character length" /> + </BitField> + <BitField start="2" size="1" name="SBS" description="Stop Bit Select"> + <Enum name="1_STOP_BIT_" start="0" description="1 stop bit." /> + <Enum name="2_STOP_BITS_1_5_IF_" start="1" description="2 stop bits (1.5 if UnLCR[1:0]=00)." /> + </BitField> + <BitField start="3" size="1" name="PE" description="Parity Enable."> + <Enum name="DISABLE_PARITY_GENER" start="0" description="Disable parity generation and checking." /> + <Enum name="ENABLE_PARITY_GENERA" start="1" description="Enable parity generation and checking." /> + </BitField> + <BitField start="4" size="2" name="PS" description="Parity Select"> + <Enum name="ODD_PARITY_NUMBER_O" start="0x0" description="Odd parity. Number of 1s in the transmitted character and the attached parity bit will be odd." /> + <Enum name="EVEN_PARITY_NUMBER_" start="0x1" description="Even Parity. Number of 1s in the transmitted character and the attached parity bit will be even." /> + <Enum name="FORCED_1_STICK_PARIT" start="0x2" description="Forced 1 stick parity." /> + <Enum name="FORCED_0_STICK_PARIT" start="0x3" description="Forced 0 stick parity." /> + </BitField> + <BitField start="6" size="1" name="BC" description="Break Control"> + <Enum name="DISABLE_BREAK_TRANSM" start="0" description="Disable break transmission." /> + <Enum name="ENABLE_BREAK_TRANSMI" start="1" description="Enable break transmission. Output pin UARTn TXD is forced to logic 0 when UnLCR[6] is active high." /> + </BitField> + <BitField start="7" size="1" name="DLAB" description="Divisor Latch Access Bit"> + <Enum name="DISABLE_ACCESS_TO_DI" start="0" description="Disable access to Divisor Latches." /> + <Enum name="ENABLE_ACCESS_TO_DIV" start="1" description="Enable access to Divisor Latches." /> + </BitField> + <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x014" size="4" name="LSR" access="None" description="Line Status Register. Contains flags for transmit and receive status, including line errors." reset_value="0x60" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RDR" description="Receiver Data Ready. UnLSR[0] is set when the UnRBR holds an unread character and is cleared when the UARTn RBR FIFO is empty."> + <Enum name="EMPTY" start="0" description="The UARTn receiver FIFO is empty." /> + <Enum name="NOTEMPTY" start="1" description="The UARTn receiver FIFO is not empty." /> + </BitField> + <BitField start="1" size="1" name="OE" description="Overrun Error. The overrun error condition is set as soon as it occurs. An UnLSR read clears UnLSR[1]. UnLSR[1] is set when UARTn RSR has a new character assembled and the UARTn RBR FIFO is full. In this case, the UARTn RBR FIFO will not be overwritten and the character in the UARTn RSR will be lost."> + <Enum name="INACTIVE" start="0" description="Overrun error status is inactive." /> + <Enum name="ACTIVE" start="1" description="Overrun error status is active." /> + </BitField> + <BitField start="2" size="1" name="PE" description="Parity Error. When the parity bit of a received character is in the wrong state, a parity error occurs. An UnLSR read clears UnLSR[2]. Time of parity error detection is dependent on UnFCR[0]. Note: A parity error is associated with the character at the top of the UARTn RBR FIFO."> + <Enum name="INACTIVE" start="0" description="Parity error status is inactive." /> + <Enum name="ACTIVE" start="1" description="Parity error status is active." /> + </BitField> + <BitField start="3" size="1" name="FE" description="Framing Error. When the stop bit of a received character is a logic 0, a framing error occurs. An UnLSR read clears UnLSR[3]. The time of the framing error detection is dependent on UnFCR[0]. Upon detection of a framing error, the Rx will attempt to resynchronize to the data and assume that the bad stop bit is actually an early start bit. However, it cannot be assumed that the next received byte will be correct even if there is no Framing Error. Note: A framing error is associated with the character at the top of the UARTn RBR FIFO."> + <Enum name="INACTIVE" start="0" description="Framing error status is inactive." /> + <Enum name="ACTIVE" start="1" description="Framing error status is active." /> + </BitField> + <BitField start="4" size="1" name="BI" description="Break Interrupt. When RXDn is held in the spacing state (all zeroes) for one full character transmission (start, data, parity, stop), a break interrupt occurs. Once the break condition has been detected, the receiver goes idle until RXDn goes to marking state (all ones). An UnLSR read clears this status bit. The time of break detection is dependent on UnFCR[0]. Note: The break interrupt is associated with the character at the top of the UARTn RBR FIFO."> + <Enum name="INACTIVE" start="0" description="Break interrupt status is inactive." /> + <Enum name="ACTIVE" start="1" description="Break interrupt status is active." /> + </BitField> + <BitField start="5" size="1" name="THRE" description="Transmitter Holding Register Empty. THRE is set immediately upon detection of an empty UARTn THR and is cleared on a UnTHR write."> + <Enum name="VALIDDATA" start="0" description="UnTHR contains valid data." /> + <Enum name="EMPTY" start="1" description="UnTHR is empty." /> + </BitField> + <BitField start="6" size="1" name="TEMT" description="Transmitter Empty. TEMT is set when both UnTHR and UnTSR are empty; TEMT is cleared when either the UnTSR or the UnTHR contain valid data."> + <Enum name="VALIDDATA" start="0" description="UnTHR and/or the UnTSR contains valid data." /> + <Enum name="EMPTY" start="1" description="UnTHR and the UnTSR are empty." /> + </BitField> + <BitField start="7" size="1" name="RXFE" description="Error in RX FIFO . UnLSR[7] is set when a character with a Rx error such as framing error, parity error or break interrupt, is loaded into the UnRBR. This bit is cleared when the UnLSR register is read and there are no subsequent errors in the UARTn FIFO."> + <Enum name="NOERROR" start="0" description="UnRBR contains no UARTn RX errors or UnFCR[0]=0." /> + <Enum name="ERRORS" start="1" description="UARTn RBR contains at least one UARTn RX error." /> + </BitField> + <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x01C" size="4" name="SCR" access="Read/Write" description="Scratch Pad Register. 8-bit temporary storage for software." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="PAD" description="A readable, writable byte." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x020" size="4" name="ACR" access="Read/Write" description="Auto-baud Control Register. Contains controls for the auto-baud feature." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="START" description="Start bit. This bit is automatically cleared after auto-baud completion."> + <Enum name="AUTO_BAUD_STOP_AUTO" start="0" description="Auto-baud stop (auto-baud is not running)." /> + <Enum name="AUTO_BAUD_START_AUT" start="1" description="Auto-baud start (auto-baud is running). Auto-baud run bit. This bit is automatically cleared after auto-baud completion." /> + </BitField> + <BitField start="1" size="1" name="MODE" description="Auto-baud mode select bit."> + <Enum name="MODE_0_" start="0" description="Mode 0." /> + <Enum name="MODE_1_" start="1" description="Mode 1." /> + </BitField> + <BitField start="2" size="1" name="AUTORESTART" description="Restart bit."> + <Enum name="NO_RESTART_" start="0" description="No restart." /> + <Enum name="RESTART_IN_CASE_OF_T" start="1" description="Restart in case of time-out (counter restarts at next UARTn Rx falling edge)" /> + </BitField> + <BitField start="3" size="5" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="8" size="1" name="ABEOINTCLR" description="End of auto-baud interrupt clear bit (write-only accessible). Writing a 1 will clear the corresponding interrupt in the UnIIR. Writing a 0 has no impact."> + <Enum name="NO_IMPACT_" start="0" description="No impact." /> + <Enum name="CLEAR_THE_CORRESPOND" start="1" description="Clear the corresponding interrupt in the IIR." /> + </BitField> + <BitField start="9" size="1" name="ABTOINTCLR" description="Auto-baud time-out interrupt clear bit (write-only accessible). Writing a 1 will clear the corresponding interrupt in the UnIIR. Writing a 0 has no impact."> + <Enum name="NO_IMPACT_" start="0" description="No impact." /> + <Enum name="CLEAR_THE_CORRESPOND" start="1" description="Clear the corresponding interrupt in the IIR." /> + </BitField> + <BitField start="10" size="22" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x028" size="4" name="FDR" access="Read/Write" description="Fractional Divider Register. Generates a clock input for the baud rate divider." reset_value="0x10" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="4" name="DIVADDVAL" description="Baud-rate generation pre-scaler divisor value. If this field is 0, fractional baud-rate generator will not impact the UARTn baudrate." /> + <BitField start="4" size="4" name="MULVAL" description="Baud-rate pre-scaler multiplier value. This field must be greater or equal 1 for UARTn to operate properly, regardless of whether the fractional baud-rate generator is used or not." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x030" size="4" name="TER" access="Read/Write" description="Transmit Enable Register. Turns off UART transmitter for use with software flow control." reset_value="0x80" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="7" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="7" size="1" name="TXEN" description="When this bit is 1, as it is after a Reset, data written to the THR is output on the TXD pin as soon as any preceding data has been sent. If this bit is cleared to 0 while a character is being sent, the transmission of that character is completed, but no further characters are sent until this bit is set again. In other words, a 0 in this bit blocks the transfer of characters from the THR or TX FIFO into the transmit shift register. Software implementing software-handshaking can clear this bit when it receives an XOFF character (DC3). Software can set this bit again when it receives an XON (DC1) character." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x04C" size="4" name="RS485CTRL" access="Read/Write" description="RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="NMMEN" description="NMM enable."> + <Enum name="DISABLED" start="0" description="RS-485/EIA-485 Normal Multidrop Mode (NMM) is disabled." /> + <Enum name="ENABLED" start="1" description="RS-485/EIA-485 Normal Multidrop Mode (NMM) is enabled. In this mode, an address is detected when a received byte has the parity bit = 1, generating a received data interrupt. See Section 18.6.16 RS-485/EIA-485 modes of operation." /> + </BitField> + <BitField start="1" size="1" name="RXDIS" description="Receiver enable."> + <Enum name="ENABLED" start="0" description="The receiver is enabled." /> + <Enum name="DISABLED" start="1" description="The receiver is disabled." /> + </BitField> + <BitField start="2" size="1" name="AADEN" description="AAD enable."> + <Enum name="DISABLED" start="0" description="Auto Address Detect (AAD) is disabled." /> + <Enum name="ENABLED" start="1" description="Auto Address Detect (AAD) is enabled." /> + </BitField> + <BitField start="3" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="4" size="1" name="DCTRL" description="Direction control enable."> + <Enum name="DISABLE_AUTO_DIRECTI" start="0" description="Disable Auto Direction Control." /> + <Enum name="ENABLE_AUTO_DIRECTIO" start="1" description="Enable Auto Direction Control." /> + </BitField> + <BitField start="5" size="1" name="OINV" description="Direction control pin polarity. This bit reverses the polarity of the direction control signal on the Un_OE pin."> + <Enum name="DIRLOW" start="0" description="The direction control pin will be driven to logic 0 when the transmitter has data to be sent. It will be driven to logic 1 after the last bit of data has been transmitted." /> + <Enum name="DIRHIGH" start="1" description="The direction control pin will be driven to logic 1 when the transmitter has data to be sent. It will be driven to logic 0 after the last bit of data has been transmitted." /> + </BitField> + <BitField start="6" size="26" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x050" size="4" name="RS485ADRMATCH" access="Read/Write" description="RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="ADRMATCH" description="Contains the address match value." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x054" size="4" name="RS485DLY" access="Read/Write" description="RS-485/EIA-485 direction control delay." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="DLY" description="Contains the direction control (UnOE) delay value. This register works in conjunction with an 8-bit counter." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + </RegisterGroup> + <RegisterGroup name="UART3" start="0x4009C000" description="UART0/2/3 "> + <Register start="+0x000" size="4" name="RBR" access="None" description="Receiver Buffer Register. Contains the next received character to be read (DLAB =0)." reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="8" name="RBR" description="The UARTn Receiver Buffer Register contains the oldest received byte in the UARTn Rx FIFO." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x000" size="4" name="THR" access="WriteOnly" description="Transmit Holding Regiter. The next character to be transmitted is written here (DLAB =0)." reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="8" name="THR" description="Writing to the UARTn Transmit Holding Register causes the data to be stored in the UARTn transmit FIFO. The byte will be sent when it reaches the bottom of the FIFO and the transmitter is available." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x000" size="4" name="DLL" access="Read/Write" description="Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB =1)." reset_value="0x01" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="DLLSB" description="The UARTn Divisor Latch LSB Register, along with the UnDLM register, determines the baud rate of the UARTn." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x004" size="4" name="DLM" access="Read/Write" description="Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB =1)." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="DLMSB" description="The UARTn Divisor Latch MSB Register, along with the U0DLL register, determines the baud rate of the UARTn." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x004" size="4" name="IER" access="Read/Write" description="Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential UART interrupts (DLAB =0)." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RBRIE" description="RBR Interrupt Enable. Enables the Receive Data Available interrupt for UARTn. It also controls the Character Receive Time-out interrupt."> + <Enum name="DISABLE_THE_RDA_INTE" start="0" description="Disable the RDA interrupts." /> + <Enum name="ENABLE_THE_RDA_INTER" start="1" description="Enable the RDA interrupts." /> + </BitField> + <BitField start="1" size="1" name="THREIE" description="THRE Interrupt Enable. Enables the THRE interrupt for UARTn. The status of this can be read from UnLSR[5]."> + <Enum name="DISABLE_THE_THRE_INT" start="0" description="Disable the THRE interrupts." /> + <Enum name="ENABLE_THE_THRE_INTE" start="1" description="Enable the THRE interrupts." /> + </BitField> + <BitField start="2" size="1" name="RXIE" description="RX Line Status Interrupt Enable. Enables the UARTn RX line status interrupts. The status of this interrupt can be read from UnLSR[4:1]."> + <Enum name="DISABLE_THE_RX_LINE_" start="0" description="Disable the RX line status interrupts." /> + <Enum name="ENABLE_THE_RX_LINE_S" start="1" description="Enable the RX line status interrupts." /> + </BitField> + <BitField start="3" size="5" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="8" size="1" name="ABEOINTEN" description="Enables the end of auto-baud interrupt."> + <Enum name="DISABLE_END_OF_AUTO_" start="0" description="Disable end of auto-baud Interrupt." /> + <Enum name="ENABLE_END_OF_AUTO_B" start="1" description="Enable end of auto-baud Interrupt." /> + </BitField> + <BitField start="9" size="1" name="ABTOINTEN" description="Enables the auto-baud time-out interrupt."> + <Enum name="DISABLE_AUTO_BAUD_TI" start="0" description="Disable auto-baud time-out Interrupt." /> + <Enum name="ENABLE_AUTO_BAUD_TIM" start="1" description="Enable auto-baud time-out Interrupt." /> + </BitField> + <BitField start="10" size="22" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x008" size="4" name="IIR" access="ReadOnly" description="Interrupt ID Register. Identifies which interrupt(s) are pending." reset_value="0x01" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="INTSTATUS" description="Interrupt status. Note that UnIIR[0] is active low. The pending interrupt can be determined by evaluating UnIIR[3:1]."> + <Enum name="AT_LEAST_ONE_INTERRU" start="0" description="At least one interrupt is pending." /> + <Enum name="NO_INTERRUPT_IS_PEND" start="1" description="No interrupt is pending." /> + </BitField> + <BitField start="1" size="3" name="INTID" description="Interrupt identification. UnIER[3:1] identifies an interrupt corresponding to the UARTn Rx or TX FIFO. All other combinations of UnIER[3:1] not listed below are reserved (000,100,101,111)."> + <Enum name="1_RECEIVE_LINE_S" start="0x3" description="1 - Receive Line Status (RLS)." /> + <Enum name="2A__RECEIVE_DATA_AV" start="0x2" description="2a - Receive Data Available (RDA)." /> + <Enum name="2B__CHARACTER_TIME_" start="0x6" description="2b - Character Time-out Indicator (CTI)." /> + <Enum name="3_THRE_INTERRUPT" start="0x1" description="3 - THRE Interrupt" /> + </BitField> + <BitField start="4" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="6" size="2" name="FIFOENABLE" description="Copies of UnFCR[0]." /> + <BitField start="8" size="1" name="ABEOINT" description="End of auto-baud interrupt. True if auto-baud has finished successfully and interrupt is enabled." /> + <BitField start="9" size="1" name="ABTOINT" description="Auto-baud time-out interrupt. True if auto-baud has timed out and interrupt is enabled." /> + <BitField start="10" size="22" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x008" size="4" name="FCR" access="WriteOnly" description="FIFO Control Register. Controls UART FIFO usage and modes." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="FIFOEN" description="FIFO Enable."> + <Enum name="UARTN_FIFOS_ARE_DISA" start="0" description="UARTn FIFOs are disabled. Must not be used in the application." /> + <Enum name="ACTIVE_HIGH_ENABLE_F" start="1" description="Active high enable for both UARTn Rx and TX FIFOs and UnFCR[7:1] access. This bit must be set for proper UART operation. Any transition on this bit will automatically clear the related UART FIFOs." /> + </BitField> + <BitField start="1" size="1" name="RXFIFORES" description="RX FIFO Reset."> + <Enum name="NO_IMPACT_ON_EITHER_" start="0" description="No impact on either of UARTn FIFOs." /> + <Enum name="WRITING_A_LOGIC_1_TO" start="1" description="Writing a logic 1 to UnFCR[1] will clear all bytes in UARTn Rx FIFO, reset the pointer logic. This bit is self-clearing." /> + </BitField> + <BitField start="2" size="1" name="TXFIFORES" description="TX FIFO Reset."> + <Enum name="NO_IMPACT_ON_EITHER_" start="0" description="No impact on either of UARTn FIFOs." /> + <Enum name="WRITING_A_LOGIC_1_TO" start="1" description="Writing a logic 1 to UnFCR[2] will clear all bytes in UARTn TX FIFO, reset the pointer logic. This bit is self-clearing." /> + </BitField> + <BitField start="3" size="1" name="DMAMODE" description="DMA Mode Select. When the FIFO enable (bit 0 of this register) is set, this bit selects the DMA mode. See Section 18.6.6.1." /> + <BitField start="4" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="6" size="2" name="RXTRIGLVL" description="RX Trigger Level. These two bits determine how many receiver UARTn FIFO characters must be written before an interrupt or DMA request is activated."> + <Enum name="TRIGGER_LEVEL_0_1_C" start="0x0" description="Trigger level 0 (1 character or 0x01)." /> + <Enum name="TRIGGER_LEVEL_1_4_C" start="0x1" description="Trigger level 1 (4 characters or 0x04)." /> + <Enum name="TRIGGER_LEVEL_2_8_C" start="0x2" description="Trigger level 2 (8 characters or 0x08)." /> + <Enum name="TRIGGER_LEVEL_3_14_" start="0x3" description="Trigger level 3 (14 characters or 0x0E)." /> + </BitField> + <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x00C" size="4" name="LCR" access="Read/Write" description="Line Control Register. Contains controls for frame formatting and break generation." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="WLS" description="Word Length Select."> + <Enum name="5_BIT_CHARACTER_LENG" start="0x0" description="5-bit character length" /> + <Enum name="6_BIT_CHARACTER_LENG" start="0x1" description="6-bit character length" /> + <Enum name="7_BIT_CHARACTER_LENG" start="0x2" description="7-bit character length" /> + <Enum name="8_BIT_CHARACTER_LENG" start="0x3" description="8-bit character length" /> + </BitField> + <BitField start="2" size="1" name="SBS" description="Stop Bit Select"> + <Enum name="1_STOP_BIT_" start="0" description="1 stop bit." /> + <Enum name="2_STOP_BITS_1_5_IF_" start="1" description="2 stop bits (1.5 if UnLCR[1:0]=00)." /> + </BitField> + <BitField start="3" size="1" name="PE" description="Parity Enable."> + <Enum name="DISABLE_PARITY_GENER" start="0" description="Disable parity generation and checking." /> + <Enum name="ENABLE_PARITY_GENERA" start="1" description="Enable parity generation and checking." /> + </BitField> + <BitField start="4" size="2" name="PS" description="Parity Select"> + <Enum name="ODD_PARITY_NUMBER_O" start="0x0" description="Odd parity. Number of 1s in the transmitted character and the attached parity bit will be odd." /> + <Enum name="EVEN_PARITY_NUMBER_" start="0x1" description="Even Parity. Number of 1s in the transmitted character and the attached parity bit will be even." /> + <Enum name="FORCED_1_STICK_PARIT" start="0x2" description="Forced 1 stick parity." /> + <Enum name="FORCED_0_STICK_PARIT" start="0x3" description="Forced 0 stick parity." /> + </BitField> + <BitField start="6" size="1" name="BC" description="Break Control"> + <Enum name="DISABLE_BREAK_TRANSM" start="0" description="Disable break transmission." /> + <Enum name="ENABLE_BREAK_TRANSMI" start="1" description="Enable break transmission. Output pin UARTn TXD is forced to logic 0 when UnLCR[6] is active high." /> + </BitField> + <BitField start="7" size="1" name="DLAB" description="Divisor Latch Access Bit"> + <Enum name="DISABLE_ACCESS_TO_DI" start="0" description="Disable access to Divisor Latches." /> + <Enum name="ENABLE_ACCESS_TO_DIV" start="1" description="Enable access to Divisor Latches." /> + </BitField> + <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x014" size="4" name="LSR" access="None" description="Line Status Register. Contains flags for transmit and receive status, including line errors." reset_value="0x60" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RDR" description="Receiver Data Ready. UnLSR[0] is set when the UnRBR holds an unread character and is cleared when the UARTn RBR FIFO is empty."> + <Enum name="EMPTY" start="0" description="The UARTn receiver FIFO is empty." /> + <Enum name="NOTEMPTY" start="1" description="The UARTn receiver FIFO is not empty." /> + </BitField> + <BitField start="1" size="1" name="OE" description="Overrun Error. The overrun error condition is set as soon as it occurs. An UnLSR read clears UnLSR[1]. UnLSR[1] is set when UARTn RSR has a new character assembled and the UARTn RBR FIFO is full. In this case, the UARTn RBR FIFO will not be overwritten and the character in the UARTn RSR will be lost."> + <Enum name="INACTIVE" start="0" description="Overrun error status is inactive." /> + <Enum name="ACTIVE" start="1" description="Overrun error status is active." /> + </BitField> + <BitField start="2" size="1" name="PE" description="Parity Error. When the parity bit of a received character is in the wrong state, a parity error occurs. An UnLSR read clears UnLSR[2]. Time of parity error detection is dependent on UnFCR[0]. Note: A parity error is associated with the character at the top of the UARTn RBR FIFO."> + <Enum name="INACTIVE" start="0" description="Parity error status is inactive." /> + <Enum name="ACTIVE" start="1" description="Parity error status is active." /> + </BitField> + <BitField start="3" size="1" name="FE" description="Framing Error. When the stop bit of a received character is a logic 0, a framing error occurs. An UnLSR read clears UnLSR[3]. The time of the framing error detection is dependent on UnFCR[0]. Upon detection of a framing error, the Rx will attempt to resynchronize to the data and assume that the bad stop bit is actually an early start bit. However, it cannot be assumed that the next received byte will be correct even if there is no Framing Error. Note: A framing error is associated with the character at the top of the UARTn RBR FIFO."> + <Enum name="INACTIVE" start="0" description="Framing error status is inactive." /> + <Enum name="ACTIVE" start="1" description="Framing error status is active." /> + </BitField> + <BitField start="4" size="1" name="BI" description="Break Interrupt. When RXDn is held in the spacing state (all zeroes) for one full character transmission (start, data, parity, stop), a break interrupt occurs. Once the break condition has been detected, the receiver goes idle until RXDn goes to marking state (all ones). An UnLSR read clears this status bit. The time of break detection is dependent on UnFCR[0]. Note: The break interrupt is associated with the character at the top of the UARTn RBR FIFO."> + <Enum name="INACTIVE" start="0" description="Break interrupt status is inactive." /> + <Enum name="ACTIVE" start="1" description="Break interrupt status is active." /> + </BitField> + <BitField start="5" size="1" name="THRE" description="Transmitter Holding Register Empty. THRE is set immediately upon detection of an empty UARTn THR and is cleared on a UnTHR write."> + <Enum name="VALIDDATA" start="0" description="UnTHR contains valid data." /> + <Enum name="EMPTY" start="1" description="UnTHR is empty." /> + </BitField> + <BitField start="6" size="1" name="TEMT" description="Transmitter Empty. TEMT is set when both UnTHR and UnTSR are empty; TEMT is cleared when either the UnTSR or the UnTHR contain valid data."> + <Enum name="VALIDDATA" start="0" description="UnTHR and/or the UnTSR contains valid data." /> + <Enum name="EMPTY" start="1" description="UnTHR and the UnTSR are empty." /> + </BitField> + <BitField start="7" size="1" name="RXFE" description="Error in RX FIFO . UnLSR[7] is set when a character with a Rx error such as framing error, parity error or break interrupt, is loaded into the UnRBR. This bit is cleared when the UnLSR register is read and there are no subsequent errors in the UARTn FIFO."> + <Enum name="NOERROR" start="0" description="UnRBR contains no UARTn RX errors or UnFCR[0]=0." /> + <Enum name="ERRORS" start="1" description="UARTn RBR contains at least one UARTn RX error." /> + </BitField> + <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x01C" size="4" name="SCR" access="Read/Write" description="Scratch Pad Register. 8-bit temporary storage for software." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="PAD" description="A readable, writable byte." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x020" size="4" name="ACR" access="Read/Write" description="Auto-baud Control Register. Contains controls for the auto-baud feature." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="START" description="Start bit. This bit is automatically cleared after auto-baud completion."> + <Enum name="AUTO_BAUD_STOP_AUTO" start="0" description="Auto-baud stop (auto-baud is not running)." /> + <Enum name="AUTO_BAUD_START_AUT" start="1" description="Auto-baud start (auto-baud is running). Auto-baud run bit. This bit is automatically cleared after auto-baud completion." /> + </BitField> + <BitField start="1" size="1" name="MODE" description="Auto-baud mode select bit."> + <Enum name="MODE_0_" start="0" description="Mode 0." /> + <Enum name="MODE_1_" start="1" description="Mode 1." /> + </BitField> + <BitField start="2" size="1" name="AUTORESTART" description="Restart bit."> + <Enum name="NO_RESTART_" start="0" description="No restart." /> + <Enum name="RESTART_IN_CASE_OF_T" start="1" description="Restart in case of time-out (counter restarts at next UARTn Rx falling edge)" /> + </BitField> + <BitField start="3" size="5" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="8" size="1" name="ABEOINTCLR" description="End of auto-baud interrupt clear bit (write-only accessible). Writing a 1 will clear the corresponding interrupt in the UnIIR. Writing a 0 has no impact."> + <Enum name="NO_IMPACT_" start="0" description="No impact." /> + <Enum name="CLEAR_THE_CORRESPOND" start="1" description="Clear the corresponding interrupt in the IIR." /> + </BitField> + <BitField start="9" size="1" name="ABTOINTCLR" description="Auto-baud time-out interrupt clear bit (write-only accessible). Writing a 1 will clear the corresponding interrupt in the UnIIR. Writing a 0 has no impact."> + <Enum name="NO_IMPACT_" start="0" description="No impact." /> + <Enum name="CLEAR_THE_CORRESPOND" start="1" description="Clear the corresponding interrupt in the IIR." /> + </BitField> + <BitField start="10" size="22" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x028" size="4" name="FDR" access="Read/Write" description="Fractional Divider Register. Generates a clock input for the baud rate divider." reset_value="0x10" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="4" name="DIVADDVAL" description="Baud-rate generation pre-scaler divisor value. If this field is 0, fractional baud-rate generator will not impact the UARTn baudrate." /> + <BitField start="4" size="4" name="MULVAL" description="Baud-rate pre-scaler multiplier value. This field must be greater or equal 1 for UARTn to operate properly, regardless of whether the fractional baud-rate generator is used or not." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x030" size="4" name="TER" access="Read/Write" description="Transmit Enable Register. Turns off UART transmitter for use with software flow control." reset_value="0x80" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="7" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="7" size="1" name="TXEN" description="When this bit is 1, as it is after a Reset, data written to the THR is output on the TXD pin as soon as any preceding data has been sent. If this bit is cleared to 0 while a character is being sent, the transmission of that character is completed, but no further characters are sent until this bit is set again. In other words, a 0 in this bit blocks the transfer of characters from the THR or TX FIFO into the transmit shift register. Software implementing software-handshaking can clear this bit when it receives an XOFF character (DC3). Software can set this bit again when it receives an XON (DC1) character." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x04C" size="4" name="RS485CTRL" access="Read/Write" description="RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="NMMEN" description="NMM enable."> + <Enum name="DISABLED" start="0" description="RS-485/EIA-485 Normal Multidrop Mode (NMM) is disabled." /> + <Enum name="ENABLED" start="1" description="RS-485/EIA-485 Normal Multidrop Mode (NMM) is enabled. In this mode, an address is detected when a received byte has the parity bit = 1, generating a received data interrupt. See Section 18.6.16 RS-485/EIA-485 modes of operation." /> + </BitField> + <BitField start="1" size="1" name="RXDIS" description="Receiver enable."> + <Enum name="ENABLED" start="0" description="The receiver is enabled." /> + <Enum name="DISABLED" start="1" description="The receiver is disabled." /> + </BitField> + <BitField start="2" size="1" name="AADEN" description="AAD enable."> + <Enum name="DISABLED" start="0" description="Auto Address Detect (AAD) is disabled." /> + <Enum name="ENABLED" start="1" description="Auto Address Detect (AAD) is enabled." /> + </BitField> + <BitField start="3" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="4" size="1" name="DCTRL" description="Direction control enable."> + <Enum name="DISABLE_AUTO_DIRECTI" start="0" description="Disable Auto Direction Control." /> + <Enum name="ENABLE_AUTO_DIRECTIO" start="1" description="Enable Auto Direction Control." /> + </BitField> + <BitField start="5" size="1" name="OINV" description="Direction control pin polarity. This bit reverses the polarity of the direction control signal on the Un_OE pin."> + <Enum name="DIRLOW" start="0" description="The direction control pin will be driven to logic 0 when the transmitter has data to be sent. It will be driven to logic 1 after the last bit of data has been transmitted." /> + <Enum name="DIRHIGH" start="1" description="The direction control pin will be driven to logic 1 when the transmitter has data to be sent. It will be driven to logic 0 after the last bit of data has been transmitted." /> + </BitField> + <BitField start="6" size="26" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x050" size="4" name="RS485ADRMATCH" access="Read/Write" description="RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="ADRMATCH" description="Contains the address match value." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x054" size="4" name="RS485DLY" access="Read/Write" description="RS-485/EIA-485 direction control delay." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="DLY" description="Contains the direction control (UnOE) delay value. This register works in conjunction with an 8-bit counter." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + </RegisterGroup> + <RegisterGroup name="I2C2" start="0x400A0000" description="I2C bus interface"> + <Register start="+0x000" size="4" name="CONSET" access="Read/Write" description="I2C Control Set Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is set. Writing a zero has no effect on the corresponding bit in the I2C control register." reset_value="0x00" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + <BitField start="2" size="1" name="AA" description="Assert acknowledge flag." /> + <BitField start="3" size="1" name="SI" description="I2C interrupt flag." /> + <BitField start="4" size="1" name="STO" description="STOP flag." /> + <BitField start="5" size="1" name="STA" description="START flag." /> + <BitField start="6" size="1" name="I2EN" description="I2C interface enable." /> + <BitField start="7" size="25" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x004" size="4" name="STAT" access="ReadOnly" description="I2C Status Register. During I2C operation, this register provides detailed status codes that allow software to determine the next action needed." reset_value="0xF8" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="RESERVED" description="These bits are unused and are always 0." /> + <BitField start="3" size="5" name="Status" description="These bits give the actual status information about the I 2C interface." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x008" size="4" name="DAT" access="Read/Write" description="I2C Data Register. During master or slave transmit mode, data to be transmitted is written to this register. During master or slave receive mode, data that has been received may be read from this register." reset_value="0x00" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="Data" description="This register holds data values that have been received or are to be transmitted." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x00C" size="4" name="ADR0" access="Read/Write" description="I2C Slave Address Register 0. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="GC" description="General Call enable bit." /> + <BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x010" size="4" name="SCLH" access="Read/Write" description="SCH Duty Cycle Register High Half Word. Determines the high time of the I2C clock." reset_value="0x04" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="16" name="SCLH" description="Count for SCL HIGH time period selection." /> + <BitField start="16" size="16" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x014" size="4" name="SCLL" access="Read/Write" description="SCL Duty Cycle Register Low Half Word. Determines the low time of the I2C clock. SCLL and SCLH together determine the clock frequency generated by an I2C master and certain times used in slave mode." reset_value="0x04" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="16" name="SCLL" description="Count for SCL low time period selection." /> + <BitField start="16" size="16" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x018" size="4" name="CONCLR" access="WriteOnly" description="I2C Control Clear Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is cleared. Writing a zero has no effect on the corresponding bit in the I2C control register." reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="2" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + <BitField start="2" size="1" name="AAC" description="Assert acknowledge Clear bit." /> + <BitField start="3" size="1" name="SIC" description="I2C interrupt Clear bit." /> + <BitField start="4" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + <BitField start="5" size="1" name="STAC" description="START flag Clear bit." /> + <BitField start="6" size="1" name="I2ENC" description="I2C interface Disable bit." /> + <BitField start="7" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x01C" size="4" name="MMCTRL" access="Read/Write" description="Monitor mode control register." reset_value="0x00" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="MM_ENA" description="Monitor mode enable."> + <Enum name="MONITOR_MODE_DISABLE" start="0" description="Monitor mode disabled." /> + <Enum name="THE_I_2C_MODULE_WILL" start="1" description="The I 2C module will enter monitor mode. In this mode the SDA output will be forced high. This will prevent the I2C module from outputting data of any kind (including ACK) onto the I2C data bus. Depending on the state of the ENA_SCL bit, the output may be also forced high, preventing the module from having control over the I2C clock line." /> + </BitField> + <BitField start="1" size="1" name="ENA_SCL" description="SCL output enable."> + <Enum name="WHEN_THIS_BIT_IS_CLE" start="0" description="When this bit is cleared to 0, the SCL output will be forced high when the module is in monitor mode. As described above, this will prevent the module from having any control over the I2C clock line." /> + <Enum name="WHEN_THIS_BIT_IS_SET" start="1" description="When this bit is set, the I2C module may exercise the same control over the clock line that it would in normal operation. This means that, acting as a slave peripheral, the I2C module can stretch the clock line (hold it low) until it has had time to respond to an I2C interrupt.[1]" /> + </BitField> + <BitField start="2" size="1" name="MATCH_ALL" description="Select interrupt register match."> + <Enum name="WHEN_THIS_BIT_IS_CLE" start="0" description="When this bit is cleared, an interrupt will only be generated when a match occurs to one of the (up-to) four address registers described above. That is, the module will respond as a normal slave as far as address-recognition is concerned." /> + <Enum name="WHEN_THIS_BIT_IS_SET" start="1" description="When this bit is set to 1 and the I2C is in monitor mode, an interrupt will be generated on ANY address received. This will enable the part to monitor all traffic on the bus." /> + </BitField> + <BitField start="3" size="29" name="RESERVED" description="Reserved. The value read from reserved bits is not defined." /> + </Register> + <Register start="+0x020+0" size="4" name="ADR1" access="Read/Write" description="I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="GC" description="General Call enable bit." /> + <BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x020+4" size="4" name="ADR2" access="Read/Write" description="I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="GC" description="General Call enable bit." /> + <BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x020+8" size="4" name="ADR3" access="Read/Write" description="I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="GC" description="General Call enable bit." /> + <BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x02C" size="4" name="DATA_BUFFER" access="ReadOnly" description="Data buffer register. The contents of the 8 MSBs of the DAT shift register will be transferred to the DATA_BUFFER automatically after every nine bits (8 bits of data plus ACK or NACK) has been received on the bus." reset_value="0x00" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="Data" description="This register holds contents of the 8 MSBs of the DAT shift register." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x030+0" size="4" name="MASK[0]" access="Read/Write" description="I2C Slave address mask register" reset_value="0x00" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." /> + <BitField start="1" size="7" name="MASK" description="Mask bits." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x030+4" size="4" name="MASK[1]" access="Read/Write" description="I2C Slave address mask register" reset_value="0x00" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." /> + <BitField start="1" size="7" name="MASK" description="Mask bits." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x030+8" size="4" name="MASK[2]" access="Read/Write" description="I2C Slave address mask register" reset_value="0x00" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." /> + <BitField start="1" size="7" name="MASK" description="Mask bits." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x030+12" size="4" name="MASK[3]" access="Read/Write" description="I2C Slave address mask register" reset_value="0x00" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." /> + <BitField start="1" size="7" name="MASK" description="Mask bits." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + </RegisterGroup> + <RegisterGroup name="UART4" start="0x400A4000" description="UART4 "> + <Register start="+0x000" size="4" name="RBR" access="None" description="Receiver Buffer Register. Contains the next received character to be read (DLAB =0)." reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="8" name="RBR" description="The UART4 Receiver Buffer Register contains the oldest received byte in the UART4 Rx FIFO." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x000" size="4" name="THR" access="WriteOnly" description="Transmit Holding Register. The next character to be transmitted is written here (DLAB =0)." reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="8" name="THR" description="Writing to the UART4 Transmit Holding Register causes the data to be stored in the UART4 transmit FIFO. The byte will be sent when it reaches the bottom of the FIFO and the transmitter is available." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x000" size="4" name="DLL" access="Read/Write" description="Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB =1)." reset_value="0x01" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="DLLSB" description="The UART4 Divisor Latch LSB Register, along with the U4DLM register, determines the baud rate of the UART4." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x004" size="4" name="DLM" access="Read/Write" description="Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB =1)." reset_value="0x01" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="DLMSB" description="The UART4 Divisor Latch MSB Register, along with the U0DLL register, determines the baud rate of the UART4." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x004" size="4" name="IER" access="Read/Write" description="Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential UART interrupts (DLAB =0)." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RBRIE" description="RBR Interrupt Enable. Enables the Receive Data Available interrupt for UARTn. It also controls the Character Receive Time-out interrupt."> + <Enum name="DISABLE_THE_RDA_INTE" start="0" description="Disable the RDA interrupts." /> + <Enum name="ENABLE_THE_RDA_INTER" start="1" description="Enable the RDA interrupts." /> + </BitField> + <BitField start="1" size="1" name="THREIE" description="THRE Interrupt Enable. Enables the THRE interrupt for UARTn. The status of this can be read from UnLSR[5]."> + <Enum name="DISABLE_THE_THRE_INT" start="0" description="Disable the THRE interrupts." /> + <Enum name="ENABLE_THE_THRE_INTE" start="1" description="Enable the THRE interrupts." /> + </BitField> + <BitField start="2" size="1" name="RXIE" description="RX Line Status Interrupt Enable. Enables the UARTn RX line status interrupts. The status of this interrupt can be read from UnLSR[4:1]."> + <Enum name="DISABLE_THE_RX_LINE_" start="0" description="Disable the RX line status interrupts." /> + <Enum name="ENABLE_THE_RX_LINE_S" start="1" description="Enable the RX line status interrupts." /> + </BitField> + <BitField start="3" size="5" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="8" size="1" name="ABEOINTEN" description="Enables the end of auto-baud interrupt."> + <Enum name="DISABLE_END_OF_AUTO_" start="0" description="Disable end of auto-baud Interrupt." /> + <Enum name="ENABLE_END_OF_AUTO_B" start="1" description="Enable end of auto-baud Interrupt." /> + </BitField> + <BitField start="9" size="1" name="ABTOINTEN" description="Enables the auto-baud time-out interrupt."> + <Enum name="DISABLE_AUTO_BAUD_TI" start="0" description="Disable auto-baud time-out Interrupt." /> + <Enum name="ENABLE_AUTO_BAUD_TIM" start="1" description="Enable auto-baud time-out Interrupt." /> + </BitField> + <BitField start="10" size="22" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x008" size="4" name="IIR" access="ReadOnly" description="Interrupt ID Register. Identifies which interrupt(s) are pending." reset_value="0x01" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="INTSTATUS" description="Interrupt status. Note that U4IIR[0] is active low. The pending interrupt can be determined by evaluating U4IIR[3:1]."> + <Enum name="AT_LEAST_ONE_INTERRU" start="0" description="At least one interrupt is pending." /> + <Enum name="NO_INTERRUPT_IS_PEND" start="1" description="No interrupt is pending." /> + </BitField> + <BitField start="1" size="3" name="INTID" description="Interrupt identification. U4IER[3:1] identifies an interrupt corresponding to the UART4 Rx or TX FIFO. All other combinations of U4IER[3:1] not listed below are reserved (000,100,101,111)."> + <Enum name="1_RECEIVE_LINE_S" start="0x3" description="1 - Receive Line Status (RLS)." /> + <Enum name="2A__RECEIVE_DATA_AV" start="0x2" description="2a - Receive Data Available (RDA)." /> + <Enum name="2B__CHARACTER_TIME_" start="0x6" description="2b - Character Time-out Indicator (CTI)." /> + <Enum name="3_THRE_INTERRUPT" start="0x1" description="3 - THRE Interrupt" /> + </BitField> + <BitField start="4" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="6" size="2" name="FIFOENABLE" description="Copies of U4FCR[0]." /> + <BitField start="8" size="1" name="ABEOINT" description="End of auto-baud interrupt. True if auto-baud has finished successfully and interrupt is enabled." /> + <BitField start="9" size="1" name="ABTOINT" description="Auto-baud time-out interrupt. True if auto-baud has timed out and interrupt is enabled." /> + <BitField start="10" size="22" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x008" size="4" name="FCR" access="WriteOnly" description="FIFO Control Register. Controls UART FIFO usage and modes." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="FIFOEN" description="FIFO Enable."> + <Enum name="UARTN_FIFOS_ARE_DISA" start="0" description="UARTn FIFOs are disabled. Must not be used in the application." /> + <Enum name="ACTIVE_HIGH_ENABLE_F" start="1" description="Active high enable for both UARTn Rx and TX FIFOs and UnFCR[7:1] access. This bit must be set for proper UART operation. Any transition on this bit will automatically clear the related UART FIFOs." /> + </BitField> + <BitField start="1" size="1" name="RXFIFORES" description="RX FIFO Reset."> + <Enum name="NO_IMPACT_ON_EITHER_" start="0" description="No impact on either of UARTn FIFOs." /> + <Enum name="WRITING_A_LOGIC_1_TO" start="1" description="Writing a logic 1 to UnFCR[1] will clear all bytes in UARTn Rx FIFO, reset the pointer logic. This bit is self-clearing." /> + </BitField> + <BitField start="2" size="1" name="TXFIFORES" description="TX FIFO Reset."> + <Enum name="NO_IMPACT_ON_EITHER_" start="0" description="No impact on either of UARTn FIFOs." /> + <Enum name="WRITING_A_LOGIC_1_TO" start="1" description="Writing a logic 1 to UnFCR[2] will clear all bytes in UARTn TX FIFO, reset the pointer logic. This bit is self-clearing." /> + </BitField> + <BitField start="3" size="1" name="DMAMODE" description="DMA Mode Select. When the FIFO enable (bit 0 of this register) is set, this bit selects the DMA mode. See Section 20.6.6.1." /> + <BitField start="4" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="6" size="2" name="RXTRIGLVL" description="RX Trigger Level. These two bits determine how many receiver UARTn FIFO characters must be written before an interrupt or DMA request is activated."> + <Enum name="TRIGGER_LEVEL_0_1_C" start="0x0" description="Trigger level 0 (1 character or 0x01)." /> + <Enum name="TRIGGER_LEVEL_1_4_C" start="0x1" description="Trigger level 1 (4 characters or 0x04)." /> + <Enum name="TRIGGER_LEVEL_2_8_C" start="0x2" description="Trigger level 2 (8 characters or 0x08)." /> + <Enum name="TRIGGER_LEVEL_3_14_" start="0x3" description="Trigger level 3 (14 characters or 0x0E)." /> + </BitField> + <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x00C" size="4" name="LCR" access="Read/Write" description="Line Control Register. Contains controls for frame formatting and break generation." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="WLS" description="Word Length Select."> + <Enum name="5_BIT_CHARACTER_LENG" start="0x0" description="5-bit character length" /> + <Enum name="6_BIT_CHARACTER_LENG" start="0x1" description="6-bit character length" /> + <Enum name="7_BIT_CHARACTER_LENG" start="0x2" description="7-bit character length" /> + <Enum name="8_BIT_CHARACTER_LENG" start="0x3" description="8-bit character length" /> + </BitField> + <BitField start="2" size="1" name="SBS" description="Stop Bit Select"> + <Enum name="1_STOP_BIT_" start="0" description="1 stop bit." /> + <Enum name="2_STOP_BITS_1_5_IF_" start="1" description="2 stop bits (1.5 if UnLCR[1:0]=00)." /> + </BitField> + <BitField start="3" size="1" name="PE" description="Parity Enable."> + <Enum name="DISABLE_PARITY_GENER" start="0" description="Disable parity generation and checking." /> + <Enum name="ENABLE_PARITY_GENERA" start="1" description="Enable parity generation and checking." /> + </BitField> + <BitField start="4" size="2" name="PS" description="Parity Select"> + <Enum name="ODD_PARITY_NUMBER_O" start="0x0" description="Odd parity. Number of 1s in the transmitted character and the attached parity bit will be odd." /> + <Enum name="EVEN_PARITY_NUMBER_" start="0x1" description="Even Parity. Number of 1s in the transmitted character and the attached parity bit will be even." /> + <Enum name="FORCED_1_STICK_PARIT" start="0x2" description="Forced 1 stick parity." /> + <Enum name="FORCED_0_STICK_PARIT" start="0x3" description="Forced 0 stick parity." /> + </BitField> + <BitField start="6" size="1" name="BC" description="Break Control"> + <Enum name="DISABLE_BREAK_TRANSM" start="0" description="Disable break transmission." /> + <Enum name="ENABLE_BREAK_TRANSMI" start="1" description="Enable break transmission. Output pin UARTn TXD is forced to logic 0 when UnLCR[6] is active high." /> + </BitField> + <BitField start="7" size="1" name="DLAB" description="Divisor Latch Access Bit"> + <Enum name="DISABLE_ACCESS_TO_DI" start="0" description="Disable access to Divisor Latches." /> + <Enum name="ENABLE_ACCESS_TO_DIV" start="1" description="Enable access to Divisor Latches." /> + </BitField> + <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x014" size="4" name="LSR" access="None" description="Line Status Register. Contains flags for transmit and receive status, including line errors." reset_value="0x60" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RDR" description="Receiver Data Ready. UnLSR[0] is set when the UnRBR holds an unread character and is cleared when the UARTn RBR FIFO is empty."> + <Enum name="THE_UARTN_RECEIVER_F" start="0" description="The UARTn receiver FIFO is empty." /> + <Enum name="THE_UARTN_RECEIVER_F" start="1" description="The UARTn receiver FIFO is not empty." /> + </BitField> + <BitField start="1" size="1" name="OE" description="Overrun Error. The overrun error condition is set as soon as it occurs. An UnLSR read clears UnLSR[1]. UnLSR[1] is set when UARTn RSR has a new character assembled and the UARTn RBR FIFO is full. In this case, the UARTn RBR FIFO will not be overwritten and the character in the UARTn RSR will be lost."> + <Enum name="OVERRUN_ERROR_STATUS" start="0" description="Overrun error status is inactive." /> + <Enum name="OVERRUN_ERROR_STATUS" start="1" description="Overrun error status is active." /> + </BitField> + <BitField start="2" size="1" name="PE" description="Parity Error. When the parity bit of a received character is in the wrong state, a parity error occurs. An UnLSR read clears UnLSR[2]. Time of parity error detection is dependent on UnFCR[0]. Note: A parity error is associated with the character at the top of the UARTn RBR FIFO."> + <Enum name="PARITY_ERROR_STATUS_" start="0" description="Parity error status is inactive." /> + <Enum name="PARITY_ERROR_STATUS_" start="1" description="Parity error status is active." /> + </BitField> + <BitField start="3" size="1" name="FE" description="Framing Error. When the stop bit of a received character is a logic 0, a framing error occurs. An UnLSR read clears UnLSR[3]. The time of the framing error detection is dependent on UnFCR[0]. Upon detection of a framing error, the Rx will attempt to resynchronize to the data and assume that the bad stop bit is actually an early start bit. However, it cannot be assumed that the next received byte will be correct even if there is no Framing Error. Note: A framing error is associated with the character at the top of the UARTn RBR FIFO."> + <Enum name="FRAMING_ERROR_STATUS" start="0" description="Framing error status is inactive." /> + <Enum name="FRAMING_ERROR_STATUS" start="1" description="Framing error status is active." /> + </BitField> + <BitField start="4" size="1" name="BI" description="Break Interrupt. When RXDn is held in the spacing state (all zeroes) for one full character transmission (start, data, parity, stop), a break interrupt occurs. Once the break condition has been detected, the receiver goes idle until RXDn goes to marking state (all ones). An UnLSR read clears this status bit. The time of break detection is dependent on UnFCR[0]. Note: The break interrupt is associated with the character at the top of the UARTn RBR FIFO."> + <Enum name="BREAK_INTERRUPT_STAT" start="0" description="Break interrupt status is inactive." /> + <Enum name="BREAK_INTERRUPT_STAT" start="1" description="Break interrupt status is active." /> + </BitField> + <BitField start="5" size="1" name="THRE" description="Transmitter Holding Register Empty. THRE is set immediately upon detection of an empty UARTn THR and is cleared on a UnTHR write."> + <Enum name="UNTHR_CONTAINS_VALID" start="0" description="UnTHR contains valid data." /> + <Enum name="UNTHR_IS_EMPTY_" start="1" description="UnTHR is empty." /> + </BitField> + <BitField start="6" size="1" name="TEMT" description="Transmitter Empty. TEMT is set when both UnTHR and UnTSR are empty; TEMT is cleared when either the UnTSR or the UnTHR contain valid data."> + <Enum name="VALID_DATA" start="0" description="UnTHR and/or the UnTSR contains valid data." /> + <Enum name="EMPTY" start="1" description="UnTHR and the UnTSR are empty." /> + </BitField> + <BitField start="7" size="1" name="RXFE" description="Error in RX FIFO . UnLSR[7] is set when a character with a Rx error such as framing error, parity error or break interrupt, is loaded into the UnRBR. This bit is cleared when the UnLSR register is read and there are no subsequent errors in the UARTn FIFO."> + <Enum name="UNRBR_CONTAINS_NO_UA" start="0" description="UnRBR contains no UARTn RX errors or UnFCR[0]=0." /> + <Enum name="UARTN_RBR_CONTAINS_A" start="1" description="UARTn RBR contains at least one UARTn RX error." /> + </BitField> + <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x01C" size="4" name="SCR" access="Read/Write" description="Scratch Pad Register. 8-bit temporary storage for software." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="Pad" description="A readable, writable byte." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x020" size="4" name="ACR" access="Read/Write" description="Auto-baud Control Register. Contains controls for the auto-baud feature." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="START" description="Start bit. This bit is automatically cleared after auto-baud completion."> + <Enum name="AUTO_BAUD_STOP_AUTO" start="0" description="Auto-baud stop (auto-baud is not running)." /> + <Enum name="AUTO_BAUD_START_AUT" start="1" description="Auto-baud start (auto-baud is running). Auto-baud run bit. This bit is automatically cleared after auto-baud completion." /> + </BitField> + <BitField start="1" size="1" name="MODE" description="Auto-baud mode select bit."> + <Enum name="MODE_0_" start="0" description="Mode 0." /> + <Enum name="MODE_1_" start="1" description="Mode 1." /> + </BitField> + <BitField start="2" size="1" name="AUTORESTART" description="Restart bit."> + <Enum name="NO_RESTART_" start="0" description="No restart." /> + <Enum name="RESTART_IN_CASE_OF_T" start="1" description="Restart in case of time-out (counter restarts at next UARTn Rx falling edge)" /> + </BitField> + <BitField start="3" size="5" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="8" size="1" name="ABEOINTCLR" description="End of auto-baud interrupt clear bit (write-only accessible). Writing a 1 will clear the corresponding interrupt in the UnIIR. Writing a 0 has no impact."> + <Enum name="NO_IMPACT_" start="0" description="No impact." /> + <Enum name="CLEAR_THE_CORRESPOND" start="1" description="Clear the corresponding interrupt in the IIR." /> + </BitField> + <BitField start="9" size="1" name="ABTOINTCLR" description="Auto-baud time-out interrupt clear bit (write-only accessible). Writing a 1 will clear the corresponding interrupt in the UnIIR. Writing a 0 has no impact."> + <Enum name="NO_IMPACT_" start="0" description="No impact." /> + <Enum name="CLEAR_THE_CORRESPOND" start="1" description="Clear the corresponding interrupt in the IIR." /> + </BitField> + <BitField start="10" size="22" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x024" size="4" name="ICR" access="Read/Write" description="IrDA Control Register. Enables and configures the IrDA mode." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="IRDAEN" description="IrDA mode"> + <Enum name="DISABLED_IRDA_MODE_" start="0" description="Disabled. IrDA mode on UART4 is disabled, UART4 acts as a standard UART." /> + <Enum name="ENABLED_IRDA_MODE_O" start="1" description="Enabled. IrDA mode on UART4 is enabled." /> + </BitField> + <BitField start="1" size="1" name="IRDAINV" description="Serial input direction."> + <Enum name="NOT_INVERTED_" start="0" description="Not inverted." /> + <Enum name="INVERTED_THIS_HAS_N" start="1" description="Inverted. This has no effect on the serial output." /> + </BitField> + <BitField start="2" size="1" name="FIXPULSEEN" description="IrDA fixed pulse width mode."> + <Enum name="DISABLED_" start="0" description="Disabled." /> + <Enum name="ENABLED_" start="1" description="Enabled." /> + </BitField> + <BitField start="3" size="3" name="PULSEDIV" description="Configures the pulse when FixPulseEn = 1."> + <Enum name="2XTPCLK" start="0x0" description="2xTPCLK" /> + <Enum name="4XTPCLK" start="0x1" description="4xTPCLK" /> + <Enum name="8XTPCLK" start="0x2" description="8xTPCLK" /> + <Enum name="16XTPCLK" start="0x3" description="16xTPCLK" /> + <Enum name="32XTPCLK" start="0x4" description="32xTPCLK" /> + <Enum name="64XTPCLK" start="0x5" description="64xTPCLK" /> + <Enum name="128XTPCLK" start="0x6" description="128xTPCLK" /> + <Enum name="256XTPCLK" start="0x7" description="256xTPCLK" /> + </BitField> + <BitField start="6" size="26" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x028" size="4" name="FDR" access="Read/Write" description="Fractional Divider Register. Generates a clock input for the baud rate divider." reset_value="0x10" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="4" name="DIVADDVAL" description="Baud Rate generation pre-scaler divisor value. If this field is 0, fractional baud rate generator will not impact the UART4 baud rate." /> + <BitField start="4" size="4" name="MULVAL" description="Baud Rate pre-scaler multiplier value. This field must be greater or equal 1 for UART4 to operate properly, regardless of whether the fractional baud rate generator is used or not." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x02C" size="4" name="OSR" access="Read/Write" description="Oversampling register. Controls the degree of oversampling during each bit time." reset_value="0xF0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="1" size="3" name="OSFRAC" description="Fractional part of the oversampling ratio, in units of 1/8th of an input clock period. (001 = 0.125, ..., 111 = 0.875)" /> + <BitField start="4" size="4" name="OSINT" description="Integer part of the oversampling ratio, minus 1. The reset values equate to the normal operating mode of 16 input clocks per bit time." /> + <BitField start="8" size="7" name="FDINT" description="In smartcard mode, these bits act as a more-significant extension of the OSint field, allowing an oversampling ratio up to 2048 as required by ISO7816-3. In smartcard mode, bits 14:4 should initially be set to 371, yielding an oversampling ratio of 372." /> + <BitField start="15" size="17" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x048" size="4" name="SCICTRL" access="Read/Write" description="Smart Card Interface control register. Enables and configures the smartcard Interface feature." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="SCIEN" description="Smart Card Interface Enable."> + <Enum name="SMART_CARD_INTERFACE" start="0" description="Smart card interface disabled." /> + <Enum name="ASYNCHRONOUS_HALF_DU" start="1" description="Asynchronous half duplex smart card interface is enabled." /> + </BitField> + <BitField start="1" size="1" name="NACKDIS" description="NACK response disable. Only applicable in T=0."> + <Enum name="A_NACK_RESPONSE_IS_E" start="0" description="A NACK response is enabled." /> + <Enum name="A_NACK_RESPONSE_IS_I" start="1" description="A NACK response is inhibited." /> + </BitField> + <BitField start="2" size="1" name="PROTSEL" description="Protocol selection as defined in the ISO7816-3 standard."> + <Enum name="T_EQ_0" start="0" description="T = 0" /> + <Enum name="T_EQ_1" start="1" description="T = 1" /> + </BitField> + <BitField start="5" size="3" name="TXRETRY" description="Maximum number of retransmissions in case of a negative acknowledge (protocol T=0). When the retry counter is exceeded, the USART will be locked until the FIFO is cleared. A TX error interrupt is generated when enabled." /> + <BitField start="8" size="8" name="GUARDTIME" description="Extra guard time. No extra guard time (0x0) results in a standard guard time as defined in ISO 7816-3, depending on the protocol type. A guard time of 0xFF indicates a minimal guard time as defined for the selected protocol." /> + <BitField start="16" size="16" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x04C" size="4" name="RS485CTRL" access="Read/Write" description="RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="NMMEN" description="NMM enable."> + <Enum name="DISABLED" start="0" description="RS-485/EIA-485 Normal Multidrop Mode (NMM) is disabled." /> + <Enum name="ENABLED" start="1" description="RS-485/EIA-485 Normal Multidrop Mode (NMM) is enabled. In this mode, an address is detected when a received byte causes the USART to set the parity error and generate an interrupt. See Section 20.6.18 RS-485/EIA-485 modes of operation." /> + </BitField> + <BitField start="1" size="1" name="RXDIS" description="Receiver enable."> + <Enum name="ENABLED_" start="0" description="Enabled." /> + <Enum name="DISABLED_" start="1" description="Disabled." /> + </BitField> + <BitField start="2" size="1" name="AADEN" description="AAD enable"> + <Enum name="DISABLED_" start="0" description="Disabled." /> + <Enum name="ENABLED_" start="1" description="Enabled." /> + </BitField> + <BitField start="3" size="1" name="RESERVED" description="Reserved." /> + <BitField start="4" size="1" name="DCTRL" description="Direction control for DIR pin."> + <Enum name="DISABLE_AUTO_DIRECTI" start="0" description="Disable Auto Direction Control." /> + <Enum name="ENABLE_AUTO_DIRECTIO" start="1" description="Enable Auto Direction Control." /> + </BitField> + <BitField start="5" size="1" name="OINV" description="Direction control pin polarity. This bit reverses the polarity of the direction control signal on the DIR pin."> + <Enum name="LOW_THE_DIRECTION_C" start="0" description="Low. The direction control pin will be driven to logic 0 when the transmitter has data to be sent. It will be driven to logic 1 after the last bit of data has been transmitted." /> + <Enum name="HIGH_THE_DIRECTION_" start="1" description="High. The direction control pin will be driven to logic 1 when the transmitter has data to be sent. It will be driven to logic 0 after the last bit of data has been transmitted." /> + </BitField> + <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x050" size="4" name="RS485ADRMATCH" access="Read/Write" description="RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="ADRMATCH" description="Contains the address match value." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x054" size="4" name="RS485DLY" access="Read/Write" description="RS-485/EIA-485 direction control delay." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="DLY" description="Contains the direction control (U4OE) delay value. This register works in conjunction with an 8-bit counter." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x058" size="4" name="SYNCCTRL" access="Read/Write" description="Synchronous mode control register." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="SYNC" description="Enables synchronous mode."> + <Enum name="DISABLED" start="0" description="Disabled" /> + <Enum name="ENABLED" start="1" description="Enabled" /> + </BitField> + <BitField start="1" size="1" name="CSRC" description="Clock source select."> + <Enum name="SYNCHRONOUS_SLAVE_MO" start="0" description="Synchronous slave mode (SCLK in)" /> + <Enum name="SYNCHRONOUS_MASTER_M" start="1" description="Synchronous master mode (SCLK out)" /> + </BitField> + <BitField start="2" size="1" name="FES" description="Falling edge sampling."> + <Enum name="RXD_IS_SAMPLED_ON_TH" start="0" description="RxD is sampled on the rising edge of SCLK" /> + <Enum name="RXD_IS_SAMPLED_ON_TH" start="1" description="RxD is sampled on the falling edge of SCLK" /> + </BitField> + <BitField start="3" size="1" name="TSBYPASS" description="Transmit synchronization bypass in synchronous slave mode."> + <Enum name="THE_INPUT_CLOCK_IS_S" start="0" description="The input clock is synchronized prior to being used in clock edge detection logic." /> + <Enum name="THE_INPUT_CLOCK_IS_N" start="1" description="The input clock is not synchronized prior to being used in clock edge detection logic. This allows for a high er input clock rate at the expense of potential metastability." /> + </BitField> + <BitField start="4" size="1" name="CSCEN" description="Continuous master clock enable (used only when CSRC is 1)"> + <Enum name="SCLK_CYCLES_ONLY_WHE" start="0" description="SCLK cycles only when characters are being sent on TxD" /> + <Enum name="SCLK_RUNS_CONTINUOUS" start="1" description="SCLK runs continuously (characters can be received on RxD independently from transmission on TxD)" /> + </BitField> + <BitField start="5" size="1" name="SSSDIS" description="Start/stop bits"> + <Enum name="SEND_START_AND_STOP_" start="0" description="Send start and stop bits as in other modes." /> + <Enum name="NOSTARTSTOPBIT" start="1" description="Do not send start/stop bits." /> + </BitField> + <BitField start="6" size="1" name="CCCLR" description="Continuous clock clear"> + <Enum name="CSCEN_IS_UNDER_SOFTW" start="0" description="CSCEN is under software control." /> + <Enum name="HARDWARE_CLEARS_CSCE" start="1" description="Hardware clears CSCEN after each character is received." /> + </BitField> + <BitField start="6" size="26" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + </RegisterGroup> + <RegisterGroup name="I2S" start="0x400A8000" description="I2S interface"> + <Register start="+0x000" size="4" name="DAO" access="Read/Write" description="I2S Digital Audio Output Register. Contains control bits for the I2S transmit channel." reset_value="0x87E1" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="WORDWIDTH" description="Selects the number of bytes in data as follows:"> + <Enum name="8_BIT_DATA" start="0x0" description="8-bit data" /> + <Enum name="16_BIT_DATA" start="0x1" description="16-bit data" /> + <Enum name="32_BIT_DATA" start="0x3" description="32-bit data" /> + </BitField> + <BitField start="2" size="1" name="MONO" description="When 1, data is of monaural format. When 0, the data is in stereo format." /> + <BitField start="3" size="1" name="STOP" description="When 1, disables accesses on FIFOs, places the transmit channel in mute mode." /> + <BitField start="4" size="1" name="RESET" description="When 1, asynchronously resets the transmit channel and FIFO." /> + <BitField start="5" size="1" name="WS_SEL" description="When 0, the interface is in master mode. When 1, the interface is in slave mode. See Section 34.7.2 for a summary of useful combinations for this bit with TXMODE." /> + <BitField start="6" size="9" name="WS_HALFPERIOD" description="Word select half period minus 1, i.e. WS 64clk period -> ws_halfperiod = 31." /> + <BitField start="15" size="1" name="MUTE" description="When 1, the transmit channel sends only zeroes." /> + <BitField start="16" size="16" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x004" size="4" name="DAI" access="Read/Write" description="I2S Digital Audio Input Register. Contains control bits for the I2S receive channel." reset_value="0x07E1" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="WORDWIDTH" description="Selects the number of bytes in data as follows:"> + <Enum name="8_BIT_DATA" start="0x0" description="8-bit data" /> + <Enum name="16_BIT_DATA" start="0x1" description="16-bit data" /> + <Enum name="32_BIT_DATA" start="0x3" description="32-bit data" /> + </BitField> + <BitField start="2" size="1" name="MONO" description="When 1, data is of monaural format. When 0, the data is in stereo format." /> + <BitField start="3" size="1" name="STOP" description="When 1, disables accesses on FIFOs, places the transmit channel in mute mode." /> + <BitField start="4" size="1" name="RESET" description="When 1, asynchronously reset the transmit channel and FIFO." /> + <BitField start="5" size="1" name="WS_SEL" description="When 0, the interface is in master mode. When 1, the interface is in slave mode. See Section 34.7.2 for a summary of useful combinations for this bit with RXMODE." /> + <BitField start="6" size="9" name="WS_HALFPERIOD" description="Word select half period minus 1, i.e. WS 64clk period -> ws_halfperiod = 31." /> + <BitField start="15" size="17" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x008" size="4" name="TXFIFO" access="WriteOnly" description="I2S Transmit FIFO. Access register for the 8 x 32-bit transmitter FIFO." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="I2STXFIFO" description="8 x 32-bit transmit FIFO." /> + </Register> + <Register start="+0x00C" size="4" name="RXFIFO" access="None" description="I2S Receive FIFO. Access register for the 8 x 32-bit receiver FIFO." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="I2SRXFIFO" description="8 x 32-bit transmit FIFO." /> + </Register> + <Register start="+0x010" size="4" name="STATE" access="ReadOnly" description="I2S Status Feedback Register. Contains status information about the I2S interface." reset_value="0x7" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="IRQ" description="This bit reflects the presence of Receive Interrupt or Transmit Interrupt. This is determined by comparing the current FIFO levels to the rx_depth_irq and tx_depth_irq fields in the IRQ register." /> + <BitField start="1" size="1" name="DMAREQ1" description="This bit reflects the presence of Receive or Transmit DMA Request 1. This is determined by comparing the current FIFO levels to the rx_depth_dma1 and tx_depth_dma1 fields in the DMA1 register." /> + <BitField start="2" size="1" name="DMAREQ2" description="This bit reflects the presence of Receive or Transmit DMA Request 2. This is determined by comparing the current FIFO levels to the rx_depth_dma2 and tx_depth_dma2 fields in the DMA2 register." /> + <BitField start="3" size="5" name="RESERVED" description="Reserved." /> + <BitField start="8" size="4" name="RX_LEVEL" description="Reflects the current level of the Receive FIFO." /> + <BitField start="12" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + <BitField start="16" size="4" name="TX_LEVEL" description="Reflects the current level of the Transmit FIFO." /> + <BitField start="20" size="12" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x014" size="4" name="DMA1" access="Read/Write" description="I2S DMA Configuration Register 1. Contains control information for DMA request 1." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RX_DMA1_ENABLE" description="When 1, enables DMA1 for I2S receive." /> + <BitField start="1" size="1" name="TX_DMA1_ENABLE" description="When 1, enables DMA1 for I2S transmit." /> + <BitField start="2" size="6" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + <BitField start="8" size="4" name="RX_DEPTH_DMA1" description="Set the FIFO level that triggers a receive DMA request on DMA1." /> + <BitField start="12" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + <BitField start="16" size="4" name="TX_DEPTH_DMA1" description="Set the FIFO level that triggers a transmit DMA request on DMA1." /> + <BitField start="20" size="12" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x018" size="4" name="DMA2" access="Read/Write" description="I2S DMA Configuration Register 2. Contains control information for DMA request 2." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RX_DMA2_ENABLE" description="When 1, enables DMA1 for I2S receive." /> + <BitField start="1" size="1" name="TX_DMA2_ENABLE" description="When 1, enables DMA1 for I2S transmit." /> + <BitField start="2" size="6" name="RESERVED" description="Reserved." /> + <BitField start="8" size="4" name="RX_DEPTH_DMA2" description="Set the FIFO level that triggers a receive DMA request on DMA2." /> + <BitField start="12" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + <BitField start="16" size="4" name="TX_DEPTH_DMA2" description="Set the FIFO level that triggers a transmit DMA request on DMA2." /> + <BitField start="20" size="12" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x01C" size="4" name="IRQ" access="Read/Write" description="I2S Interrupt Request Control Register. Contains bits that control how the I2S interrupt request is generated." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RX_IRQ_ENABLE" description="When 1, enables I2S receive interrupt." /> + <BitField start="1" size="1" name="TX_IRQ_ENABLE" description="When 1, enables I2S transmit interrupt." /> + <BitField start="2" size="6" name="RESERVED" description="Reserved." /> + <BitField start="8" size="4" name="RX_DEPTH_IRQ" description="Set the FIFO level on which to create an irq request." /> + <BitField start="12" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + <BitField start="16" size="4" name="TX_DEPTH_IRQ" description="Set the FIFO level on which to create an irq request." /> + <BitField start="20" size="12" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x020" size="4" name="TXRATE" access="Read/Write" description="I2S Transmit MCLK divider. This register determines the I2S TX MCLK rate by specifying the value to divide PCLK by in order to produce MCLK." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="Y_DIVIDER" description="I2S transmit MCLK rate denominator. This value is used to divide PCLK to produce the transmit MCLK. Eight bits of fractional divide supports a wide range of possibilities. A value of 0 stops the clock." /> + <BitField start="8" size="8" name="X_DIVIDER" description="I2S transmit MCLK rate numerator. This value is used to multiply PCLK by to produce the transmit MCLK. A value of 0 stops the clock. Eight bits of fractional divide supports a wide range of possibilities. Note: the resulting ratio X/Y is divided by 2." /> + <BitField start="16" size="16" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x024" size="4" name="RXRATE" access="Read/Write" description="I2S Receive MCLK divider. This register determines the I2S RX MCLK rate by specifying the value to divide PCLK by in order to produce MCLK." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="Y_DIVIDER" description="I2S receive MCLK rate denominator. This value is used to divide PCLK to produce the receive MCLK. Eight bits of fractional divide supports a wide range of possibilities. A value of 0 stops the clock." /> + <BitField start="8" size="8" name="X_DIVIDER" description="I2S receive MCLK rate numerator. This value is used to multiply PCLK by to produce the receive MCLK. A value of 0 stops the clock. Eight bits of fractional divide supports a wide range of possibilities. Note: the resulting ratio X/Y is divided by 2." /> + <BitField start="16" size="16" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x028" size="4" name="TXBITRATE" access="Read/Write" description="I2S Transmit bit rate divider. This register determines the I2S transmit bit rate by specifying the value to divide TX_MCLK by in order to produce the transmit bit clock." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="6" name="TX_BITRATE" description="I2S transmit bit rate. This value plus one is used to divide TX_MCLK to produce the transmit bit clock." /> + <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x02C" size="4" name="RXBITRATE" access="Read/Write" description="I2S Receive bit rate divider. This register determines the I2S receive bit rate by specifying the value to divide RX_MCLK by in order to produce the receive bit clock." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="6" name="RX_BITRATE" description="I2S receive bit rate. This value plus one is used to divide RX_MCLK to produce the receive bit clock." /> + <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x030" size="4" name="TXMODE" access="Read/Write" description="I2S Transmit mode control." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="TXCLKSEL" description="Clock source selection for the transmit bit clock divider."> + <Enum name="SELECT_THE_TX_FRACTI" start="0x0" description="Select the TX fractional rate divider clock output as the source" /> + <Enum name="SELECT_THE_RX_MCLK_S" start="0x2" description="Select the RX_MCLK signal as the TX_MCLK clock source" /> + </BitField> + <BitField start="2" size="1" name="TX4PIN" description="Transmit 4-pin mode selection. When 1, enables 4-pin mode." /> + <BitField start="3" size="1" name="TXMCENA" description="Enable for the TX_MCLK output. When 0, output of TX_MCLK is not enabled. When 1, output of TX_MCLK is enabled." /> + <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x034" size="4" name="RXMODE" access="Read/Write" description="I2S Receive mode control." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="RXCLKSEL" description="Clock source selection for the receive bit clock divider."> + <Enum name="SELECT_THE_RX_FRACTI" start="0x0" description="Select the RX fractional rate divider clock output as the source" /> + <Enum name="SELECT_THE_TX_MCLK_S" start="0x2" description="Select the TX_MCLK signal as the RX_MCLK clock source" /> + </BitField> + <BitField start="2" size="1" name="RX4PIN" description="Receive 4-pin mode selection. When 1, enables 4-pin mode." /> + <BitField start="3" size="1" name="RXMCENA" description="Enable for the RX_MCLK output. When 0, output of RX_MCLK is not enabled. When 1, output of RX_MCLK is enabled." /> + <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + </RegisterGroup> + <RegisterGroup name="MCPWM" start="0x400B8000" description="Motor Control PWM"> + <Register start="+0x000" size="4" name="CON" access="ReadOnly" description="PWM Control read address" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RUN0" description="Stops/starts timer channel 0."> + <Enum name="STOP_" start="0" description="Stop." /> + <Enum name="RUN_" start="1" description="Run." /> + </BitField> + <BitField start="1" size="1" name="CENTER0" description="Edge/center aligned operation for channel 0."> + <Enum name="EDGE_ALIGNED_" start="0" description="Edge-aligned." /> + <Enum name="CENTER_ALIGNED_" start="1" description="Center-aligned." /> + </BitField> + <BitField start="2" size="1" name="POLA0" description="Selects polarity of the MCOA0 and MCOB0 pins."> + <Enum name="PASSIVE_STATE_IS_LOW" start="0" description="Passive state is LOW, active state is HIGH." /> + <Enum name="PASSIVE_STATE_IS_HIG" start="1" description="Passive state is HIGH, active state is LOW." /> + </BitField> + <BitField start="3" size="1" name="DTE0" description="Controls the dead-time feature for channel 0."> + <Enum name="DEAD_TIME_DISABLED_" start="0" description="Dead-time disabled." /> + <Enum name="DEAD_TIME_ENABLED_" start="1" description="Dead-time enabled." /> + </BitField> + <BitField start="4" size="1" name="DISUP0" description="Enable/disable updates of functional registers for channel 0 (see Section 24.8.2)."> + <Enum name="UPDATE" start="0" description="Functional registers are updated from the write registers at the end of each PWM cycle." /> + <Enum name="NOUPDATE" start="1" description="Functional registers remain the same as long as the timer is running." /> + </BitField> + <BitField start="5" size="3" name="RESERVED" description="Reserved." /> + <BitField start="8" size="1" name="RUN1" description="Stops/starts timer channel 1."> + <Enum name="STOP_" start="0" description="Stop." /> + <Enum name="RUN_" start="1" description="Run." /> + </BitField> + <BitField start="9" size="1" name="CENTER1" description="Edge/center aligned operation for channel 1."> + <Enum name="EDGE_ALIGNED_" start="0" description="Edge-aligned." /> + <Enum name="CENTER_ALIGNED_" start="1" description="Center-aligned." /> + </BitField> + <BitField start="10" size="1" name="POLA1" description="Selects polarity of the MCOA1 and MCOB1 pins."> + <Enum name="PASSIVE_STATE_IS_LOW" start="0" description="Passive state is LOW, active state is HIGH." /> + <Enum name="PASSIVE_STATE_IS_HIG" start="1" description="Passive state is HIGH, active state is LOW." /> + </BitField> + <BitField start="11" size="1" name="DTE1" description="Controls the dead-time feature for channel 1."> + <Enum name="DEAD_TIME_DISABLED_" start="0" description="Dead-time disabled." /> + <Enum name="DEAD_TIME_ENABLED_" start="1" description="Dead-time enabled." /> + </BitField> + <BitField start="12" size="1" name="DISUP1" description="Enable/disable updates of functional registers for channel 1 (see Section 24.8.2)."> + <Enum name="UPDATE" start="0" description="Functional registers are updated from the write registers at the end of each PWM cycle." /> + <Enum name="NOUPDATE" start="1" description="Functional registers remain the same as long as the timer is running." /> + </BitField> + <BitField start="13" size="3" name="RESERVED" description="Reserved." /> + <BitField start="16" size="1" name="RUN2" description="Stops/starts timer channel 2."> + <Enum name="STOP_" start="0" description="Stop." /> + <Enum name="RUN_" start="1" description="Run." /> + </BitField> + <BitField start="17" size="1" name="CENTER2" description="Edge/center aligned operation for channel 2."> + <Enum name="EDGE_ALIGNED_" start="0" description="Edge-aligned." /> + <Enum name="CENTER_ALIGNED_" start="1" description="Center-aligned." /> + </BitField> + <BitField start="18" size="1" name="POLA2" description="Selects polarity of the MCOA2 and MCOB2 pins."> + <Enum name="PASSIVE_STATE_IS_LOW" start="0" description="Passive state is LOW, active state is HIGH." /> + <Enum name="PASSIVE_STATE_IS_HIG" start="1" description="Passive state is HIGH, active state is LOW." /> + </BitField> + <BitField start="19" size="1" name="DTE2" description="Controls the dead-time feature for channel 1."> + <Enum name="DEAD_TIME_DISABLED_" start="0" description="Dead-time disabled." /> + <Enum name="DEAD_TIME_ENABLED_" start="1" description="Dead-time enabled." /> + </BitField> + <BitField start="20" size="1" name="DISUP2" description="Enable/disable updates of functional registers for channel 2 (see Section 24.8.2)."> + <Enum name="UPDATE" start="0" description="Functional registers are updated from the write registers at the end of each PWM cycle." /> + <Enum name="NOUPDATE" start="1" description="Functional registers remain the same as long as the timer is running." /> + </BitField> + <BitField start="21" size="8" name="RESERVED" description="Reserved." /> + <BitField start="29" size="1" name="INVBDC" description="Controls the polarity of the MCOB outputs for all 3 channels. This bit is typically set to 1 only in 3-phase DC mode."> + <Enum name="OPPOSITE" start="0" description="The MCOB outputs have opposite polarity from the MCOA outputs (aside from dead time)." /> + <Enum name="SAME" start="1" description="The MCOB outputs have the same basic polarity as the MCOA outputs. (see Section 24.8.6)" /> + </BitField> + <BitField start="30" size="1" name="ACMODE" description="3-phase AC mode select (see Section 24.8.7)."> + <Enum name="3_PHASE_AC_MODE_OFF" start="0" description="3-phase AC-mode off: Each PWM channel uses its own timer-counter and period register." /> + <Enum name="3_PHASE_AC_MODE_ON_" start="1" description="3-phase AC-mode on: All PWM channels use the timer-counter and period register of channel 0." /> + </BitField> + <BitField start="31" size="1" name="DCMODE" description="3-phase DC mode select (see Section 24.8.6)."> + <Enum name="3_PHASE_DC_MODE_OFF" start="0" description="3-phase DC mode off: PWM channels are independent (unless bit ACMODE = 1)" /> + <Enum name="3_PHASE_DC_MODE_ON_" start="1" description="3-phase DC mode on: The internal MCOA0 output is routed through the CP register (i.e. a mask) register to all six PWM outputs." /> + </BitField> + </Register> + <Register start="+0x004" size="4" name="CON_SET" access="WriteOnly" description="PWM Control set address" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="RUN0_SET" description="Writing a one sets the corresponding bit in the CON register." /> + <BitField start="1" size="1" name="CENTER0_SET" description="Writing a one sets the corresponding bit in the CON register." /> + <BitField start="2" size="1" name="POLA0_SET" description="Writing a one sets the corresponding bit in the CON register." /> + <BitField start="3" size="1" name="DTE0_SET" description="Writing a one sets the corresponding bit in the CON register." /> + <BitField start="4" size="1" name="DISUP0_SET" description="Writing a one sets the corresponding bit in the CON register." /> + <BitField start="5" size="3" name="RESERVED" description="Writing a one sets the corresponding bit in the CON register." /> + <BitField start="8" size="1" name="RUN1_SET" description="Writing a one sets the corresponding bit in the CON register." /> + <BitField start="9" size="1" name="CENTER1_SET" description="Writing a one sets the corresponding bit in the CON register." /> + <BitField start="10" size="1" name="POLA1_SET" description="Writing a one sets the corresponding bit in the CON register." /> + <BitField start="11" size="1" name="DTE1_SET" description="Writing a one sets the corresponding bit in the CON register." /> + <BitField start="12" size="1" name="DISUP1_SET" description="Writing a one sets the corresponding bit in the CON register." /> + <BitField start="13" size="3" name="RESERVED" description="Writing a one sets the corresponding bit in the CON register." /> + <BitField start="16" size="1" name="RUN2_SET" description="Writing a one sets the corresponding bit in the CON register." /> + <BitField start="17" size="1" name="CENTER2_SET" description="Writing a one sets the corresponding bit in the CON register." /> + <BitField start="18" size="1" name="POLA2_SET" description="Writing a one sets the corresponding bit in the CON register." /> + <BitField start="19" size="1" name="DTE2_SET" description="Writing a one sets the corresponding bit in the CON register." /> + <BitField start="20" size="1" name="DISUP2_SET" description="Writing a one sets the corresponding bit in the CON register." /> + <BitField start="21" size="8" name="RESERVED" description="Writing a one sets the corresponding bit in the CON register." /> + <BitField start="29" size="1" name="INVBDC_SET" description="Writing a one sets the corresponding bit in the CON register." /> + <BitField start="30" size="1" name="ACMODE_SET" description="Writing a one sets the corresponding bit in the CON register." /> + <BitField start="31" size="1" name="DCMODE_SET" description="Writing a one sets the corresponding bit in the CON register." /> + </Register> + <Register start="+0x008" size="4" name="CON_CLR" access="WriteOnly" description="PWM Control clear address" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="RUN0_CLR" description="Writing a one clears the corresponding bit in the CON register." /> + <BitField start="1" size="1" name="CENTER0_CLR" description="Writing a one clears the corresponding bit in the CON register." /> + <BitField start="2" size="1" name="POLA0_CLR" description="Writing a one clears the corresponding bit in the CON register." /> + <BitField start="3" size="1" name="DTE0_CLR" description="Writing a one clears the corresponding bit in the CON register." /> + <BitField start="4" size="1" name="DISUP0_CLR" description="Writing a one clears the corresponding bit in the CON register." /> + <BitField start="5" size="3" name="RESERVED" description="Writing a one clears the corresponding bit in the CON register." /> + <BitField start="8" size="1" name="RUN1_CLR" description="Writing a one clears the corresponding bit in the CON register." /> + <BitField start="9" size="1" name="CENTER1_CLR" description="Writing a one clears the corresponding bit in the CON register." /> + <BitField start="10" size="1" name="POLA1_CLR" description="Writing a one clears the corresponding bit in the CON register." /> + <BitField start="11" size="1" name="DTE1_CLR" description="Writing a one clears the corresponding bit in the CON register." /> + <BitField start="12" size="1" name="DISUP1_CLR" description="Writing a one clears the corresponding bit in the CON register." /> + <BitField start="13" size="3" name="RESERVED" description="Writing a one clears the corresponding bit in the CON register." /> + <BitField start="16" size="1" name="RUN2_CLR" description="Writing a one clears the corresponding bit in the CON register." /> + <BitField start="17" size="1" name="CENTER2_CLR" description="Writing a one clears the corresponding bit in the CON register." /> + <BitField start="18" size="1" name="POLA2_CLR" description="Writing a one clears the corresponding bit in the CON register." /> + <BitField start="19" size="1" name="DTE2_CLR" description="Writing a one clears the corresponding bit in the CON register." /> + <BitField start="20" size="1" name="DISUP2_CLR" description="Writing a one clears the corresponding bit in the CON register." /> + <BitField start="21" size="8" name="RESERVED" description="Writing a one clears the corresponding bit in the CON register." /> + <BitField start="29" size="1" name="INVBDC_CLR" description="Writing a one clears the corresponding bit in the CON register." /> + <BitField start="30" size="1" name="ACMOD_CLR" description="Writing a one clears the corresponding bit in the CON register." /> + <BitField start="31" size="1" name="DCMODE_CLR" description="Writing a one clears the corresponding bit in the CON register." /> + </Register> + <Register start="+0x00C" size="4" name="CAPCON" access="ReadOnly" description="Capture Control read address" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="CAP0MCI0_RE" description="A 1 in this bit enables a channel 0 capture event on a rising edge on MCI0." /> + <BitField start="1" size="1" name="CAP0MCI0_FE" description="A 1 in this bit enables a channel 0 capture event on a falling edge on MCI0." /> + <BitField start="2" size="1" name="CAP0MCI1_RE" description="A 1 in this bit enables a channel 0 capture event on a rising edge on MCI1." /> + <BitField start="3" size="1" name="CAP0MCI1_FE" description="A 1 in this bit enables a channel 0 capture event on a falling edge on MCI1." /> + <BitField start="4" size="1" name="CAP0MCI2_RE" description="A 1 in this bit enables a channel 0 capture event on a rising edge on MCI2." /> + <BitField start="5" size="1" name="CAP0MCI2_FE" description="A 1 in this bit enables a channel 0 capture event on a falling edge on MCI2." /> + <BitField start="6" size="1" name="CAP1MCI0_RE" description="A 1 in this bit enables a channel 1 capture event on a rising edge on MCI0." /> + <BitField start="7" size="1" name="CAP1MCI0_FE" description="A 1 in this bit enables a channel 1 capture event on a falling edge on MCI0." /> + <BitField start="8" size="1" name="CAP1MCI1_RE" description="A 1 in this bit enables a channel 1 capture event on a rising edge on MCI1." /> + <BitField start="9" size="1" name="CAP1MCI1_FE" description="A 1 in this bit enables a channel 1 capture event on a falling edge on MCI1." /> + <BitField start="10" size="1" name="CAP1MCI2_RE" description="A 1 in this bit enables a channel 1 capture event on a rising edge on MCI2." /> + <BitField start="11" size="1" name="CAP1MCI2_FE" description="A 1 in this bit enables a channel 1 capture event on a falling edge on MCI2." /> + <BitField start="12" size="1" name="CAP2MCI0_RE" description="A 1 in this bit enables a channel 2 capture event on a rising edge on MCI0." /> + <BitField start="13" size="1" name="CAP2MCI0_FE" description="A 1 in this bit enables a channel 2 capture event on a falling edge on MCI0." /> + <BitField start="14" size="1" name="CAP2MCI1_RE" description="A 1 in this bit enables a channel 2 capture event on a rising edge on MCI1." /> + <BitField start="15" size="1" name="CAP2MCI1_FE" description="A 1 in this bit enables a channel 2 capture event on a falling edge on MCI1." /> + <BitField start="16" size="1" name="CAP2MCI2_RE" description="A 1 in this bit enables a channel 2 capture event on a rising edge on MCI2." /> + <BitField start="17" size="1" name="CAP2MCI2_FE" description="A 1 in this bit enables a channel 2 capture event on a falling edge on MCI2." /> + <BitField start="18" size="1" name="RT0" description="If this bit is 1, TC0 is reset by a channel 0 capture event." /> + <BitField start="19" size="1" name="RT1" description="If this bit is 1, TC1 is reset by a channel 1 capture event." /> + <BitField start="20" size="1" name="RT2" description="If this bit is 1, TC2 is reset by a channel 2 capture event." /> + <BitField start="21" size="11" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x010" size="4" name="CAPCON_SET" access="WriteOnly" description="Capture Control set address" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="CAP0MCI0_RE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." /> + <BitField start="1" size="1" name="CAP0MCI0_FE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." /> + <BitField start="2" size="1" name="CAP0MCI1_RE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." /> + <BitField start="3" size="1" name="CAP0MCI1_FE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." /> + <BitField start="4" size="1" name="CAP0MCI2_RE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." /> + <BitField start="5" size="1" name="CAP0MCI2_FE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." /> + <BitField start="6" size="1" name="CAP1MCI0_RE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." /> + <BitField start="7" size="1" name="CAP1MCI0_FE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." /> + <BitField start="8" size="1" name="CAP1MCI1_RE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." /> + <BitField start="9" size="1" name="CAP1MCI1_FE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." /> + <BitField start="10" size="1" name="CAP1MCI2_RE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." /> + <BitField start="11" size="1" name="CAP1MCI2_FE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." /> + <BitField start="12" size="1" name="CAP2MCI0_RE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." /> + <BitField start="13" size="1" name="CAP2MCI0_FE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." /> + <BitField start="14" size="1" name="CAP2MCI1_RE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." /> + <BitField start="15" size="1" name="CAP2MCI1_FE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." /> + <BitField start="16" size="1" name="CAP2MCI2_RE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." /> + <BitField start="17" size="1" name="CAP2MCI2_FE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." /> + <BitField start="18" size="1" name="RT0_SET" description="Writing a one sets the corresponding bits in the CAPCON register." /> + <BitField start="19" size="1" name="RT1_SET" description="Writing a one sets the corresponding bits in the CAPCON register." /> + <BitField start="20" size="1" name="RT2_SET" description="Writing a one sets the corresponding bits in the CAPCON register." /> + <BitField start="21" size="11" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x014" size="4" name="CAPCON_CLR" access="WriteOnly" description="Event Control clear address" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="CAP0MCI0_RE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." /> + <BitField start="1" size="1" name="CAP0MCI0_FE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." /> + <BitField start="2" size="1" name="CAP0MCI1_RE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." /> + <BitField start="3" size="1" name="CAP0MCI1_FE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." /> + <BitField start="4" size="1" name="CAP0MCI2_RE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." /> + <BitField start="5" size="1" name="CAP0MCI2_FE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." /> + <BitField start="6" size="1" name="CAP1MCI0_RE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." /> + <BitField start="7" size="1" name="CAP1MCI0_FE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." /> + <BitField start="8" size="1" name="CAP1MCI1_RE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." /> + <BitField start="9" size="1" name="CAP1MCI1_FE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." /> + <BitField start="10" size="1" name="CAP1MCI2_RE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." /> + <BitField start="11" size="1" name="CAP1MCI2_FE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." /> + <BitField start="12" size="1" name="CAP2MCI0_RE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." /> + <BitField start="13" size="1" name="CAP2MCI0_FE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." /> + <BitField start="14" size="1" name="CAP2MCI1_RE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." /> + <BitField start="15" size="1" name="CAP2MCI1_FE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." /> + <BitField start="16" size="1" name="CAP2MCI2_RE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." /> + <BitField start="17" size="1" name="CAP2MCI2_FE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." /> + <BitField start="18" size="1" name="RT0_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." /> + <BitField start="19" size="1" name="RT1_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." /> + <BitField start="20" size="1" name="RT2_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." /> + <BitField start="21" size="11" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x018+0" size="4" name="TC[0]" access="Read/Write" description="Timer Counter register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="MCTC" description="Timer/Counter value." /> + </Register> + <Register start="+0x018+4" size="4" name="TC[1]" access="Read/Write" description="Timer Counter register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="MCTC" description="Timer/Counter value." /> + </Register> + <Register start="+0x018+8" size="4" name="TC[2]" access="Read/Write" description="Timer Counter register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="MCTC" description="Timer/Counter value." /> + </Register> + <Register start="+0x024+0" size="4" name="LIM[0]" access="Read/Write" description="Limit register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="MCLIM" description="Limit value." /> + </Register> + <Register start="+0x024+4" size="4" name="LIM[1]" access="Read/Write" description="Limit register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="MCLIM" description="Limit value." /> + </Register> + <Register start="+0x024+8" size="4" name="LIM[2]" access="Read/Write" description="Limit register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="MCLIM" description="Limit value." /> + </Register> + <Register start="+0x030+0" size="4" name="MAT[0]" access="Read/Write" description="Match register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="MCMAT" description="Match value." /> + </Register> + <Register start="+0x030+4" size="4" name="MAT[1]" access="Read/Write" description="Match register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="MCMAT" description="Match value." /> + </Register> + <Register start="+0x030+8" size="4" name="MAT[2]" access="Read/Write" description="Match register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="MCMAT" description="Match value." /> + </Register> + <Register start="+0x03C" size="4" name="DT" access="Read/Write" description="Dead time register" reset_value="0x3FFFFFFF" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="10" name="DT0" description="Dead time for channel 0.[1]" /> + <BitField start="10" size="10" name="DT1" description="Dead time for channel 1.[2]" /> + <BitField start="20" size="10" name="DT2" description="Dead time for channel 2.[2]" /> + <BitField start="30" size="2" name="RESERVED" description="reserved" /> + </Register> + <Register start="+0x040" size="4" name="CCP" access="Read/Write" description="Communication Pattern register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="CCPA0" description="Communication pattern output A, channel 0."> + <Enum name="MCOA0_PASSIVE_" start="0" description="MCOA0 passive." /> + <Enum name="INTERNAL_MCOA0_" start="1" description="internal MCOA0." /> + </BitField> + <BitField start="1" size="1" name="CCPB0" description="Communication pattern output B, channel 0."> + <Enum name="MCOB0_PASSIVE_" start="0" description="MCOB0 passive." /> + <Enum name="MCOB0_TRACKS_INTERNA" start="1" description="MCOB0 tracks internal MCOA0." /> + </BitField> + <BitField start="2" size="1" name="CCPA1" description="Communication pattern output A, channel 1."> + <Enum name="MCOA1_PASSIVE_" start="0" description="MCOA1 passive." /> + <Enum name="MCOA1_TRACKS_INTERNA" start="1" description="MCOA1 tracks internal MCOA0." /> + </BitField> + <BitField start="3" size="1" name="CCPB1" description="Communication pattern output B, channel 1."> + <Enum name="MCOB1_PASSIVE_" start="0" description="MCOB1 passive." /> + <Enum name="MCOB1_TRACKS_INTERNA" start="1" description="MCOB1 tracks internal MCOA0." /> + </BitField> + <BitField start="4" size="1" name="CCPA2" description="Communication pattern output A, channel 2."> + <Enum name="MCOA2_PASSIVE_" start="0" description="MCOA2 passive." /> + <Enum name="MCOA2_TRACKS_INTERNA" start="1" description="MCOA2 tracks internal MCOA0." /> + </BitField> + <BitField start="5" size="1" name="CCPB2" description="Communication pattern output B, channel 2."> + <Enum name="MCOB2_PASSIVE_" start="0" description="MCOB2 passive." /> + <Enum name="MCOB2_TRACKS_INTERNA" start="1" description="MCOB2 tracks internal MCOA0." /> + </BitField> + <BitField start="6" size="26" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x044+0" size="4" name="CAP[0]" access="ReadOnly" description="Capture register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CAP" description="Current TC value at a capture event." /> + </Register> + <Register start="+0x044+4" size="4" name="CAP[1]" access="ReadOnly" description="Capture register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CAP" description="Current TC value at a capture event." /> + </Register> + <Register start="+0x044+8" size="4" name="CAP[2]" access="ReadOnly" description="Capture register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CAP" description="Current TC value at a capture event." /> + </Register> + <Register start="+0x050" size="4" name="INTEN" access="ReadOnly" description="Interrupt Enable read address" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="ILIM0" description="Limit interrupt for channel 0."> + <Enum name="INTERRUPT_DISABLED_" start="0" description="Interrupt disabled." /> + <Enum name="INTERRUPT_ENABLED_" start="1" description="Interrupt enabled." /> + </BitField> + <BitField start="1" size="1" name="IMAT0" description="Match interrupt for channel 0."> + <Enum name="INTERRUPT_DISABLED_" start="0" description="Interrupt disabled." /> + <Enum name="INTERRUPT_ENABLED_" start="1" description="Interrupt enabled." /> + </BitField> + <BitField start="2" size="1" name="ICAP0" description="Capture interrupt for channel 0."> + <Enum name="INTERRUPT_DISABLED_" start="0" description="Interrupt disabled." /> + <Enum name="INTERRUPT_ENABLED_" start="1" description="Interrupt enabled." /> + </BitField> + <BitField start="3" size="1" name="RESERVED" description="Reserved." /> + <BitField start="4" size="1" name="ILIM1" description="Limit interrupt for channel 1."> + <Enum name="INTERRUPT_DISABLED_" start="0" description="Interrupt disabled." /> + <Enum name="INTERRUPT_ENABLED_" start="1" description="Interrupt enabled." /> + </BitField> + <BitField start="5" size="1" name="IMAT1" description="Match interrupt for channel 1."> + <Enum name="INTERRUPT_DISABLED_" start="0" description="Interrupt disabled." /> + <Enum name="INTERRUPT_ENABLED_" start="1" description="Interrupt enabled." /> + </BitField> + <BitField start="6" size="1" name="ICAP1" description="Capture interrupt for channel 1."> + <Enum name="INTERRUPT_DISABLED_" start="0" description="Interrupt disabled." /> + <Enum name="INTERRUPT_ENABLED_" start="1" description="Interrupt enabled." /> + </BitField> + <BitField start="7" size="1" name="RESERVED" description="Reserved." /> + <BitField start="8" size="1" name="ILIM2" description="Limit interrupt for channel 2."> + <Enum name="INTERRUPT_DISABLED_" start="0" description="Interrupt disabled." /> + <Enum name="INTERRUPT_ENABLED_" start="1" description="Interrupt enabled." /> + </BitField> + <BitField start="9" size="1" name="IMAT2" description="Match interrupt for channel 2."> + <Enum name="INTERRUPT_DISABLED_" start="0" description="Interrupt disabled." /> + <Enum name="INTERRUPT_ENABLED_" start="1" description="Interrupt enabled." /> + </BitField> + <BitField start="10" size="1" name="ICAP2" description="Capture interrupt for channel 2."> + <Enum name="INTERRUPT_DISABLED_" start="0" description="Interrupt disabled." /> + <Enum name="INTERRUPT_ENABLED_" start="1" description="Interrupt enabled." /> + </BitField> + <BitField start="11" size="4" name="RESERVED" description="Reserved." /> + <BitField start="15" size="1" name="ABORT" description="Fast abort interrupt."> + <Enum name="INTERRUPT_DISABLED_" start="0" description="Interrupt disabled." /> + <Enum name="INTERRUPT_ENABLED_" start="1" description="Interrupt enabled." /> + </BitField> + <BitField start="16" size="16" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x054" size="4" name="INTEN_SET" access="WriteOnly" description="Interrupt Enable set address" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="ILIM0_SET" description="Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt." /> + <BitField start="1" size="1" name="IMAT0_SET" description="Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt." /> + <BitField start="2" size="1" name="ICAP0_SET" description="Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt." /> + <BitField start="3" size="1" name="RESERVED" description="Reserved." /> + <BitField start="4" size="1" name="ILIM1_SET" description="Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt." /> + <BitField start="5" size="1" name="IMAT1_SET" description="Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt." /> + <BitField start="6" size="1" name="ICAP1_SET" description="Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt." /> + <BitField start="7" size="1" name="RESERVED" description="Reserved." /> + <BitField start="9" size="1" name="ILIM2_SET" description="Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt." /> + <BitField start="10" size="1" name="IMAT2_SET" description="Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt." /> + <BitField start="11" size="1" name="ICAP2_SET" description="Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt." /> + <BitField start="12" size="3" name="RESERVED" description="Reserved." /> + <BitField start="15" size="1" name="ABORT_SET" description="Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt." /> + <BitField start="16" size="16" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x058" size="4" name="INTEN_CLR" access="WriteOnly" description="Interrupt Enable clear address" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="ILIM0_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." /> + <BitField start="1" size="1" name="IMAT0_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." /> + <BitField start="2" size="1" name="ICAP0_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." /> + <BitField start="3" size="1" name="RESERVED" description="Reserved." /> + <BitField start="4" size="1" name="ILIM1_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." /> + <BitField start="5" size="1" name="IMAT1_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." /> + <BitField start="6" size="1" name="ICAP1_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." /> + <BitField start="7" size="1" name="RESERVED" description="Reserved." /> + <BitField start="8" size="1" name="ILIM2_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." /> + <BitField start="9" size="1" name="IMAT2_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." /> + <BitField start="10" size="1" name="ICAP2_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." /> + <BitField start="11" size="4" name="RESERVED" description="Reserved." /> + <BitField start="15" size="1" name="ABORT_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." /> + <BitField start="16" size="16" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x068" size="4" name="INTF" access="ReadOnly" description="Interrupt flags read address" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="ILIM0_F" description="Limit interrupt flag for channel 0."> + <Enum name="THIS_INTERRUPT_SOURC" start="0" description="This interrupt source is not contributing to the MCPWM interrupt request." /> + <Enum name="IF_THE_CORRESPONDING" start="1" description="If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller." /> + </BitField> + <BitField start="1" size="1" name="IMAT0_F" description="Match interrupt flag for channel 0."> + <Enum name="THIS_INTERRUPT_SOURC" start="0" description="This interrupt source is not contributing to the MCPWM interrupt request." /> + <Enum name="IF_THE_CORRESPONDING" start="1" description="If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller." /> + </BitField> + <BitField start="2" size="1" name="ICAP0_F" description="Capture interrupt flag for channel 0."> + <Enum name="THIS_INTERRUPT_SOURC" start="0" description="This interrupt source is not contributing to the MCPWM interrupt request." /> + <Enum name="IF_THE_CORRESPONDING" start="1" description="If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller." /> + </BitField> + <BitField start="3" size="1" name="RESERVED" description="Reserved." /> + <BitField start="4" size="1" name="ILIM1_F" description="Limit interrupt flag for channel 1."> + <Enum name="THIS_INTERRUPT_SOURC" start="0" description="This interrupt source is not contributing to the MCPWM interrupt request." /> + <Enum name="IF_THE_CORRESPONDING" start="1" description="If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller." /> + </BitField> + <BitField start="5" size="1" name="IMAT1_F" description="Match interrupt flag for channel 1."> + <Enum name="THIS_INTERRUPT_SOURC" start="0" description="This interrupt source is not contributing to the MCPWM interrupt request." /> + <Enum name="IF_THE_CORRESPONDING" start="1" description="If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller." /> + </BitField> + <BitField start="6" size="1" name="ICAP1_F" description="Capture interrupt flag for channel 1."> + <Enum name="THIS_INTERRUPT_SOURC" start="0" description="This interrupt source is not contributing to the MCPWM interrupt request." /> + <Enum name="IF_THE_CORRESPONDING" start="1" description="If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller." /> + </BitField> + <BitField start="7" size="1" name="RESERVED" description="Reserved." /> + <BitField start="8" size="1" name="ILIM2_F" description="Limit interrupt flag for channel 2."> + <Enum name="THIS_INTERRUPT_SOURC" start="0" description="This interrupt source is not contributing to the MCPWM interrupt request." /> + <Enum name="IF_THE_CORRESPONDING" start="1" description="If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller." /> + </BitField> + <BitField start="9" size="1" name="IMAT2_F" description="Match interrupt flag for channel 2."> + <Enum name="THIS_INTERRUPT_SOURC" start="0" description="This interrupt source is not contributing to the MCPWM interrupt request." /> + <Enum name="IF_THE_CORRESPONDING" start="1" description="If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller." /> + </BitField> + <BitField start="10" size="1" name="ICAP2_F" description="Capture interrupt flag for channel 2."> + <Enum name="THIS_INTERRUPT_SOURC" start="0" description="This interrupt source is not contributing to the MCPWM interrupt request." /> + <Enum name="IF_THE_CORRESPONDING" start="1" description="If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller." /> + </BitField> + <BitField start="11" size="4" name="RESERVED" description="Reserved." /> + <BitField start="15" size="1" name="ABORT_F" description="Fast abort interrupt flag."> + <Enum name="THIS_INTERRUPT_SOURC" start="0" description="This interrupt source is not contributing to the MCPWM interrupt request." /> + <Enum name="IF_THE_CORRESPONDING" start="1" description="If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller." /> + </BitField> + <BitField start="16" size="16" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x06C" size="4" name="INTF_SET" access="WriteOnly" description="Interrupt flags set address" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="ILIM0_F_SET" description="Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt." /> + <BitField start="1" size="1" name="IMAT0_F_SET" description="Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt." /> + <BitField start="2" size="1" name="ICAP0_F_SET" description="Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt." /> + <BitField start="3" size="1" name="RESERVED" description="Reserved." /> + <BitField start="4" size="1" name="ILIM1_F_SET" description="Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt." /> + <BitField start="5" size="1" name="IMAT1_F_SET" description="Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt." /> + <BitField start="6" size="1" name="ICAP1_F_SET" description="Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt." /> + <BitField start="7" size="1" name="RESERVED" description="Reserved." /> + <BitField start="8" size="1" name="ILIM2_F_SET" description="Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt." /> + <BitField start="9" size="1" name="IMAT2_F_SET" description="Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt." /> + <BitField start="10" size="1" name="ICAP2_F_SET" description="Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt." /> + <BitField start="11" size="4" name="RESERVED" description="Reserved." /> + <BitField start="15" size="1" name="ABORT_F_SET" description="Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt." /> + <BitField start="16" size="16" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x070" size="4" name="INTF_CLR" access="WriteOnly" description="Interrupt flags clear address" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="ILIM0_F_CLR" description="Writing a one clears the corresponding bit in the INTF register, thus clearing the corresponding interrupt request." /> + <BitField start="1" size="1" name="IMAT0_F_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." /> + <BitField start="2" size="1" name="ICAP0_F_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." /> + <BitField start="3" size="1" name="RESERVED" description="Reserved." /> + <BitField start="4" size="1" name="ILIM1_F_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." /> + <BitField start="5" size="1" name="IMAT1_F_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." /> + <BitField start="6" size="1" name="ICAP1_F_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." /> + <BitField start="7" size="1" name="RESERVED" description="Reserved." /> + <BitField start="8" size="1" name="ILIM2_F_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." /> + <BitField start="9" size="1" name="IMAT2_F_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." /> + <BitField start="10" size="1" name="ICAP2_F_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." /> + <BitField start="11" size="4" name="RESERVED" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." /> + <BitField start="15" size="1" name="ABORT_F_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." /> + <BitField start="16" size="16" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x05C" size="4" name="CNTCON" access="ReadOnly" description="Count Control read address" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="TC0MCI0_RE" description="Counter 0 rising edge mode, channel 0."> + <Enum name="A_RISING_EDGE_ON_MCI" start="0" description="A rising edge on MCI0 does not affect counter 0." /> + <Enum name="RISING" start="1" description="If MODE0 is 1, counter 0 advances on a rising edge on MCI0." /> + </BitField> + <BitField start="1" size="1" name="TC0MCI0_FE" description="Counter 0 falling edge mode, channel 0."> + <Enum name="A_FALLING_EDGE_ON_MC" start="0" description="A falling edge on MCI0 does not affect counter 0." /> + <Enum name="FALLING" start="1" description="If MODE0 is 1, counter 0 advances on a falling edge on MCI0." /> + </BitField> + <BitField start="2" size="1" name="TC0MCI1_RE" description="Counter 0 rising edge mode, channel 1."> + <Enum name="A_RISING_EDGE_ON_MCI" start="0" description="A rising edge on MCI1 does not affect counter 0." /> + <Enum name="RISING" start="1" description="If MODE0 is 1, counter 0 advances on a rising edge on MCI1." /> + </BitField> + <BitField start="3" size="1" name="TC0MCI1_FE" description="Counter 0 falling edge mode, channel 1."> + <Enum name="A_FALLING_EDGE_ON_MC" start="0" description="A falling edge on MCI1 does not affect counter 0." /> + <Enum name="FALLING" start="1" description="If MODE0 is 1, counter 0 advances on a falling edge on MCI1." /> + </BitField> + <BitField start="4" size="1" name="TC0MCI2_RE" description="Counter 0 rising edge mode, channel 2."> + <Enum name="A_RISING_EDGE_ON_MCI" start="0" description="A rising edge on MCI0 does not affect counter 0." /> + <Enum name="RISING" start="1" description="If MODE0 is 1, counter 0 advances on a rising edge on MCI2." /> + </BitField> + <BitField start="5" size="1" name="TC0MCI2_FE" description="Counter 0 falling edge mode, channel 2."> + <Enum name="A_FALLING_EDGE_ON_MC" start="0" description="A falling edge on MCI0 does not affect counter 0." /> + <Enum name="FALLLING" start="1" description="If MODE0 is 1, counter 0 advances on a falling edge on MCI2." /> + </BitField> + <BitField start="6" size="1" name="TC1MCI0_RE" description="Counter 1 rising edge mode, channel 0."> + <Enum name="A_RISING_EDGE_ON_MCI" start="0" description="A rising edge on MCI0 does not affect counter 1." /> + <Enum name="RISING" start="1" description="If MODE1 is 1, counter 1 advances on a rising edge on MCI0." /> + </BitField> + <BitField start="7" size="1" name="TC1MCI0_FE" description="Counter 1 falling edge mode, channel 0."> + <Enum name="A_FALLING_EDGE_ON_MC" start="0" description="A falling edge on MCI0 does not affect counter 1." /> + <Enum name="FALLING" start="1" description="If MODE1 is 1, counter 1 advances on a falling edge on MCI0." /> + </BitField> + <BitField start="8" size="1" name="TC1MCI1_RE" description="Counter 1 rising edge mode, channel 1."> + <Enum name="A_RISING_EDGE_ON_MCI" start="0" description="A rising edge on MCI1 does not affect counter 1." /> + <Enum name="RISING" start="1" description="If MODE1 is 1, counter 1 advances on a rising edge on MCI1." /> + </BitField> + <BitField start="9" size="1" name="TC1MCI1_FE" description="Counter 1 falling edge mode, channel 1."> + <Enum name="A_FALLING_EDGE_ON_MC" start="0" description="A falling edge on MCI0 does not affect counter 1." /> + <Enum name="FALLING" start="1" description="If MODE1 is 1, counter 1 advances on a falling edge on MCI1." /> + </BitField> + <BitField start="10" size="1" name="TC1MCI2_RE" description="Counter 1 rising edge mode, channel 2."> + <Enum name="A_RISING_EDGE_ON_MCI" start="0" description="A rising edge on MCI2 does not affect counter 1." /> + <Enum name="RISING" start="1" description="If MODE1 is 1, counter 1 advances on a rising edge on MCI2." /> + </BitField> + <BitField start="11" size="1" name="TC1MCI2_FE" description="Counter 1 falling edge mode, channel 2."> + <Enum name="A_FALLING_EDGE_ON_MC" start="0" description="A falling edge on MCI2 does not affect counter 1." /> + <Enum name="FALLING" start="1" description="If MODE1 is 1, counter 1 advances on a falling edge on MCI2." /> + </BitField> + <BitField start="12" size="1" name="TC2MCI0_RE" description="Counter 2 rising edge mode, channel 0."> + <Enum name="A_RISING_EDGE_ON_MCI" start="0" description="A rising edge on MCI0 does not affect counter 2." /> + <Enum name="RISING" start="1" description="If MODE2 is 1, counter 2 advances on a rising edge on MCI0." /> + </BitField> + <BitField start="13" size="1" name="TC2MCI0_FE" description="Counter 2 falling edge mode, channel 0."> + <Enum name="A_FALLING_EDGE_ON_MC" start="0" description="A falling edge on MCI0 does not affect counter 2." /> + <Enum name="FALLING" start="1" description="If MODE2 is 1, counter 2 advances on a falling edge on MCI0." /> + </BitField> + <BitField start="14" size="1" name="TC2MCI1_RE" description="Counter 2 rising edge mode, channel 1."> + <Enum name="A_RISING_EDGE_ON_MCI" start="0" description="A rising edge on MCI1 does not affect counter 2." /> + <Enum name="RISING" start="1" description="If MODE2 is 1, counter 2 advances on a rising edge on MCI1." /> + </BitField> + <BitField start="15" size="1" name="TC2MCI1_FE" description="Counter 2 falling edge mode, channel 1."> + <Enum name="A_FALLING_EDGE_ON_MC" start="0" description="A falling edge on MCI1 does not affect counter 2." /> + <Enum name="FALLING" start="1" description="If MODE2 is 1, counter 2 advances on a falling edge on MCI1." /> + </BitField> + <BitField start="16" size="1" name="TC2MCI2_RE" description="Counter 2 rising edge mode, channel 2."> + <Enum name="A_RISING_EDGE_ON_MCI" start="0" description="A rising edge on MCI2 does not affect counter 2." /> + <Enum name="RISIING" start="1" description="If MODE2 is 1, counter 2 advances on a rising edge on MCI2." /> + </BitField> + <BitField start="17" size="1" name="TC2MCI2_FE" description="Counter 2 falling edge mode, channel 2."> + <Enum name="A_FALLING_EDGE_ON_MC" start="0" description="A falling edge on MCI2 does not affect counter 2." /> + <Enum name="FALLING" start="1" description="If MODE2 is 1, counter 2 advances on a falling edge on MCI2." /> + </BitField> + <BitField start="18" size="11" name="RESERVED" description="Reserved." /> + <BitField start="29" size="1" name="CNTR0" description="Channel 0 counter/timer mode."> + <Enum name="CHANNEL_0_IS_IN_TIME" start="0" description="Channel 0 is in timer mode." /> + <Enum name="CHANNEL_0_IS_IN_COUN" start="1" description="Channel 0 is in counter mode." /> + </BitField> + <BitField start="30" size="1" name="CNTR1" description="Channel 1 counter/timer mode."> + <Enum name="CHANNEL_1_IS_IN_TIME" start="0" description="Channel 1 is in timer mode." /> + <Enum name="CHANNEL_1_IS_IN_COUN" start="1" description="Channel 1 is in counter mode." /> + </BitField> + <BitField start="31" size="1" name="CNTR2" description="Channel 2 counter/timer mode."> + <Enum name="CHANNEL_2_IS_IN_TIME" start="0" description="Channel 2 is in timer mode." /> + <Enum name="CHANNEL_2_IS_IN_COUN" start="1" description="Channel 2 is in counter mode." /> + </BitField> + </Register> + <Register start="+0x060" size="4" name="CNTCON_SET" access="WriteOnly" description="Count Control set address" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="TC0MCI0_RE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." /> + <BitField start="1" size="1" name="TC0MCI0_FE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." /> + <BitField start="2" size="1" name="TC0MCI1_RE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." /> + <BitField start="3" size="1" name="TC0MCI1_FE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." /> + <BitField start="4" size="1" name="TC0MCI2_RE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." /> + <BitField start="5" size="1" name="TC0MCI2_FE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." /> + <BitField start="6" size="1" name="TC1MCI0_RE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." /> + <BitField start="7" size="1" name="TC1MCI0_FE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." /> + <BitField start="8" size="1" name="TC1MCI1_RE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." /> + <BitField start="9" size="1" name="TC1MCI1_FE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." /> + <BitField start="10" size="1" name="TC1MCI2_RE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." /> + <BitField start="11" size="1" name="TC1MCI2_FE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." /> + <BitField start="12" size="1" name="TC2MCI0_RE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." /> + <BitField start="13" size="1" name="TC2MCI0_FE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." /> + <BitField start="14" size="1" name="TC2MCI1_RE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." /> + <BitField start="15" size="1" name="TC2MCI1_FE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." /> + <BitField start="16" size="1" name="TC2MCI2_RE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." /> + <BitField start="17" size="1" name="TC2MCI2_FE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." /> + <BitField start="18" size="11" name="RESERVED" description="Reserved." /> + <BitField start="29" size="1" name="CNTR0_SET" description="Writing a one sets the corresponding bit in the CNTCON register." /> + <BitField start="30" size="1" name="CNTR1_SET" description="Writing a one sets the corresponding bit in the CNTCON register." /> + <BitField start="31" size="1" name="CNTR2_SET" description="Writing a one sets the corresponding bit in the CNTCON register." /> + </Register> + <Register start="+0x064" size="4" name="CNTCON_CLR" access="WriteOnly" description="Count Control clear address" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="TC0MCI0_RE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." /> + <BitField start="1" size="1" name="TC0MCI0_FE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." /> + <BitField start="2" size="1" name="TC0MCI1_RE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." /> + <BitField start="3" size="1" name="TC0MCI1_FE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." /> + <BitField start="4" size="1" name="TC0MCI2_RE" description="Writing a one clears the corresponding bit in the CNTCON register." /> + <BitField start="5" size="1" name="TC0MCI2_FE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." /> + <BitField start="6" size="1" name="TC1MCI0_RE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." /> + <BitField start="7" size="1" name="TC1MCI0_FE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." /> + <BitField start="8" size="1" name="TC1MCI1_RE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." /> + <BitField start="9" size="1" name="TC1MCI1_FE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." /> + <BitField start="10" size="1" name="TC1MCI2_RE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." /> + <BitField start="11" size="1" name="TC1MCI2_FE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." /> + <BitField start="12" size="1" name="TC2MCI0_RE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." /> + <BitField start="13" size="1" name="TC2MCI0_FE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." /> + <BitField start="14" size="1" name="TC2MCI1_RE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." /> + <BitField start="15" size="1" name="TC2MCI1_FE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." /> + <BitField start="16" size="1" name="TC2MCI2_RE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." /> + <BitField start="17" size="1" name="TC2MCI2_FE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." /> + <BitField start="18" size="11" name="RESERVED" description="Reserved." /> + <BitField start="29" size="1" name="CNTR0_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." /> + <BitField start="30" size="1" name="CNTR1_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." /> + <BitField start="31" size="1" name="CNTR2_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." /> + </Register> + <Register start="+0x074" size="4" name="CAP_CLR" access="WriteOnly" description="Capture clear address" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="CAP_CLR0" description="Writing a 1 to this bit clears the CAP0 register." /> + <BitField start="1" size="1" name="CAP_CLR1" description="Writing a 1 to this bit clears the CAP1 register." /> + <BitField start="2" size="1" name="CAP_CLR2" description="Writing a 1 to this bit clears the CAP2 register." /> + <BitField start="3" size="29" name="RESERVED" description="Reserved" /> + </Register> + </RegisterGroup> + <RegisterGroup name="QEI" start="0x400BC000" description="Quadrature Encoder Interface (QEI) "> + <Register start="+0x000" size="4" name="CON" access="WriteOnly" description="Control register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="RESP" description="Reset position counter. When set = 1, resets the position counter to all zeros. Autoclears when the position counter is cleared." /> + <BitField start="1" size="1" name="RESPI" description="Reset position counter on index. When set = 1, resets the position counter to all zeros once only the first time an index pulse occurs. Autoclears when the position counter is cleared." /> + <BitField start="2" size="1" name="RESV" description="Reset velocity. When set = 1, resets the velocity counter to all zeros, reloads the velocity timer, and presets the velocity compare register. Autoclears when the velocity counter is cleared." /> + <BitField start="3" size="1" name="RESI" description="Reset index counter. When set = 1, resets the index counter to all zeros. Autoclears when the index counter is cleared." /> + <BitField start="4" size="28" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x008" size="4" name="CONF" access="Read/Write" description="Configuration register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="DIRINV" description="Direction invert. When 1, complements the DIR bit." /> + <BitField start="1" size="1" name="SIGMODE" description="Signal Mode. When 0, PhA and PhB function as quadrature encoder inputs. When 1, PhA functions as the direction signal and PhB functions as the clock signal." /> + <BitField start="2" size="1" name="CAPMODE" description="Capture Mode. When 0, only PhA edges are counted (2X). When 1, BOTH PhA and PhB edges are counted (4X), increasing resolution but decreasing range." /> + <BitField start="3" size="1" name="INVINX" description="Invert Index. When 1, inverts the sense of the index input." /> + <BitField start="4" size="1" name="CRESPI" description="Continuously reset the position counter on index. When 1, resets the position counter to all zeros whenever an index pulse occurs after the next position increase (recalibration)." /> + <BitField start="5" size="11" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="16" size="4" name="INXGATE" description="Index gating configuration: When INXGATE[16] = 1, pass the index when PHA = 1 and PHB = 0, otherwise block index. When INXGATE[17] = 1, pass the index when PHA = 1 and PHB = 1, otherwise block index. When INXGATE[18] = 1, pass the index when PHA = 0 and PHB = 1, otherwise block index. When INXGATE[19] = 1, pass the index when PHA = 0 and PHB = 0, otherwise block index." /> + <BitField start="20" size="12" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x004" size="4" name="STAT" access="ReadOnly" description="Status register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="DIR" description="Direction bit. In combination with DIRINV bit indicates forward or reverse direction. See Table 597." /> + <BitField start="1" size="31" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x00C" size="4" name="POS" access="ReadOnly" description="Position register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="POS" description="Current position value." /> + </Register> + <Register start="+0x010" size="4" name="MAXPOS" access="Read/Write" description="Maximum position register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="MAXPOS" description="Current maximum position value." /> + </Register> + <Register start="+0x014" size="4" name="CMPOS0" access="Read/Write" description="Position compare register 0" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="PCMP0" description="Position compare value 0." /> + </Register> + <Register start="+0x018" size="4" name="CMPOS1" access="Read/Write" description="Position compare register 1" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="PCMP1" description="Position compare value 1." /> + </Register> + <Register start="+0x01C" size="4" name="CMPOS2" access="Read/Write" description="Position compare register 2" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="PCMP2" description="Position compare value 2." /> + </Register> + <Register start="+0x020" size="4" name="INXCNT" access="ReadOnly" description="Index count register 0" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="ENCPOS" description="Current index counter value." /> + </Register> + <Register start="+0x024" size="4" name="INXCMP0" access="Read/Write" description="Index compare register 0" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="ICMP0" description="Index compare value 0." /> + </Register> + <Register start="+0x028" size="4" name="LOAD" access="Read/Write" description="Velocity timer reload register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="VELLOAD" description="Current velocity timer load value." /> + </Register> + <Register start="+0x02C" size="4" name="TIME" access="ReadOnly" description="Velocity timer register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="VELVAL" description="Current velocity timer value." /> + </Register> + <Register start="+0x030" size="4" name="VEL" access="ReadOnly" description="Velocity counter register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="VELPC" description="Current velocity pulse count." /> + </Register> + <Register start="+0x034" size="4" name="CAP" access="ReadOnly" description="Velocity capture register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="VELCAP" description="Last velocity capture." /> + </Register> + <Register start="+0x038" size="4" name="VELCOMP" access="Read/Write" description="Velocity compare register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="VELPC" description="Compare velocity pulse count." /> + </Register> + <Register start="+0x03C" size="4" name="FILTERPHA" access="Read/Write" description="Digital filter register on PHA" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="FILTA" description="Digital filter sampling delay for PhA." /> + </Register> + <Register start="+0x040" size="4" name="FILTERPHB" access="Read/Write" description="Digital filter register on PHB" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="FILTB" description="Digital filter sampling delay for PhB." /> + </Register> + <Register start="+0x044" size="4" name="FILTERINX" access="Read/Write" description="Digital filter register on IDX" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="FITLINX" description="Digital filter sampling delay for the index." /> + </Register> + <Register start="+0x048" size="4" name="WINDOW" access="Read/Write" description="Index acceptance window register" reset_value="0xF" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="WINDOW" description="Index acceptance window width." /> + </Register> + <Register start="+0x04C" size="4" name="INXCMP1" access="Read/Write" description="Index compare register 1" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="ICMP1" description="Index compare value 1." /> + </Register> + <Register start="+0x050" size="4" name="INXCMP2" access="Read/Write" description="Index compare register 2" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="ICMP2" description="Index compare value 2." /> + </Register> + <Register start="+0xFE0" size="4" name="INTSTAT" access="ReadOnly" description="Interrupt status register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="INX_INT" description="Indicates that an index pulse was detected." /> + <BitField start="1" size="1" name="TIM_INT" description="Indicates that a velocity timer overflow occurred" /> + <BitField start="2" size="1" name="VELC_INT" description="Indicates that captured velocity is less than compare velocity." /> + <BitField start="3" size="1" name="DIR_INT" description="Indicates that a change of direction was detected." /> + <BitField start="4" size="1" name="ERR_INT" description="Indicates that an encoder phase error was detected." /> + <BitField start="5" size="1" name="ENCLK_INT" description="Indicates that and encoder clock pulse was detected." /> + <BitField start="6" size="1" name="POS0_INT" description="Indicates that the position 0 compare value is equal to the current position." /> + <BitField start="7" size="1" name="POS1_INT" description="Indicates that the position 1compare value is equal to the current position." /> + <BitField start="8" size="1" name="POS2_INT" description="Indicates that the position 2 compare value is equal to the current position." /> + <BitField start="9" size="1" name="REV0_INT" description="Indicates that the index compare 0 value is equal to the current index count." /> + <BitField start="10" size="1" name="POS0REV_INT" description="Combined position 0 and revolution count interrupt. Set when both the POS0_Int bit is set and the REV0_Int is set." /> + <BitField start="11" size="1" name="POS1REV_INT" description="Combined position 1 and revolution count interrupt. Set when both the POS1_Int bit is set and the REV1_Int is set." /> + <BitField start="12" size="1" name="POS2REV_INT" description="Combined position 2 and revolution count interrupt. Set when both the POS2_Int bit is set and the REV2_Int is set." /> + <BitField start="13" size="1" name="REV1_INT" description="Indicates that the index compare 1value is equal to the current index count." /> + <BitField start="14" size="1" name="REV2_INT" description="Indicates that the index compare 2 value is equal to the current index count." /> + <BitField start="15" size="1" name="MAXPOS_INT" description="Indicates that the current position count goes through the MAXPOS value to zero in the forward direction, or through zero to MAXPOS in the reverse direction." /> + <BitField start="16" size="16" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0xFEC" size="4" name="SET" access="WriteOnly" description="Interrupt status set register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="INX_INT" description="Writing a 1 sets the INX_Int bit in QEIINTSTAT." /> + <BitField start="1" size="1" name="TIM_INT" description="Writing a 1 sets the TIN_Int bit in QEIINTSTAT." /> + <BitField start="2" size="1" name="VELC_INT" description="Writing a 1 sets the VELC_Int bit in QEIINTSTAT." /> + <BitField start="3" size="1" name="DIR_INT" description="Writing a 1 sets the DIR_Int bit in QEIINTSTAT." /> + <BitField start="4" size="1" name="ERR_INT" description="Writing a 1 sets the ERR_Int bit in QEIINTSTAT." /> + <BitField start="5" size="1" name="ENCLK_INT" description="Writing a 1 sets the ENCLK_Int bit in QEIINTSTAT." /> + <BitField start="6" size="1" name="POS0_INT" description="Writing a 1 sets the POS0_Int bit in QEIINTSTAT." /> + <BitField start="7" size="1" name="POS1_INT" description="Writing a 1 sets the POS1_Int bit in QEIINTSTAT." /> + <BitField start="8" size="1" name="POS2_INT" description="Writing a 1 sets the POS2_Int bit in QEIINTSTAT." /> + <BitField start="9" size="1" name="REV0_INT" description="Writing a 1 sets the REV0_Int bit in QEIINTSTAT." /> + <BitField start="10" size="1" name="POS0REV_INT" description="Writing a 1 sets the POS0REV_Int bit in QEIINTSTAT." /> + <BitField start="11" size="1" name="POS1REV_INT" description="Writing a 1 sets the POS1REV_Int bit in QEIINTSTAT." /> + <BitField start="12" size="1" name="POS2REV_INT" description="Writing a 1 sets the POS2REV_Int bit in QEIINTSTAT." /> + <BitField start="13" size="1" name="REV1_INT" description="Writing a 1 sets the REV1_Int bit in QEIINTSTAT." /> + <BitField start="14" size="1" name="REV2_INT" description="Writing a 1 sets the REV2_Int bit in QEIINTSTAT." /> + <BitField start="15" size="1" name="MAXPOS_INT" description="Writing a 1 sets the MAXPOS_Int bit in QEIINTSTAT." /> + <BitField start="16" size="16" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0xFE8" size="4" name="CLR" access="WriteOnly" description="Interrupt status clear register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="INX_INT" description="Writing a 1 clears the INX_Int bit in QEIINTSTAT." /> + <BitField start="1" size="1" name="TIM_INT" description="Writing a 1 clears the TIN_Int bit in QEIINTSTAT." /> + <BitField start="2" size="1" name="VELC_INT" description="Writing a 1 clears the VELC_Int bit in QEIINTSTAT." /> + <BitField start="3" size="1" name="DIR_INT" description="Writing a 1 clears the DIR_Int bit in QEIINTSTAT." /> + <BitField start="4" size="1" name="ERR_INT" description="Writing a 1 clears the ERR_Int bit in QEIINTSTAT." /> + <BitField start="5" size="1" name="ENCLK_INT" description="Writing a 1 clears the ENCLK_Int bit in QEIINTSTAT." /> + <BitField start="6" size="1" name="POS0_INT" description="Writing a 1 clears the POS0_Int bit in QEIINTSTAT." /> + <BitField start="7" size="1" name="POS1_INT" description="Writing a 1 clears the POS1_Int bit in QEIINTSTAT." /> + <BitField start="8" size="1" name="POS2_INT" description="Writing a 1 clears the POS2_Int bit in QEIINTSTAT." /> + <BitField start="9" size="1" name="REV0_INT" description="Writing a 1 clears the REV0_Int bit in QEIINTSTAT." /> + <BitField start="10" size="1" name="POS0REV_INT" description="Writing a 1 clears the POS0REV_Int bit in QEIINTSTAT." /> + <BitField start="11" size="1" name="POS1REV_INT" description="Writing a 1 clears the POS1REV_Int bit in QEIINTSTAT." /> + <BitField start="12" size="1" name="POS2REV_INT" description="Writing a 1 clears the POS2REV_Int bit in QEIINTSTAT." /> + <BitField start="13" size="1" name="REV1_INT" description="Writing a 1 clears the REV1_Int bit in QEIINTSTAT." /> + <BitField start="14" size="1" name="REV2_INT" description="Writing a 1 clears the REV2_Int bit in QEIINTSTAT." /> + <BitField start="15" size="1" name="MAXPOS_INT" description="Writing a 1 clears the MAXPOS_Int bit in QEIINTSTAT." /> + <BitField start="16" size="16" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0xFE4" size="4" name="IE" access="ReadOnly" description="Interrupt enable register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="INX_INT" description="When 1, the INX_Int interrupt is enabled." /> + <BitField start="1" size="1" name="TIM_INT" description="When 1, the TIN_Int interrupt is enabled." /> + <BitField start="2" size="1" name="VELC_INT" description="When 1, the VELC_Int interrupt is enabled." /> + <BitField start="3" size="1" name="DIR_INT" description="When 1, the DIR_Int interrupt is enabled." /> + <BitField start="4" size="1" name="ERR_INT" description="When 1, the ERR_Int interrupt is enabled." /> + <BitField start="5" size="1" name="ENCLK_INT" description="When 1, the ENCLK_Int interrupt is enabled." /> + <BitField start="6" size="1" name="POS0_INT" description="When 1, the POS0_Int interrupt is enabled." /> + <BitField start="7" size="1" name="POS1_INT" description="When 1, the POS1_Int interrupt is enabled." /> + <BitField start="8" size="1" name="POS2_INT" description="When 1, the POS2_Int interrupt is enabled." /> + <BitField start="9" size="1" name="REV0_INT" description="When 1, the REV0_Int interrupt is enabled." /> + <BitField start="10" size="1" name="POS0REV_INT" description="When 1, the POS0REV_Int interrupt is enabled." /> + <BitField start="11" size="1" name="POS1REV_INT" description="When 1, the POS1REV_Int interrupt is enabled." /> + <BitField start="12" size="1" name="POS2REV_INT" description="When 1, the POS2REV_Int interrupt is enabled." /> + <BitField start="13" size="1" name="REV1_INT" description="When 1, the REV1_Int interrupt is enabled." /> + <BitField start="14" size="1" name="REV2_INT" description="When 1, the REV2_Int interrupt is enabled." /> + <BitField start="15" size="1" name="MAXPOS_INT" description="When 1, the MAXPOS_Int interrupt is enabled." /> + <BitField start="16" size="16" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0xFDC" size="4" name="IES" access="WriteOnly" description="Interrupt enable set register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="INX_INT" description="Writing a 1 enables the INX_Int interrupt in the QEIIE register." /> + <BitField start="1" size="1" name="TIM_INT" description="Writing a 1 enables the TIN_Int interrupt in the QEIIE register." /> + <BitField start="2" size="1" name="VELC_INT" description="Writing a 1 enables the VELC_Int interrupt in the QEIIE register." /> + <BitField start="3" size="1" name="DIR_INT" description="Writing a 1 enables the DIR_Int interrupt in the QEIIE register." /> + <BitField start="4" size="1" name="ERR_INT" description="Writing a 1 enables the ERR_Int interrupt in the QEIIE register." /> + <BitField start="5" size="1" name="ENCLK_INT" description="Writing a 1 enables the ENCLK_Int interrupt in the QEIIE register." /> + <BitField start="6" size="1" name="POS0_INT" description="Writing a 1 enables the POS0_Int interrupt in the QEIIE register." /> + <BitField start="7" size="1" name="POS1_INT" description="Writing a 1 enables the POS1_Int interrupt in the QEIIE register." /> + <BitField start="8" size="1" name="POS2_INT" description="Writing a 1 enables the POS2_Int interrupt in the QEIIE register." /> + <BitField start="9" size="1" name="REV0_INT" description="Writing a 1 enables the REV0_Int interrupt in the QEIIE register." /> + <BitField start="10" size="1" name="POS0REV_INT" description="Writing a 1 enables the POS0REV_Int interrupt in the QEIIE register." /> + <BitField start="11" size="1" name="POS1REV_INT" description="Writing a 1 enables the POS1REV_Int interrupt in the QEIIE register." /> + <BitField start="12" size="1" name="POS2REV_INT" description="Writing a 1 enables the POS2REV_Int interrupt in the QEIIE register." /> + <BitField start="13" size="1" name="REV1_INT" description="Writing a 1 enables the REV1_Int interrupt in the QEIIE register." /> + <BitField start="14" size="1" name="REV2_INT" description="Writing a 1 enables the REV2_Int interrupt in the QEIIE register." /> + <BitField start="15" size="1" name="MAXPOS_INT" description="Writing a 1 enables the MAXPOS_Int interrupt in the QEIIE register." /> + <BitField start="16" size="16" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0xFD8" size="4" name="IEC" access="WriteOnly" description="Interrupt enable clear register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="INX_INT" description="Writing a 1 disables the INX_Int interrupt in the QEIIE register." /> + <BitField start="1" size="1" name="TIM_INT" description="Writing a 1 disables the TIN_Int interrupt in the QEIIE register." /> + <BitField start="2" size="1" name="VELC_INT" description="Writing a 1 disables the VELC_Int interrupt in the QEIIE register." /> + <BitField start="3" size="1" name="DIR_INT" description="Writing a 1 disables the DIR_Int interrupt in the QEIIE register." /> + <BitField start="4" size="1" name="ERR_INT" description="Writing a 1 disables the ERR_Int interrupt in the QEIIE register." /> + <BitField start="5" size="1" name="ENCLK_INT" description="Writing a 1 disables the ENCLK_Int interrupt in the QEIIE register." /> + <BitField start="6" size="1" name="POS0_INT" description="Writing a 1 disables the POS0_Int interrupt in the QEIIE register." /> + <BitField start="7" size="1" name="POS1_INT" description="Writing a 1 disables the POS1_Int interrupt in the QEIIE register." /> + <BitField start="8" size="1" name="POS2_INT" description="Writing a 1 disables the POS2_Int interrupt in the QEIIE register." /> + <BitField start="9" size="1" name="REV0_INT" description="Writing a 1 disables the REV0_Int interrupt in the QEIIE register." /> + <BitField start="10" size="1" name="POS0REV_INT" description="Writing a 1 disables the POS0REV_Int interrupt in the QEIIE register." /> + <BitField start="11" size="1" name="POS1REV_INT" description="Writing a 1 disables the POS1REV_Int interrupt in the QEIIE register." /> + <BitField start="12" size="1" name="POS2REV_INT" description="Writing a 1 disables the POS2REV_Int interrupt in the QEIIE register." /> + <BitField start="13" size="1" name="REV1_INT" description="Writing a 1 disables the REV1_Int interrupt in the QEIIE register." /> + <BitField start="14" size="1" name="REV2_INT" description="Writing a 1 disables the REV2_Int interrupt in the QEIIE register." /> + <BitField start="15" size="1" name="MAXPOS_INT" description="Writing a 1 disables the MAXPOS_Int interrupt in the QEIIE register." /> + <BitField start="16" size="16" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + </RegisterGroup> + <RegisterGroup name="SDMMC" start="0x400C0000" description="SD card"> + <Register start="+0x000" size="4" name="PWR" access="Read/Write" description="Power control register." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="CTRL" description="Power control"> + <Enum name="POWER_OFF" start="0x0" description="Power-off" /> + <Enum name="POWER_UP" start="0x2" description="Power-up" /> + <Enum name="POWER_ON" start="0x3" description="Power-on" /> + </BitField> + <BitField start="2" size="4" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="6" size="1" name="OPENDRAIN" description="SD_CMD output control." /> + <BitField start="7" size="1" name="ROD" description="Rod control." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x004" size="4" name="CLOCK" access="Read/Write" description="Clock control register." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="CLKDIV" description="Bus clock period: SD_CLK frequency = MCLK / [2x(ClkDiv+1)]." /> + <BitField start="8" size="1" name="ENABLE" description="Enable SD card bus clock:"> + <Enum name="CLOCK_DISABLED_" start="0" description="Clock disabled." /> + <Enum name="CLOCK_ENABLED_" start="1" description="Clock enabled." /> + </BitField> + <BitField start="9" size="1" name="PWRSAVE" description="Disable SD_CLK output when bus is idle:"> + <Enum name="ALWAYS_ENABLED_" start="0" description="Always enabled." /> + <Enum name="CLOCK_ENABLED_WHEN_B" start="1" description="Clock enabled when bus is active." /> + </BitField> + <BitField start="10" size="1" name="BYPASS" description="Enable bypass of clock divide logic:"> + <Enum name="DISABLE_BYPASS_" start="0" description="Disable bypass." /> + <Enum name="ENABLE_BYPASS_MCLK_" start="1" description="Enable bypass. MCLK driven to card bus output (SD_CLK)." /> + </BitField> + <BitField start="11" size="1" name="WIDEBUS" description="Enable wide bus mode."> + <Enum name="STANDARD_BUS_MODE_O" start="0" description="Standard bus mode (only SD_DAT[0] used)." /> + <Enum name="WIDE_BUS_MODE_SD_DA" start="1" description="Wide bus mode (SD_DAT[3:0] used)" /> + </BitField> + <BitField start="12" size="20" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x008" size="4" name="ARGUMENT" access="Read/Write" description="Argument register." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CmdArg" description="Command argument" /> + </Register> + <Register start="+0x00C" size="4" name="COMMAND" access="Read/Write" description="Command register." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="6" name="CmdIndex" description="Command index." /> + <BitField start="6" size="1" name="Response" description="If set, CPSM waits for a response." /> + <BitField start="7" size="1" name="LongRsp" description="If set, CPSM receives a 136 bit long response." /> + <BitField start="8" size="1" name="Interrupt" description="If set, CPSM disables command timer and waits for interrupt request." /> + <BitField start="9" size="1" name="Pending" description="If set, CPSM waits for CmdPend before it starts sending a command." /> + <BitField start="10" size="1" name="Enable" description="If set, CPSM is enabled." /> + <BitField start="11" size="21" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x010" size="4" name="RESPCMD" access="ReadOnly" description="Response command register." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="6" name="RESPCMD" description="Response command index" /> + <BitField start="6" size="26" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x014+0" size="4" name="RESPONSE0" access="ReadOnly" description="Response register." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="STATUS" description="Card status" /> + </Register> + <Register start="+0x014+4" size="4" name="RESPONSE1" access="ReadOnly" description="Response register." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="STATUS" description="Card status" /> + </Register> + <Register start="+0x014+8" size="4" name="RESPONSE2" access="ReadOnly" description="Response register." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="STATUS" description="Card status" /> + </Register> + <Register start="+0x014+12" size="4" name="RESPONSE3" access="ReadOnly" description="Response register." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="STATUS" description="Card status" /> + </Register> + <Register start="+0x024" size="4" name="DATATIMER" access="Read/Write" description="Data Timer." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="DATATIME" description="Data timeout period." /> + </Register> + <Register start="+0x028" size="4" name="DATALENGTH" access="Read/Write" description="Data length register." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="16" name="DATALENGTH" description="Data length value" /> + <BitField start="16" size="16" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x02C" size="4" name="DATACTRL" access="Read/Write" description="Data control register." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="ENABLE" description="Data transfer enable." /> + <BitField start="1" size="1" name="DIRECTION" description="Data transfer direction"> + <Enum name="FROM_CONTROLLER_TO_C" start="0" description="From controller to card." /> + <Enum name="FROM_CARD_TO_CONTROL" start="1" description="From card to controller." /> + </BitField> + <BitField start="2" size="1" name="MODE" description="Data transfer mode"> + <Enum name="BLOCK_DATA_TRANSFER_" start="0" description="Block data transfer." /> + <Enum name="STREAM_DATA_TRANSFER" start="1" description="Stream data transfer." /> + </BitField> + <BitField start="3" size="1" name="DMAENABLE" description="Enable DMA"> + <Enum name="DMA_DISABLED_" start="0" description="DMA disabled." /> + <Enum name="DMA_ENABLED_" start="1" description="DMA enabled." /> + </BitField> + <BitField start="4" size="4" name="BLOCKSIZE" description="Data block length" /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x030" size="4" name="DATACNT" access="ReadOnly" description="Data counter." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="16" name="DATACOUNT" description="Remaining data" /> + <BitField start="16" size="16" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x034" size="4" name="STATUS" access="ReadOnly" description="Status register." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="CMDCRCFAIL" description="Command response received (CRC check failed)." /> + <BitField start="1" size="1" name="DATACRCFAIL" description="Data block sent/received (CRC check failed)." /> + <BitField start="2" size="1" name="CMDTIMEOUT" description="Command response timeout." /> + <BitField start="3" size="1" name="DATATIMEOUT" description="Data timeout." /> + <BitField start="4" size="1" name="TXUNDERRUN" description="Transmit FIFO underrun error." /> + <BitField start="5" size="1" name="RXOVERRUN" description="Receive FIFO overrun error." /> + <BitField start="6" size="1" name="CMDRESPEND" description="Command response received (CRC check passed)." /> + <BitField start="7" size="1" name="CMDSENT" description="Command sent (no response required)." /> + <BitField start="8" size="1" name="DATAEND" description="Data end (data counter is zero)." /> + <BitField start="9" size="1" name="STARTBITERR" description="Start bit not detected on all data signals in wide bus mode." /> + <BitField start="10" size="1" name="DATABLOCKEND" description="Data block sent/received (CRC check passed)." /> + <BitField start="11" size="1" name="CMDACTIVE" description="Command transfer in progress." /> + <BitField start="12" size="1" name="TXACTIVE" description="Data transmit in progress." /> + <BitField start="13" size="1" name="RXACTIVE" description="Data receive in progress." /> + <BitField start="14" size="1" name="TXFIFOHALFEMPTY" description="Transmit FIFO half empty." /> + <BitField start="15" size="1" name="RXFIFOHALFFULL" description="Receive FIFO half full." /> + <BitField start="16" size="1" name="TXFIFOFULL" description="Transmit FIFO full." /> + <BitField start="17" size="1" name="RXFIFOFULL" description="Receive FIFO full." /> + <BitField start="18" size="1" name="TXFIFOEMPTY" description="Transmit FIFO empty." /> + <BitField start="19" size="1" name="RXFIFOEMPTY" description="Receive FIFO empty." /> + <BitField start="20" size="1" name="TXDATAAVLBL" description="Data available in transmit FIFO." /> + <BitField start="21" size="1" name="RXDATAAVLBL" description="Data available in receive FIFO." /> + <BitField start="22" size="10" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x038" size="4" name="CLEAR" access="WriteOnly" description="Clear register." reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="CMDCRCFAILCLR" description="Clears CmdCrcFail flag." /> + <BitField start="1" size="1" name="DATACRCFAILCLR" description="Clears DataCrcFail flag." /> + <BitField start="2" size="1" name="CMDTIMEOUTCLR" description="Clears CmdTimeOut flag." /> + <BitField start="3" size="1" name="DATATIMEOUTCLR" description="Clears DataTimeOut flag." /> + <BitField start="4" size="1" name="TXUNDERRUNCLR" description="Clears TxUnderrun flag." /> + <BitField start="5" size="1" name="RXOVERRUNCLR" description="Clears RxOverrun flag." /> + <BitField start="6" size="1" name="CMDRESPENDCLR" description="Clears CmdRespEnd flag." /> + <BitField start="7" size="1" name="CMDSENTCLR" description="Clears CmdSent flag." /> + <BitField start="8" size="1" name="DATAENDCLR" description="Clears DataEnd flag." /> + <BitField start="9" size="1" name="STARTBITERRCLR" description="Clears StartBitErr flag." /> + <BitField start="10" size="1" name="DATABLOCKENDCLR" description="Clears DataBlockEnd flag." /> + <BitField start="11" size="21" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x03C" size="4" name="MASK0" access="Read/Write" description="Interrupt 0 mask register." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="MASK0" description="Mask CmdCrcFail flag." /> + <BitField start="1" size="1" name="MASK1" description="Mask DataCrcFail flag." /> + <BitField start="2" size="1" name="MASK2" description="Mask CmdTimeOut flag." /> + <BitField start="3" size="1" name="MASK3" description="Mask DataTimeOut flag." /> + <BitField start="4" size="1" name="MASK4" description="Mask TxUnderrun flag." /> + <BitField start="5" size="1" name="MASK5" description="Mask RxOverrun flag." /> + <BitField start="6" size="1" name="MASK6" description="Mask CmdRespEnd flag." /> + <BitField start="7" size="1" name="MASK7" description="Mask CmdSent flag." /> + <BitField start="8" size="1" name="MASK8" description="Mask DataEnd flag." /> + <BitField start="9" size="1" name="MASK9" description="Mask StartBitErr flag." /> + <BitField start="10" size="1" name="MASK10" description="Mask DataBlockEnd flag." /> + <BitField start="11" size="1" name="MASK11" description="Mask CmdActive flag." /> + <BitField start="12" size="1" name="MASK12" description="Mask TxActive flag." /> + <BitField start="13" size="1" name="MASK13" description="Mask RxActive flag." /> + <BitField start="14" size="1" name="MASK14" description="Mask TxFifoHalfEmpty flag." /> + <BitField start="15" size="1" name="MASK15" description="Mask RxFifoHalfFull flag." /> + <BitField start="16" size="1" name="MASK16" description="Mask TxFifoFull flag." /> + <BitField start="17" size="1" name="MASK17" description="Mask RxFifoFull flag." /> + <BitField start="18" size="1" name="MASK18" description="Mask TxFifoEmpty flag." /> + <BitField start="19" size="1" name="MASK19" description="Mask RxFifoEmpty flag." /> + <BitField start="20" size="1" name="MASK20" description="Mask TxDataAvlbl flag." /> + <BitField start="21" size="1" name="MASK21" description="Mask RxDataAvlbl flag." /> + <BitField start="22" size="10" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x048" size="4" name="FIFOCNT" access="ReadOnly" description="FIFO Counter." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="15" name="DATACOUNT" description="Remaining data" /> + <BitField start="15" size="17" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x080+0" size="4" name="FIFO0" access="Read/Write" description="Data FIFO Register." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="DATA" description="FIFO data." /> + </Register> + <Register start="+0x080+4" size="4" name="FIFO1" access="Read/Write" description="Data FIFO Register." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="DATA" description="FIFO data." /> + </Register> + <Register start="+0x080+8" size="4" name="FIFO2" access="Read/Write" description="Data FIFO Register." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="DATA" description="FIFO data." /> + </Register> + <Register start="+0x080+12" size="4" name="FIFO3" access="Read/Write" description="Data FIFO Register." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="DATA" description="FIFO data." /> + </Register> + <Register start="+0x080+16" size="4" name="FIFO4" access="Read/Write" description="Data FIFO Register." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="DATA" description="FIFO data." /> + </Register> + <Register start="+0x080+20" size="4" name="FIFO5" access="Read/Write" description="Data FIFO Register." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="DATA" description="FIFO data." /> + </Register> + <Register start="+0x080+24" size="4" name="FIFO6" access="Read/Write" description="Data FIFO Register." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="DATA" description="FIFO data." /> + </Register> + <Register start="+0x080+28" size="4" name="FIFO7" access="Read/Write" description="Data FIFO Register." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="DATA" description="FIFO data." /> + </Register> + <Register start="+0x080+32" size="4" name="FIFO8" access="Read/Write" description="Data FIFO Register." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="DATA" description="FIFO data." /> + </Register> + <Register start="+0x080+36" size="4" name="FIFO9" access="Read/Write" description="Data FIFO Register." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="DATA" description="FIFO data." /> + </Register> + <Register start="+0x080+40" size="4" name="FIFO10" access="Read/Write" description="Data FIFO Register." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="DATA" description="FIFO data." /> + </Register> + <Register start="+0x080+44" size="4" name="FIFO11" access="Read/Write" description="Data FIFO Register." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="DATA" description="FIFO data." /> + </Register> + <Register start="+0x080+48" size="4" name="FIFO12" access="Read/Write" description="Data FIFO Register." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="DATA" description="FIFO data." /> + </Register> + <Register start="+0x080+52" size="4" name="FIFO13" access="Read/Write" description="Data FIFO Register." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="DATA" description="FIFO data." /> + </Register> + <Register start="+0x080+56" size="4" name="FIFO14" access="Read/Write" description="Data FIFO Register." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="DATA" description="FIFO data." /> + </Register> + <Register start="+0x080+60" size="4" name="FIFO15" access="Read/Write" description="Data FIFO Register." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="DATA" description="FIFO data." /> + </Register> + </RegisterGroup> + <RegisterGroup name="SYSCON" start="0x400FC000" description=" System and clock control "> + <Register start="+0x000" size="4" name="FLASHCFG" access="Read/Write" description="Flash Accelerator Configuration Register. Controls flash access timing." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="12" name="RESERVED" description="Reserved, user software should not change these bits from the reset value." /> + <BitField start="12" size="4" name="FLASHTIM" description="Flash access time. The value of this field plus 1 gives the number of CPU clocks used for a flash access. Warning: improper setting of this value may result in incorrect operation of the device. All other values are reserved."> + <Enum name="FLASH_ACCESSES_USE_1" start="0x0" description="Flash accesses use 1 CPU clock. Use for up to 20 MHz CPU clock with power boost off." /> + <Enum name="FLASH_ACCESSES_USE_2" start="0x1" description="Flash accesses use 2 CPU clocks. Use for up to 40 MHz CPU clock with power boost off." /> + <Enum name="FLASH_ACCESSES_USE_3" start="0x2" description="Flash accesses use 3 CPU clocks. Use for up to 60 MHz CPU clock with power boost off." /> + <Enum name="FLASH_ACCESSES_USE_4" start="0x3" description="Flash accesses use 4 CPU clocks. Use for up to 80 MHz CPU clock with power boost off. Use this setting for operation from 100 to 120 MHz operation with power boost on." /> + <Enum name="FLASH_ACCESSES_USE_5" start="0x4" description="Flash accesses use 5 CPU clocks. Use for up to 100 MHz CPU clock with power boost off." /> + <Enum name="FLASH_ACCESSES_USE_6" start="0x5" description="Flash accesses use 6 CPU clocks. Safe setting for any allowed conditions." /> + </BitField> + <BitField start="16" size="16" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x080+0" size="4" name="PLLCON0" access="Read/Write" description="PLL Control register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="PLLE" description="PLL Enable. When one, and after a valid PLL feed, this bit will activate the related PLL and allow it to lock to the requested frequency. See PLLSTAT register, Table 12." /> + <BitField start="1" size="31" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x080+32" size="4" name="PLLCON1" access="Read/Write" description="PLL Control register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="PLLE" description="PLL Enable. When one, and after a valid PLL feed, this bit will activate the related PLL and allow it to lock to the requested frequency. See PLLSTAT register, Table 12." /> + <BitField start="1" size="31" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x084+0" size="4" name="PLLCFG0" access="Read/Write" description="PLL Configuration register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="MSEL" description="PLL Multiplier value. Supplies the value "M" in the PLL frequency calculations. Note: For details on selecting the right value for MSEL see Section 3.10.4." /> + <BitField start="5" size="2" name="PSEL" description="PLL Divider value. Supplies the value "P" in the PLL frequency calculations. Note: For details on selecting the right value for PSEL see Section 3.10.4." /> + <BitField start="7" size="25" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x084+32" size="4" name="PLLCFG1" access="Read/Write" description="PLL Configuration register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="MSEL" description="PLL Multiplier value. Supplies the value "M" in the PLL frequency calculations. Note: For details on selecting the right value for MSEL see Section 3.10.4." /> + <BitField start="5" size="2" name="PSEL" description="PLL Divider value. Supplies the value "P" in the PLL frequency calculations. Note: For details on selecting the right value for PSEL see Section 3.10.4." /> + <BitField start="7" size="25" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x088+0" size="4" name="PLLSTAT0" access="ReadOnly" description="PLL Status register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="MSEL" description="Read-back for the PLL Multiplier value. This is the value currently used by the related PLL." /> + <BitField start="5" size="2" name="PSEL" description="Read-back for the PLL Divider value. This is the value currently used by the related PLL." /> + <BitField start="7" size="1" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + <BitField start="8" size="1" name="PLLE_STAT" description="Read-back for the PLL Enable bit. When one, the related PLL is currently activated. When zero, the related PLL is turned off. This bit is automatically cleared when Power-down mode is activated." /> + <BitField start="9" size="1" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + <BitField start="10" size="1" name="PLOCK" description="Reflects the PLL Lock status. When zero, the related PLL is not locked. When one, the related PLL is locked onto the requested frequency." /> + <BitField start="11" size="21" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x088+32" size="4" name="PLLSTAT1" access="ReadOnly" description="PLL Status register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="MSEL" description="Read-back for the PLL Multiplier value. This is the value currently used by the related PLL." /> + <BitField start="5" size="2" name="PSEL" description="Read-back for the PLL Divider value. This is the value currently used by the related PLL." /> + <BitField start="7" size="1" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + <BitField start="8" size="1" name="PLLE_STAT" description="Read-back for the PLL Enable bit. When one, the related PLL is currently activated. When zero, the related PLL is turned off. This bit is automatically cleared when Power-down mode is activated." /> + <BitField start="9" size="1" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + <BitField start="10" size="1" name="PLOCK" description="Reflects the PLL Lock status. When zero, the related PLL is not locked. When one, the related PLL is locked onto the requested frequency." /> + <BitField start="11" size="21" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x08C+0" size="4" name="PLLFEED0" access="WriteOnly" description="PLL Feed register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="8" name="PLLFEED" description="The PLL feed sequence must be written to this register in order for the related PLL's configuration and control register changes to take effect." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x08C+32" size="4" name="PLLFEED1" access="WriteOnly" description="PLL Feed register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="8" name="PLLFEED" description="The PLL feed sequence must be written to this register in order for the related PLL's configuration and control register changes to take effect." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x0C0" size="4" name="PCON" access="Read/Write" description="Power Control register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="PM0" description="Power mode control bit 0. This bit controls entry to the Power-down mode. See Section 3.3.6.1 below for details." /> + <BitField start="1" size="1" name="PM1" description="Power mode control bit 1. This bit controls entry to the Deep Power-down mode. See Section 3.3.6.1 below for details." /> + <BitField start="2" size="1" name="BODRPM" description="Brown-Out Reduced Power Mode. When BODRPM is 1, the Brown-Out Detect circuitry will be turned off when chip Power-down mode or Deep Sleep mode is entered, resulting in a further reduction in power usage. However, the possibility of using Brown-Out Detect as a wake-up source from the reduced power mode will be lost. When 0, the Brown-Out Detect function remains active during Power-down and Deep Sleep modes. See the System Control Block chapter for details of Brown-Out detection." /> + <BitField start="3" size="1" name="BOGD" description="Brown-Out Global Disable. When BOGD is 1, the Brown-Out Detect circuitry is fully disabled at all times, and does not consume power. When 0, the Brown-Out Detect circuitry is enabled. See the System Control Block chapter for details of Brown-Out detection." /> + <BitField start="4" size="1" name="BORD" description="Brown-Out Reset Disable. When BORD is 1, the BOD will not reset the device when the VDD(REG)(3V3) voltage dips goes below the BOD reset trip level. The Brown-Out interrupt is not affected. When BORD is 0, the BOD reset is enabled. See the Section 3.6 for details of Brown-Out detection." /> + <BitField start="3" size="5" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="8" size="1" name="SMFLAG" description="Sleep Mode entry flag. Set when the Sleep mode is successfully entered. Cleared by software writing a one to this bit." /> + <BitField start="9" size="1" name="DSFLAG" description="Deep Sleep entry flag. Set when the Deep Sleep mode is successfully entered. Cleared by software writing a one to this bit." /> + <BitField start="10" size="1" name="PDFLAG" description="Power-down entry flag. Set when the Power-down mode is successfully entered. Cleared by software writing a one to this bit." /> + <BitField start="11" size="1" name="DPDFLAG" description="Deep Power-down entry flag. Set when the Deep Power-down mode is successfully entered. Cleared by software writing a one to this bit." /> + <BitField start="12" size="20" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x0C4" size="4" name="PCONP0" access="Read/Write" description="Power Control for Peripherals" reset_value="0x0408829E" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="PCLCD" description="LCD controller power/clock control bit." /> + <BitField start="1" size="1" name="PCTIM0" description="Timer/Counter 0 power/clock control bit." /> + <BitField start="2" size="1" name="PCTIM1" description="Timer/Counter 1 power/clock control bit." /> + <BitField start="3" size="1" name="PCUART0" description="UART0 power/clock control bit." /> + <BitField start="4" size="1" name="PCUART1" description="UART1 power/clock control bit." /> + <BitField start="5" size="1" name="PCPWM0" description="PWM0 power/clock control bit." /> + <BitField start="6" size="1" name="PCPWM1" description="PWM1 power/clock control bit." /> + <BitField start="7" size="1" name="PCI2C0" description="I2C0 interface power/clock control bit." /> + <BitField start="8" size="1" name="PCUART4" description="UART4 power/clock control bit." /> + <BitField start="9" size="1" name="PCRTC" description="RTC and Event Monitor/Recorder power/clock control bit." /> + <BitField start="10" size="1" name="PCSSP1" description="SSP 1 interface power/clock control bit." /> + <BitField start="11" size="1" name="PCEMC" description="External Memory Controller power/clock control bit." /> + <BitField start="12" size="1" name="PCADC" description="A/D converter (ADC) power/clock control bit. Note: Clear the PDN bit in the AD0CR before clearing this bit, and set this bit before attempting to set PDN." /> + <BitField start="13" size="1" name="PCCAN1" description="CAN Controller 1 power/clock control bit." /> + <BitField start="14" size="1" name="PCCAN2" description="CAN Controller 2 power/clock control bit." /> + <BitField start="15" size="1" name="PCGPIO" description="Power/clock control bit for IOCON, GPIO, and GPIO interrupts." /> + <BitField start="16" size="1" name="PCSPIFI" description="SPI Flash Interface power/clock control bit." /> + <BitField start="17" size="1" name="PCMCPWM" description="Motor Control PWM power/clock control bit." /> + <BitField start="18" size="1" name="PCQEI" description="Quadrature Encoder Interface power/clock control bit." /> + <BitField start="19" size="1" name="PCI2C1" description="I2C1 interface power/clock control bit." /> + <BitField start="20" size="1" name="PCSSP2" description="SSP2 interface power/clock control bit." /> + <BitField start="21" size="1" name="PCSSP0" description="SSP0 interface power/clock control bit." /> + <BitField start="22" size="1" name="PCTIM2" description="Timer 2 power/clock control bit." /> + <BitField start="23" size="1" name="PCTIM3" description="Timer 3 power/clock control bit." /> + <BitField start="24" size="1" name="PCUART2" description="UART 2 power/clock control bit." /> + <BitField start="25" size="1" name="PCUART3" description="UART 3 power/clock control bit." /> + <BitField start="26" size="1" name="PCI2C2" description="I2C interface 2 power/clock control bit." /> + <BitField start="27" size="1" name="PCI2S" description="I2S interface power/clock control bit." /> + <BitField start="28" size="1" name="PCSDC" description="SD Card interface power/clock control bit." /> + <BitField start="29" size="1" name="PCGPDMA" description="GPDMA function power/clock control bit." /> + <BitField start="30" size="1" name="PCENET" description="Ethernet block power/clock control bit." /> + <BitField start="31" size="1" name="PCUSB" description="USB interface power/clock control bit." /> + </Register> + <Register start="+0x0C8" size="4" name="PCONP1" access="Read/Write" description="Power Control for Peripherals" reset_value="0x00000000" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="RESERVED" description="Reserved." /> + <BitField start="3" size="1" name="PCCMP" description="comparator 0/1 power/clock control bit." /> + <BitField start="4" size="28" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x100" size="4" name="EMCCLKSEL" access="Read/Write" description="External Memory Controller Clock Selection register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="EMCDIV" description="Selects the EMC clock rate relative to the CPU clock."> + <Enum name="THE_EMC_USES_THE_SAM" start="0" description="The EMC uses the same clock as the CPU." /> + <Enum name="THE_EMC_USES_A_CLOCK" start="1" description="The EMC uses a clock at half the rate of the CPU." /> + </BitField> + <BitField start="1" size="31" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x104" size="4" name="CCLKSEL" access="Read/Write" description="CPU Clock Selection register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="5" name="CCLKDIV" description="Selects the divide value for creating the CPU clock (CCLK) from the selected clock source. 0 = The divider is turned off., no clock will be provided to the CPU. This setting should typically not be used, the CPU will be halted and a reset will be required to restore operation. 1 = The input clock is divided by 1 to produce the CPU clock. 2 = The input clock is divided by 2 to produce the CPU clock. 3 = The input clock is divided by 3 to produce the CPU clock. ... 31 = The input clock is divided by 31 to produce the CPU clock." /> + <BitField start="5" size="3" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="8" size="1" name="CCLKSEL" description="Selects the input clock for the CPU clock divider."> + <Enum name="SYSCLK_IS_USED_AS_TH" start="0" description="Sysclk is used as the input to the CPU clock divider." /> + <Enum name="THE_OUTPUT_OF_THE_MA" start="1" description="The output of the Main PLL is used as the input to the CPU clock divider." /> + </BitField> + <BitField start="9" size="23" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x108" size="4" name="USBCLKSEL" access="Read/Write" description="USB Clock Selection register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="USBDIV" description="Selects the divide value for creating the USB clock from the selected PLL output. Only the values shown below can produce even number multiples of 48 MHz from the PLL. Warning: Improper setting of this value will result in incorrect operation of the USB interface. Only the main oscillator in conjunction with either PLL0 or PLL1 can provide a clock that meets USB accuracy and jitter specifications. Other values cannot produce the 48 MHz clock required for USB operation."> + <Enum name="THE_DIVIDER_IS_TURNE" start="0x0" description="The divider is turned off, no clock will be provided to the USB subsystem." /> + <Enum name="PLL0_OUTPUT_IS_DIVID" start="0x4" description="PLL0 output is divided by 4. PLL0 output must be 192 MHz." /> + <Enum name="PLL0_OUTPUT_IS_DIVID" start="0x6" description="PLL0 output is divided by 6. PLL0 output must be 288 MHz." /> + </BitField> + <BitField start="5" size="3" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="8" size="2" name="USBSEL" description="Selects the input clock for the USB clock divider."> + <Enum name="SYSCLK" start="0x0" description="Sysclk is used as the input to the USB clock divider. When this clock is selected, the USB can be accessed by software but cannot perform USB functions." /> + <Enum name="MAINPLLOUT" start="0x1" description="The output of the Main PLL is used as the input to the USB clock divider." /> + <Enum name="ALTPLLOOUT" start="0x2" description="The output of the Alt PLL is used as the input to the USB clock divider." /> + </BitField> + <BitField start="10" size="22" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x10C" size="4" name="CLKSRCSEL" access="Read/Write" description="Clock Source Select Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="CLKSRC" description="Selects the clock source for sysclk and PLL0 as follows:"> + <Enum name="SELECTS_THE_INTERNAL" start="0" description="Selects the Internal RC oscillator as the sysclk and PLL0 clock source (default)." /> + <Enum name="SELECTS_THE_MAIN_OSC" start="1" description="Selects the main oscillator as the sysclk and PLL0 clock source." /> + </BitField> + <BitField start="1" size="31" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x110" size="4" name="CANSLEEPCLR" access="Read/Write" description="Allows clearing the current CAN channel sleep state as well as reading that state." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="1" size="1" name="CAN1SLEEP" description="Sleep status and control for CAN channel 1. Read: when 1, indicates that CAN channel 1 is in the sleep mode. Write: writing a 1 causes clocks to be restored to CAN channel 1." /> + <BitField start="2" size="1" name="CAN2SLEEP" description="Sleep status and control for CAN channel 2. Read: when 1, indicates that CAN channel 2 is in the sleep mode. Write: writing a 1 causes clocks to be restored to CAN channel 2." /> + <BitField start="3" size="29" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x114" size="4" name="CANWAKEFLAGS" access="Read/Write" description="Allows reading the wake-up state of the CAN channels." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="1" size="1" name="CAN1WAKE" description="Wake-up status for CAN channel 1. Read: when 1, indicates that a falling edge has occurred on the receive data line of CAN channel 1. Write: writing a 1 clears this bit." /> + <BitField start="2" size="1" name="CAN2WAKE" description="Wake-up status for CAN channel 2. Read: when 1, indicates that a falling edge has occurred on the receive data line of CAN channel 2. Write: writing a 1 clears this bit." /> + <BitField start="3" size="29" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x140" size="4" name="EXTINT" access="Read/Write" description="External Interrupt Flag Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="EINT0" description="In level-sensitive mode, this bit is set if the EINT0 function is selected for its pin, and the pin is in its active state. In edge-sensitive mode, this bit is set if the EINT0 function is selected for its pin, and the selected edge occurs on the pin. This bit is cleared by writing a one to it, except in level sensitive mode when the pin is in its active state.[1]" /> + <BitField start="1" size="1" name="EINT1" description="In level-sensitive mode, this bit is set if the EINT1 function is selected for its pin, and the pin is in its active state. In edge-sensitive mode, this bit is set if the EINT1 function is selected for its pin, and the selected edge occurs on the pin. This bit is cleared by writing a one to it, except in level sensitive mode when the pin is in its active state.[1]" /> + <BitField start="2" size="1" name="EINT2" description="In level-sensitive mode, this bit is set if the EINT2 function is selected for its pin, and the pin is in its active state. In edge-sensitive mode, this bit is set if the EINT2 function is selected for its pin, and the selected edge occurs on the pin. This bit is cleared by writing a one to it, except in level sensitive mode when the pin is in its active state.[1]" /> + <BitField start="3" size="1" name="EINT3" description="In level-sensitive mode, this bit is set if the EINT3 function is selected for its pin, and the pin is in its active state. In edge-sensitive mode, this bit is set if the EINT3 function is selected for its pin, and the selected edge occurs on the pin. This bit is cleared by writing a one to it, except in level sensitive mode when the pin is in its active state.[1]" /> + <BitField start="4" size="28" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x148" size="4" name="EXTMODE" access="Read/Write" description="External Interrupt Mode register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="EXTMODE0" description="Level or edge sensitivity select for EINT0."> + <Enum name="LEVEL_SENSITIVE_" start="0" description="Level sensitive." /> + <Enum name="EDGE_SENSITIVE_" start="1" description="Edge sensitive." /> + </BitField> + <BitField start="1" size="1" name="EXTMODE1" description="Level or edge sensitivity select for EINT1."> + <Enum name="LEVEL_SENSITIVE_" start="0" description="Level sensitive." /> + <Enum name="EDGE_SENSITIVE_" start="1" description="Edge sensitive." /> + </BitField> + <BitField start="2" size="1" name="EXTMODE2" description="Level or edge sensitivity select for EINT2."> + <Enum name="LEVEL_SENSITIVE_" start="0" description="Level sensitive." /> + <Enum name="EDGE_SENSITIVE_" start="1" description="Edge sensitive." /> + </BitField> + <BitField start="3" size="1" name="EXTMODE3" description="Level or edge sensitivity select for EINT3."> + <Enum name="LEVEL_SENSITIVE_" start="0" description="Level sensitive." /> + <Enum name="EDGE_SENSITIVE_" start="1" description="Edge sensitive." /> + </BitField> + <BitField start="4" size="28" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x14C" size="4" name="EXTPOLAR" access="Read/Write" description="External Interrupt Polarity Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="EXTPOLAR0" description="External interrupt polarity for EINT0."> + <Enum name="LOW_ACTIVE_OR_FALLIN" start="0" description="Low-active or falling-edge sensitive (depending on EXTMODE0)." /> + <Enum name="HIGH_ACTIVE_OR_RISIN" start="1" description="High-active or rising-edge sensitive (depending on EXTMODE0)." /> + </BitField> + <BitField start="1" size="1" name="EXTPOLAR1" description="External interrupt polarity for EINT1."> + <Enum name="LOW_ACTIVE_OR_FALLIN" start="0" description="Low-active or falling-edge sensitive (depending on EXTMODE1)." /> + <Enum name="HIGH_ACTIVE_OR_RISIN" start="1" description="High-active or rising-edge sensitive (depending on EXTMODE1)." /> + </BitField> + <BitField start="2" size="1" name="EXTPOLAR2" description="External interrupt polarity for EINT2."> + <Enum name="LOW_ACTIVE_OR_FALLIN" start="0" description="Low-active or falling-edge sensitive (depending on EXTMODE2)." /> + <Enum name="HIGH_ACTIVE_OR_RISIN" start="1" description="High-active or rising-edge sensitive (depending on EXTMODE2)." /> + </BitField> + <BitField start="3" size="1" name="EXTPOLAR3" description="External interrupt polarity for EINT3."> + <Enum name="LOW_ACTIVE_OR_FALLIN" start="0" description="Low-active or falling-edge sensitive (depending on EXTMODE3)." /> + <Enum name="HIGH_ACTIVE_OR_RISIN" start="1" description="High-active or rising-edge sensitive (depending on EXTMODE3)." /> + </BitField> + <BitField start="4" size="28" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x180" size="4" name="RSID" access="Read/Write" description="Reset Source Identification Register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="POR" description="Assertion of the POR signal sets this bit, and clears all of the other bits in this register. But if another Reset signal (e.g., External Reset) remains asserted after the POR signal is negated, then its bit is set. This bit is not affected by any of the other sources of Reset." /> + <BitField start="1" size="1" name="EXTR" description="Assertion of the external RESET signal sets this bit. This bit is cleared only by software or POR." /> + <BitField start="2" size="1" name="WDTR" description="This bit is set when the Watchdog Timer times out and the WDTRESET bit in the Watchdog Mode Register is 1. This bit is cleared only by software or POR." /> + <BitField start="3" size="1" name="BODR" description="This bit is set when the VDD(REG)(3V3) voltage reaches a level below the BOD reset trip level (typically 1.85 V under nominal room temperature conditions). If the VDD(REG)(3V3) voltage dips from the normal operating range to below the BOD reset trip level and recovers, the BODR bit will be set to 1. If the VDD(REG)(3V3) voltage dips from the normal operating range to below the BOD reset trip level and continues to decline to the level at which POR is asserted (nominally 1 V), the BODR bit is cleared. If the VDD(REG)(3V3) voltage rises continuously from below 1 V to a level above the BOD reset trip level, the BODR will be set to 1. This bit is cleared only by software or POR. Note: Only in the case where a reset occurs and the POR = 0, the BODR bit indicates if the VDD(REG)(3V3) voltage was below the BOD reset trip level or not." /> + <BitField start="4" size="1" name="SYSRESET" description="This bit is set if the processor has been reset due to a system reset request. Setting the SYSRESETREQ bit in the Cortex-M4 AIRCR register causes a chip reset. This bit is cleared only by software or POR." /> + <BitField start="5" size="1" name="LOCKUP" description="This bit is set if the processor has been reset due to a "lockup". The lockup state causes a chip reset. This bit is cleared only by software or POR." /> + <BitField start="6" size="26" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x188" size="4" name="MATRIXARB" access="Read/Write" description="Matrix arbitration register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="2" name="PRI_ICODE" description="I-Code bus priority. Should be lower than PRI_DCODE for proper operation." /> + <BitField start="2" size="2" name="PRI_DCODE" description="D-Code bus priority." /> + <BitField start="4" size="2" name="PRI_SYS" description="System bus priority." /> + <BitField start="6" size="2" name="PRI_GPDMA" description="General Purpose DMA controller priority." /> + <BitField start="8" size="2" name="PRI_ETH" description="Ethernet DMA priority." /> + <BitField start="10" size="2" name="PRI_LCD" description="LCD DMA priority." /> + <BitField start="12" size="2" name="PRI_USB" description="USB DMA priority." /> + <BitField start="14" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="16" size="1" name="ROM_LAT" description="ROM latency select. Should always be 0." /> + <BitField start="17" size="15" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x1A0" size="4" name="SCS" access="Read/Write" description="System Control and Status" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="EMCSC" description="EMC Shift Control. Controls how addresses are output on the EMC address pins for static memories. Also see Section 9.9 in the EMC chapter."> + <Enum name="STATIC_MEMORY_ADDRES" start="0" description="Static memory addresses are shifted to match the data bus width. For example, when accessing a 32-bit wide data bus, the address is shifted right 2 places such that bit 2 is the LSB. In this mode, address bit 0 for the this device is connected to address bit 0 of the memory device, thus simplifying memory connections. This also makes a larger memory address range possible, because additional upper address bits can appear on the higher address pins due to the shift." /> + <Enum name="STATIC_MEMORY_ADDRES" start="1" description="Static memory addresses are always output as byte addresses regardless of the data bus width. For example, when word data is accessed on a 32-bit bus, address bits 1 and 0 will always be 0. In this mode, one or both lower address bits may not be connected to memories that are part of a bus that is wider than 8 bits. This mode matches the operation of LPC23xx and LPC24xx devices." /> + </BitField> + <BitField start="1" size="1" name="EMCRD" description="EMC Reset Disable[1]. External Memory Controller Reset Disable. Also see Section 9.8 in the EMC chapter."> + <Enum name="BOTH_EMC_RESETS_ARE_" start="0" description="Both EMC resets are asserted when any type of chip reset event occurs. In this mode, all registers and functions of the EMC are initialized upon any reset condition." /> + <Enum name="MANY_PORTIONS_OF_THE" start="1" description="Many portions of the EMC are only reset by a power-on or brown-out event, in order to allow the EMC to retain its state through a warm reset (external reset or watchdog reset). If the EMC is configured correctly, auto-refresh can be maintained through a warm reset." /> + </BitField> + <BitField start="2" size="1" name="EMCBC" description="External Memory Controller burst control. Also see Section 9.10 in the EMC chapter."> + <Enum name="BURST_ENABLED_" start="0" description="Burst enabled." /> + <Enum name="BURST_DISABLED_THIS" start="1" description="Burst disabled. This mode can be used to prevent multiple sequential accesses to memory mapped I/O devices connected to EMC static memory chip selects. These unrequested accesses can cause issues with some I/O devices." /> + </BitField> + <BitField start="3" size="1" name="MCIPWRAL" description="MCIPWR Active Level[1]. Selects the active level of the SD card interface signal SD_PWR."> + <Enum name="SD_PWR_IS_ACTIVE_LOW" start="0" description="SD_PWR is active low (inverted output of the SD Card interface block)." /> + <Enum name="SD_PWR_IS_ACTIVE_HIG" start="1" description="SD_PWR is active high (follows the output of the SD Card interface block)." /> + </BitField> + <BitField start="4" size="1" name="OSCRS" description="Main oscillator range select."> + <Enum name="THE_FREQUENCY_RANGE_" start="0" description="The frequency range of the main oscillator is 1 MHz to 20 MHz." /> + <Enum name="THE_FREQUENCY_RANGE_" start="1" description="The frequency range of the main oscillator is 15 MHz to 25 MHz." /> + </BitField> + <BitField start="5" size="1" name="OSCEN" description="Main oscillator enable."> + <Enum name="THE_MAIN_OSCILLATOR_" start="0" description="The main oscillator is disabled." /> + <Enum name="THE_MAIN_OSCILLATOR_" start="1" description="The main oscillator is enabled, and will start up if the correct external circuitry is connected to the XTAL1 and XTAL2 pins." /> + </BitField> + <BitField start="6" size="1" name="OSCSTAT" description="Main oscillator status."> + <Enum name="THE_MAIN_OSCILLATOR_" start="0" description="The main oscillator is not ready to be used as a clock source." /> + <Enum name="THE_MAIN_OSCILLATOR_" start="1" description="The main oscillator is ready to be used as a clock source. The main oscillator must be enabled via the OSCEN bit." /> + </BitField> + <BitField start="7" size="25" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x1A8" size="4" name="PCLKSEL" access="Read/Write" description="Peripheral Clock Selection register" reset_value="0x10" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="PCLKDIV" description="Selects the divide value for the clock used for all APB peripherals. 0 = The divider is turned off., no clock will be provided to APB peripherals. 1 = The input clock is divided by 1 to produce the APB peripheral clock. 2 = The input clock is divided by 2 to produce the APB peripheral clock. 3 = The input clock is divided by 3 to produce the APB peripheral clock. ... 31 = The input clock is divided by 31 to produce the APB peripheral clock." /> + <BitField start="5" size="27" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x1B0" size="4" name="PBOOST" access="Read/Write" description="Power boost register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="2" name="Boost" description="Boost control bits. 00 : Boost is off, operation must be below 100 MHz. 11 : Boost is on, operation up to 120 MHz is supported. Other values are not allowed." /> + <BitField start="2" size="30" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x1B4" size="4" name="SPIFICLKSEL" access="Read/Write" description="SPIFI Clock Selection register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="SPIFIDIV" description="Selects the divide value for creating the SPIFI clock from the selected clock source. 0 = The divider is turned off., no clock will be provided to the SPIFI. 1 = The input clock is divided by 1 to produce the SPIFI clock. 2 = The input clock is divided by 2 to produce the SPIFI clock. 3 = The input clock is divided by 3 to produce the SPIFI clock. ... 31 = The input clock is divided by 31 to produce the SPIFI clock." /> + <BitField start="5" size="3" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="8" size="2" name="SPIFISEL" description="Selects the input clock for the USB clock divider."> + <Enum name="SYSCLK" start="0x0" description="Sysclk is used as the input to the SPIFI clock divider." /> + <Enum name="MAINPLLOUT" start="0x1" description="The output of the Main PLL is used as the input to the SPIFI clock divider." /> + <Enum name="ALTPLLOUT" start="0x2" description="The output of the Alt PLL is used as the input to the SPIFI clock divider." /> + </BitField> + <BitField start="10" size="22" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x1B8" size="4" name="LCD_CFG" access="Read/Write" description="LCD Clock configuration register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="CLKDIV" description="LCD panel clock prescaler selection. The value in the this register plus 1 is used to divide the selected input clock (see the CLKSEL bit in the LCD_POL register), to produce the panel clock." /> + <BitField start="5" size="27" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x1C0" size="4" name="USBINTST" access="Read/Write" description="USB Interrupt Status" reset_value="0x80000000" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="USB_INT_REQ_LP" description="Low priority interrupt line status. This bit is read-only." /> + <BitField start="1" size="1" name="USB_INT_REQ_HP" description="High priority interrupt line status. This bit is read-only." /> + <BitField start="2" size="1" name="USB_INT_REQ_DMA" description="DMA interrupt line status. This bit is read-only." /> + <BitField start="3" size="1" name="USB_HOST_INT" description="USB host interrupt line status. This bit is read-only." /> + <BitField start="4" size="1" name="USB_ATX_INT" description="External ATX interrupt line status. This bit is read-only." /> + <BitField start="5" size="1" name="USB_OTG_INT" description="OTG interrupt line status. This bit is read-only." /> + <BitField start="6" size="1" name="USB_I2C_INT" description="I2C module interrupt line status. This bit is read-only." /> + <BitField start="7" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="8" size="1" name="USB_NEED_CLK" description="USB need clock indicator. This bit is read-only. This bit is set to 1 when USB activity or a change of state on the USB data pins is detected, and it indicates that a PLL supplied clock of 48 MHz is needed. Once USB_NEED_CLK becomes one, it resets to zero 5 ms after the last packet has been received/sent, or 2 ms after the Suspend Change (SUS_CH) interrupt has occurred. A change of this bit from 0 to 1 can wake up the microcontroller if activity on the USB bus is selected to wake up the part from the Power-down mode (see Section 3.12.8 "Wake-up from Reduced Power Modes" for details). Also see Section 3.10.3 "PLLs and Power-down mode" and Section 3.3.7 "Power Control for Peripherals registers" for considerations about the PLL and invoking the Power-down mode. This bit is read-only." /> + <BitField start="9" size="22" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="31" size="1" name="EN_USB_INTS" description="Enable all USB interrupts. When this bit is cleared, the NVIC does not see the ORed output of the USB interrupt lines." /> + </Register> + <Register start="+0x1C4" size="4" name="DMACREQSEL" access="Read/Write" description="Selects between alternative requests on DMA channels 0 through 7 and 10 through 15" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="DMASEL00" description="Selects the DMA request for GPDMA input 0: 0 - (unused) 1 - Timer 0 match 0 is selected." /> + <BitField start="1" size="1" name="DMASEL01" description="Selects the DMA request for GPDMA input 1: 0 - SD card interface is selected. 1 - Timer 0 match 1 is selected." /> + <BitField start="2" size="1" name="DMASEL02" description="Selects the DMA request for GPDMA input 2: 0 - SSP0 transmit is selected. 1 - Timer 1 match 0 is selected." /> + <BitField start="3" size="1" name="DMASEL03" description="Selects the DMA request for GPDMA input 3: 0 - SSP0 receive is selected. 1 - Timer 1 match 1 is selected." /> + <BitField start="4" size="1" name="DMASEL04" description="Selects the DMA request for GPDMA input 4: 0 - SSP1 transmit is selected. 1 - Timer 2 match 0 is selected." /> + <BitField start="5" size="1" name="DMASEL05" description="Selects the DMA request for GPDMA input 5: 0 - SSP1 receive is selected. 1 - Timer 2 match 1 is selected." /> + <BitField start="6" size="1" name="DMASEL06" description="Selects the DMA request for GPDMA input 6: 0 - SSP2 transmit is selected. 1 - I2S channel 0 is selected." /> + <BitField start="7" size="1" name="DMASEL07" description="Selects the DMA request for GPDMA input 7: 0 - SSP2 receive is selected. 1 - I2S channel 1 is selected." /> + <BitField start="8" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="10" size="1" name="DMASEL10" description="Selects the DMA request for GPDMA input 10: 0 - UART0 transmit is selected. 1 - UART3 transmit is selected." /> + <BitField start="11" size="1" name="DMASEL11" description="Selects the DMA request for GPDMA input 11: 0 - UART0 receive is selected. 1 - UART3 receive is selected." /> + <BitField start="12" size="1" name="DMASEL12" description="Selects the DMA request for GPDMA input 12: 0 - UART1 transmit is selected. 1 - UART4 transmit is selected." /> + <BitField start="13" size="1" name="DMASEL13" description="Selects the DMA request for GPDMA input 13: 0 - UART1 receive is selected. 1 - UART4 receive is selected." /> + <BitField start="14" size="1" name="DMASEL14" description="Selects the DMA request for GPDMA input 14: 0 - UART2 transmit is selected. 1 - Timer 3 match 0 is selected." /> + <BitField start="15" size="1" name="DMASEL15" description="Selects the DMA request for GPDMA input 15: 0 - UART2 receive is selected. 1 - Timer 3 match 1 is selected." /> + <BitField start="16" size="16" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x1C8" size="4" name="CLKOUTCFG" access="Read/Write" description="Clock Output Configuration register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="4" name="CLKOUTSEL" description="Selects the clock source for the CLKOUT function. 0x0 = Selects the CPU clock as the CLKOUT source. 0x1 = Selects the main oscillator as the CLKOUT source. 0x2 = Selects the Internal RC oscillator as the CLKOUT source. 0x3 = Selects the USB clock as the CLKOUT source. 0x4 = Selects the RTC oscillator as the CLKOUT source. 0x5 = Selects the SPIFI clock as the CLKOUT source. 0x6 = Selects the Watchdog oscillator as the CLKOUT source. Other settings are reserved. Do not use." /> + <BitField start="4" size="4" name="CLKOUTDIV" description="Integer value to divide the output clock by, minus one. 0x0 = Clock is divided by 1. 0x1 = Clock is divided by 2. 0x2 = Clock is divided by 3. ... 0xF = Clock is divided by 16." /> + <BitField start="8" size="1" name="CLKOUT_EN" description="CLKOUT enable control, allows switching the CLKOUT source without glitches. Clear to stop CLKOUT on the next falling edge. Set to enable CLKOUT." /> + <BitField start="9" size="1" name="CLKOUT_ACT" description="CLKOUT activity indication. Reads as 1 when CLKOUT is enabled. Read as 0 when CLKOUT has been disabled via the CLKOUT_EN bit and the clock has completed being stopped." /> + <BitField start="10" size="22" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x1CC" size="4" name="RSTCON0" access="Read/Write" description="Individual peripheral reset control bits" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RSTLCD" description="LCD controller reset control bit." /> + <BitField start="1" size="1" name="RSTTIM0" description="Timer/Counter 0 reset control bit." /> + <BitField start="2" size="1" name="RSTTIM1" description="Timer/Counter 1 reset control bit." /> + <BitField start="3" size="1" name="RSTUART0" description="UART0 reset control bit." /> + <BitField start="4" size="1" name="RSTUART1" description="UART1 reset control bit." /> + <BitField start="5" size="1" name="RSTPWM0" description="PWM0 reset control bit." /> + <BitField start="6" size="1" name="RSTPWM1" description="PWM1 reset control bit." /> + <BitField start="7" size="1" name="RSTI2C0" description="The I2C0 interface reset control bit." /> + <BitField start="8" size="1" name="RSTUART4" description="UART4 reset control bit." /> + <BitField start="9" size="1" name="RSTRTC" description="RTC and Event Monitor/Recorder reset control bit. RTC reset is limited, see Table 626 "Register overview: Real-Time Clock (base address 0x4002 4000)" for details." /> + <BitField start="10" size="1" name="RSTSSP1" description="The SSP 1 interface reset control bit." /> + <BitField start="11" size="1" name="RSTEMC" description="External Memory Controller reset control bit." /> + <BitField start="12" size="1" name="RSTADC" description="A/D converter (ADC) reset control bit." /> + <BitField start="13" size="1" name="RSTCAN1" description="CAN Controller 1 reset control bit. Note: The CAN acceptance filter may be reset by a separate bit in the RSTCON1 register." /> + <BitField start="14" size="1" name="RSTCAN2" description="CAN Controller 2 reset control bit. Note: The CAN acceptance filter may be reset by a separate bit in the RSTCON1 register." /> + <BitField start="15" size="1" name="RSTGPIO" description="Reset control bit for GPIO, and GPIO interrupts. Note: IOCON may be reset by a separate bit in the RSTCON1 register." /> + <BitField start="16" size="1" name="RSTSPIFI" description="SPI Flash Interface reset control bit." /> + <BitField start="17" size="1" name="RSTMCPWM" description="Motor Control PWM reset control bit." /> + <BitField start="18" size="1" name="RSTQEI" description="Quadrature Encoder Interface reset control bit." /> + <BitField start="19" size="1" name="RSTI2C1" description="The I2C1 interface reset control bit." /> + <BitField start="20" size="1" name="RSTSSP2" description="The SSP2 interface reset control bit." /> + <BitField start="21" size="1" name="RSTSSP0" description="The SSP0 interface reset control bit." /> + <BitField start="22" size="1" name="RSTTIM2" description="Timer 2 reset control bit." /> + <BitField start="23" size="1" name="RSTTIM3" description="Timer 3 reset control bit." /> + <BitField start="24" size="1" name="RSTUART2" description="UART 2 reset control bit." /> + <BitField start="25" size="1" name="RSTUART3" description="UART 3 reset control bit." /> + <BitField start="26" size="1" name="RSTI2C2" description="I2C interface 2 reset control bit." /> + <BitField start="27" size="1" name="RSTI2S" description="I2S interface reset control bit." /> + <BitField start="28" size="1" name="RSTSDC" description="SD Card interface reset control bit." /> + <BitField start="29" size="1" name="RSTGPDMA" description="GPDMA function reset control bit." /> + <BitField start="30" size="1" name="RSTENET" description="Ethernet block reset control bit." /> + <BitField start="31" size="1" name="RSTUSB" description="USB interface reset control bit." /> + </Register> + <Register start="+0x1D0" size="4" name="RSTCON1" access="Read/Write" description="Individual peripheral reset control bits" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RSTIOCON" description="Reset control bit for the IOCON registers." /> + <BitField start="1" size="1" name="RSTDAC" description="D/A converter (DAC) reset control bit." /> + <BitField start="2" size="1" name="RSTCANACC" description="CAN acceptance filter reset control bit." /> + <BitField start="3" size="1" name="RSTCMP" description="Comparator 0/1 reset control bit." /> + <BitField start="4" size="28" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x1DC" size="4" name="EMCDLYCTL" access="Read/Write" description="Values for the 4 programmable delays associated with SDRAM operation." reset_value="0x210" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="CMDDLY" description="Programmable delay value for EMC outputs in command delayed mode. See Section 9.12.6. The delay amount is roughly (CMDDLY+1) * 250 picoseconds. This field applies only when the command delayed read strategy is selected in the EMCDynamicReadConfig register. In this mode, all control outputs from the EMC are delayed, but the output clock is not. Delaying the control outputs changes dynamic characteristics defined in the device data sheet." /> + <BitField start="5" size="3" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="8" size="5" name="FBCLKDLY" description="Programmable delay value for the feedback clock that controls input data sampling. See Section 9.5.3. The delay amount is roughly (FBCLKDLY+1) * 250 picoseconds." /> + <BitField start="13" size="3" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="16" size="5" name="CLKOUT0DLY" description="Programmable delay value for the CLKOUT0 output. This would typically be used in clock delayed mode. See Section 9.12.6 The delay amount is roughly (CLKOUT0DLY+1) * 250 picoseconds. Delaying the clock output changes dynamic characteristics defined in the device data sheet." /> + <BitField start="21" size="3" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="24" size="5" name="CLKOUT1DLY" description="Programmable delay value for the CLKOUT1 output. This would typically be used in clock delayed mode. See Section 9.12.6 The delay amount is roughly (CLKOUT1DLY+1) * 250 picoseconds." /> + <BitField start="29" size="3" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x1E0" size="4" name="EMCCAL" access="Read/Write" description="Controls the calibration counter for programmable delays and returns the result value." reset_value="0x1F00" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="CALVALUE" description="Returns the count of the approximately 50 MHz ring oscillator that occur during 32 clocks of the IRC oscillator. This represents the composite effect of processing variation, internal regulator supply voltage, and ambient temperature." /> + <BitField start="8" size="6" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="14" size="1" name="START" description="Start control bit for the EMC calibration counter. Writing a 1 to this bit begins the measurement process. This bit is cleared automatically when the measurement is complete." /> + <BitField start="15" size="1" name="DONE" description="Measurement completion flag. this bit is set when a calibration measurement is completed. This bit is cleared automatically when the START bit is set." /> + <BitField start="16" size="16" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + </RegisterGroup> + <RegisterGroup name="NVIC" start="0xE000E100" description="Nested Vectored Interrupt Controller"> + <Register name="NVIC_ISER0" description="Interrupt Set-Enable Register 0" start="0xE000E100"> + <BitField name="WWDT" start="0" size="1" /> + <BitField name="TIMER0" start="1" size="1" /> + <BitField name="TIMER1" start="2" size="1" /> + <BitField name="TIMER2" start="3" size="1" /> + <BitField name="TIMER3" start="4" size="1" /> + <BitField name="UART0" start="5" size="1" /> + <BitField name="UART1" start="6" size="1" /> + <BitField name="UART2" start="7" size="1" /> + <BitField name="UART3" start="8" size="1" /> + <BitField name="PWM1" start="9" size="1" /> + <BitField name="I2C0" start="10" size="1" /> + <BitField name="I2C1" start="11" size="1" /> + <BitField name="I2C2" start="12" size="1" /> + <BitField name="SSP0" start="14" size="1" /> + <BitField name="SSP1" start="15" size="1" /> + <BitField name="RTC" start="17" size="1" /> + <BitField name="EINT0" start="18" size="1" /> + <BitField name="EINT1" start="19" size="1" /> + <BitField name="EINT2" start="20" size="1" /> + <BitField name="EINT3" start="21" size="1" /> + <BitField name="ADC" start="22" size="1" /> + <BitField name="BOD" start="23" size="1" /> + <BitField name="USB" start="24" size="1" /> + <BitField name="CAN" start="25" size="1" /> + <BitField name="GPDMA" start="26" size="1" /> + <BitField name="I2S" start="27" size="1" /> + <BitField name="ETHERNET" start="28" size="1" /> + <BitField name="SDMMC" start="29" size="1" /> + <BitField name="MCPWM" start="30" size="1" /> + <BitField name="QEI" start="31" size="1" /> + </Register> + <Register name="NVIC_ISER1" description="Interrupt Set-Enable Register 1" start="0xE000E104"> + <BitField name="USB_NEED_CLK" start="1" size="1" /> + <BitField name="UART4" start="3" size="1" /> + <BitField name="SSP2" start="4" size="1" /> + <BitField name="LCD" start="5" size="1" /> + <BitField name="GPIOINT" start="6" size="1" /> + <BitField name="PWM0" start="7" size="1" /> + <BitField name="EEPROM" start="8" size="1" /> + <BitField name="CMP0" start="9" size="1" /> + <BitField name="CMP1" start="10" size="1" /> + </Register> + <Register name="NVIC_ICER0" description="Interrupt Clear-Enable Register 0" start="0xE000E180"> + <BitField name="WWDT" start="0" size="1" /> + <BitField name="TIMER0" start="1" size="1" /> + <BitField name="TIMER1" start="2" size="1" /> + <BitField name="TIMER2" start="3" size="1" /> + <BitField name="TIMER3" start="4" size="1" /> + <BitField name="UART0" start="5" size="1" /> + <BitField name="UART1" start="6" size="1" /> + <BitField name="UART2" start="7" size="1" /> + <BitField name="UART3" start="8" size="1" /> + <BitField name="PWM1" start="9" size="1" /> + <BitField name="I2C0" start="10" size="1" /> + <BitField name="I2C1" start="11" size="1" /> + <BitField name="I2C2" start="12" size="1" /> + <BitField name="SSP0" start="14" size="1" /> + <BitField name="SSP1" start="15" size="1" /> + <BitField name="RTC" start="17" size="1" /> + <BitField name="EINT0" start="18" size="1" /> + <BitField name="EINT1" start="19" size="1" /> + <BitField name="EINT2" start="20" size="1" /> + <BitField name="EINT3" start="21" size="1" /> + <BitField name="ADC" start="22" size="1" /> + <BitField name="BOD" start="23" size="1" /> + <BitField name="USB" start="24" size="1" /> + <BitField name="CAN" start="25" size="1" /> + <BitField name="GPDMA" start="26" size="1" /> + <BitField name="I2S" start="27" size="1" /> + <BitField name="ETHERNET" start="28" size="1" /> + <BitField name="SDMMC" start="29" size="1" /> + <BitField name="MCPWM" start="30" size="1" /> + <BitField name="QEI" start="31" size="1" /> + </Register> + <Register name="NVIC_ICER1" description="Interrupt Clear-Enable Register 1" start="0xE000E184"> + <BitField name="USB_NEED_CLK" start="1" size="1" /> + <BitField name="UART4" start="3" size="1" /> + <BitField name="SSP2" start="4" size="1" /> + <BitField name="LCD" start="5" size="1" /> + <BitField name="GPIOINT" start="6" size="1" /> + <BitField name="PWM0" start="7" size="1" /> + <BitField name="EEPROM" start="8" size="1" /> + <BitField name="CMP0" start="9" size="1" /> + <BitField name="CMP1" start="10" size="1" /> + </Register> + <Register name="NVIC_ISPR0" description="Interrupt Set-Pending Register 0" start="0xE000E200"> + <BitField name="WWDT" start="0" size="1" /> + <BitField name="TIMER0" start="1" size="1" /> + <BitField name="TIMER1" start="2" size="1" /> + <BitField name="TIMER2" start="3" size="1" /> + <BitField name="TIMER3" start="4" size="1" /> + <BitField name="UART0" start="5" size="1" /> + <BitField name="UART1" start="6" size="1" /> + <BitField name="UART2" start="7" size="1" /> + <BitField name="UART3" start="8" size="1" /> + <BitField name="PWM1" start="9" size="1" /> + <BitField name="I2C0" start="10" size="1" /> + <BitField name="I2C1" start="11" size="1" /> + <BitField name="I2C2" start="12" size="1" /> + <BitField name="SSP0" start="14" size="1" /> + <BitField name="SSP1" start="15" size="1" /> + <BitField name="RTC" start="17" size="1" /> + <BitField name="EINT0" start="18" size="1" /> + <BitField name="EINT1" start="19" size="1" /> + <BitField name="EINT2" start="20" size="1" /> + <BitField name="EINT3" start="21" size="1" /> + <BitField name="ADC" start="22" size="1" /> + <BitField name="BOD" start="23" size="1" /> + <BitField name="USB" start="24" size="1" /> + <BitField name="CAN" start="25" size="1" /> + <BitField name="GPDMA" start="26" size="1" /> + <BitField name="I2S" start="27" size="1" /> + <BitField name="ETHERNET" start="28" size="1" /> + <BitField name="SDMMC" start="29" size="1" /> + <BitField name="MCPWM" start="30" size="1" /> + <BitField name="QEI" start="31" size="1" /> + </Register> + <Register name="NVIC_ISPR1" description="Interrupt Set-Pending Register 1" start="0xE000E204"> + <BitField name="USB_NEED_CLK" start="1" size="1" /> + <BitField name="UART4" start="3" size="1" /> + <BitField name="SSP2" start="4" size="1" /> + <BitField name="LCD" start="5" size="1" /> + <BitField name="GPIOINT" start="6" size="1" /> + <BitField name="PWM0" start="7" size="1" /> + <BitField name="EEPROM" start="8" size="1" /> + <BitField name="CMP0" start="9" size="1" /> + <BitField name="CMP1" start="10" size="1" /> + </Register> + <Register name="NVIC_ICPR0" description="Interrupt Clear-Pending Register 0" start="0xE000E280"> + <BitField name="WWDT" start="0" size="1" /> + <BitField name="TIMER0" start="1" size="1" /> + <BitField name="TIMER1" start="2" size="1" /> + <BitField name="TIMER2" start="3" size="1" /> + <BitField name="TIMER3" start="4" size="1" /> + <BitField name="UART0" start="5" size="1" /> + <BitField name="UART1" start="6" size="1" /> + <BitField name="UART2" start="7" size="1" /> + <BitField name="UART3" start="8" size="1" /> + <BitField name="PWM1" start="9" size="1" /> + <BitField name="I2C0" start="10" size="1" /> + <BitField name="I2C1" start="11" size="1" /> + <BitField name="I2C2" start="12" size="1" /> + <BitField name="SSP0" start="14" size="1" /> + <BitField name="SSP1" start="15" size="1" /> + <BitField name="RTC" start="17" size="1" /> + <BitField name="EINT0" start="18" size="1" /> + <BitField name="EINT1" start="19" size="1" /> + <BitField name="EINT2" start="20" size="1" /> + <BitField name="EINT3" start="21" size="1" /> + <BitField name="ADC" start="22" size="1" /> + <BitField name="BOD" start="23" size="1" /> + <BitField name="USB" start="24" size="1" /> + <BitField name="CAN" start="25" size="1" /> + <BitField name="GPDMA" start="26" size="1" /> + <BitField name="I2S" start="27" size="1" /> + <BitField name="ETHERNET" start="28" size="1" /> + <BitField name="SDMMC" start="29" size="1" /> + <BitField name="MCPWM" start="30" size="1" /> + <BitField name="QEI" start="31" size="1" /> + </Register> + <Register name="NVIC_ICPR1" description="Interrupt Clear-Pending Register 1" start="0xE000E284"> + <BitField name="USB_NEED_CLK" start="1" size="1" /> + <BitField name="UART4" start="3" size="1" /> + <BitField name="SSP2" start="4" size="1" /> + <BitField name="LCD" start="5" size="1" /> + <BitField name="GPIOINT" start="6" size="1" /> + <BitField name="PWM0" start="7" size="1" /> + <BitField name="EEPROM" start="8" size="1" /> + <BitField name="CMP0" start="9" size="1" /> + <BitField name="CMP1" start="10" size="1" /> + </Register> + <Register name="NVIC_IABR0" description="Interrupt Active Bit Register 0" start="0xE000E300" access="ReadOnly"> + <BitField name="WWDT" start="0" size="1" /> + <BitField name="TIMER0" start="1" size="1" /> + <BitField name="TIMER1" start="2" size="1" /> + <BitField name="TIMER2" start="3" size="1" /> + <BitField name="TIMER3" start="4" size="1" /> + <BitField name="UART0" start="5" size="1" /> + <BitField name="UART1" start="6" size="1" /> + <BitField name="UART2" start="7" size="1" /> + <BitField name="UART3" start="8" size="1" /> + <BitField name="PWM1" start="9" size="1" /> + <BitField name="I2C0" start="10" size="1" /> + <BitField name="I2C1" start="11" size="1" /> + <BitField name="I2C2" start="12" size="1" /> + <BitField name="SSP0" start="14" size="1" /> + <BitField name="SSP1" start="15" size="1" /> + <BitField name="RTC" start="17" size="1" /> + <BitField name="EINT0" start="18" size="1" /> + <BitField name="EINT1" start="19" size="1" /> + <BitField name="EINT2" start="20" size="1" /> + <BitField name="EINT3" start="21" size="1" /> + <BitField name="ADC" start="22" size="1" /> + <BitField name="BOD" start="23" size="1" /> + <BitField name="USB" start="24" size="1" /> + <BitField name="CAN" start="25" size="1" /> + <BitField name="GPDMA" start="26" size="1" /> + <BitField name="I2S" start="27" size="1" /> + <BitField name="ETHERNET" start="28" size="1" /> + <BitField name="SDMMC" start="29" size="1" /> + <BitField name="MCPWM" start="30" size="1" /> + <BitField name="QEI" start="31" size="1" /> + </Register> + <Register name="NVIC_IABR1" description="Interrupt Active Bit Register 1" start="0xE000E304" access="ReadOnly"> + <BitField name="USB_NEED_CLK" start="1" size="1" /> + <BitField name="UART4" start="3" size="1" /> + <BitField name="SSP2" start="4" size="1" /> + <BitField name="LCD" start="5" size="1" /> + <BitField name="GPIOINT" start="6" size="1" /> + <BitField name="PWM0" start="7" size="1" /> + <BitField name="EEPROM" start="8" size="1" /> + <BitField name="CMP0" start="9" size="1" /> + <BitField name="CMP1" start="10" size="1" /> + </Register> + <Register name="NVIC_IPR0" description="Interrupt Priority Register 0" start="0xE000E400"> + <BitField name="WWDT" start="4" size="4" /> + <BitField name="TIMER0" start="12" size="4" /> + <BitField name="TIMER1" start="20" size="4" /> + <BitField name="TIMER2" start="28" size="4" /> + </Register> + <Register name="NVIC_IPR1" description="Interrupt Priority Register 1" start="0xE000E404"> + <BitField name="TIMER3" start="4" size="4" /> + <BitField name="UART0" start="12" size="4" /> + <BitField name="UART1" start="20" size="4" /> + <BitField name="UART2" start="28" size="4" /> + </Register> + <Register name="NVIC_IPR2" description="Interrupt Priority Register 2" start="0xE000E408"> + <BitField name="UART3" start="4" size="4" /> + <BitField name="PWM1" start="12" size="4" /> + <BitField name="I2C0" start="20" size="4" /> + <BitField name="I2C1" start="28" size="4" /> + </Register> + <Register name="NVIC_IPR3" description="Interrupt Priority Register 3" start="0xE000E40C"> + <BitField name="I2C2" start="4" size="4" /> + <BitField name="SSP0" start="20" size="4" /> + <BitField name="SSP1" start="28" size="4" /> + </Register> + <Register name="NVIC_IPR4" description="Interrupt Priority Register 4" start="0xE000E410"> + <BitField name="RTC" start="12" size="4" /> + <BitField name="EINT0" start="20" size="4" /> + <BitField name="EINT1" start="28" size="4" /> + </Register> + <Register name="NVIC_IPR5" description="Interrupt Priority Register 5" start="0xE000E414"> + <BitField name="EINT2" start="4" size="4" /> + <BitField name="EINT3" start="12" size="4" /> + <BitField name="ADC" start="20" size="4" /> + <BitField name="BOD" start="28" size="4" /> + </Register> + <Register name="NVIC_IPR6" description="Interrupt Priority Register 6" start="0xE000E418"> + <BitField name="USB" start="4" size="4" /> + <BitField name="CAN" start="12" size="4" /> + <BitField name="GPDMA" start="20" size="4" /> + <BitField name="I2S" start="28" size="4" /> + </Register> + <Register name="NVIC_IPR7" description="Interrupt Priority Register 7" start="0xE000E41C"> + <BitField name="ETHERNET" start="4" size="4" /> + <BitField name="SDMMC" start="12" size="4" /> + <BitField name="MCPWM" start="20" size="4" /> + <BitField name="QEI" start="28" size="4" /> + </Register> + <Register name="NVIC_IPR8" description="Interrupt Priority Register 8" start="0xE000E420"> + <BitField name="USB_NEED_CLK" start="12" size="4" /> + <BitField name="UART4" start="28" size="4" /> + </Register> + <Register name="NVIC_IPR9" description="Interrupt Priority Register 9" start="0xE000E424"> + <BitField name="SSP2" start="4" size="4" /> + <BitField name="LCD" start="12" size="4" /> + <BitField name="GPIOINT" start="20" size="4" /> + <BitField name="PWM0" start="28" size="4" /> + </Register> + <Register name="NVIC_IPR10" description="Interrupt Priority Register 10" start="0xE000E428"> + <BitField name="EEPROM" start="4" size="4" /> + <BitField name="CMP0" start="12" size="4" /> + <BitField name="CMP1" start="20" size="4" /> + </Register> + </RegisterGroup> + <RegisterGroup name="SysTick" start="0xE000E010" description="24-bit System Timer"> + <Register name="SYST_CSR" start="0xE000E010" description="SysTick Control and Status Register"> + <BitField name="COUNTFLAG" start="16" size="1" description="Counter Flag" /> + <BitField name="CLKSOURCE" start="2" size="1" description="Timer Clock Source" /> + <BitField name="TICKINT" start="1" size="1" description="Tick Interrupt Enable" /> + <BitField name="ENABLE" start="0" size="1" description="Enable SysTick Timer" /> + </Register> + <Register name="SYST_RVR" start="0xE000E014" description="SysTick Reload Value Register"> + <BitField name="RELOAD" start="0" size="24" description="Value to load into the SYST_CVR when the counter is enabled and when it reaches 0" /> + </Register> + <Register name="SYST_CVR" start="0xE000E018" description="SysTick Current Value Register Register"> + <BitField name="CURRENT" start="0" size="24" description="The current value of the SysTick counter" /> + </Register> + <Register name="SYST_CALIB" start="0xE000E01C" access="ReadOnly" description="SysTick Calibration Value Register"> + <BitField name="NOREF" start="31" size="1" description="Indicates whether the device provides a reference clock to the processor" /> + <BitField name="SKEW" start="30" size="1" description="Indicates whether the TENMS value is exact" /> + <BitField name="TENMS" start="0" size="24" description="Reload value for 10ms (100Hz) timing, subject to system clock skew errors" /> + </Register> + </RegisterGroup> + <RegisterGroup name="SCB" start="" description="System Control Block"> + <Register name="ACTLR" start="0xE000E008" description="Auxiliary Control Register"> + <BitField name="DISOOFP" start="9" size="1" description="Disables floating pointinstructions completing outof order with respect to integer instructions" /> + <BitField name="DISFPCA" start="8" size="1" description="When set to 1, disables IT folding" /> + <BitField name="DISFOLD" start="2" size="1" description="When set to 1, disables write buffer use during default memory map accesses" /> + <BitField name="DISDEFWBUF" start="1" size="1" description="When set to 1, disables write buffer use during default memory map accesses" /> + <BitField name="DISMCYCINT" start="0" size="1" description="When set to 1, disables interruption of load multiple and store multiple instructions" /> + </Register> + <Register name="CPUID" start="0xE000ED00" access="ReadOnly" description="CPUID Register"> + <BitField name="IMPLEMENTER" start="24" size="8" description="Implementer Code" /> + <BitField name="VARIANT" start="20" size="4" description="Variant Number" /> + <BitField name="PARTNO" start="4" size="12" description="Part Number" /> + <BitField name="REVISION" start="0" size="4" description="Revision Number" /> + </Register> + <Register name="ICSR" start="0xE000ED04" description="Interrupt Control and State Register"> + <BitField name="NMIPENDSET" start="31" size="1" description="NMI set-pending bit" /> + <BitField name="PENDSVSET" start="28" size="1" description="PendSV set-pending bit" /> + <BitField name="PENDSVCLR" start="27" size="1" description="PendSV clear-pending bit" /> + <BitField name="PENDSTSET" start="26" size="1" description="SysTick exception set-pending bit" /> + <BitField name="PENDSTCLR" start="25" size="1" description="SysTick exception clear-pending bit" /> + <BitField name="ISRPREEMPT" start="23" size="1" description="" /> + <BitField name="ISRPENDING" start="22" size="1" description="Interrupt pending flag" /> + <BitField name="VECTPENDING" start="12" size="9" description="Indicates the exception number of the highest priority pending enabled exception" /> + <BitField name="RETTOBASE" start="11" size="1" description="Indicates whether there are preempted active exceptions" /> + <BitField name="VECTACTIVE" start="0" size="9" description="Contains the active exception number" /> + </Register> + <Register name="VTOR" start="0xE000ED08" description="Vector Table Offset Register"> + <BitField name="TBLOFF" start="7" size="25" description="Vector table base offset field" /> + </Register> + <Register name="AIRCR" start="0xE000ED0C" description="Application Interrupt and Reset Control Register"> + <BitField name="VECTKEY" start="16" size="16" description="Register key" /> + <BitField name="ENDIANESS" start="15" size="1" description="Data endianness bit" /> + <BitField name="PRIGROUP" start="8" size="3" description="Interrupt priority grouping field" /> + <BitField name="SYSRESETREQ" start="2" size="1" description="System reset request bit" /> + <BitField name="VECTCLRACTIVE" start="1" size="1" description="" /> + <BitField name="VECTRESET" start="0" size="1" description="" /> + </Register> + <Register name="SCR" start="0xE000ED10" description="System Control Register"> + <BitField name="SEVONPEND" start="4" size="1" description="Send event on pending bit" /> + <BitField name="SLEEPDEEP" start="2" size="1" description="Controls whether the processor uses sleep or deep sleep as its low power mode" /> + <BitField name="SLEEPONEXIT" start="1" size="1" description="Indicates sleep-on-exit when returning from Handler mode to Thread mode" /> + </Register> + <Register name="CCR" start="0xE000ED14" access="ReadOnly" description="Configuration and Control Register"> + <BitField name="STKALIGN" start="9" size="1" description="Indicates stack alignment on exception entry" /> + <BitField name="BFHFNMIGN" start="8" size="1" description="Enables handlers with priority -1 or-2 to ignore data BusFaults caused by load and store instructions" /> + <BitField name="DIV_0_TRP" start="4" size="1" description="Enables faulting or halting when the processor executes an SDIVor UDIV instruction with a divisor of 0" /> + <BitField name="UNALIGN_TRP" start="3" size="1" description="Enables unaligned access traps" /> + <BitField name="USERSETMPEND" start="1" size="1" description="Enables unprivileged software access to the STIR" /> + <BitField name="NONBASETHRDENA" start="0" size="1" description="Indicates how the processor enters Thread mode" /> + </Register> + <Register name="SHPR1" start="0xE000ED18" description="System Handler Priority Register 1"> + <BitField name="PRI_6" start="20" size="4" description="Priority of system handler 6 (UsageFault)" /> + <BitField name="PRI_5" start="12" size="4" description="Priority of system handler 5 (BusFault)" /> + <BitField name="PRI_4" start="4" size="4" description="Priority of system handler 4 (MemManage)" /> + </Register> + <Register name="SHPR2" start="0xE000ED1C" description="System Handler Priority Register 2"> + <BitField name="PRI_11" start="28" size="4" description="Priority of system handler 11 (SVCall)" /> + </Register> + <Register name="SHPR3" start="0xE000ED20" description="System Handler Priority Register 3"> + <BitField name="PRI_15" start="28" size="4" description="Priority of system handler 15 (SysTick)" /> + <BitField name="PRI_14" start="20" size="4" description="Priority of system handler 14 (PendSV)" /> + </Register> + <Register name="SHCSR" start="0xE000ED24" description="System Handler Control and State Register"> + <BitField name="USGFAULTENA" start="18" size="1" description="UsageFault enable Bit" /> + <BitField name="BUSFAULTENA" start="17" size="1" description="BusFault Enable Bit" /> + <BitField name="MEMFAULTENA" start="16" size="1" description="MemManage Enable Bit" /> + <BitField name="SVCALLPENDED" start="15" size="1" description="SVCall Pending Bit" /> + <BitField name="BUSFAULTPENDED" start="14" size="1" description="BusFault Exception Pending Bit" /> + <BitField name="MEMFAULTPENDED" start="13" size="1" description="MemManage Exception Pending Bit" /> + <BitField name="USGFAULTPENDED" start="12" size="1" description="UsageFault Exception Pending Bit" /> + <BitField name="SYSTICKACT" start="11" size="1" description="SysTick Exception Active Bit" /> + <BitField name="PENDSVACT" start="10" size="1" description="PendSV Exception Active Bit" /> + <BitField name="MONITORACT" start="8" size="1" description="Debug Monitor Active Bit" /> + <BitField name="SVCALLACT" start="7" size="1" description="SVCall Active Bit" /> + <BitField name="USGFAULTACT" start="3" size="1" description="UsageFault Exception Active Bit" /> + <BitField name="BUSFAULTACT" start="1" size="1" description="BusFault Exception Active Bit" /> + <BitField name="MEMFAULTACT" start="0" size="1" description="MemManage Exception Active Bit" /> + </Register> + <Register name="MMSR" start="0xE000ED28" size="1" description="MemManage Fault Status Register"> + <BitField name="MMARVALID" start="7" size="1" description="MemManage Fault Address Register(MMFAR) valid flag" /> + <BitField name="MLSPERR" start="5" size="1" description="Indicates a MemManage fault occurred during floating-point lazy state preservation" /> + <BitField name="MSTKERR" start="4" size="1" description="MemManage fault on stacking for exception entry" /> + <BitField name="MUNSTKERR" start="3" size="1" description="MemManage fault on unstacking for a return from exception" /> + <BitField name="DACCVIOL" start="1" size="1" description="Data access violation flag" /> + <BitField name="IACCVIOL" start="0" size="1" description="Instruction access violation flag" /> + </Register> + <Register name="BFSR" start="0xE000ED29" size="1" description="BusFault Status Register"> + <BitField name="BFARVALID" start="7" size="1" description="BusFault Address Register(BFAR) valid flag" /> + <BitField name="LSPERR" start="5" size="1" description="Indicates a bus fault occurred during floating-point lazy state preservation" /> + <BitField name="STKERR" start="4" size="1" description="BusFault on stacking for exception entry" /> + <BitField name="UNSTKERR" start="3" size="1" description="BusFault on unstacking for a return from exception" /> + <BitField name="IMPRECISERR" start="2" size="1" description="Imprecise data bus error" /> + <BitField name="PRECISERR" start="1" size="1" description="Precise data bus error" /> + <BitField name="IBUSERR" start="0" size="1" description="Instruction bus error" /> + </Register> + <Register name="UFSR" start="0xE000ED2A" size="2" description="UsageFault Status Register"> + <BitField name="DIVBYZERO" start="9" size="1" description="Divide by zero UsageFault" /> + <BitField name="UNALIGNED" start="8" size="1" description="Unaligned access UsageFault" /> + <BitField name="NOCP" start="3" size="1" description="No coprocessor UsageFault" /> + <BitField name="INVPC" start="2" size="1" description="Invalid PC load UsageFault, causedby an invalid PC load by EXC_RETURN" /> + <BitField name="INVSTATE" start="1" size="1" description="Invalid state UsageFault" /> + <BitField name="UNDEFINSTR" start="0" size="1" description="Undefined instruction UsageFault" /> + </Register> + <Register name="HFSR" start="0xE000ED2C" description="HardFault Status Register"> + <BitField name="DEBUGEVT" start="31" size="1" description="" /> + <BitField name="FORCED" start="30" size="1" description="Indicates a forced hard fault, generated by escalation of a fault with configurable priority that cannot be handled, either because of priority or because it is disabled" /> + <BitField name="VECTTBL" start="1" size="1" description="Indicates a BusFault on a vectortable read during exception processing" /> + </Register> + <Register name="DFSR" start="0xE000ED30" description="Debug Fault Status Register"> + <BitField name="EXTERNAL" start="4" size="1" description="" /> + <BitField name="VCATCH" start="3" size="1" description="" /> + <BitField name="DWTTRAP" start="2" size="1" description="" /> + <BitField name="BKPT" start="1" size="1" description="" /> + <BitField name="HALTED" start="0" size="1" description="" /> + </Register> + <Register name="MMAR" start="0xE000ED34" description="MemManage Fault Address Register"> + <BitField name="ADDRESS" start="0" size="32" description="When the MMARVALID bit of the MMFSR is set to 1, this field holds the address of the location that generated the MemManage fault" /> + </Register> + <Register name="BFAR" start="0xE000ED38" description="BusFault Address Register"> + <BitField name="ADDRESS" start="0" size="32" description="When the BFARVALID bit of the BFSR is set to1, this field holds the address of the location that generated the BusFault" /> + </Register> + <Register name="AFSR" start="0xE000ED3C" description="Auxiliary Fault Status Register"> + <BitField name="IMPDEF" start="0" size="32" description="Implementation defined, the bits map to the AUXFAULT input signals" /> + </Register> + </RegisterGroup> + <RegisterGroup name="MPU" start="0xE000ED90" description="Memory Protection Unit"> + <Register name="MPU_TYPE" start="0xE000ED90" access="ReadOnly" description="MPU Type Register"> + <BitField name="IREGION" start="16" size="8" description="Number of supported MPU instruction regions" /> + <BitField name="DREGION" start="8" size="8" description="Number of supported MPU data regions" /> + <BitField name="SEPARATE" start="0" size="1" description="Support for unified or separate instruction and date memory maps" /> + </Register> + <Register name="MPU_CTRL" start="0xE000ED94" description="MPU Control Register"> + <BitField name="PRIVDEFENA" start="2" size="1" description="Enables privileged software access to the default memory map" /> + <BitField name="HFNMIENA" start="1" size="1" description="Enable the operation of MPU during hard fault, NMI, and FAULTMASK handlers" /> + <BitField name="ENABLE" start="0" size="1" description="Enable MPU" /> + </Register> + <Register name="MPU_RNR" start="0xE000ED98" description="MPU Region Number Register"> + <BitField name="REGION" start="0" size="8" description="Indicates the MPU region referenced by the MPU_RBAR and MPU_RASR registers" /> + </Register> + <Register name="MPU_RBAR" start="0xE000ED9C" description="MPU Region Base Address Register"> + <BitField name="ADDR" start="5" size="27" description="Region base address field" /> + <BitField name="VALID" start="4" size="1" description="MPU Region Number valid bit" /> + <BitField name="REGION" start="0" size="4" description="MPU region field" /> + </Register> + <Register name="MPU_RASR" start="0xE000EDA0" description="MPU Region Attribute and Size Register"> + <BitField name="XN" start="28" size="1" description="Instruction access disable bit" /> + <BitField name="AP" start="24" size="3" description="Access permission field" /> + <BitField name="TEX" start="19" size="3" description="Memory access attribute" /> + <BitField name="S" start="18" size="1" description="Shareable bit" /> + <BitField name="C" start="17" size="1" description="Memory access attribute" /> + <BitField name="B" start="16" size="1" description="Memory access attribute" /> + <BitField name="SRD" start="8" size="8" description="Subregion disable bits" /> + <BitField name="SIZE" start="1" size="5" description="MPU protection region size" /> + <BitField name="ENABLE" start="0" size="1" description="Region enable bit" /> + </Register> + </RegisterGroup> +</Processor> diff --git a/examples/device/cdc_msc_hid/ses/lpc40xx/LPC408x_7x_Vectors.s b/examples/device/cdc_msc_hid/ses/lpc40xx/LPC408x_7x_Vectors.s new file mode 100644 index 000000000..025685469 --- /dev/null +++ b/examples/device/cdc_msc_hid/ses/lpc40xx/LPC408x_7x_Vectors.s @@ -0,0 +1,458 @@ +/***************************************************************************** + * SEGGER Microcontroller GmbH & Co. KG * + * Solutions for real time microcontroller applications * + ***************************************************************************** + * * + * (c) 2017 SEGGER Microcontroller GmbH & Co. KG * + * * + * Internet: www.segger.com Support: [email protected] * + * * + *****************************************************************************/ + +/***************************************************************************** + * Preprocessor Definitions * + * ------------------------ * + * VECTORS_IN_RAM * + * * + * If defined, an area of RAM will large enough to store the vector table * + * will be reserved. * + * * + *****************************************************************************/ + + .syntax unified + .code 16 + + .section .init, "ax" + .align 0 + +/***************************************************************************** + * Default Exception Handlers * + *****************************************************************************/ + + .thumb_func + .weak NMI_Handler +NMI_Handler: + b . + + .thumb_func + .weak HardFault_Handler +HardFault_Handler: + b . + + .thumb_func + .weak SVC_Handler +SVC_Handler: + b . + + .thumb_func + .weak PendSV_Handler +PendSV_Handler: + b . + + .thumb_func + .weak SysTick_Handler +SysTick_Handler: + b . + + .thumb_func +Dummy_Handler: + b . + +#if defined(__OPTIMIZATION_SMALL) + + .weak WWDT_IRQHandler + .thumb_set WWDT_IRQHandler,Dummy_Handler + + .weak TIMER0_IRQHandler + .thumb_set TIMER0_IRQHandler,Dummy_Handler + + .weak TIMER1_IRQHandler + .thumb_set TIMER1_IRQHandler,Dummy_Handler + + .weak TIMER2_IRQHandler + .thumb_set TIMER2_IRQHandler,Dummy_Handler + + .weak TIMER3_IRQHandler + .thumb_set TIMER3_IRQHandler,Dummy_Handler + + .weak UART0_IRQHandler + .thumb_set UART0_IRQHandler,Dummy_Handler + + .weak UART1_IRQHandler + .thumb_set UART1_IRQHandler,Dummy_Handler + + .weak UART2_IRQHandler + .thumb_set UART2_IRQHandler,Dummy_Handler + + .weak UART3_IRQHandler + .thumb_set UART3_IRQHandler,Dummy_Handler + + .weak PWM1_IRQHandler + .thumb_set PWM1_IRQHandler,Dummy_Handler + + .weak I2C0_IRQHandler + .thumb_set I2C0_IRQHandler,Dummy_Handler + + .weak I2C1_IRQHandler + .thumb_set I2C1_IRQHandler,Dummy_Handler + + .weak I2C2_IRQHandler + .thumb_set I2C2_IRQHandler,Dummy_Handler + + .weak SSP0_IRQHandler + .thumb_set SSP0_IRQHandler,Dummy_Handler + + .weak SSP1_IRQHandler + .thumb_set SSP1_IRQHandler,Dummy_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Dummy_Handler + + .weak EINT0_IRQHandler + .thumb_set EINT0_IRQHandler,Dummy_Handler + + .weak EINT1_IRQHandler + .thumb_set EINT1_IRQHandler,Dummy_Handler + + .weak EINT2_IRQHandler + .thumb_set EINT2_IRQHandler,Dummy_Handler + + .weak EINT3_IRQHandler + .thumb_set EINT3_IRQHandler,Dummy_Handler + + .weak ADC_IRQHandler + .thumb_set ADC_IRQHandler,Dummy_Handler + + .weak BOD_IRQHandler + .thumb_set BOD_IRQHandler,Dummy_Handler + + .weak USB_IRQHandler + .thumb_set USB_IRQHandler,Dummy_Handler + + .weak CAN_IRQHandler + .thumb_set CAN_IRQHandler,Dummy_Handler + + .weak GPDMA_IRQHandler + .thumb_set GPDMA_IRQHandler,Dummy_Handler + + .weak I2S_IRQHandler + .thumb_set I2S_IRQHandler,Dummy_Handler + + .weak ETHERNET_IRQHandler + .thumb_set ETHERNET_IRQHandler,Dummy_Handler + + .weak SDMMC_IRQHandler + .thumb_set SDMMC_IRQHandler,Dummy_Handler + + .weak MCPWM_IRQHandler + .thumb_set MCPWM_IRQHandler,Dummy_Handler + + .weak QEI_IRQHandler + .thumb_set QEI_IRQHandler,Dummy_Handler + + .weak USB_NEED_CLK_IRQHandler + .thumb_set USB_NEED_CLK_IRQHandler,Dummy_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Dummy_Handler + + .weak SSP2_IRQHandler + .thumb_set SSP2_IRQHandler,Dummy_Handler + + .weak LCD_IRQHandler + .thumb_set LCD_IRQHandler,Dummy_Handler + + .weak GPIOINT_IRQHandler + .thumb_set GPIOINT_IRQHandler,Dummy_Handler + + .weak PWM0_IRQHandler + .thumb_set PWM0_IRQHandler,Dummy_Handler + + .weak EEPROM_IRQHandler + .thumb_set EEPROM_IRQHandler,Dummy_Handler + + .weak CMP0_IRQHandler + .thumb_set CMP0_IRQHandler,Dummy_Handler + + .weak CMP1_IRQHandler + .thumb_set CMP1_IRQHandler,Dummy_Handler + +#else + + .thumb_func + .weak WWDT_IRQHandler +WWDT_IRQHandler: + b . + + .thumb_func + .weak TIMER0_IRQHandler +TIMER0_IRQHandler: + b . + + .thumb_func + .weak TIMER1_IRQHandler +TIMER1_IRQHandler: + b . + + .thumb_func + .weak TIMER2_IRQHandler +TIMER2_IRQHandler: + b . + + .thumb_func + .weak TIMER3_IRQHandler +TIMER3_IRQHandler: + b . + + .thumb_func + .weak UART0_IRQHandler +UART0_IRQHandler: + b . + + .thumb_func + .weak UART1_IRQHandler +UART1_IRQHandler: + b . + + .thumb_func + .weak UART2_IRQHandler +UART2_IRQHandler: + b . + + .thumb_func + .weak UART3_IRQHandler +UART3_IRQHandler: + b . + + .thumb_func + .weak PWM1_IRQHandler +PWM1_IRQHandler: + b . + + .thumb_func + .weak I2C0_IRQHandler +I2C0_IRQHandler: + b . + + .thumb_func + .weak I2C1_IRQHandler +I2C1_IRQHandler: + b . + + .thumb_func + .weak I2C2_IRQHandler +I2C2_IRQHandler: + b . + + .thumb_func + .weak SSP0_IRQHandler +SSP0_IRQHandler: + b . + + .thumb_func + .weak SSP1_IRQHandler +SSP1_IRQHandler: + b . + + .thumb_func + .weak RTC_IRQHandler +RTC_IRQHandler: + b . + + .thumb_func + .weak EINT0_IRQHandler +EINT0_IRQHandler: + b . + + .thumb_func + .weak EINT1_IRQHandler +EINT1_IRQHandler: + b . + + .thumb_func + .weak EINT2_IRQHandler +EINT2_IRQHandler: + b . + + .thumb_func + .weak EINT3_IRQHandler +EINT3_IRQHandler: + b . + + .thumb_func + .weak ADC_IRQHandler +ADC_IRQHandler: + b . + + .thumb_func + .weak BOD_IRQHandler +BOD_IRQHandler: + b . + + .thumb_func + .weak USB_IRQHandler +USB_IRQHandler: + b . + + .thumb_func + .weak CAN_IRQHandler +CAN_IRQHandler: + b . + + .thumb_func + .weak GPDMA_IRQHandler +GPDMA_IRQHandler: + b . + + .thumb_func + .weak I2S_IRQHandler +I2S_IRQHandler: + b . + + .thumb_func + .weak ETHERNET_IRQHandler +ETHERNET_IRQHandler: + b . + + .thumb_func + .weak SDMMC_IRQHandler +SDMMC_IRQHandler: + b . + + .thumb_func + .weak MCPWM_IRQHandler +MCPWM_IRQHandler: + b . + + .thumb_func + .weak QEI_IRQHandler +QEI_IRQHandler: + b . + + .thumb_func + .weak USB_NEED_CLK_IRQHandler +USB_NEED_CLK_IRQHandler: + b . + + .thumb_func + .weak UART4_IRQHandler +UART4_IRQHandler: + b . + + .thumb_func + .weak SSP2_IRQHandler +SSP2_IRQHandler: + b . + + .thumb_func + .weak LCD_IRQHandler +LCD_IRQHandler: + b . + + .thumb_func + .weak GPIOINT_IRQHandler +GPIOINT_IRQHandler: + b . + + .thumb_func + .weak PWM0_IRQHandler +PWM0_IRQHandler: + b . + + .thumb_func + .weak EEPROM_IRQHandler +EEPROM_IRQHandler: + b . + + .thumb_func + .weak CMP0_IRQHandler +CMP0_IRQHandler: + b . + + .thumb_func + .weak CMP1_IRQHandler +CMP1_IRQHandler: + b . + +#endif + +/***************************************************************************** + * Vector Table * + *****************************************************************************/ + + .section .vectors, "ax" + .align 0 + .global _vectors + .extern __stack_end__ + .extern Reset_Handler + +_vectors: + .word __stack_end__ + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word SVC_Handler + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word PendSV_Handler + .word SysTick_Handler + .word WWDT_IRQHandler + .word TIMER0_IRQHandler + .word TIMER1_IRQHandler + .word TIMER2_IRQHandler + .word TIMER3_IRQHandler + .word UART0_IRQHandler + .word UART1_IRQHandler + .word UART2_IRQHandler + .word UART3_IRQHandler + .word PWM1_IRQHandler + .word I2C0_IRQHandler + .word I2C1_IRQHandler + .word I2C2_IRQHandler + .word Dummy_Handler /* Reserved */ + .word SSP0_IRQHandler + .word SSP1_IRQHandler + .word Dummy_Handler /* Reserved */ + .word RTC_IRQHandler + .word EINT0_IRQHandler + .word EINT1_IRQHandler + .word EINT2_IRQHandler + .word EINT3_IRQHandler + .word ADC_IRQHandler + .word BOD_IRQHandler + .word USB_IRQHandler + .word CAN_IRQHandler + .word GPDMA_IRQHandler + .word I2S_IRQHandler + .word ETHERNET_IRQHandler + .word SDMMC_IRQHandler + .word MCPWM_IRQHandler + .word QEI_IRQHandler + .word Dummy_Handler /* Reserved */ + .word USB_NEED_CLK_IRQHandler + .word Dummy_Handler /* Reserved */ + .word UART4_IRQHandler + .word SSP2_IRQHandler + .word LCD_IRQHandler + .word GPIOINT_IRQHandler + .word PWM0_IRQHandler + .word EEPROM_IRQHandler + .word CMP0_IRQHandler + .word CMP1_IRQHandler +_vectors_end: + +#ifdef VECTORS_IN_RAM + .section .vectors_ram, "ax" + .align 0 + .global _vectors_ram + +_vectors_ram: + .space _vectors_end - _vectors, 0 +#endif diff --git a/examples/device/cdc_msc_hid/ses/lpc40xx/flash_placement.xml b/examples/device/cdc_msc_hid/ses/lpc40xx/flash_placement.xml new file mode 100644 index 000000000..79bedc537 --- /dev/null +++ b/examples/device/cdc_msc_hid/ses/lpc40xx/flash_placement.xml @@ -0,0 +1,37 @@ +<!DOCTYPE Linker_Placement_File> +<Root name="Flash Section Placement"> + <MemorySegment name="$(FLASH_NAME:FLASH)"> + <ProgramSection alignment="0x100" load="Yes" name=".vectors" start="$(FLASH_START:)" /> + <ProgramSection alignment="4" load="Yes" name=".init" /> + <ProgramSection alignment="4" load="Yes" name=".init_rodata" /> + <ProgramSection alignment="4" load="Yes" name=".text" /> + <ProgramSection alignment="4" load="Yes" name=".dtors" /> + <ProgramSection alignment="4" load="Yes" name=".ctors" /> + <ProgramSection alignment="4" load="Yes" name=".rodata" /> + <ProgramSection alignment="4" load="Yes" name=".ARM.exidx" address_symbol="__exidx_start" end_symbol="__exidx_end" /> + <ProgramSection alignment="4" load="Yes" runin=".fast_run" name=".fast" /> + <ProgramSection alignment="4" load="Yes" runin=".data_run" name=".data" /> + <ProgramSection alignment="4" load="Yes" runin=".tdata_run" name=".tdata" /> + </MemorySegment> + <MemorySegment name="$(RAM_NAME:RAM);SRAM"> + <ProgramSection alignment="0x100" load="No" name=".vectors_ram" start="$(RAM_START:$(SRAM_START:))" /> + <ProgramSection alignment="4" load="No" name=".fast_run" /> + <ProgramSection alignment="4" load="No" name=".data_run" /> + <ProgramSection alignment="4" load="No" name=".bss" /> + <ProgramSection alignment="4" load="No" name=".tbss" /> + <ProgramSection alignment="4" load="No" name=".tdata_run" /> + <ProgramSection alignment="4" load="No" name=".non_init" /> + <ProgramSection alignment="4" size="__HEAPSIZE__" load="No" name=".heap" /> + <ProgramSection alignment="8" size="__STACKSIZE__" load="No" place_from_segment_end="Yes" name=".stack" /> + <ProgramSection alignment="8" size="__STACKSIZE_PROCESS__" load="No" name=".stack_process" /> + </MemorySegment> + <MemorySegment name="$(FLASH2_NAME:FLASH2)"> + <ProgramSection alignment="4" load="Yes" name=".text2" /> + <ProgramSection alignment="4" load="Yes" name=".rodata2" /> + <ProgramSection alignment="4" load="Yes" runin=".data2_run" name=".data2" /> + </MemorySegment> + <MemorySegment name="$(RAM2_NAME:RAM2)"> + <ProgramSection alignment="4" load="No" name=".data2_run" /> + <ProgramSection alignment="4" load="No" name=".bss2" /> + </MemorySegment> +</Root> diff --git a/examples/device/cdc_msc_hid/ses/lpc40xx/lpc40xx.emProject b/examples/device/cdc_msc_hid/ses/lpc40xx/lpc40xx.emProject new file mode 100644 index 000000000..da115786b --- /dev/null +++ b/examples/device/cdc_msc_hid/ses/lpc40xx/lpc40xx.emProject @@ -0,0 +1,120 @@ +<!DOCTYPE CrossStudio_Project_File> +<solution Name="lpc40xx" target="8" version="2"> + <project Name="lpc40xx"> + <configuration + Name="Common" + Placement="Flash" + Target="LPC4088FBD208" + arm_architecture="v7EM" + arm_core_type="Cortex-M4" + arm_endian="Little" + arm_fp_abi="Hard" + arm_fpu_type="FPv4-SP-D16" + arm_interwork="No" + arm_linker_heap_size="256" + arm_linker_process_stack_size="0" + arm_linker_stack_size="256" + arm_simulator_memory_simulation_parameter="ROM;0x00000000;0x00080000;RAM;0x10000000;0x00010000;RAM;0x20000000;0x00008000" + arm_target_debug_interface_type="ADIv5" + arm_target_device_name="LPC4088" + arm_target_interface_type="SWD" + build_treat_warnings_as_errors="Yes" + c_preprocessor_definitions="CORE_M4;__LPC4000_FAMILY;__LPC408x_SUBFAMILY;ARM_MATH_CM4;FLASH_PLACEMENT=1;BOARD_EA4088QS;CFG_TUSB_MCU=OPT_MCU_LPC40XX;CFG_TUSB_MEM_SECTION= __attribute__((section(".bss2")))" + c_user_include_directories="../../src;$(rootDir)/hw;$(rootDir)/src;$(lpcDir)/inc" + debug_register_definition_file="$(ProjectDir)/LPC408x_7x_Registers.xml" + debug_target_connection="J-Link" + gcc_enable_all_warnings="Yes" + gcc_entry_point="Reset_Handler" + linker_memory_map_file="$(ProjectDir)/LPC4088FBD208_MemoryMap.xml" + linker_section_placement_file="$(ProjectDir)/flash_placement.xml" + macros="DeviceFamily=LPC4000;DeviceSubFamily=LPC408x;Target=LPC4088FBD208;Placement=Flash;rootDir=../../../../..;lpcDir=../../../../../hw/mcu/nxp/lpc_chip_40xx" + package_dependencies="LPC4000" + project_directory="" + project_type="Executable" + target_reset_script="Reset();" + target_trace_initialize_script="EnableTrace("$(TraceInterfaceType)")" /> + <folder Name="System Files"> + <file file_name="thumb_crt0.s" /> + <file file_name="LPC4000_Startup.s" /> + <file file_name="LPC408x_7x_Vectors.s"> + <configuration Name="Common" file_type="Assembly" /> + </file> + <file file_name="LPC4088FBD208_MemoryMap.xml" /> + <file file_name="flash_placement.xml" /> + <file file_name="LPC4000_Target.js"> + <configuration Name="Common" file_type="Reset Script" /> + </file> + </folder> + <configuration + Name="EA4088 QuickStart" + link_use_linker_script_file="No" + linker_section_placement_file="flash_placement.xml" /> + <folder Name="hw"> + <folder Name="bsp"> + <file file_name="../../../../../hw/bsp/ansi_escape.h" /> + <file file_name="../../../../../hw/bsp/board.h" /> + <folder Name="ea4088qs"> + <file file_name="../../../../../hw/bsp/ea4088qs/board_ea4088qs.c" /> + <file file_name="../../../../../hw/bsp/ea4088qs/board_ea4088qs.h" /> + </folder> + </folder> + <folder Name="mcu"> + <folder Name="nxp"> + <folder Name="lpc_chip_40xx"> + <folder Name="inc"> + <file file_name="../../../../../hw/mcu/nxp/lpc_chip_40xx/inc/chip.h" /> + <file file_name="../../../../../hw/mcu/nxp/lpc_chip_40xx/inc/chip_lpc175x_6x.h" /> + <file file_name="../../../../../hw/mcu/nxp/lpc_chip_40xx/inc/chip_lpc177x_8x.h" /> + <file file_name="../../../../../hw/mcu/nxp/lpc_chip_40xx/inc/chip_lpc407x_8x.h" /> + <file file_name="../../../../../hw/mcu/nxp/lpc_chip_40xx/inc/clock_17xx_40xx.h" /> + <file file_name="../../../../../hw/mcu/nxp/lpc_chip_40xx/inc/cmsis.h" /> + <file file_name="../../../../../hw/mcu/nxp/lpc_chip_40xx/inc/cmsis_40xx.h" /> + <file file_name="../../../../../hw/mcu/nxp/lpc_chip_40xx/inc/core_cm4.h" /> + <file file_name="../../../../../hw/mcu/nxp/lpc_chip_40xx/inc/core_cm4_simd.h" /> + <file file_name="../../../../../hw/mcu/nxp/lpc_chip_40xx/inc/core_cmFunc.h" /> + <file file_name="../../../../../hw/mcu/nxp/lpc_chip_40xx/inc/core_cmInstr.h" /> + <file file_name="../../../../../hw/mcu/nxp/lpc_chip_40xx/inc/gpio_17xx_40xx.h" /> + <file file_name="../../../../../hw/mcu/nxp/lpc_chip_40xx/inc/sys_config.h" /> + <file file_name="../../../../../hw/mcu/nxp/lpc_chip_40xx/inc/sysctl_17xx_40xx.h" /> + <file file_name="../../../../../hw/mcu/nxp/lpc_chip_40xx/inc/uart_17xx_40xx.h" /> + <file file_name="../../../../../hw/mcu/nxp/lpc_chip_40xx/inc/usb_17xx_40xx.h" /> + <file file_name="../../../../../hw/mcu/nxp/lpc_chip_40xx/inc/iocon_17xx_40xx.h" /> + </folder> + <folder Name="src"> + <file file_name="../../../../../hw/mcu/nxp/lpc_chip_40xx/src/chip_17xx_40xx.c" /> + <file file_name="../../../../../hw/mcu/nxp/lpc_chip_40xx/src/clock_17xx_40xx.c" /> + <file file_name="../../../../../hw/mcu/nxp/lpc_chip_40xx/src/gpio_17xx_40xx.c" /> + <file file_name="../../../../../hw/mcu/nxp/lpc_chip_40xx/src/iocon_17xx_40xx.c" /> + <file file_name="../../../../../hw/mcu/nxp/lpc_chip_40xx/src/sysctl_17xx_40xx.c" /> + <file file_name="../../../../../hw/mcu/nxp/lpc_chip_40xx/src/sysinit_17xx_40xx.c" /> + <file file_name="../../../../../hw/mcu/nxp/lpc_chip_40xx/src/uart_17xx_40xx.c" /> + </folder> + </folder> + </folder> + </folder> + </folder> + <folder + Name="segger_rtt" + exclude="" + filter="*.c;*.h" + path="../../../../../lib/segger_rtt" + recurse="No" /> + <folder + Name="src" + exclude="" + filter="*.c;*.h" + path="../../src" + recurse="Yes" /> + <folder + Name="tinyusb" + exclude="" + filter="*.c;*.h" + path="../../../../../src" + recurse="Yes" /> + </project> + <configuration + Name="EA4088 QuickStart" + c_preprocessor_definitions="DEBUG" + gcc_debugging_level="Level 3" + gcc_optimization_level="None" /> +</solution> diff --git a/examples/device/cdc_msc_hid/ses/lpc40xx/thumb_crt0.s b/examples/device/cdc_msc_hid/ses/lpc40xx/thumb_crt0.s new file mode 100644 index 000000000..17f88e0ca --- /dev/null +++ b/examples/device/cdc_msc_hid/ses/lpc40xx/thumb_crt0.s @@ -0,0 +1,415 @@ +// ********************************************************************** +// * SEGGER Microcontroller GmbH * +// * The Embedded Experts * +// ********************************************************************** +// * * +// * (c) 2014 - 2018 SEGGER Microcontroller GmbH * +// * (c) 2001 - 2018 Rowley Associates Limited * +// * * +// * www.segger.com Support: [email protected] * +// * * +// ********************************************************************** +// * * +// * All rights reserved. * +// * * +// * Redistribution and use in source and binary forms, with or * +// * without modification, are permitted provided that the following * +// * conditions are met: * +// * * +// * - Redistributions of source code must retain the above copyright * +// * notice, this list of conditions and the following disclaimer. * +// * * +// * - Neither the name of SEGGER Microcontroller GmbH * +// * nor the names of its contributors may be used to endorse or * +// * promote products derived from this software without specific * +// * prior written permission. * +// * * +// * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND * +// * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, * +// * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * +// * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * +// * DISCLAIMED. * +// * IN NO EVENT SHALL SEGGER Microcontroller GmbH BE LIABLE FOR * +// * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * +// * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT * +// * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * +// * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF * +// * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * +// * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE * +// * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH * +// * DAMAGE. * +// * * +// ********************************************************************** +// +// +// Preprocessor Definitions +// ------------------------ +// APP_ENTRY_POINT +// +// Defines the application entry point function, if undefined this setting +// defaults to "main". +// +// INITIALIZE_STACK +// +// If defined, the contents of the stack will be initialized to a the +// value 0xCC. +// +// INITIALIZE_SECONDARY_SECTIONS +// +// If defined, the .data2, .text2, .rodata2 and .bss2 sections will be initialized. +// +// INITIALIZE_TCM_SECTIONS +// +// If defined, the .data_tcm, .text_tcm, .rodata_tcm and .bss_tcm sections +// will be initialized. +// +// INITIALIZE_USER_SECTIONS +// +// If defined, the function InitializeUserMemorySections will be called prior +// to entering main in order to allow the user to initialize any user defined +// memory sections. +// +// FULL_LIBRARY +// +// If defined then +// - argc, argv are setup by the debug_getargs. +// - the exit symbol is defined and executes on return from main. +// - the exit symbol calls destructors, atexit functions and then debug_exit. +// +// If not defined then +// - argc and argv are zero. +// - the exit symbol is defined, executes on return from main and loops +// + +#ifndef APP_ENTRY_POINT +#define APP_ENTRY_POINT main +#endif + +#ifndef ARGSSPACE +#define ARGSSPACE 128 +#endif + .syntax unified + + .global _start + .extern APP_ENTRY_POINT + .global exit + .weak exit + +#ifdef INITIALIZE_USER_SECTIONS + .extern InitializeUserMemorySections +#endif + + .section .init, "ax" + .code 16 + .balign 2 + .thumb_func + +_start: + /* Set up main stack if size > 0 */ + ldr r1, =__stack_end__ + ldr r0, =__stack_start__ + subs r2, r1, r0 + beq 1f +#ifdef __ARM_EABI__ + movs r2, #0x7 + bics r1, r2 +#endif + mov sp, r1 +#ifdef INITIALIZE_STACK + movs r2, #0xCC + ldr r0, =__stack_start__ + bl memory_set +#endif +1: + + /* Set up process stack if size > 0 */ + ldr r1, =__stack_process_end__ + ldr r0, =__stack_process_start__ + subs r2, r1, r0 + beq 1f +#ifdef __ARM_EABI__ + movs r2, #0x7 + bics r1, r2 +#endif + msr psp, r1 + movs r2, #2 + msr control, r2 +#ifdef INITIALIZE_STACK + movs r2, #0xCC + bl memory_set +#endif +1: + + /* Copy initialized memory sections into RAM (if necessary). */ + ldr r0, =__data_load_start__ + ldr r1, =__data_start__ + ldr r2, =__data_end__ + bl memory_copy + ldr r0, =__text_load_start__ + ldr r1, =__text_start__ + ldr r2, =__text_end__ + bl memory_copy + ldr r0, =__fast_load_start__ + ldr r1, =__fast_start__ + ldr r2, =__fast_end__ + bl memory_copy + ldr r0, =__ctors_load_start__ + ldr r1, =__ctors_start__ + ldr r2, =__ctors_end__ + bl memory_copy + ldr r0, =__dtors_load_start__ + ldr r1, =__dtors_start__ + ldr r2, =__dtors_end__ + bl memory_copy + ldr r0, =__rodata_load_start__ + ldr r1, =__rodata_start__ + ldr r2, =__rodata_end__ + bl memory_copy + ldr r0, =__tdata_load_start__ + ldr r1, =__tdata_start__ + ldr r2, =__tdata_end__ + bl memory_copy +#ifdef INITIALIZE_SECONDARY_SECTIONS + ldr r0, =__data2_load_start__ + ldr r1, =__data2_start__ + ldr r2, =__data2_end__ + bl memory_copy + ldr r0, =__text2_load_start__ + ldr r1, =__text2_start__ + ldr r2, =__text2_end__ + bl memory_copy + ldr r0, =__rodata2_load_start__ + ldr r1, =__rodata2_start__ + ldr r2, =__rodata2_end__ + bl memory_copy +#endif /* #ifdef INITIALIZE_SECONDARY_SECTIONS */ +#ifdef INITIALIZE_TCM_SECTIONS + ldr r0, =__data_tcm_load_start__ + ldr r1, =__data_tcm_start__ + ldr r2, =__data_tcm_end__ + bl memory_copy + ldr r0, =__text_tcm_load_start__ + ldr r1, =__text_tcm_start__ + ldr r2, =__text_tcm_end__ + bl memory_copy + ldr r0, =__rodata_tcm_load_start__ + ldr r1, =__rodata_tcm_start__ + ldr r2, =__rodata_tcm_end__ + bl memory_copy +#endif /* #ifdef INITIALIZE_TCM_SECTIONS */ + + /* Zero the bss. */ + ldr r0, =__bss_start__ + ldr r1, =__bss_end__ + movs r2, #0 + bl memory_set + ldr r0, =__tbss_start__ + ldr r1, =__tbss_end__ + movs r2, #0 + bl memory_set +#ifdef INITIALIZE_SECONDARY_SECTIONS + ldr r0, =__bss2_start__ + ldr r1, =__bss2_end__ + mov r2, #0 + bl memory_set +#endif /* #ifdef INITIALIZE_SECONDARY_SECTIONS */ +#ifdef INITIALIZE_TCM_SECTIONS + ldr r0, =__bss_tcm_start__ + ldr r1, =__bss_tcm_end__ + mov r2, #0 + bl memory_set +#endif /* #ifdef INITIALIZE_TCM_SECTIONS */ + + /* Initialize the heap */ + ldr r0, = __heap_start__ + ldr r1, = __heap_end__ + subs r1, r1, r0 + cmp r1, #8 + blt 1f + movs r2, #0 + str r2, [r0] + adds r0, r0, #4 + str r1, [r0] +1: + +#ifdef INITIALIZE_USER_SECTIONS + ldr r2, =InitializeUserMemorySections + blx r2 +#endif + + /* Call constructors */ + ldr r0, =__ctors_start__ + ldr r1, =__ctors_end__ +ctor_loop: + cmp r0, r1 + beq ctor_end + ldr r2, [r0] + adds r0, #4 + push {r0-r1} + blx r2 + pop {r0-r1} + b ctor_loop +ctor_end: + + /* Setup initial call frame */ + movs r0, #0 + mov lr, r0 + mov r12, sp + + .type start, function +start: + /* Jump to application entry point */ +#ifdef FULL_LIBRARY + movs r0, #ARGSSPACE + ldr r1, =args + ldr r2, =debug_getargs + blx r2 + ldr r1, =args +#else + movs r0, #0 + movs r1, #0 +#endif + ldr r2, =APP_ENTRY_POINT + blx r2 + + .thumb_func +exit: +#ifdef FULL_LIBRARY + mov r5, r0 // save the exit parameter/return result + + /* Call destructors */ + ldr r0, =__dtors_start__ + ldr r1, =__dtors_end__ +dtor_loop: + cmp r0, r1 + beq dtor_end + ldr r2, [r0] + add r0, #4 + push {r0-r1} + blx r2 + pop {r0-r1} + b dtor_loop +dtor_end: + + /* Call atexit functions */ + ldr r2, =_execute_at_exit_fns + blx r2 + + /* Call debug_exit with return result/exit parameter */ + mov r0, r5 + ldr r2, =debug_exit + blx r2 +#endif + + /* Returned from application entry point, loop forever. */ +exit_loop: + b exit_loop + + .thumb_func +memory_copy: + cmp r0, r1 + beq 2f + subs r2, r2, r1 + beq 2f +1: + ldrb r3, [r0] + adds r0, r0, #1 + strb r3, [r1] + adds r1, r1, #1 + subs r2, r2, #1 + bne 1b +2: + bx lr + + .thumb_func +memory_set: + cmp r0, r1 + beq 1f + strb r2, [r0] + adds r0, r0, #1 + b memory_set +1: + bx lr + + // default C/C++ library helpers + +.macro HELPER helper_name + .section .text.\helper_name, "ax", %progbits + .balign 2 + .global \helper_name + .weak \helper_name +\helper_name: + .thumb_func +.endm + +.macro JUMPTO name +#if defined(__thumb__) && !defined(__thumb2__) + mov r12, r0 + ldr r0, =\name + push {r0} + mov r0, r12 + pop {pc} +#else + b \name +#endif +.endm + +HELPER __aeabi_read_tp + ldr r0, =__tbss_start__-8 + bx lr +HELPER abort + b . +HELPER __assert + b . +HELPER __aeabi_assert + b . +HELPER __sync_synchronize + bx lr +HELPER __getchar + JUMPTO debug_getchar +HELPER __putchar + JUMPTO debug_putchar +HELPER __open + JUMPTO debug_fopen +HELPER __close + JUMPTO debug_fclose +HELPER __write + mov r3, r0 + mov r0, r1 + movs r1, #1 + JUMPTO debug_fwrite +HELPER __read + mov r3, r0 + mov r0, r1 + movs r1, #1 + JUMPTO debug_fread +HELPER __seek + push {r4, lr} + mov r4, r0 + bl debug_fseek + cmp r0, #0 + bne 1f + mov r0, r4 + bl debug_ftell + pop {r4, pc} +1: + ldr r0, =-1 + pop {r4, pc} + // char __user_locale_name_buffer[]; + .section .bss.__user_locale_name_buffer, "aw", %nobits + .global __user_locale_name_buffer + .weak __user_locale_name_buffer + __user_locale_name_buffer: + .word 0x0 + +#ifdef FULL_LIBRARY + .bss +args: + .space ARGSSPACE +#endif + + /* Setup attibutes of stack and heap sections so they don't take up room in the elf file */ + .section .stack, "wa", %nobits + .section .stack_process, "wa", %nobits + .section .heap, "wa", %nobits + diff --git a/examples/device/cdc_msc_hid/ses/lpc43xx/lpc43xx.emProject b/examples/device/cdc_msc_hid/ses/lpc43xx/lpc43xx.emProject index 363fae3e2..cd33bb601 100644 --- a/examples/device/cdc_msc_hid/ses/lpc43xx/lpc43xx.emProject +++ b/examples/device/cdc_msc_hid/ses/lpc43xx/lpc43xx.emProject @@ -20,15 +20,16 @@ arm_target_interface_type="SWD" build_treat_warnings_as_errors="Yes" c_preprocessor_definitions="CORE_M4;__LPC4300_FAMILY;__LPC435x_SUBFAMILY;ARM_MATH_CM4;FLASH_PLACEMENT=1;BOARD_EA4357;CFG_TUSB_MCU=OPT_MCU_LPC43XX;CFG_TUSB_MEM_SECTION= __attribute__((section(".bss2")))" - c_user_include_directories="../../src;$(rootDir)/hw/cmsis/Include;$(rootDir)/hw;$(rootDir)/src;$(lpcDir)/CMSIS_LPC43xx_DriverLib/inc" + c_user_include_directories="../../src;$(rootDir)/hw;$(rootDir)/src;$(lpcDir)//inc;$(lpcDir)//inc/config_43xx" debug_register_definition_file="LPC43xx_Registers.xml" debug_target_connection="J-Link" + gcc_enable_all_warnings="Yes" gcc_entry_point="Reset_Handler" link_use_linker_script_file="No" linker_memory_map_file="LPC4357 Cortex-M4_MemoryMap.xml" linker_section_placement_file="flash_placement.xml" linker_section_placements_segments="FLASH RX 0x1a000000 0x00080000;RAM RWX 0x10000000 0x00008000" - macros="DeviceFamily=LPC4300;DeviceSubFamily=LPC435x;Target=LPC4357 Cortex-M4;Placement=Flash;rootDir=../../../../..;lpcDir=../../../../../hw/mcu/nxp/lpc43xx" + macros="DeviceFamily=LPC4300;DeviceSubFamily=LPC435x;Target=LPC4357 Cortex-M4;Placement=Flash;rootDir=../../../../..;lpcDir=../../../../../hw/mcu/nxp/lpc_chip_43xx" project_directory="" project_type="Executable" target_reset_script="Reset();" @@ -47,24 +48,61 @@ <folder Name="ea4357"> <file file_name="../../../../../hw/bsp/ea4357/board_ea4357.c" /> <file file_name="../../../../../hw/bsp/ea4357/board_ea4357.h" /> - <folder Name="oem_base_board"> - <file file_name="../../../../../hw/bsp/ea4357/oem_base_board/pca9532.c" /> - <file file_name="../../../../../hw/bsp/ea4357/oem_base_board/pca9532.h" /> - </folder> + <file file_name="../../../../../hw/bsp/ea4357/pca9532.c" /> + <file file_name="../../../../../hw/bsp/ea4357/pca9532.h" /> </folder> </folder> <folder Name="mcu"> <folder Name="nxp"> - <folder Name="lpc43xx"> - <folder Name="CMSIS_LPC43xx_DriverLib"> - <folder Name="src"> - <file file_name="../../../../../hw/mcu/nxp/lpc43xx/CMSIS_LPC43xx_DriverLib/src/system_LPC43xx.c" /> - <file file_name="../../../../../hw/mcu/nxp/lpc43xx/CMSIS_LPC43xx_DriverLib/src/lpc43xx_gpio.c" /> - <file file_name="../../../../../hw/mcu/nxp/lpc43xx/CMSIS_LPC43xx_DriverLib/src/lpc43xx_cgu.c" /> - <file file_name="../../../../../hw/mcu/nxp/lpc43xx/CMSIS_LPC43xx_DriverLib/src/lpc43xx_scu.c" /> - <file file_name="../../../../../hw/mcu/nxp/lpc43xx/CMSIS_LPC43xx_DriverLib/src/lpc43xx_i2c.c" /> + <folder Name="lpc_chip_43xx"> + <folder Name="inc"> + <file file_name="../../../../../hw/mcu/nxp/lpc_chip_43xx/inc/arm_common_tables.h" /> + <file file_name="../../../../../hw/mcu/nxp/lpc_chip_43xx/inc/arm_math.h" /> + <file file_name="../../../../../hw/mcu/nxp/lpc_chip_43xx/inc/cguccu_18xx_43xx.h" /> + <file file_name="../../../../../hw/mcu/nxp/lpc_chip_43xx/inc/chip.h" /> + <file file_name="../../../../../hw/mcu/nxp/lpc_chip_43xx/inc/chip_clocks.h" /> + <file file_name="../../../../../hw/mcu/nxp/lpc_chip_43xx/inc/chip_lpc18xx.h" /> + <file file_name="../../../../../hw/mcu/nxp/lpc_chip_43xx/inc/chip_lpc43xx.h" /> + <file file_name="../../../../../hw/mcu/nxp/lpc_chip_43xx/inc/clock_18xx_43xx.h" /> + <file file_name="../../../../../hw/mcu/nxp/lpc_chip_43xx/inc/cmsis.h" /> + <file file_name="../../../../../hw/mcu/nxp/lpc_chip_43xx/inc/cmsis_18xx.h" /> + <file file_name="../../../../../hw/mcu/nxp/lpc_chip_43xx/inc/cmsis_43xx.h" /> + <file file_name="../../../../../hw/mcu/nxp/lpc_chip_43xx/inc/cmsis_43xx_m0app.h" /> + <file file_name="../../../../../hw/mcu/nxp/lpc_chip_43xx/inc/cmsis_43xx_m0sub.h" /> + <file file_name="../../../../../hw/mcu/nxp/lpc_chip_43xx/inc/core_cm0.h" /> + <file file_name="../../../../../hw/mcu/nxp/lpc_chip_43xx/inc/core_cm0plus.h" /> + <file file_name="../../../../../hw/mcu/nxp/lpc_chip_43xx/inc/core_cm3.h" /> + <file file_name="../../../../../hw/mcu/nxp/lpc_chip_43xx/inc/core_cm4.h" /> + <file file_name="../../../../../hw/mcu/nxp/lpc_chip_43xx/inc/core_cm4_simd.h" /> + <file file_name="../../../../../hw/mcu/nxp/lpc_chip_43xx/inc/core_cmFunc.h" /> + <file file_name="../../../../../hw/mcu/nxp/lpc_chip_43xx/inc/core_cmInstr.h" /> + <file file_name="../../../../../hw/mcu/nxp/lpc_chip_43xx/inc/core_sc000.h" /> + <file file_name="../../../../../hw/mcu/nxp/lpc_chip_43xx/inc/core_sc300.h" /> + <file file_name="../../../../../hw/mcu/nxp/lpc_chip_43xx/inc/creg_18xx_43xx.h" /> + <file file_name="../../../../../hw/mcu/nxp/lpc_chip_43xx/inc/fpu_init.h" /> + <file file_name="../../../../../hw/mcu/nxp/lpc_chip_43xx/inc/gpio_18xx_43xx.h" /> + <file file_name="../../../../../hw/mcu/nxp/lpc_chip_43xx/inc/i2c_18xx_43xx.h" /> + <file file_name="../../../../../hw/mcu/nxp/lpc_chip_43xx/inc/i2c_common_18xx_43xx.h" /> + <file file_name="../../../../../hw/mcu/nxp/lpc_chip_43xx/inc/i2cm_18xx_43xx.h" /> + <file file_name="../../../../../hw/mcu/nxp/lpc_chip_43xx/inc/lpc_types.h" /> + <file file_name="../../../../../hw/mcu/nxp/lpc_chip_43xx/inc/packing.h" /> + <file file_name="../../../../../hw/mcu/nxp/lpc_chip_43xx/inc/uart_18xx_43xx.h" /> + <file file_name="../../../../../hw/mcu/nxp/lpc_chip_43xx/inc/usbhs_18xx_43xx.h" /> + <folder Name="config_43xx"> + <file file_name="../../../../../hw/mcu/nxp/lpc_chip_43xx/inc/config_43xx/cmsis_43xx.h" /> + <file file_name="../../../../../hw/mcu/nxp/lpc_chip_43xx/inc/config_43xx/sys_config.h" /> </folder> </folder> + <folder Name="src"> + <file file_name="../../../../../hw/mcu/nxp/lpc_chip_43xx/src/chip_18xx_43xx.c" /> + <file file_name="../../../../../hw/mcu/nxp/lpc_chip_43xx/src/clock_18xx_43xx.c" /> + <file file_name="../../../../../hw/mcu/nxp/lpc_chip_43xx/src/fpu_init.c" /> + <file file_name="../../../../../hw/mcu/nxp/lpc_chip_43xx/src/gpio_18xx_43xx.c" /> + <file file_name="../../../../../hw/mcu/nxp/lpc_chip_43xx/src/i2c_18xx_43xx.c" /> + <file file_name="../../../../../hw/mcu/nxp/lpc_chip_43xx/src/i2cm_18xx_43xx.c" /> + <file file_name="../../../../../hw/mcu/nxp/lpc_chip_43xx/src/sysinit_18xx_43xx.c" /> + <file file_name="../../../../../hw/mcu/nxp/lpc_chip_43xx/src/uart_18xx_43xx.c" /> + </folder> </folder> </folder> </folder> diff --git a/examples/device/cdc_msc_hid/ses/nrf5x/nrf5x.emProject b/examples/device/cdc_msc_hid/ses/nrf5x/nrf5x.emProject index b16c43efa..de2a6a78d 100644 --- a/examples/device/cdc_msc_hid/ses/nrf5x/nrf5x.emProject +++ b/examples/device/cdc_msc_hid/ses/nrf5x/nrf5x.emProject @@ -23,6 +23,7 @@ c_user_include_directories="../../src;$(rootDir)/hw/cmsis/Include;$(rootDir)/hw;$(rootDir)/src;$(nrfxDir)/..;$(nrfxDir);$(nrfxDir)/mdk;$(nrfxDir)/hal;$(nrfxDir)/drivers/include" debug_register_definition_file="nrf52840_Registers.xml" debug_target_connection="J-Link" + gcc_enable_all_warnings="Yes" gcc_entry_point="Reset_Handler" link_use_linker_script_file="No" linker_memory_map_file="nRF52840_xxAA_MemoryMap.xml" @@ -104,6 +105,7 @@ filter="*.c;*.h" path="../../../../../lib/segger_rtt" recurse="No" /> + <configuration Name="pca10056" build_treat_warnings_as_errors="No" /> </project> <configuration Name="pca10056" /> </solution> diff --git a/examples/device/cdc_msc_hid/ses/samd21/samd21.emProject b/examples/device/cdc_msc_hid/ses/samd21/samd21.emProject index a6a439970..4452699ef 100644 --- a/examples/device/cdc_msc_hid/ses/samd21/samd21.emProject +++ b/examples/device/cdc_msc_hid/ses/samd21/samd21.emProject @@ -19,9 +19,10 @@ arm_target_interface_type="SWD" build_treat_warnings_as_errors="Yes" c_preprocessor_definitions="__SAMD21G18A__;__SAMD21_FAMILY;__SAM_D21_SUBFAMILY;ARM_MATH_CM0PLUS;FLASH_PLACEMENT=1;USE_SIMPLE_ASSERT;CONF_XOSC32K_CONFIG=1;CONF_OSC32K_ENABLE=1;CONF_OSC32K_EN32K=1;CONF_XOSC32K_STARTUP=CONF_XOSC32K_STARTUP_TIME_2000092MCS;CONF_DFLL_ONDEMAND=0;CONF_DFLL_OVERWRITE_CALIBRATION=0;BOARD_METRO_M0_EXPRESS;CFG_TUSB_MCU=OPT_MCU_SAMD21" - c_user_include_directories="../../src;$(rootDir)/hw/cmsis/Include;$(rootDir)/hw;$(rootDir)/src;$(asf4Dir);$(asf4Dir)/include;$(asf4Dir)/config;$(asf4Dir)/hri;$(asf4Dir)/hal/include;$(asf4Dir)/hal/utils/include;$(asf4Dir)/hpl/port;$(asf4Dir)/hpl/gclk;$(asf4Dir)/hpl/pm" + c_user_include_directories="../../src;$(rootDir)/hw;$(rootDir)/src;$(asf4Dir);$(asf4Dir)/CMSIS/Include;$(asf4Dir)/include;$(asf4Dir)/config;$(asf4Dir)/hri;$(asf4Dir)/hal/include;$(asf4Dir)/hal/utils/include;$(asf4Dir)/hpl/port;$(asf4Dir)/hpl/gclk;$(asf4Dir)/hpl/pm" debug_register_definition_file="ATSAMD21G18A_Registers.xml" debug_target_connection="J-Link" + gcc_enable_all_warnings="Yes" gcc_entry_point="Reset_Handler" link_use_linker_script_file="No" linker_memory_map_file="$(ProjectDir)/ATSAMD21G18A_MemoryMap.xml" @@ -57,9 +58,6 @@ <file file_name="../../../../../hw/mcu/microchip/samd/asf4/samd21/gcc/system_samd21.c" /> </folder> <folder Name="hpl"> - <folder Name="core"> - <file file_name="../../../../../hw/mcu/microchip/samd/asf4/samd21/hpl/core/hpl_init.c" /> - </folder> <folder Name="gclk"> <file file_name="../../../../../hw/mcu/microchip/samd/asf4/samd21/hpl/gclk/hpl_gclk.c" /> </folder> diff --git a/examples/device/cdc_msc_hid/ses/samd51/samd51.emProject b/examples/device/cdc_msc_hid/ses/samd51/samd51.emProject index 260d452f7..6d5c14507 100644 --- a/examples/device/cdc_msc_hid/ses/samd51/samd51.emProject +++ b/examples/device/cdc_msc_hid/ses/samd51/samd51.emProject @@ -20,9 +20,10 @@ arm_target_interface_type="SWD" build_treat_warnings_as_errors="Yes" c_preprocessor_definitions="__SAMD51_FAMILY;__SAMD51J19A__;ARM_MATH_CM4;FLASH_PLACEMENT=1;USE_SIMPLE_ASSERT;BOARD_METRO_M4_EXPRESS;CFG_TUSB_MCU=OPT_MCU_SAMD51" - c_user_include_directories="../../src;$(rootDir)/hw/cmsis/Include;$(rootDir)/hw;$(rootDir)/src;$(asf4Dir);$(asf4Dir)/include;$(asf4Dir)/config;$(asf4Dir)/hri;$(asf4Dir)/hal/include;$(asf4Dir)/hal/utils/include;$(asf4Dir)/hpl/port;$(asf4Dir)/hpl/gclk" + c_user_include_directories="../../src;$(rootDir)/hw;$(rootDir)/src;$(asf4Dir);$(asf4Dir)/CMSIS/Include;$(asf4Dir)/include;$(asf4Dir)/config;$(asf4Dir)/hri;$(asf4Dir)/hal/include;$(asf4Dir)/hal/utils/include;$(asf4Dir)/hpl/port;$(asf4Dir)/hpl/gclk" debug_register_definition_file="ATSAMD51J19A_Registers.xml" debug_target_connection="J-Link" + gcc_enable_all_warnings="Yes" gcc_entry_point="Reset_Handler" link_use_linker_script_file="No" linker_memory_map_file="ATSAMD51J19A_MemoryMap.xml" @@ -58,9 +59,6 @@ <file file_name="../../../../../hw/mcu/microchip/samd/asf4/samd51/gcc/system_samd51.c" /> </folder> <folder Name="hpl"> - <folder Name="core"> - <file file_name="../../../../../hw/mcu/microchip/samd/asf4/samd51/hpl/core/hpl_init.c" /> - </folder> <folder Name="osc32kctrl"> <file file_name="../../../../../hw/mcu/microchip/samd/asf4/samd51/hpl/osc32kctrl/hpl_osc32kctrl.c" /> </folder> diff --git a/examples/device/cdc_msc_hid/src/main.c b/examples/device/cdc_msc_hid/src/main.c index 9d3e088cf..20b7dd12b 100644 --- a/examples/device/cdc_msc_hid/src/main.c +++ b/examples/device/cdc_msc_hid/src/main.c @@ -46,7 +46,6 @@ //--------------------------------------------------------------------+ // MACRO CONSTANT TYPEDEF PROTYPES //--------------------------------------------------------------------+ -void print_greeting(void); void led_blinking_task(void); extern void virtual_com_task(void); @@ -56,13 +55,13 @@ extern void usb_hid_task(void); int main(void) { board_init(); - print_greeting(); tusb_init(); while (1) { - tusb_task(); + // tinyusb device task + tud_task(); led_blinking_task(); @@ -84,9 +83,9 @@ int main(void) #if CFG_TUD_CDC void virtual_com_task(void) { - // connected and there are data available if ( tud_cdc_connected() ) { + // connected and there are data available if ( tud_cdc_available() ) { uint8_t buf[64]; @@ -94,10 +93,15 @@ void virtual_com_task(void) // read and echo back uint32_t count = tud_cdc_read(buf, sizeof(buf)); - tud_cdc_write(buf, count); - } + for(uint32_t i=0; i<count; i++) + { + tud_cdc_write_char(buf[i]); + + if ( buf[i] == '\r' ) tud_cdc_write_char('\n'); + } - tud_cdc_write_flush(); + tud_cdc_write_flush(); + } } } @@ -108,8 +112,8 @@ void tud_cdc_line_state_cb(uint8_t itf, bool dtr, bool rts) // connected if ( dtr && rts ) { - // print greeting - tud_cdc_write_str("tinyusb usb cdc\n"); + // print initial message when connected + tud_cdc_write_str("\r\nTinyUSB CDC MSC HID device example\r\n"); } } #endif @@ -187,6 +191,7 @@ void tud_umount_cb(void) void tud_cdc_rx_cb(uint8_t itf) { + (void) itf; } //--------------------------------------------------------------------+ @@ -200,31 +205,6 @@ void led_blinking_task(void) if ( !tu_timeout_expired(&tm) ) return; // not enough time tu_timeout_reset(&tm); - board_led_control(BOARD_LED0, led_state); + board_led_control(led_state); led_state = 1 - led_state; // toggle } - -//--------------------------------------------------------------------+ -// HELPER FUNCTION -//--------------------------------------------------------------------+ -void print_greeting(void) -{ - char const * const rtos_name[] = - { - [OPT_OS_NONE] = "None", - [OPT_OS_FREERTOS] = "FreeRTOS", - }; - - printf("\n--------------------------------------------------------------------\n"); - printf("- Device Demo (a tinyusb example)\n"); - printf("- if you find any bugs or get any questions, feel free to file an\n"); - printf("- issue at https://github.com/hathach/tinyusb\n"); - printf("--------------------------------------------------------------------\n\n"); - - printf("This DEVICE demo is configured to support:"); - printf(" - RTOS = %s\n", rtos_name[CFG_TUSB_OS]); - if (CFG_TUD_CDC ) puts(" - Communication Device Class"); - if (CFG_TUD_MSC ) puts(" - Mass Storage"); - if (CFG_TUD_HID_KEYBOARD ) puts(" - HID Keyboard"); - if (CFG_TUD_HID_MOUSE ) puts(" - HID Mouse"); -} diff --git a/examples/device/cdc_msc_hid/src/msc_disk_ram.c b/examples/device/cdc_msc_hid/src/msc_disk_ram.c index 08cef5f25..98d3f5adb 100644 --- a/examples/device/cdc_msc_hid/src/msc_disk_ram.c +++ b/examples/device/cdc_msc_hid/src/msc_disk_ram.c @@ -41,6 +41,12 @@ #if CFG_TUD_MSC +// Some MCU doesn't have enough 8KB SRAM to store the whole disk +// We will use Flash as read-only disk +#if CFG_TUSB_MCU == OPT_MCU_LPC13XX +#define DISK_READONLY +#endif + #define README_CONTENTS \ "This is tinyusb's MassStorage Class demo.\r\n\r\n\ If you find any bugs or get any questions, feel free to file an\r\n\ @@ -52,7 +58,10 @@ enum DISK_BLOCK_SIZE = 512 }; -uint8_t msc_device_ramdisk[DISK_BLOCK_NUM][DISK_BLOCK_SIZE] = +#ifdef DISK_READONLY +const +#endif +uint8_t msc_disk[DISK_BLOCK_NUM][DISK_BLOCK_SIZE] = { //------------- Boot Sector -------------// // byte_per_sector = DISK_BLOCK_SIZE; fat12_sector_num_16 = DISK_BLOCK_NUM; @@ -99,7 +108,7 @@ int32_t tud_msc_read10_cb(uint8_t lun, uint32_t lba, uint32_t offset, void* buff { (void) lun; - uint8_t* addr = msc_device_ramdisk[lba] + offset; + uint8_t const* addr = msc_disk[lba] + offset; memcpy(buffer, addr, bufsize); return bufsize; @@ -111,8 +120,12 @@ int32_t tud_msc_write10_cb(uint8_t lun, uint32_t lba, uint32_t offset, uint8_t* { (void) lun; - uint8_t* addr = msc_device_ramdisk[lba] + offset; +#ifndef DISK_READONLY + uint8_t* addr = msc_disk[lba] + offset; memcpy(addr, buffer, bufsize); +#else + (void) lba; (void) offset; (void) buffer; +#endif return bufsize; } diff --git a/examples/device/cdc_msc_hid/src/tusb_config.h b/examples/device/cdc_msc_hid/src/tusb_config.h index 70a08567f..c190f26c5 100644 --- a/examples/device/cdc_msc_hid/src/tusb_config.h +++ b/examples/device/cdc_msc_hid/src/tusb_config.h @@ -39,9 +39,6 @@ #ifndef _TUSB_CONFIG_H_ #define _TUSB_CONFIG_H_ -#include "tusb_option.h" -#include "bsp/board.h" - #ifdef __cplusplus extern "C" { #endif @@ -52,10 +49,15 @@ // defined by compiler flags for flexibility #ifndef CFG_TUSB_MCU - #error CFG_TUSB_MCU should be defined using compiler flags + #error CFG_TUSB_MCU must be defined #endif +#if CFG_TUSB_MCU == OPT_MCU_LPC43XX || CFG_TUSB_MCU == OPT_MCU_LPC18XX +#define CFG_TUSB_RHPORT0_MODE (OPT_MODE_DEVICE | OPT_MODE_HIGH_SPEED) +#else #define CFG_TUSB_RHPORT0_MODE OPT_MODE_DEVICE +#endif + #define CFG_TUSB_DEBUG 2 #define CFG_TUSB_OS OPT_OS_NONE @@ -88,12 +90,22 @@ */ #define CFG_TUD_DESC_AUTO 1 -/* USB VID/PID if not defined, tinyusb to use default value +/* If USB VID/PID is not defined, tinyusb will use default value * Note: different class combination e.g CDC and (CDC + MSC) should have different * PID since Host OS will "remembered" device driver after the first plug */ // #define CFG_TUD_DESC_VID 0xCAFE // #define CFG_TUD_DESC_PID 0x0001 +// LPC 17xx and 40xx endpoint type (bulk/interrupt/iso) are fixed by its number +// Therefor we need to force endpoint number to correct type on lpc17xx +#if CFG_TUSB_MCU == OPT_MCU_LPC175X_6X || CFG_TUSB_MCU == OPT_MCU_LPC177X_8X || CFG_TUSB_MCU == OPT_MCU_LPC40XX +#define CFG_TUD_DESC_CDC_EPNUM_NOTIF 1 +#define CFG_TUD_DESC_CDC_EPNUM 2 +#define CFG_TUD_DESC_MSC_EPNUM 5 +#define CFG_TUD_DESC_HID_KEYBOARD_EPNUM 4 +#define CFG_TUD_DESC_HID_MOUSE_EPNUM 7 +#endif + //------------- CLASS -------------// #define CFG_TUD_CDC 1 #define CFG_TUD_MSC 0 @@ -109,7 +121,6 @@ #define CFG_TUD_HID_KEYBOARD_BOOT 1 #define CFG_TUD_HID_MOUSE_BOOT 1 - //-------------------------------------------------------------------- // CDC //-------------------------------------------------------------------- @@ -121,7 +132,6 @@ //-------------------------------------------------------------------- // MSC //-------------------------------------------------------------------- - // Number of supported Logical Unit Number (At least 1) #define CFG_TUD_MSC_MAXLUN 1 diff --git a/examples/device/cdc_msc_hid_freertos/ses/cdc_msc_hid_freertos.emProject b/examples/device/cdc_msc_hid_freertos/ses/cdc_msc_hid_freertos.emProject index d666ec949..acd8e98c2 100644 --- a/examples/device/cdc_msc_hid_freertos/ses/cdc_msc_hid_freertos.emProject +++ b/examples/device/cdc_msc_hid_freertos/ses/cdc_msc_hid_freertos.emProject @@ -3,4 +3,5 @@ <import file_name="nrf5x/nrf5x.emProject" /> <import file_name="samd21/samd21.emProject" /> <import file_name="samd51/samd51.emProject" /> + <import file_name="lpc175x_6x/lpc175x_6x.emProject" /> </solution> diff --git a/examples/device/cdc_msc_hid_freertos/ses/lpc175x_6x/FreeRTOSConfig.h b/examples/device/cdc_msc_hid_freertos/ses/lpc175x_6x/FreeRTOSConfig.h new file mode 100644 index 000000000..0fad1dc89 --- /dev/null +++ b/examples/device/cdc_msc_hid_freertos/ses/lpc175x_6x/FreeRTOSConfig.h @@ -0,0 +1,134 @@ +#ifndef __FREERTOS_CONFIG__H +#define __FREERTOS_CONFIG__H + +//--------------------------------------------------------------------+ +// See http://www.freertos.org/a00110.html. +//--------------------------------------------------------------------+ +#include "LPC17xx.h" + +#define configCPU_CLOCK_HZ SystemCoreClock + +#if 0 +#if CFG_TUSB_MCU == OPT_MCU_LPC43XX + // TODO remove + #include "lpc43xx_cgu.h" + #define configCPU_CLOCK_HZ CGU_GetPCLKFrequency(CGU_PERIPHERAL_M4CORE) +#endif +#endif + +#define configUSE_PREEMPTION 1 +#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 +#define configTICK_RATE_HZ ( 1000 ) +#define configMAX_PRIORITIES (8) +#define configMINIMAL_STACK_SIZE (128 ) +#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 16*1024 ) ) +#define configMAX_TASK_NAME_LEN 32 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 1 +#define configUSE_MUTEXES 1 +#define configUSE_RECURSIVE_MUTEXES 0 +#define configUSE_COUNTING_SEMAPHORES 1 +#define configQUEUE_REGISTRY_SIZE 10 // used to name queue/semaphore with debugger +#define configUSE_QUEUE_SETS 0 +#define configUSE_TIME_SLICING 0 +#define configUSE_NEWLIB_REENTRANT 0 +#define configENABLE_BACKWARD_COMPATIBILITY 1 + +#define configSUPPORT_STATIC_ALLOCATION 1 +#define configSUPPORT_DYNAMIC_ALLOCATION 1 + +/* Hook function related definitions. */ +#define configUSE_IDLE_HOOK 0 +#define configUSE_TICK_HOOK 0 +#define configUSE_MALLOC_FAILED_HOOK 1 +#define configCHECK_FOR_STACK_OVERFLOW 2 + +/* Run time and task stats gathering related definitions. */ +#define configGENERATE_RUN_TIME_STATS 0 +#define configUSE_TRACE_FACILITY 1 // legacy trace +#define configUSE_STATS_FORMATTING_FUNCTIONS 0 + +/* Co-routine definitions. */ +#define configUSE_CO_ROUTINES 0 +#define configMAX_CO_ROUTINE_PRIORITIES 2 + +/* Software timer related definitions. */ +#define configUSE_TIMERS 1 +#define configTIMER_TASK_PRIORITY ( configMAX_PRIORITIES - 3 ) +#define configTIMER_QUEUE_LENGTH 10 +#define configTIMER_TASK_STACK_DEPTH configMINIMAL_STACK_SIZE + +/* Optional functions - most linkers will remove unused functions anyway. */ +#define INCLUDE_vTaskPrioritySet 0 +#define INCLUDE_uxTaskPriorityGet 0 +#define INCLUDE_vTaskDelete 0 +#define INCLUDE_vTaskSuspend 1 // required for queue, semaphore, mutex to be blocked indefinitely with portMAX_DELAY +#define INCLUDE_xResumeFromISR 0 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 +#define INCLUDE_xTaskGetSchedulerState 0 +#define INCLUDE_xTaskGetCurrentTaskHandle 0 +#define INCLUDE_uxTaskGetStackHighWaterMark 0 +#define INCLUDE_xTaskGetIdleTaskHandle 0 +#define INCLUDE_xTimerGetTimerDaemonTaskHandle 0 +#define INCLUDE_pcTaskGetTaskName 0 +#define INCLUDE_eTaskGetState 0 +#define INCLUDE_xEventGroupSetBitFromISR 0 +#define INCLUDE_xTimerPendFunctionCall 0 + +/* Define to trap errors during development. */ + +// Halt CPU (breakpoint) when hitting error, only apply for Cortex M3, M4, M7 +#if defined(__ARM_ARCH_7M__) || defined (__ARM_ARCH_7EM__) + +static inline void configASSERT_breakpoint(void) +{ + // Cortex M CoreDebug->DHCSR + volatile uint32_t* ARM_CM_DHCSR = ((volatile uint32_t*) 0xE000EDF0UL); + + // Only halt mcu if debugger is attached + if ( (*ARM_CM_DHCSR) & 1UL ) __asm("BKPT #0\n"); +} + +#else +#define configASSERT_breakpoint() +#endif + + +#define configASSERT( x ) if( ( x ) == 0 ) { taskDISABLE_INTERRUPTS(); configASSERT_breakpoint(); } + +/* FreeRTOS hooks to NVIC vectors */ +#define xPortPendSVHandler PendSV_Handler +#define xPortSysTickHandler SysTick_Handler +#define vPortSVCHandler SVC_Handler + +//--------------------------------------------------------------------+ +// Interrupt nesting behaviour configuration. +//--------------------------------------------------------------------+ +/* Cortex-M specific definitions. __NVIC_PRIO_BITS is defined in mcu_variant.h */ +#ifdef __NVIC_PRIO_BITS + #define configPRIO_BITS __NVIC_PRIO_BITS +#else + #error "This port requires __NVIC_PRIO_BITS to be defined" +#endif + + +/* The lowest interrupt priority that can be used in a call to a "set priority" +function. */ +#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY 0x1f + +/* The highest interrupt priority that can be used by any interrupt service +routine that makes calls to interrupt safe FreeRTOS API functions. DO NOT CALL +INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER +PRIORITY THAN THIS! (higher priorities are lower numeric values. */ +#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 2 + +/* Interrupt priorities used by the kernel port layer itself. These are generic +to all Cortex-M ports, and do not rely on any particular library functions. */ +#define configKERNEL_INTERRUPT_PRIORITY ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) ) + +/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!! +See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */ +#define configMAX_SYSCALL_INTERRUPT_PRIORITY ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) ) + +#endif /* __FREERTOS_CONFIG__H */ diff --git a/examples/device/cdc_msc_hid_freertos/ses/lpc175x_6x/LPC1700_Startup.s b/examples/device/cdc_msc_hid_freertos/ses/lpc175x_6x/LPC1700_Startup.s new file mode 100644 index 000000000..f039ad934 --- /dev/null +++ b/examples/device/cdc_msc_hid_freertos/ses/lpc175x_6x/LPC1700_Startup.s @@ -0,0 +1,109 @@ +/***************************************************************************** + * SEGGER Microcontroller GmbH & Co. KG * + * Solutions for real time microcontroller applications * + ***************************************************************************** + * * + * (c) 2015 SEGGER Microcontroller GmbH & Co. KG * + * * + * Internet: www.segger.com Support: [email protected] * + * * + *****************************************************************************/ + +/***************************************************************************** + * Preprocessor Definitions * + * ------------------------ * + * NO_STACK_INIT * + * * + * If defined, the stack pointer will not be initialised. * + * * + * NO_SYSTEM_INIT * + * * + * If defined, the SystemInit() function will not be called. By default * + * SystemInit() is called after reset to enable the clocks and memories to * + * be initialised prior to any C startup initialisation. * + * * + * NO_VTOR_CONFIG * + * * + * If defined, the vector table offset register will not be configured. * + * * + * MEMORY_INIT * + * * + * If defined, the MemoryInit() function will be called. By default * + * MemoryInit() is called after SystemInit() to enable an external memory * + * controller. * + * * + * STACK_INIT_VAL * + * * + * If defined, specifies the initial stack pointer value. If undefined, * + * the stack pointer will be initialised to point to the end of the * + * RAM segment. * + * * + * VECTORS_IN_RAM * + * * + * If defined, the exception vectors will be copied from Flash to RAM. * + * * + *****************************************************************************/ + + .syntax unified + + .global Reset_Handler + .extern _vectors + + .section .init, "ax" + .thumb_func + + .equ VTOR_REG, 0xE000ED08 + +#ifndef STACK_INIT_VAL +#define STACK_INIT_VAL __RAM_segment_end__ +#endif + +Reset_Handler: +#ifndef NO_STACK_INIT + /* Initialise main stack */ + ldr r0, =STACK_INIT_VAL + bic r0, #0x7 + mov sp, r0 +#endif +#ifndef NO_SYSTEM_INIT + /* Initialise system */ + ldr r0, =SystemInit + blx r0 +#endif + +#ifdef MEMORY_INIT + ldr r0, =MemoryInit + blx r0 +#endif + +#ifdef VECTORS_IN_RAM + /* Copy exception vectors into RAM */ + ldr r0, =__vectors_start__ + ldr r1, =__vectors_end__ + ldr r2, =__vectors_ram_start__ +1: + cmp r0, r1 + beq 2f + ldr r3, [r0] + str r3, [r2] + adds r0, r0, #4 + adds r2, r2, #4 + b 1b +2: +#endif + +#ifndef NO_VTOR_CONFIG + /* Configure vector table offset register */ + ldr r0, =VTOR_REG +#ifdef VECTORS_IN_RAM + ldr r1, =_vectors_ram +#else + ldr r1, =_vectors +#endif + str r1, [r0] +#endif + + /* Jump to program start */ + b _start + + diff --git a/examples/device/cdc_msc_hid_freertos/ses/lpc175x_6x/LPC1700_Target.js b/examples/device/cdc_msc_hid_freertos/ses/lpc175x_6x/LPC1700_Target.js new file mode 100644 index 000000000..7f945a3d2 --- /dev/null +++ b/examples/device/cdc_msc_hid_freertos/ses/lpc175x_6x/LPC1700_Target.js @@ -0,0 +1,19 @@ +/***************************************************************************** + * SEGGER Microcontroller GmbH & Co. KG * + * Solutions for real time microcontroller applications * + ***************************************************************************** + * * + * (c) 2015 SEGGER Microcontroller GmbH & Co. KG * + * * + * Internet: www.segger.com Support: [email protected] * + * * + *****************************************************************************/ + +function Reset() { + TargetInterface.resetAndStop(); +} + +function EnableTrace(traceInterfaceType) { + // TODO: Enable trace +} + diff --git a/examples/device/cdc_msc_hid_freertos/ses/lpc175x_6x/LPC1769_MemoryMap.xml b/examples/device/cdc_msc_hid_freertos/ses/lpc175x_6x/LPC1769_MemoryMap.xml new file mode 100644 index 000000000..d9c07aea3 --- /dev/null +++ b/examples/device/cdc_msc_hid_freertos/ses/lpc175x_6x/LPC1769_MemoryMap.xml @@ -0,0 +1,6 @@ +<!DOCTYPE Board_Memory_Definition_File> +<root name="LPC1769"> + <MemorySegment name="FLASH" start="0x00000000" size="0x00080000" access="ReadOnly" /> + <MemorySegment name="RAM" start="0x10000000" size="0x00008000" access="Read/Write" /> + <MemorySegment name="RAM2" start="0x2007C000" size="0x00008000" access="Read/Write" /> +</root> diff --git a/examples/device/cdc_msc_hid_freertos/ses/lpc175x_6x/LPC176x5x_Registers.xml b/examples/device/cdc_msc_hid_freertos/ses/lpc175x_6x/LPC176x5x_Registers.xml new file mode 100644 index 000000000..fd38966b8 --- /dev/null +++ b/examples/device/cdc_msc_hid_freertos/ses/lpc175x_6x/LPC176x5x_Registers.xml @@ -0,0 +1,11058 @@ +<!DOCTYPE Register_Definition_File> +<Processor name="LPC176x5x" description="LPC176x/LPC175x M3"> + <RegisterGroup name="WDT" start="0x40000000" description="Watchdog Timer (WDT) "> + <Register start="+0x000" size="4" name="MOD" access="Read/Write" description="Watchdog mode register. This register determines the basic mode and status of the Watchdog Timer." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="WDEN" description="Watchdog enable bit. This bit is Set Only."> + <Enum name="STOP" start="0" description="The watchdog timer is stopped." /> + <Enum name="RUN" start="1" description="The watchdog timer is running." /> + </BitField> + <BitField start="1" size="1" name="WDRESET" description="Watchdog reset enable bit. This bit is Set Only. See Table 652."> + <Enum name="NORESET" start="0" description="A watchdog timeout will not cause a chip reset." /> + <Enum name="RESET" start="1" description="A watchdog timeout will cause a chip reset." /> + </BitField> + <BitField start="2" size="1" name="WDTOF" description="Watchdog time-out flag. Set when the watchdog timer times out, cleared by software." /> + <BitField start="3" size="1" name="WDINT" description="Watchdog interrupt flag. Cleared by software." /> + <BitField start="4" size="28" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x004" size="4" name="TC" access="Read/Write" description="Watchdog timer constant register. The value in this register determines the time-out value." reset_value="0xFF" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="Count" description="Watchdog time-out interval." /> + </Register> + <Register start="+0x008" size="4" name="FEED" access="WriteOnly" description="Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in WDTC." reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="8" name="Feed" description="Feed value should be 0xAA followed by 0x55." /> + </Register> + <Register start="+0x00C" size="4" name="TV" access="ReadOnly" description="Watchdog timer value register. This register reads out the current value of the Watchdog timer." reset_value="0xFF" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="Count" description="Counter timer value." /> + </Register> + <Register start="+0x010" size="4" name="CLKSEL" access="Read/Write" description="Watchdog clock select register." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="CLKSEL" description="Selects source of WDT clock"> + <Enum name="IRC" start="0x0" description="IRC" /> + <Enum name="PCLK" start="0x1" description="Peripheral clock" /> + <Enum name="RTCOSC" start="0x2" description="RTC oscillator" /> + </BitField> + <BitField start="1" size="30" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + <BitField start="31" size="1" name="LOCK" description="If this bit is set to one writing to this register does not affect bit 0. The clock source can only be changed by first clearing this bit, then writing the new value of bit 0."> + <Enum name="UNLOCKED" start="0" description="This bit is set to 0 on any reset. It cannot be cleared by software." /> + <Enum name="LOCKED" start="1" description="Software can set this bit to 1 at any time. Once WDLOCK is set, the bits of this register
										cannot be modified." /> + </BitField> + </Register> + </RegisterGroup> + <RegisterGroup name="TIMER0" start="0x40004000" description="Timer0/1/2/3 "> + <Register start="+0x000" size="4" name="IR" access="Read/Write" description="Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="MR0INT" description="Interrupt flag for match channel 0." /> + <BitField start="1" size="1" name="MR1INT" description="Interrupt flag for match channel 1." /> + <BitField start="2" size="1" name="MR2INT" description="Interrupt flag for match channel 2." /> + <BitField start="3" size="1" name="MR3INT" description="Interrupt flag for match channel 3." /> + <BitField start="4" size="1" name="CR0INT" description="Interrupt flag for capture channel 0 event." /> + <BitField start="5" size="1" name="CR1INT" description="Interrupt flag for capture channel 1 event." /> + <BitField start="6" size="26" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x004" size="4" name="TCR" access="Read/Write" description="Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="CEN" description="When one, the Timer Counter and Prescale Counter are enabled for counting. When zero, the counters are disabled." /> + <BitField start="1" size="1" name="CRST" description="When one, the Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero." /> + <BitField start="2" size="30" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x008" size="4" name="TC" access="Read/Write" description="Timer Counter. The 32 bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="TC" description="Timer counter value." /> + </Register> + <Register start="+0x00C" size="4" name="PR" access="Read/Write" description="Prescale Register. When the Prescale Counter (PC) is equal to this value, the next clock increments the TC and clears the PC." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="PM" description="Prescale counter maximum value." /> + </Register> + <Register start="+0x010" size="4" name="PC" access="Read/Write" description="Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="PC" description="Prescale counter value." /> + </Register> + <Register start="+0x014" size="4" name="MCR" access="Read/Write" description="Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="MR0I" description="Interrupt on MR0"> + <Enum name="INTERRUPT_IS_GENERAT" start="1" description="Interrupt is generated when MR0 matches the value in the TC." /> + <Enum name="INTERRUPT_IS_DISABLE" start="0" description="Interrupt is disabled" /> + </BitField> + <BitField start="1" size="1" name="MR0R" description="Reset on MR0"> + <Enum name="TC_WILL_BE_RESET_IF_" start="1" description="TC will be reset if MR0 matches it." /> + <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." /> + </BitField> + <BitField start="2" size="1" name="MR0S" description="Stop on MR0"> + <Enum name="TC_AND_PC_WILL_BE_ST" start="1" description="TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC." /> + <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." /> + </BitField> + <BitField start="3" size="1" name="MR1I" description="Interrupt on MR1"> + <Enum name="INTERRUPT_IS_GENERAT" start="1" description="Interrupt is generated when MR1 matches the value in the TC." /> + <Enum name="INTERRUPT_IS_DISABLE" start="0" description="Interrupt is disabled." /> + </BitField> + <BitField start="4" size="1" name="MR1R" description="Reset on MR1"> + <Enum name="TC_WILL_BE_RESET_IF_" start="1" description="TC will be reset if MR1 matches it." /> + <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." /> + </BitField> + <BitField start="5" size="1" name="MR1S" description="Stop on MR1"> + <Enum name="TC_AND_PC_WILL_BE_ST" start="1" description="TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC." /> + <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." /> + </BitField> + <BitField start="6" size="1" name="MR2I" description="Interrupt on MR2"> + <Enum name="INTERRUPT_IS_GENERAT" start="1" description="Interrupt is generated when MR2 matches the value in the TC." /> + <Enum name="INTERRUPT_IS_DISABLE" start="0" description="Interrupt is disabled" /> + </BitField> + <BitField start="7" size="1" name="MR2R" description="Reset on MR2"> + <Enum name="TC_WILL_BE_RESET_IF_" start="1" description="TC will be reset if MR2 matches it." /> + <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." /> + </BitField> + <BitField start="8" size="1" name="MR2S" description="Stop on MR2."> + <Enum name="TC_AND_PC_WILL_BE_ST" start="1" description="TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC" /> + <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." /> + </BitField> + <BitField start="9" size="1" name="MR3I" description="Interrupt on MR3"> + <Enum name="INTERRUPT_IS_GENERAT" start="1" description="Interrupt is generated when MR3 matches the value in the TC." /> + <Enum name="THIS_INTERRUPT_IS_DI" start="0" description="This interrupt is disabled" /> + </BitField> + <BitField start="10" size="1" name="MR3R" description="Reset on MR3"> + <Enum name="TC_WILL_BE_RESET_IF_" start="1" description="TC will be reset if MR3 matches it." /> + <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." /> + </BitField> + <BitField start="11" size="1" name="MR3S" description="Stop on MR3"> + <Enum name="TC_AND_PC_WILL_BE_ST" start="1" description="TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC." /> + <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." /> + </BitField> + <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x018+0" size="4" name="MR[0]" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="MATCH" description="Timer counter match value." /> + </Register> + <Register start="+0x018+4" size="4" name="MR[1]" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="MATCH" description="Timer counter match value." /> + </Register> + <Register start="+0x018+8" size="4" name="MR[2]" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="MATCH" description="Timer counter match value." /> + </Register> + <Register start="+0x018+12" size="4" name="MR[3]" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="MATCH" description="Timer counter match value." /> + </Register> + <Register start="+0x028" size="4" name="CCR" access="Read/Write" description="Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="CAP0RE" description="Capture on CAPn.0 rising edge"> + <Enum name="ENABLE" start="1" description="A sequence of 0 then 1 on CAPn.0 will cause CR0 to be loaded with the contents of TC." /> + <Enum name="DISABLE" start="0" description="This feature is disabled." /> + </BitField> + <BitField start="1" size="1" name="CAP0FE" description="Capture on CAPn.0 falling edge"> + <Enum name="ENABLE" start="1" description="A sequence of 1 then 0 on CAPn.0 will cause CR0 to be loaded with the contents of TC." /> + <Enum name="DISABLE" start="0" description="This feature is disabled." /> + </BitField> + <BitField start="2" size="1" name="CAP0I" description="Interrupt on CAPn.0 event"> + <Enum name="ENABLE" start="1" description="A CR0 load due to a CAPn.0 event will generate an interrupt." /> + <Enum name="DISABLE" start="0" description="This feature is disabled." /> + </BitField> + <BitField start="3" size="1" name="CAP1RE" description="Capture on CAPn.1 rising edge"> + <Enum name="ENABLE" start="1" description="A sequence of 0 then 1 on CAPn.1 will cause CR1 to be loaded with the contents of TC." /> + <Enum name="DISABLE" start="0" description="This feature is disabled." /> + </BitField> + <BitField start="4" size="1" name="CAP1FE" description="Capture on CAPn.1 falling edge"> + <Enum name="ENABLE" start="1" description="A sequence of 1 then 0 on CAPn.1 will cause CR1 to be loaded with the contents of TC." /> + <Enum name="DISABLE" start="0" description="This feature is disabled." /> + </BitField> + <BitField start="5" size="1" name="CAP1I" description="Interrupt on CAPn.1 event"> + <Enum name="ENABLE" start="1" description="A CR1 load due to a CAPn.1 event will generate an interrupt." /> + <Enum name="DISABLE" start="0" description="This feature is disabled." /> + </BitField> + <BitField start="6" size="26" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x02C+0" size="4" name="CR[0]" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CAP" description="Timer counter capture value." /> + </Register> + <Register start="+0x02C+4" size="4" name="CR[1]" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CAP" description="Timer counter capture value." /> + </Register> + <Register start="+0x03C" size="4" name="EMR" access="Read/Write" description="External Match Register. The EMR controls the external match pins." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="EM0" description="External Match 0. When a match occurs between the TC and MR0, this bit can either toggle, go low, go high, or do nothing, depending on bits 5:4 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." /> + <BitField start="1" size="1" name="EM1" description="External Match 1. When a match occurs between the TC and MR1, this bit can either toggle, go low, go high, or do nothing, depending on bits 7:6 of this register. This bit can be driven onto a MATn.1 pin, in a positive-logic manner (0 = low, 1 = high)." /> + <BitField start="2" size="1" name="EM2" description="External Match 2. When a match occurs between the TC and MR2, this bit can either toggle, go low, go high, or do nothing, depending on bits 9:8 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." /> + <BitField start="3" size="1" name="EM3" description="External Match 3. When a match occurs between the TC and MR3, this bit can either toggle, go low, go high, or do nothing, depending on bits 11:10 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." /> + <BitField start="4" size="2" name="EMC0" description="External Match Control 0. Determines the functionality of External Match 0."> + <Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." /> + <Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." /> + <Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." /> + <Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." /> + </BitField> + <BitField start="6" size="2" name="EMC1" description="External Match Control 1. Determines the functionality of External Match 1."> + <Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." /> + <Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." /> + <Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." /> + <Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." /> + </BitField> + <BitField start="8" size="2" name="EMC2" description="External Match Control 2. Determines the functionality of External Match 2."> + <Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." /> + <Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." /> + <Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." /> + <Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." /> + </BitField> + <BitField start="10" size="2" name="EMC3" description="External Match Control 3. Determines the functionality of External Match 3."> + <Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." /> + <Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." /> + <Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." /> + <Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." /> + </BitField> + <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x070" size="4" name="CTCR" access="Read/Write" description="Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="CTMODE" description="Counter/Timer Mode This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale Register."> + <Enum name="TIMER_MODE_EVERY_RI" start="0x0" description="Timer Mode: every rising PCLK edge" /> + <Enum name="RISING" start="0x1" description="Counter Mode: TC is incremented on rising edges on the CAP input selected by bits 3:2." /> + <Enum name="FALLING" start="0x2" description="Counter Mode: TC is incremented on falling edges on the CAP input selected by bits 3:2." /> + <Enum name="DUALEDGE" start="0x3" description="Counter Mode: TC is incremented on both edges on the CAP input selected by bits 3:2." /> + </BitField> + <BitField start="2" size="2" name="CINSEL" description="Count Input Select When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the TnCTCR, the 3 bits for that input in the Capture Control Register (TnCCR) must be programmed as 000. However, capture and/or interrupt can be selected for the other 3 CAPn inputs in the same timer."> + <Enum name="CAPN_0_FOR_TIMERN" start="0x0" description="CAPn.0 for TIMERn" /> + <Enum name="CAPN_1_FOR_TIMERN" start="0x1" description="CAPn.1 for TIMERn" /> + </BitField> + <BitField start="4" size="28" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + </RegisterGroup> + <RegisterGroup name="TIMER1" start="0x40008000" description="Timer0/1/2/3 "> + <Register start="+0x000" size="4" name="IR" access="Read/Write" description="Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="MR0INT" description="Interrupt flag for match channel 0." /> + <BitField start="1" size="1" name="MR1INT" description="Interrupt flag for match channel 1." /> + <BitField start="2" size="1" name="MR2INT" description="Interrupt flag for match channel 2." /> + <BitField start="3" size="1" name="MR3INT" description="Interrupt flag for match channel 3." /> + <BitField start="4" size="1" name="CR0INT" description="Interrupt flag for capture channel 0 event." /> + <BitField start="5" size="1" name="CR1INT" description="Interrupt flag for capture channel 1 event." /> + <BitField start="6" size="26" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x004" size="4" name="TCR" access="Read/Write" description="Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="CEN" description="When one, the Timer Counter and Prescale Counter are enabled for counting. When zero, the counters are disabled." /> + <BitField start="1" size="1" name="CRST" description="When one, the Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero." /> + <BitField start="2" size="30" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x008" size="4" name="TC" access="Read/Write" description="Timer Counter. The 32 bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="TC" description="Timer counter value." /> + </Register> + <Register start="+0x00C" size="4" name="PR" access="Read/Write" description="Prescale Register. When the Prescale Counter (PC) is equal to this value, the next clock increments the TC and clears the PC." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="PM" description="Prescale counter maximum value." /> + </Register> + <Register start="+0x010" size="4" name="PC" access="Read/Write" description="Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="PC" description="Prescale counter value." /> + </Register> + <Register start="+0x014" size="4" name="MCR" access="Read/Write" description="Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="MR0I" description="Interrupt on MR0"> + <Enum name="INTERRUPT_IS_GENERAT" start="1" description="Interrupt is generated when MR0 matches the value in the TC." /> + <Enum name="INTERRUPT_IS_DISABLE" start="0" description="Interrupt is disabled" /> + </BitField> + <BitField start="1" size="1" name="MR0R" description="Reset on MR0"> + <Enum name="TC_WILL_BE_RESET_IF_" start="1" description="TC will be reset if MR0 matches it." /> + <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." /> + </BitField> + <BitField start="2" size="1" name="MR0S" description="Stop on MR0"> + <Enum name="TC_AND_PC_WILL_BE_ST" start="1" description="TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC." /> + <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." /> + </BitField> + <BitField start="3" size="1" name="MR1I" description="Interrupt on MR1"> + <Enum name="INTERRUPT_IS_GENERAT" start="1" description="Interrupt is generated when MR1 matches the value in the TC." /> + <Enum name="INTERRUPT_IS_DISABLE" start="0" description="Interrupt is disabled." /> + </BitField> + <BitField start="4" size="1" name="MR1R" description="Reset on MR1"> + <Enum name="TC_WILL_BE_RESET_IF_" start="1" description="TC will be reset if MR1 matches it." /> + <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." /> + </BitField> + <BitField start="5" size="1" name="MR1S" description="Stop on MR1"> + <Enum name="TC_AND_PC_WILL_BE_ST" start="1" description="TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC." /> + <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." /> + </BitField> + <BitField start="6" size="1" name="MR2I" description="Interrupt on MR2"> + <Enum name="INTERRUPT_IS_GENERAT" start="1" description="Interrupt is generated when MR2 matches the value in the TC." /> + <Enum name="INTERRUPT_IS_DISABLE" start="0" description="Interrupt is disabled" /> + </BitField> + <BitField start="7" size="1" name="MR2R" description="Reset on MR2"> + <Enum name="TC_WILL_BE_RESET_IF_" start="1" description="TC will be reset if MR2 matches it." /> + <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." /> + </BitField> + <BitField start="8" size="1" name="MR2S" description="Stop on MR2."> + <Enum name="TC_AND_PC_WILL_BE_ST" start="1" description="TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC" /> + <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." /> + </BitField> + <BitField start="9" size="1" name="MR3I" description="Interrupt on MR3"> + <Enum name="INTERRUPT_IS_GENERAT" start="1" description="Interrupt is generated when MR3 matches the value in the TC." /> + <Enum name="THIS_INTERRUPT_IS_DI" start="0" description="This interrupt is disabled" /> + </BitField> + <BitField start="10" size="1" name="MR3R" description="Reset on MR3"> + <Enum name="TC_WILL_BE_RESET_IF_" start="1" description="TC will be reset if MR3 matches it." /> + <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." /> + </BitField> + <BitField start="11" size="1" name="MR3S" description="Stop on MR3"> + <Enum name="TC_AND_PC_WILL_BE_ST" start="1" description="TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC." /> + <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." /> + </BitField> + <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x018+0" size="4" name="MR[0]" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="MATCH" description="Timer counter match value." /> + </Register> + <Register start="+0x018+4" size="4" name="MR[1]" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="MATCH" description="Timer counter match value." /> + </Register> + <Register start="+0x018+8" size="4" name="MR[2]" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="MATCH" description="Timer counter match value." /> + </Register> + <Register start="+0x018+12" size="4" name="MR[3]" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="MATCH" description="Timer counter match value." /> + </Register> + <Register start="+0x028" size="4" name="CCR" access="Read/Write" description="Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="CAP0RE" description="Capture on CAPn.0 rising edge"> + <Enum name="ENABLE" start="1" description="A sequence of 0 then 1 on CAPn.0 will cause CR0 to be loaded with the contents of TC." /> + <Enum name="DISABLE" start="0" description="This feature is disabled." /> + </BitField> + <BitField start="1" size="1" name="CAP0FE" description="Capture on CAPn.0 falling edge"> + <Enum name="ENABLE" start="1" description="A sequence of 1 then 0 on CAPn.0 will cause CR0 to be loaded with the contents of TC." /> + <Enum name="DISABLE" start="0" description="This feature is disabled." /> + </BitField> + <BitField start="2" size="1" name="CAP0I" description="Interrupt on CAPn.0 event"> + <Enum name="ENABLE" start="1" description="A CR0 load due to a CAPn.0 event will generate an interrupt." /> + <Enum name="DISABLE" start="0" description="This feature is disabled." /> + </BitField> + <BitField start="3" size="1" name="CAP1RE" description="Capture on CAPn.1 rising edge"> + <Enum name="ENABLE" start="1" description="A sequence of 0 then 1 on CAPn.1 will cause CR1 to be loaded with the contents of TC." /> + <Enum name="DISABLE" start="0" description="This feature is disabled." /> + </BitField> + <BitField start="4" size="1" name="CAP1FE" description="Capture on CAPn.1 falling edge"> + <Enum name="ENABLE" start="1" description="A sequence of 1 then 0 on CAPn.1 will cause CR1 to be loaded with the contents of TC." /> + <Enum name="DISABLE" start="0" description="This feature is disabled." /> + </BitField> + <BitField start="5" size="1" name="CAP1I" description="Interrupt on CAPn.1 event"> + <Enum name="ENABLE" start="1" description="A CR1 load due to a CAPn.1 event will generate an interrupt." /> + <Enum name="DISABLE" start="0" description="This feature is disabled." /> + </BitField> + <BitField start="6" size="26" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x02C+0" size="4" name="CR[0]" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CAP" description="Timer counter capture value." /> + </Register> + <Register start="+0x02C+4" size="4" name="CR[1]" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CAP" description="Timer counter capture value." /> + </Register> + <Register start="+0x03C" size="4" name="EMR" access="Read/Write" description="External Match Register. The EMR controls the external match pins." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="EM0" description="External Match 0. When a match occurs between the TC and MR0, this bit can either toggle, go low, go high, or do nothing, depending on bits 5:4 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." /> + <BitField start="1" size="1" name="EM1" description="External Match 1. When a match occurs between the TC and MR1, this bit can either toggle, go low, go high, or do nothing, depending on bits 7:6 of this register. This bit can be driven onto a MATn.1 pin, in a positive-logic manner (0 = low, 1 = high)." /> + <BitField start="2" size="1" name="EM2" description="External Match 2. When a match occurs between the TC and MR2, this bit can either toggle, go low, go high, or do nothing, depending on bits 9:8 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." /> + <BitField start="3" size="1" name="EM3" description="External Match 3. When a match occurs between the TC and MR3, this bit can either toggle, go low, go high, or do nothing, depending on bits 11:10 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." /> + <BitField start="4" size="2" name="EMC0" description="External Match Control 0. Determines the functionality of External Match 0."> + <Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." /> + <Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." /> + <Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." /> + <Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." /> + </BitField> + <BitField start="6" size="2" name="EMC1" description="External Match Control 1. Determines the functionality of External Match 1."> + <Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." /> + <Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." /> + <Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." /> + <Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." /> + </BitField> + <BitField start="8" size="2" name="EMC2" description="External Match Control 2. Determines the functionality of External Match 2."> + <Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." /> + <Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." /> + <Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." /> + <Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." /> + </BitField> + <BitField start="10" size="2" name="EMC3" description="External Match Control 3. Determines the functionality of External Match 3."> + <Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." /> + <Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." /> + <Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." /> + <Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." /> + </BitField> + <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x070" size="4" name="CTCR" access="Read/Write" description="Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="CTMODE" description="Counter/Timer Mode This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale Register."> + <Enum name="TIMER_MODE_EVERY_RI" start="0x0" description="Timer Mode: every rising PCLK edge" /> + <Enum name="RISING" start="0x1" description="Counter Mode: TC is incremented on rising edges on the CAP input selected by bits 3:2." /> + <Enum name="FALLING" start="0x2" description="Counter Mode: TC is incremented on falling edges on the CAP input selected by bits 3:2." /> + <Enum name="DUALEDGE" start="0x3" description="Counter Mode: TC is incremented on both edges on the CAP input selected by bits 3:2." /> + </BitField> + <BitField start="2" size="2" name="CINSEL" description="Count Input Select When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the TnCTCR, the 3 bits for that input in the Capture Control Register (TnCCR) must be programmed as 000. However, capture and/or interrupt can be selected for the other 3 CAPn inputs in the same timer."> + <Enum name="CAPN_0_FOR_TIMERN" start="0x0" description="CAPn.0 for TIMERn" /> + <Enum name="CAPN_1_FOR_TIMERN" start="0x1" description="CAPn.1 for TIMERn" /> + </BitField> + <BitField start="4" size="28" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + </RegisterGroup> + <RegisterGroup name="UART0" start="0x4000C000" description="UART0/2/3 "> + <Register start="+0x000" size="4" name="RBR" access="None" description="Receiver Buffer Register. Contains the next received character to be read (DLAB =0)." reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="8" name="RBR" description="The UARTn Receiver Buffer Register contains the oldest received byte in the UARTn Rx FIFO." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x000" size="4" name="THR" access="WriteOnly" description="Transmit Holding Regiter. The next character to be transmitted is written here (DLAB =0)." reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="8" name="THR" description="Writing to the UARTn Transmit Holding Register causes the data to be stored in the UARTn transmit FIFO. The byte will be sent when it reaches the bottom of the FIFO and the transmitter is available." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x000" size="4" name="DLL" access="Read/Write" description="Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB =1)." reset_value="0x01" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="DLLSB" description="The UARTn Divisor Latch LSB Register, along with the UnDLM register, determines the baud rate of the UARTn." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x004" size="4" name="DLM" access="Read/Write" description="Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB =1)." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="DLMSB" description="The UARTn Divisor Latch MSB Register, along with the U0DLL register, determines the baud rate of the UARTn." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x004" size="4" name="IER" access="Read/Write" description="Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential UART interrupts (DLAB =0)." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RBRIE" description="RBR Interrupt Enable. Enables the Receive Data Available interrupt for UARTn. It also controls the Character Receive Time-out interrupt."> + <Enum name="DISABLE_THE_RDA_INTE" start="0" description="Disable the RDA interrupts." /> + <Enum name="ENABLE_THE_RDA_INTER" start="1" description="Enable the RDA interrupts." /> + </BitField> + <BitField start="1" size="1" name="THREIE" description="THRE Interrupt Enable. Enables the THRE interrupt for UARTn. The status of this can be read from UnLSR[5]."> + <Enum name="DISABLE_THE_THRE_INT" start="0" description="Disable the THRE interrupts." /> + <Enum name="ENABLE_THE_THRE_INTE" start="1" description="Enable the THRE interrupts." /> + </BitField> + <BitField start="2" size="1" name="RXIE" description="RX Line Status Interrupt Enable. Enables the UARTn RX line status interrupts. The status of this interrupt can be read from UnLSR[4:1]."> + <Enum name="DISABLE_THE_RX_LINE_" start="0" description="Disable the RX line status interrupts." /> + <Enum name="ENABLE_THE_RX_LINE_S" start="1" description="Enable the RX line status interrupts." /> + </BitField> + <BitField start="3" size="5" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="8" size="1" name="ABEOINTEN" description="Enables the end of auto-baud interrupt."> + <Enum name="DISABLE_END_OF_AUTO_" start="0" description="Disable end of auto-baud Interrupt." /> + <Enum name="ENABLE_END_OF_AUTO_B" start="1" description="Enable end of auto-baud Interrupt." /> + </BitField> + <BitField start="9" size="1" name="ABTOINTEN" description="Enables the auto-baud time-out interrupt."> + <Enum name="DISABLE_AUTO_BAUD_TI" start="0" description="Disable auto-baud time-out Interrupt." /> + <Enum name="ENABLE_AUTO_BAUD_TIM" start="1" description="Enable auto-baud time-out Interrupt." /> + </BitField> + <BitField start="10" size="22" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x008" size="4" name="IIR" access="ReadOnly" description="Interrupt ID Register. Identifies which interrupt(s) are pending." reset_value="0x01" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="INTSTATUS" description="Interrupt status. Note that UnIIR[0] is active low. The pending interrupt can be determined by evaluating UnIIR[3:1]."> + <Enum name="AT_LEAST_ONE_INTERRU" start="0" description="At least one interrupt is pending." /> + <Enum name="NO_INTERRUPT_IS_PEND" start="1" description="No interrupt is pending." /> + </BitField> + <BitField start="1" size="3" name="INTID" description="Interrupt identification. UnIER[3:1] identifies an interrupt corresponding to the UARTn Rx or TX FIFO. All other combinations of UnIER[3:1] not listed below are reserved (000,100,101,111)."> + <Enum name="1_RECEIVE_LINE_S" start="0x3" description="1 - Receive Line Status (RLS)." /> + <Enum name="2A__RECEIVE_DATA_AV" start="0x2" description="2a - Receive Data Available (RDA)." /> + <Enum name="2B__CHARACTER_TIME_" start="0x6" description="2b - Character Time-out Indicator (CTI)." /> + <Enum name="3_THRE_INTERRUPT" start="0x1" description="3 - THRE Interrupt" /> + </BitField> + <BitField start="4" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="6" size="2" name="FIFOENABLE" description="Copies of UnFCR[0]." /> + <BitField start="8" size="1" name="ABEOINT" description="End of auto-baud interrupt. True if auto-baud has finished successfully and interrupt is enabled." /> + <BitField start="9" size="1" name="ABTOINT" description="Auto-baud time-out interrupt. True if auto-baud has timed out and interrupt is enabled." /> + <BitField start="10" size="22" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x008" size="4" name="FCR" access="WriteOnly" description="FIFO Control Register. Controls UART FIFO usage and modes." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="FIFOEN" description="FIFO Enable."> + <Enum name="UARTN_FIFOS_ARE_DISA" start="0" description="UARTn FIFOs are disabled. Must not be used in the application." /> + <Enum name="ACTIVE_HIGH_ENABLE_F" start="1" description="Active high enable for both UARTn Rx and TX FIFOs and UnFCR[7:1] access. This bit must be set for proper UART operation. Any transition on this bit will automatically clear the related UART FIFOs." /> + </BitField> + <BitField start="1" size="1" name="RXFIFORES" description="RX FIFO Reset."> + <Enum name="NO_IMPACT_ON_EITHER_" start="0" description="No impact on either of UARTn FIFOs." /> + <Enum name="WRITING_A_LOGIC_1_TO" start="1" description="Writing a logic 1 to UnFCR[1] will clear all bytes in UARTn Rx FIFO, reset the pointer logic. This bit is self-clearing." /> + </BitField> + <BitField start="2" size="1" name="TXFIFORES" description="TX FIFO Reset."> + <Enum name="NO_IMPACT_ON_EITHER_" start="0" description="No impact on either of UARTn FIFOs." /> + <Enum name="WRITING_A_LOGIC_1_TO" start="1" description="Writing a logic 1 to UnFCR[2] will clear all bytes in UARTn TX FIFO, reset the pointer logic. This bit is self-clearing." /> + </BitField> + <BitField start="3" size="1" name="DMAMODE" description="DMA Mode Select. When the FIFO enable (bit 0 of this register) is set, this bit selects the DMA mode. See Section 18.6.6.1." /> + <BitField start="4" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="6" size="2" name="RXTRIGLVL" description="RX Trigger Level. These two bits determine how many receiver UARTn FIFO characters must be written before an interrupt or DMA request is activated."> + <Enum name="TRIGGER_LEVEL_0_1_C" start="0x0" description="Trigger level 0 (1 character or 0x01)." /> + <Enum name="TRIGGER_LEVEL_1_4_C" start="0x1" description="Trigger level 1 (4 characters or 0x04)." /> + <Enum name="TRIGGER_LEVEL_2_8_C" start="0x2" description="Trigger level 2 (8 characters or 0x08)." /> + <Enum name="TRIGGER_LEVEL_3_14_" start="0x3" description="Trigger level 3 (14 characters or 0x0E)." /> + </BitField> + <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x00C" size="4" name="LCR" access="Read/Write" description="Line Control Register. Contains controls for frame formatting and break generation." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="WLS" description="Word Length Select."> + <Enum name="5_BIT_CHARACTER_LENG" start="0x0" description="5-bit character length" /> + <Enum name="6_BIT_CHARACTER_LENG" start="0x1" description="6-bit character length" /> + <Enum name="7_BIT_CHARACTER_LENG" start="0x2" description="7-bit character length" /> + <Enum name="8_BIT_CHARACTER_LENG" start="0x3" description="8-bit character length" /> + </BitField> + <BitField start="2" size="1" name="SBS" description="Stop Bit Select"> + <Enum name="1_STOP_BIT_" start="0" description="1 stop bit." /> + <Enum name="2_STOP_BITS_1_5_IF_" start="1" description="2 stop bits (1.5 if UnLCR[1:0]=00)." /> + </BitField> + <BitField start="3" size="1" name="PE" description="Parity Enable."> + <Enum name="DISABLE_PARITY_GENER" start="0" description="Disable parity generation and checking." /> + <Enum name="ENABLE_PARITY_GENERA" start="1" description="Enable parity generation and checking." /> + </BitField> + <BitField start="4" size="2" name="PS" description="Parity Select"> + <Enum name="ODD_PARITY_NUMBER_O" start="0x0" description="Odd parity. Number of 1s in the transmitted character and the attached parity bit will be odd." /> + <Enum name="EVEN_PARITY_NUMBER_" start="0x1" description="Even Parity. Number of 1s in the transmitted character and the attached parity bit will be even." /> + <Enum name="FORCED_1_STICK_PARIT" start="0x2" description="Forced 1 stick parity." /> + <Enum name="FORCED_0_STICK_PARIT" start="0x3" description="Forced 0 stick parity." /> + </BitField> + <BitField start="6" size="1" name="BC" description="Break Control"> + <Enum name="DISABLE_BREAK_TRANSM" start="0" description="Disable break transmission." /> + <Enum name="ENABLE_BREAK_TRANSMI" start="1" description="Enable break transmission. Output pin UARTn TXD is forced to logic 0 when UnLCR[6] is active high." /> + </BitField> + <BitField start="7" size="1" name="DLAB" description="Divisor Latch Access Bit"> + <Enum name="DISABLE_ACCESS_TO_DI" start="0" description="Disable access to Divisor Latches." /> + <Enum name="ENABLE_ACCESS_TO_DIV" start="1" description="Enable access to Divisor Latches." /> + </BitField> + <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x014" size="4" name="LSR" access="None" description="Line Status Register. Contains flags for transmit and receive status, including line errors." reset_value="0x60" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RDR" description="Receiver Data Ready. UnLSR[0] is set when the UnRBR holds an unread character and is cleared when the UARTn RBR FIFO is empty."> + <Enum name="EMPTY" start="0" description="The UARTn receiver FIFO is empty." /> + <Enum name="NOTEMPTY" start="1" description="The UARTn receiver FIFO is not empty." /> + </BitField> + <BitField start="1" size="1" name="OE" description="Overrun Error. The overrun error condition is set as soon as it occurs. An UnLSR read clears UnLSR[1]. UnLSR[1] is set when UARTn RSR has a new character assembled and the UARTn RBR FIFO is full. In this case, the UARTn RBR FIFO will not be overwritten and the character in the UARTn RSR will be lost."> + <Enum name="INACTIVE" start="0" description="Overrun error status is inactive." /> + <Enum name="ACTIVE" start="1" description="Overrun error status is active." /> + </BitField> + <BitField start="2" size="1" name="PE" description="Parity Error. When the parity bit of a received character is in the wrong state, a parity error occurs. An UnLSR read clears UnLSR[2]. Time of parity error detection is dependent on UnFCR[0]. Note: A parity error is associated with the character at the top of the UARTn RBR FIFO."> + <Enum name="INACTIVE" start="0" description="Parity error status is inactive." /> + <Enum name="ACTIVE" start="1" description="Parity error status is active." /> + </BitField> + <BitField start="3" size="1" name="FE" description="Framing Error. When the stop bit of a received character is a logic 0, a framing error occurs. An UnLSR read clears UnLSR[3]. The time of the framing error detection is dependent on UnFCR[0]. Upon detection of a framing error, the Rx will attempt to resynchronize to the data and assume that the bad stop bit is actually an early start bit. However, it cannot be assumed that the next received byte will be correct even if there is no Framing Error. Note: A framing error is associated with the character at the top of the UARTn RBR FIFO."> + <Enum name="INACTIVE" start="0" description="Framing error status is inactive." /> + <Enum name="ACTIVE" start="1" description="Framing error status is active." /> + </BitField> + <BitField start="4" size="1" name="BI" description="Break Interrupt. When RXDn is held in the spacing state (all zeroes) for one full character transmission (start, data, parity, stop), a break interrupt occurs. Once the break condition has been detected, the receiver goes idle until RXDn goes to marking state (all ones). An UnLSR read clears this status bit. The time of break detection is dependent on UnFCR[0]. Note: The break interrupt is associated with the character at the top of the UARTn RBR FIFO."> + <Enum name="INACTIVE" start="0" description="Break interrupt status is inactive." /> + <Enum name="ACTIVE" start="1" description="Break interrupt status is active." /> + </BitField> + <BitField start="5" size="1" name="THRE" description="Transmitter Holding Register Empty. THRE is set immediately upon detection of an empty UARTn THR and is cleared on a UnTHR write."> + <Enum name="VALIDDATA" start="0" description="UnTHR contains valid data." /> + <Enum name="EMPTY" start="1" description="UnTHR is empty." /> + </BitField> + <BitField start="6" size="1" name="TEMT" description="Transmitter Empty. TEMT is set when both UnTHR and UnTSR are empty; TEMT is cleared when either the UnTSR or the UnTHR contain valid data."> + <Enum name="VALIDDATA" start="0" description="UnTHR and/or the UnTSR contains valid data." /> + <Enum name="EMPTY" start="1" description="UnTHR and the UnTSR are empty." /> + </BitField> + <BitField start="7" size="1" name="RXFE" description="Error in RX FIFO . UnLSR[7] is set when a character with a Rx error such as framing error, parity error or break interrupt, is loaded into the UnRBR. This bit is cleared when the UnLSR register is read and there are no subsequent errors in the UARTn FIFO."> + <Enum name="NOERROR" start="0" description="UnRBR contains no UARTn RX errors or UnFCR[0]=0." /> + <Enum name="ERRORS" start="1" description="UARTn RBR contains at least one UARTn RX error." /> + </BitField> + <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x01C" size="4" name="SCR" access="Read/Write" description="Scratch Pad Register. 8-bit temporary storage for software." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="PAD" description="A readable, writable byte." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x020" size="4" name="ACR" access="Read/Write" description="Auto-baud Control Register. Contains controls for the auto-baud feature." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="START" description="Start bit. This bit is automatically cleared after auto-baud completion."> + <Enum name="AUTO_BAUD_STOP_AUTO" start="0" description="Auto-baud stop (auto-baud is not running)." /> + <Enum name="AUTO_BAUD_START_AUT" start="1" description="Auto-baud start (auto-baud is running). Auto-baud run bit. This bit is automatically cleared after auto-baud completion." /> + </BitField> + <BitField start="1" size="1" name="MODE" description="Auto-baud mode select bit."> + <Enum name="MODE_0_" start="0" description="Mode 0." /> + <Enum name="MODE_1_" start="1" description="Mode 1." /> + </BitField> + <BitField start="2" size="1" name="AUTORESTART" description="Restart bit."> + <Enum name="NO_RESTART_" start="0" description="No restart." /> + <Enum name="RESTART_IN_CASE_OF_T" start="1" description="Restart in case of time-out (counter restarts at next UARTn Rx falling edge)" /> + </BitField> + <BitField start="3" size="5" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="8" size="1" name="ABEOINTCLR" description="End of auto-baud interrupt clear bit (write-only accessible). Writing a 1 will clear the corresponding interrupt in the UnIIR. Writing a 0 has no impact."> + <Enum name="NO_IMPACT_" start="0" description="No impact." /> + <Enum name="CLEAR_THE_CORRESPOND" start="1" description="Clear the corresponding interrupt in the IIR." /> + </BitField> + <BitField start="9" size="1" name="ABTOINTCLR" description="Auto-baud time-out interrupt clear bit (write-only accessible). Writing a 1 will clear the corresponding interrupt in the UnIIR. Writing a 0 has no impact."> + <Enum name="NO_IMPACT_" start="0" description="No impact." /> + <Enum name="CLEAR_THE_CORRESPOND" start="1" description="Clear the corresponding interrupt in the IIR." /> + </BitField> + <BitField start="10" size="22" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x028" size="4" name="FDR" access="Read/Write" description="Fractional Divider Register. Generates a clock input for the baud rate divider." reset_value="0x10" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="4" name="DIVADDVAL" description="Baud-rate generation pre-scaler divisor value. If this field is 0, fractional baud-rate generator will not impact the UARTn baudrate." /> + <BitField start="4" size="4" name="MULVAL" description="Baud-rate pre-scaler multiplier value. This field must be greater or equal 1 for UARTn to operate properly, regardless of whether the fractional baud-rate generator is used or not." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x030" size="4" name="TER" access="Read/Write" description="Transmit Enable Register. Turns off UART transmitter for use with software flow control." reset_value="0x80" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="7" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="7" size="1" name="TXEN" description="When this bit is 1, as it is after a Reset, data written to the THR is output on the TXD pin as soon as any preceding data has been sent. If this bit is cleared to 0 while a character is being sent, the transmission of that character is completed, but no further characters are sent until this bit is set again. In other words, a 0 in this bit blocks the transfer of characters from the THR or TX FIFO into the transmit shift register. Software implementing software-handshaking can clear this bit when it receives an XOFF character (DC3). Software can set this bit again when it receives an XON (DC1) character." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x04C" size="4" name="RS485CTRL" access="Read/Write" description="RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="NMMEN" description="NMM enable."> + <Enum name="DISABLED" start="0" description="RS-485/EIA-485 Normal Multidrop Mode (NMM) is disabled." /> + <Enum name="ENABLED" start="1" description="RS-485/EIA-485 Normal Multidrop Mode (NMM) is enabled. In this mode, an address is detected when a received byte has the parity bit = 1, generating a received data interrupt. See Section 18.6.16 RS-485/EIA-485 modes of operation." /> + </BitField> + <BitField start="1" size="1" name="RXDIS" description="Receiver enable."> + <Enum name="ENABLED" start="0" description="The receiver is enabled." /> + <Enum name="DISABLED" start="1" description="The receiver is disabled." /> + </BitField> + <BitField start="2" size="1" name="AADEN" description="AAD enable."> + <Enum name="DISABLED" start="0" description="Auto Address Detect (AAD) is disabled." /> + <Enum name="ENABLED" start="1" description="Auto Address Detect (AAD) is enabled." /> + </BitField> + <BitField start="3" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="4" size="1" name="DCTRL" description="Direction control enable."> + <Enum name="DISABLE_AUTO_DIRECTI" start="0" description="Disable Auto Direction Control." /> + <Enum name="ENABLE_AUTO_DIRECTIO" start="1" description="Enable Auto Direction Control." /> + </BitField> + <BitField start="5" size="1" name="OINV" description="Direction control pin polarity. This bit reverses the polarity of the direction control signal on the Un_OE pin."> + <Enum name="DIRLOW" start="0" description="The direction control pin will be driven to logic 0 when the transmitter has data to be sent. It will be driven to logic 1 after the last bit of data has been transmitted." /> + <Enum name="DIRHIGH" start="1" description="The direction control pin will be driven to logic 1 when the transmitter has data to be sent. It will be driven to logic 0 after the last bit of data has been transmitted." /> + </BitField> + <BitField start="6" size="26" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x050" size="4" name="RS485ADRMATCH" access="Read/Write" description="RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="ADRMATCH" description="Contains the address match value." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x054" size="4" name="RS485DLY" access="Read/Write" description="RS-485/EIA-485 direction control delay." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="DLY" description="Contains the direction control (UnOE) delay value. This register works in conjunction with an 8-bit counter." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + </RegisterGroup> + <RegisterGroup name="UART1" start="0x40010000" description="UART1 "> + <Register start="+0x000" size="4" name="RBR" access="None" description="DLAB =0 Receiver Buffer Register. Contains the next received character to be read." reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="8" name="RBR" description="The UART1 Receiver Buffer Register contains the oldest received byte in the UART1 RX FIFO." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x000" size="4" name="THR" access="WriteOnly" description="DLAB =0. Transmit Holding Register. The next character to be transmitted is written here." reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="8" name="THR" description="Writing to the UART1 Transmit Holding Register causes the data to be stored in the UART1 transmit FIFO. The byte will be sent when it reaches the bottom of the FIFO and the transmitter is available." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x000" size="4" name="DLL" access="Read/Write" description="DLAB =1. Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider." reset_value="0x01" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="DLLSB" description="The UART1 Divisor Latch LSB Register, along with the U1DLM register, determines the baud rate of the UART1." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x004" size="4" name="DLM" access="Read/Write" description="DLAB =1. Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="DLMSB" description="The UART1 Divisor Latch MSB Register, along with the U1DLL register, determines the baud rate of the UART1." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x004" size="4" name="IER" access="Read/Write" description="DLAB =0. Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential UART1 interrupts." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RBRIE" description="RBR Interrupt Enable. Enables the Receive Data Available interrupt for UART1. It also controls the Character Receive Time-out interrupt."> + <Enum name="DISABLE_THE_RDA_INTE" start="0" description="Disable the RDA interrupts." /> + <Enum name="ENABLE_THE_RDA_INTER" start="1" description="Enable the RDA interrupts." /> + </BitField> + <BitField start="1" size="1" name="THREIE" description="THRE Interrupt Enable. Enables the THRE interrupt for UART1. The status of this interrupt can be read from LSR[5]."> + <Enum name="DISABLE_THE_THRE_INT" start="0" description="Disable the THRE interrupts." /> + <Enum name="ENABLE_THE_THRE_INTE" start="1" description="Enable the THRE interrupts." /> + </BitField> + <BitField start="2" size="1" name="RXIE" description="RX Line Interrupt Enable. Enables the UART1 RX line status interrupts. The status of this interrupt can be read from LSR[4:1]."> + <Enum name="DISABLE_THE_RX_LINE_" start="0" description="Disable the RX line status interrupts." /> + <Enum name="ENABLE_THE_RX_LINE_S" start="1" description="Enable the RX line status interrupts." /> + </BitField> + <BitField start="3" size="1" name="MSIE" description="Modem Status Interrupt Enable. Enables the modem interrupt. The status of this interrupt can be read from MSR[3:0]."> + <Enum name="DISABLE_THE_MODEM_IN" start="0" description="Disable the modem interrupt." /> + <Enum name="ENABLE_THE_MODEM_INT" start="1" description="Enable the modem interrupt." /> + </BitField> + <BitField start="4" size="3" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + <BitField start="7" size="1" name="CTSIE" description="CTS Interrupt Enable. If auto-cts mode is enabled this bit enables/disables the modem status interrupt generation on a CTS1 signal transition. If auto-cts mode is disabled a CTS1 transition will generate an interrupt if Modem Status Interrupt Enable (IER[3]) is set. In normal operation a CTS1 signal transition will generate a Modem Status Interrupt unless the interrupt has been disabled by clearing the IER[3] bit in the IER register. In auto-cts mode a transition on the CTS1 bit will trigger an interrupt only if both the IER[3] and IER[7] bits are set."> + <Enum name="DISABLE_THE_CTS_INTE" start="0" description="Disable the CTS interrupt." /> + <Enum name="ENABLE_THE_CTS_INTER" start="1" description="Enable the CTS interrupt." /> + </BitField> + <BitField start="8" size="1" name="ABEOIE" description="Enables the end of auto-baud interrupt."> + <Enum name="DISABLE_END_OF_AUTO_" start="0" description="Disable end of auto-baud Interrupt." /> + <Enum name="ENABLE_END_OF_AUTO_B" start="1" description="Enable end of auto-baud Interrupt." /> + </BitField> + <BitField start="9" size="1" name="ABTOIE" description="Enables the auto-baud time-out interrupt."> + <Enum name="DISABLE_AUTO_BAUD_TI" start="0" description="Disable auto-baud time-out Interrupt." /> + <Enum name="ENABLE_AUTO_BAUD_TIM" start="1" description="Enable auto-baud time-out Interrupt." /> + </BitField> + <BitField start="10" size="22" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x008" size="4" name="IIR" access="ReadOnly" description="Interrupt ID Register. Identifies which interrupt(s) are pending." reset_value="0x01" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="INTSTATUS" description="Interrupt status. Note that IIR[0] is active low. The pending interrupt can be determined by evaluating IIR[3:1]."> + <Enum name="AT_LEAST_ONE_INTERRU" start="0" description="At least one interrupt is pending." /> + <Enum name="NO_INTERRUPT_IS_PEND" start="1" description="No interrupt is pending." /> + </BitField> + <BitField start="1" size="3" name="INTID" description="Interrupt identification. IER[3:1] identifies an interrupt corresponding to the UART1 Rx or TX FIFO. All other combinations of IER[3:1] not listed below are reserved (100,101,111)."> + <Enum name="RLS" start="0x3" description="1 - Receive Line Status (RLS)." /> + <Enum name="RDA" start="0x2" description="2a - Receive Data Available (RDA)." /> + <Enum name="CTI" start="0x6" description="2b - Character Time-out Indicator (CTI)." /> + <Enum name="THRE" start="0x1" description="3 - THRE Interrupt." /> + <Enum name="MODEM" start="0x0" description="4 - Modem Interrupt." /> + </BitField> + <BitField start="4" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + <BitField start="6" size="2" name="FIFOENABLE" description="Copies of FCR[0]." /> + <BitField start="8" size="1" name="ABEOINT" description="End of auto-baud interrupt. True if auto-baud has finished successfully and interrupt is enabled." /> + <BitField start="9" size="1" name="ABTOINT" description="Auto-baud time-out interrupt. True if auto-baud has timed out and interrupt is enabled." /> + <BitField start="10" size="22" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x008" size="4" name="FCR" access="WriteOnly" description="FIFO Control Register. Controls UART1 FIFO usage and modes." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="FIFOEN" description="FIFO enable."> + <Enum name="MUST_NOT_BE_USED_IN_" start="0" description="Must not be used in the application." /> + <Enum name="ACTIVE_HIGH_ENABLE_F" start="1" description="Active high enable for both UART1 Rx and TX FIFOs and FCR[7:1] access. This bit must be set for proper UART1 operation. Any transition on this bit will automatically clear the UART1 FIFOs." /> + </BitField> + <BitField start="1" size="1" name="RXFIFORES" description="RX FIFO Reset."> + <Enum name="NO_IMPACT_ON_EITHER_" start="0" description="No impact on either of UART1 FIFOs." /> + <Enum name="WRITING_A_LOGIC_1_TO" start="1" description="Writing a logic 1 to FCR[1] will clear all bytes in UART1 Rx FIFO, reset the pointer logic. This bit is self-clearing." /> + </BitField> + <BitField start="2" size="1" name="TXFIFORES" description="TX FIFO Reset."> + <Enum name="NO_IMPACT_ON_EITHER_" start="0" description="No impact on either of UART1 FIFOs." /> + <Enum name="WRITING_A_LOGIC_1_TO" start="1" description="Writing a logic 1 to FCR[2] will clear all bytes in UART1 TX FIFO, reset the pointer logic. This bit is self-clearing." /> + </BitField> + <BitField start="3" size="1" name="DMAMODE" description="DMA Mode Select. When the FIFO enable bit (bit 0 of this register) is set, this bit selects the DMA mode. See Section 36.6.6.1." /> + <BitField start="4" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + <BitField start="6" size="2" name="RXTRIGLVL" description="RX Trigger Level. These two bits determine how many receiver UART1 FIFO characters must be written before an interrupt is activated."> + <Enum name="TRIGGER_LEVEL_0_1_C" start="0x0" description="Trigger level 0 (1 character or 0x01)." /> + <Enum name="TRIGGER_LEVEL_1_4_C" start="0x1" description="Trigger level 1 (4 characters or 0x04)." /> + <Enum name="TRIGGER_LEVEL_2_8_C" start="0x2" description="Trigger level 2 (8 characters or 0x08)." /> + <Enum name="TRIGGER_LEVEL_3_14_" start="0x3" description="Trigger level 3 (14 characters or 0x0E)." /> + </BitField> + <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits." /> + </Register> + <Register start="+0x00C" size="4" name="LCR" access="Read/Write" description="Line Control Register. Contains controls for frame formatting and break generation." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="WLS" description="Word Length Select."> + <Enum name="5_BIT_CHARACTER_LENG" start="0x0" description="5-bit character length." /> + <Enum name="6_BIT_CHARACTER_LENG" start="0x1" description="6-bit character length." /> + <Enum name="7_BIT_CHARACTER_LENG" start="0x2" description="7-bit character length." /> + <Enum name="8_BIT_CHARACTER_LENG" start="0x3" description="8-bit character length." /> + </BitField> + <BitField start="2" size="1" name="SBS" description="Stop Bit Select."> + <Enum name="1_STOP_BIT_" start="0" description="1 stop bit." /> + <Enum name="2_STOP_BITS_1_5_IF_" start="1" description="2 stop bits (1.5 if LCR[1:0]=00)." /> + </BitField> + <BitField start="3" size="1" name="PE" description="Parity Enable."> + <Enum name="DISABLE_PARITY_GENER" start="0" description="Disable parity generation and checking." /> + <Enum name="ENABLE_PARITY_GENERA" start="1" description="Enable parity generation and checking." /> + </BitField> + <BitField start="4" size="2" name="PS" description="Parity Select."> + <Enum name="ODD_PARITY_NUMBER_O" start="0x0" description="Odd parity. Number of 1s in the transmitted character and the attached parity bit will be odd." /> + <Enum name="EVEN_PARITY_NUMBER_" start="0x1" description="Even Parity. Number of 1s in the transmitted character and the attached parity bit will be even." /> + <Enum name="FORCED1STICK_PAR" start="0x2" description="Forced 1 stick parity." /> + <Enum name="FORCED0STICK_PAR" start="0x3" description="Forced 0 stick parity." /> + </BitField> + <BitField start="6" size="1" name="BC" description="Break Control."> + <Enum name="DISABLE_BREAK_TRANSM" start="0" description="Disable break transmission." /> + <Enum name="ENABLE_BREAK_TRANSMI" start="1" description="Enable break transmission. Output pin UART1 TXD is forced to logic 0 when LCR[6] is active high." /> + </BitField> + <BitField start="7" size="1" name="DLAB" description="Divisor Latch Access Bit (DLAB)"> + <Enum name="DISABLE_ACCESS_TO_DI" start="0" description="Disable access to Divisor Latches." /> + <Enum name="ENABLE_ACCESS_TO_DIV" start="1" description="Enable access to Divisor Latches." /> + </BitField> + <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x010" size="4" name="MCR" access="Read/Write" description="Modem Control Register. Contains controls for flow control handshaking and loopback mode." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="DTRCTRL" description="DTR Control. Source for modem output pin, DTR. This bit reads as 0 when modem loopback mode is active." /> + <BitField start="1" size="1" name="RTSCTRL" description="RTS Control. Source for modem output pin RTS. This bit reads as 0 when modem loopback mode is active." /> + <BitField start="2" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + <BitField start="4" size="1" name="LMS" description="Loopback Mode Select. The modem loopback mode provides a mechanism to perform diagnostic loopback testing. Serial data from the transmitter is connected internally to serial input of the receiver. Input pin, RXD1, has no effect on loopback and output pin, TXD1 is held in marking state. The 4 modem inputs (CTS, DSR, RI and DCD) are disconnected externally. Externally, the modem outputs (RTS, DTR) are set inactive. Internally, the 4 modem outputs are connected to the 4 modem inputs. As a result of these connections, the upper 4 bits of the MSR will be driven by the lower 4 bits of the MCR rather than the 4 modem inputs in normal mode. This permits modem status interrupts to be generated in loopback mode by writing the lower 4 bits of MCR."> + <Enum name="DISABLE_MODEM_LOOPBA" start="0" description="Disable modem loopback mode." /> + <Enum name="ENABLE_MODEM_LOOPBAC" start="1" description="Enable modem loopback mode." /> + </BitField> + <BitField start="5" size="1" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + <BitField start="6" size="1" name="RTSEN" description="RTS enable."> + <Enum name="DISABLE_AUTO_RTS_FLO" start="0" description="Disable auto-rts flow control." /> + <Enum name="ENABLE_AUTO_RTS_FLOW" start="1" description="Enable auto-rts flow control." /> + </BitField> + <BitField start="7" size="1" name="CTSEN" description="CTS enable."> + <Enum name="DISABLE_AUTO_CTS_FLO" start="0" description="Disable auto-cts flow control." /> + <Enum name="ENABLE_AUTO_CTS_FLOW" start="1" description="Enable auto-cts flow control." /> + </BitField> + <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x014" size="4" name="LSR" access="None" description="Line Status Register. Contains flags for transmit and receive status, including line errors." reset_value="0x60" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RDR" description="Receiver Data Ready. LSR[0] is set when the RBR holds an unread character and is cleared when the UART1 RBR FIFO is empty."> + <Enum name="EMPTY" start="0" description="The UART1 receiver FIFO is empty." /> + <Enum name="NOTEMPTY" start="1" description="The UART1 receiver FIFO is not empty." /> + </BitField> + <BitField start="1" size="1" name="OE" description="Overrun Error. The overrun error condition is set as soon as it occurs. An LSR read clears LSR[1]. LSR[1] is set when UART1 RSR has a new character assembled and the UART1 RBR FIFO is full. In this case, the UART1 RBR FIFO will not be overwritten and the character in the UART1 RSR will be lost."> + <Enum name="INACTIVE" start="0" description="Overrun error status is inactive." /> + <Enum name="ACTIVE" start="1" description="Overrun error status is active." /> + </BitField> + <BitField start="2" size="1" name="PE" description="Parity Error. When the parity bit of a received character is in the wrong state, a parity error occurs. An LSR read clears LSR[2]. Time of parity error detection is dependent on FCR[0]. Note: A parity error is associated with the character at the top of the UART1 RBR FIFO."> + <Enum name="INACTIVE" start="0" description="Parity error status is inactive." /> + <Enum name="ACTIVE" start="1" description="Parity error status is active." /> + </BitField> + <BitField start="3" size="1" name="FE" description="Framing Error. When the stop bit of a received character is a logic 0, a framing error occurs. An LSR read clears LSR[3]. The time of the framing error detection is dependent on FCR0. Upon detection of a framing error, the RX will attempt to resynchronize to the data and assume that the bad stop bit is actually an early start bit. However, it cannot be assumed that the next received byte will be correct even if there is no Framing Error. Note: A framing error is associated with the character at the top of the UART1 RBR FIFO."> + <Enum name="INACTIVE" start="0" description="Framing error status is inactive." /> + <Enum name="ACTIVE" start="1" description="Framing error status is active." /> + </BitField> + <BitField start="4" size="1" name="BI" description="Break Interrupt. When RXD1 is held in the spacing state (all zeroes) for one full character transmission (start, data, parity, stop), a break interrupt occurs. Once the break condition has been detected, the receiver goes idle until RXD1 goes to marking state (all ones). An LSR read clears this status bit. The time of break detection is dependent on FCR[0]. Note: The break interrupt is associated with the character at the top of the UART1 RBR FIFO."> + <Enum name="INACTIVE" start="0" description="Break interrupt status is inactive." /> + <Enum name="ACTIVE" start="1" description="Break interrupt status is active." /> + </BitField> + <BitField start="5" size="1" name="THRE" description="Transmitter Holding Register Empty. THRE is set immediately upon detection of an empty UART1 THR and is cleared on a THR write."> + <Enum name="VALID" start="0" description="THR contains valid data." /> + <Enum name="THR_IS_EMPTY_" start="1" description="THR is empty." /> + </BitField> + <BitField start="6" size="1" name="TEMT" description="Transmitter Empty. TEMT is set when both THR and TSR are empty; TEMT is cleared when either the TSR or the THR contain valid data."> + <Enum name="VALID" start="0" description="THR and/or the TSR contains valid data." /> + <Enum name="EMPTY" start="1" description="THR and the TSR are empty." /> + </BitField> + <BitField start="7" size="1" name="RXFE" description="Error in RX FIFO. LSR[7] is set when a character with a RX error such as framing error, parity error or break interrupt, is loaded into the RBR. This bit is cleared when the LSR register is read and there are no subsequent errors in the UART1 FIFO."> + <Enum name="NOERROR" start="0" description="RBR contains no UART1 RX errors or FCR[0]=0." /> + <Enum name="ERRORS" start="1" description="UART1 RBR contains at least one UART1 RX error." /> + </BitField> + <BitField start="8" size="24" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x018" size="4" name="MSR" access="None" description="Modem Status Register. Contains handshake signal status flags." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="DCTS" description="Delta CTS. Set upon state change of input CTS. Cleared on an MSR read."> + <Enum name="NO_CHANGE_DETECTED_O" start="0" description="No change detected on modem input, CTS." /> + <Enum name="STATE_CHANGE_DETECTE" start="1" description="State change detected on modem input, CTS." /> + </BitField> + <BitField start="1" size="1" name="DDSR" description="Delta DSR. Set upon state change of input DSR. Cleared on an MSR read."> + <Enum name="NO_CHANGE_DETECTED_O" start="0" description="No change detected on modem input, DSR." /> + <Enum name="STATE_CHANGE_DETECTE" start="1" description="State change detected on modem input, DSR." /> + </BitField> + <BitField start="2" size="1" name="TERI" description="Trailing Edge RI. Set upon low to high transition of input RI. Cleared on an MSR read."> + <Enum name="NO_CHANGE_DETECTED_O" start="0" description="No change detected on modem input, RI." /> + <Enum name="LOW_TO_HIGH_TRANSITI" start="1" description="Low-to-high transition detected on RI." /> + </BitField> + <BitField start="3" size="1" name="DDCD" description="Delta DCD. Set upon state change of input DCD. Cleared on an MSR read."> + <Enum name="NO_CHANGE_DETECTED_O" start="0" description="No change detected on modem input, DCD." /> + <Enum name="STATE_CHANGE_DETECTE" start="1" description="State change detected on modem input, DCD." /> + </BitField> + <BitField start="4" size="1" name="CTS" description="Clear To Send State. Complement of input signal CTS. This bit is connected to MCR[1] in modem loopback mode." /> + <BitField start="5" size="1" name="DSR" description="Data Set Ready State. Complement of input signal DSR. This bit is connected to MCR[0] in modem loopback mode." /> + <BitField start="6" size="1" name="RI" description="Ring Indicator State. Complement of input RI. This bit is connected to MCR[2] in modem loopback mode." /> + <BitField start="7" size="1" name="DCD" description="Data Carrier Detect State. Complement of input DCD. This bit is connected to MCR[3] in modem loopback mode." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x01C" size="4" name="SCR" access="Read/Write" description="Scratch Pad Register. 8-bit temporary storage for software." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="Pad" description="A readable, writable byte." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x020" size="4" name="ACR" access="Read/Write" description="Auto-baud Control Register. Contains controls for the auto-baud feature." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="START" description="Auto-baud start bit. This bit is automatically cleared after auto-baud completion."> + <Enum name="STOP" start="0" description="Auto-baud stop (auto-baud is not running)." /> + <Enum name="START" start="1" description="Auto-baud start (auto-baud is running). Auto-baud run bit. This bit is automatically cleared after auto-baud completion." /> + </BitField> + <BitField start="1" size="1" name="MODE" description="Auto-baud mode select bit."> + <Enum name="MODE_0_" start="0" description="Mode 0." /> + <Enum name="MODE_1_" start="1" description="Mode 1." /> + </BitField> + <BitField start="2" size="1" name="AUTORESTART" description="Auto-baud restart bit."> + <Enum name="NO_RESTART" start="0" description="No restart" /> + <Enum name="RESTART_IN_CASE_OF_T" start="1" description="Restart in case of time-out (counter restarts at next UART1 Rx falling edge)" /> + </BitField> + <BitField start="3" size="5" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + <BitField start="8" size="1" name="ABEOINTCLR" description="End of auto-baud interrupt clear bit (write-only)."> + <Enum name="WRITING_A_0_HAS_NO_I" start="0" description="Writing a 0 has no impact." /> + <Enum name="WRITING_A_1_WILL_CLE" start="1" description="Writing a 1 will clear the corresponding interrupt in the IIR." /> + </BitField> + <BitField start="9" size="1" name="ABTOINTCLR" description="Auto-baud time-out interrupt clear bit (write-only)."> + <Enum name="WRITING_A_0_HAS_NO_I" start="0" description="Writing a 0 has no impact." /> + <Enum name="WRITING_A_1_WILL_CLE" start="1" description="Writing a 1 will clear the corresponding interrupt in the IIR." /> + </BitField> + <BitField start="10" size="22" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x028" size="4" name="FDR" access="Read/Write" description="Fractional Divider Register. Generates a clock input for the baud rate divider." reset_value="0x10" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="4" name="DIVADDVAL" description="Baud rate generation pre-scaler divisor value. If this field is 0, fractional baud rate generator will not impact the UART1 baud rate." /> + <BitField start="4" size="4" name="MULVAL" description="Baud rate pre-scaler multiplier value. This field must be greater or equal 1 for UART1 to operate properly, regardless of whether the fractional baud rate generator is used or not." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x030" size="4" name="TER" access="Read/Write" description="Transmit Enable Register. Turns off UART transmitter for use with software flow control." reset_value="0x80" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="7" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="7" size="1" name="TXEN" description="When this bit is 1, as it is after a Reset, data written to the THR is output on the TXD pin as soon as any preceding data has been sent. If this bit cleared to 0 while a character is being sent, the transmission of that character is completed, but no further characters are sent until this bit is set again. In other words, a 0 in this bit blocks the transfer of characters from the THR or TX FIFO into the transmit shift register. Software can clear this bit when it detects that the a hardware-handshaking TX-permit signal (CTS) has gone false, or with software handshaking, when it receives an XOFF character (DC3). Software can set this bit again when it detects that the TX-permit signal has gone true, or when it receives an XON (DC1) character." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x04C" size="4" name="RS485CTRL" access="Read/Write" description="RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="NMMEN" description="RS-485/EIA-485 Normal Multidrop Mode (NMM) mode select."> + <Enum name="DISABLED_" start="0" description="Disabled." /> + <Enum name="ENABLED_IN_THIS_MOD" start="1" description="Enabled. In this mode, an address is detected when a received byte causes the UART to set the parity error and generate an interrupt." /> + </BitField> + <BitField start="1" size="1" name="RXDIS" description="Receive enable."> + <Enum name="ENABLED_" start="0" description="Enabled." /> + <Enum name="DISABLED_" start="1" description="Disabled." /> + </BitField> + <BitField start="2" size="1" name="AADEN" description="Auto Address Detect (AAD) enable."> + <Enum name="DISABLED_" start="0" description="Disabled." /> + <Enum name="ENABLED_" start="1" description="Enabled." /> + </BitField> + <BitField start="3" size="1" name="SEL" description="Direction control."> + <Enum name="RTS_IF_DIRECTION_CO" start="0" description="RTS. If direction control is enabled (bit DCTRL = 1), pin RTS is used for direction control." /> + <Enum name="DTR_IF_DIRECTION_CO" start="1" description="DTR. If direction control is enabled (bit DCTRL = 1), pin DTR is used for direction control." /> + </BitField> + <BitField start="4" size="1" name="DCTRL" description="Direction control enable."> + <Enum name="DISABLE_AUTO_DIRECTI" start="0" description="Disable Auto Direction Control." /> + <Enum name="ENABLE_AUTO_DIRECTIO" start="1" description="Enable Auto Direction Control." /> + </BitField> + <BitField start="5" size="1" name="OINV" description="Polarity. This bit reverses the polarity of the direction control signal on the RTS (or DTR) pin."> + <Enum name="LOW_THE_DIRECTION_C" start="0" description="LOW. The direction control pin will be driven to logic 0 when the transmitter has data to be sent. It will be driven to logic 1 after the last bit of data has been transmitted." /> + <Enum name="HIGH_THE_DIRECTION_" start="1" description="HIGH. The direction control pin will be driven to logic 1 when the transmitter has data to be sent. It will be driven to logic 0 after the last bit of data has been transmitted." /> + </BitField> + <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x050" size="4" name="RS485ADRMATCH" access="Read/Write" description="RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="ADRMATCH" description="Contains the address match value." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x054" size="4" name="RS485DLY" access="Read/Write" description="RS-485/EIA-485 direction control delay." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="DLY" description="Contains the direction control (RTS or DTR) delay value. This register works in conjunction with an 8-bit counter." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + </RegisterGroup> + <RegisterGroup name="PWM1" start="0x40018000" description="Pulse Width Modulators (PWM1) "> + <Register start="+0x000" size="4" name="IR" access="Read/Write" description="Interrupt Register. The IR can be written to clear interrupts, or read to identify which PWM interrupt sources are pending." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="PWMMR0INT" description="Interrupt flag for PWM match channel 0." /> + <BitField start="1" size="1" name="PWMMR1INT" description="Interrupt flag for PWM match channel 1." /> + <BitField start="2" size="1" name="PWMMR2INT" description="Interrupt flag for PWM match channel 2." /> + <BitField start="3" size="1" name="PWMMR3INT" description="Interrupt flag for PWM match channel 3." /> + <BitField start="4" size="1" name="PWMCAP0INT" description="Interrupt flag for capture input 0" /> + <BitField start="5" size="1" name="PWMCAP1INT" description="Interrupt flag for capture input 1 (available in PWM1IR only; this bit is reserved in PWM0IR)." /> + <BitField start="6" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="8" size="1" name="PWMMR4INT" description="Interrupt flag for PWM match channel 4." /> + <BitField start="9" size="1" name="PWMMR5INT" description="Interrupt flag for PWM match channel 5." /> + <BitField start="10" size="1" name="PWMMR6INT" description="Interrupt flag for PWM match channel 6." /> + <BitField start="11" size="21" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x004" size="4" name="TCR" access="Read/Write" description="Timer Control Register. The TCR is used to control the Timer Counter functions." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="CE" description="Counter Enable"> + <Enum name="THE_PWM_TIMER_COUNTE" start="1" description="The PWM Timer Counter and PWM Prescale Counter are enabled for counting." /> + <Enum name="THE_COUNTERS_ARE_DIS" start="0" description="The counters are disabled." /> + </BitField> + <BitField start="1" size="1" name="CR" description="Counter Reset"> + <Enum name="THE_PWM_TIMER_COUNTE" start="1" description="The PWM Timer Counter and the PWM Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until this bit is returned to zero." /> + <Enum name="CLEAR_RESET_" start="0" description="Clear reset." /> + </BitField> + <BitField start="2" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="3" size="1" name="PWMEN" description="PWM Enable"> + <Enum name="PWM_MODE_IS_ENABLED_" start="1" description="PWM mode is enabled (counter resets to 1). PWM mode causes the shadow registers to operate in connection with the Match registers. A program write to a Match register will not have an effect on the Match result until the corresponding bit in PWMLER has been set, followed by the occurrence of a PWM Match 0 event. Note that the PWM Match register that determines the PWM rate (PWM Match Register 0 - MR0) must be set up prior to the PWM being enabled. Otherwise a Match event will not occur to cause shadow register contents to become effective." /> + <Enum name="TIMER_MODE_IS_ENABLE" start="0" description="Timer mode is enabled (counter resets to 0)." /> + </BitField> + <BitField start="4" size="1" name="MDIS" description="Master Disable (PWM0 only). The two PWMs may be synchronized using the Master Disable control bit. The Master disable bit of the Master PWM (PWM0 module) controls a secondary enable input to both PWMs, as shown in Figure 141. This bit has no function in the Slave PWM (PWM1)."> + <Enum name="MASTER_USE_PWM0_IS_" start="1" description="Master use. PWM0 is the master, and both PWMs are enabled for counting." /> + <Enum name="INDIVIDUAL_USE_THE_" start="0" description="Individual use. The PWMs are used independently, and the individual Counter Enable bits are used to control the PWMs." /> + </BitField> + <BitField start="5" size="27" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x008" size="4" name="TC" access="Read/Write" description="Timer Counter. The 32 bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="TC" description="Timer counter value." /> + </Register> + <Register start="+0x00C" size="4" name="PR" access="Read/Write" description="Prescale Register. Determines how often the PWM counter is incremented." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="PM" description="Prescale counter maximum value." /> + </Register> + <Register start="+0x010" size="4" name="PC" access="Read/Write" description="Prescale Counter. Prescaler for the main PWM counter." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="PC" description="Prescale counter value." /> + </Register> + <Register start="+0x014" size="4" name="MCR" access="Read/Write" description="Match Control Register. The MCR is used to control whether an interrupt is generated and if the PWM counter is reset when a Match occurs." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="PWMMR0I" description="Interrupt PWM0"> + <Enum name="DISABLED_" start="0" description="Disabled." /> + <Enum name="INTERRUPT_ON_PWMMR0" start="1" description="Interrupt on PWMMR0: an interrupt is generated when PWMMR0 matches the value in the PWMTC." /> + </BitField> + <BitField start="1" size="1" name="PWMMR0R" description="Reset PWM0"> + <Enum name="DISABLED_" start="0" description="Disabled." /> + <Enum name="RESET_ON_PWMMR0_THE" start="1" description="Reset on PWMMR0: the PWMTC will be reset if PWMMR0 matches it." /> + </BitField> + <BitField start="2" size="1" name="PWMMR0S" description="Stop PWM0"> + <Enum name="DISABLED" start="0" description="Disabled" /> + <Enum name="STOP_ON_PWMMR0_THE_" start="1" description="Stop on PWMMR0: the PWMTC and PWMPC will be stopped and PWMTCR bit 0 will be set to 0 if PWMMR0 matches the PWMTC." /> + </BitField> + <BitField start="3" size="1" name="PWMMR1I" description="Interrupt PWM1"> + <Enum name="DISABLED_" start="0" description="Disabled." /> + <Enum name="INTERRUPT_ON_PWMMR1" start="1" description="Interrupt on PWMMR1: an interrupt is generated when PWMMR1 matches the value in the PWMTC." /> + </BitField> + <BitField start="4" size="1" name="PWMMR1R" description="Reset PWM1"> + <Enum name="DISABLED_" start="0" description="Disabled." /> + <Enum name="RESET_ON_PWMMR1_THE" start="1" description="Reset on PWMMR1: the PWMTC will be reset if PWMMR1 matches it." /> + </BitField> + <BitField start="5" size="1" name="PWMMR1S" description="Stop PWM1"> + <Enum name="DISABLED" start="0" description="Disabled" /> + <Enum name="STOP_ON_PWMMR1_THE_" start="1" description="Stop on PWMMR1: the PWMTC and PWMPC will be stopped and PWMTCR bit 0 will be set to 0 if PWMMR1 matches the PWMTC." /> + </BitField> + <BitField start="6" size="1" name="PWMMR2I" description="Interrupt PWM0"> + <Enum name="DISABLED_" start="0" description="Disabled." /> + <Enum name="INTERRUPT_ON_PWMMR2" start="1" description="Interrupt on PWMMR2: an interrupt is generated when PWMMR2 matches the value in the PWMTC." /> + </BitField> + <BitField start="7" size="1" name="PWMMR2R" description="Reset PWM0"> + <Enum name="DISABLED_" start="0" description="Disabled." /> + <Enum name="RESET_ON_PWMMR2_THE" start="1" description="Reset on PWMMR2: the PWMTC will be reset if PWMMR2 matches it." /> + </BitField> + <BitField start="8" size="1" name="PWMMR2S" description="Stop PWM0"> + <Enum name="DISABLED" start="0" description="Disabled" /> + <Enum name="STOP_ON_PWMMR2_THE_" start="1" description="Stop on PWMMR2: the PWMTC and PWMPC will be stopped and PWMTCR bit 0 will be set to 0 if PWMMR0 matches the PWMTC." /> + </BitField> + <BitField start="9" size="1" name="PWMMR3I" description="Interrupt PWM3"> + <Enum name="DISABLED_" start="0" description="Disabled." /> + <Enum name="INTERRUPT_ON_PWMMR3" start="1" description="Interrupt on PWMMR3: an interrupt is generated when PWMMR3 matches the value in the PWMTC." /> + </BitField> + <BitField start="10" size="1" name="PWMMR3R" description="Reset PWM3"> + <Enum name="DISABLED_" start="0" description="Disabled." /> + <Enum name="RESET_ON_PWMMR3_THE" start="1" description="Reset on PWMMR3: the PWMTC will be reset if PWMMR3 matches it." /> + </BitField> + <BitField start="11" size="1" name="PWMMR3S" description="Stop PWM0"> + <Enum name="DISABLED" start="0" description="Disabled" /> + <Enum name="STOP_ON_PWMMR3_THE_" start="1" description="Stop on PWMMR3: the PWMTC and PWMPC will be stopped and PWMTCR bit 0 will be set to 0 if PWMMR0 matches the PWMTC." /> + </BitField> + <BitField start="12" size="1" name="PWMMR4I" description="Interrupt PWM4"> + <Enum name="DISABLED_" start="0" description="Disabled." /> + <Enum name="INTERRUPT_ON_PWMMR4" start="1" description="Interrupt on PWMMR4: an interrupt is generated when PWMMR4 matches the value in the PWMTC." /> + </BitField> + <BitField start="13" size="1" name="PWMMR4R" description="Reset PWM4"> + <Enum name="DISABLED_" start="0" description="Disabled." /> + <Enum name="RESET_ON_PWMMR4_THE" start="1" description="Reset on PWMMR4: the PWMTC will be reset if PWMMR4 matches it." /> + </BitField> + <BitField start="14" size="1" name="PWMMR4S" description="Stop PWM4"> + <Enum name="DISABLED" start="0" description="Disabled" /> + <Enum name="STOP_ON_PWMMR4_THE_" start="1" description="Stop on PWMMR4: the PWMTC and PWMPC will be stopped and PWMTCR bit 0 will be set to 0 if PWMMR4 matches the PWMTC." /> + </BitField> + <BitField start="15" size="1" name="PWMMR5I" description="Interrupt PWM5"> + <Enum name="DISABLED_" start="0" description="Disabled." /> + <Enum name="INTERRUPT_ON_PWMMR5" start="1" description="Interrupt on PWMMR5: an interrupt is generated when PWMMR5 matches the value in the PWMTC." /> + </BitField> + <BitField start="16" size="1" name="PWMMR5R" description="Reset PWM5"> + <Enum name="DISABLED_" start="0" description="Disabled." /> + <Enum name="RESET_ON_PWMMR5_THE" start="1" description="Reset on PWMMR5: the PWMTC will be reset if PWMMR5 matches it." /> + </BitField> + <BitField start="17" size="1" name="PWMMR5S" description="Stop PWM5"> + <Enum name="DISABLED" start="0" description="Disabled" /> + <Enum name="STOP_ON_PWMMR5_THE_" start="1" description="Stop on PWMMR5: the PWMTC and PWMPC will be stopped and PWMTCR bit 0 will be set to 0 if PWMMR5 matches the PWMTC." /> + </BitField> + <BitField start="18" size="1" name="PWMMR6I" description="Interrupt PWM6"> + <Enum name="DISABLED_" start="0" description="Disabled." /> + <Enum name="INTERRUPT_ON_PWMMR6" start="1" description="Interrupt on PWMMR6: an interrupt is generated when PWMMR6 matches the value in the PWMTC." /> + </BitField> + <BitField start="19" size="1" name="PWMMR6R" description="Reset PWM6"> + <Enum name="DISABLED_" start="0" description="Disabled." /> + <Enum name="RESET_ON_PWMMR6_THE" start="1" description="Reset on PWMMR6: the PWMTC will be reset if PWMMR6 matches it." /> + </BitField> + <BitField start="20" size="1" name="PWMMR6S" description="Stop PWM6"> + <Enum name="DISABLED" start="0" description="Disabled" /> + <Enum name="STOP_ON_PWMMR6_THE_" start="1" description="Stop on PWMMR6: the PWMTC and PWMPC will be stopped and PWMTCR bit 0 will be set to 0 if PWMMR6 matches the PWMTC." /> + </BitField> + <BitField start="21" size="11" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x018+0" size="4" name="MR0" access="Read/Write" description="Match Register. Match registers
are continuously compared to the PWM counter in order to control PWM
output edges." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="MATCH" description="Timer counter match value." /> + </Register> + <Register start="+0x018+4" size="4" name="MR1" access="Read/Write" description="Match Register. Match registers
are continuously compared to the PWM counter in order to control PWM
output edges." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="MATCH" description="Timer counter match value." /> + </Register> + <Register start="+0x018+8" size="4" name="MR2" access="Read/Write" description="Match Register. Match registers
are continuously compared to the PWM counter in order to control PWM
output edges." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="MATCH" description="Timer counter match value." /> + </Register> + <Register start="+0x018+12" size="4" name="MR3" access="Read/Write" description="Match Register. Match registers
are continuously compared to the PWM counter in order to control PWM
output edges." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="MATCH" description="Timer counter match value." /> + </Register> + <Register start="+0x028" size="4" name="CCR" access="Read/Write" description="Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated for a capture event." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="CAP0_R" description="Capture on PWMn_CAP0 rising edge"> + <Enum name="DISABLED_THIS_FEATU" start="0" description="Disabled. This feature is disabled." /> + <Enum name="RISING_EDGE_A_SYNCH" start="1" description="Rising edge. A synchronously sampled rising edge on PWMn_CAP0 will cause CR0 to be loaded with the contents of the TC." /> + </BitField> + <BitField start="1" size="1" name="CAP0_F" description="Capture on PWMn_CAP0 falling edge"> + <Enum name="DISABLED_THIS_FEATU" start="0" description="Disabled. This feature is disabled." /> + <Enum name="FALLING_EDGE_A_SYNC" start="1" description="Falling edge. A synchronously sampled falling edge on PWMn_CAP0 will cause CR0 to be loaded with the contents of TC." /> + </BitField> + <BitField start="2" size="1" name="CAP0_I" description="Interrupt on PWMn_CAP0 event"> + <Enum name="DISABLED_THIS_FEATU" start="0" description="Disabled. This feature is disabled." /> + <Enum name="INTERRUPT_A_CR0_LOA" start="1" description="Interrupt. A CR0 load due to a PWMn_CAP0 event will generate an interrupt." /> + </BitField> + <BitField start="3" size="1" name="CAP1_R" description="Capture on PWMn_CAP1 rising edge. Reserved for PWM0."> + <Enum name="DISABLED_THIS_FEATU" start="0" description="Disabled. This feature is disabled." /> + <Enum name="RISING_EDGE_A_SYNCH" start="1" description="Rising edge. A synchronously sampled rising edge on PWMn_CAP1 will cause CR1 to be loaded with the contents of the TC." /> + </BitField> + <BitField start="4" size="1" name="CAP1_F" description="Capture on PWMn_CAP1 falling edge. Reserved for PWM0."> + <Enum name="DISABLED_THIS_FEATU" start="0" description="Disabled. This feature is disabled." /> + <Enum name="FALLING_EDGE_A_SYNC" start="1" description="Falling edge. A synchronously sampled falling edge on PWMn_CAP1 will cause CR1 to be loaded with the contents of TC." /> + </BitField> + <BitField start="5" size="1" name="CAP1_I" description="Interrupt on PWMn_CAP1 event. Reserved for PWM0."> + <Enum name="DISABLED_THIS_FEATU" start="0" description="Disabled. This feature is disabled." /> + <Enum name="INTERRUPT_A_CR1_LOA" start="1" description="Interrupt. A CR1 load due to a PWMn_CAP1 event will generate an interrupt." /> + </BitField> + <BitField start="6" size="26" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x02C+0" size="4" name="CR[0]" access="Read/Write" description="PWM Control Register. Enables PWM outputs and selects either single edge or double edge controlled PWM outputs." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="RESERVED" description="Reserved." /> + <BitField start="2" size="1" name="PWMSEL2" description="PWM[2] output single/double edge mode control."> + <Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." /> + <Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." /> + </BitField> + <BitField start="3" size="1" name="PWMSEL3" description="PWM[3] output edge control."> + <Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." /> + <Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." /> + </BitField> + <BitField start="4" size="1" name="PWMSEL4" description="PWM[4] output edge control."> + <Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." /> + <Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." /> + </BitField> + <BitField start="5" size="1" name="PWMSEL5" description="PWM[5] output edge control."> + <Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." /> + <Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." /> + </BitField> + <BitField start="6" size="1" name="PWMSEL6" description="PWM[6] output edge control."> + <Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." /> + <Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." /> + </BitField> + <BitField start="7" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="9" size="1" name="PWMENA1" description="PWM[1] output enable control."> + <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." /> + <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." /> + </BitField> + <BitField start="10" size="1" name="PWMENA2" description="PWM[2] output enable control."> + <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." /> + <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." /> + </BitField> + <BitField start="11" size="1" name="PWMENA3" description="PWM[3] output enable control."> + <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." /> + <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." /> + </BitField> + <BitField start="12" size="1" name="PWMENA4" description="PWM[4] output enable control."> + <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." /> + <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." /> + </BitField> + <BitField start="13" size="1" name="PWMENA5" description="PWM[5] output enable control."> + <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." /> + <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." /> + </BitField> + <BitField start="14" size="1" name="PWMENA6" description="PWM[6] output enable control. See PWMENA1 for details."> + <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." /> + <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." /> + </BitField> + <BitField start="15" size="17" name="RESERVED" description="Unused, always zero." /> + </Register> + <Register start="+0x02C+4" size="4" name="CR[1]" access="Read/Write" description="PWM Control Register. Enables PWM outputs and selects either single edge or double edge controlled PWM outputs." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="RESERVED" description="Reserved." /> + <BitField start="2" size="1" name="PWMSEL2" description="PWM[2] output single/double edge mode control."> + <Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." /> + <Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." /> + </BitField> + <BitField start="3" size="1" name="PWMSEL3" description="PWM[3] output edge control."> + <Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." /> + <Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." /> + </BitField> + <BitField start="4" size="1" name="PWMSEL4" description="PWM[4] output edge control."> + <Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." /> + <Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." /> + </BitField> + <BitField start="5" size="1" name="PWMSEL5" description="PWM[5] output edge control."> + <Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." /> + <Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." /> + </BitField> + <BitField start="6" size="1" name="PWMSEL6" description="PWM[6] output edge control."> + <Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." /> + <Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." /> + </BitField> + <BitField start="7" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="9" size="1" name="PWMENA1" description="PWM[1] output enable control."> + <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." /> + <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." /> + </BitField> + <BitField start="10" size="1" name="PWMENA2" description="PWM[2] output enable control."> + <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." /> + <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." /> + </BitField> + <BitField start="11" size="1" name="PWMENA3" description="PWM[3] output enable control."> + <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." /> + <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." /> + </BitField> + <BitField start="12" size="1" name="PWMENA4" description="PWM[4] output enable control."> + <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." /> + <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." /> + </BitField> + <BitField start="13" size="1" name="PWMENA5" description="PWM[5] output enable control."> + <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." /> + <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." /> + </BitField> + <BitField start="14" size="1" name="PWMENA6" description="PWM[6] output enable control. See PWMENA1 for details."> + <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." /> + <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." /> + </BitField> + <BitField start="15" size="17" name="RESERVED" description="Unused, always zero." /> + </Register> + <Register start="+0x040+0" size="4" name="MR4" access="Read/Write" description="Match Register. Match registers
are continuously compared to the PWM counter in order to control PWM
output edges." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="MATCH" description="Timer counter match value." /> + </Register> + <Register start="+0x040+4" size="4" name="MR5" access="Read/Write" description="Match Register. Match registers
are continuously compared to the PWM counter in order to control PWM
output edges." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="MATCH" description="Timer counter match value." /> + </Register> + <Register start="+0x040+8" size="4" name="MR6" access="Read/Write" description="Match Register. Match registers
are continuously compared to the PWM counter in order to control PWM
output edges." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="MATCH" description="Timer counter match value." /> + </Register> + <Register start="+0x04C" size="4" name="PCR" access="Read/Write" description="PWM Control Register. Enables PWM outputs and selects either single edge or double edge controlled PWM outputs." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="RESERVED" description="Reserved." /> + <BitField start="2" size="1" name="PWMSEL2" description="PWM[2] output single/double edge mode control."> + <Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." /> + <Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." /> + </BitField> + <BitField start="3" size="1" name="PWMSEL3" description="PWM[3] output edge control."> + <Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." /> + <Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." /> + </BitField> + <BitField start="4" size="1" name="PWMSEL4" description="PWM[4] output edge control."> + <Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." /> + <Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." /> + </BitField> + <BitField start="5" size="1" name="PWMSEL5" description="PWM[5] output edge control."> + <Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." /> + <Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." /> + </BitField> + <BitField start="6" size="1" name="PWMSEL6" description="PWM[6] output edge control."> + <Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." /> + <Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." /> + </BitField> + <BitField start="7" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="9" size="1" name="PWMENA1" description="PWM[1] output enable control."> + <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." /> + <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." /> + </BitField> + <BitField start="10" size="1" name="PWMENA2" description="PWM[2] output enable control."> + <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." /> + <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." /> + </BitField> + <BitField start="11" size="1" name="PWMENA3" description="PWM[3] output enable control."> + <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." /> + <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." /> + </BitField> + <BitField start="12" size="1" name="PWMENA4" description="PWM[4] output enable control."> + <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." /> + <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." /> + </BitField> + <BitField start="13" size="1" name="PWMENA5" description="PWM[5] output enable control."> + <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." /> + <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." /> + </BitField> + <BitField start="14" size="1" name="PWMENA6" description="PWM[6] output enable control. See PWMENA1 for details."> + <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." /> + <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." /> + </BitField> + <BitField start="15" size="17" name="RESERVED" description="Unused, always zero." /> + </Register> + <Register start="+0x050" size="4" name="LER" access="Read/Write" description="Load Enable Register. Enables use of updated PWM match values." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="MAT0LATCHEN" description="Enable PWM Match 0 Latch. PWM MR0 register update control. Writing a one to this bit allows the last value written to the PWM Match Register 0 to be become effective when the timer is next reset by a PWM Match event. See Section 27.6.7." /> + <BitField start="1" size="1" name="MAT1LATCHEN" description="Enable PWM Match 1 Latch. PWM MR1 register update control. See bit 0 for details." /> + <BitField start="2" size="1" name="MAT2LATCHEN" description="Enable PWM Match 2 Latch. PWM MR2 register update control. See bit 0 for details." /> + <BitField start="3" size="1" name="MAT3LATCHEN" description="Enable PWM Match 3 Latch. PWM MR3 register update control. See bit 0 for details." /> + <BitField start="4" size="1" name="MAT4LATCHEN" description="Enable PWM Match 4 Latch. PWM MR4 register update control. See bit 0 for details." /> + <BitField start="5" size="1" name="MAT5LATCHEN" description="Enable PWM Match 5 Latch. PWM MR5 register update control. See bit 0 for details." /> + <BitField start="6" size="1" name="MAT6LATCHEN" description="Enable PWM Match 6 Latch. PWM MR6 register update control. See bit 0 for details." /> + <BitField start="7" size="25" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x070" size="4" name="CTCR" access="Read/Write" description="Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="MOD" description="Counter/ Timer Mode"> + <Enum name="TIMER_MODE_THE_TC_I" start="0x0" description="Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale register." /> + <Enum name="RISING_EDGE_COUNTER_" start="0x1" description="Rising edge counter Mode: the TC is incremented on rising edges of the PWM_CAP input selected by bits 3:2." /> + <Enum name="FALLING_EDGE_COUNTER" start="0x2" description="Falling edge counter Mode: the TC is incremented on falling edges of the PWM_CAP input selected by bits 3:2." /> + <Enum name="DUAL_EDGE_COUNTER_MO" start="0x3" description="Dual edge counter Mode: the TC is incremented on both edges of the PWM_CAP input selected by bits 3:2." /> + </BitField> + <BitField start="2" size="2" name="CIS" description="Count Input Select. When bits 1:0 are not 00, these bits select which PWM_CAP pin carries the signal used to increment the TC. Other combinations are reserved."> + <Enum name="FOR_PWM0_00_EQ_PWM0_" start="0x0" description="For PWM0: 00 = PWM0_CAP0 (Other combinations are reserved) For PWM1: 00 = PWM1_CAP0, 01 = PWM1_CAP1 (Other combinations are reserved)" /> + </BitField> + <BitField start="4" size="28" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + </RegisterGroup> + <RegisterGroup name="I2C0" start="0x4001C000" description="I2C bus interface"> + <Register start="+0x000" size="4" name="CONSET" access="Read/Write" description="I2C Control Set Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is set. Writing a zero has no effect on the corresponding bit in the I2C control register." reset_value="0x00" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + <BitField start="2" size="1" name="AA" description="Assert acknowledge flag." /> + <BitField start="3" size="1" name="SI" description="I2C interrupt flag." /> + <BitField start="4" size="1" name="STO" description="STOP flag." /> + <BitField start="5" size="1" name="STA" description="START flag." /> + <BitField start="6" size="1" name="I2EN" description="I2C interface enable." /> + <BitField start="7" size="25" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x004" size="4" name="STAT" access="ReadOnly" description="I2C Status Register. During I2C operation, this register provides detailed status codes that allow software to determine the next action needed." reset_value="0xF8" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="RESERVED" description="These bits are unused and are always 0." /> + <BitField start="3" size="5" name="Status" description="These bits give the actual status information about the I 2C interface." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x008" size="4" name="DAT" access="Read/Write" description="I2C Data Register. During master or slave transmit mode, data to be transmitted is written to this register. During master or slave receive mode, data that has been received may be read from this register." reset_value="0x00" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="Data" description="This register holds data values that have been received or are to be transmitted." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x00C" size="4" name="ADR0" access="Read/Write" description="I2C Slave Address Register 0. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="GC" description="General Call enable bit." /> + <BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x010" size="4" name="SCLH" access="Read/Write" description="SCH Duty Cycle Register High Half Word. Determines the high time of the I2C clock." reset_value="0x04" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="16" name="SCLH" description="Count for SCL HIGH time period selection." /> + <BitField start="16" size="16" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x014" size="4" name="SCLL" access="Read/Write" description="SCL Duty Cycle Register Low Half Word. Determines the low time of the I2C clock. SCLL and SCLH together determine the clock frequency generated by an I2C master and certain times used in slave mode." reset_value="0x04" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="16" name="SCLL" description="Count for SCL low time period selection." /> + <BitField start="16" size="16" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x018" size="4" name="CONCLR" access="WriteOnly" description="I2C Control Clear Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is cleared. Writing a zero has no effect on the corresponding bit in the I2C control register." reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="2" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + <BitField start="2" size="1" name="AAC" description="Assert acknowledge Clear bit." /> + <BitField start="3" size="1" name="SIC" description="I2C interrupt Clear bit." /> + <BitField start="4" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + <BitField start="5" size="1" name="STAC" description="START flag Clear bit." /> + <BitField start="6" size="1" name="I2ENC" description="I2C interface Disable bit." /> + <BitField start="7" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x01C" size="4" name="MMCTRL" access="Read/Write" description="Monitor mode control register." reset_value="0x00" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="MM_ENA" description="Monitor mode enable."> + <Enum name="MONITOR_MODE_DISABLE" start="0" description="Monitor mode disabled." /> + <Enum name="THE_I_2C_MODULE_WILL" start="1" description="The I 2C module will enter monitor mode. In this mode the SDA output will be forced high. This will prevent the I2C module from outputting data of any kind (including ACK) onto the I2C data bus. Depending on the state of the ENA_SCL bit, the output may be also forced high, preventing the module from having control over the I2C clock line." /> + </BitField> + <BitField start="1" size="1" name="ENA_SCL" description="SCL output enable."> + <Enum name="WHEN_THIS_BIT_IS_CLE" start="0" description="When this bit is cleared to 0, the SCL output will be forced high when the module is in monitor mode. As described above, this will prevent the module from having any control over the I2C clock line." /> + <Enum name="WHEN_THIS_BIT_IS_SET" start="1" description="When this bit is set, the I2C module may exercise the same control over the clock line that it would in normal operation. This means that, acting as a slave peripheral, the I2C module can stretch the clock line (hold it low) until it has had time to respond to an I2C interrupt.[1]" /> + </BitField> + <BitField start="2" size="1" name="MATCH_ALL" description="Select interrupt register match."> + <Enum name="WHEN_THIS_BIT_IS_CLE" start="0" description="When this bit is cleared, an interrupt will only be generated when a match occurs to one of the (up-to) four address registers described above. That is, the module will respond as a normal slave as far as address-recognition is concerned." /> + <Enum name="WHEN_THIS_BIT_IS_SET" start="1" description="When this bit is set to 1 and the I2C is in monitor mode, an interrupt will be generated on ANY address received. This will enable the part to monitor all traffic on the bus." /> + </BitField> + <BitField start="3" size="29" name="RESERVED" description="Reserved. The value read from reserved bits is not defined." /> + </Register> + <Register start="+0x020+0" size="4" name="ADR1" access="Read/Write" description="I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="GC" description="General Call enable bit." /> + <BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x020+4" size="4" name="ADR2" access="Read/Write" description="I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="GC" description="General Call enable bit." /> + <BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x020+8" size="4" name="ADR3" access="Read/Write" description="I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="GC" description="General Call enable bit." /> + <BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x02C" size="4" name="DATA_BUFFER" access="ReadOnly" description="Data buffer register. The contents of the 8 MSBs of the DAT shift register will be transferred to the DATA_BUFFER automatically after every nine bits (8 bits of data plus ACK or NACK) has been received on the bus." reset_value="0x00" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="Data" description="This register holds contents of the 8 MSBs of the DAT shift register." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x030+0" size="4" name="MASK[0]" access="Read/Write" description="I2C Slave address mask register" reset_value="0x00" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." /> + <BitField start="1" size="7" name="MASK" description="Mask bits." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x030+4" size="4" name="MASK[1]" access="Read/Write" description="I2C Slave address mask register" reset_value="0x00" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." /> + <BitField start="1" size="7" name="MASK" description="Mask bits." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x030+8" size="4" name="MASK[2]" access="Read/Write" description="I2C Slave address mask register" reset_value="0x00" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." /> + <BitField start="1" size="7" name="MASK" description="Mask bits." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x030+12" size="4" name="MASK[3]" access="Read/Write" description="I2C Slave address mask register" reset_value="0x00" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." /> + <BitField start="1" size="7" name="MASK" description="Mask bits." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + </RegisterGroup> + <RegisterGroup name="SPI" start="0x40020000" description="SPI "> + <Register start="+0x000" size="4" name="CR" access="Read/Write" description="SPI Control Register. This register controls the operation of the SPI." reset_value="0x00" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + <BitField start="2" size="1" name="BITENABLE" description="The SPI controller sends and receives 8 bits of data per transfer."> + <Enum name="THE_SPI_CONTROLLER_S" start="1" description="The SPI controller sends and receives the number of bits selected by bits 11:8." /> + </BitField> + <BitField start="3" size="1" name="CPHA" description="Clock phase control determines the relationship between the data and the clock on SPI transfers, and controls when a slave transfer is defined as starting and ending."> + <Enum name="FIRST_EDGE" start="0" description="Data is sampled on the first clock edge of SCK. A transfer starts and ends with activation and deactivation of the SSEL signal." /> + <Enum name="SECOND_EDGE" start="1" description="Data is sampled on the second clock edge of the SCK. A transfer starts with the first clock edge, and ends with the last sampling edge when the SSEL signal is active." /> + </BitField> + <BitField start="4" size="1" name="CPOL" description="Clock polarity control."> + <Enum name="SCK_IS_ACTIVE_HIGH_" start="0" description="SCK is active high." /> + <Enum name="SCK_IS_ACTIVE_LOW_" start="1" description="SCK is active low." /> + </BitField> + <BitField start="5" size="1" name="MSTR" description="Master mode select."> + <Enum name="SLAVE" start="0" description="The SPI operates in Slave mode." /> + <Enum name="MASTER" start="1" description="The SPI operates in Master mode." /> + </BitField> + <BitField start="6" size="1" name="LSBF" description="LSB First controls which direction each byte is shifted when transferred."> + <Enum name="MSB" start="0" description="SPI data is transferred MSB (bit 7) first." /> + <Enum name="LSB" start="1" description="SPI data is transferred LSB (bit 0) first." /> + </BitField> + <BitField start="7" size="1" name="SPIE" description="Serial peripheral interrupt enable."> + <Enum name="INTBLOCK" start="0" description="SPI interrupts are inhibited." /> + <Enum name="HWINT" start="1" description="A hardware interrupt is generated each time the SPIF or MODF bits are activated." /> + </BitField> + <BitField start="8" size="4" name="BITS" description="When bit 2 of this register is 1, this field controls the number of bits per transfer:"> + <Enum name="8_BITS_PER_TRANSFER" start="0x8" description="8 bits per transfer" /> + <Enum name="9_BITS_PER_TRANSFER" start="0x9" description="9 bits per transfer" /> + <Enum name="10_BITS_PER_TRANSFER" start="0xA" description="10 bits per transfer" /> + <Enum name="11_BITS_PER_TRANSFER" start="0xB" description="11 bits per transfer" /> + <Enum name="12_BITS_PER_TRANSFER" start="0xC" description="12 bits per transfer" /> + <Enum name="13_BITS_PER_TRANSFER" start="0xD" description="13 bits per transfer" /> + <Enum name="14_BITS_PER_TRANSFER" start="0xE" description="14 bits per transfer" /> + <Enum name="15_BITS_PER_TRANSFER" start="0xF" description="15 bits per transfer" /> + <Enum name="16_BITS_PER_TRANSFER" start="0x0" description="16 bits per transfer" /> + </BitField> + <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x004" size="4" name="SR" access="ReadOnly" description="SPI Status Register. This register shows the status of the SPI." reset_value="0x00" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + <BitField start="3" size="1" name="ABRT" description="Slave abort. When 1, this bit indicates that a slave abort has occurred. This bit is cleared by reading this register." /> + <BitField start="4" size="1" name="MODF" description="Mode fault. when 1, this bit indicates that a Mode fault error has occurred. This bit is cleared by reading this register, then writing the SPI0 control register." /> + <BitField start="5" size="1" name="ROVR" description="Read overrun. When 1, this bit indicates that a read overrun has occurred. This bit is cleared by reading this register." /> + <BitField start="6" size="1" name="WCOL" description="Write collision. When 1, this bit indicates that a write collision has occurred. This bit is cleared by reading this register, then accessing the SPI Data Register." /> + <BitField start="7" size="1" name="SPIF" description="SPI transfer complete flag. When 1, this bit indicates when a SPI data transfer is complete. When a master, this bit is set at the end of the last cycle of the transfer. When a slave, this bit is set on the last data sampling edge of the SCK. This bit is cleared by first reading this register, then accessing the SPI Data Register. Note: this is not the SPI interrupt flag. This flag is found in the SPINT register." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x008" size="4" name="DR" access="None" description="SPI Data Register. This bi-directional register provides the transmit and receive data for the SPI. Transmit data is provided to the SPI0 by writing to this register. Data received by the SPI0 can be read from this register." reset_value="0x00" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="DATALOW" description="SPI Bi-directional data port." /> + <BitField start="8" size="8" name="DATAHIGH" description="If bit 2 of the SPCR is 1 and bits 11:8 are other than 1000, some or all of these bits contain the additional transmit and receive bits. When less than 16 bits are selected, the more significant among these bits read as zeroes." /> + <BitField start="16" size="16" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x00C" size="4" name="CCR" access="Read/Write" description="SPI Clock Counter Register. This register controls the frequency of a master's SCK0." reset_value="0x00" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="COUNTER" description="SPI0 Clock counter setting." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x01C" size="4" name="INT" access="Read/Write" description="SPI Interrupt Flag. This register contains the interrupt flag for the SPI interface." reset_value="0x00" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="SPIF" description="SPI interrupt flag. Set by the SPI interface to generate an interrupt. Cleared by writing a 1 to this bit. Note: this bit will be set once when SPIE = 1 and at least one of SPIF and WCOL bits is 1. However, only when the SPI Interrupt bit is set and SPI0 Interrupt is enabled in the NVIC, SPI based interrupt can be processed by interrupt handling software." /> + <BitField start="1" size="7" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + </RegisterGroup> + <RegisterGroup name="RTC" start="0x40024000" description=" Real Time Clock (RTC) "> + <Register start="+0x000" size="4" name="ILR" access="Read/Write" description="Interrupt Location Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RTCCIF" description="When one, the Counter Increment Interrupt block generated an interrupt. Writing a one to this bit location clears the counter increment interrupt." /> + <BitField start="1" size="1" name="RTCALF" description="When one, the alarm registers generated an interrupt. Writing a one to this bit location clears the alarm interrupt." /> + <BitField start="21" size="11" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x008" size="4" name="CCR" access="Read/Write" description="Clock Control Register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="CLKEN" description="Clock Enable."> + <Enum name="THE_TIME_COUNTERS_AR" start="1" description="The time counters are enabled." /> + <Enum name="THE_TIME_COUNTERS_AR" start="0" description="The time counters are disabled so that they may be initialized." /> + </BitField> + <BitField start="1" size="1" name="CTCRST" description="CTC Reset."> + <Enum name="RESET" start="1" description="When one, the elements in the internal oscillator divider are reset, and remain reset until CCR[1] is changed to zero. This is the divider that generates the 1 Hz clock from the 32.768 kHz crystal. The state of the divider is not visible to software." /> + <Enum name="NO_EFFECT_" start="0" description="No effect." /> + </BitField> + <BitField start="2" size="2" name="RESERVED" description="Internal test mode controls. These bits must be 0 for normal RTC operation." /> + <BitField start="4" size="1" name="CCALEN" description="Calibration counter enable."> + <Enum name="THE_CALIBRATION_COUN" start="1" description="The calibration counter is disabled and reset to zero." /> + <Enum name="THE_CALIBRATION_COUN" start="0" description="The calibration counter is enabled and counting, using the 1 Hz clock. When the calibration counter is equal to the value of the CALIBRATION register, the counter resets and repeats counting up to the value of the CALIBRATION register. See Section 30.6.4.2 and Section 30.6.5." /> + </BitField> + <BitField start="5" size="27" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x00C" size="4" name="CIIR" access="Read/Write" description="Counter Increment Interrupt Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="IMSEC" description="When 1, an increment of the Second value generates an interrupt." /> + <BitField start="1" size="1" name="IMMIN" description="When 1, an increment of the Minute value generates an interrupt." /> + <BitField start="2" size="1" name="IMHOUR" description="When 1, an increment of the Hour value generates an interrupt." /> + <BitField start="3" size="1" name="IMDOM" description="When 1, an increment of the Day of Month value generates an interrupt." /> + <BitField start="4" size="1" name="IMDOW" description="When 1, an increment of the Day of Week value generates an interrupt." /> + <BitField start="5" size="1" name="IMDOY" description="When 1, an increment of the Day of Year value generates an interrupt." /> + <BitField start="6" size="1" name="IMMON" description="When 1, an increment of the Month value generates an interrupt." /> + <BitField start="7" size="1" name="IMYEAR" description="When 1, an increment of the Year value generates an interrupt." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x010" size="4" name="AMR" access="Read/Write" description="Alarm Mask Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="AMRSEC" description="When 1, the Second value is not compared for the alarm." /> + <BitField start="1" size="1" name="AMRMIN" description="When 1, the Minutes value is not compared for the alarm." /> + <BitField start="2" size="1" name="AMRHOUR" description="When 1, the Hour value is not compared for the alarm." /> + <BitField start="3" size="1" name="AMRDOM" description="When 1, the Day of Month value is not compared for the alarm." /> + <BitField start="4" size="1" name="AMRDOW" description="When 1, the Day of Week value is not compared for the alarm." /> + <BitField start="5" size="1" name="AMRDOY" description="When 1, the Day of Year value is not compared for the alarm." /> + <BitField start="6" size="1" name="AMRMON" description="When 1, the Month value is not compared for the alarm." /> + <BitField start="7" size="1" name="AMRYEAR" description="When 1, the Year value is not compared for the alarm." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x014" size="4" name="CTIME0" access="ReadOnly" description="Consolidated Time Register 0" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="6" name="SECONDS" description="Seconds value in the range of 0 to 59" /> + <BitField start="6" size="2" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + <BitField start="8" size="6" name="MINUTES" description="Minutes value in the range of 0 to 59" /> + <BitField start="14" size="2" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + <BitField start="16" size="5" name="HOURS" description="Hours value in the range of 0 to 23" /> + <BitField start="21" size="3" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + <BitField start="24" size="3" name="DOW" description="Day of week value in the range of 0 to 6" /> + <BitField start="27" size="5" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x018" size="4" name="CTIME1" access="ReadOnly" description="Consolidated Time Register 1" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="5" name="DOM" description="Day of month value in the range of 1 to 28, 29, 30, or 31 (depending on the month and whether it is a leap year)." /> + <BitField start="5" size="3" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + <BitField start="8" size="4" name="MONTH" description="Month value in the range of 1 to 12." /> + <BitField start="12" size="4" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + <BitField start="16" size="12" name="YEAR" description="Year value in the range of 0 to 4095." /> + <BitField start="28" size="4" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x01C" size="4" name="CTIME2" access="ReadOnly" description="Consolidated Time Register 2" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="12" name="DOY" description="Day of year value in the range of 1 to 365 (366 for leap years)." /> + <BitField start="12" size="20" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x020" size="4" name="SEC" access="Read/Write" description="Seconds Counter" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="6" name="SECONDS" description="Seconds value in the range of 0 to 59" /> + <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x024" size="4" name="MIN" access="Read/Write" description="Minutes Register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="6" name="MINUTES" description="Minutes value in the range of 0 to 59" /> + <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x028" size="4" name="HRS" access="Read/Write" description="Hours Register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="5" name="HOURS" description="Hours value in the range of 0 to 23" /> + <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x02C" size="4" name="DOM" access="Read/Write" description="Day of Month Register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="5" name="DOM" description="Day of month value in the range of 1 to 28, 29, 30, or 31 (depending on the month and whether it is a leap year)." /> + <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x030" size="4" name="DOW" access="Read/Write" description="Day of Week Register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="3" name="DOW" description="Day of week value in the range of 0 to 6." /> + <BitField start="3" size="29" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x034" size="4" name="DOY" access="Read/Write" description="Day of Year Register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="9" name="DOY" description="Day of year value in the range of 1 to 365 (366 for leap years)." /> + <BitField start="9" size="23" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x038" size="4" name="MONTH" access="Read/Write" description="Months Register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="4" name="MONTH" description="Month value in the range of 1 to 12." /> + <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x03C" size="4" name="YEAR" access="Read/Write" description="Years Register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="12" name="YEAR" description="Year value in the range of 0 to 4095." /> + <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x040" size="4" name="CALIBRATION" access="Read/Write" description="Calibration Value Register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="17" name="CALVAL" description="If enabled, the calibration counter counts up to this value. The maximum value is 131, 072 corresponding to about 36.4 hours. Calibration is disabled if CALVAL = 0." /> + <BitField start="17" size="1" name="CALDIR" description="Calibration direction"> + <Enum name="BACKWARD_CALIBRATION" start="1" description="Backward calibration. When CALVAL is equal to the calibration counter, the RTC timers will stop incrementing for 1 second." /> + <Enum name="FORWARD_CALIBRATION_" start="0" description="Forward calibration. When CALVAL is equal to the calibration counter, the RTC timers will jump by 2 seconds." /> + </BitField> + </Register> + <Register start="+0x044+0" size="4" name="GPREG0" access="Read/Write" description="General Purpose Register 0" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="GP" description="General purpose storage." /> + </Register> + <Register start="+0x044+4" size="4" name="GPREG1" access="Read/Write" description="General Purpose Register 0" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="GP" description="General purpose storage." /> + </Register> + <Register start="+0x044+8" size="4" name="GPREG2" access="Read/Write" description="General Purpose Register 0" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="GP" description="General purpose storage." /> + </Register> + <Register start="+0x044+12" size="4" name="GPREG3" access="Read/Write" description="General Purpose Register 0" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="GP" description="General purpose storage." /> + </Register> + <Register start="+0x044+16" size="4" name="GPREG4" access="Read/Write" description="General Purpose Register 0" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="GP" description="General purpose storage." /> + </Register> + <Register start="+0x05C" size="4" name="RTC_AUX" access="Read/Write" description="RTC Auxiliary control register" reset_value="0x10" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="4" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="4" size="1" name="RTC_OSCF" description="RTC Oscillator Fail detect flag. Read: this bit is set if the RTC oscillator stops, and when RTC power is first turned on. An interrupt will occur when this bit is set, the RTC_OSCFEN bit in RTC_AUXEN is a 1, and the RTC interrupt is enabled in the NVIC. Write: writing a 1 to this bit clears the flag." /> + <BitField start="5" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="6" size="1" name="RTC_PDOUT" description="When 0: the RTC_ALARM pin reflects the RTC alarm status. When 1: the RTC_ALARM pin indicates Deep Power-down mode." /> + <BitField start="7" size="25" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x058" size="4" name="RTC_AUXEN" access="Read/Write" description="RTC Auxiliary Enable register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="4" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="4" size="1" name="RTC_OSCFEN" description="Oscillator Fail Detect interrupt enable. When 0: the RTC Oscillator Fail detect interrupt is disabled. When 1: the RTC Oscillator Fail detect interrupt is enabled. See Section 30.6.2.5." /> + <BitField start="5" size="27" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x060" size="4" name="ASEC" access="Read/Write" description="Alarm value for Seconds" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="6" name="SECONDS" description="Seconds value in the range of 0 to 59" /> + <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x64" size="4" name="AMIN" access="Read/Write" description="Alarm value for Minutes" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="6" name="MINUTES" description="Minutes value in the range of 0 to 59" /> + <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x068" size="4" name="AHRS" access="Read/Write" description="Alarm value for Hours" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="5" name="HOURS" description="Hours value in the range of 0 to 23" /> + <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x06C" size="4" name="ADOM" access="Read/Write" description="Alarm value for Day of Month" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="5" name="DOM" description="Day of month value in the range of 1 to 28, 29, 30, or 31 (depending on the month and whether it is a leap year)." /> + <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x070" size="4" name="ADOW" access="Read/Write" description="Alarm value for Day of Week" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="3" name="DOW" description="Day of week value in the range of 0 to 6." /> + <BitField start="3" size="29" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x074" size="4" name="ADOY" access="Read/Write" description="Alarm value for Day of Year" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="9" name="DOY" description="Day of year value in the range of 1 to 365 (366 for leap years)." /> + <BitField start="9" size="23" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x078" size="4" name="AMON" access="Read/Write" description="Alarm value for Months" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="4" name="MONTH" description="Month value in the range of 1 to 12." /> + <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x07C" size="4" name="AYRS" access="Read/Write" description="Alarm value for Year" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="12" name="YEAR" description="Year value in the range of 0 to 4095." /> + <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + </RegisterGroup> + <RegisterGroup name="GPIOINT" start="0x40028080" description="GPIO"> + <Register start="+0x000" size="4" name="STATUS" access="ReadOnly" description="GPIO overall Interrupt Status." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="P0INT" description="Port 0 GPIO interrupt pending."> + <Enum name="NO_PENDING_INTERRUPT" start="0" description="No pending interrupts on Port 0." /> + <Enum name="AT_LEAST_ONE_PENDING" start="1" description="At least one pending interrupt on Port 0." /> + </BitField> + <BitField start="1" size="1" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + <BitField start="2" size="1" name="P2INT" description="Port 2 GPIO interrupt pending."> + <Enum name="NO_PENDING_INTERRUPT" start="0" description="No pending interrupts on Port 2." /> + <Enum name="AT_LEAST_ONE_PENDING" start="1" description="At least one pending interrupt on Port 2." /> + </BitField> + <BitField start="2" size="30" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x004" size="4" name="STATR0" access="ReadOnly" description="GPIO Interrupt Status for Rising edge for Port 0." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="P0_0REI" description="Status of Rising Edge Interrupt for P0[0]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." /> + <BitField start="1" size="1" name="P0_1REI" description="Status of Rising Edge Interrupt for P0[1]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." /> + <BitField start="2" size="1" name="P0_2REI" description="Status of Rising Edge Interrupt for P0[2]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." /> + <BitField start="3" size="1" name="P0_3REI" description="Status of Rising Edge Interrupt for P0[3]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." /> + <BitField start="4" size="1" name="P0_4REI" description="Status of Rising Edge Interrupt for P0[4]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." /> + <BitField start="5" size="1" name="P0_5REI" description="Status of Rising Edge Interrupt for P0[5]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." /> + <BitField start="6" size="1" name="P0_6REI" description="Status of Rising Edge Interrupt for P0[6]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." /> + <BitField start="7" size="1" name="P0_7REI" description="Status of Rising Edge Interrupt for P0[7]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." /> + <BitField start="8" size="1" name="P0_8REI" description="Status of Rising Edge Interrupt for P0[8]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." /> + <BitField start="9" size="1" name="P0_9REI" description="Status of Rising Edge Interrupt for P0[9]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." /> + <BitField start="10" size="1" name="P0_10REI" description="Status of Rising Edge Interrupt for P0[10]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." /> + <BitField start="11" size="1" name="P0_11REI" description="Status of Rising Edge Interrupt for P0[11]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." /> + <BitField start="12" size="1" name="P0_12REI" description="Status of Rising Edge Interrupt for P0[12]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." /> + <BitField start="13" size="1" name="P0_13REI" description="Status of Rising Edge Interrupt for P0[13]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." /> + <BitField start="14" size="1" name="P0_14REI" description="Status of Rising Edge Interrupt for P0[14]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." /> + <BitField start="15" size="1" name="P0_15REI" description="Status of Rising Edge Interrupt for P0[15]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." /> + <BitField start="16" size="1" name="P0_16REI" description="Status of Rising Edge Interrupt for P0[16]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." /> + <BitField start="17" size="1" name="P0_17REI" description="Status of Rising Edge Interrupt for P0[17]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." /> + <BitField start="18" size="1" name="P0_18REI" description="Status of Rising Edge Interrupt for P0[18]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." /> + <BitField start="19" size="1" name="P0_19REI" description="Status of Rising Edge Interrupt for P0[19]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." /> + <BitField start="20" size="1" name="P0_20REI" description="Status of Rising Edge Interrupt for P0[20]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." /> + <BitField start="21" size="1" name="P0_21REI" description="Status of Rising Edge Interrupt for P0[21]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." /> + <BitField start="22" size="1" name="P0_22REI" description="Status of Rising Edge Interrupt for P0[22]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." /> + <BitField start="23" size="1" name="P0_23REI" description="Status of Rising Edge Interrupt for P0[23]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." /> + <BitField start="24" size="1" name="P0_24REI" description="Status of Rising Edge Interrupt for P0[24]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." /> + <BitField start="25" size="1" name="P0_25REI" description="Status of Rising Edge Interrupt for P0[25]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." /> + <BitField start="26" size="1" name="P0_26REI" description="Status of Rising Edge Interrupt for P0[26]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." /> + <BitField start="27" size="1" name="P0_27REI" description="Status of Rising Edge Interrupt for P0[27]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." /> + <BitField start="28" size="1" name="P0_28REI" description="Status of Rising Edge Interrupt for P0[28]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." /> + <BitField start="29" size="1" name="P0_29REI" description="Status of Rising Edge Interrupt for P0[29]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." /> + <BitField start="30" size="1" name="P0_30REI" description="Status of Rising Edge Interrupt for P0[30]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." /> + <BitField start="31" size="1" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x008" size="4" name="STATF0" access="ReadOnly" description="GPIO Interrupt Status for Falling edge for Port 0." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="P0_0FEI" description="Status of Falling Edge Interrupt for P0[0]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." /> + <BitField start="1" size="1" name="P0_1FEI" description="Status of Falling Edge Interrupt for P0[1]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." /> + <BitField start="2" size="1" name="P0_2FEI" description="Status of Falling Edge Interrupt for P0[2]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." /> + <BitField start="3" size="1" name="P0_3FEI" description="Status of Falling Edge Interrupt for P0[3]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." /> + <BitField start="4" size="1" name="P0_4FEI" description="Status of Falling Edge Interrupt for P0[4]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." /> + <BitField start="5" size="1" name="P0_5FEI" description="Status of Falling Edge Interrupt for P0[5]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." /> + <BitField start="6" size="1" name="P0_6FEI" description="Status of Falling Edge Interrupt for P0[6]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." /> + <BitField start="7" size="1" name="P0_7FEI" description="Status of Falling Edge Interrupt for P0[7]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." /> + <BitField start="8" size="1" name="P0_8FEI" description="Status of Falling Edge Interrupt for P0[8]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." /> + <BitField start="9" size="1" name="P0_9FEI" description="Status of Falling Edge Interrupt for P0[9]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." /> + <BitField start="10" size="1" name="P0_10FEI" description="Status of Falling Edge Interrupt for P0[10]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." /> + <BitField start="11" size="1" name="P0_11FEI" description="Status of Falling Edge Interrupt for P0[11]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." /> + <BitField start="12" size="1" name="P0_12FEI" description="Status of Falling Edge Interrupt for P0[12]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." /> + <BitField start="13" size="1" name="P0_13FEI" description="Status of Falling Edge Interrupt for P0[13]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." /> + <BitField start="14" size="1" name="P0_14FEI" description="Status of Falling Edge Interrupt for P0[14]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." /> + <BitField start="15" size="1" name="P0_15FEI" description="Status of Falling Edge Interrupt for P0[15]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." /> + <BitField start="16" size="1" name="P0_16FEI" description="Status of Falling Edge Interrupt for P0[16]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." /> + <BitField start="17" size="1" name="P0_17FEI" description="Status of Falling Edge Interrupt for P0[17]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." /> + <BitField start="18" size="1" name="P0_18FEI" description="Status of Falling Edge Interrupt for P0[18]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." /> + <BitField start="19" size="1" name="P0_19FEI" description="Status of Falling Edge Interrupt for P0[19]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." /> + <BitField start="20" size="1" name="P0_20FEI" description="Status of Falling Edge Interrupt for P0[20]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." /> + <BitField start="21" size="1" name="P0_21FEI" description="Status of Falling Edge Interrupt for P0[21]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." /> + <BitField start="22" size="1" name="P0_22FEI" description="Status of Falling Edge Interrupt for P0[22]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." /> + <BitField start="23" size="1" name="P0_23FEI" description="Status of Falling Edge Interrupt for P0[23]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." /> + <BitField start="24" size="1" name="P0_24FEI" description="Status of Falling Edge Interrupt for P0[24]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." /> + <BitField start="25" size="1" name="P0_25FEI" description="Status of Falling Edge Interrupt for P0[25]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." /> + <BitField start="26" size="1" name="P0_26FEI" description="Status of Falling Edge Interrupt for P0[26]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." /> + <BitField start="27" size="1" name="P0_27FEI" description="Status of Falling Edge Interrupt for P0[27]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." /> + <BitField start="28" size="1" name="P0_28FEI" description="Status of Falling Edge Interrupt for P0[28]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." /> + <BitField start="29" size="1" name="P0_29FEI" description="Status of Falling Edge Interrupt for P0[29]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." /> + <BitField start="30" size="1" name="P0_30FEI" description="Status of Falling Edge Interrupt for P0[30]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." /> + <BitField start="31" size="1" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x00C" size="4" name="CLR0" access="WriteOnly" description="GPIO Interrupt Clear." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="P0_0CI" description="Clear GPIO port Interrupts for P0[0]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." /> + <BitField start="1" size="1" name="P0_1CI" description="Clear GPIO port Interrupts for P0[1]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." /> + <BitField start="2" size="1" name="P0_2CI" description="Clear GPIO port Interrupts for P0[2]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." /> + <BitField start="3" size="1" name="P0_3CI" description="Clear GPIO port Interrupts for P0[3]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." /> + <BitField start="4" size="1" name="P0_4CI" description="Clear GPIO port Interrupts for P0[4]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." /> + <BitField start="5" size="1" name="P0_5CI" description="Clear GPIO port Interrupts for P0[5]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." /> + <BitField start="6" size="1" name="P0_6CI" description="Clear GPIO port Interrupts for P0[6]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." /> + <BitField start="7" size="1" name="P0_7CI" description="Clear GPIO port Interrupts for P0[7]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." /> + <BitField start="8" size="1" name="P0_8CI" description="Clear GPIO port Interrupts for P0[8]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." /> + <BitField start="9" size="1" name="P0_9CI" description="Clear GPIO port Interrupts for P0[9]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." /> + <BitField start="10" size="1" name="P0_10CI" description="Clear GPIO port Interrupts for P0[10]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." /> + <BitField start="11" size="1" name="P0_11CI" description="Clear GPIO port Interrupts for P0[11]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." /> + <BitField start="12" size="1" name="P0_12CI" description="Clear GPIO port Interrupts for P0[12]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." /> + <BitField start="13" size="1" name="P0_13CI" description="Clear GPIO port Interrupts for P0[13]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." /> + <BitField start="14" size="1" name="P0_14CI" description="Clear GPIO port Interrupts for P0[14]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." /> + <BitField start="15" size="1" name="P0_15CI" description="Clear GPIO port Interrupts for P0[15]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." /> + <BitField start="16" size="1" name="P0_16CI" description="Clear GPIO port Interrupts for P0[16]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." /> + <BitField start="17" size="1" name="P0_17CI" description="Clear GPIO port Interrupts for P0[17]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." /> + <BitField start="18" size="1" name="P0_18CI" description="Clear GPIO port Interrupts for P0[18]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." /> + <BitField start="19" size="1" name="P0_19CI" description="Clear GPIO port Interrupts for P0[19]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." /> + <BitField start="20" size="1" name="P0_20CI" description="Clear GPIO port Interrupts for P0[20]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." /> + <BitField start="21" size="1" name="P0_21CI" description="Clear GPIO port Interrupts for P0[21]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." /> + <BitField start="22" size="1" name="P0_22CI" description="Clear GPIO port Interrupts for P0[22]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." /> + <BitField start="23" size="1" name="P0_23CI" description="Clear GPIO port Interrupts for P0[23]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." /> + <BitField start="24" size="1" name="P0_24CI" description="Clear GPIO port Interrupts for P0[24]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." /> + <BitField start="25" size="1" name="P0_25CI" description="Clear GPIO port Interrupts for P0[25]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." /> + <BitField start="26" size="1" name="P0_26CI" description="Clear GPIO port Interrupts for P0[26]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." /> + <BitField start="27" size="1" name="P0_27CI" description="Clear GPIO port Interrupts for P0[27]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." /> + <BitField start="28" size="1" name="P0_28CI" description="Clear GPIO port Interrupts for P0[28]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." /> + <BitField start="29" size="1" name="P0_29CI" description="Clear GPIO port Interrupts for P0[29]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." /> + <BitField start="30" size="1" name="P0_30CI" description="Clear GPIO port Interrupts for P0[30]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." /> + <BitField start="31" size="1" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x010" size="4" name="ENR0" access="Read/Write" description="GPIO Interrupt Enable for Rising edge for Port 0." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="P0_0ER" description="Enable rising edge interrupt for P0[0]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." /> + <BitField start="1" size="1" name="P0_1ER" description="Enable rising edge interrupt for P0[1]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." /> + <BitField start="2" size="1" name="P0_2ER" description="Enable rising edge interrupt for P0[2]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." /> + <BitField start="3" size="1" name="P0_3ER" description="Enable rising edge interrupt for P0[3]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." /> + <BitField start="4" size="1" name="P0_4ER" description="Enable rising edge interrupt for P0[4]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." /> + <BitField start="5" size="1" name="P0_5ER" description="Enable rising edge interrupt for P0[5]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." /> + <BitField start="6" size="1" name="P0_6ER" description="Enable rising edge interrupt for P0[6]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." /> + <BitField start="7" size="1" name="P0_7ER" description="Enable rising edge interrupt for P0[7]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." /> + <BitField start="8" size="1" name="P0_8ER" description="Enable rising edge interrupt for P0[8]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." /> + <BitField start="9" size="1" name="P0_9ER" description="Enable rising edge interrupt for P0[9]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." /> + <BitField start="10" size="1" name="P0_10ER" description="Enable rising edge interrupt for P0[10]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." /> + <BitField start="11" size="1" name="P0_11ER" description="Enable rising edge interrupt for P0[11]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." /> + <BitField start="12" size="1" name="P0_12ER" description="Enable rising edge interrupt for P0[12]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." /> + <BitField start="13" size="1" name="P0_13ER" description="Enable rising edge interrupt for P0[13]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." /> + <BitField start="14" size="1" name="P0_14ER" description="Enable rising edge interrupt for P0[14]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." /> + <BitField start="15" size="1" name="P0_15ER" description="Enable rising edge interrupt for P0[15]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." /> + <BitField start="16" size="1" name="P0_16ER" description="Enable rising edge interrupt for P0[16]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." /> + <BitField start="17" size="1" name="P0_17ER" description="Enable rising edge interrupt for P0[17]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." /> + <BitField start="18" size="1" name="P0_18ER" description="Enable rising edge interrupt for P0[18]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." /> + <BitField start="19" size="1" name="P0_19ER" description="Enable rising edge interrupt for P0[19]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." /> + <BitField start="20" size="1" name="P0_20ER" description="Enable rising edge interrupt for P0[20]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." /> + <BitField start="21" size="1" name="P0_21ER" description="Enable rising edge interrupt for P0[21]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." /> + <BitField start="22" size="1" name="P0_22ER" description="Enable rising edge interrupt for P0[22]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." /> + <BitField start="23" size="1" name="P0_23ER" description="Enable rising edge interrupt for P0[23]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." /> + <BitField start="24" size="1" name="P0_24ER" description="Enable rising edge interrupt for P0[24]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." /> + <BitField start="25" size="1" name="P0_25ER" description="Enable rising edge interrupt for P0[25]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." /> + <BitField start="26" size="1" name="P0_26ER" description="Enable rising edge interrupt for P0[26]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." /> + <BitField start="27" size="1" name="P0_27ER" description="Enable rising edge interrupt for P0[27]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." /> + <BitField start="28" size="1" name="P0_28ER" description="Enable rising edge interrupt for P0[28]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." /> + <BitField start="29" size="1" name="P0_29ER" description="Enable rising edge interrupt for P0[29]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." /> + <BitField start="30" size="1" name="P0_30ER" description="Enable rising edge interrupt for P0[30]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." /> + <BitField start="31" size="1" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x014" size="4" name="ENF0" access="Read/Write" description="GPIO Interrupt Enable for Falling edge for Port 0." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="P0_0EF" description="Enable falling edge interrupt for P0[0]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." /> + <BitField start="1" size="1" name="P0_1EF" description="Enable falling edge interrupt for P0[1]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." /> + <BitField start="2" size="1" name="P0_2EF" description="Enable falling edge interrupt for P0[2]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." /> + <BitField start="3" size="1" name="P0_3EF" description="Enable falling edge interrupt for P0[3]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." /> + <BitField start="4" size="1" name="P0_4EF" description="Enable falling edge interrupt for P0[4]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." /> + <BitField start="5" size="1" name="P0_5EF" description="Enable falling edge interrupt for P0[5]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." /> + <BitField start="6" size="1" name="P0_6EF" description="Enable falling edge interrupt for P0[6]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." /> + <BitField start="7" size="1" name="P0_7EF" description="Enable falling edge interrupt for P0[7]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." /> + <BitField start="8" size="1" name="P0_8EF" description="Enable falling edge interrupt for P0[8]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." /> + <BitField start="9" size="1" name="P0_9EF" description="Enable falling edge interrupt for P0[9]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." /> + <BitField start="10" size="1" name="P0_10EF" description="Enable falling edge interrupt for P0[10]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." /> + <BitField start="11" size="1" name="P0_11EF" description="Enable falling edge interrupt for P0[11]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." /> + <BitField start="12" size="1" name="P0_12EF" description="Enable falling edge interrupt for P0[12]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." /> + <BitField start="13" size="1" name="P0_13EF" description="Enable falling edge interrupt for P0[13]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." /> + <BitField start="14" size="1" name="P0_14EF" description="Enable falling edge interrupt for P0[14]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." /> + <BitField start="15" size="1" name="P0_15EF" description="Enable falling edge interrupt for P0[15]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." /> + <BitField start="16" size="1" name="P0_16EF" description="Enable falling edge interrupt for P0[16]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." /> + <BitField start="17" size="1" name="P0_17EF" description="Enable falling edge interrupt for P0[17]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." /> + <BitField start="18" size="1" name="P0_18EF" description="Enable falling edge interrupt for P0[18]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." /> + <BitField start="19" size="1" name="P0_19EF" description="Enable falling edge interrupt for P0[19]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." /> + <BitField start="20" size="1" name="P0_20EF" description="Enable falling edge interrupt for P0[20]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." /> + <BitField start="21" size="1" name="P0_21EF" description="Enable falling edge interrupt for P0[21]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." /> + <BitField start="22" size="1" name="P0_22EF" description="Enable falling edge interrupt for P0[22]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." /> + <BitField start="23" size="1" name="P0_23EF" description="Enable falling edge interrupt for P0[23]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." /> + <BitField start="24" size="1" name="P0_24EF" description="Enable falling edge interrupt for P0[24]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." /> + <BitField start="25" size="1" name="P0_25EF" description="Enable falling edge interrupt for P0[25]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." /> + <BitField start="26" size="1" name="P0_26EF" description="Enable falling edge interrupt for P0[26]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." /> + <BitField start="27" size="1" name="P0_27EF" description="Enable falling edge interrupt for P0[27]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." /> + <BitField start="28" size="1" name="P0_28EF" description="Enable falling edge interrupt for P0[28]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." /> + <BitField start="29" size="1" name="P0_29EF" description="Enable falling edge interrupt for P0[29]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." /> + <BitField start="30" size="1" name="P0_30EF" description="Enable falling edge interrupt for P0[30]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." /> + <BitField start="31" size="1" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x024" size="4" name="STATR2" access="ReadOnly" description="GPIO Interrupt Status for Rising edge for Port 0." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="P2_0REI" description="Status of Rising Edge Interrupt for P2[0]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." /> + <BitField start="1" size="1" name="P2_1REI" description="Status of Rising Edge Interrupt for P2[1]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." /> + <BitField start="2" size="1" name="P2_2REI" description="Status of Rising Edge Interrupt for P2[2]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." /> + <BitField start="3" size="1" name="P2_3REI" description="Status of Rising Edge Interrupt for P2[3]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." /> + <BitField start="4" size="1" name="P2_4REI" description="Status of Rising Edge Interrupt for P2[4]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." /> + <BitField start="5" size="1" name="P2_5REI" description="Status of Rising Edge Interrupt for P2[5]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." /> + <BitField start="6" size="1" name="P2_6REI" description="Status of Rising Edge Interrupt for P2[6]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." /> + <BitField start="7" size="1" name="P2_7REI" description="Status of Rising Edge Interrupt for P2[7]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." /> + <BitField start="8" size="1" name="P2_8REI" description="Status of Rising Edge Interrupt for P2[8]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." /> + <BitField start="9" size="1" name="P2_9REI" description="Status of Rising Edge Interrupt for P2[9]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." /> + <BitField start="10" size="1" name="P2_10REI" description="Status of Rising Edge Interrupt for P2[10]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." /> + <BitField start="11" size="1" name="P2_11REI" description="Status of Rising Edge Interrupt for P2[11]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." /> + <BitField start="12" size="1" name="P2_12REI" description="Status of Rising Edge Interrupt for P2[12]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." /> + <BitField start="13" size="1" name="P2_13REI" description="Status of Rising Edge Interrupt for P2[13]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." /> + <BitField start="14" size="18" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x028" size="4" name="STATF2" access="ReadOnly" description="GPIO Interrupt Status for Falling edge for Port 0." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="P2_0FEI" description="Status of Falling Edge Interrupt for P2[0]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." /> + <BitField start="1" size="1" name="P2_1FEI" description="Status of Falling Edge Interrupt for P2[1]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." /> + <BitField start="2" size="1" name="P2_2FEI" description="Status of Falling Edge Interrupt for P2[2]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." /> + <BitField start="3" size="1" name="P2_3FEI" description="Status of Falling Edge Interrupt for P2[3]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." /> + <BitField start="4" size="1" name="P2_4FEI" description="Status of Falling Edge Interrupt for P2[4]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." /> + <BitField start="5" size="1" name="P2_5FEI" description="Status of Falling Edge Interrupt for P2[5]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." /> + <BitField start="6" size="1" name="P2_6FEI" description="Status of Falling Edge Interrupt for P2[6]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." /> + <BitField start="7" size="1" name="P2_7FEI" description="Status of Falling Edge Interrupt for P2[7]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." /> + <BitField start="8" size="1" name="P2_8FEI" description="Status of Falling Edge Interrupt for P2[8]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." /> + <BitField start="9" size="1" name="P2_9FEI" description="Status of Falling Edge Interrupt for P2[9]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." /> + <BitField start="10" size="1" name="P2_10FEI" description="Status of Falling Edge Interrupt for P2[10]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." /> + <BitField start="11" size="1" name="P2_11FEI" description="Status of Falling Edge Interrupt for P2[11]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." /> + <BitField start="12" size="1" name="P2_12FEI" description="Status of Falling Edge Interrupt for P2[12]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." /> + <BitField start="13" size="1" name="P2_13FEI" description="Status of Falling Edge Interrupt for P2[13]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." /> + <BitField start="14" size="18" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x02C" size="4" name="CLR2" access="WriteOnly" description="GPIO Interrupt Clear." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="P2_0CI" description="Clear GPIO port Interrupts for P2[0]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." /> + <BitField start="1" size="1" name="P2_1CI" description="Clear GPIO port Interrupts for P2[1]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." /> + <BitField start="2" size="1" name="P2_2CI" description="Clear GPIO port Interrupts for P2[2]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." /> + <BitField start="3" size="1" name="P2_3CI" description="Clear GPIO port Interrupts for P2[3]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." /> + <BitField start="4" size="1" name="P2_4CI" description="Clear GPIO port Interrupts for P2[4]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." /> + <BitField start="5" size="1" name="P2_5CI" description="Clear GPIO port Interrupts for P2[5]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." /> + <BitField start="6" size="1" name="P2_6CI" description="Clear GPIO port Interrupts for P2[6]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." /> + <BitField start="7" size="1" name="P2_7CI" description="Clear GPIO port Interrupts for P2[7]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." /> + <BitField start="8" size="1" name="P2_8CI" description="Clear GPIO port Interrupts for P2[8]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." /> + <BitField start="9" size="1" name="P2_9CI" description="Clear GPIO port Interrupts for P2[9]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." /> + <BitField start="10" size="1" name="P2_10CI" description="Clear GPIO port Interrupts for P2[10]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." /> + <BitField start="11" size="1" name="P2_11CI" description="Clear GPIO port Interrupts for P2[11]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." /> + <BitField start="12" size="1" name="P2_12CI" description="Clear GPIO port Interrupts for P2[12]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." /> + <BitField start="13" size="1" name="P2_13CI" description="Clear GPIO port Interrupts for P2[13]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." /> + <BitField start="14" size="18" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x030" size="4" name="ENR2" access="Read/Write" description="GPIO Interrupt Enable for Rising edge for Port 0." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="P2_0ER" description="Enable rising edge interrupt for P2[0]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." /> + <BitField start="1" size="1" name="P2_1ER" description="Enable rising edge interrupt for P2[1]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." /> + <BitField start="2" size="1" name="P2_2ER" description="Enable rising edge interrupt for P2[2]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." /> + <BitField start="3" size="1" name="P2_3ER" description="Enable rising edge interrupt for P2[3]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." /> + <BitField start="4" size="1" name="P2_4ER" description="Enable rising edge interrupt for P2[4]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." /> + <BitField start="5" size="1" name="P2_5ER" description="Enable rising edge interrupt for P2[5]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." /> + <BitField start="6" size="1" name="P2_6ER" description="Enable rising edge interrupt for P2[6]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." /> + <BitField start="7" size="1" name="P2_7ER" description="Enable rising edge interrupt for P2[7]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." /> + <BitField start="8" size="1" name="P2_8ER" description="Enable rising edge interrupt for P2[8]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." /> + <BitField start="9" size="1" name="P2_9ER" description="Enable rising edge interrupt for P2[9]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." /> + <BitField start="10" size="1" name="P2_10ER" description="Enable rising edge interrupt for P2[10]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." /> + <BitField start="11" size="1" name="P2_11ER" description="Enable rising edge interrupt for P2[11]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." /> + <BitField start="12" size="1" name="P2_12ER" description="Enable rising edge interrupt for P2[12]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." /> + <BitField start="13" size="1" name="P2_13ER" description="Enable rising edge interrupt for P2[13]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." /> + <BitField start="14" size="18" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x034" size="4" name="ENF2" access="Read/Write" description="GPIO Interrupt Enable for Falling edge for Port 0." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="P2_0EF" description="Enable falling edge interrupt for P2[0]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." /> + <BitField start="1" size="1" name="P2_1EF" description="Enable falling edge interrupt for P2[1]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." /> + <BitField start="2" size="1" name="P2_2EF" description="Enable falling edge interrupt for P2[2]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." /> + <BitField start="3" size="1" name="P2_3EF" description="Enable falling edge interrupt for P2[3]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." /> + <BitField start="4" size="1" name="P2_4EF" description="Enable falling edge interrupt for P2[4]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." /> + <BitField start="5" size="1" name="P2_5EF" description="Enable falling edge interrupt for P2[5]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." /> + <BitField start="6" size="1" name="P2_6EF" description="Enable falling edge interrupt for P2[6]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." /> + <BitField start="7" size="1" name="P2_7EF" description="Enable falling edge interrupt for P2[7]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." /> + <BitField start="8" size="1" name="P2_8EF" description="Enable falling edge interrupt for P2[8]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." /> + <BitField start="9" size="1" name="P2_9EF" description="Enable falling edge interrupt for P2[9]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." /> + <BitField start="10" size="1" name="P2_10EF" description="Enable falling edge interrupt for P2[10]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." /> + <BitField start="11" size="1" name="P2_11EF" description="Enable falling edge interrupt for P2[11]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." /> + <BitField start="12" size="1" name="P2_12EF" description="Enable falling edge interrupt for P2[12]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." /> + <BitField start="13" size="1" name="P2_13EF" description="Enable falling edge interrupt for P2[13]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." /> + <BitField start="14" size="18" name="RESERVED" description="Reserved." /> + </Register> + </RegisterGroup> + <RegisterGroup name="PINCONNECT" start="0x4002C000" description="Pin connect block"> + <Register start="+0x000" size="4" name="PINSEL0" access="Read/Write" description="Pin function select register 0." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="P0_0" description="Pin function select P0.0."> + <Enum name="GPIO_P0" start="0x0" description="GPIO P0.0" /> + <Enum name="RD1" start="0x1" description="RD1" /> + <Enum name="TXD3" start="0x2" description="TXD3" /> + <Enum name="SDA1" start="0x3" description="SDA1" /> + </BitField> + <BitField start="2" size="2" name="P0_1" description="Pin function select P0.1."> + <Enum name="GPIO_P0" start="0x0" description="GPIO P0.1" /> + <Enum name="TD1" start="0x1" description="TD1" /> + <Enum name="RXD3" start="0x2" description="RXD3" /> + <Enum name="SCL1" start="0x3" description="SCL1" /> + </BitField> + <BitField start="4" size="2" name="P0_2" description="Pin function select P0.2."> + <Enum name="GPIO_P0" start="0x0" description="GPIO P0.2" /> + <Enum name="TXD0" start="0x1" description="TXD0" /> + <Enum name="AD0" start="0x2" description="AD0.7" /> + <Enum name="RESERVED" start="0x3" description="Reserved" /> + </BitField> + <BitField start="6" size="2" name="P0_3" description="Pin function select P0.3."> + <Enum name="GPIO_P0" start="0x0" description="GPIO P0.3." /> + <Enum name="RXD0" start="0x1" description="RXD0" /> + <Enum name="AD0" start="0x2" description="AD0.6" /> + <Enum name="RESERVED" start="0x3" description="Reserved." /> + </BitField> + <BitField start="8" size="2" name="P0_4" description="Pin function select P0.4."> + <Enum name="GPIO_P0" start="0x0" description="GPIO P0.4." /> + <Enum name="I2SRX_CLK" start="0x1" description="I2SRX_CLK" /> + <Enum name="RD2" start="0x2" description="RD2" /> + <Enum name="CAP2" start="0x3" description="CAP2.0" /> + </BitField> + <BitField start="10" size="2" name="P0_5" description="Pin function select P0.5."> + <Enum name="GPIO_P0" start="0x0" description="GPIO P0.5." /> + <Enum name="I2SRX_WS" start="0x1" description="I2SRX_WS" /> + <Enum name="TD2" start="0x2" description="TD2" /> + <Enum name="CAP2" start="0x3" description="CAP2.1" /> + </BitField> + <BitField start="12" size="2" name="P0_6" description="Pin function select P0.6."> + <Enum name="GPIO_P0" start="0x0" description="GPIO P0.6." /> + <Enum name="I2SRX_SDA" start="0x1" description="I2SRX_SDA" /> + <Enum name="SSEL1" start="0x2" description="SSEL1" /> + <Enum name="MAT2" start="0x3" description="MAT2.0" /> + </BitField> + <BitField start="14" size="2" name="P0_7" description="Pin function select P0.7."> + <Enum name="GPIO_P0" start="0x0" description="GPIO P0.7." /> + <Enum name="I2STX_CLK" start="0x1" description="I2STX_CLK" /> + <Enum name="SCK1" start="0x2" description="SCK1" /> + <Enum name="MAT2" start="0x3" description="MAT2.1" /> + </BitField> + <BitField start="16" size="2" name="P0_8" description="Pin function select P0.8."> + <Enum name="GPIO_P0" start="0x0" description="GPIO P0.8." /> + <Enum name="I2STX_WS" start="0x1" description="I2STX_WS" /> + <Enum name="MISO1" start="0x2" description="MISO1" /> + <Enum name="MAT2" start="0x3" description="MAT2.2" /> + </BitField> + <BitField start="18" size="2" name="P0_9" description="Pin function select P0.9."> + <Enum name="GPIO_P0" start="0x0" description="GPIO P0.9" /> + <Enum name="I2STX_SDA" start="0x1" description="I2STX_SDA" /> + <Enum name="MOSI1" start="0x2" description="MOSI1" /> + <Enum name="MAT2" start="0x3" description="MAT2.3" /> + </BitField> + <BitField start="20" size="2" name="P0_10" description="Pin function select P0.10."> + <Enum name="GPIO_P0" start="0x0" description="GPIO P0.10" /> + <Enum name="TXD2" start="0x1" description="TXD2" /> + <Enum name="SDA2" start="0x2" description="SDA2" /> + <Enum name="MAT3" start="0x3" description="MAT3.0" /> + </BitField> + <BitField start="22" size="2" name="P0_11" description="Pin function select P0.11."> + <Enum name="GPIO_P0" start="0x0" description="GPIO P0.11" /> + <Enum name="RXD2" start="0x1" description="RXD2" /> + <Enum name="SCL2" start="0x2" description="SCL2" /> + <Enum name="MAT3" start="0x3" description="MAT3.1" /> + </BitField> + <BitField start="24" size="6" name="RESERVED" description="Reserved." /> + <BitField start="30" size="2" name="P0_15" description="Pin function select P0.15."> + <Enum name="GPIO_P0" start="0x0" description="GPIO P0.15" /> + <Enum name="TXD1" start="0x1" description="TXD1" /> + <Enum name="SCK0" start="0x2" description="SCK0" /> + <Enum name="SCK" start="0x3" description="SCK" /> + </BitField> + </Register> + <Register start="+0x004" size="4" name="PINSEL1" access="Read/Write" description="Pin function select register 1." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="P0_16" description="Pin function select P0.16."> + <Enum name="GPIO_P0" start="0x0" description="GPIO P0.16" /> + <Enum name="RXD1" start="0x1" description="RXD1" /> + <Enum name="SSEL0" start="0x2" description="SSEL0" /> + <Enum name="SSEL" start="0x3" description="SSEL" /> + </BitField> + <BitField start="2" size="2" name="P0_17" description="Pin function select P0.17."> + <Enum name="GPIO_P0" start="0x0" description="GPIO P0.17" /> + <Enum name="CTS1" start="0x1" description="CTS1" /> + <Enum name="MISO0" start="0x2" description="MISO0" /> + <Enum name="MISO" start="0x3" description="MISO" /> + </BitField> + <BitField start="4" size="2" name="P0_18" description="Pin function select P0.18."> + <Enum name="GPIO_P0" start="0x0" description="GPIO P0.18" /> + <Enum name="DCD1" start="0x1" description="DCD1" /> + <Enum name="MOSI0" start="0x2" description="MOSI0" /> + <Enum name="MOSI" start="0x3" description="MOSI" /> + </BitField> + <BitField start="6" size="2" name="P0_19" description="Pin function select P019."> + <Enum name="GPIO_P0" start="0x0" description="GPIO P0.19." /> + <Enum name="DSR1" start="0x1" description="DSR1" /> + <Enum name="RESERVED" start="0x2" description="Reserved" /> + <Enum name="SDA1" start="0x3" description="SDA1" /> + </BitField> + <BitField start="8" size="2" name="P0_20" description="Pin function select P0.20."> + <Enum name="GPIO_P0" start="0x0" description="GPIO P0.20." /> + <Enum name="DTR1" start="0x1" description="DTR1" /> + <Enum name="RESERVED" start="0x2" description="Reserved" /> + <Enum name="SCL1" start="0x3" description="SCL1" /> + </BitField> + <BitField start="10" size="2" name="P0_21" description="Pin function select P0.21."> + <Enum name="GPIO_PORT_0" start="0x0" description="GPIO Port 0.21." /> + <Enum name="RI1" start="0x1" description="RI1" /> + <Enum name="RESERVED" start="0x2" description="Reserved" /> + <Enum name="RD1" start="0x3" description="RD1" /> + </BitField> + <BitField start="12" size="2" name="P0_22" description="Pin function select P022"> + <Enum name="GPIO_P0" start="0x0" description="GPIO P0.22." /> + <Enum name="RTS1" start="0x1" description="RTS1" /> + <Enum name="RESERVED" start="0x2" description="Reserved" /> + <Enum name="TD1" start="0x3" description="TD1" /> + </BitField> + <BitField start="14" size="2" name="P0_23" description="Pin function select P023."> + <Enum name="GPIO_P0" start="0x0" description="GPIO P0.23." /> + <Enum name="AD0" start="0x1" description="AD0.0" /> + <Enum name="I2SRX_CLK" start="0x2" description="I2SRX_CLK" /> + <Enum name="CAP3" start="0x3" description="CAP3.0" /> + </BitField> + <BitField start="16" size="2" name="P0_24" description="Pin function select P0.24."> + <Enum name="GPIO_P0" start="0x0" description="GPIO P0.24." /> + <Enum name="AD0" start="0x1" description="AD0.1" /> + <Enum name="I2SRX_WS" start="0x2" description="I2SRX_WS" /> + <Enum name="CAP3" start="0x3" description="CAP3.1" /> + </BitField> + <BitField start="18" size="2" name="P0_25" description="Pin function select P0.25."> + <Enum name="GPIO_P0" start="0x0" description="GPIO P0.25" /> + <Enum name="AD0" start="0x1" description="AD0.2" /> + <Enum name="I2SRX_SDA" start="0x2" description="I2SRX_SDA" /> + <Enum name="TXD3" start="0x3" description="TXD3" /> + </BitField> + <BitField start="20" size="2" name="P0_26" description="Pin function select P0.26."> + <Enum name="GPIO_P0" start="0x0" description="GPIO P0.26" /> + <Enum name="AD0" start="0x1" description="AD0.3" /> + <Enum name="AOUT" start="0x2" description="AOUT" /> + <Enum name="RXD3" start="0x3" description="RXD3" /> + </BitField> + <BitField start="22" size="2" name="P0_27" description="Pin function select P0.27."> + <Enum name="GPIO_P0" start="0x0" description="GPIO P0.27" /> + <Enum name="SDA0" start="0x1" description="SDA0" /> + <Enum name="USB_SDA" start="0x2" description="USB_SDA" /> + <Enum name="RESERVED" start="0x3" description="Reserved" /> + </BitField> + <BitField start="24" size="2" name="P0_28" description="Pin function select P0.28."> + <Enum name="GPIO_P0" start="0x0" description="GPIO P0.28" /> + <Enum name="SCL0" start="0x1" description="SCL0" /> + <Enum name="USB_SCL" start="0x2" description="USB_SCL" /> + <Enum name="RESERVED" start="0x3" description="Reserved" /> + </BitField> + <BitField start="26" size="2" name="P0_29" description="Pin function select P0.29"> + <Enum name="GPIO_P0" start="0x0" description="GPIO P0.29" /> + <Enum name="USB_DP" start="0x1" description="USB_D+" /> + <Enum name="RESERVED" start="0x2" description="Reserved" /> + <Enum name="RESERVED" start="0x3" description="Reserved" /> + </BitField> + <BitField start="28" size="2" name="P0_30" description="Pin function select P0.30."> + <Enum name="GPIO_P0" start="0x0" description="GPIO P0.30" /> + <Enum name="USB_DM" start="0x1" description="USB_D-" /> + <Enum name="RESERVED" start="0x2" description="Reserved" /> + <Enum name="RESERVED" start="0x3" description="Reserved" /> + </BitField> + <BitField start="30" size="2" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x008" size="4" name="PINSEL2" access="Read/Write" description="Pin function select register 2." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="P1_0" description="Pin function select P1.0."> + <Enum name="GPIO_P1" start="0x0" description="GPIO P1.0" /> + <Enum name="ENET_TXD0" start="0x1" description="ENET_TXD0" /> + <Enum name="RESERVED" start="0x2" description="Reserved" /> + <Enum name="RESERVED" start="0x3" description="Reserved" /> + </BitField> + <BitField start="2" size="2" name="P1_1" description="Pin function select P1.1."> + <Enum name="GPIO_P1" start="0x0" description="GPIO P1.1" /> + <Enum name="ENET_TXD1" start="0x1" description="ENET_TXD1" /> + <Enum name="RESERVED" start="0x2" description="Reserved" /> + <Enum name="RESERVED" start="0x3" description="Reserved" /> + </BitField> + <BitField start="4" size="4" name="RESERVED" description="Reserved." /> + <BitField start="8" size="2" name="P1_4" description="Pin function select P1.4."> + <Enum name="GPIO_P1" start="0x0" description="GPIO P1.4." /> + <Enum name="ENET_TX_EN" start="0x1" description="ENET_TX_EN" /> + <Enum name="RESERVED" start="0x2" description="Reserved" /> + <Enum name="RESERVED" start="0x3" description="Reserved" /> + </BitField> + <BitField start="10" size="6" name="RESERVED" description="Reserved." /> + <BitField start="16" size="2" name="P1_8" description="Pin function select P1.8."> + <Enum name="GPIO_P1" start="0x0" description="GPIO P1.8." /> + <Enum name="ENET_CRS" start="0x1" description="ENET_CRS" /> + <Enum name="RESERVED" start="0x2" description="Reserved" /> + <Enum name="RESERVED" start="0x3" description="Reserved" /> + </BitField> + <BitField start="18" size="2" name="P1_9" description="Pin function select P1.9."> + <Enum name="GPIO_PORT_1" start="0x0" description="GPIO Port 1.9" /> + <Enum name="ENET_RXD0" start="0x1" description="ENET_RXD0" /> + <Enum name="RESERVED" start="0x2" description="Reserved" /> + <Enum name="RESERVED" start="0x3" description="Reserved" /> + </BitField> + <BitField start="20" size="2" name="P1_10" description="Pin function select P1.10."> + <Enum name="GPIO_P1" start="0x0" description="GPIO P1.10" /> + <Enum name="ENET_RXD1" start="0x1" description="ENET_RXD1" /> + <Enum name="RESERVED" start="0x2" description="Reserved" /> + <Enum name="RESERVED" start="0x3" description="Reserved" /> + </BitField> + <BitField start="24" size="6" name="RESERVED" description="Reserved." /> + <BitField start="22" size="2" name="P1_14" description="Pin function select P1.14."> + <Enum name="GPIO_P1" start="0x0" description="GPIO P1.14" /> + <Enum name="ENET_RX_ER" start="0x1" description="ENET_RX_ER" /> + <Enum name="RESERVED" start="0x2" description="Reserved" /> + <Enum name="RESERVED" start="0x3" description="Reserved" /> + </BitField> + <BitField start="24" size="6" name="RESERVED" description="Reserved." /> + <BitField start="30" size="2" name="P1_15" description="Pin function select P1.15."> + <Enum name="GPIO_P1" start="0x0" description="GPIO P1.15" /> + <Enum name="ENET_REF_CLK" start="0x1" description="ENET_REF_CLK" /> + <Enum name="RESERVED" start="0x2" description="Reserved" /> + <Enum name="RESERVED" start="0x3" description="Reserved" /> + </BitField> + </Register> + <Register start="+0x00C" size="4" name="PINSEL3" access="Read/Write" description="Pin function select register 3." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="P1_16" description="Pin function select P1.16."> + <Enum name="GPIO_P1" start="0x0" description="GPIO P1.16" /> + <Enum name="ENET_MDC" start="0x1" description="ENET_MDC" /> + <Enum name="RESERVED" start="0x2" description="Reserved" /> + <Enum name="RESERVED" start="0x3" description="Reserved" /> + </BitField> + <BitField start="2" size="2" name="P1_17" description="Pin function select P1.17."> + <Enum name="GPIO_P1" start="0x0" description="GPIO P1.17" /> + <Enum name="ENET_MDIO" start="0x1" description="ENET_MDIO" /> + <Enum name="RESERVED" start="0x2" description="Reserved" /> + <Enum name="RESERVED" start="0x3" description="Reserved" /> + </BitField> + <BitField start="4" size="2" name="P1_18" description="Pin function select P1.18."> + <Enum name="GPIO_P1" start="0x0" description="GPIO P1.18" /> + <Enum name="USB_UP_LED" start="0x1" description="USB_UP_LED" /> + <Enum name="PWM1" start="0x2" description="PWM1.1" /> + <Enum name="CAP1" start="0x3" description="CAP1.0" /> + </BitField> + <BitField start="6" size="2" name="P1_19" description="Pin function select P1.19."> + <Enum name="GPIO_P1" start="0x0" description="GPIO P1.19." /> + <Enum name="MCOA0" start="0x1" description="MCOA0" /> + <Enum name="USB_PPWR" start="0x2" description="USB_PPWR" /> + <Enum name="CAP1" start="0x3" description="CAP1.1" /> + </BitField> + <BitField start="8" size="2" name="P1_20" description="Pin function select P1.20."> + <Enum name="GPIO_P1" start="0x0" description="GPIO P1.20." /> + <Enum name="MCI0" start="0x1" description="MCI0" /> + <Enum name="PWM1" start="0x2" description="PWM1.2" /> + <Enum name="SCK0" start="0x3" description="SCK0" /> + </BitField> + <BitField start="10" size="2" name="P1_21" description="Pin function select P1.21."> + <Enum name="GPIO_P1" start="0x0" description="GPIO P1.21." /> + <Enum name="MCABORT" start="0x1" description="MCABORT" /> + <Enum name="PWM1" start="0x2" description="PWM1.3" /> + <Enum name="SSEL0" start="0x3" description="SSEL0" /> + </BitField> + <BitField start="12" size="2" name="P1_22" description="Pin function select P1.22"> + <Enum name="GPIO_P1" start="0x0" description="GPIO P1.22." /> + <Enum name="MCOB0" start="0x1" description="MCOB0" /> + <Enum name="USB_PWRD" start="0x2" description="USB_PWRD" /> + <Enum name="MAT1" start="0x3" description="MAT1.0" /> + </BitField> + <BitField start="14" size="2" name="P1_23" description="Pin function select P1.23."> + <Enum name="GPIO_P1" start="0x0" description="GPIO P1.23." /> + <Enum name="MCI1" start="0x1" description="MCI1" /> + <Enum name="PWM1" start="0x2" description="PWM1.4" /> + <Enum name="MISO0" start="0x3" description="MISO0" /> + </BitField> + <BitField start="16" size="2" name="P1_24" description="Pin function select P1.24."> + <Enum name="GPIO_P1" start="0x0" description="GPIO P1.24." /> + <Enum name="MCI2" start="0x1" description="MCI2" /> + <Enum name="PWM1" start="0x2" description="PWM1.5" /> + <Enum name="MOSI0" start="0x3" description="MOSI0" /> + </BitField> + <BitField start="18" size="2" name="P1_25" description="Pin function select P1.25."> + <Enum name="GPIO_P1" start="0x0" description="GPIO P1.25" /> + <Enum name="MCOA1" start="0x1" description="MCOA1" /> + <Enum name="RESERVED" start="0x2" description="Reserved" /> + <Enum name="MAT1" start="0x3" description="MAT1.1" /> + </BitField> + <BitField start="20" size="2" name="P1_26" description="Pin function select P1.26."> + <Enum name="GPIO_P1" start="0x0" description="GPIO P1.26" /> + <Enum name="MCOB1" start="0x1" description="MCOB1" /> + <Enum name="PWM1" start="0x2" description="PWM1.6" /> + <Enum name="CAP0" start="0x3" description="CAP0.0" /> + </BitField> + <BitField start="22" size="2" name="P1_27" description="Pin function select P1.27."> + <Enum name="GPIO_P1" start="0x0" description="GPIO P1.27" /> + <Enum name="CLKOUT" start="0x1" description="CLKOUT" /> + <Enum name="USB_OVRCR" start="0x2" description="USB_OVRCR" /> + <Enum name="CAP0" start="0x3" description="CAP0.1" /> + </BitField> + <BitField start="24" size="2" name="P1_28" description="Pin function select P1.28."> + <Enum name="GPIO_P1" start="0x0" description="GPIO P1.28" /> + <Enum name="MCOA2" start="0x1" description="MCOA2" /> + <Enum name="PCAP1" start="0x2" description="PCAP1.0" /> + <Enum name="MAT0" start="0x3" description="MAT0.0" /> + </BitField> + <BitField start="26" size="2" name="P1_29" description="Pin function select P1.29"> + <Enum name="GPIO_P1" start="0x0" description="GPIO P1.29" /> + <Enum name="MCOB2" start="0x1" description="MCOB2" /> + <Enum name="PCAP1" start="0x2" description="PCAP1.1" /> + <Enum name="MAT0" start="0x3" description="MAT0.1" /> + </BitField> + <BitField start="28" size="2" name="P1_30" description="Pin function select P1.30."> + <Enum name="GPIO_P1" start="0x0" description="GPIO P1.30" /> + <Enum name="RESERVED" start="0x1" description="Reserved" /> + <Enum name="VBUS" start="0x2" description="VBUS" /> + <Enum name="AD0" start="0x3" description="AD0.4" /> + </BitField> + <BitField start="30" size="2" name="P1_31" description="Pin function select P1.31."> + <Enum name="GPIO_PORT_1" start="0x0" description="GPIO Port 1.31" /> + <Enum name="RESERVED" start="0x1" description="Reserved" /> + <Enum name="SCK1" start="0x2" description="SCK1" /> + <Enum name="AD0" start="0x3" description="AD0.5" /> + </BitField> + </Register> + <Register start="+0x010" size="4" name="PINSEL4" access="Read/Write" description="Pin function select register 4" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="P2_0" description="Pin function select P2.0."> + <Enum name="GPIO_P2" start="0x0" description="GPIO P2.0" /> + <Enum name="PWM1" start="0x1" description="PWM1.1" /> + <Enum name="TXD1" start="0x2" description="TXD1" /> + <Enum name="RESERVED" start="0x3" description="Reserved" /> + </BitField> + <BitField start="2" size="2" name="P2_1" description="Pin function select P2.1."> + <Enum name="GPIO_P2" start="0x0" description="GPIO P2.1" /> + <Enum name="PWM1" start="0x1" description="PWM1.2" /> + <Enum name="RXD1" start="0x2" description="RXD1" /> + <Enum name="RESERVED" start="0x3" description="Reserved" /> + </BitField> + <BitField start="4" size="2" name="P2_2" description="Pin function select P2.2."> + <Enum name="GPIO_P2" start="0x0" description="GPIO P2.2" /> + <Enum name="PWM1" start="0x1" description="PWM1.3" /> + <Enum name="CTS1" start="0x2" description="CTS1" /> + <Enum name="RESERVED" start="0x3" description="Reserved" /> + </BitField> + <BitField start="6" size="2" name="P2_3" description="Pin function select P2.3."> + <Enum name="GPIO_P2" start="0x0" description="GPIO P2.3." /> + <Enum name="PWM1" start="0x1" description="PWM1.4" /> + <Enum name="DCD1" start="0x2" description="DCD1" /> + <Enum name="RESERVED" start="0x3" description="Reserved." /> + </BitField> + <BitField start="8" size="2" name="P2_4" description="Pin function select P2.4."> + <Enum name="GPIO_P2" start="0x0" description="GPIO P2.4." /> + <Enum name="PWM1" start="0x1" description="PWM1.5" /> + <Enum name="DSR1" start="0x2" description="DSR1" /> + <Enum name="RESERVED" start="0x3" description="Reserved." /> + </BitField> + <BitField start="10" size="2" name="P2_5" description="Pin function select P2.5."> + <Enum name="GPIO_P2" start="0x0" description="GPIO P2.5." /> + <Enum name="PWM1" start="0x1" description="PWM1.6" /> + <Enum name="DTR1" start="0x2" description="DTR1" /> + <Enum name="RESERVED" start="0x3" description="Reserved" /> + </BitField> + <BitField start="12" size="2" name="P2_6" description="Pin function select P2.6."> + <Enum name="GPIO_P2" start="0x0" description="GPIO P2.6." /> + <Enum name="PCAP1" start="0x1" description="PCAP1.0" /> + <Enum name="RI1" start="0x2" description="RI1" /> + <Enum name="RESERVED" start="0x3" description="Reserved" /> + </BitField> + <BitField start="14" size="2" name="P2_7" description="Pin function select P2.7."> + <Enum name="GPIO_P2" start="0x0" description="GPIO P2.7." /> + <Enum name="RD2" start="0x1" description="RD2" /> + <Enum name="RTS1" start="0x2" description="RTS1" /> + <Enum name="RESERVED" start="0x3" description="Reserved" /> + </BitField> + <BitField start="16" size="2" name="P2_8" description="Pin function select P2.8."> + <Enum name="GPIO_P2" start="0x0" description="GPIO P2.8." /> + <Enum name="TD2" start="0x1" description="TD2" /> + <Enum name="TXD2" start="0x2" description="TXD2" /> + <Enum name="ENET_MDC" start="0x3" description="ENET_MDC" /> + </BitField> + <BitField start="18" size="2" name="P2_9" description="Pin function select P2.9."> + <Enum name="GPIO_P2" start="0x0" description="GPIO P2.9" /> + <Enum name="USB_CONNECT" start="0x1" description="USB_CONNECT" /> + <Enum name="RXD2" start="0x2" description="RXD2" /> + <Enum name="ENET_MDIO" start="0x3" description="ENET_MDIO" /> + </BitField> + <BitField start="20" size="2" name="P2_10" description="Pin function select P2.10."> + <Enum name="GPIO_P2" start="0x0" description="GPIO P2.10" /> + <Enum name="EINT0" start="0x1" description="EINT0" /> + <Enum name="NMI" start="0x2" description="NMI" /> + <Enum name="RESERVED" start="0x3" description="Reserved" /> + </BitField> + <BitField start="22" size="2" name="P2_11" description="Pin function select P2.11."> + <Enum name="GPIO_P2" start="0x0" description="GPIO P2.11" /> + <Enum name="EINT1" start="0x1" description="EINT1" /> + <Enum name="RESERVED" start="0x2" description="Reserved" /> + <Enum name="I2STX_CLK" start="0x3" description="I2STX_CLK" /> + </BitField> + <BitField start="24" size="2" name="P2_12" description="Pin function select P2.12."> + <Enum name="GPIO_P2" start="0x0" description="GPIO P2.12" /> + <Enum name="EINT2" start="0x1" description="EINT2" /> + <Enum name="RESERVED" start="0x2" description="Reserved" /> + <Enum name="I2STX_WS" start="0x3" description="I2STX_WS" /> + </BitField> + <BitField start="26" size="2" name="P2_13" description="Pin function select P2.13."> + <Enum name="GPIO_P2" start="0x0" description="GPIO P2.13" /> + <Enum name="EINT3" start="0x1" description="EINT3" /> + <Enum name="RESERVED" start="0x2" description="Reserved" /> + <Enum name="I2STX_SDA" start="0x3" description="I2STX_SDA" /> + </BitField> + <BitField start="28" size="4" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x01C" size="4" name="PINSEL7" access="Read/Write" description="Pin function select register 7" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="18" name="RESERVED" description="Reserved." /> + <BitField start="18" size="2" name="P3_25" description="Pin function select P3.25."> + <Enum name="GPIO_P3" start="0x0" description="GPIO P3.25" /> + <Enum name="RESERVED" start="0x1" description="Reserved" /> + <Enum name="MAT0" start="0x2" description="MAT0.0" /> + <Enum name="PWM1" start="0x3" description="PWM1.2" /> + </BitField> + <BitField start="20" size="2" name="P3_26" description="Pin function select P3.26."> + <Enum name="GPIO_P3" start="0x0" description="GPIO P3.26" /> + <Enum name="STCLK" start="0x1" description="STCLK" /> + <Enum name="MAT0" start="0x2" description="MAT0.1" /> + <Enum name="PWM1" start="0x3" description="PWM1.3" /> + </BitField> + <BitField start="22" size="10" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x024" size="4" name="PINSEL9" access="Read/Write" description="Pin function select register 9" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="24" name="RESERVED" description="Reserved." /> + <BitField start="24" size="2" name="P4_28" description="Pin function select P4.28."> + <Enum name="GPIO_P4" start="0x0" description="GPIO P4.28" /> + <Enum name="RX_MCLK" start="0x1" description="RX_MCLK" /> + <Enum name="MAT2" start="0x2" description="MAT2.0" /> + <Enum name="TXD3" start="0x3" description="TXD3" /> + </BitField> + <BitField start="26" size="2" name="P4_29" description="Pin function select P4.29."> + <Enum name="GPIO_P4" start="0x0" description="GPIO P4.29" /> + <Enum name="TX_MCLK" start="0x1" description="TX_MCLK" /> + <Enum name="MAT2" start="0x2" description="MAT2.1" /> + <Enum name="RXD3" start="0x3" description="RXD3" /> + </BitField> + <BitField start="28" size="4" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x028" size="4" name="PINSEL10" access="Read/Write" description="Pin function select register 10" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="RESERVED" description="Reserved. Software should not write 1 to these bits." /> + <BitField start="3" size="1" name="TPIUCTRL" description="TPIU interface pins control."> + <Enum name="DISABLED" start="0" description="Disabled. TPIU interface is disabled." /> + <Enum name="ENABLED" start="1" description="Enabled. TPIU interface is enabled. TPIU signals are available on the pins hosting them regardless of the PINSEL4 content." /> + </BitField> + <BitField start="4" size="28" name="RESERVED" description="Reserved. Software should not write 1 to these bits." /> + </Register> + <Register start="+0x040" size="4" name="PINMODE0" access="Read/Write" description="Pin mode select register 0" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="P0_00MODE" description="Port 0 pin 0 on-chip pull-up/down resistor control."> + <Enum name="PULL_UP" start="0x0" description="Pull-up. P0.0 pin has a pull-up resistor enabled." /> + <Enum name="REPEATER" start="0x1" description="Repeater. P0.0 pin has repeater mode enabled." /> + <Enum name="DISABLED" start="0x2" description="Disabled. P0.0 pin has neither pull-up nor pull-down." /> + <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P0.0 has a pull-down resistor enabled." /> + </BitField> + <BitField start="2" size="2" name="P0_01MODE" description="Port 0 pin 1 control."> + <Enum name="PULL_UP" start="0x0" description="Pull-up. P0.1 pin has a pull-up resistor enabled." /> + <Enum name="REPEATER" start="0x1" description="Repeater. P0.1 pin has repeater mode enabled." /> + <Enum name="DISABLED" start="0x2" description="Disabled. P0.1 pin has neither pull-up nor pull-down." /> + <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P0.1 has a pull-down resistor enabled." /> + </BitField> + <BitField start="4" size="2" name="P0_02MODE" description="Port 0 pin 2 control."> + <Enum name="PULL_UP" start="0x0" description="Pull-up. P0.2 pin has a pull-up resistor enabled." /> + <Enum name="REPEATER" start="0x1" description="Repeater. P0.2 pin has repeater mode enabled." /> + <Enum name="DISABLED" start="0x2" description="Disabled. P0.2 pin has neither pull-up nor pull-down." /> + <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P0.2 has a pull-down resistor enabled." /> + </BitField> + <BitField start="6" size="2" name="P0_03MODE" description="Port 0 pin 3 control."> + <Enum name="PULL_UP" start="0x0" description="Pull-up. P0.3 pin has a pull-up resistor enabled." /> + <Enum name="REPEATER" start="0x1" description="Repeater. P0.3 pin has repeater mode enabled." /> + <Enum name="DISABLED" start="0x2" description="Disabled. P0.3 pin has neither pull-up nor pull-down." /> + <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P0.3 has a pull-down resistor enabled." /> + </BitField> + <BitField start="8" size="2" name="P0_04MODE" description="Port 0 pin 4 control."> + <Enum name="PULL_UP" start="0x0" description="Pull-up. P0.4 pin has a pull-up resistor enabled." /> + <Enum name="REPEATER" start="0x1" description="Repeater. P0.4 pin has repeater mode enabled." /> + <Enum name="DISABLED" start="0x2" description="Disabled. P0.4 pin has neither pull-up nor pull-down." /> + <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P0.4 has a pull-down resistor enabled." /> + </BitField> + <BitField start="10" size="2" name="P0_05MODE" description="Port 0 pin 5 control."> + <Enum name="PULL_UP" start="0x0" description="Pull-up. P0.5 pin has a pull-up resistor enabled." /> + <Enum name="REPEATER" start="0x1" description="Repeater. P0.5 pin has repeater mode enabled." /> + <Enum name="DISABLED" start="0x2" description="Disabled. P0.5 pin has neither pull-up nor pull-down." /> + <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P0.5 has a pull-down resistor enabled." /> + </BitField> + <BitField start="12" size="2" name="P0_06MODE" description="Port 0 pin 6 control."> + <Enum name="PULL_UP" start="0x0" description="Pull-up. P0.6 pin has a pull-up resistor enabled." /> + <Enum name="DISABLED" start="0x1" description="Disabled. Repeater. P0.6 pin has repeater mode enabled." /> + <Enum name="DISABLED" start="0x2" description="Disabled. P0.6 pin has neither pull-up nor pull-down." /> + <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P0.6 has a pull-down resistor enabled." /> + </BitField> + <BitField start="14" size="2" name="P0_07MODE" description="Port 0 pin 7 control."> + <Enum name="PULL_UP" start="0x0" description="Pull-up. P0.7 pin has a pull-up resistor enabled." /> + <Enum name="REPEATER" start="0x1" description="Repeater. P0.7 pin has repeater mode enabled." /> + <Enum name="DISABLED" start="0x2" description="Disabled. P0.7 pin has neither pull-up nor pull-down." /> + <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P0.7 has a pull-down resistor enabled." /> + </BitField> + <BitField start="16" size="2" name="P0_08MODE" description="Port 0 pin 8 control."> + <Enum name="PULL_UP" start="0x0" description="Pull-up. P0.8 pin has a pull-up resistor enabled." /> + <Enum name="REPEATER" start="0x1" description="Repeater. P0.8 pin has repeater mode enabled." /> + <Enum name="DISABLED" start="0x2" description="Disabled. P0.8 pin has neither pull-up nor pull-down." /> + <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P0.8 has a pull-down resistor enabled." /> + </BitField> + <BitField start="18" size="2" name="P0_09MODE" description="Port 0 pin 9 control."> + <Enum name="PULL_UP" start="0x0" description="Pull-up. P0.9 pin has a pull-up resistor enabled." /> + <Enum name="REPEATER" start="0x1" description="Repeater. P0.9 pin has repeater mode enabled." /> + <Enum name="DISABLED" start="0x2" description="Disabled. P0.9 pin has neither pull-up nor pull-down." /> + <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P0.9 has a pull-down resistor enabled." /> + </BitField> + <BitField start="20" size="2" name="P0_10MODE" description="Port 0 pin 10 control."> + <Enum name="PULL_UP" start="0x0" description="Pull-up. P0.10 pin has a pull-up resistor enabled." /> + <Enum name="REPEATER" start="0x1" description="Repeater. P0.10 pin has repeater mode enabled." /> + <Enum name="DISABLED" start="0x2" description="Disabled. P0.10 pin has neither pull-up nor pull-down." /> + <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P0.10 has a pull-down resistor enabled." /> + </BitField> + <BitField start="22" size="2" name="P0_11MODE" description="Port 0 pin 11 control."> + <Enum name="PULL_UP" start="0x0" description="Pull-up. P0.11 pin has a pull-up resistor enabled." /> + <Enum name="REPEATER" start="0x1" description="Repeater. P0.11 pin has repeater mode enabled." /> + <Enum name="DISABLED" start="0x2" description="Disabled. P0.11 pin has neither pull-up nor pull-down." /> + <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P0.11 has a pull-down resistor enabled." /> + </BitField> + <BitField start="24" size="6" name="RESERVED" description="Reserved." /> + <BitField start="30" size="2" name="P0_15MODE" description="Port 0 pin 15 control."> + <Enum name="PULL_UP" start="0x0" description="Pull-up. P0.15 pin has a pull-up resistor enabled." /> + <Enum name="REPEATER" start="0x1" description="Repeater. P0.15 pin has repeater mode enabled." /> + <Enum name="DISABLED" start="0x2" description="Disabled. P0.15 pin has neither pull-up nor pull-down." /> + <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P0.15 has a pull-down resistor enabled." /> + </BitField> + </Register> + <Register start="+0x044" size="4" name="PINMODE1" access="Read/Write" description="Pin mode select register 1" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="P0_16MODE" description="Port 1 pin 16 control."> + <Enum name="PULL_UP" start="0x0" description="Pull-up. P0.16 pin has a pull-up resistor enabled." /> + <Enum name="REPEATER" start="0x1" description="Repeater. P0.16 pin has repeater mode enabled." /> + <Enum name="DISABLED" start="0x2" description="Disabled. P0.16 pin has neither pull-up nor pull-down." /> + <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P0.16 has a pull-down resistor enabled." /> + </BitField> + <BitField start="2" size="2" name="P0_17MODE" description="Port 1 pin 17 control."> + <Enum name="PULL_UP" start="0x0" description="Pull-up. P0.17 pin has a pull-up resistor enabled." /> + <Enum name="REPEATER" start="0x1" description="Repeater. P0.17 pin has repeater mode enabled." /> + <Enum name="DISABLED" start="0x2" description="Disabled. P0.17 pin has neither pull-up nor pull-down." /> + <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P0.17 has a pull-down resistor enabled." /> + </BitField> + <BitField start="4" size="2" name="P0_18MODE" description="Port 1 pin 18 control."> + <Enum name="PULL_UP" start="0x0" description="Pull-up. P0.18 pin has a pull-up resistor enabled." /> + <Enum name="REPEATER" start="0x1" description="Repeater. P0.18 pin has repeater mode enabled." /> + <Enum name="DISABLED" start="0x2" description="Disabled. P0.18 pin has neither pull-up nor pull-down." /> + <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P0.18 has a pull-down resistor enabled." /> + </BitField> + <BitField start="6" size="2" name="P0_19MODE" description="Port 1 pin 19 control."> + <Enum name="PULL_UP" start="0x0" description="Pull-up. P0.19 pin has a pull-up resistor enabled." /> + <Enum name="REPEATER" start="0x1" description="Repeater. P0.19 pin has repeater mode enabled." /> + <Enum name="DISABLED" start="0x2" description="Disabled. P0.19 pin has neither pull-up nor pull-down." /> + <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P0.19 has a pull-down resistor enabled." /> + </BitField> + <BitField start="8" size="2" name="P0_20MODE" description="Port 1 pin 20 control."> + <Enum name="PULL_UP" start="0x0" description="Pull-up. P0.20 pin has a pull-up resistor enabled." /> + <Enum name="REPEATER" start="0x1" description="Repeater. P0.20 pin has repeater mode enabled." /> + <Enum name="DISABLED" start="0x2" description="Disabled. P0.20 pin has neither pull-up nor pull-down." /> + <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P0.20 has a pull-down resistor enabled." /> + </BitField> + <BitField start="10" size="2" name="P0_21MODE" description="Port 1 pin 21 control."> + <Enum name="PULL_UP" start="0x0" description="Pull-up. P0.21 pin has a pull-up resistor enabled." /> + <Enum name="REPEATER" start="0x1" description="Repeater. P0.21 pin has repeater mode enabled." /> + <Enum name="DISABLED" start="0x2" description="Disabled. P0.21 pin has neither pull-up nor pull-down." /> + <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P0.21 has a pull-down resistor enabled." /> + </BitField> + <BitField start="12" size="2" name="P0_22MODE" description="Port 1 pin 22 control."> + <Enum name="PULL_UP" start="0x0" description="Pull-up. P0.22 pin has a pull-up resistor enabled." /> + <Enum name="REPEATER" start="0x1" description="Repeater. P0.22 pin has repeater mode enabled." /> + <Enum name="DISABLED" start="0x2" description="Disabled. P0.22 pin has neither pull-up nor pull-down." /> + <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P0.22 has a pull-down resistor enabled." /> + </BitField> + <BitField start="14" size="2" name="P0_23MODE" description="Port 1 pin 23 control."> + <Enum name="PULL_UP" start="0x0" description="Pull-up. P0.23 pin has a pull-up resistor enabled." /> + <Enum name="REPEATER" start="0x1" description="Repeater. P0.23 pin has repeater mode enabled." /> + <Enum name="DISABLED" start="0x2" description="Disabled. P0.23 pin has neither pull-up nor pull-down." /> + <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P0.23 has a pull-down resistor enabled." /> + </BitField> + <BitField start="16" size="2" name="P0_24MODE" description="Port 1 pin 24 control."> + <Enum name="PULL_UP" start="0x0" description="Pull-up. P0.24 pin has a pull-up resistor enabled." /> + <Enum name="REPEATER" start="0x1" description="Repeater. P0.24 pin has repeater mode enabled." /> + <Enum name="DISABLED" start="0x2" description="Disabled. P0.24 pin has neither pull-up nor pull-down." /> + <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P0.24 has a pull-down resistor enabled." /> + </BitField> + <BitField start="18" size="2" name="P0_25MODE" description="Port 1 pin 25 control."> + <Enum name="PULL_UP" start="0x0" description="Pull-up. P0.25 pin has a pull-up resistor enabled." /> + <Enum name="REPEATER" start="0x1" description="Repeater. P0.25 pin has repeater mode enabled." /> + <Enum name="DISABLED" start="0x2" description="Disabled. P0.25 pin has neither pull-up nor pull-down." /> + <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P0.25 has a pull-down resistor enabled." /> + </BitField> + <BitField start="20" size="2" name="P0_26MODE" description="Port 1 pin 26 control."> + <Enum name="PULL_UP" start="0x0" description="Pull-up. P0.26 pin has a pull-up resistor enabled." /> + <Enum name="REPEATER" start="0x1" description="Repeater. P0.26 pin has repeater mode enabled." /> + <Enum name="DISABLED" start="0x2" description="Disabled. P0.26 pin has neither pull-up nor pull-down." /> + <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P0.26 has a pull-down resistor enabled." /> + </BitField> + <BitField start="22" size="8" name="RESERVED" description="Reserved." /> + <BitField start="30" size="2" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x048" size="4" name="PINMODE2" access="Read/Write" description="Pin mode select register 2" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="P1_00MODE" description="Port 1 pin 0 control."> + <Enum name="PULL_UP" start="0x0" description="Pull-up. P1.0 pin has a pull-up resistor enabled." /> + <Enum name="REPEATER" start="0x1" description="Repeater. P1.0 pin has repeater mode enabled." /> + <Enum name="DISABLED" start="0x2" description="Disabled. P1.0 pin has neither pull-up nor pull-down." /> + <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P1.0 has a pull-down resistor enabled." /> + </BitField> + <BitField start="2" size="2" name="P1_01MODE" description="Port 1 pin 1 control."> + <Enum name="PULL_UP" start="0x0" description="Pull-up. P1.1 pin has a pull-up resistor enabled." /> + <Enum name="REPEATER" start="0x1" description="Repeater. P1.1 pin has repeater mode enabled." /> + <Enum name="DISABLED" start="0x2" description="Disabled. P1.1 pin has neither pull-up nor pull-down." /> + <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P1.1 has a pull-down resistor enabled." /> + </BitField> + <BitField start="4" size="4" name="RESERVED" description="Reserved." /> + <BitField start="8" size="2" name="P1_04MODE" description="Port 1 pin 4 control."> + <Enum name="PULL_UP" start="0x0" description="Pull-up. P1.4 pin has a pull-up resistor enabled." /> + <Enum name="REPEATER" start="0x1" description="Repeater. P1.4 pin has repeater mode enabled." /> + <Enum name="DISABLED" start="0x2" description="Disabled. P1.4 pin has neither pull-up nor pull-down." /> + <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P1.4 has a pull-down resistor enabled." /> + </BitField> + <BitField start="10" size="6" name="RESERVED" description="Reserved." /> + <BitField start="16" size="2" name="P1_08MODE" description="Port 1 pin 8 control."> + <Enum name="PULL_UP" start="0x0" description="Pull-up. P1.8 pin has a pull-up resistor enabled." /> + <Enum name="REPEATER" start="0x1" description="Repeater. P1.8 pin has repeater mode enabled." /> + <Enum name="DISABLED" start="0x2" description="Disabled. P1.8 pin has neither pull-up nor pull-down." /> + <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P1.8 has a pull-down resistor enabled." /> + </BitField> + <BitField start="18" size="2" name="P1_09MODE" description="Port 1 pin 9 control."> + <Enum name="PULL_UP" start="0x0" description="Pull-up. P1.9 pin has a pull-up resistor enabled." /> + <Enum name="REPEATER" start="0x1" description="Repeater. P1.9 pin has repeater mode enabled." /> + <Enum name="DISABLED" start="0x2" description="Disabled. P1.9 pin has neither pull-up nor pull-down." /> + <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P1.9 has a pull-down resistor enabled." /> + </BitField> + <BitField start="20" size="2" name="P1_10MODE" description="Port 1 pin 10 control."> + <Enum name="PULL_UP" start="0x0" description="Pull-up. P1.10 pin has a pull-up resistor enabled." /> + <Enum name="REPEATER" start="0x1" description="Repeater. P1.10 pin has repeater mode enabled." /> + <Enum name="DISABLED" start="0x2" description="Disabled. P1.10 pin has neither pull-up nor pull-down." /> + <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P1.10 has a pull-down resistor enabled." /> + </BitField> + <BitField start="22" size="6" name="RESERVED" description="Reserved." /> + <BitField start="28" size="2" name="P1_14MODE" description="Port 1 pin 14 control."> + <Enum name="PULL_UP" start="0x0" description="Pull-up. P1.14 pin has a pull-up resistor enabled." /> + <Enum name="REPEATER" start="0x1" description="Repeater. P1.14 pin has repeater mode enabled." /> + <Enum name="DISABLED" start="0x2" description="Disabled. P1.14 pin has neither pull-up nor pull-down." /> + <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P1.14 has a pull-down resistor enabled." /> + </BitField> + <BitField start="30" size="2" name="P1_15MODE" description="Port 1 pin 15 control."> + <Enum name="PULL_UP" start="0x0" description="Pull-up. P1.15 pin has a pull-up resistor enabled." /> + <Enum name="REPEATER" start="0x1" description="Repeater. P1.15 pin has repeater mode enabled." /> + <Enum name="DISABLED" start="0x2" description="Disabled. P1.15 pin has neither pull-up nor pull-down." /> + <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P1.15 has a pull-down resistor enabled." /> + </BitField> + </Register> + <Register start="+0x04C" size="4" name="PINMODE3" access="Read/Write" description="Pin mode select register 3." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="P1_16MODE" description="Port 1 pin 16 control."> + <Enum name="PULL_UP" start="0x0" description="Pull-up. P1.16 pin has a pull-up resistor enabled." /> + <Enum name="REPEATER" start="0x1" description="Repeater. P1.16 pin has repeater mode enabled." /> + <Enum name="DISABLED" start="0x2" description="Disabled. P1.16 pin has neither pull-up nor pull-down." /> + <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P1.16 has a pull-down resistor enabled." /> + </BitField> + <BitField start="2" size="2" name="P1_17MODE" description="Port 1 pin 17 control."> + <Enum name="PULL_UP" start="0x0" description="Pull-up. P1.17 pin has a pull-up resistor enabled." /> + <Enum name="REPEATER" start="0x1" description="Repeater. P1.17 pin has repeater mode enabled." /> + <Enum name="DISABLED" start="0x2" description="Disabled. P1.17 pin has neither pull-up nor pull-down." /> + <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P1.17 has a pull-down resistor enabled." /> + </BitField> + <BitField start="4" size="2" name="P1_18MODE" description="Port 1 pin 18 control."> + <Enum name="PULL_UP" start="0x0" description="Pull-up. P1.18 pin has a pull-up resistor enabled." /> + <Enum name="REPEATER" start="0x1" description="Repeater. P1.18 pin has repeater mode enabled." /> + <Enum name="DISABLED" start="0x2" description="Disabled. P1.18 pin has neither pull-up nor pull-down." /> + <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P1.18 has a pull-down resistor enabled." /> + </BitField> + <BitField start="6" size="2" name="P1_19MODE" description="Port 1 pin 19 control."> + <Enum name="PULL_UP" start="0x0" description="Pull-up. P1.19 pin has a pull-up resistor enabled." /> + <Enum name="REPEATER" start="0x1" description="Repeater. P1.19 pin has repeater mode enabled." /> + <Enum name="DISABLED" start="0x2" description="Disabled. P1.19 pin has neither pull-up nor pull-down." /> + <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P1.19 has a pull-down resistor enabled." /> + </BitField> + <BitField start="8" size="2" name="P1_20MODE" description="Port 1 pin 20 control."> + <Enum name="PULL_UP" start="0x0" description="Pull-up. P1.20 pin has a pull-up resistor enabled." /> + <Enum name="REPEATER" start="0x1" description="Repeater. P1.20 pin has repeater mode enabled." /> + <Enum name="DISABLED" start="0x2" description="Disabled. P1.20 pin has neither pull-up nor pull-down." /> + <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P1.20 has a pull-down resistor enabled." /> + </BitField> + <BitField start="10" size="2" name="P1_21MODE" description="Port 1 pin 21 control."> + <Enum name="PULL_UP" start="0x0" description="Pull-up. P1.21 pin has a pull-up resistor enabled." /> + <Enum name="REPEATER" start="0x1" description="Repeater. P1.21 pin has repeater mode enabled." /> + <Enum name="DISABLED" start="0x2" description="Disabled. P1.21 pin has neither pull-up nor pull-down." /> + <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P1.21 has a pull-down resistor enabled." /> + </BitField> + <BitField start="12" size="2" name="P1_22MODE" description="Port 1 pin 22 control."> + <Enum name="PULL_UP" start="0x0" description="Pull-up. P1.22 pin has a pull-up resistor enabled." /> + <Enum name="REPEATER" start="0x1" description="Repeater. P1.22 pin has repeater mode enabled." /> + <Enum name="DISABLED" start="0x2" description="Disabled. P1.22 pin has neither pull-up nor pull-down." /> + <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P1.22 has a pull-down resistor enabled." /> + </BitField> + <BitField start="14" size="2" name="P1_23MODE" description="Port 1 pin 23 control."> + <Enum name="PULL_UP" start="0x0" description="Pull-up. P1.23 pin has a pull-up resistor enabled." /> + <Enum name="REPEATER" start="0x1" description="Repeater. P1.23 pin has repeater mode enabled." /> + <Enum name="DISABLED" start="0x2" description="Disabled. P1.23 pin has neither pull-up nor pull-down." /> + <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P1.23 has a pull-down resistor enabled." /> + </BitField> + <BitField start="16" size="2" name="P1_24MODE" description="Port 1 pin 24 control."> + <Enum name="PULL_UP" start="0x0" description="Pull-up. P1.24 pin has a pull-up resistor enabled." /> + <Enum name="REPEATER" start="0x1" description="Repeater. P1.24 pin has repeater mode enabled." /> + <Enum name="DISABLED" start="0x2" description="Disabled. P1.24 pin has neither pull-up nor pull-down." /> + <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P1.24 has a pull-down resistor enabled." /> + </BitField> + <BitField start="18" size="2" name="P1_25MODE" description="Port 1 pin 25 control."> + <Enum name="PULL_UP" start="0x0" description="Pull-up. P1.25 pin has a pull-up resistor enabled." /> + <Enum name="REPEATER" start="0x1" description="Repeater. P1.25 pin has repeater mode enabled." /> + <Enum name="DISABLED" start="0x2" description="Disabled. P1.25 pin has neither pull-up nor pull-down." /> + <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P1.25 has a pull-down resistor enabled." /> + </BitField> + <BitField start="20" size="2" name="P1_26MODE" description="Port 1 pin 26 control."> + <Enum name="PULL_UP" start="0x0" description="Pull-up. P1.26 pin has a pull-up resistor enabled." /> + <Enum name="REPEATER" start="0x1" description="Repeater. P1.26 pin has repeater mode enabled." /> + <Enum name="DISABLED" start="0x2" description="Disabled. P1.26 pin has neither pull-up nor pull-down." /> + <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P1.26 has a pull-down resistor enabled." /> + </BitField> + <BitField start="22" size="2" name="P1_27MODE" description="Port 1 pin 27 control."> + <Enum name="PULL_UP" start="0x0" description="Pull-up. P1.27 pin has a pull-up resistor enabled." /> + <Enum name="REPEATER" start="0x1" description="Repeater. P1.27 pin has repeater mode enabled." /> + <Enum name="DISABLED" start="0x2" description="Disabled. P1.27 pin has neither pull-up nor pull-down." /> + <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P1.27 has a pull-down resistor enabled." /> + </BitField> + <BitField start="24" size="2" name="P1_28MODE" description="Port 1 pin 28 control."> + <Enum name="PULL_UP" start="0x0" description="Pull-up. P1.28 pin has a pull-up resistor enabled." /> + <Enum name="REPEATER" start="0x1" description="Repeater. P1.28 pin has repeater mode enabled." /> + <Enum name="DISABLED" start="0x2" description="Disabled. P1.28 pin has neither pull-up nor pull-down." /> + <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P1.28 has a pull-down resistor enabled." /> + </BitField> + <BitField start="26" size="2" name="P1_29MODE" description="Port 1 pin 29 control."> + <Enum name="PULL_UP" start="0x0" description="Pull-up. P1.29 pin has a pull-up resistor enabled." /> + <Enum name="REPEATER" start="0x1" description="Repeater. P1.29 pin has repeater mode enabled." /> + <Enum name="DISABLED" start="0x2" description="Disabled. P1.29 pin has neither pull-up nor pull-down." /> + <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P1.29 has a pull-down resistor enabled." /> + </BitField> + <BitField start="28" size="2" name="P1_30MODE" description="Port 1 pin 30 control."> + <Enum name="PULL_UP" start="0x0" description="Pull-up. P1.30 pin has a pull-up resistor enabled." /> + <Enum name="REPEATER" start="0x1" description="Repeater. P1.30 pin has repeater mode enabled." /> + <Enum name="DISABLED" start="0x2" description="Disabled. P1.30 pin has neither pull-up nor pull-down." /> + <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P1.30 has a pull-down resistor enabled." /> + </BitField> + <BitField start="30" size="2" name="P1_31MODE" description="Port 1 pin 31 control."> + <Enum name="PULL_UP" start="0x0" description="Pull-up. P1.31 pin has a pull-up resistor enabled." /> + <Enum name="REPEATER" start="0x1" description="Repeater. P1.31 pin has repeater mode enabled." /> + <Enum name="DISABLED" start="0x2" description="Disabled. P1.31 pin has neither pull-up nor pull-down." /> + <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P1.31 has a pull-down resistor enabled." /> + </BitField> + </Register> + <Register start="+0x050" size="4" name="PINMODE4" access="Read/Write" description="Pin mode select register 4" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="P2_00MODE" description="Port 2 pin 0 control."> + <Enum name="PULL_UP" start="0x0" description="Pull-up. P2.0 pin has a pull-up resistor enabled." /> + <Enum name="REPEATER" start="0x1" description="Repeater. P2.0 pin has repeater mode enabled." /> + <Enum name="DISABLED" start="0x2" description="Disabled. P2.0 pin has neither pull-up nor pull-down." /> + <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P2.0 has a pull-down resistor enabled." /> + </BitField> + <BitField start="2" size="2" name="P2_01MODE" description="Port 2 pin 1 control."> + <Enum name="PULL_UP" start="0x0" description="Pull-up. P2.1 pin has a pull-up resistor enabled." /> + <Enum name="REPEATER" start="0x1" description="Repeater. P2.1 pin has repeater mode enabled." /> + <Enum name="DISABLED" start="0x2" description="Disabled. P2.1 pin has neither pull-up nor pull-down." /> + <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P2.1 has a pull-down resistor enabled." /> + </BitField> + <BitField start="4" size="2" name="P2_02MODE" description="Port 2 pin 2 control."> + <Enum name="PULL_UP" start="0x0" description="Pull-up. P2.2 pin has a pull-up resistor enabled." /> + <Enum name="REPEATER" start="0x1" description="Repeater. P2.2 pin has repeater mode enabled." /> + <Enum name="DISABLED" start="0x2" description="Disabled. P2.2 pin has neither pull-up nor pull-down." /> + <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P2.2 has a pull-down resistor enabled." /> + </BitField> + <BitField start="6" size="2" name="P2_03MODE" description="Port 2 pin 3 control."> + <Enum name="PULL_UP" start="0x0" description="Pull-up. P2.3 pin has a pull-up resistor enabled." /> + <Enum name="REPEATER" start="0x1" description="Repeater. P2.3 pin has repeater mode enabled." /> + <Enum name="DISABLED" start="0x2" description="Disabled. P2.3 pin has neither pull-up nor pull-down." /> + <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P2.3 has a pull-down resistor enabled." /> + </BitField> + <BitField start="8" size="2" name="P2_04MODE" description="Port 2 pin 4 control."> + <Enum name="PULL_UP" start="0x0" description="Pull-up. P2.4 pin has a pull-up resistor enabled." /> + <Enum name="REPEATER" start="0x1" description="Repeater. P2.4 pin has repeater mode enabled." /> + <Enum name="DISABLED" start="0x2" description="Disabled. P2.4 pin has neither pull-up nor pull-down." /> + <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P2.4 has a pull-down resistor enabled." /> + </BitField> + <BitField start="10" size="2" name="P2_05MODE" description="Port 2 pin 5 control."> + <Enum name="PULL_UP" start="0x0" description="Pull-up. P2.5 pin has a pull-up resistor enabled." /> + <Enum name="REPEATER" start="0x1" description="Repeater. P2.5 pin has repeater mode enabled." /> + <Enum name="DISABLED" start="0x2" description="Disabled. P2.5 pin has neither pull-up nor pull-down." /> + <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P2.5 has a pull-down resistor enabled." /> + </BitField> + <BitField start="12" size="2" name="P2_06MODE" description="Port 2 pin 6 control."> + <Enum name="PULL_UP" start="0x0" description="Pull-up. P2.6 pin has a pull-up resistor enabled." /> + <Enum name="REPEATER" start="0x1" description="Repeater. P2.6 pin has repeater mode enabled." /> + <Enum name="DISABLED" start="0x2" description="Disabled. P2.6 pin has neither pull-up nor pull-down." /> + <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P2.6 has a pull-down resistor enabled." /> + </BitField> + <BitField start="14" size="2" name="P2_07MODE" description="Port 2 pin 7 control."> + <Enum name="PULL_UP" start="0x0" description="Pull-up. P2.7 pin has a pull-up resistor enabled." /> + <Enum name="REPEATER" start="0x1" description="Repeater. P2.7 pin has repeater mode enabled." /> + <Enum name="DISABLED" start="0x2" description="Disabled. P2.7 pin has neither pull-up nor pull-down." /> + <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P2.7 has a pull-down resistor enabled." /> + </BitField> + <BitField start="16" size="2" name="P2_08MODE" description="Port 2 pin 8 control."> + <Enum name="PULL_UP" start="0x0" description="Pull-up. P2.8 pin has a pull-up resistor enabled." /> + <Enum name="REPEATER" start="0x1" description="Repeater. P2.8 pin has repeater mode enabled." /> + <Enum name="DISABLED" start="0x2" description="Disabled. P2.8 pin has neither pull-up nor pull-down." /> + <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P2.8 has a pull-down resistor enabled." /> + </BitField> + <BitField start="18" size="2" name="P2_09MODE" description="Port 2 pin 9 control."> + <Enum name="PULL_UP" start="0x0" description="Pull-up. P2.9 pin has a pull-up resistor enabled." /> + <Enum name="REPEATER" start="0x1" description="Repeater. P2.9 pin has repeater mode enabled." /> + <Enum name="DISABLED" start="0x2" description="Disabled. P2.9 pin has neither pull-up nor pull-down." /> + <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P2.9 has a pull-down resistor enabled." /> + </BitField> + <BitField start="20" size="2" name="P2_10MODE" description="Port 2 pin 10 control."> + <Enum name="PULL_UP" start="0x0" description="Pull-up. P2.10 pin has a pull-up resistor enabled." /> + <Enum name="REPEATER" start="0x1" description="Repeater. P2.10 pin has repeater mode enabled." /> + <Enum name="DISABLED" start="0x2" description="Disabled. P2.10 pin has neither pull-up nor pull-down." /> + <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P2.10 has a pull-down resistor enabled." /> + </BitField> + <BitField start="22" size="2" name="P2_11MODE" description="Port 2 pin 11 control."> + <Enum name="PULL_UP" start="0x0" description="Pull-up. P2.11 pin has a pull-up resistor enabled." /> + <Enum name="REPEATER" start="0x1" description="Repeater. P2.11 pin has repeater mode enabled." /> + <Enum name="DISABLED" start="0x2" description="Disabled. P2.11 pin has neither pull-up nor pull-down." /> + <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P2.11 has a pull-down resistor enabled." /> + </BitField> + <BitField start="24" size="2" name="P2_12MODE" description="Port 2 pin 12 control."> + <Enum name="PULL_UP" start="0x0" description="Pull-up. P2.12 pin has a pull-up resistor enabled." /> + <Enum name="REPEATER" start="0x1" description="Repeater. P2.12 pin has repeater mode enabled." /> + <Enum name="DISABLED" start="0x2" description="Disabled. P2.12 pin has neither pull-up nor pull-down." /> + <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P2.12 has a pull-down resistor enabled." /> + </BitField> + <BitField start="26" size="2" name="P2_13MODE" description="Port 2 pin 13 control."> + <Enum name="PULL_UP" start="0x0" description="Pull-up. P2.13 pin has a pull-up resistor enabled." /> + <Enum name="REPEATER" start="0x1" description="Repeater. P2.13 pin has repeater mode enabled." /> + <Enum name="DISABLED" start="0x2" description="Disabled. P2.13 pin has neither pull-up nor pull-down." /> + <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P2.13 has a pull-down resistor enabled." /> + </BitField> + <BitField start="28" size="4" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x05C" size="4" name="PINMODE7" access="Read/Write" description="Pin mode select register 7" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="18" name="RESERVED" description="Reserved" /> + <BitField start="18" size="2" name="P3_25MODE" description="Port 3 pin 25 control."> + <Enum name="PULL_UP" start="0x0" description="Pull-up. P3.25 pin has a pull-up resistor enabled." /> + <Enum name="REPEATER" start="0x1" description="Repeater. P3.25 pin has repeater mode enabled." /> + <Enum name="DISABLED" start="0x2" description="Disabled. P3.25 pin has neither pull-up nor pull-down." /> + <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P3.25 has a pull-down resistor enabled." /> + </BitField> + <BitField start="20" size="2" name="P3_26MODE" description="Port 3 pin 26 control."> + <Enum name="PULL_UP" start="0x0" description="Pull-up. P3.26 pin has a pull-up resistor enabled." /> + <Enum name="REPEATER" start="0x1" description="Repeater. P3.26 pin has repeater mode enabled." /> + <Enum name="DISABLED" start="0x2" description="Disabled. P3.26 pin has neither pull-up nor pull-down." /> + <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P3.26 has a pull-down resistor enabled." /> + </BitField> + <BitField start="22" size="10" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x064" size="4" name="PINMODE9" access="Read/Write" description="Pin mode select register 9" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="24" name="RESERVED" description="Reserved." /> + <BitField start="24" size="2" name="P4_28MODE" description="Port 4 pin 28 control."> + <Enum name="PULL_UP" start="0x0" description="Pull-up. P4.28 pin has a pull-up resistor enabled." /> + <Enum name="REPEATER" start="0x1" description="Repeater. P4.28 pin has repeater mode enabled." /> + <Enum name="DISABLED" start="0x2" description="Disabled. P4.28 pin has neither pull-up nor pull-down." /> + <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P4.28 has a pull-down resistor enabled." /> + </BitField> + <BitField start="26" size="2" name="P4_29MODE" description="Port 4 pin 29 control."> + <Enum name="PULL_UP" start="0x0" description="Pull-up. P4.29 pin has a pull-up resistor enabled." /> + <Enum name="REPEATER" start="0x1" description="Repeater. P4.29 pin has repeater mode enabled." /> + <Enum name="DISABLED" start="0x2" description="Disabled. P4.29 pin has neither pull-up nor pull-down." /> + <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P4.29 has a pull-down resistor enabled." /> + </BitField> + <BitField start="28" size="4" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x068" size="4" name="PINMODE_OD0" access="Read/Write" description="Open drain mode control register 0" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="P0_00OD" description="Port 0 pin 0 open drain mode control. Pins may potentially be used for I2C-buses using standard port pins. If so, they should be configured for open drain mode via the related bits in PINMODE_OD0."> + <Enum name="NORMAL" start="0" description="Normal. P0.0 pin is in the normal (not open drain) mode." /> + <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P0.0 pin is in the open drain mode." /> + </BitField> + <BitField start="1" size="1" name="P0_01OD" description="Port 0 pin 1 open drain mode control. Pins may potentially be used for I2C-buses using standard port pins. If so, they should be configured for open drain mode via the related bits in PINMODE_OD0."> + <Enum name="NORMAL" start="0" description="Normal. P0.1 pin is in the normal (not open drain) mode." /> + <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P0.1 pin is in the open drain mode." /> + </BitField> + <BitField start="2" size="1" name="P0_02OD" description="Port 0 pin 2 open drain mode control"> + <Enum name="NORMAL" start="0" description="Normal. P0.2 pin is in the normal (not open drain) mode." /> + <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P0.2 pin is in the open drain mode." /> + </BitField> + <BitField start="3" size="1" name="P0_03OD" description="Port 0 pin 3 open drain mode control"> + <Enum name="NORMAL" start="0" description="Normal. P0.3 pin is in the normal (not open drain) mode." /> + <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P0.3 pin is in the open drain mode." /> + </BitField> + <BitField start="4" size="1" name="P0_04OD" description="Port 0 pin 4 open drain mode control"> + <Enum name="NORMAL" start="0" description="Normal. P0.4 pin is in the normal (not open drain) mode." /> + <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P0.4 pin is in the open drain mode." /> + </BitField> + <BitField start="5" size="1" name="P0_05OD" description="Port 0 pin 5 open drain mode control"> + <Enum name="NORMAL" start="0" description="Normal. P0.5 pin is in the normal (not open drain) mode." /> + <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P0.5 pin is in the open drain mode." /> + </BitField> + <BitField start="6" size="1" name="P0_06OD" description="Port 0 pin 6 open drain mode control"> + <Enum name="NORMAL" start="0" description="Normal. P0.6 pin is in the normal (not open drain) mode." /> + <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P0.6 pin is in the open drain mode." /> + </BitField> + <BitField start="7" size="1" name="P0_07OD" description="Port 0 pin 7 open drain mode control"> + <Enum name="NORMAL" start="0" description="Normal. P0.7 pin is in the normal (not open drain) mode." /> + <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P0.7 pin is in the open drain mode." /> + </BitField> + <BitField start="8" size="1" name="P0_08OD" description="Port 0 pin 8 open drain mode control"> + <Enum name="NORMAL" start="0" description="Normal. P0.8 pin is in the normal (not open drain) mode." /> + <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P0.8 pin is in the open drain mode." /> + </BitField> + <BitField start="9" size="1" name="P0_09OD" description="Port 0 pin 9 open drain mode control"> + <Enum name="NORMAL" start="0" description="Normal. P0.9 pin is in the normal (not open drain) mode." /> + <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P0.9 pin is in the open drain mode." /> + </BitField> + <BitField start="10" size="1" name="P0_10OD" description="Port 0 pin 10 open drain mode control. Pins may potentially be used for I2C-buses using standard port pins. If so, they should be configured for open drain mode via the related bits in PINMODE_OD0."> + <Enum name="NORMAL" start="0" description="Normal. P0.10 pin is in the normal (not open drain) mode." /> + <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P0.10 pin is in the open drain mode." /> + </BitField> + <BitField start="11" size="1" name="P0_11OD" description="Port 0 pin 11 open drain mode control. Pins may potentially be used for I2C-buses using standard port pins. If so, they should be configured for open drain mode via the related bits in PINMODE_OD0."> + <Enum name="NORMAL" start="0" description="Normal. P0.11 pin is in the normal (not open drain) mode." /> + <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P0.11 pin is in the open drain mode." /> + </BitField> + <BitField start="12" size="3" name="RESERVED" description="Reserved." /> + <BitField start="15" size="1" name="P0_15OD" description="Port 0 pin 15 open drain mode control"> + <Enum name="NORMAL" start="0" description="Normal. P0.15 pin is in the normal (not open drain) mode." /> + <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P0.15 pin is in the open drain mode." /> + </BitField> + <BitField start="16" size="1" name="P0_16OD" description="Port 0 pin 16 open drain mode control"> + <Enum name="NORMAL" start="0" description="Normal. P0.16 pin is in the normal (not open drain) mode." /> + <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P0.16 pin is in the open drain mode." /> + </BitField> + <BitField start="17" size="1" name="P0_17OD" description="Port 0 pin 17 open drain mode control"> + <Enum name="NORMAL" start="0" description="Normal. P0.17 pin is in the normal (not open drain) mode." /> + <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P0.17 pin is in the open drain mode." /> + </BitField> + <BitField start="18" size="1" name="P0_18OD" description="Port 0 pin 18 open drain mode control"> + <Enum name="NORMAL" start="0" description="Normal. P0.18 pin is in the normal (not open drain) mode." /> + <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P0.18 pin is in the open drain mode." /> + </BitField> + <BitField start="19" size="1" name="P0_19OD" description="Port 0 pin 19 open drain mode control. Pins may potentially be used for I2C-buses using standard port pins. If so, they should be configured for open drain mode via the related bits in PINMODE_OD0."> + <Enum name="NORMAL" start="0" description="Normal. P0.19 pin is in the normal (not open drain) mode." /> + <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P0.19 pin is in the open drain mode." /> + </BitField> + <BitField start="20" size="1" name="P0_20OD" description="Port 0 pin 20open drain mode control. Pins may potentially be used for I2C-buses using standard port pins. If so, they should be configured for open drain mode via the related bits in PINMODE_OD0."> + <Enum name="NORMAL" start="0" description="Normal. P0.20 pin is in the normal (not open drain) mode." /> + <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P0.20 pin is in the open drain mode." /> + </BitField> + <BitField start="21" size="1" name="P0_21OD" description="Port 0 pin 21 open drain mode control"> + <Enum name="NORMAL" start="0" description="Normal. P0.21 pin is in the normal (not open drain) mode." /> + <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P0.21 pin is in the open drain mode." /> + </BitField> + <BitField start="22" size="1" name="P0_22OD" description="Port 0 pin 22 open drain mode control"> + <Enum name="NORMAL" start="0" description="Normal. P0.22 pin is in the normal (not open drain) mode." /> + <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P0.22 pin is in the open drain mode." /> + </BitField> + <BitField start="23" size="1" name="P0_23OD" description="Port 0 pin 23 open drain mode control"> + <Enum name="NORMAL" start="0" description="Normal. P0.23 pin is in the normal (not open drain) mode." /> + <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P0.23 pin is in the open drain mode." /> + </BitField> + <BitField start="24" size="1" name="P0_24OD" description="Port 0 pin 24open drain mode control"> + <Enum name="NORMAL" start="0" description="Normal. P0.23 pin is in the normal (not open drain) mode." /> + <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P0.23 pin is in the open drain mode." /> + </BitField> + <BitField start="25" size="1" name="P0_25OD" description="Port 0 pin 25 open drain mode control"> + <Enum name="NORMAL" start="0" description="Normal. P0.25 pin is in the normal (not open drain) mode." /> + <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P0.25 pin is in the open drain mode." /> + </BitField> + <BitField start="26" size="1" name="P0_26OD" description="Port 0 pin 26 open drain mode control"> + <Enum name="NORMAL" start="0" description="Normal. P0.26 pin is in the normal (not open drain) mode." /> + <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P0.26 pin is in the open drain mode." /> + </BitField> + <BitField start="27" size="2" name="RESERVED" description="Reserved." /> + <BitField start="29" size="1" name="P0_29OD" description="Port 0 pin 29 open drain mode control"> + <Enum name="NORMAL" start="0" description="Normal. P0.29 pin is in the normal (not open drain) mode." /> + <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P0.29 pin is in the open drain mode." /> + </BitField> + <BitField start="30" size="1" name="P0_30OD" description="Port 0 pin 30 open drain mode control"> + <Enum name="NORMAL" start="0" description="Normal. P0.30 pin is in the normal (not open drain) mode." /> + <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P0.30 pin is in the open drain mode." /> + </BitField> + <BitField start="31" size="1" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x06C" size="4" name="PINMODE_OD1" access="Read/Write" description="Open drain mode control register 1" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="P1_00OD" description="Port 1 pin 0 open drain mode control."> + <Enum name="NORMAL" start="0" description="Normal. P1.0 pin is in the normal (not open drain) mode." /> + <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P1.0 pin is in the open drain mode." /> + </BitField> + <BitField start="1" size="1" name="P1_01OD" description="Port 1 pin 1 open drain mode control, see P1.00OD"> + <Enum name="NORMAL" start="0" description="Normal. P1.1 pin is in the normal (not open drain) mode." /> + <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P1.1 pin is in the open drain mode." /> + </BitField> + <BitField start="2" size="2" name="RESERVED" description="Reserved." /> + <BitField start="4" size="1" name="P1_04OD" description="Port 1 pin 4 open drain mode control, see P1.00OD"> + <Enum name="NORMAL" start="0" description="Normal. P1.4 pin is in the normal (not open drain) mode." /> + <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P1.4 pin is in the open drain mode." /> + </BitField> + <BitField start="5" size="3" name="RESERVED" description="Reserved." /> + <BitField start="8" size="1" name="P1_08OD" description="Port 1 pin 8 open drain mode control, see P1.00OD"> + <Enum name="NORMAL" start="0" description="Normal. P1.8 pin is in the normal (not open drain) mode." /> + <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P1.8 pin is in the open drain mode." /> + </BitField> + <BitField start="9" size="1" name="P1_09OD" description="Port 1 pin 9 open drain mode control, see P1.00OD"> + <Enum name="NORMAL" start="0" description="Normal. P1.9 pin is in the normal (not open drain) mode." /> + <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P1.9 pin is in the open drain mode." /> + </BitField> + <BitField start="10" size="1" name="P1_10OD" description="Port 1 pin 10 open drain mode control, see P1.00OD"> + <Enum name="NORMAL" start="0" description="Normal. P1.10 pin is in the normal (not open drain) mode." /> + <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P1.10 pin is in the open drain mode." /> + </BitField> + <BitField start="11" size="3" name="RESERVED" description="Reserved." /> + <BitField start="14" size="1" name="P1_14OD" description="Port 1 pin 14 open drain mode control, see P1.00OD"> + <Enum name="NORMAL" start="0" description="Normal. P1.14 pin is in the normal (not open drain) mode." /> + <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P1.14 pin is in the open drain mode." /> + </BitField> + <BitField start="15" size="1" name="P1_15OD" description="Port 1 pin 15 open drain mode control, see P1.00OD"> + <Enum name="NORMAL" start="0" description="Normal. P1.15 pin is in the normal (not open drain) mode." /> + <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P1.15 pin is in the open drain mode." /> + </BitField> + <BitField start="16" size="1" name="P1_16OD" description="Port 1 pin 16 open drain mode control, see P1.00OD"> + <Enum name="NORMAL" start="0" description="Normal. P1.16 pin is in the normal (not open drain) mode." /> + <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P1.16 pin is in the open drain mode." /> + </BitField> + <BitField start="17" size="1" name="P1_17OD" description="Port 1 pin 17 open drain mode control, see P1.00OD"> + <Enum name="NORMAL" start="0" description="Normal. P1.17 pin is in the normal (not open drain) mode." /> + <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P1.17 pin is in the open drain mode." /> + </BitField> + <BitField start="18" size="1" name="P1_18OD" description="Port 1 pin 18 open drain mode control, see P1.00OD"> + <Enum name="NORMAL" start="0" description="Normal. P1.18 pin is in the normal (not open drain) mode." /> + <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P1.18 pin is in the open drain mode." /> + </BitField> + <BitField start="19" size="1" name="P1_19OD" description="Port 1 pin 19 open drain mode control, see P1.00OD"> + <Enum name="NORMAL" start="0" description="Normal. P1.19 pin is in the normal (not open drain) mode." /> + <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P1.19 pin is in the open drain mode." /> + </BitField> + <BitField start="20" size="1" name="P1_20OD" description="Port 1 pin 20open drain mode control, see P1.00OD"> + <Enum name="NORMAL" start="0" description="Normal. P1.20 pin is in the normal (not open drain) mode." /> + <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P1.20 pin is in the open drain mode." /> + </BitField> + <BitField start="21" size="1" name="P1_21OD" description="Port 1 pin 21 open drain mode control, see P1.00OD"> + <Enum name="NORMAL" start="0" description="Normal. P1.21 pin is in the normal (not open drain) mode." /> + <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P1.21 pin is in the open drain mode." /> + </BitField> + <BitField start="22" size="1" name="P1_22OD" description="Port 1 pin 22 open drain mode control, see P1.00OD"> + <Enum name="NORMAL" start="0" description="Normal. P1.22 pin is in the normal (not open drain) mode." /> + <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P1.22 pin is in the open drain mode." /> + </BitField> + <BitField start="23" size="1" name="P1_23OD" description="Port 1 pin 23 open drain mode control, see P1.00OD"> + <Enum name="NORMAL" start="0" description="Normal. P1.23 pin is in the normal (not open drain) mode." /> + <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P1.23 pin is in the open drain mode." /> + </BitField> + <BitField start="24" size="1" name="P1_24OD" description="Port 1 pin 24open drain mode control, see P1.00OD"> + <Enum name="NORMAL" start="0" description="Normal. P1.24 pin is in the normal (not open drain) mode." /> + <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P1.24 pin is in the open drain mode." /> + </BitField> + <BitField start="25" size="1" name="P1_25OD" description="Port 1 pin 25 open drain mode control, see P1.00OD"> + <Enum name="NORMAL" start="0" description="Normal. P1.25 pin is in the normal (not open drain) mode." /> + <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P1.25 pin is in the open drain mode." /> + </BitField> + <BitField start="26" size="1" name="P1_26OD" description="Port 1 pin 26 open drain mode control, see P1.00OD"> + <Enum name="NORMAL" start="0" description="Normal. P1.26 pin is in the normal (not open drain) mode." /> + <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P1.26 pin is in the open drain mode." /> + </BitField> + <BitField start="27" size="1" name="P1_27OD" description="Port 1 pin 27 open drain mode control, see P1.00OD"> + <Enum name="NORMAL" start="0" description="Normal. P1.27 pin is in the normal (not open drain) mode." /> + <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P1.27 pin is in the open drain mode." /> + </BitField> + <BitField start="28" size="1" name="P1_28OD" description="Port 1 pin 28 open drain mode control, see P1.00OD"> + <Enum name="NORMAL" start="0" description="Normal. P1.28 pin is in the normal (not open drain) mode." /> + <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P1.28 pin is in the open drain mode." /> + </BitField> + <BitField start="29" size="1" name="P1_29OD" description="Port 1 pin 29 open drain mode control, see P1.00OD"> + <Enum name="NORMAL" start="0" description="Normal. P1.29 pin is in the normal (not open drain) mode." /> + <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P1.29 pin is in the open drain mode." /> + </BitField> + <BitField start="30" size="1" name="P1_30OD" description="Port 1 pin 30 open drain mode control, see P1.00OD"> + <Enum name="NORMAL" start="0" description="Normal. P1.30 pin is in the normal (not open drain) mode." /> + <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P1.30 pin is in the open drain mode." /> + </BitField> + <BitField start="31" size="1" name="P1_31OD" description="Port 1 pin 31 open drain mode control."> + <Enum name="NORMAL" start="0" description="Normal. P1.31 pin is in the normal (not open drain) mode." /> + <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P1.31 pin is in the open drain mode." /> + </BitField> + </Register> + <Register start="+0x070" size="4" name="PINMODE_OD2" access="Read/Write" description="Open drain mode control register 2" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="P2_00OD" description="Port 2 pin 0 open drain mode control."> + <Enum name="NORMAL" start="0" description="Normal. P2.0 pin is in the normal (not open drain) mode." /> + <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P2.0 pin is in the open drain mode." /> + </BitField> + <BitField start="1" size="1" name="P2_01OD" description="Port 2 pin 1 open drain mode control, see P2.00OD"> + <Enum name="NORMAL" start="0" description="Normal. P2.1 pin is in the normal (not open drain) mode." /> + <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P2.1p in is in the open drain mode." /> + </BitField> + <BitField start="2" size="1" name="P2_02OD" description="Port 2 pin 2 open drain mode control, see P2.00OD"> + <Enum name="NORMAL" start="0" description="Normal. P2.2 pin is in the normal (not open drain) mode." /> + <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P2.2 pin is in the open drain mode." /> + </BitField> + <BitField start="3" size="1" name="P2_03OD" description="Port 2 pin 3 open drain mode control, see P2.00OD"> + <Enum name="NORMAL" start="0" description="Normal. P2.3 pin is in the normal (not open drain) mode." /> + <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P2.3 pin is in the open drain mode." /> + </BitField> + <BitField start="4" size="1" name="P2_04OD" description="Port 2 pin 4 open drain mode control, see P2.00OD"> + <Enum name="NORMAL" start="0" description="Normal. P2.4 pin is in the normal (not open drain) mode." /> + <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P2.4 pin is in the open drain mode." /> + </BitField> + <BitField start="5" size="1" name="P2_05OD" description="Port 2 pin 5 open drain mode control, see P2.00OD"> + <Enum name="NORMAL" start="0" description="Normal. P2.5 pin is in the normal (not open drain) mode." /> + <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P2.5 pin is in the open drain mode." /> + </BitField> + <BitField start="6" size="1" name="P2_06OD" description="Port 2 pin 6 open drain mode control, see P2.00OD"> + <Enum name="NORMAL" start="0" description="Normal. P2.6 pin is in the normal (not open drain) mode." /> + <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P2.6 pin is in the open drain mode." /> + </BitField> + <BitField start="7" size="1" name="P2_07OD" description="Port 2 pin 7 open drain mode control, see P2.00OD"> + <Enum name="NORMAL" start="0" description="Normal. P2.7 pin is in the normal (not open drain) mode." /> + <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P2.7 pin is in the open drain mode." /> + </BitField> + <BitField start="8" size="1" name="P2_08OD" description="Port 2 pin 8 open drain mode control, see P2.00OD"> + <Enum name="NORMAL" start="0" description="Normal. P2.8 pin is in the normal (not open drain) mode." /> + <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P2.8 pin is in the open drain mode." /> + </BitField> + <BitField start="9" size="1" name="P2_09OD" description="Port 2 pin 9 open drain mode control, see P2.00OD"> + <Enum name="NORMAL" start="0" description="Normal. P2.9 pin is in the normal (not open drain) mode." /> + <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P2.9 pin is in the open drain mode." /> + </BitField> + <BitField start="10" size="1" name="P2_10OD" description="Port 2 pin 10 open drain mode control, see P2.00OD"> + <Enum name="NORMAL" start="0" description="Normal. P2.10 pin is in the normal (not open drain) mode." /> + <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P2.10 pin is in the open drain mode." /> + </BitField> + <BitField start="11" size="1" name="P2_11OD" description="Port 2 pin 11 open drain mode control, see P2.00OD"> + <Enum name="NORMAL" start="0" description="Normal. P2.11 pin is in the normal (not open drain) mode." /> + <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P2.11 pin is in the open drain mode." /> + </BitField> + <BitField start="12" size="1" name="P2_12OD" description="Port 2 pin 12 open drain mode control, see P2.00OD"> + <Enum name="NORMAL" start="0" description="Normal. P2.12 pin is in the normal (not open drain) mode." /> + <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P2.12 pin is in the open drain mode." /> + </BitField> + <BitField start="13" size="1" name="P2_13OD" description="Port 2 pin 13 open drain mode control, see P2.00OD"> + <Enum name="NORMAL" start="0" description="Normal. P2.13 pin is in the normal (not open drain) mode." /> + <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P2.13 pin is in the open drain mode." /> + </BitField> + <BitField start="14" size="18" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x074" size="4" name="PINMODE_OD3" access="Read/Write" description="Open drain mode control register 3" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="25" name="RESERVED" description="Reserved." /> + <BitField start="25" size="1" name="P3_25OD" description="Port 3 pin 25 open drain mode control."> + <Enum name="NORMAL" start="0" description="Normal. P3.25 pin is in the normal (not open drain) mode." /> + <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P3.25 pin is in the open drain mode." /> + </BitField> + <BitField start="26" size="1" name="P3_26OD" description="Port 3 pin 26 open drain mode control, see P3.25OD" /> + <BitField start="27" size="5" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x078" size="4" name="PINMODE_OD4" access="Read/Write" description="Open drain mode control register 4" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="28" name="RESERVED" description="Reserved." /> + <BitField start="28" size="1" name="P4_28OD" description="Port 4 pin 28 open drain mode control."> + <Enum name="NORMAL" start="0" description="Normal. P4.28 pin is in the normal (not open drain) mode." /> + <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P4.28 pin is in the open drain mode." /> + </BitField> + <BitField start="29" size="1" name="P4_29OD" description="Port 4 pin 29 open drain mode control, see P4.28OD" /> + <BitField start="30" size="2" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x07C" size="4" name="I2CPADCFG" access="Read/Write" description="I2C Pin Configuration register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="SDADRV0" description="Drive mode control for the SDA0 pin, P0.27."> + <Enum name="STANDARD" start="0" description="Standard. The SDA0 pin is in the standard drive mode." /> + <Enum name="FAST_MODE_PLUS" start="1" description="Fast-mode plus. The SDA0 pin is in Fast Mode Plus drive mode." /> + </BitField> + <BitField start="1" size="1" name="SDAI2C0" description="I 2C filter mode control for the SDA0 pin, P0.27."> + <Enum name="ENABLED" start="0" description="Enabled. The SDA0 pin has I2C glitch filtering and slew rate control enabled." /> + <Enum name="DISABLED" start="1" description="Disabled. The SDA0 pin has I2C glitch filtering and slew rate control disabled." /> + </BitField> + <BitField start="2" size="1" name="SCLDRV0" description="Drive mode control for the SCL0 pin, P0.28."> + <Enum name="STANDARD" start="0" description="Standard. The SCL0 pin is in the standard drive mode." /> + <Enum name="FAST_MODE_PLUS" start="1" description="Fast-mode plus. The SCL0 pin is in Fast Mode Plus drive mode." /> + </BitField> + <BitField start="3" size="1" name="SCLI2C0" description="I 2C filter mode control for the SCL0 pin, P0.28."> + <Enum name="ENABLED" start="0" description="Enabled. The SCL0 pin has I2C glitch filtering and slew rate control enabled." /> + <Enum name="DISABLED" start="1" description="Disabled. The SCL0 pin has I2C glitch filtering and slew rate control disabled." /> + </BitField> + <BitField start="4" size="28" name="RESERVED" description="Reserved." /> + </Register> + </RegisterGroup> + <RegisterGroup name="SSP1" start="0x40030000" description="SSP1 controller"> + <Register start="+0x000" size="4" name="CR0" access="Read/Write" description="Control Register 0. Selects the serial clock rate, bus type, and data size." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="4" name="DSS" description="Data Size Select. This field controls the number of bits transferred in each frame. Values 0000-0010 are not supported and should not be used."> + <Enum name="4_BIT_TRANSFER" start="0x3" description="4-bit transfer" /> + <Enum name="5_BIT_TRANSFER" start="0x4" description="5-bit transfer" /> + <Enum name="6_BIT_TRANSFER" start="0x5" description="6-bit transfer" /> + <Enum name="7_BIT_TRANSFER" start="0x6" description="7-bit transfer" /> + <Enum name="8_BIT_TRANSFER" start="0x7" description="8-bit transfer" /> + <Enum name="9_BIT_TRANSFER" start="0x8" description="9-bit transfer" /> + <Enum name="10_BIT_TRANSFER" start="0x9" description="10-bit transfer" /> + <Enum name="11_BIT_TRANSFER" start="0xA" description="11-bit transfer" /> + <Enum name="12_BIT_TRANSFER" start="0xB" description="12-bit transfer" /> + <Enum name="13_BIT_TRANSFER" start="0xC" description="13-bit transfer" /> + <Enum name="14_BIT_TRANSFER" start="0xD" description="14-bit transfer" /> + <Enum name="15_BIT_TRANSFER" start="0xE" description="15-bit transfer" /> + <Enum name="16_BIT_TRANSFER" start="0xF" description="16-bit transfer" /> + </BitField> + <BitField start="4" size="2" name="FRF" description="Frame Format."> + <Enum name="SPI" start="0x0" description="SPI" /> + <Enum name="TI" start="0x1" description="TI" /> + <Enum name="MICROWIRE" start="0x2" description="Microwire" /> + <Enum name="THIS_COMBINATION_IS_" start="0x3" description="This combination is not supported and should not be used." /> + </BitField> + <BitField start="6" size="1" name="CPOL" description="Clock Out Polarity. This bit is only used in SPI mode."> + <Enum name="BUS_LOW" start="0" description="SSP controller maintains the bus clock low between frames." /> + <Enum name="BUS_HIGH" start="1" description="SSP controller maintains the bus clock high between frames." /> + </BitField> + <BitField start="7" size="1" name="CPHA" description="Clock Out Phase. This bit is only used in SPI mode."> + <Enum name="FIRST_CLOCK" start="0" description="SSP controller captures serial data on the first clock transition of the frame, that is, the transition away from the inter-frame state of the clock line." /> + <Enum name="SECOND_CLOCK" start="1" description="SSP controller captures serial data on the second clock transition of the frame, that is, the transition back to the inter-frame state of the clock line." /> + </BitField> + <BitField start="8" size="8" name="SCR" description="Serial Clock Rate. The number of prescaler-output clocks per bit on the bus, minus one. Given that CPSDVSR is the prescale divider, and the APB clock PCLK clocks the prescaler, the bit frequency is PCLK / (CPSDVSR X [SCR+1])." /> + <BitField start="16" size="16" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x004" size="4" name="CR1" access="Read/Write" description="Control Register 1. Selects master/slave and other modes." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="LBM" description="Loop Back Mode."> + <Enum name="NORMAL" start="0" description="During normal operation." /> + <Enum name="OUPTU" start="1" description="Serial input is taken from the serial output (MOSI or MISO) rather than the serial input pin (MISO or MOSI respectively)." /> + </BitField> + <BitField start="1" size="1" name="SSE" description="SSP Enable."> + <Enum name="DISABLED" start="0" description="The SSP controller is disabled." /> + <Enum name="ENABLED" start="1" description="The SSP controller will interact with other devices on the serial bus. Software should write the appropriate control information to the other SSP registers and interrupt controller registers, before setting this bit." /> + </BitField> + <BitField start="2" size="1" name="MS" description="Master/Slave Mode.This bit can only be written when the SSE bit is 0."> + <Enum name="MASTER" start="0" description="The SSP controller acts as a master on the bus, driving the SCLK, MOSI, and SSEL lines and receiving the MISO line." /> + <Enum name="SLAVE" start="1" description="The SSP controller acts as a slave on the bus, driving MISO line and receiving SCLK, MOSI, and SSEL lines." /> + </BitField> + <BitField start="3" size="1" name="SOD" description="Slave Output Disable. This bit is relevant only in slave mode (MS = 1). If it is 1, this blocks this SSP controller from driving the transmit data line (MISO)." /> + <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x008" size="4" name="DR" access="None" description="Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="16" name="DATA" description="Write: software can write data to be sent in a future frame to this register whenever the TNF bit in the Status register is 1, indicating that the Tx FIFO is not full. If the Tx FIFO was previously empty and the SSP controller is not busy on the bus, transmission of the data will begin immediately. Otherwise the data written to this register will be sent as soon as all previous data has been sent (and received). If the data length is less than 16 bits, software must right-justify the data written to this register. Read: software can read data from this register whenever the RNE bit in the Status register is 1, indicating that the Rx FIFO is not empty. When software reads this register, the SSP controller returns data from the least recent frame in the Rx FIFO. If the data length is less than 16 bits, the data is right-justified in this field with higher order bits filled with 0s." /> + <BitField start="16" size="16" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x00C" size="4" name="SR" access="ReadOnly" description="Status Register" reset_value="0x00000003" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="TFE" description="Transmit FIFO Empty. This bit is 1 is the Transmit FIFO is empty, 0 if not." /> + <BitField start="1" size="1" name="TNF" description="Transmit FIFO Not Full. This bit is 0 if the Tx FIFO is full, 1 if not." /> + <BitField start="2" size="1" name="RNE" description="Receive FIFO Not Empty. This bit is 0 if the Receive FIFO is empty, 1 if not." /> + <BitField start="3" size="1" name="RFF" description="Receive FIFO Full. This bit is 1 if the Receive FIFO is full, 0 if not." /> + <BitField start="4" size="1" name="BSY" description="Busy. This bit is 0 if the SSPn controller is idle, or 1 if it is currently sending/receiving a frame and/or the Tx FIFO is not empty." /> + <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x010" size="4" name="CPSR" access="Read/Write" description="Clock Prescale Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="CPSDVSR" description="This even value between 2 and 254, by which PCLK is divided to yield the prescaler output clock. Bit 0 always reads as 0." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x014" size="4" name="IMSC" access="Read/Write" description="Interrupt Mask Set and Clear Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RORIM" description="Software should set this bit to enable interrupt when a Receive Overrun occurs, that is, when the Rx FIFO is full and another frame is completely received. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs." /> + <BitField start="1" size="1" name="RTIM" description="Software should set this bit to enable interrupt when a Receive Time-out condition occurs. A Receive Time-out occurs when the Rx FIFO is not empty, and no has not been read for a time-out period. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1])." /> + <BitField start="2" size="1" name="RXIM" description="Software should set this bit to enable interrupt when the Rx FIFO is at least half full." /> + <BitField start="3" size="1" name="TXIM" description="Software should set this bit to enable interrupt when the Tx FIFO is at least half empty." /> + <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x018" size="4" name="RIS" access="ReadOnly" description="Raw Interrupt Status Register" reset_value="0x00000008" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RORRIS" description="This bit is 1 if another frame was completely received while the RxFIFO was full. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs." /> + <BitField start="1" size="1" name="RTRIS" description="This bit is 1 if the Rx FIFO is not empty, and has not been read for a time-out period. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1])." /> + <BitField start="2" size="1" name="RXRIS" description="This bit is 1 if the Rx FIFO is at least half full." /> + <BitField start="3" size="1" name="TXRIS" description="This bit is 1 if the Tx FIFO is at least half empty." /> + <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x01C" size="4" name="MIS" access="ReadOnly" description="Masked Interrupt Status Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RORMIS" description="This bit is 1 if another frame was completely received while the RxFIFO was full, and this interrupt is enabled." /> + <BitField start="1" size="1" name="RTMIS" description="This bit is 1 if the Rx FIFO is not empty, has not been read for a time-out period, and this interrupt is enabled. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1])." /> + <BitField start="2" size="1" name="RXMIS" description="This bit is 1 if the Rx FIFO is at least half full, and this interrupt is enabled." /> + <BitField start="3" size="1" name="TXMIS" description="This bit is 1 if the Tx FIFO is at least half empty, and this interrupt is enabled." /> + <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x020" size="4" name="ICR" access="WriteOnly" description="SSPICR Interrupt Clear Register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="RORIC" description="Writing a 1 to this bit clears the frame was received when RxFIFO was full interrupt." /> + <BitField start="1" size="1" name="RTIC" description="Writing a 1 to this bit clears the Rx FIFO was not empty and has not been read for a time-out period interrupt. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR / [SCR+1])." /> + <BitField start="2" size="30" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x024" size="4" name="DMACR" access="Read/Write" description="SSP0 DMA control register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RXDMAE" description="Receive DMA Enable. When this bit is set to one 1, DMA for the receive FIFO is enabled, otherwise receive DMA is disabled." /> + <BitField start="1" size="1" name="TXDMAE" description="Transmit DMA Enable. When this bit is set to one 1, DMA for the transmit FIFO is enabled, otherwise transmit DMA is disabled" /> + <BitField start="2" size="30" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + </RegisterGroup> + <RegisterGroup name="ADC" start="0x40034000" description="Analog-to-Digital Converter (ADC) "> + <Register start="+0x000" size="4" name="CR" access="Read/Write" description="A/D Control Register. The ADCR register must be written to select the operating mode before A/D conversion can occur." reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="8" name="SEL" description="Selects which of the AD0[7:0] pins is (are) to be sampled and converted. For AD0, bit 0 selects Pin AD0[0], and bit 7 selects pin AD0[7]. In software-controlled mode, only one of these bits should be 1. In hardware scan mode, any value containing 1 to 8 ones is allowed. All zeroes is equivalent to 0x01." /> + <BitField start="8" size="8" name="CLKDIV" description="The APB clock (PCLK) is divided by (this value plus one) to produce the clock for the A/D converter, which should be less than or equal to 12.4 MHz. Typically, software should program the smallest value in this field that yields a clock of 12.4 MHz or slightly less, but in certain cases (such as a high-impedance analog source) a slower clock may be desirable." /> + <BitField start="16" size="1" name="BURST" description="Burst mode"> + <Enum name="BURST" start="1" description="The AD converter does repeated conversions at up to 400 kHz, scanning (if necessary) through the pins selected by bits set to ones in the SEL field. The first conversion after the start corresponds to the least-significant 1 in the SEL field, then higher numbered 1-bits (pins) if applicable. Repeated conversions can be terminated by clearing this bit, but the conversion that's in progress when this bit is cleared will be completed. START bits must be 000 when BURST = 1 or conversions will not start." /> + <Enum name="SW" start="0" description="Conversions are software controlled and require 31 clocks." /> + </BitField> + <BitField start="17" size="4" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="21" size="1" name="PDN" description="Power down mode"> + <Enum name="POWERED" start="1" description="The A/D converter is operational." /> + <Enum name="POWERDOWN" start="0" description="The A/D converter is in power-down mode." /> + </BitField> + <BitField start="22" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="24" size="3" name="START" description="When the BURST bit is 0, these bits control whether and when an A/D conversion is started:"> + <Enum name="NO_START_THIS_VALUE" start="0x0" description="No start (this value should be used when clearing PDN to 0)." /> + <Enum name="START_CONVERSION_NOW" start="0x1" description="Start conversion now." /> + <Enum name="P2_10" start="0x2" description="Start conversion when the edge selected by bit 27 occurs on the P2[10] pin." /> + <Enum name="P1_27" start="0x3" description="Start conversion when the edge selected by bit 27 occurs on the P1[27] pin." /> + <Enum name="MAT0_1" start="0x4" description="Start conversion when the edge selected by bit 27 occurs on MAT0.1. Note that this does not require that the MAT0.1 function appear on a device pin." /> + <Enum name="MAT0_3" start="0x5" description="Start conversion when the edge selected by bit 27 occurs on MAT0.3. Note that it is not possible to cause the MAT0.3 function to appear on a device pin." /> + <Enum name="MAT1_0" start="0x6" description="Start conversion when the edge selected by bit 27 occurs on MAT1.0. Note that this does not require that the MAT1.0 function appear on a device pin." /> + <Enum name="MAT1_1" start="0x7" description="Start conversion when the edge selected by bit 27 occurs on MAT1.1. Note that this does not require that the MAT1.1 function appear on a device pin." /> + </BitField> + <BitField start="27" size="1" name="EDGE" description="This bit is significant only when the START field contains 010-111. In these cases:"> + <Enum name="FALLLING" start="1" description="Start conversion on a falling edge on the selected CAP/MAT signal." /> + <Enum name="RISING" start="0" description="Start conversion on a rising edge on the selected CAP/MAT signal." /> + </BitField> + <BitField start="28" size="4" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x004" size="4" name="GDR" access="Read/Write" description="A/D Global Data Register. This register contains the ADC's DONE bit and the result of the most recent A/D conversion." reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="4" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="4" size="12" name="RESULT" description="When DONE is 1, this field contains a binary fraction representing the voltage on the AD0[n] pin selected by the SEL field, as it falls within the range of VREFP to VSS. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VSS, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP." /> + <BitField start="16" size="8" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="24" size="3" name="CHN" description="These bits contain the channel from which the RESULT bits were converted (e.g. 000 identifies channel 0, 001 channel 1...)." /> + <BitField start="27" size="3" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the RESULT bits. This bit is cleared by reading this register." /> + <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read and when the ADCR is written. If the ADCR is written while a conversion is still in progress, this bit is set and a new conversion is started." /> + </Register> + <Register start="+0x00C" size="4" name="INTEN" access="Read/Write" description="A/D Interrupt Enable Register. This register contains enable bits that allow the DONE flag of each A/D channel to be included or excluded from contributing to the generation of an A/D interrupt." reset_value="0x100" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="ADINTEN0" description="Interrupt enable"> + <Enum name="DISABLE" start="0" description="Completion of a conversion on ADC channel 0 will not generate an interrupt." /> + <Enum name="ENABLE" start="1" description="Completion of a conversion on ADC channel 0 will generate an interrupt." /> + </BitField> + <BitField start="1" size="1" name="ADINTEN1" description="Interrupt enable"> + <Enum name="DISABLE" start="0" description="Completion of a conversion on ADC channel 1 will not generate an interrupt." /> + <Enum name="ENABLE" start="1" description="Completion of a conversion on ADC channel 1 will generate an interrupt." /> + </BitField> + <BitField start="2" size="1" name="ADINTEN2" description="Interrupt enable"> + <Enum name="DISABLE" start="0" description="Completion of a conversion on ADC channel 2 will not generate an interrupt." /> + <Enum name="ENABLE" start="1" description="Completion of a conversion on ADC channel 2 will generate an interrupt." /> + </BitField> + <BitField start="3" size="1" name="ADINTEN3" description="Interrupt enable"> + <Enum name="DISABLE" start="0" description="Completion of a conversion on ADC channel 3 will not generate an interrupt." /> + <Enum name="ENABLE" start="1" description="Completion of a conversion on ADC channel 3 will generate an interrupt." /> + </BitField> + <BitField start="4" size="1" name="ADINTEN4" description="Interrupt enable"> + <Enum name="DISABLE" start="0" description="Completion of a conversion on ADC channel 4 will not generate an interrupt." /> + <Enum name="ENABLE" start="1" description="Completion of a conversion on ADC channel 4 will generate an interrupt." /> + </BitField> + <BitField start="5" size="1" name="ADINTEN5" description="Interrupt enable"> + <Enum name="DISABLE" start="0" description="Completion of a conversion on ADC channel 5 will not generate an interrupt." /> + <Enum name="ENABLE" start="1" description="Completion of a conversion on ADC channel 5 will generate an interrupt." /> + </BitField> + <BitField start="6" size="1" name="ADINTEN6" description="Interrupt enable"> + <Enum name="DISABLE" start="0" description="Completion of a conversion on ADC channel 6 will not generate an interrupt." /> + <Enum name="ENABLE" start="1" description="Completion of a conversion on ADC channel 6 will generate an interrupt." /> + </BitField> + <BitField start="7" size="1" name="ADINTEN7" description="Interrupt enable"> + <Enum name="DISABLE" start="0" description="Completion of a conversion on ADC channel 7 will not generate an interrupt." /> + <Enum name="ENABLE" start="1" description="Completion of a conversion on ADC channel 7 will generate an interrupt." /> + </BitField> + <BitField start="8" size="1" name="ADGINTEN" description="Interrupt enable"> + <Enum name="CHANNELS" start="0" description="Only the individual ADC channels enabled by ADINTEN7:0 will generate interrupts." /> + <Enum name="GLOBAL" start="1" description="The global DONE flag in ADDR is enabled to generate an interrupt in addition to any individual ADC channels that are enabled to generate interrupts." /> + </BitField> + <BitField start="9" size="23" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x010+0" size="4" name="DR[0]" access="ReadOnly" description="A/D Channel 0 Data Register. This register contains the result of the most recent conversion completed on channel 0." reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="4" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="4" size="12" name="RESULT" description="When DONE is 1, this field contains a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to V SS. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VSS, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP." /> + <BitField start="16" size="14" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the RESULT bits.This bit is cleared by reading this register." /> + <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." /> + </Register> + <Register start="+0x010+4" size="4" name="DR[1]" access="ReadOnly" description="A/D Channel 0 Data Register. This register contains the result of the most recent conversion completed on channel 0." reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="4" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="4" size="12" name="RESULT" description="When DONE is 1, this field contains a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to V SS. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VSS, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP." /> + <BitField start="16" size="14" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the RESULT bits.This bit is cleared by reading this register." /> + <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." /> + </Register> + <Register start="+0x010+8" size="4" name="DR[2]" access="ReadOnly" description="A/D Channel 0 Data Register. This register contains the result of the most recent conversion completed on channel 0." reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="4" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="4" size="12" name="RESULT" description="When DONE is 1, this field contains a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to V SS. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VSS, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP." /> + <BitField start="16" size="14" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the RESULT bits.This bit is cleared by reading this register." /> + <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." /> + </Register> + <Register start="+0x010+12" size="4" name="DR[3]" access="ReadOnly" description="A/D Channel 0 Data Register. This register contains the result of the most recent conversion completed on channel 0." reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="4" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="4" size="12" name="RESULT" description="When DONE is 1, this field contains a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to V SS. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VSS, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP." /> + <BitField start="16" size="14" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the RESULT bits.This bit is cleared by reading this register." /> + <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." /> + </Register> + <Register start="+0x010+16" size="4" name="DR[4]" access="ReadOnly" description="A/D Channel 0 Data Register. This register contains the result of the most recent conversion completed on channel 0." reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="4" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="4" size="12" name="RESULT" description="When DONE is 1, this field contains a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to V SS. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VSS, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP." /> + <BitField start="16" size="14" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the RESULT bits.This bit is cleared by reading this register." /> + <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." /> + </Register> + <Register start="+0x010+20" size="4" name="DR[5]" access="ReadOnly" description="A/D Channel 0 Data Register. This register contains the result of the most recent conversion completed on channel 0." reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="4" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="4" size="12" name="RESULT" description="When DONE is 1, this field contains a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to V SS. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VSS, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP." /> + <BitField start="16" size="14" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the RESULT bits.This bit is cleared by reading this register." /> + <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." /> + </Register> + <Register start="+0x010+24" size="4" name="DR[6]" access="ReadOnly" description="A/D Channel 0 Data Register. This register contains the result of the most recent conversion completed on channel 0." reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="4" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="4" size="12" name="RESULT" description="When DONE is 1, this field contains a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to V SS. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VSS, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP." /> + <BitField start="16" size="14" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the RESULT bits.This bit is cleared by reading this register." /> + <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." /> + </Register> + <Register start="+0x010+28" size="4" name="DR[7]" access="ReadOnly" description="A/D Channel 0 Data Register. This register contains the result of the most recent conversion completed on channel 0." reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="4" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="4" size="12" name="RESULT" description="When DONE is 1, this field contains a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to V SS. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VSS, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP." /> + <BitField start="16" size="14" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the RESULT bits.This bit is cleared by reading this register." /> + <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." /> + </Register> + <Register start="+0x030" size="4" name="STAT" access="ReadOnly" description="A/D Status Register. This register contains DONE and OVERRUN flags for all of the A/D channels, as well as the A/D interrupt/DMA flag." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="DONE0" description="This bit mirrors the DONE status flag from the result register for A/D channel 0." /> + <BitField start="1" size="1" name="DONE1" description="This bit mirrors the DONE status flag from the result register for A/D channel 1." /> + <BitField start="2" size="1" name="DONE2" description="This bit mirrors the DONE status flag from the result register for A/D channel 2." /> + <BitField start="3" size="1" name="DONE3" description="This bit mirrors the DONE status flag from the result register for A/D channel 3." /> + <BitField start="4" size="1" name="DONE4" description="This bit mirrors the DONE status flag from the result register for A/D channel 4." /> + <BitField start="5" size="1" name="DONE5" description="This bit mirrors the DONE status flag from the result register for A/D channel 5." /> + <BitField start="6" size="1" name="DONE6" description="This bit mirrors the DONE status flag from the result register for A/D channel 6." /> + <BitField start="7" size="1" name="DONE7" description="This bit mirrors the DONE status flag from the result register for A/D channel 7." /> + <BitField start="8" size="1" name="OVERRUN0" description="This bit mirrors the OVERRRUN status flag from the result register for A/D channel 0." /> + <BitField start="9" size="1" name="OVERRUN1" description="This bit mirrors the OVERRRUN status flag from the result register for A/D channel 1." /> + <BitField start="10" size="1" name="OVERRUN2" description="This bit mirrors the OVERRRUN status flag from the result register for A/D channel 2." /> + <BitField start="11" size="1" name="OVERRUN3" description="This bit mirrors the OVERRRUN status flag from the result register for A/D channel 3." /> + <BitField start="12" size="1" name="OVERRUN4" description="This bit mirrors the OVERRRUN status flag from the result register for A/D channel 4." /> + <BitField start="13" size="1" name="OVERRUN5" description="This bit mirrors the OVERRRUN status flag from the result register for A/D channel 5." /> + <BitField start="14" size="1" name="OVERRUN6" description="This bit mirrors the OVERRRUN status flag from the result register for A/D channel 6." /> + <BitField start="15" size="1" name="OVERRUN7" description="This bit mirrors the OVERRRUN status flag from the result register for A/D channel 7." /> + <BitField start="16" size="1" name="ADINT" description="This bit is the A/D interrupt flag. It is one when any of the individual A/D channel Done flags is asserted and enabled to contribute to the A/D interrupt via the ADINTEN register." /> + <BitField start="17" size="15" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x034" size="4" name="TRM" access="Read/Write" description="ADC trim register." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="4" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="4" size="4" name="ADCOFFS" description="Offset trim bits for ADC operation. Initialized by the boot code. Can be overwritten by the user." /> + <BitField start="8" size="4" name="TRIM" description="written-to by boot code. Can not be overwritten by the user. These bits are locked after boot code write." /> + <BitField start="12" size="20" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + </RegisterGroup> + <RegisterGroup name="CANAFRAM" start="0x40038000" description="CAN acceptance filter RAM"> + <Register start="+0x000+0" size="4" name="MASK[0]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+4" size="4" name="MASK[1]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+8" size="4" name="MASK[2]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+12" size="4" name="MASK[3]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+16" size="4" name="MASK[4]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+20" size="4" name="MASK[5]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+24" size="4" name="MASK[6]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+28" size="4" name="MASK[7]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+32" size="4" name="MASK[8]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+36" size="4" name="MASK[9]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+40" size="4" name="MASK[10]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+44" size="4" name="MASK[11]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+48" size="4" name="MASK[12]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+52" size="4" name="MASK[13]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+56" size="4" name="MASK[14]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+60" size="4" name="MASK[15]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+64" size="4" name="MASK[16]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+68" size="4" name="MASK[17]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+72" size="4" name="MASK[18]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+76" size="4" name="MASK[19]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+80" size="4" name="MASK[20]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+84" size="4" name="MASK[21]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+88" size="4" name="MASK[22]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+92" size="4" name="MASK[23]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+96" size="4" name="MASK[24]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+100" size="4" name="MASK[25]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+104" size="4" name="MASK[26]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+108" size="4" name="MASK[27]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+112" size="4" name="MASK[28]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+116" size="4" name="MASK[29]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+120" size="4" name="MASK[30]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+124" size="4" name="MASK[31]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+128" size="4" name="MASK[32]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+132" size="4" name="MASK[33]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+136" size="4" name="MASK[34]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+140" size="4" name="MASK[35]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+144" size="4" name="MASK[36]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+148" size="4" name="MASK[37]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+152" size="4" name="MASK[38]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+156" size="4" name="MASK[39]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+160" size="4" name="MASK[40]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+164" size="4" name="MASK[41]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+168" size="4" name="MASK[42]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+172" size="4" name="MASK[43]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+176" size="4" name="MASK[44]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+180" size="4" name="MASK[45]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+184" size="4" name="MASK[46]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+188" size="4" name="MASK[47]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+192" size="4" name="MASK[48]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+196" size="4" name="MASK[49]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+200" size="4" name="MASK[50]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+204" size="4" name="MASK[51]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+208" size="4" name="MASK[52]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+212" size="4" name="MASK[53]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+216" size="4" name="MASK[54]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+220" size="4" name="MASK[55]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+224" size="4" name="MASK[56]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+228" size="4" name="MASK[57]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+232" size="4" name="MASK[58]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+236" size="4" name="MASK[59]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+240" size="4" name="MASK[60]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+244" size="4" name="MASK[61]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+248" size="4" name="MASK[62]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+252" size="4" name="MASK[63]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+256" size="4" name="MASK[64]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+260" size="4" name="MASK[65]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+264" size="4" name="MASK[66]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+268" size="4" name="MASK[67]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+272" size="4" name="MASK[68]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+276" size="4" name="MASK[69]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+280" size="4" name="MASK[70]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+284" size="4" name="MASK[71]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+288" size="4" name="MASK[72]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+292" size="4" name="MASK[73]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+296" size="4" name="MASK[74]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+300" size="4" name="MASK[75]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+304" size="4" name="MASK[76]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+308" size="4" name="MASK[77]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+312" size="4" name="MASK[78]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+316" size="4" name="MASK[79]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+320" size="4" name="MASK[80]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+324" size="4" name="MASK[81]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+328" size="4" name="MASK[82]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+332" size="4" name="MASK[83]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+336" size="4" name="MASK[84]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+340" size="4" name="MASK[85]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+344" size="4" name="MASK[86]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+348" size="4" name="MASK[87]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+352" size="4" name="MASK[88]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+356" size="4" name="MASK[89]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+360" size="4" name="MASK[90]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+364" size="4" name="MASK[91]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+368" size="4" name="MASK[92]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+372" size="4" name="MASK[93]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+376" size="4" name="MASK[94]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+380" size="4" name="MASK[95]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+384" size="4" name="MASK[96]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+388" size="4" name="MASK[97]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+392" size="4" name="MASK[98]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+396" size="4" name="MASK[99]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+400" size="4" name="MASK[100]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+404" size="4" name="MASK[101]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+408" size="4" name="MASK[102]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+412" size="4" name="MASK[103]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+416" size="4" name="MASK[104]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+420" size="4" name="MASK[105]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+424" size="4" name="MASK[106]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+428" size="4" name="MASK[107]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+432" size="4" name="MASK[108]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+436" size="4" name="MASK[109]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+440" size="4" name="MASK[110]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+444" size="4" name="MASK[111]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+448" size="4" name="MASK[112]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+452" size="4" name="MASK[113]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+456" size="4" name="MASK[114]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+460" size="4" name="MASK[115]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+464" size="4" name="MASK[116]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+468" size="4" name="MASK[117]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+472" size="4" name="MASK[118]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+476" size="4" name="MASK[119]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+480" size="4" name="MASK[120]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+484" size="4" name="MASK[121]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+488" size="4" name="MASK[122]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+492" size="4" name="MASK[123]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+496" size="4" name="MASK[124]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+500" size="4" name="MASK[125]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+504" size="4" name="MASK[126]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+508" size="4" name="MASK[127]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+512" size="4" name="MASK[128]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+516" size="4" name="MASK[129]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+520" size="4" name="MASK[130]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+524" size="4" name="MASK[131]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+528" size="4" name="MASK[132]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+532" size="4" name="MASK[133]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+536" size="4" name="MASK[134]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+540" size="4" name="MASK[135]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+544" size="4" name="MASK[136]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+548" size="4" name="MASK[137]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+552" size="4" name="MASK[138]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+556" size="4" name="MASK[139]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+560" size="4" name="MASK[140]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+564" size="4" name="MASK[141]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+568" size="4" name="MASK[142]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+572" size="4" name="MASK[143]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+576" size="4" name="MASK[144]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+580" size="4" name="MASK[145]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+584" size="4" name="MASK[146]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+588" size="4" name="MASK[147]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+592" size="4" name="MASK[148]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+596" size="4" name="MASK[149]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+600" size="4" name="MASK[150]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+604" size="4" name="MASK[151]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+608" size="4" name="MASK[152]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+612" size="4" name="MASK[153]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+616" size="4" name="MASK[154]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+620" size="4" name="MASK[155]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+624" size="4" name="MASK[156]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+628" size="4" name="MASK[157]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+632" size="4" name="MASK[158]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+636" size="4" name="MASK[159]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+640" size="4" name="MASK[160]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+644" size="4" name="MASK[161]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+648" size="4" name="MASK[162]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+652" size="4" name="MASK[163]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+656" size="4" name="MASK[164]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+660" size="4" name="MASK[165]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+664" size="4" name="MASK[166]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+668" size="4" name="MASK[167]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+672" size="4" name="MASK[168]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+676" size="4" name="MASK[169]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+680" size="4" name="MASK[170]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+684" size="4" name="MASK[171]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+688" size="4" name="MASK[172]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+692" size="4" name="MASK[173]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+696" size="4" name="MASK[174]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+700" size="4" name="MASK[175]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+704" size="4" name="MASK[176]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+708" size="4" name="MASK[177]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+712" size="4" name="MASK[178]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+716" size="4" name="MASK[179]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+720" size="4" name="MASK[180]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+724" size="4" name="MASK[181]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+728" size="4" name="MASK[182]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+732" size="4" name="MASK[183]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+736" size="4" name="MASK[184]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+740" size="4" name="MASK[185]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+744" size="4" name="MASK[186]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+748" size="4" name="MASK[187]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+752" size="4" name="MASK[188]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+756" size="4" name="MASK[189]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+760" size="4" name="MASK[190]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+764" size="4" name="MASK[191]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+768" size="4" name="MASK[192]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+772" size="4" name="MASK[193]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+776" size="4" name="MASK[194]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+780" size="4" name="MASK[195]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+784" size="4" name="MASK[196]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+788" size="4" name="MASK[197]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+792" size="4" name="MASK[198]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+796" size="4" name="MASK[199]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+800" size="4" name="MASK[200]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+804" size="4" name="MASK[201]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+808" size="4" name="MASK[202]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+812" size="4" name="MASK[203]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+816" size="4" name="MASK[204]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+820" size="4" name="MASK[205]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+824" size="4" name="MASK[206]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+828" size="4" name="MASK[207]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+832" size="4" name="MASK[208]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+836" size="4" name="MASK[209]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+840" size="4" name="MASK[210]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+844" size="4" name="MASK[211]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+848" size="4" name="MASK[212]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+852" size="4" name="MASK[213]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+856" size="4" name="MASK[214]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+860" size="4" name="MASK[215]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+864" size="4" name="MASK[216]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+868" size="4" name="MASK[217]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+872" size="4" name="MASK[218]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+876" size="4" name="MASK[219]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+880" size="4" name="MASK[220]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+884" size="4" name="MASK[221]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+888" size="4" name="MASK[222]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+892" size="4" name="MASK[223]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+896" size="4" name="MASK[224]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+900" size="4" name="MASK[225]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+904" size="4" name="MASK[226]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+908" size="4" name="MASK[227]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+912" size="4" name="MASK[228]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+916" size="4" name="MASK[229]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+920" size="4" name="MASK[230]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+924" size="4" name="MASK[231]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+928" size="4" name="MASK[232]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+932" size="4" name="MASK[233]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+936" size="4" name="MASK[234]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+940" size="4" name="MASK[235]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+944" size="4" name="MASK[236]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+948" size="4" name="MASK[237]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+952" size="4" name="MASK[238]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+956" size="4" name="MASK[239]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+960" size="4" name="MASK[240]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+964" size="4" name="MASK[241]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+968" size="4" name="MASK[242]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+972" size="4" name="MASK[243]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+976" size="4" name="MASK[244]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+980" size="4" name="MASK[245]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+984" size="4" name="MASK[246]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+988" size="4" name="MASK[247]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+992" size="4" name="MASK[248]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+996" size="4" name="MASK[249]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1000" size="4" name="MASK[250]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1004" size="4" name="MASK[251]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1008" size="4" name="MASK[252]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1012" size="4" name="MASK[253]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1016" size="4" name="MASK[254]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1020" size="4" name="MASK[255]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1024" size="4" name="MASK[256]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1028" size="4" name="MASK[257]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1032" size="4" name="MASK[258]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1036" size="4" name="MASK[259]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1040" size="4" name="MASK[260]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1044" size="4" name="MASK[261]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1048" size="4" name="MASK[262]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1052" size="4" name="MASK[263]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1056" size="4" name="MASK[264]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1060" size="4" name="MASK[265]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1064" size="4" name="MASK[266]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1068" size="4" name="MASK[267]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1072" size="4" name="MASK[268]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1076" size="4" name="MASK[269]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1080" size="4" name="MASK[270]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1084" size="4" name="MASK[271]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1088" size="4" name="MASK[272]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1092" size="4" name="MASK[273]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1096" size="4" name="MASK[274]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1100" size="4" name="MASK[275]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1104" size="4" name="MASK[276]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1108" size="4" name="MASK[277]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1112" size="4" name="MASK[278]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1116" size="4" name="MASK[279]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1120" size="4" name="MASK[280]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1124" size="4" name="MASK[281]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1128" size="4" name="MASK[282]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1132" size="4" name="MASK[283]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1136" size="4" name="MASK[284]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1140" size="4" name="MASK[285]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1144" size="4" name="MASK[286]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1148" size="4" name="MASK[287]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1152" size="4" name="MASK[288]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1156" size="4" name="MASK[289]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1160" size="4" name="MASK[290]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1164" size="4" name="MASK[291]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1168" size="4" name="MASK[292]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1172" size="4" name="MASK[293]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1176" size="4" name="MASK[294]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1180" size="4" name="MASK[295]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1184" size="4" name="MASK[296]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1188" size="4" name="MASK[297]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1192" size="4" name="MASK[298]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1196" size="4" name="MASK[299]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1200" size="4" name="MASK[300]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1204" size="4" name="MASK[301]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1208" size="4" name="MASK[302]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1212" size="4" name="MASK[303]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1216" size="4" name="MASK[304]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1220" size="4" name="MASK[305]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1224" size="4" name="MASK[306]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1228" size="4" name="MASK[307]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1232" size="4" name="MASK[308]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1236" size="4" name="MASK[309]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1240" size="4" name="MASK[310]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1244" size="4" name="MASK[311]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1248" size="4" name="MASK[312]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1252" size="4" name="MASK[313]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1256" size="4" name="MASK[314]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1260" size="4" name="MASK[315]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1264" size="4" name="MASK[316]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1268" size="4" name="MASK[317]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1272" size="4" name="MASK[318]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1276" size="4" name="MASK[319]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1280" size="4" name="MASK[320]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1284" size="4" name="MASK[321]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1288" size="4" name="MASK[322]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1292" size="4" name="MASK[323]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1296" size="4" name="MASK[324]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1300" size="4" name="MASK[325]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1304" size="4" name="MASK[326]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1308" size="4" name="MASK[327]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1312" size="4" name="MASK[328]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1316" size="4" name="MASK[329]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1320" size="4" name="MASK[330]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1324" size="4" name="MASK[331]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1328" size="4" name="MASK[332]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1332" size="4" name="MASK[333]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1336" size="4" name="MASK[334]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1340" size="4" name="MASK[335]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1344" size="4" name="MASK[336]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1348" size="4" name="MASK[337]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1352" size="4" name="MASK[338]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1356" size="4" name="MASK[339]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1360" size="4" name="MASK[340]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1364" size="4" name="MASK[341]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1368" size="4" name="MASK[342]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1372" size="4" name="MASK[343]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1376" size="4" name="MASK[344]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1380" size="4" name="MASK[345]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1384" size="4" name="MASK[346]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1388" size="4" name="MASK[347]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1392" size="4" name="MASK[348]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1396" size="4" name="MASK[349]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1400" size="4" name="MASK[350]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1404" size="4" name="MASK[351]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1408" size="4" name="MASK[352]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1412" size="4" name="MASK[353]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1416" size="4" name="MASK[354]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1420" size="4" name="MASK[355]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1424" size="4" name="MASK[356]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1428" size="4" name="MASK[357]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1432" size="4" name="MASK[358]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1436" size="4" name="MASK[359]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1440" size="4" name="MASK[360]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1444" size="4" name="MASK[361]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1448" size="4" name="MASK[362]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1452" size="4" name="MASK[363]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1456" size="4" name="MASK[364]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1460" size="4" name="MASK[365]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1464" size="4" name="MASK[366]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1468" size="4" name="MASK[367]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1472" size="4" name="MASK[368]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1476" size="4" name="MASK[369]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1480" size="4" name="MASK[370]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1484" size="4" name="MASK[371]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1488" size="4" name="MASK[372]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1492" size="4" name="MASK[373]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1496" size="4" name="MASK[374]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1500" size="4" name="MASK[375]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1504" size="4" name="MASK[376]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1508" size="4" name="MASK[377]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1512" size="4" name="MASK[378]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1516" size="4" name="MASK[379]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1520" size="4" name="MASK[380]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1524" size="4" name="MASK[381]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1528" size="4" name="MASK[382]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1532" size="4" name="MASK[383]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1536" size="4" name="MASK[384]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1540" size="4" name="MASK[385]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1544" size="4" name="MASK[386]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1548" size="4" name="MASK[387]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1552" size="4" name="MASK[388]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1556" size="4" name="MASK[389]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1560" size="4" name="MASK[390]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1564" size="4" name="MASK[391]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1568" size="4" name="MASK[392]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1572" size="4" name="MASK[393]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1576" size="4" name="MASK[394]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1580" size="4" name="MASK[395]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1584" size="4" name="MASK[396]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1588" size="4" name="MASK[397]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1592" size="4" name="MASK[398]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1596" size="4" name="MASK[399]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1600" size="4" name="MASK[400]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1604" size="4" name="MASK[401]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1608" size="4" name="MASK[402]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1612" size="4" name="MASK[403]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1616" size="4" name="MASK[404]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1620" size="4" name="MASK[405]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1624" size="4" name="MASK[406]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1628" size="4" name="MASK[407]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1632" size="4" name="MASK[408]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1636" size="4" name="MASK[409]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1640" size="4" name="MASK[410]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1644" size="4" name="MASK[411]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1648" size="4" name="MASK[412]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1652" size="4" name="MASK[413]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1656" size="4" name="MASK[414]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1660" size="4" name="MASK[415]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1664" size="4" name="MASK[416]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1668" size="4" name="MASK[417]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1672" size="4" name="MASK[418]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1676" size="4" name="MASK[419]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1680" size="4" name="MASK[420]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1684" size="4" name="MASK[421]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1688" size="4" name="MASK[422]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1692" size="4" name="MASK[423]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1696" size="4" name="MASK[424]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1700" size="4" name="MASK[425]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1704" size="4" name="MASK[426]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1708" size="4" name="MASK[427]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1712" size="4" name="MASK[428]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1716" size="4" name="MASK[429]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1720" size="4" name="MASK[430]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1724" size="4" name="MASK[431]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1728" size="4" name="MASK[432]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1732" size="4" name="MASK[433]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1736" size="4" name="MASK[434]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1740" size="4" name="MASK[435]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1744" size="4" name="MASK[436]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1748" size="4" name="MASK[437]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1752" size="4" name="MASK[438]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1756" size="4" name="MASK[439]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1760" size="4" name="MASK[440]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1764" size="4" name="MASK[441]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1768" size="4" name="MASK[442]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1772" size="4" name="MASK[443]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1776" size="4" name="MASK[444]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1780" size="4" name="MASK[445]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1784" size="4" name="MASK[446]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1788" size="4" name="MASK[447]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1792" size="4" name="MASK[448]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1796" size="4" name="MASK[449]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1800" size="4" name="MASK[450]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1804" size="4" name="MASK[451]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1808" size="4" name="MASK[452]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1812" size="4" name="MASK[453]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1816" size="4" name="MASK[454]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1820" size="4" name="MASK[455]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1824" size="4" name="MASK[456]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1828" size="4" name="MASK[457]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1832" size="4" name="MASK[458]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1836" size="4" name="MASK[459]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1840" size="4" name="MASK[460]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1844" size="4" name="MASK[461]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1848" size="4" name="MASK[462]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1852" size="4" name="MASK[463]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1856" size="4" name="MASK[464]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1860" size="4" name="MASK[465]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1864" size="4" name="MASK[466]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1868" size="4" name="MASK[467]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1872" size="4" name="MASK[468]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1876" size="4" name="MASK[469]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1880" size="4" name="MASK[470]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1884" size="4" name="MASK[471]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1888" size="4" name="MASK[472]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1892" size="4" name="MASK[473]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1896" size="4" name="MASK[474]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1900" size="4" name="MASK[475]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1904" size="4" name="MASK[476]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1908" size="4" name="MASK[477]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1912" size="4" name="MASK[478]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1916" size="4" name="MASK[479]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1920" size="4" name="MASK[480]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1924" size="4" name="MASK[481]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1928" size="4" name="MASK[482]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1932" size="4" name="MASK[483]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1936" size="4" name="MASK[484]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1940" size="4" name="MASK[485]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1944" size="4" name="MASK[486]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1948" size="4" name="MASK[487]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1952" size="4" name="MASK[488]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1956" size="4" name="MASK[489]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1960" size="4" name="MASK[490]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1964" size="4" name="MASK[491]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1968" size="4" name="MASK[492]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1972" size="4" name="MASK[493]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1976" size="4" name="MASK[494]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1980" size="4" name="MASK[495]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1984" size="4" name="MASK[496]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1988" size="4" name="MASK[497]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1992" size="4" name="MASK[498]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+1996" size="4" name="MASK[499]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+2000" size="4" name="MASK[500]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+2004" size="4" name="MASK[501]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+2008" size="4" name="MASK[502]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+2012" size="4" name="MASK[503]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+2016" size="4" name="MASK[504]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+2020" size="4" name="MASK[505]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+2024" size="4" name="MASK[506]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+2028" size="4" name="MASK[507]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+2032" size="4" name="MASK[508]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+2036" size="4" name="MASK[509]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+2040" size="4" name="MASK[510]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + <Register start="+0x000+2044" size="4" name="MASK[511]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" /> + </Register> + </RegisterGroup> + <RegisterGroup name="CANAF" start="0x4003C000" description=" CAN controller acceptance filter "> + <Register start="+0x000" size="4" name="AFMR" access="Read/Write" description="Acceptance Filter Register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="ACCOFF" description="if AccBP is 0, the Acceptance Filter is not operational. All Rx messages on all CAN buses are ignored." /> + <BitField start="1" size="1" name="ACCBP" description="All Rx messages are accepted on enabled CAN controllers. Software must set this bit before modifying the contents of any of the registers described below, and before modifying the contents of Lookup Table RAM in any way other than setting or clearing Disable bits in Standard Identifier entries. When both this bit and AccOff are 0, the Acceptance filter operates to screen received CAN Identifiers." /> + <BitField start="2" size="1" name="EFCAN" description="FullCAN mode"> + <Enum name="SOFTWARE_MUST_READ_A" start="0" description="Software must read all messages for all enabled IDs on all enabled CAN buses, from the receiving CAN controllers." /> + <Enum name="THE_ACCEPTANCE_FILTE" start="1" description="The Acceptance Filter itself will take care of receiving and storing messages for selected Standard ID values on selected CAN buses. See Section 21.16 FullCAN mode on page 576." /> + </BitField> + <BitField start="3" size="29" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x004" size="4" name="SFF_SA" access="Read/Write" description="Standard Frame Individual Start Address Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="2" size="9" name="SFF_SA" description="The start address of the table of individual Standard Identifiers in AF Lookup RAM. If the table is empty, write the same value in this register and the SFF_GRP_sa register described below. For compatibility with possible future devices, write zeroes in bits 31:11 and 1:0 of this register. If the eFCAN bit in the AFMR is 1, this value also indicates the size of the table of Standard IDs which the Acceptance Filter will search and (if found) automatically store received messages in Acceptance Filter RAM." /> + <BitField start="11" size="21" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x008" size="4" name="SFF_GRP_SA" access="Read/Write" description="Standard Frame Group Start Address Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="2" size="10" name="SFF_GRP_SA" description="The start address of the table of grouped Standard Identifiers in AF Lookup RAM. If the table is empty, write the same value in this register and the EFF_sa register described below. The largest value that should be written to this register is 0x800, when only the Standard Individual table is used, and the last word (address 0x7FC) in AF Lookup Table RAM is used. For compatibility with possible future devices, please write zeroes in bits 31:12 and 1:0 of this register." /> + <BitField start="12" size="20" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x00C" size="4" name="EFF_SA" access="Read/Write" description="Extended Frame Start Address Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="2" size="9" name="EFF_SA" description="The start address of the table of individual Extended Identifiers in AF Lookup RAM. If the table is empty, write the same value in this register and the EFF_GRP_sa register described below. The largest value that should be written to this register is 0x800, when both Extended Tables are empty and the last word (address 0x7FC) in AF Lookup Table RAM is used. For compatibility with possible future devices, please write zeroes in bits 31:11 and 1:0 of this register." /> + <BitField start="11" size="21" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x010" size="4" name="EFF_GRP_SA" access="Read/Write" description="Extended Frame Group Start Address Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="2" size="10" name="EFF_GRP_SA" description="The start address of the table of grouped Extended Identifiers in AF Lookup RAM. If the table is empty, write the same value in this register and the ENDofTable register described below. The largest value that should be written to this register is 0x800, when this table is empty and the last word (address 0x7FC) in AF Lookup Table RAM is used. For compatibility with possible future devices, please write zeroes in bits 31:12 and 1:0 of this register." /> + <BitField start="12" size="20" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x014" size="4" name="ENDOFTABLE" access="Read/Write" description="End of AF Tables register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="2" size="10" name="ENDOFTABLE" description="The address above the last active address in the last active AF table. For compatibility with possible future devices, please write zeroes in bits 31:12 and 1:0 of this register. If the eFCAN bit in the AFMR is 0, the largest value that should be written to this register is 0x800, which allows the last word (address 0x7FC) in AF Lookup Table RAM to be used. If the eFCAN bit in the AFMR is 1, this value marks the start of the area of Acceptance Filter RAM, into which the Acceptance Filter will automatically receive messages for selected IDs on selected CAN buses. In this case, the maximum value that should be written to this register is 0x800 minus 6 times the value in SFF_sa. This allows 12 bytes of message storage between this address and the end of Acceptance Filter RAM, for each Standard ID that is specified between the start of Acceptance Filter RAM, and the next active AF table." /> + <BitField start="12" size="20" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x018" size="4" name="LUTERRAD" access="ReadOnly" description="LUT Error Address register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="2" size="9" name="LUTERRAD" description="It the LUT Error bit (below) is 1, this read-only field contains the address in AF Lookup Table RAM, at which the Acceptance Filter encountered an error in the content of the tables." /> + <BitField start="11" size="21" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x01C" size="4" name="LUTERR" access="ReadOnly" description="LUT Error Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="LUTERR" description="This read-only bit is set to 1 if the Acceptance Filter encounters an error in the content of the tables in AF RAM. It is cleared when software reads the LUTerrAd register. This condition is ORed with the other CAN interrupts from the CAN controllers, to produce the request that is connected to the NVIC." /> + <BitField start="1" size="31" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x020" size="4" name="FCANIE" access="Read/Write" description="FullCAN interrupt enable register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="FCANIE" description="Global FullCAN Interrupt Enable. When 1, this interrupt is enabled." /> + <BitField start="1" size="31" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x024" size="4" name="FCANIC0" access="Read/Write" description="FullCAN interrupt and capture register0" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="INTPND" description="FullCan Interrupt Pending 0 = FullCan Interrupt Pending bit 0. 1 = FullCan Interrupt Pending bit 1. ... 31 = FullCan Interrupt Pending bit 31." /> + </Register> + <Register start="+0x028" size="4" name="FCANIC1" access="Read/Write" description="FullCAN interrupt and capture register1" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="IntPnd32" description="FullCan Interrupt Pending bit 32. 0 = FullCan Interrupt Pending bit 32. 1 = FullCan Interrupt Pending bit 33. ... 31 = FullCan Interrupt Pending bit 63." /> + </Register> + </RegisterGroup> + <RegisterGroup name="CCAN" start="0x40040000" description="Central CAN controller "> + <Register start="+0x000" size="4" name="TXSR" access="ReadOnly" description="CAN Central Transmit Status Register" reset_value="0x00030300" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="TS1" description="When 1, the CAN controller 1 is sending a message (same as TS in the CAN1GSR)." /> + <BitField start="1" size="1" name="TS2" description="When 1, the CAN controller 2 is sending a message (same as TS in the CAN2GSR)" /> + <BitField start="2" size="6" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." /> + <BitField start="8" size="1" name="TBS1" description="When 1, all 3 Tx Buffers of the CAN1 controller are available to the CPU (same as TBS in CAN1GSR)." /> + <BitField start="9" size="1" name="TBS2" description="When 1, all 3 Tx Buffers of the CAN2 controller are available to the CPU (same as TBS in CAN2GSR)." /> + <BitField start="10" size="6" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." /> + <BitField start="16" size="1" name="TCS1" description="When 1, all requested transmissions have been completed successfully by the CAN1 controller (same as TCS in CAN1GSR)." /> + <BitField start="17" size="1" name="TCS2" description="When 1, all requested transmissions have been completed successfully by the CAN2 controller (same as TCS in CAN2GSR)." /> + <BitField start="18" size="14" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x004" size="4" name="RXSR" access="ReadOnly" description="CAN Central Receive Status Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RS1" description="When 1, CAN1 is receiving a message (same as RS in CAN1GSR)." /> + <BitField start="1" size="1" name="RS2" description="When 1, CAN2 is receiving a message (same as RS in CAN2GSR)." /> + <BitField start="2" size="6" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." /> + <BitField start="8" size="1" name="RB1" description="When 1, a received message is available in the CAN1 controller (same as RBS in CAN1GSR)." /> + <BitField start="9" size="1" name="RB2" description="When 1, a received message is available in the CAN2 controller (same as RBS in CAN2GSR)." /> + <BitField start="10" size="6" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." /> + <BitField start="16" size="1" name="DOS1" description="When 1, a message was lost because the preceding message to CAN1 controller was not read out quickly enough (same as DOS in CAN1GSR)." /> + <BitField start="17" size="1" name="DOS2" description="When 1, a message was lost because the preceding message to CAN2 controller was not read out quickly enough (same as DOS in CAN2GSR)." /> + <BitField start="18" size="14" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x008" size="4" name="MSR" access="ReadOnly" description="CAN Central Miscellaneous Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="E1" description="When 1, one or both of the CAN1 Tx and Rx Error Counters has reached the limit set in the CAN1EWL register (same as ES in CAN1GSR)" /> + <BitField start="1" size="1" name="E2" description="When 1, one or both of the CAN2 Tx and Rx Error Counters has reached the limit set in the CAN2EWL register (same as ES in CAN2GSR)" /> + <BitField start="2" size="6" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." /> + <BitField start="8" size="1" name="BS1" description="When 1, the CAN1 controller is currently involved in bus activities (same as BS in CAN1GSR)." /> + <BitField start="9" size="1" name="BS2" description="When 1, the CAN2 controller is currently involved in bus activities (same as BS in CAN2GSR)." /> + <BitField start="10" size="22" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." /> + </Register> + </RegisterGroup> + <RegisterGroup name="CAN1" start="0x40044000" description="CAN1 controller "> + <Register start="+0x000" size="4" name="MOD" access="Read/Write" description="Controls the operating mode of the CAN Controller." reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="RM" description="Reset Mode."> + <Enum name="NORMAL_THE_CAN_CONTR" start="0" description="Normal.The CAN Controller is in the Operating Mode, and certain registers can not be written." /> + <Enum name="RESET_CAN_OPERATION" start="1" description="Reset. CAN operation is disabled, writable registers can be written and the current transmission/reception of a message is aborted." /> + </BitField> + <BitField start="1" size="1" name="LOM" description="Listen Only Mode."> + <Enum name="NORMAL_THE_CAN_CONT" start="0" description="Normal. The CAN controller acknowledges a successfully received message on the CAN bus. The error counters are stopped at the current value." /> + <Enum name="LISTEN_ONLY_THE_CON" start="1" description="Listen only. The controller gives no acknowledgment, even if a message is successfully received. Messages cannot be sent, and the controller operates in error passive mode. This mode is intended for software bit rate detection and hot plugging." /> + </BitField> + <BitField start="2" size="1" name="STM" description="Self Test Mode."> + <Enum name="NORMAL_A_TRANSMITTE" start="0" description="Normal. A transmitted message must be acknowledged to be considered successful." /> + <Enum name="SELF_TEST_THE_CONTR" start="1" description="Self test. The controller will consider a Tx message successful even if there is no acknowledgment received. In this mode a full node test is possible without any other active node on the bus using the SRR bit in CANxCMR." /> + </BitField> + <BitField start="3" size="1" name="TPM" description="Transmit Priority Mode."> + <Enum name="CAN_ID_THE_TRANSMIT" start="0" description="CAN ID. The transmit priority for 3 Transmit Buffers depends on the CAN Identifier." /> + <Enum name="LOCAL_PRIORITY_THE_" start="1" description="Local priority. The transmit priority for 3 Transmit Buffers depends on the contents of the Tx Priority register within the Transmit Buffer." /> + </BitField> + <BitField start="4" size="1" name="SM" description="Sleep Mode."> + <Enum name="WAKE_UP_NORMAL_OPER" start="0" description="Wake-up. Normal operation." /> + <Enum name="SLEEP_THE_CAN_CONTR" start="1" description="Sleep. The CAN controller enters Sleep Mode if no CAN interrupt is pending and there is no bus activity. See the Sleep Mode description Section 21.8.2 on page 565." /> + </BitField> + <BitField start="5" size="1" name="RPM" description="Receive Polarity Mode."> + <Enum name="LOW_ACTIVE_RD_INPUT" start="0" description="Low active. RD input is active Low (dominant bit = 0)." /> + <Enum name="HIGH_ACTIVE_RD_INPU" start="1" description="High active. RD input is active High (dominant bit = 1) -- reverse polarity." /> + </BitField> + <BitField start="6" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="7" size="1" name="TM" description="Test Mode."> + <Enum name="DISABLED_NORMAL_OPE" start="0" description="Disabled. Normal operation." /> + <Enum name="ENABLED_THE_TD_PIN_" start="1" description="Enabled. The TD pin will reflect the bit, detected on RD pin, with the next positive edge of the system clock." /> + </BitField> + <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x004" size="4" name="CMR" access="WriteOnly" description="Command bits that affect the state of the CAN Controller" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="TR" description="Transmission Request."> + <Enum name="ABSENT_NO_TRANSMISSI" start="0" description="Absent.No transmission request." /> + <Enum name="PRESENT_THE_MESSAGE" start="1" description="Present. The message, previously written to the CANxTFI, CANxTID, and optionally the CANxTDA and CANxTDB registers, is queued for transmission from the selected Transmit Buffer. If at two or all three of STB1, STB2 and STB3 bits are selected when TR=1 is written, Transmit Buffer will be selected based on the chosen priority scheme (for details see Section 21.5.3 Transmit Buffers (TXB))" /> + </BitField> + <BitField start="1" size="1" name="AT" description="Abort Transmission."> + <Enum name="NO_ACTION_DO_NOT_AB" start="0" description="No action. Do not abort the transmission." /> + <Enum name="PRESENT_IF_NOT_ALRE" start="1" description="Present. if not already in progress, a pending Transmission Request for the selected Transmit Buffer is cancelled." /> + </BitField> + <BitField start="2" size="1" name="RRB" description="Release Receive Buffer."> + <Enum name="NO_ACTION_DO_NOT_RE" start="0" description="No action. Do not release the receive buffer." /> + <Enum name="RELEASED_THE_INFORM" start="1" description="Released. The information in the Receive Buffer (consisting of CANxRFS, CANxRID, and if applicable the CANxRDA and CANxRDB registers) is released, and becomes eligible for replacement by the next received frame. If the next received frame is not available, writing this command clears the RBS bit in the Status Register(s)." /> + </BitField> + <BitField start="3" size="1" name="CDO" description="Clear Data Overrun."> + <Enum name="NO_ACTION_DO_NOT_CL" start="0" description="No action. Do not clear the data overrun bit." /> + <Enum name="CLEAR_THE_DATA_OVER" start="1" description="Clear. The Data Overrun bit in Status Register(s) is cleared." /> + </BitField> + <BitField start="4" size="1" name="SRR" description="Self Reception Request."> + <Enum name="ABSENT_NO_SELF_RECE" start="0" description="Absent. No self reception request." /> + <Enum name="PRESENT_THE_MESSAGE" start="1" description="Present. The message, previously written to the CANxTFS, CANxTID, and optionally the CANxTDA and CANxTDB registers, is queued for transmission from the selected Transmit Buffer and received simultaneously. This differs from the TR bit above in that the receiver is not disabled during the transmission, so that it receives the message if its Identifier is recognized by the Acceptance Filter." /> + </BitField> + <BitField start="5" size="1" name="STB1" description="Select Tx Buffer 1."> + <Enum name="NOT_SELECTED_TX_BUF" start="0" description="Not selected. Tx Buffer 1 is not selected for transmission." /> + <Enum name="SELECTED_TX_BUFFER_" start="1" description="Selected. Tx Buffer 1 is selected for transmission." /> + </BitField> + <BitField start="6" size="1" name="STB2" description="Select Tx Buffer 2."> + <Enum name="NOT_SELECTED_TX_BUF" start="0" description="Not selected. Tx Buffer 2 is not selected for transmission." /> + <Enum name="SELECTED_TX_BUFFER_" start="1" description="Selected. Tx Buffer 2 is selected for transmission." /> + </BitField> + <BitField start="7" size="1" name="STB3" description="Select Tx Buffer 3."> + <Enum name="NOT_SELECTED_TX_BUF" start="0" description="Not selected. Tx Buffer 3 is not selected for transmission." /> + <Enum name="SELECTED_TX_BUFFER_" start="1" description="Selected. Tx Buffer 3 is selected for transmission." /> + </BitField> + <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x008" size="4" name="GSR" access="ReadOnly" description="Global Controller Status and Error Counters. The error counters can only be written when RM in CANMOD is 1." reset_value="0x3C" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RBS" description="Receive Buffer Status. After reading all messages and releasing their memory space with the command 'Release Receive Buffer,' this bit is cleared."> + <Enum name="EMPTY_NO_MESSAGE_IS" start="0" description="Empty. No message is available." /> + <Enum name="FULL_AT_LEAST_ONE_C" start="1" description="Full. At least one complete message is received by the Double Receive Buffer and available in the CANxRFS, CANxRID, and if applicable the CANxRDA and CANxRDB registers. This bit is cleared by the Release Receive Buffer command in CANxCMR, if no subsequent received message is available." /> + </BitField> + <BitField start="1" size="1" name="DOS" description="Data Overrun Status. If there is not enough space to store the message within the Receive Buffer, that message is dropped and the Data Overrun condition is signalled to the CPU in the moment this message becomes valid. If this message is not completed successfully (e.g. because of an error), no overrun condition is signalled."> + <Enum name="ABSENT_NO_DATA_OVER" start="0" description="Absent. No data overrun has occurred since the last Clear Data Overrun command was given/written to CANxCMR (or since Reset)." /> + <Enum name="OVERRUN_A_MESSAGE_W" start="1" description="Overrun. A message was lost because the preceding message to this CAN controller was not read and released quickly enough (there was not enough space for a new message in the Double Receive Buffer)." /> + </BitField> + <BitField start="2" size="1" name="TBS" description="Transmit Buffer Status."> + <Enum name="LOCKED_AT_LEAST_ONE" start="0" description="Locked. At least one of the Transmit Buffers is not available for the CPU, i.e. at least one previously queued message for this CAN controller has not yet been sent, and therefore software should not write to the CANxTFI, CANxTID, CANxTDA, nor CANxTDB registers of that (those) Tx buffer(s)." /> + <Enum name="RELEASED_ALL_THREE_" start="1" description="Released. All three Transmit Buffers are available for the CPU. No transmit message is pending for this CAN controller (in any of the 3 Tx buffers), and software may write to any of the CANxTFI, CANxTID, CANxTDA, and CANxTDB registers." /> + </BitField> + <BitField start="3" size="1" name="TCS" description="Transmit Complete Status. The Transmission Complete Status bit is set '0' (incomplete) whenever the Transmission Request bit or the Self Reception Request bit is set '1' at least for one of the three Transmit Buffers. The Transmission Complete Status bit will remain '0' until all messages are transmitted successfully."> + <Enum name="INCOMPLETE_AT_LEAST" start="0" description="Incomplete. At least one requested transmission has not been successfully completed yet." /> + <Enum name="COMPLETE_ALL_REQUES" start="1" description="Complete. All requested transmission(s) has (have) been successfully completed." /> + </BitField> + <BitField start="4" size="1" name="RS" description="Receive Status. If both the Receive Status and the Transmit Status bits are '0' (idle), the CAN-Bus is idle. If both bits are set, the controller is waiting to become idle again. After hardware reset 11 consecutive recessive bits have to be detected until idle status is reached. After Bus-off this will take 128 times of 11 consecutive recessive bits."> + <Enum name="IDLE_THE_CAN_CONTRO" start="0" description="Idle. The CAN controller is idle." /> + <Enum name="RECEIVE_THE_CAN_CON" start="1" description="Receive. The CAN controller is receiving a message." /> + </BitField> + <BitField start="5" size="1" name="TS" description="Transmit Status. If both the Receive Status and the Transmit Status bits are '0' (idle), the CAN-Bus is idle. If both bits are set, the controller is waiting to become idle again. After hardware reset 11 consecutive recessive bits have to be detected until idle status is reached. After Bus-off this will take 128 times of 11 consecutive recessive bits."> + <Enum name="IDLE_THE_CAN_CONTRO" start="0" description="Idle. The CAN controller is idle." /> + <Enum name="TRANSMIT_THE_CAN_CO" start="1" description="Transmit. The CAN controller is sending a message." /> + </BitField> + <BitField start="6" size="1" name="ES" description="Error Status. Errors detected during reception or transmission will effect the error counters according to the CAN specification. The Error Status bit is set when at least one of the error counters has reached or exceeded the Error Warning Limit. An Error Warning Interrupt is generated, if enabled. The default value of the Error Warning Limit after hardware reset is 96 decimal, see also Section 21.7.7 CAN Error Warning Limit register (CAN1EWL - 0x4004 4018, CAN2EWL - 0x4004 8018)."> + <Enum name="OK_BOTH_ERROR_COUNT" start="0" description="OK. Both error counters are below the Error Warning Limit." /> + <Enum name="ERROR_ONE_OR_BOTH_O" start="1" description="Error. One or both of the Transmit and Receive Error Counters has reached the limit set in the Error Warning Limit register." /> + </BitField> + <BitField start="7" size="1" name="BS" description="Bus Status. Mode bit '1' (present) and an Error Warning Interrupt is generated, if enabled. Afterwards the Transmit Error Counter is set to '127', and the Receive Error Counter is cleared. It will stay in this mode until the CPU clears the Reset Mode bit. Once this is completed the CAN Controller will wait the minimum protocol-defined time (128 occurrences of the Bus-Free signal) counting down the Transmit Error Counter. After that, the Bus Status bit is cleared (Bus-On), the Error Status bit is set '0' (ok), the Error Counters are reset, and an Error Warning Interrupt is generated, if enabled. Reading the TX Error Counter during this time gives information about the status of the Bus-Off recovery."> + <Enum name="BUS_ON_THE_CAN_CONT" start="0" description="Bus-on. The CAN Controller is involved in bus activities" /> + <Enum name="BUS_OFF_THE_CAN_CON" start="1" description="Bus-off. The CAN controller is currently not involved/prohibited from bus activity because the Transmit Error Counter reached its limiting value of 255." /> + </BitField> + <BitField start="8" size="8" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="16" size="8" name="RXERR" description="The current value of the Rx Error Counter (an 8-bit value)." /> + <BitField start="24" size="8" name="TXERR" description="The current value of the Tx Error Counter (an 8-bit value)." /> + </Register> + <Register start="+0x00C" size="4" name="ICR" access="ReadOnly" description="Interrupt status, Arbitration Lost Capture, Error Code Capture" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RI" description="Receive Interrupt. This bit is set whenever the RBS bit in CANxSR and the RIE bit in CANxIER are both 1, indicating that a new message was received and stored in the Receive Buffer. The Receive Interrupt Bit is not cleared upon a read access to the Interrupt Register. Giving the Command Release Receive Buffer will clear RI temporarily. If there is another message available within the Receive Buffer after the release command, RI is set again. Otherwise RI remains cleared."> + <Enum name="RESET" start="0" description="Reset" /> + <Enum name="SET" start="1" description="Set" /> + </BitField> + <BitField start="1" size="1" name="TI1" description="Transmit Interrupt 1. This bit is set when the TBS1 bit in CANxSR goes from 0 to 1 (whenever a message out of TXB1 was successfully transmitted or aborted), indicating that Transmit buffer 1 is available, and the TIE1 bit in CANxIER is 1."> + <Enum name="RESET" start="0" description="Reset" /> + <Enum name="SET" start="1" description="Set" /> + </BitField> + <BitField start="2" size="1" name="EI" description="Error Warning Interrupt. This bit is set on every change (set or clear) of either the Error Status or Bus Status bit in CANxSR and the EIE bit bit is set within the Interrupt Enable Register at the time of the change."> + <Enum name="RESET" start="0" description="Reset" /> + <Enum name="SET" start="1" description="Set" /> + </BitField> + <BitField start="3" size="1" name="DOI" description="Data Overrun Interrupt. This bit is set when the DOS bit in CANxSR goes from 0 to 1 and the DOIE bit in CANxIER is 1."> + <Enum name="RESET" start="0" description="Reset" /> + <Enum name="SET" start="1" description="Set" /> + </BitField> + <BitField start="4" size="1" name="WUI" description="Wake-Up Interrupt. This bit is set if the CAN controller is sleeping and bus activity is detected and the WUIE bit in CANxIER is 1. A Wake-Up Interrupt is also generated if the CPU tries to set the Sleep bit while the CAN controller is involved in bus activities or a CAN Interrupt is pending. The WUI flag can also get asserted when the according enable bit WUIE is not set. In this case a Wake-Up Interrupt does not get asserted."> + <Enum name="RESET" start="0" description="Reset" /> + <Enum name="SET" start="1" description="Set" /> + </BitField> + <BitField start="5" size="1" name="EPI" description="Error Passive Interrupt. This bit is set if the EPIE bit in CANxIER is 1, and the CAN controller switches between Error Passive and Error Active mode in either direction. This is the case when the CAN Controller has reached the Error Passive Status (at least one error counter exceeds the CAN protocol defined level of 127) or if the CAN Controller is in Error Passive Status and enters the Error Active Status again."> + <Enum name="RESET" start="0" description="Reset" /> + <Enum name="SET" start="1" description="Set" /> + </BitField> + <BitField start="6" size="1" name="ALI" description="Arbitration Lost Interrupt. This bit is set if the ALIE bit in CANxIER is 1, and the CAN controller loses arbitration while attempting to transmit. In this case the CAN node becomes a receiver."> + <Enum name="RESET" start="0" description="Reset" /> + <Enum name="SET" start="1" description="Set" /> + </BitField> + <BitField start="7" size="1" name="BEI" description="Bus Error Interrupt -- this bit is set if the BEIE bit in CANxIER is 1, and the CAN controller detects an error on the bus."> + <Enum name="RESET" start="0" description="Reset" /> + <Enum name="SET" start="1" description="Set" /> + </BitField> + <BitField start="8" size="1" name="IDI" description="ID Ready Interrupt -- this bit is set if the IDIE bit in CANxIER is 1, and a CAN Identifier has been received (a message was successfully transmitted or aborted). This bit is set whenever a message was successfully transmitted or aborted and the IDIE bit is set in the IER register."> + <Enum name="RESET" start="0" description="Reset" /> + <Enum name="SET" start="1" description="Set" /> + </BitField> + <BitField start="9" size="1" name="TI2" description="Transmit Interrupt 2. This bit is set when the TBS2 bit in CANxSR goes from 0 to 1 (whenever a message out of TXB2 was successfully transmitted or aborted), indicating that Transmit buffer 2 is available, and the TIE2 bit in CANxIER is 1."> + <Enum name="RESET" start="0" description="Reset" /> + <Enum name="SET" start="1" description="Set" /> + </BitField> + <BitField start="10" size="1" name="TI3" description="Transmit Interrupt 3. This bit is set when the TBS3 bit in CANxSR goes from 0 to 1 (whenever a message out of TXB3 was successfully transmitted or aborted), indicating that Transmit buffer 3 is available, and the TIE3 bit in CANxIER is 1."> + <Enum name="RESET" start="0" description="Reset" /> + <Enum name="SET" start="1" description="Set" /> + </BitField> + <BitField start="11" size="5" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + <BitField start="16" size="5" name="ERRBIT4_0" description="Error Code Capture: when the CAN controller detects a bus error, the location of the error within the frame is captured in this field. The value reflects an internal state variable, and as a result is not very linear: 00011 = Start of Frame 00010 = ID28 ... ID21 00110 = ID20 ... ID18 00100 = SRTR Bit 00101 = IDE bit 00111 = ID17 ... 13 01111 = ID12 ... ID5 01110 = ID4 ... ID0 01100 = RTR Bit 01101 = Reserved Bit 1 01001 = Reserved Bit 0 01011 = Data Length Code 01010 = Data Field 01000 = CRC Sequence 11000 = CRC Delimiter 11001 = Acknowledge Slot 11011 = Acknowledge Delimiter 11010 = End of Frame 10010 = Intermission Whenever a bus error occurs, the corresponding bus error interrupt is forced, if enabled. At the same time, the current position of the Bit Stream Processor is captured into the Error Code Capture Register. The content within this register is fixed until the user software has read out its content once. From now on, the capture mechanism is activated again, i.e. reading the CANxICR enables another Bus Error Interrupt." /> + <BitField start="21" size="1" name="ERRDIR" description="When the CAN controller detects a bus error, the direction of the current bit is captured in this bit."> + <Enum name="ERROR_OCCURRED_DURIN" start="0" description="Error occurred during transmitting." /> + <Enum name="ERROR_OCCURRED_DURIN" start="1" description="Error occurred during receiving." /> + </BitField> + <BitField start="22" size="2" name="ERRC1_0" description="When the CAN controller detects a bus error, the type of error is captured in this field:"> + <Enum name="BIT_ERROR" start="0x0" description="Bit error" /> + <Enum name="FORM_ERROR" start="0x1" description="Form error" /> + <Enum name="STUFF_ERROR" start="0x2" description="Stuff error" /> + <Enum name="OTHER_ERROR" start="0x3" description="Other error" /> + </BitField> + <BitField start="24" size="8" name="ALCBIT" description="Each time arbitration is lost while trying to send on the CAN, the bit number within the frame is captured into this field. After the content of ALCBIT is read, the ALI bit is cleared and a new Arbitration Lost interrupt can occur. 00 = arbitration lost in the first bit (MS) of identifier ... 11 = arbitration lost in SRTS bit (RTR bit for standard frame messages) 12 = arbitration lost in IDE bit 13 = arbitration lost in 12th bit of identifier (extended frame only) ... 30 = arbitration lost in last bit of identifier (extended frame only) 31 = arbitration lost in RTR bit (extended frame only) On arbitration lost, the corresponding arbitration lost interrupt is forced, if enabled. At that time, the current bit position of the Bit Stream Processor is captured into the Arbitration Lost Capture Register. The content within this register is fixed until the user application has read out its contents once. From now on, the capture mechanism is activated again." /> + </Register> + <Register start="+0x010" size="4" name="IER" access="Read/Write" description="Interrupt Enable" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RIE" description="Receiver Interrupt Enable. When the Receive Buffer Status is 'full', the CAN Controller requests the respective interrupt." /> + <BitField start="1" size="1" name="TIE1" description="Transmit Interrupt Enable for Buffer1. When a message has been successfully transmitted out of TXB1 or Transmit Buffer 1 is accessible again (e.g. after an Abort Transmission command), the CAN Controller requests the respective interrupt." /> + <BitField start="2" size="1" name="EIE" description="Error Warning Interrupt Enable. If the Error or Bus Status change (see Status Register), the CAN Controller requests the respective interrupt." /> + <BitField start="3" size="1" name="DOIE" description="Data Overrun Interrupt Enable. If the Data Overrun Status bit is set (see Status Register), the CAN Controller requests the respective interrupt." /> + <BitField start="4" size="1" name="WUIE" description="Wake-Up Interrupt Enable. If the sleeping CAN controller wakes up, the respective interrupt is requested." /> + <BitField start="5" size="1" name="EPIE" description="Error Passive Interrupt Enable. If the error status of the CAN Controller changes from error active to error passive or vice versa, the respective interrupt is requested." /> + <BitField start="6" size="1" name="ALIE" description="Arbitration Lost Interrupt Enable. If the CAN Controller has lost arbitration, the respective interrupt is requested." /> + <BitField start="7" size="1" name="BEIE" description="Bus Error Interrupt Enable. If a bus error has been detected, the CAN Controller requests the respective interrupt." /> + <BitField start="8" size="1" name="IDIE" description="ID Ready Interrupt Enable. When a CAN identifier has been received, the CAN Controller requests the respective interrupt." /> + <BitField start="9" size="1" name="TIE2" description="Transmit Interrupt Enable for Buffer2. When a message has been successfully transmitted out of TXB2 or Transmit Buffer 2 is accessible again (e.g. after an Abort Transmission command), the CAN Controller requests the respective interrupt." /> + <BitField start="10" size="1" name="TIE3" description="Transmit Interrupt Enable for Buffer3. When a message has been successfully transmitted out of TXB3 or Transmit Buffer 3 is accessible again (e.g. after an Abort Transmission command), the CAN Controller requests the respective interrupt." /> + <BitField start="11" size="21" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x014" size="4" name="BTR" access="Read/Write" description="Bus Timing. Can only be written when RM in CANMOD is 1." reset_value="0x1C0000" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="10" name="BRP" description="Baud Rate Prescaler. The APB clock is divided by (this value plus one) to produce the CAN clock." /> + <BitField start="10" size="4" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="14" size="2" name="SJW" description="The Synchronization Jump Width is (this value plus one) CAN clocks." /> + <BitField start="16" size="4" name="TESG1" description="The delay from the nominal Sync point to the sample point is (this value plus one) CAN clocks." /> + <BitField start="20" size="3" name="TESG2" description="The delay from the sample point to the next nominal sync point is (this value plus one) CAN clocks. The nominal CAN bit time is (this value plus the value in TSEG1 plus 3) CAN clocks." /> + <BitField start="23" size="1" name="SAM" description="Sampling"> + <Enum name="THE_BUS_IS_SAMPLED_O" start="0" description="The bus is sampled once (recommended for high speed buses)" /> + <Enum name="THE_BUS_IS_SAMPLED_3" start="1" description="The bus is sampled 3 times (recommended for low to medium speed buses to filter spikes on the bus-line)" /> + </BitField> + <BitField start="24" size="8" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x018" size="4" name="EWL" access="Read/Write" description="Error Warning Limit. Can only be written when RM in CANMOD is 1." reset_value="0x60" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="EWL" description="During CAN operation, this value is compared to both the Tx and Rx Error Counters. If either of these counter matches this value, the Error Status (ES) bit in CANSR is set." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x01C" size="4" name="SR" access="ReadOnly" description="Status Register" reset_value="0x3C3C3C" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RBS_1" description="Receive Buffer Status. This bit is identical to the RBS bit in the CANxGSR." /> + <BitField start="1" size="1" name="DOS_1" description="Data Overrun Status. This bit is identical to the DOS bit in the CANxGSR." /> + <BitField start="2" size="1" name="TBS1_1" description="Transmit Buffer Status 1."> + <Enum name="LOCKED_SOFTWARE_CAN" start="0" description="Locked. Software cannot access the Tx Buffer 1 nor write to the corresponding CANxTFI, CANxTID, CANxTDA, and CANxTDB registers because a message is either waiting for transmission or is in transmitting process." /> + <Enum name="RELEASED_SOFTWARE_M" start="1" description="Released. Software may write a message into the Transmit Buffer 1 and its CANxTFI, CANxTID, CANxTDA, and CANxTDB registers." /> + </BitField> + <BitField start="3" size="1" name="TCS1_1" description="Transmission Complete Status."> + <Enum name="INCOMPLETE_THE_PREV" start="0" description="Incomplete. The previously requested transmission for Tx Buffer 1 is not complete." /> + <Enum name="COMPLETE_THE_PREVIO" start="1" description="Complete. The previously requested transmission for Tx Buffer 1 has been successfully completed." /> + </BitField> + <BitField start="4" size="1" name="RS_1" description="Receive Status. This bit is identical to the RS bit in the GSR." /> + <BitField start="5" size="1" name="TS1_1" description="Transmit Status 1."> + <Enum name="IDLE_THERE_IS_NO_TR" start="0" description="Idle. There is no transmission from Tx Buffer 1." /> + <Enum name="TRANSMIT_THE_CAN_CO" start="1" description="Transmit. The CAN Controller is transmitting a message from Tx Buffer 1." /> + </BitField> + <BitField start="6" size="1" name="ES_1" description="Error Status. This bit is identical to the ES bit in the CANxGSR." /> + <BitField start="7" size="1" name="BS_1" description="Bus Status. This bit is identical to the BS bit in the CANxGSR." /> + <BitField start="8" size="1" name="RBS_2" description="Receive Buffer Status. This bit is identical to the RBS bit in the CANxGSR." /> + <BitField start="9" size="1" name="DOS_2" description="Data Overrun Status. This bit is identical to the DOS bit in the CANxGSR." /> + <BitField start="10" size="1" name="TBS2_2" description="Transmit Buffer Status 2."> + <Enum name="LOCKED_SOFTWARE_CAN" start="0" description="Locked. Software cannot access the Tx Buffer 2 nor write to the corresponding CANxTFI, CANxTID, CANxTDA, and CANxTDB registers because a message is either waiting for transmission or is in transmitting process." /> + <Enum name="RELEASED_SOFTWARE_M" start="1" description="Released. Software may write a message into the Transmit Buffer 2 and its CANxTFI, CANxTID, CANxTDA, and CANxTDB registers." /> + </BitField> + <BitField start="11" size="1" name="TCS2_2" description="Transmission Complete Status."> + <Enum name="INCOMPLETE_THE_PREV" start="0" description="Incomplete. The previously requested transmission for Tx Buffer 2 is not complete." /> + <Enum name="COMPLETE_THE_PREVIO" start="1" description="Complete. The previously requested transmission for Tx Buffer 2 has been successfully completed." /> + </BitField> + <BitField start="12" size="1" name="RS_2" description="Receive Status. This bit is identical to the RS bit in the GSR." /> + <BitField start="13" size="1" name="TS2_2" description="Transmit Status 2."> + <Enum name="IDLE_THERE_IS_NO_TR" start="0" description="Idle. There is no transmission from Tx Buffer 2." /> + <Enum name="TRANSMIT_THE_CAN_CO" start="1" description="Transmit. The CAN Controller is transmitting a message from Tx Buffer 2." /> + </BitField> + <BitField start="14" size="1" name="ES_2" description="Error Status. This bit is identical to the ES bit in the CANxGSR." /> + <BitField start="15" size="1" name="BS_2" description="Bus Status. This bit is identical to the BS bit in the CANxGSR." /> + <BitField start="16" size="1" name="RBS_3" description="Receive Buffer Status. This bit is identical to the RBS bit in the CANxGSR." /> + <BitField start="17" size="1" name="DOS_3" description="Data Overrun Status. This bit is identical to the DOS bit in the CANxGSR." /> + <BitField start="18" size="1" name="TBS3_3" description="Transmit Buffer Status 3."> + <Enum name="LOCKED_SOFTWARE_CAN" start="0" description="Locked. Software cannot access the Tx Buffer 3 nor write to the corresponding CANxTFI, CANxTID, CANxTDA, and CANxTDB registers because a message is either waiting for transmission or is in transmitting process." /> + <Enum name="RELEASED_SOFTWARE_M" start="1" description="Released. Software may write a message into the Transmit Buffer 3 and its CANxTFI, CANxTID, CANxTDA, and CANxTDB registers." /> + </BitField> + <BitField start="19" size="1" name="TCS3_3" description="Transmission Complete Status."> + <Enum name="INCOMPLETE_THE_PREV" start="0" description="Incomplete. The previously requested transmission for Tx Buffer 3 is not complete." /> + <Enum name="COMPLETE_THE_PREVIO" start="1" description="Complete. The previously requested transmission for Tx Buffer 3 has been successfully completed." /> + </BitField> + <BitField start="20" size="1" name="RS_3" description="Receive Status. This bit is identical to the RS bit in the GSR." /> + <BitField start="21" size="1" name="TS3_3" description="Transmit Status 3."> + <Enum name="IDLE_THERE_IS_NO_TR" start="0" description="Idle. There is no transmission from Tx Buffer 3." /> + <Enum name="TRANSMIT_THE_CAN_CO" start="1" description="Transmit. The CAN Controller is transmitting a message from Tx Buffer 3." /> + </BitField> + <BitField start="22" size="1" name="ES_3" description="Error Status. This bit is identical to the ES bit in the CANxGSR." /> + <BitField start="23" size="1" name="BS_3" description="Bus Status. This bit is identical to the BS bit in the CANxGSR." /> + <BitField start="24" size="8" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x020" size="4" name="RFS" access="Read/Write" description="Receive frame status. Can only be written when RM in CANMOD is 1." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="10" name="IDINDEX" description="ID Index. If the BP bit (below) is 0, this value is the zero-based number of the Lookup Table RAM entry at which the Acceptance Filter matched the received Identifier. Disabled entries in the Standard tables are included in this numbering, but will not be matched. See Section 21.17 Examples of acceptance filter tables and ID index values on page 587 for examples of ID Index values." /> + <BitField start="10" size="1" name="BP" description="If this bit is 1, the current message was received in AF Bypass mode, and the ID Index field (above) is meaningless." /> + <BitField start="11" size="5" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + <BitField start="16" size="4" name="DLC" description="The field contains the Data Length Code (DLC) field of the current received message. When RTR = 0, this is related to the number of data bytes available in the CANRDA and CANRDB registers as follows: 0000-0111 = 0 to 7 bytes1000-1111 = 8 bytes With RTR = 1, this value indicates the number of data bytes requested to be sent back, with the same encoding." /> + <BitField start="20" size="10" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="30" size="1" name="RTR" description="This bit contains the Remote Transmission Request bit of the current received message. 0 indicates a Data Frame, in which (if DLC is non-zero) data can be read from the CANRDA and possibly the CANRDB registers. 1 indicates a Remote frame, in which case the DLC value identifies the number of data bytes requested to be sent using the same Identifier." /> + <BitField start="31" size="1" name="FF" description="A 0 in this bit indicates that the current received message included an 11-bit Identifier, while a 1 indicates a 29-bit Identifier. This affects the contents of the CANid register described below." /> + </Register> + <Register start="+0x024" size="4" name="RID" access="Read/Write" description="Received Identifier. Can only be written when RM in CANMOD is 1." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="11" name="ID" description="The 11-bit Identifier field of the current received message. In CAN 2.0A, these bits are called ID10-0, while in CAN 2.0B they're called ID29-18." /> + <BitField start="11" size="21" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x028" size="4" name="RDA" access="Read/Write" description="Received data bytes 1-4. Can only be written when RM in CANMOD is 1." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="DATA1" description="Data 1. If the DLC field in CANRFS >= 0001, this contains the first Data byte of the current received message." /> + <BitField start="8" size="8" name="DATA2" description="Data 2. If the DLC field in CANRFS >= 0010, this contains the first Data byte of the current received message." /> + <BitField start="16" size="8" name="DATA3" description="Data 3. If the DLC field in CANRFS >= 0011, this contains the first Data byte of the current received message." /> + <BitField start="24" size="8" name="DATA4" description="Data 4. If the DLC field in CANRFS >= 0100, this contains the first Data byte of the current received message." /> + </Register> + <Register start="+0x02C" size="4" name="RDB" access="Read/Write" description="Received data bytes 5-8. Can only be written when RM in CANMOD is 1." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="DATA5" description="Data 5. If the DLC field in CANRFS >= 0101, this contains the first Data byte of the current received message." /> + <BitField start="8" size="8" name="DATA6" description="Data 6. If the DLC field in CANRFS >= 0110, this contains the first Data byte of the current received message." /> + <BitField start="16" size="8" name="DATA7" description="Data 7. If the DLC field in CANRFS >= 0111, this contains the first Data byte of the current received message." /> + <BitField start="24" size="8" name="DATA8" description="Data 8. If the DLC field in CANRFS >= 1000, this contains the first Data byte of the current received message." /> + </Register> + <Register start="+0x030+0" size="4" name="TFI1" access="Read/Write" description="Transmit
frame info (Tx Buffer )" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="PRIO" description="If the TPM (Transmit Priority Mode) bit in the CANxMOD register is set to 1, enabled Tx Buffers contend for the right to send their messages based on this field. The buffer with the lowest TX Priority value wins the prioritization and is sent first." /> + <BitField start="8" size="8" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="16" size="4" name="DLC" description="Data Length Code. This value is sent in the DLC field of the next transmit message. In addition, if RTR = 0, this value controls the number of Data bytes sent in the next transmit message, from the CANxTDA and CANxTDB registers: 0000-0111 = 0-7 bytes 1xxx = 8 bytes" /> + <BitField start="20" size="10" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="30" size="1" name="RTR" description="This value is sent in the RTR bit of the next transmit message. If this bit is 0, the number of data bytes called out by the DLC field are sent from the CANxTDA and CANxTDB registers. If this bit is 1, a Remote Frame is sent, containing a request for that number of bytes." /> + <BitField start="31" size="1" name="FF" description="If this bit is 0, the next transmit message will be sent with an 11-bit Identifier (standard frame format), while if it's 1, the message will be sent with a 29-bit Identifier (extended frame format)." /> + </Register> + <Register start="+0x030+16" size="4" name="TFI2" access="Read/Write" description="Transmit
frame info (Tx Buffer )" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="PRIO" description="If the TPM (Transmit Priority Mode) bit in the CANxMOD register is set to 1, enabled Tx Buffers contend for the right to send their messages based on this field. The buffer with the lowest TX Priority value wins the prioritization and is sent first." /> + <BitField start="8" size="8" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="16" size="4" name="DLC" description="Data Length Code. This value is sent in the DLC field of the next transmit message. In addition, if RTR = 0, this value controls the number of Data bytes sent in the next transmit message, from the CANxTDA and CANxTDB registers: 0000-0111 = 0-7 bytes 1xxx = 8 bytes" /> + <BitField start="20" size="10" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="30" size="1" name="RTR" description="This value is sent in the RTR bit of the next transmit message. If this bit is 0, the number of data bytes called out by the DLC field are sent from the CANxTDA and CANxTDB registers. If this bit is 1, a Remote Frame is sent, containing a request for that number of bytes." /> + <BitField start="31" size="1" name="FF" description="If this bit is 0, the next transmit message will be sent with an 11-bit Identifier (standard frame format), while if it's 1, the message will be sent with a 29-bit Identifier (extended frame format)." /> + </Register> + <Register start="+0x030+32" size="4" name="TFI3" access="Read/Write" description="Transmit
frame info (Tx Buffer )" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="PRIO" description="If the TPM (Transmit Priority Mode) bit in the CANxMOD register is set to 1, enabled Tx Buffers contend for the right to send their messages based on this field. The buffer with the lowest TX Priority value wins the prioritization and is sent first." /> + <BitField start="8" size="8" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="16" size="4" name="DLC" description="Data Length Code. This value is sent in the DLC field of the next transmit message. In addition, if RTR = 0, this value controls the number of Data bytes sent in the next transmit message, from the CANxTDA and CANxTDB registers: 0000-0111 = 0-7 bytes 1xxx = 8 bytes" /> + <BitField start="20" size="10" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="30" size="1" name="RTR" description="This value is sent in the RTR bit of the next transmit message. If this bit is 0, the number of data bytes called out by the DLC field are sent from the CANxTDA and CANxTDB registers. If this bit is 1, a Remote Frame is sent, containing a request for that number of bytes." /> + <BitField start="31" size="1" name="FF" description="If this bit is 0, the next transmit message will be sent with an 11-bit Identifier (standard frame format), while if it's 1, the message will be sent with a 29-bit Identifier (extended frame format)." /> + </Register> + <Register start="+0x034+0" size="4" name="TID1" access="Read/Write" description="Transmit
Identifier (Tx Buffer)" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="11" name="ID" description="The 11-bit Identifier to be sent in the next transmit message." /> + <BitField start="11" size="21" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x034+16" size="4" name="TID2" access="Read/Write" description="Transmit
Identifier (Tx Buffer)" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="11" name="ID" description="The 11-bit Identifier to be sent in the next transmit message." /> + <BitField start="11" size="21" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x034+32" size="4" name="TID3" access="Read/Write" description="Transmit
Identifier (Tx Buffer)" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="11" name="ID" description="The 11-bit Identifier to be sent in the next transmit message." /> + <BitField start="11" size="21" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x038+0" size="4" name="TDA1" access="Read/Write" description="Transmit
data bytes 1-4 (Tx Buffer)" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="8" name="DATA1" description="Data 1. If RTR = 0 and DLC >= 0001 in the corresponding CANxTFI, this byte is sent as the first Data byte of the next transmit message." /> + <BitField start="8" size="8" name="DATA2" description="Data 2. If RTR = 0 and DLC >= 0010 in the corresponding CANxTFI, this byte is sent as the 2nd Data byte of the next transmit message." /> + <BitField start="16" size="8" name="DATA3" description="Data 3. If RTR = 0 and DLC >= 0011 in the corresponding CANxTFI, this byte is sent as the 3rd Data byte of the next transmit message." /> + <BitField start="24" size="8" name="DATA4" description="Data 4. If RTR = 0 and DLC >= 0100 in the corresponding CANxTFI, this byte is sent as the 4th Data byte of the next transmit message." /> + </Register> + <Register start="+0x038+16" size="4" name="TDA2" access="Read/Write" description="Transmit
data bytes 1-4 (Tx Buffer)" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="8" name="DATA1" description="Data 1. If RTR = 0 and DLC >= 0001 in the corresponding CANxTFI, this byte is sent as the first Data byte of the next transmit message." /> + <BitField start="8" size="8" name="DATA2" description="Data 2. If RTR = 0 and DLC >= 0010 in the corresponding CANxTFI, this byte is sent as the 2nd Data byte of the next transmit message." /> + <BitField start="16" size="8" name="DATA3" description="Data 3. If RTR = 0 and DLC >= 0011 in the corresponding CANxTFI, this byte is sent as the 3rd Data byte of the next transmit message." /> + <BitField start="24" size="8" name="DATA4" description="Data 4. If RTR = 0 and DLC >= 0100 in the corresponding CANxTFI, this byte is sent as the 4th Data byte of the next transmit message." /> + </Register> + <Register start="+0x038+32" size="4" name="TDA3" access="Read/Write" description="Transmit
data bytes 1-4 (Tx Buffer)" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="8" name="DATA1" description="Data 1. If RTR = 0 and DLC >= 0001 in the corresponding CANxTFI, this byte is sent as the first Data byte of the next transmit message." /> + <BitField start="8" size="8" name="DATA2" description="Data 2. If RTR = 0 and DLC >= 0010 in the corresponding CANxTFI, this byte is sent as the 2nd Data byte of the next transmit message." /> + <BitField start="16" size="8" name="DATA3" description="Data 3. If RTR = 0 and DLC >= 0011 in the corresponding CANxTFI, this byte is sent as the 3rd Data byte of the next transmit message." /> + <BitField start="24" size="8" name="DATA4" description="Data 4. If RTR = 0 and DLC >= 0100 in the corresponding CANxTFI, this byte is sent as the 4th Data byte of the next transmit message." /> + </Register> + <Register start="+0x03C+0" size="4" name="TDB1" access="Read/Write" description="Transmit
data bytes 5-8 (Tx Buffer )" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="8" name="DATA5" description="Data 5. If RTR = 0 and DLC >= 0101 in the corresponding CANTFI, this byte is sent as the 5th Data byte of the next transmit message." /> + <BitField start="8" size="8" name="DATA6" description="Data 6. If RTR = 0 and DLC >= 0110 in the corresponding CANTFI, this byte is sent as the 6th Data byte of the next transmit message." /> + <BitField start="16" size="8" name="DATA7" description="Data 7. If RTR = 0 and DLC >= 0111 in the corresponding CANTFI, this byte is sent as the 7th Data byte of the next transmit message." /> + <BitField start="24" size="8" name="DATA8" description="Data 8. If RTR = 0 and DLC >= 1000 in the corresponding CANTFI, this byte is sent as the 8th Data byte of the next transmit message." /> + </Register> + <Register start="+0x03C+16" size="4" name="TDB2" access="Read/Write" description="Transmit
data bytes 5-8 (Tx Buffer )" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="8" name="DATA5" description="Data 5. If RTR = 0 and DLC >= 0101 in the corresponding CANTFI, this byte is sent as the 5th Data byte of the next transmit message." /> + <BitField start="8" size="8" name="DATA6" description="Data 6. If RTR = 0 and DLC >= 0110 in the corresponding CANTFI, this byte is sent as the 6th Data byte of the next transmit message." /> + <BitField start="16" size="8" name="DATA7" description="Data 7. If RTR = 0 and DLC >= 0111 in the corresponding CANTFI, this byte is sent as the 7th Data byte of the next transmit message." /> + <BitField start="24" size="8" name="DATA8" description="Data 8. If RTR = 0 and DLC >= 1000 in the corresponding CANTFI, this byte is sent as the 8th Data byte of the next transmit message." /> + </Register> + <Register start="+0x03C+32" size="4" name="TDB3" access="Read/Write" description="Transmit
data bytes 5-8 (Tx Buffer )" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="8" name="DATA5" description="Data 5. If RTR = 0 and DLC >= 0101 in the corresponding CANTFI, this byte is sent as the 5th Data byte of the next transmit message." /> + <BitField start="8" size="8" name="DATA6" description="Data 6. If RTR = 0 and DLC >= 0110 in the corresponding CANTFI, this byte is sent as the 6th Data byte of the next transmit message." /> + <BitField start="16" size="8" name="DATA7" description="Data 7. If RTR = 0 and DLC >= 0111 in the corresponding CANTFI, this byte is sent as the 7th Data byte of the next transmit message." /> + <BitField start="24" size="8" name="DATA8" description="Data 8. If RTR = 0 and DLC >= 1000 in the corresponding CANTFI, this byte is sent as the 8th Data byte of the next transmit message." /> + </Register> + </RegisterGroup> + <RegisterGroup name="CAN2" start="0x40048000" description="CAN1 controller "> + <Register start="+0x000" size="4" name="MOD" access="Read/Write" description="Controls the operating mode of the CAN Controller." reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="RM" description="Reset Mode."> + <Enum name="NORMAL_THE_CAN_CONTR" start="0" description="Normal.The CAN Controller is in the Operating Mode, and certain registers can not be written." /> + <Enum name="RESET_CAN_OPERATION" start="1" description="Reset. CAN operation is disabled, writable registers can be written and the current transmission/reception of a message is aborted." /> + </BitField> + <BitField start="1" size="1" name="LOM" description="Listen Only Mode."> + <Enum name="NORMAL_THE_CAN_CONT" start="0" description="Normal. The CAN controller acknowledges a successfully received message on the CAN bus. The error counters are stopped at the current value." /> + <Enum name="LISTEN_ONLY_THE_CON" start="1" description="Listen only. The controller gives no acknowledgment, even if a message is successfully received. Messages cannot be sent, and the controller operates in error passive mode. This mode is intended for software bit rate detection and hot plugging." /> + </BitField> + <BitField start="2" size="1" name="STM" description="Self Test Mode."> + <Enum name="NORMAL_A_TRANSMITTE" start="0" description="Normal. A transmitted message must be acknowledged to be considered successful." /> + <Enum name="SELF_TEST_THE_CONTR" start="1" description="Self test. The controller will consider a Tx message successful even if there is no acknowledgment received. In this mode a full node test is possible without any other active node on the bus using the SRR bit in CANxCMR." /> + </BitField> + <BitField start="3" size="1" name="TPM" description="Transmit Priority Mode."> + <Enum name="CAN_ID_THE_TRANSMIT" start="0" description="CAN ID. The transmit priority for 3 Transmit Buffers depends on the CAN Identifier." /> + <Enum name="LOCAL_PRIORITY_THE_" start="1" description="Local priority. The transmit priority for 3 Transmit Buffers depends on the contents of the Tx Priority register within the Transmit Buffer." /> + </BitField> + <BitField start="4" size="1" name="SM" description="Sleep Mode."> + <Enum name="WAKE_UP_NORMAL_OPER" start="0" description="Wake-up. Normal operation." /> + <Enum name="SLEEP_THE_CAN_CONTR" start="1" description="Sleep. The CAN controller enters Sleep Mode if no CAN interrupt is pending and there is no bus activity. See the Sleep Mode description Section 21.8.2 on page 565." /> + </BitField> + <BitField start="5" size="1" name="RPM" description="Receive Polarity Mode."> + <Enum name="LOW_ACTIVE_RD_INPUT" start="0" description="Low active. RD input is active Low (dominant bit = 0)." /> + <Enum name="HIGH_ACTIVE_RD_INPU" start="1" description="High active. RD input is active High (dominant bit = 1) -- reverse polarity." /> + </BitField> + <BitField start="6" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="7" size="1" name="TM" description="Test Mode."> + <Enum name="DISABLED_NORMAL_OPE" start="0" description="Disabled. Normal operation." /> + <Enum name="ENABLED_THE_TD_PIN_" start="1" description="Enabled. The TD pin will reflect the bit, detected on RD pin, with the next positive edge of the system clock." /> + </BitField> + <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x004" size="4" name="CMR" access="WriteOnly" description="Command bits that affect the state of the CAN Controller" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="TR" description="Transmission Request."> + <Enum name="ABSENT_NO_TRANSMISSI" start="0" description="Absent.No transmission request." /> + <Enum name="PRESENT_THE_MESSAGE" start="1" description="Present. The message, previously written to the CANxTFI, CANxTID, and optionally the CANxTDA and CANxTDB registers, is queued for transmission from the selected Transmit Buffer. If at two or all three of STB1, STB2 and STB3 bits are selected when TR=1 is written, Transmit Buffer will be selected based on the chosen priority scheme (for details see Section 21.5.3 Transmit Buffers (TXB))" /> + </BitField> + <BitField start="1" size="1" name="AT" description="Abort Transmission."> + <Enum name="NO_ACTION_DO_NOT_AB" start="0" description="No action. Do not abort the transmission." /> + <Enum name="PRESENT_IF_NOT_ALRE" start="1" description="Present. if not already in progress, a pending Transmission Request for the selected Transmit Buffer is cancelled." /> + </BitField> + <BitField start="2" size="1" name="RRB" description="Release Receive Buffer."> + <Enum name="NO_ACTION_DO_NOT_RE" start="0" description="No action. Do not release the receive buffer." /> + <Enum name="RELEASED_THE_INFORM" start="1" description="Released. The information in the Receive Buffer (consisting of CANxRFS, CANxRID, and if applicable the CANxRDA and CANxRDB registers) is released, and becomes eligible for replacement by the next received frame. If the next received frame is not available, writing this command clears the RBS bit in the Status Register(s)." /> + </BitField> + <BitField start="3" size="1" name="CDO" description="Clear Data Overrun."> + <Enum name="NO_ACTION_DO_NOT_CL" start="0" description="No action. Do not clear the data overrun bit." /> + <Enum name="CLEAR_THE_DATA_OVER" start="1" description="Clear. The Data Overrun bit in Status Register(s) is cleared." /> + </BitField> + <BitField start="4" size="1" name="SRR" description="Self Reception Request."> + <Enum name="ABSENT_NO_SELF_RECE" start="0" description="Absent. No self reception request." /> + <Enum name="PRESENT_THE_MESSAGE" start="1" description="Present. The message, previously written to the CANxTFS, CANxTID, and optionally the CANxTDA and CANxTDB registers, is queued for transmission from the selected Transmit Buffer and received simultaneously. This differs from the TR bit above in that the receiver is not disabled during the transmission, so that it receives the message if its Identifier is recognized by the Acceptance Filter." /> + </BitField> + <BitField start="5" size="1" name="STB1" description="Select Tx Buffer 1."> + <Enum name="NOT_SELECTED_TX_BUF" start="0" description="Not selected. Tx Buffer 1 is not selected for transmission." /> + <Enum name="SELECTED_TX_BUFFER_" start="1" description="Selected. Tx Buffer 1 is selected for transmission." /> + </BitField> + <BitField start="6" size="1" name="STB2" description="Select Tx Buffer 2."> + <Enum name="NOT_SELECTED_TX_BUF" start="0" description="Not selected. Tx Buffer 2 is not selected for transmission." /> + <Enum name="SELECTED_TX_BUFFER_" start="1" description="Selected. Tx Buffer 2 is selected for transmission." /> + </BitField> + <BitField start="7" size="1" name="STB3" description="Select Tx Buffer 3."> + <Enum name="NOT_SELECTED_TX_BUF" start="0" description="Not selected. Tx Buffer 3 is not selected for transmission." /> + <Enum name="SELECTED_TX_BUFFER_" start="1" description="Selected. Tx Buffer 3 is selected for transmission." /> + </BitField> + <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x008" size="4" name="GSR" access="ReadOnly" description="Global Controller Status and Error Counters. The error counters can only be written when RM in CANMOD is 1." reset_value="0x3C" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RBS" description="Receive Buffer Status. After reading all messages and releasing their memory space with the command 'Release Receive Buffer,' this bit is cleared."> + <Enum name="EMPTY_NO_MESSAGE_IS" start="0" description="Empty. No message is available." /> + <Enum name="FULL_AT_LEAST_ONE_C" start="1" description="Full. At least one complete message is received by the Double Receive Buffer and available in the CANxRFS, CANxRID, and if applicable the CANxRDA and CANxRDB registers. This bit is cleared by the Release Receive Buffer command in CANxCMR, if no subsequent received message is available." /> + </BitField> + <BitField start="1" size="1" name="DOS" description="Data Overrun Status. If there is not enough space to store the message within the Receive Buffer, that message is dropped and the Data Overrun condition is signalled to the CPU in the moment this message becomes valid. If this message is not completed successfully (e.g. because of an error), no overrun condition is signalled."> + <Enum name="ABSENT_NO_DATA_OVER" start="0" description="Absent. No data overrun has occurred since the last Clear Data Overrun command was given/written to CANxCMR (or since Reset)." /> + <Enum name="OVERRUN_A_MESSAGE_W" start="1" description="Overrun. A message was lost because the preceding message to this CAN controller was not read and released quickly enough (there was not enough space for a new message in the Double Receive Buffer)." /> + </BitField> + <BitField start="2" size="1" name="TBS" description="Transmit Buffer Status."> + <Enum name="LOCKED_AT_LEAST_ONE" start="0" description="Locked. At least one of the Transmit Buffers is not available for the CPU, i.e. at least one previously queued message for this CAN controller has not yet been sent, and therefore software should not write to the CANxTFI, CANxTID, CANxTDA, nor CANxTDB registers of that (those) Tx buffer(s)." /> + <Enum name="RELEASED_ALL_THREE_" start="1" description="Released. All three Transmit Buffers are available for the CPU. No transmit message is pending for this CAN controller (in any of the 3 Tx buffers), and software may write to any of the CANxTFI, CANxTID, CANxTDA, and CANxTDB registers." /> + </BitField> + <BitField start="3" size="1" name="TCS" description="Transmit Complete Status. The Transmission Complete Status bit is set '0' (incomplete) whenever the Transmission Request bit or the Self Reception Request bit is set '1' at least for one of the three Transmit Buffers. The Transmission Complete Status bit will remain '0' until all messages are transmitted successfully."> + <Enum name="INCOMPLETE_AT_LEAST" start="0" description="Incomplete. At least one requested transmission has not been successfully completed yet." /> + <Enum name="COMPLETE_ALL_REQUES" start="1" description="Complete. All requested transmission(s) has (have) been successfully completed." /> + </BitField> + <BitField start="4" size="1" name="RS" description="Receive Status. If both the Receive Status and the Transmit Status bits are '0' (idle), the CAN-Bus is idle. If both bits are set, the controller is waiting to become idle again. After hardware reset 11 consecutive recessive bits have to be detected until idle status is reached. After Bus-off this will take 128 times of 11 consecutive recessive bits."> + <Enum name="IDLE_THE_CAN_CONTRO" start="0" description="Idle. The CAN controller is idle." /> + <Enum name="RECEIVE_THE_CAN_CON" start="1" description="Receive. The CAN controller is receiving a message." /> + </BitField> + <BitField start="5" size="1" name="TS" description="Transmit Status. If both the Receive Status and the Transmit Status bits are '0' (idle), the CAN-Bus is idle. If both bits are set, the controller is waiting to become idle again. After hardware reset 11 consecutive recessive bits have to be detected until idle status is reached. After Bus-off this will take 128 times of 11 consecutive recessive bits."> + <Enum name="IDLE_THE_CAN_CONTRO" start="0" description="Idle. The CAN controller is idle." /> + <Enum name="TRANSMIT_THE_CAN_CO" start="1" description="Transmit. The CAN controller is sending a message." /> + </BitField> + <BitField start="6" size="1" name="ES" description="Error Status. Errors detected during reception or transmission will effect the error counters according to the CAN specification. The Error Status bit is set when at least one of the error counters has reached or exceeded the Error Warning Limit. An Error Warning Interrupt is generated, if enabled. The default value of the Error Warning Limit after hardware reset is 96 decimal, see also Section 21.7.7 CAN Error Warning Limit register (CAN1EWL - 0x4004 4018, CAN2EWL - 0x4004 8018)."> + <Enum name="OK_BOTH_ERROR_COUNT" start="0" description="OK. Both error counters are below the Error Warning Limit." /> + <Enum name="ERROR_ONE_OR_BOTH_O" start="1" description="Error. One or both of the Transmit and Receive Error Counters has reached the limit set in the Error Warning Limit register." /> + </BitField> + <BitField start="7" size="1" name="BS" description="Bus Status. Mode bit '1' (present) and an Error Warning Interrupt is generated, if enabled. Afterwards the Transmit Error Counter is set to '127', and the Receive Error Counter is cleared. It will stay in this mode until the CPU clears the Reset Mode bit. Once this is completed the CAN Controller will wait the minimum protocol-defined time (128 occurrences of the Bus-Free signal) counting down the Transmit Error Counter. After that, the Bus Status bit is cleared (Bus-On), the Error Status bit is set '0' (ok), the Error Counters are reset, and an Error Warning Interrupt is generated, if enabled. Reading the TX Error Counter during this time gives information about the status of the Bus-Off recovery."> + <Enum name="BUS_ON_THE_CAN_CONT" start="0" description="Bus-on. The CAN Controller is involved in bus activities" /> + <Enum name="BUS_OFF_THE_CAN_CON" start="1" description="Bus-off. The CAN controller is currently not involved/prohibited from bus activity because the Transmit Error Counter reached its limiting value of 255." /> + </BitField> + <BitField start="8" size="8" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="16" size="8" name="RXERR" description="The current value of the Rx Error Counter (an 8-bit value)." /> + <BitField start="24" size="8" name="TXERR" description="The current value of the Tx Error Counter (an 8-bit value)." /> + </Register> + <Register start="+0x00C" size="4" name="ICR" access="ReadOnly" description="Interrupt status, Arbitration Lost Capture, Error Code Capture" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RI" description="Receive Interrupt. This bit is set whenever the RBS bit in CANxSR and the RIE bit in CANxIER are both 1, indicating that a new message was received and stored in the Receive Buffer. The Receive Interrupt Bit is not cleared upon a read access to the Interrupt Register. Giving the Command Release Receive Buffer will clear RI temporarily. If there is another message available within the Receive Buffer after the release command, RI is set again. Otherwise RI remains cleared."> + <Enum name="RESET" start="0" description="Reset" /> + <Enum name="SET" start="1" description="Set" /> + </BitField> + <BitField start="1" size="1" name="TI1" description="Transmit Interrupt 1. This bit is set when the TBS1 bit in CANxSR goes from 0 to 1 (whenever a message out of TXB1 was successfully transmitted or aborted), indicating that Transmit buffer 1 is available, and the TIE1 bit in CANxIER is 1."> + <Enum name="RESET" start="0" description="Reset" /> + <Enum name="SET" start="1" description="Set" /> + </BitField> + <BitField start="2" size="1" name="EI" description="Error Warning Interrupt. This bit is set on every change (set or clear) of either the Error Status or Bus Status bit in CANxSR and the EIE bit bit is set within the Interrupt Enable Register at the time of the change."> + <Enum name="RESET" start="0" description="Reset" /> + <Enum name="SET" start="1" description="Set" /> + </BitField> + <BitField start="3" size="1" name="DOI" description="Data Overrun Interrupt. This bit is set when the DOS bit in CANxSR goes from 0 to 1 and the DOIE bit in CANxIER is 1."> + <Enum name="RESET" start="0" description="Reset" /> + <Enum name="SET" start="1" description="Set" /> + </BitField> + <BitField start="4" size="1" name="WUI" description="Wake-Up Interrupt. This bit is set if the CAN controller is sleeping and bus activity is detected and the WUIE bit in CANxIER is 1. A Wake-Up Interrupt is also generated if the CPU tries to set the Sleep bit while the CAN controller is involved in bus activities or a CAN Interrupt is pending. The WUI flag can also get asserted when the according enable bit WUIE is not set. In this case a Wake-Up Interrupt does not get asserted."> + <Enum name="RESET" start="0" description="Reset" /> + <Enum name="SET" start="1" description="Set" /> + </BitField> + <BitField start="5" size="1" name="EPI" description="Error Passive Interrupt. This bit is set if the EPIE bit in CANxIER is 1, and the CAN controller switches between Error Passive and Error Active mode in either direction. This is the case when the CAN Controller has reached the Error Passive Status (at least one error counter exceeds the CAN protocol defined level of 127) or if the CAN Controller is in Error Passive Status and enters the Error Active Status again."> + <Enum name="RESET" start="0" description="Reset" /> + <Enum name="SET" start="1" description="Set" /> + </BitField> + <BitField start="6" size="1" name="ALI" description="Arbitration Lost Interrupt. This bit is set if the ALIE bit in CANxIER is 1, and the CAN controller loses arbitration while attempting to transmit. In this case the CAN node becomes a receiver."> + <Enum name="RESET" start="0" description="Reset" /> + <Enum name="SET" start="1" description="Set" /> + </BitField> + <BitField start="7" size="1" name="BEI" description="Bus Error Interrupt -- this bit is set if the BEIE bit in CANxIER is 1, and the CAN controller detects an error on the bus."> + <Enum name="RESET" start="0" description="Reset" /> + <Enum name="SET" start="1" description="Set" /> + </BitField> + <BitField start="8" size="1" name="IDI" description="ID Ready Interrupt -- this bit is set if the IDIE bit in CANxIER is 1, and a CAN Identifier has been received (a message was successfully transmitted or aborted). This bit is set whenever a message was successfully transmitted or aborted and the IDIE bit is set in the IER register."> + <Enum name="RESET" start="0" description="Reset" /> + <Enum name="SET" start="1" description="Set" /> + </BitField> + <BitField start="9" size="1" name="TI2" description="Transmit Interrupt 2. This bit is set when the TBS2 bit in CANxSR goes from 0 to 1 (whenever a message out of TXB2 was successfully transmitted or aborted), indicating that Transmit buffer 2 is available, and the TIE2 bit in CANxIER is 1."> + <Enum name="RESET" start="0" description="Reset" /> + <Enum name="SET" start="1" description="Set" /> + </BitField> + <BitField start="10" size="1" name="TI3" description="Transmit Interrupt 3. This bit is set when the TBS3 bit in CANxSR goes from 0 to 1 (whenever a message out of TXB3 was successfully transmitted or aborted), indicating that Transmit buffer 3 is available, and the TIE3 bit in CANxIER is 1."> + <Enum name="RESET" start="0" description="Reset" /> + <Enum name="SET" start="1" description="Set" /> + </BitField> + <BitField start="11" size="5" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + <BitField start="16" size="5" name="ERRBIT4_0" description="Error Code Capture: when the CAN controller detects a bus error, the location of the error within the frame is captured in this field. The value reflects an internal state variable, and as a result is not very linear: 00011 = Start of Frame 00010 = ID28 ... ID21 00110 = ID20 ... ID18 00100 = SRTR Bit 00101 = IDE bit 00111 = ID17 ... 13 01111 = ID12 ... ID5 01110 = ID4 ... ID0 01100 = RTR Bit 01101 = Reserved Bit 1 01001 = Reserved Bit 0 01011 = Data Length Code 01010 = Data Field 01000 = CRC Sequence 11000 = CRC Delimiter 11001 = Acknowledge Slot 11011 = Acknowledge Delimiter 11010 = End of Frame 10010 = Intermission Whenever a bus error occurs, the corresponding bus error interrupt is forced, if enabled. At the same time, the current position of the Bit Stream Processor is captured into the Error Code Capture Register. The content within this register is fixed until the user software has read out its content once. From now on, the capture mechanism is activated again, i.e. reading the CANxICR enables another Bus Error Interrupt." /> + <BitField start="21" size="1" name="ERRDIR" description="When the CAN controller detects a bus error, the direction of the current bit is captured in this bit."> + <Enum name="ERROR_OCCURRED_DURIN" start="0" description="Error occurred during transmitting." /> + <Enum name="ERROR_OCCURRED_DURIN" start="1" description="Error occurred during receiving." /> + </BitField> + <BitField start="22" size="2" name="ERRC1_0" description="When the CAN controller detects a bus error, the type of error is captured in this field:"> + <Enum name="BIT_ERROR" start="0x0" description="Bit error" /> + <Enum name="FORM_ERROR" start="0x1" description="Form error" /> + <Enum name="STUFF_ERROR" start="0x2" description="Stuff error" /> + <Enum name="OTHER_ERROR" start="0x3" description="Other error" /> + </BitField> + <BitField start="24" size="8" name="ALCBIT" description="Each time arbitration is lost while trying to send on the CAN, the bit number within the frame is captured into this field. After the content of ALCBIT is read, the ALI bit is cleared and a new Arbitration Lost interrupt can occur. 00 = arbitration lost in the first bit (MS) of identifier ... 11 = arbitration lost in SRTS bit (RTR bit for standard frame messages) 12 = arbitration lost in IDE bit 13 = arbitration lost in 12th bit of identifier (extended frame only) ... 30 = arbitration lost in last bit of identifier (extended frame only) 31 = arbitration lost in RTR bit (extended frame only) On arbitration lost, the corresponding arbitration lost interrupt is forced, if enabled. At that time, the current bit position of the Bit Stream Processor is captured into the Arbitration Lost Capture Register. The content within this register is fixed until the user application has read out its contents once. From now on, the capture mechanism is activated again." /> + </Register> + <Register start="+0x010" size="4" name="IER" access="Read/Write" description="Interrupt Enable" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RIE" description="Receiver Interrupt Enable. When the Receive Buffer Status is 'full', the CAN Controller requests the respective interrupt." /> + <BitField start="1" size="1" name="TIE1" description="Transmit Interrupt Enable for Buffer1. When a message has been successfully transmitted out of TXB1 or Transmit Buffer 1 is accessible again (e.g. after an Abort Transmission command), the CAN Controller requests the respective interrupt." /> + <BitField start="2" size="1" name="EIE" description="Error Warning Interrupt Enable. If the Error or Bus Status change (see Status Register), the CAN Controller requests the respective interrupt." /> + <BitField start="3" size="1" name="DOIE" description="Data Overrun Interrupt Enable. If the Data Overrun Status bit is set (see Status Register), the CAN Controller requests the respective interrupt." /> + <BitField start="4" size="1" name="WUIE" description="Wake-Up Interrupt Enable. If the sleeping CAN controller wakes up, the respective interrupt is requested." /> + <BitField start="5" size="1" name="EPIE" description="Error Passive Interrupt Enable. If the error status of the CAN Controller changes from error active to error passive or vice versa, the respective interrupt is requested." /> + <BitField start="6" size="1" name="ALIE" description="Arbitration Lost Interrupt Enable. If the CAN Controller has lost arbitration, the respective interrupt is requested." /> + <BitField start="7" size="1" name="BEIE" description="Bus Error Interrupt Enable. If a bus error has been detected, the CAN Controller requests the respective interrupt." /> + <BitField start="8" size="1" name="IDIE" description="ID Ready Interrupt Enable. When a CAN identifier has been received, the CAN Controller requests the respective interrupt." /> + <BitField start="9" size="1" name="TIE2" description="Transmit Interrupt Enable for Buffer2. When a message has been successfully transmitted out of TXB2 or Transmit Buffer 2 is accessible again (e.g. after an Abort Transmission command), the CAN Controller requests the respective interrupt." /> + <BitField start="10" size="1" name="TIE3" description="Transmit Interrupt Enable for Buffer3. When a message has been successfully transmitted out of TXB3 or Transmit Buffer 3 is accessible again (e.g. after an Abort Transmission command), the CAN Controller requests the respective interrupt." /> + <BitField start="11" size="21" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x014" size="4" name="BTR" access="Read/Write" description="Bus Timing. Can only be written when RM in CANMOD is 1." reset_value="0x1C0000" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="10" name="BRP" description="Baud Rate Prescaler. The APB clock is divided by (this value plus one) to produce the CAN clock." /> + <BitField start="10" size="4" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="14" size="2" name="SJW" description="The Synchronization Jump Width is (this value plus one) CAN clocks." /> + <BitField start="16" size="4" name="TESG1" description="The delay from the nominal Sync point to the sample point is (this value plus one) CAN clocks." /> + <BitField start="20" size="3" name="TESG2" description="The delay from the sample point to the next nominal sync point is (this value plus one) CAN clocks. The nominal CAN bit time is (this value plus the value in TSEG1 plus 3) CAN clocks." /> + <BitField start="23" size="1" name="SAM" description="Sampling"> + <Enum name="THE_BUS_IS_SAMPLED_O" start="0" description="The bus is sampled once (recommended for high speed buses)" /> + <Enum name="THE_BUS_IS_SAMPLED_3" start="1" description="The bus is sampled 3 times (recommended for low to medium speed buses to filter spikes on the bus-line)" /> + </BitField> + <BitField start="24" size="8" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x018" size="4" name="EWL" access="Read/Write" description="Error Warning Limit. Can only be written when RM in CANMOD is 1." reset_value="0x60" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="EWL" description="During CAN operation, this value is compared to both the Tx and Rx Error Counters. If either of these counter matches this value, the Error Status (ES) bit in CANSR is set." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x01C" size="4" name="SR" access="ReadOnly" description="Status Register" reset_value="0x3C3C3C" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RBS_1" description="Receive Buffer Status. This bit is identical to the RBS bit in the CANxGSR." /> + <BitField start="1" size="1" name="DOS_1" description="Data Overrun Status. This bit is identical to the DOS bit in the CANxGSR." /> + <BitField start="2" size="1" name="TBS1_1" description="Transmit Buffer Status 1."> + <Enum name="LOCKED_SOFTWARE_CAN" start="0" description="Locked. Software cannot access the Tx Buffer 1 nor write to the corresponding CANxTFI, CANxTID, CANxTDA, and CANxTDB registers because a message is either waiting for transmission or is in transmitting process." /> + <Enum name="RELEASED_SOFTWARE_M" start="1" description="Released. Software may write a message into the Transmit Buffer 1 and its CANxTFI, CANxTID, CANxTDA, and CANxTDB registers." /> + </BitField> + <BitField start="3" size="1" name="TCS1_1" description="Transmission Complete Status."> + <Enum name="INCOMPLETE_THE_PREV" start="0" description="Incomplete. The previously requested transmission for Tx Buffer 1 is not complete." /> + <Enum name="COMPLETE_THE_PREVIO" start="1" description="Complete. The previously requested transmission for Tx Buffer 1 has been successfully completed." /> + </BitField> + <BitField start="4" size="1" name="RS_1" description="Receive Status. This bit is identical to the RS bit in the GSR." /> + <BitField start="5" size="1" name="TS1_1" description="Transmit Status 1."> + <Enum name="IDLE_THERE_IS_NO_TR" start="0" description="Idle. There is no transmission from Tx Buffer 1." /> + <Enum name="TRANSMIT_THE_CAN_CO" start="1" description="Transmit. The CAN Controller is transmitting a message from Tx Buffer 1." /> + </BitField> + <BitField start="6" size="1" name="ES_1" description="Error Status. This bit is identical to the ES bit in the CANxGSR." /> + <BitField start="7" size="1" name="BS_1" description="Bus Status. This bit is identical to the BS bit in the CANxGSR." /> + <BitField start="8" size="1" name="RBS_2" description="Receive Buffer Status. This bit is identical to the RBS bit in the CANxGSR." /> + <BitField start="9" size="1" name="DOS_2" description="Data Overrun Status. This bit is identical to the DOS bit in the CANxGSR." /> + <BitField start="10" size="1" name="TBS2_2" description="Transmit Buffer Status 2."> + <Enum name="LOCKED_SOFTWARE_CAN" start="0" description="Locked. Software cannot access the Tx Buffer 2 nor write to the corresponding CANxTFI, CANxTID, CANxTDA, and CANxTDB registers because a message is either waiting for transmission or is in transmitting process." /> + <Enum name="RELEASED_SOFTWARE_M" start="1" description="Released. Software may write a message into the Transmit Buffer 2 and its CANxTFI, CANxTID, CANxTDA, and CANxTDB registers." /> + </BitField> + <BitField start="11" size="1" name="TCS2_2" description="Transmission Complete Status."> + <Enum name="INCOMPLETE_THE_PREV" start="0" description="Incomplete. The previously requested transmission for Tx Buffer 2 is not complete." /> + <Enum name="COMPLETE_THE_PREVIO" start="1" description="Complete. The previously requested transmission for Tx Buffer 2 has been successfully completed." /> + </BitField> + <BitField start="12" size="1" name="RS_2" description="Receive Status. This bit is identical to the RS bit in the GSR." /> + <BitField start="13" size="1" name="TS2_2" description="Transmit Status 2."> + <Enum name="IDLE_THERE_IS_NO_TR" start="0" description="Idle. There is no transmission from Tx Buffer 2." /> + <Enum name="TRANSMIT_THE_CAN_CO" start="1" description="Transmit. The CAN Controller is transmitting a message from Tx Buffer 2." /> + </BitField> + <BitField start="14" size="1" name="ES_2" description="Error Status. This bit is identical to the ES bit in the CANxGSR." /> + <BitField start="15" size="1" name="BS_2" description="Bus Status. This bit is identical to the BS bit in the CANxGSR." /> + <BitField start="16" size="1" name="RBS_3" description="Receive Buffer Status. This bit is identical to the RBS bit in the CANxGSR." /> + <BitField start="17" size="1" name="DOS_3" description="Data Overrun Status. This bit is identical to the DOS bit in the CANxGSR." /> + <BitField start="18" size="1" name="TBS3_3" description="Transmit Buffer Status 3."> + <Enum name="LOCKED_SOFTWARE_CAN" start="0" description="Locked. Software cannot access the Tx Buffer 3 nor write to the corresponding CANxTFI, CANxTID, CANxTDA, and CANxTDB registers because a message is either waiting for transmission or is in transmitting process." /> + <Enum name="RELEASED_SOFTWARE_M" start="1" description="Released. Software may write a message into the Transmit Buffer 3 and its CANxTFI, CANxTID, CANxTDA, and CANxTDB registers." /> + </BitField> + <BitField start="19" size="1" name="TCS3_3" description="Transmission Complete Status."> + <Enum name="INCOMPLETE_THE_PREV" start="0" description="Incomplete. The previously requested transmission for Tx Buffer 3 is not complete." /> + <Enum name="COMPLETE_THE_PREVIO" start="1" description="Complete. The previously requested transmission for Tx Buffer 3 has been successfully completed." /> + </BitField> + <BitField start="20" size="1" name="RS_3" description="Receive Status. This bit is identical to the RS bit in the GSR." /> + <BitField start="21" size="1" name="TS3_3" description="Transmit Status 3."> + <Enum name="IDLE_THERE_IS_NO_TR" start="0" description="Idle. There is no transmission from Tx Buffer 3." /> + <Enum name="TRANSMIT_THE_CAN_CO" start="1" description="Transmit. The CAN Controller is transmitting a message from Tx Buffer 3." /> + </BitField> + <BitField start="22" size="1" name="ES_3" description="Error Status. This bit is identical to the ES bit in the CANxGSR." /> + <BitField start="23" size="1" name="BS_3" description="Bus Status. This bit is identical to the BS bit in the CANxGSR." /> + <BitField start="24" size="8" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x020" size="4" name="RFS" access="Read/Write" description="Receive frame status. Can only be written when RM in CANMOD is 1." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="10" name="IDINDEX" description="ID Index. If the BP bit (below) is 0, this value is the zero-based number of the Lookup Table RAM entry at which the Acceptance Filter matched the received Identifier. Disabled entries in the Standard tables are included in this numbering, but will not be matched. See Section 21.17 Examples of acceptance filter tables and ID index values on page 587 for examples of ID Index values." /> + <BitField start="10" size="1" name="BP" description="If this bit is 1, the current message was received in AF Bypass mode, and the ID Index field (above) is meaningless." /> + <BitField start="11" size="5" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + <BitField start="16" size="4" name="DLC" description="The field contains the Data Length Code (DLC) field of the current received message. When RTR = 0, this is related to the number of data bytes available in the CANRDA and CANRDB registers as follows: 0000-0111 = 0 to 7 bytes1000-1111 = 8 bytes With RTR = 1, this value indicates the number of data bytes requested to be sent back, with the same encoding." /> + <BitField start="20" size="10" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="30" size="1" name="RTR" description="This bit contains the Remote Transmission Request bit of the current received message. 0 indicates a Data Frame, in which (if DLC is non-zero) data can be read from the CANRDA and possibly the CANRDB registers. 1 indicates a Remote frame, in which case the DLC value identifies the number of data bytes requested to be sent using the same Identifier." /> + <BitField start="31" size="1" name="FF" description="A 0 in this bit indicates that the current received message included an 11-bit Identifier, while a 1 indicates a 29-bit Identifier. This affects the contents of the CANid register described below." /> + </Register> + <Register start="+0x024" size="4" name="RID" access="Read/Write" description="Received Identifier. Can only be written when RM in CANMOD is 1." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="11" name="ID" description="The 11-bit Identifier field of the current received message. In CAN 2.0A, these bits are called ID10-0, while in CAN 2.0B they're called ID29-18." /> + <BitField start="11" size="21" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x028" size="4" name="RDA" access="Read/Write" description="Received data bytes 1-4. Can only be written when RM in CANMOD is 1." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="DATA1" description="Data 1. If the DLC field in CANRFS >= 0001, this contains the first Data byte of the current received message." /> + <BitField start="8" size="8" name="DATA2" description="Data 2. If the DLC field in CANRFS >= 0010, this contains the first Data byte of the current received message." /> + <BitField start="16" size="8" name="DATA3" description="Data 3. If the DLC field in CANRFS >= 0011, this contains the first Data byte of the current received message." /> + <BitField start="24" size="8" name="DATA4" description="Data 4. If the DLC field in CANRFS >= 0100, this contains the first Data byte of the current received message." /> + </Register> + <Register start="+0x02C" size="4" name="RDB" access="Read/Write" description="Received data bytes 5-8. Can only be written when RM in CANMOD is 1." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="DATA5" description="Data 5. If the DLC field in CANRFS >= 0101, this contains the first Data byte of the current received message." /> + <BitField start="8" size="8" name="DATA6" description="Data 6. If the DLC field in CANRFS >= 0110, this contains the first Data byte of the current received message." /> + <BitField start="16" size="8" name="DATA7" description="Data 7. If the DLC field in CANRFS >= 0111, this contains the first Data byte of the current received message." /> + <BitField start="24" size="8" name="DATA8" description="Data 8. If the DLC field in CANRFS >= 1000, this contains the first Data byte of the current received message." /> + </Register> + <Register start="+0x030+0" size="4" name="TFI1" access="Read/Write" description="Transmit
frame info (Tx Buffer )" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="PRIO" description="If the TPM (Transmit Priority Mode) bit in the CANxMOD register is set to 1, enabled Tx Buffers contend for the right to send their messages based on this field. The buffer with the lowest TX Priority value wins the prioritization and is sent first." /> + <BitField start="8" size="8" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="16" size="4" name="DLC" description="Data Length Code. This value is sent in the DLC field of the next transmit message. In addition, if RTR = 0, this value controls the number of Data bytes sent in the next transmit message, from the CANxTDA and CANxTDB registers: 0000-0111 = 0-7 bytes 1xxx = 8 bytes" /> + <BitField start="20" size="10" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="30" size="1" name="RTR" description="This value is sent in the RTR bit of the next transmit message. If this bit is 0, the number of data bytes called out by the DLC field are sent from the CANxTDA and CANxTDB registers. If this bit is 1, a Remote Frame is sent, containing a request for that number of bytes." /> + <BitField start="31" size="1" name="FF" description="If this bit is 0, the next transmit message will be sent with an 11-bit Identifier (standard frame format), while if it's 1, the message will be sent with a 29-bit Identifier (extended frame format)." /> + </Register> + <Register start="+0x030+16" size="4" name="TFI2" access="Read/Write" description="Transmit
frame info (Tx Buffer )" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="PRIO" description="If the TPM (Transmit Priority Mode) bit in the CANxMOD register is set to 1, enabled Tx Buffers contend for the right to send their messages based on this field. The buffer with the lowest TX Priority value wins the prioritization and is sent first." /> + <BitField start="8" size="8" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="16" size="4" name="DLC" description="Data Length Code. This value is sent in the DLC field of the next transmit message. In addition, if RTR = 0, this value controls the number of Data bytes sent in the next transmit message, from the CANxTDA and CANxTDB registers: 0000-0111 = 0-7 bytes 1xxx = 8 bytes" /> + <BitField start="20" size="10" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="30" size="1" name="RTR" description="This value is sent in the RTR bit of the next transmit message. If this bit is 0, the number of data bytes called out by the DLC field are sent from the CANxTDA and CANxTDB registers. If this bit is 1, a Remote Frame is sent, containing a request for that number of bytes." /> + <BitField start="31" size="1" name="FF" description="If this bit is 0, the next transmit message will be sent with an 11-bit Identifier (standard frame format), while if it's 1, the message will be sent with a 29-bit Identifier (extended frame format)." /> + </Register> + <Register start="+0x030+32" size="4" name="TFI3" access="Read/Write" description="Transmit
frame info (Tx Buffer )" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="PRIO" description="If the TPM (Transmit Priority Mode) bit in the CANxMOD register is set to 1, enabled Tx Buffers contend for the right to send their messages based on this field. The buffer with the lowest TX Priority value wins the prioritization and is sent first." /> + <BitField start="8" size="8" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="16" size="4" name="DLC" description="Data Length Code. This value is sent in the DLC field of the next transmit message. In addition, if RTR = 0, this value controls the number of Data bytes sent in the next transmit message, from the CANxTDA and CANxTDB registers: 0000-0111 = 0-7 bytes 1xxx = 8 bytes" /> + <BitField start="20" size="10" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="30" size="1" name="RTR" description="This value is sent in the RTR bit of the next transmit message. If this bit is 0, the number of data bytes called out by the DLC field are sent from the CANxTDA and CANxTDB registers. If this bit is 1, a Remote Frame is sent, containing a request for that number of bytes." /> + <BitField start="31" size="1" name="FF" description="If this bit is 0, the next transmit message will be sent with an 11-bit Identifier (standard frame format), while if it's 1, the message will be sent with a 29-bit Identifier (extended frame format)." /> + </Register> + <Register start="+0x034+0" size="4" name="TID1" access="Read/Write" description="Transmit
Identifier (Tx Buffer)" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="11" name="ID" description="The 11-bit Identifier to be sent in the next transmit message." /> + <BitField start="11" size="21" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x034+16" size="4" name="TID2" access="Read/Write" description="Transmit
Identifier (Tx Buffer)" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="11" name="ID" description="The 11-bit Identifier to be sent in the next transmit message." /> + <BitField start="11" size="21" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x034+32" size="4" name="TID3" access="Read/Write" description="Transmit
Identifier (Tx Buffer)" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="11" name="ID" description="The 11-bit Identifier to be sent in the next transmit message." /> + <BitField start="11" size="21" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x038+0" size="4" name="TDA1" access="Read/Write" description="Transmit
data bytes 1-4 (Tx Buffer)" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="8" name="DATA1" description="Data 1. If RTR = 0 and DLC >= 0001 in the corresponding CANxTFI, this byte is sent as the first Data byte of the next transmit message." /> + <BitField start="8" size="8" name="DATA2" description="Data 2. If RTR = 0 and DLC >= 0010 in the corresponding CANxTFI, this byte is sent as the 2nd Data byte of the next transmit message." /> + <BitField start="16" size="8" name="DATA3" description="Data 3. If RTR = 0 and DLC >= 0011 in the corresponding CANxTFI, this byte is sent as the 3rd Data byte of the next transmit message." /> + <BitField start="24" size="8" name="DATA4" description="Data 4. If RTR = 0 and DLC >= 0100 in the corresponding CANxTFI, this byte is sent as the 4th Data byte of the next transmit message." /> + </Register> + <Register start="+0x038+16" size="4" name="TDA2" access="Read/Write" description="Transmit
data bytes 1-4 (Tx Buffer)" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="8" name="DATA1" description="Data 1. If RTR = 0 and DLC >= 0001 in the corresponding CANxTFI, this byte is sent as the first Data byte of the next transmit message." /> + <BitField start="8" size="8" name="DATA2" description="Data 2. If RTR = 0 and DLC >= 0010 in the corresponding CANxTFI, this byte is sent as the 2nd Data byte of the next transmit message." /> + <BitField start="16" size="8" name="DATA3" description="Data 3. If RTR = 0 and DLC >= 0011 in the corresponding CANxTFI, this byte is sent as the 3rd Data byte of the next transmit message." /> + <BitField start="24" size="8" name="DATA4" description="Data 4. If RTR = 0 and DLC >= 0100 in the corresponding CANxTFI, this byte is sent as the 4th Data byte of the next transmit message." /> + </Register> + <Register start="+0x038+32" size="4" name="TDA3" access="Read/Write" description="Transmit
data bytes 1-4 (Tx Buffer)" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="8" name="DATA1" description="Data 1. If RTR = 0 and DLC >= 0001 in the corresponding CANxTFI, this byte is sent as the first Data byte of the next transmit message." /> + <BitField start="8" size="8" name="DATA2" description="Data 2. If RTR = 0 and DLC >= 0010 in the corresponding CANxTFI, this byte is sent as the 2nd Data byte of the next transmit message." /> + <BitField start="16" size="8" name="DATA3" description="Data 3. If RTR = 0 and DLC >= 0011 in the corresponding CANxTFI, this byte is sent as the 3rd Data byte of the next transmit message." /> + <BitField start="24" size="8" name="DATA4" description="Data 4. If RTR = 0 and DLC >= 0100 in the corresponding CANxTFI, this byte is sent as the 4th Data byte of the next transmit message." /> + </Register> + <Register start="+0x03C+0" size="4" name="TDB1" access="Read/Write" description="Transmit
data bytes 5-8 (Tx Buffer )" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="8" name="DATA5" description="Data 5. If RTR = 0 and DLC >= 0101 in the corresponding CANTFI, this byte is sent as the 5th Data byte of the next transmit message." /> + <BitField start="8" size="8" name="DATA6" description="Data 6. If RTR = 0 and DLC >= 0110 in the corresponding CANTFI, this byte is sent as the 6th Data byte of the next transmit message." /> + <BitField start="16" size="8" name="DATA7" description="Data 7. If RTR = 0 and DLC >= 0111 in the corresponding CANTFI, this byte is sent as the 7th Data byte of the next transmit message." /> + <BitField start="24" size="8" name="DATA8" description="Data 8. If RTR = 0 and DLC >= 1000 in the corresponding CANTFI, this byte is sent as the 8th Data byte of the next transmit message." /> + </Register> + <Register start="+0x03C+16" size="4" name="TDB2" access="Read/Write" description="Transmit
data bytes 5-8 (Tx Buffer )" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="8" name="DATA5" description="Data 5. If RTR = 0 and DLC >= 0101 in the corresponding CANTFI, this byte is sent as the 5th Data byte of the next transmit message." /> + <BitField start="8" size="8" name="DATA6" description="Data 6. If RTR = 0 and DLC >= 0110 in the corresponding CANTFI, this byte is sent as the 6th Data byte of the next transmit message." /> + <BitField start="16" size="8" name="DATA7" description="Data 7. If RTR = 0 and DLC >= 0111 in the corresponding CANTFI, this byte is sent as the 7th Data byte of the next transmit message." /> + <BitField start="24" size="8" name="DATA8" description="Data 8. If RTR = 0 and DLC >= 1000 in the corresponding CANTFI, this byte is sent as the 8th Data byte of the next transmit message." /> + </Register> + <Register start="+0x03C+32" size="4" name="TDB3" access="Read/Write" description="Transmit
data bytes 5-8 (Tx Buffer )" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="8" name="DATA5" description="Data 5. If RTR = 0 and DLC >= 0101 in the corresponding CANTFI, this byte is sent as the 5th Data byte of the next transmit message." /> + <BitField start="8" size="8" name="DATA6" description="Data 6. If RTR = 0 and DLC >= 0110 in the corresponding CANTFI, this byte is sent as the 6th Data byte of the next transmit message." /> + <BitField start="16" size="8" name="DATA7" description="Data 7. If RTR = 0 and DLC >= 0111 in the corresponding CANTFI, this byte is sent as the 7th Data byte of the next transmit message." /> + <BitField start="24" size="8" name="DATA8" description="Data 8. If RTR = 0 and DLC >= 1000 in the corresponding CANTFI, this byte is sent as the 8th Data byte of the next transmit message." /> + </Register> + </RegisterGroup> + <RegisterGroup name="I2C1" start="0x4005C000" description="I2C bus interface"> + <Register start="+0x000" size="4" name="CONSET" access="Read/Write" description="I2C Control Set Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is set. Writing a zero has no effect on the corresponding bit in the I2C control register." reset_value="0x00" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + <BitField start="2" size="1" name="AA" description="Assert acknowledge flag." /> + <BitField start="3" size="1" name="SI" description="I2C interrupt flag." /> + <BitField start="4" size="1" name="STO" description="STOP flag." /> + <BitField start="5" size="1" name="STA" description="START flag." /> + <BitField start="6" size="1" name="I2EN" description="I2C interface enable." /> + <BitField start="7" size="25" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x004" size="4" name="STAT" access="ReadOnly" description="I2C Status Register. During I2C operation, this register provides detailed status codes that allow software to determine the next action needed." reset_value="0xF8" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="RESERVED" description="These bits are unused and are always 0." /> + <BitField start="3" size="5" name="Status" description="These bits give the actual status information about the I 2C interface." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x008" size="4" name="DAT" access="Read/Write" description="I2C Data Register. During master or slave transmit mode, data to be transmitted is written to this register. During master or slave receive mode, data that has been received may be read from this register." reset_value="0x00" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="Data" description="This register holds data values that have been received or are to be transmitted." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x00C" size="4" name="ADR0" access="Read/Write" description="I2C Slave Address Register 0. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="GC" description="General Call enable bit." /> + <BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x010" size="4" name="SCLH" access="Read/Write" description="SCH Duty Cycle Register High Half Word. Determines the high time of the I2C clock." reset_value="0x04" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="16" name="SCLH" description="Count for SCL HIGH time period selection." /> + <BitField start="16" size="16" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x014" size="4" name="SCLL" access="Read/Write" description="SCL Duty Cycle Register Low Half Word. Determines the low time of the I2C clock. SCLL and SCLH together determine the clock frequency generated by an I2C master and certain times used in slave mode." reset_value="0x04" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="16" name="SCLL" description="Count for SCL low time period selection." /> + <BitField start="16" size="16" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x018" size="4" name="CONCLR" access="WriteOnly" description="I2C Control Clear Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is cleared. Writing a zero has no effect on the corresponding bit in the I2C control register." reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="2" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + <BitField start="2" size="1" name="AAC" description="Assert acknowledge Clear bit." /> + <BitField start="3" size="1" name="SIC" description="I2C interrupt Clear bit." /> + <BitField start="4" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + <BitField start="5" size="1" name="STAC" description="START flag Clear bit." /> + <BitField start="6" size="1" name="I2ENC" description="I2C interface Disable bit." /> + <BitField start="7" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x01C" size="4" name="MMCTRL" access="Read/Write" description="Monitor mode control register." reset_value="0x00" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="MM_ENA" description="Monitor mode enable."> + <Enum name="MONITOR_MODE_DISABLE" start="0" description="Monitor mode disabled." /> + <Enum name="THE_I_2C_MODULE_WILL" start="1" description="The I 2C module will enter monitor mode. In this mode the SDA output will be forced high. This will prevent the I2C module from outputting data of any kind (including ACK) onto the I2C data bus. Depending on the state of the ENA_SCL bit, the output may be also forced high, preventing the module from having control over the I2C clock line." /> + </BitField> + <BitField start="1" size="1" name="ENA_SCL" description="SCL output enable."> + <Enum name="WHEN_THIS_BIT_IS_CLE" start="0" description="When this bit is cleared to 0, the SCL output will be forced high when the module is in monitor mode. As described above, this will prevent the module from having any control over the I2C clock line." /> + <Enum name="WHEN_THIS_BIT_IS_SET" start="1" description="When this bit is set, the I2C module may exercise the same control over the clock line that it would in normal operation. This means that, acting as a slave peripheral, the I2C module can stretch the clock line (hold it low) until it has had time to respond to an I2C interrupt.[1]" /> + </BitField> + <BitField start="2" size="1" name="MATCH_ALL" description="Select interrupt register match."> + <Enum name="WHEN_THIS_BIT_IS_CLE" start="0" description="When this bit is cleared, an interrupt will only be generated when a match occurs to one of the (up-to) four address registers described above. That is, the module will respond as a normal slave as far as address-recognition is concerned." /> + <Enum name="WHEN_THIS_BIT_IS_SET" start="1" description="When this bit is set to 1 and the I2C is in monitor mode, an interrupt will be generated on ANY address received. This will enable the part to monitor all traffic on the bus." /> + </BitField> + <BitField start="3" size="29" name="RESERVED" description="Reserved. The value read from reserved bits is not defined." /> + </Register> + <Register start="+0x020+0" size="4" name="ADR1" access="Read/Write" description="I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="GC" description="General Call enable bit." /> + <BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x020+4" size="4" name="ADR2" access="Read/Write" description="I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="GC" description="General Call enable bit." /> + <BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x020+8" size="4" name="ADR3" access="Read/Write" description="I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="GC" description="General Call enable bit." /> + <BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x02C" size="4" name="DATA_BUFFER" access="ReadOnly" description="Data buffer register. The contents of the 8 MSBs of the DAT shift register will be transferred to the DATA_BUFFER automatically after every nine bits (8 bits of data plus ACK or NACK) has been received on the bus." reset_value="0x00" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="Data" description="This register holds contents of the 8 MSBs of the DAT shift register." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x030+0" size="4" name="MASK[0]" access="Read/Write" description="I2C Slave address mask register" reset_value="0x00" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." /> + <BitField start="1" size="7" name="MASK" description="Mask bits." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x030+4" size="4" name="MASK[1]" access="Read/Write" description="I2C Slave address mask register" reset_value="0x00" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." /> + <BitField start="1" size="7" name="MASK" description="Mask bits." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x030+8" size="4" name="MASK[2]" access="Read/Write" description="I2C Slave address mask register" reset_value="0x00" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." /> + <BitField start="1" size="7" name="MASK" description="Mask bits." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x030+12" size="4" name="MASK[3]" access="Read/Write" description="I2C Slave address mask register" reset_value="0x00" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." /> + <BitField start="1" size="7" name="MASK" description="Mask bits." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + </RegisterGroup> + <RegisterGroup name="SSP0" start="0x40088000" description="SSP controller"> + <Register start="+0x000" size="4" name="CR0" access="Read/Write" description="Control Register 0. Selects the serial clock rate, bus type, and data size." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="4" name="DSS" description="Data Size Select. This field controls the number of bits transferred in each frame. Values 0000-0010 are not supported and should not be used."> + <Enum name="4_BIT_TRANSFER" start="0x3" description="4-bit transfer" /> + <Enum name="5_BIT_TRANSFER" start="0x4" description="5-bit transfer" /> + <Enum name="6_BIT_TRANSFER" start="0x5" description="6-bit transfer" /> + <Enum name="7_BIT_TRANSFER" start="0x6" description="7-bit transfer" /> + <Enum name="8_BIT_TRANSFER" start="0x7" description="8-bit transfer" /> + <Enum name="9_BIT_TRANSFER" start="0x8" description="9-bit transfer" /> + <Enum name="10_BIT_TRANSFER" start="0x9" description="10-bit transfer" /> + <Enum name="11_BIT_TRANSFER" start="0xA" description="11-bit transfer" /> + <Enum name="12_BIT_TRANSFER" start="0xB" description="12-bit transfer" /> + <Enum name="13_BIT_TRANSFER" start="0xC" description="13-bit transfer" /> + <Enum name="14_BIT_TRANSFER" start="0xD" description="14-bit transfer" /> + <Enum name="15_BIT_TRANSFER" start="0xE" description="15-bit transfer" /> + <Enum name="16_BIT_TRANSFER" start="0xF" description="16-bit transfer" /> + </BitField> + <BitField start="4" size="2" name="FRF" description="Frame Format."> + <Enum name="SPI" start="0x0" description="SPI" /> + <Enum name="TI" start="0x1" description="TI" /> + <Enum name="MICROWIRE" start="0x2" description="Microwire" /> + <Enum name="THIS_COMBINATION_IS_" start="0x3" description="This combination is not supported and should not be used." /> + </BitField> + <BitField start="6" size="1" name="CPOL" description="Clock Out Polarity. This bit is only used in SPI mode."> + <Enum name="BUS_LOW" start="0" description="SSP controller maintains the bus clock low between frames." /> + <Enum name="BUS_HIGH" start="1" description="SSP controller maintains the bus clock high between frames." /> + </BitField> + <BitField start="7" size="1" name="CPHA" description="Clock Out Phase. This bit is only used in SPI mode."> + <Enum name="FIRST_CLOCK" start="0" description="SSP controller captures serial data on the first clock transition of the frame, that is, the transition away from the inter-frame state of the clock line." /> + <Enum name="SECOND_CLOCK" start="1" description="SSP controller captures serial data on the second clock transition of the frame, that is, the transition back to the inter-frame state of the clock line." /> + </BitField> + <BitField start="8" size="8" name="SCR" description="Serial Clock Rate. The number of prescaler-output clocks per bit on the bus, minus one. Given that CPSDVSR is the prescale divider, and the APB clock PCLK clocks the prescaler, the bit frequency is PCLK / (CPSDVSR X [SCR+1])." /> + <BitField start="16" size="16" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x004" size="4" name="CR1" access="Read/Write" description="Control Register 1. Selects master/slave and other modes." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="LBM" description="Loop Back Mode."> + <Enum name="NORMAL" start="0" description="During normal operation." /> + <Enum name="OUPTU" start="1" description="Serial input is taken from the serial output (MOSI or MISO) rather than the serial input pin (MISO or MOSI respectively)." /> + </BitField> + <BitField start="1" size="1" name="SSE" description="SSP Enable."> + <Enum name="DISABLED" start="0" description="The SSP controller is disabled." /> + <Enum name="ENABLED" start="1" description="The SSP controller will interact with other devices on the serial bus. Software should write the appropriate control information to the other SSP registers and interrupt controller registers, before setting this bit." /> + </BitField> + <BitField start="2" size="1" name="MS" description="Master/Slave Mode.This bit can only be written when the SSE bit is 0."> + <Enum name="MASTER" start="0" description="The SSP controller acts as a master on the bus, driving the SCLK, MOSI, and SSEL lines and receiving the MISO line." /> + <Enum name="SLAVE" start="1" description="The SSP controller acts as a slave on the bus, driving MISO line and receiving SCLK, MOSI, and SSEL lines." /> + </BitField> + <BitField start="3" size="1" name="SOD" description="Slave Output Disable. This bit is relevant only in slave mode (MS = 1). If it is 1, this blocks this SSP controller from driving the transmit data line (MISO)." /> + <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x008" size="4" name="DR" access="None" description="Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="16" name="DATA" description="Write: software can write data to be sent in a future frame to this register whenever the TNF bit in the Status register is 1, indicating that the Tx FIFO is not full. If the Tx FIFO was previously empty and the SSP controller is not busy on the bus, transmission of the data will begin immediately. Otherwise the data written to this register will be sent as soon as all previous data has been sent (and received). If the data length is less than 16 bits, software must right-justify the data written to this register. Read: software can read data from this register whenever the RNE bit in the Status register is 1, indicating that the Rx FIFO is not empty. When software reads this register, the SSP controller returns data from the least recent frame in the Rx FIFO. If the data length is less than 16 bits, the data is right-justified in this field with higher order bits filled with 0s." /> + <BitField start="16" size="16" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x00C" size="4" name="SR" access="ReadOnly" description="Status Register" reset_value="0x00000003" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="TFE" description="Transmit FIFO Empty. This bit is 1 is the Transmit FIFO is empty, 0 if not." /> + <BitField start="1" size="1" name="TNF" description="Transmit FIFO Not Full. This bit is 0 if the Tx FIFO is full, 1 if not." /> + <BitField start="2" size="1" name="RNE" description="Receive FIFO Not Empty. This bit is 0 if the Receive FIFO is empty, 1 if not." /> + <BitField start="3" size="1" name="RFF" description="Receive FIFO Full. This bit is 1 if the Receive FIFO is full, 0 if not." /> + <BitField start="4" size="1" name="BSY" description="Busy. This bit is 0 if the SSPn controller is idle, or 1 if it is currently sending/receiving a frame and/or the Tx FIFO is not empty." /> + <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x010" size="4" name="CPSR" access="Read/Write" description="Clock Prescale Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="CPSDVSR" description="This even value between 2 and 254, by which PCLK is divided to yield the prescaler output clock. Bit 0 always reads as 0." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x014" size="4" name="IMSC" access="Read/Write" description="Interrupt Mask Set and Clear Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RORIM" description="Software should set this bit to enable interrupt when a Receive Overrun occurs, that is, when the Rx FIFO is full and another frame is completely received. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs." /> + <BitField start="1" size="1" name="RTIM" description="Software should set this bit to enable interrupt when a Receive Time-out condition occurs. A Receive Time-out occurs when the Rx FIFO is not empty, and no has not been read for a time-out period. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1])." /> + <BitField start="2" size="1" name="RXIM" description="Software should set this bit to enable interrupt when the Rx FIFO is at least half full." /> + <BitField start="3" size="1" name="TXIM" description="Software should set this bit to enable interrupt when the Tx FIFO is at least half empty." /> + <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x018" size="4" name="RIS" access="ReadOnly" description="Raw Interrupt Status Register" reset_value="0x00000008" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RORRIS" description="This bit is 1 if another frame was completely received while the RxFIFO was full. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs." /> + <BitField start="1" size="1" name="RTRIS" description="This bit is 1 if the Rx FIFO is not empty, and has not been read for a time-out period. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1])." /> + <BitField start="2" size="1" name="RXRIS" description="This bit is 1 if the Rx FIFO is at least half full." /> + <BitField start="3" size="1" name="TXRIS" description="This bit is 1 if the Tx FIFO is at least half empty." /> + <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x01C" size="4" name="MIS" access="ReadOnly" description="Masked Interrupt Status Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RORMIS" description="This bit is 1 if another frame was completely received while the RxFIFO was full, and this interrupt is enabled." /> + <BitField start="1" size="1" name="RTMIS" description="This bit is 1 if the Rx FIFO is not empty, has not been read for a time-out period, and this interrupt is enabled. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1])." /> + <BitField start="2" size="1" name="RXMIS" description="This bit is 1 if the Rx FIFO is at least half full, and this interrupt is enabled." /> + <BitField start="3" size="1" name="TXMIS" description="This bit is 1 if the Tx FIFO is at least half empty, and this interrupt is enabled." /> + <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x020" size="4" name="ICR" access="WriteOnly" description="SSPICR Interrupt Clear Register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="RORIC" description="Writing a 1 to this bit clears the frame was received when RxFIFO was full interrupt." /> + <BitField start="1" size="1" name="RTIC" description="Writing a 1 to this bit clears the Rx FIFO was not empty and has not been read for a time-out period interrupt. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR / [SCR+1])." /> + <BitField start="2" size="30" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x024" size="4" name="DMACR" access="Read/Write" description="SSP0 DMA control register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RXDMAE" description="Receive DMA Enable. When this bit is set to one 1, DMA for the receive FIFO is enabled, otherwise receive DMA is disabled." /> + <BitField start="1" size="1" name="TXDMAE" description="Transmit DMA Enable. When this bit is set to one 1, DMA for the transmit FIFO is enabled, otherwise transmit DMA is disabled" /> + <BitField start="2" size="30" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + </RegisterGroup> + <RegisterGroup name="DAC" start="0x4008C000" description=" Digital-to-Analog Converter (DAC) "> + <Register start="+0x000" size="4" name="CR" access="Read/Write" description="D/A Converter Register. This register contains the digital value to be converted to analog and a power control bit." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="6" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="6" size="10" name="VALUE" description="After the selected settling time after this field is written with a new VALUE, the voltage on the DAC_OUT pin (with respect to VSSA) is VALUE x ((VREFP - V REFN)/1024) + VREFN." /> + <BitField start="16" size="1" name="BIAS" description="Settling time The settling times noted in the description of the BIAS bit are valid for a capacitance load on the DAC_OUT pin not exceeding 100 pF. A load impedance value greater than that value will cause settling time longer than the specified time. One or more graphs of load impedance vs. settling time will be included in the final data sheet."> + <Enum name="FAST" start="0" description="The settling time of the DAC is 1 us max, and the maximum current is 700 uA. This allows a maximum update rate of 1 MHz." /> + <Enum name="SLOW" start="1" description="The settling time of the DAC is 2.5 us and the maximum current is 350 uA. This allows a maximum update rate of 400 kHz." /> + </BitField> + <BitField start="17" size="15" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x004" size="4" name="CTRL" access="Read/Write" description="DAC Control register. This register controls DMA and timer operation." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="INT_DMA_REQ" description="DMA interrupt request"> + <Enum name="CLEAR_ON_ANY_WRITE_T" start="0" description="Clear on any write to the DACR register." /> + <Enum name="SET_BY_HARDWARE_WHEN" start="1" description="Set by hardware when the timer times out." /> + </BitField> + <BitField start="1" size="1" name="DBLBUF_ENA" description="Double buffering"> + <Enum name="DISABLE" start="0" description="Disable" /> + <Enum name="ENABLE_WHEN_THIS_BI" start="1" description="Enable. When this bit and the CNT_ENA bit are both set, the double-buffering feature in the DACR register will be enabled. Writes to the DACR register are written to a pre-buffer and then transferred to the DACR on the next time-out of the counter." /> + </BitField> + <BitField start="2" size="1" name="CNT_ENA" description="Time-out counter operation"> + <Enum name="DISABLE" start="0" description="Disable" /> + <Enum name="ENABLE" start="1" description="Enable" /> + </BitField> + <BitField start="3" size="1" name="DMA_ENA" description="DMA access"> + <Enum name="DISABLE" start="0" description="Disable" /> + <Enum name="ENABLE_DMA_BURST_RE" start="1" description="Enable. DMA Burst Request Input 7 is enabled for the DAC (see Table 672)." /> + </BitField> + <BitField start="4" size="28" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x008" size="4" name="CNTVAL" access="Read/Write" description="DAC Counter Value register. This register contains the reload value for the DAC DMA/Interrupt timer." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="16" name="VALUE" description="16-bit reload value for the DAC interrupt/DMA timer." /> + <BitField start="16" size="16" name="RESERVED" description="Reserved" /> + </Register> + </RegisterGroup> + <RegisterGroup name="TIMER2" start="0x40090000" description="Timer0/1/2/3 "> + <Register start="+0x000" size="4" name="IR" access="Read/Write" description="Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="MR0INT" description="Interrupt flag for match channel 0." /> + <BitField start="1" size="1" name="MR1INT" description="Interrupt flag for match channel 1." /> + <BitField start="2" size="1" name="MR2INT" description="Interrupt flag for match channel 2." /> + <BitField start="3" size="1" name="MR3INT" description="Interrupt flag for match channel 3." /> + <BitField start="4" size="1" name="CR0INT" description="Interrupt flag for capture channel 0 event." /> + <BitField start="5" size="1" name="CR1INT" description="Interrupt flag for capture channel 1 event." /> + <BitField start="6" size="26" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x004" size="4" name="TCR" access="Read/Write" description="Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="CEN" description="When one, the Timer Counter and Prescale Counter are enabled for counting. When zero, the counters are disabled." /> + <BitField start="1" size="1" name="CRST" description="When one, the Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero." /> + <BitField start="2" size="30" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x008" size="4" name="TC" access="Read/Write" description="Timer Counter. The 32 bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="TC" description="Timer counter value." /> + </Register> + <Register start="+0x00C" size="4" name="PR" access="Read/Write" description="Prescale Register. When the Prescale Counter (PC) is equal to this value, the next clock increments the TC and clears the PC." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="PM" description="Prescale counter maximum value." /> + </Register> + <Register start="+0x010" size="4" name="PC" access="Read/Write" description="Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="PC" description="Prescale counter value." /> + </Register> + <Register start="+0x014" size="4" name="MCR" access="Read/Write" description="Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="MR0I" description="Interrupt on MR0"> + <Enum name="INTERRUPT_IS_GENERAT" start="1" description="Interrupt is generated when MR0 matches the value in the TC." /> + <Enum name="INTERRUPT_IS_DISABLE" start="0" description="Interrupt is disabled" /> + </BitField> + <BitField start="1" size="1" name="MR0R" description="Reset on MR0"> + <Enum name="TC_WILL_BE_RESET_IF_" start="1" description="TC will be reset if MR0 matches it." /> + <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." /> + </BitField> + <BitField start="2" size="1" name="MR0S" description="Stop on MR0"> + <Enum name="TC_AND_PC_WILL_BE_ST" start="1" description="TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC." /> + <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." /> + </BitField> + <BitField start="3" size="1" name="MR1I" description="Interrupt on MR1"> + <Enum name="INTERRUPT_IS_GENERAT" start="1" description="Interrupt is generated when MR1 matches the value in the TC." /> + <Enum name="INTERRUPT_IS_DISABLE" start="0" description="Interrupt is disabled." /> + </BitField> + <BitField start="4" size="1" name="MR1R" description="Reset on MR1"> + <Enum name="TC_WILL_BE_RESET_IF_" start="1" description="TC will be reset if MR1 matches it." /> + <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." /> + </BitField> + <BitField start="5" size="1" name="MR1S" description="Stop on MR1"> + <Enum name="TC_AND_PC_WILL_BE_ST" start="1" description="TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC." /> + <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." /> + </BitField> + <BitField start="6" size="1" name="MR2I" description="Interrupt on MR2"> + <Enum name="INTERRUPT_IS_GENERAT" start="1" description="Interrupt is generated when MR2 matches the value in the TC." /> + <Enum name="INTERRUPT_IS_DISABLE" start="0" description="Interrupt is disabled" /> + </BitField> + <BitField start="7" size="1" name="MR2R" description="Reset on MR2"> + <Enum name="TC_WILL_BE_RESET_IF_" start="1" description="TC will be reset if MR2 matches it." /> + <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." /> + </BitField> + <BitField start="8" size="1" name="MR2S" description="Stop on MR2."> + <Enum name="TC_AND_PC_WILL_BE_ST" start="1" description="TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC" /> + <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." /> + </BitField> + <BitField start="9" size="1" name="MR3I" description="Interrupt on MR3"> + <Enum name="INTERRUPT_IS_GENERAT" start="1" description="Interrupt is generated when MR3 matches the value in the TC." /> + <Enum name="THIS_INTERRUPT_IS_DI" start="0" description="This interrupt is disabled" /> + </BitField> + <BitField start="10" size="1" name="MR3R" description="Reset on MR3"> + <Enum name="TC_WILL_BE_RESET_IF_" start="1" description="TC will be reset if MR3 matches it." /> + <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." /> + </BitField> + <BitField start="11" size="1" name="MR3S" description="Stop on MR3"> + <Enum name="TC_AND_PC_WILL_BE_ST" start="1" description="TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC." /> + <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." /> + </BitField> + <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x018+0" size="4" name="MR[0]" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="MATCH" description="Timer counter match value." /> + </Register> + <Register start="+0x018+4" size="4" name="MR[1]" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="MATCH" description="Timer counter match value." /> + </Register> + <Register start="+0x018+8" size="4" name="MR[2]" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="MATCH" description="Timer counter match value." /> + </Register> + <Register start="+0x018+12" size="4" name="MR[3]" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="MATCH" description="Timer counter match value." /> + </Register> + <Register start="+0x028" size="4" name="CCR" access="Read/Write" description="Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="CAP0RE" description="Capture on CAPn.0 rising edge"> + <Enum name="ENABLE" start="1" description="A sequence of 0 then 1 on CAPn.0 will cause CR0 to be loaded with the contents of TC." /> + <Enum name="DISABLE" start="0" description="This feature is disabled." /> + </BitField> + <BitField start="1" size="1" name="CAP0FE" description="Capture on CAPn.0 falling edge"> + <Enum name="ENABLE" start="1" description="A sequence of 1 then 0 on CAPn.0 will cause CR0 to be loaded with the contents of TC." /> + <Enum name="DISABLE" start="0" description="This feature is disabled." /> + </BitField> + <BitField start="2" size="1" name="CAP0I" description="Interrupt on CAPn.0 event"> + <Enum name="ENABLE" start="1" description="A CR0 load due to a CAPn.0 event will generate an interrupt." /> + <Enum name="DISABLE" start="0" description="This feature is disabled." /> + </BitField> + <BitField start="3" size="1" name="CAP1RE" description="Capture on CAPn.1 rising edge"> + <Enum name="ENABLE" start="1" description="A sequence of 0 then 1 on CAPn.1 will cause CR1 to be loaded with the contents of TC." /> + <Enum name="DISABLE" start="0" description="This feature is disabled." /> + </BitField> + <BitField start="4" size="1" name="CAP1FE" description="Capture on CAPn.1 falling edge"> + <Enum name="ENABLE" start="1" description="A sequence of 1 then 0 on CAPn.1 will cause CR1 to be loaded with the contents of TC." /> + <Enum name="DISABLE" start="0" description="This feature is disabled." /> + </BitField> + <BitField start="5" size="1" name="CAP1I" description="Interrupt on CAPn.1 event"> + <Enum name="ENABLE" start="1" description="A CR1 load due to a CAPn.1 event will generate an interrupt." /> + <Enum name="DISABLE" start="0" description="This feature is disabled." /> + </BitField> + <BitField start="6" size="26" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x02C+0" size="4" name="CR[0]" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CAP" description="Timer counter capture value." /> + </Register> + <Register start="+0x02C+4" size="4" name="CR[1]" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CAP" description="Timer counter capture value." /> + </Register> + <Register start="+0x03C" size="4" name="EMR" access="Read/Write" description="External Match Register. The EMR controls the external match pins." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="EM0" description="External Match 0. When a match occurs between the TC and MR0, this bit can either toggle, go low, go high, or do nothing, depending on bits 5:4 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." /> + <BitField start="1" size="1" name="EM1" description="External Match 1. When a match occurs between the TC and MR1, this bit can either toggle, go low, go high, or do nothing, depending on bits 7:6 of this register. This bit can be driven onto a MATn.1 pin, in a positive-logic manner (0 = low, 1 = high)." /> + <BitField start="2" size="1" name="EM2" description="External Match 2. When a match occurs between the TC and MR2, this bit can either toggle, go low, go high, or do nothing, depending on bits 9:8 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." /> + <BitField start="3" size="1" name="EM3" description="External Match 3. When a match occurs between the TC and MR3, this bit can either toggle, go low, go high, or do nothing, depending on bits 11:10 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." /> + <BitField start="4" size="2" name="EMC0" description="External Match Control 0. Determines the functionality of External Match 0."> + <Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." /> + <Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." /> + <Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." /> + <Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." /> + </BitField> + <BitField start="6" size="2" name="EMC1" description="External Match Control 1. Determines the functionality of External Match 1."> + <Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." /> + <Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." /> + <Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." /> + <Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." /> + </BitField> + <BitField start="8" size="2" name="EMC2" description="External Match Control 2. Determines the functionality of External Match 2."> + <Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." /> + <Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." /> + <Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." /> + <Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." /> + </BitField> + <BitField start="10" size="2" name="EMC3" description="External Match Control 3. Determines the functionality of External Match 3."> + <Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." /> + <Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." /> + <Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." /> + <Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." /> + </BitField> + <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x070" size="4" name="CTCR" access="Read/Write" description="Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="CTMODE" description="Counter/Timer Mode This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale Register."> + <Enum name="TIMER_MODE_EVERY_RI" start="0x0" description="Timer Mode: every rising PCLK edge" /> + <Enum name="RISING" start="0x1" description="Counter Mode: TC is incremented on rising edges on the CAP input selected by bits 3:2." /> + <Enum name="FALLING" start="0x2" description="Counter Mode: TC is incremented on falling edges on the CAP input selected by bits 3:2." /> + <Enum name="DUALEDGE" start="0x3" description="Counter Mode: TC is incremented on both edges on the CAP input selected by bits 3:2." /> + </BitField> + <BitField start="2" size="2" name="CINSEL" description="Count Input Select When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the TnCTCR, the 3 bits for that input in the Capture Control Register (TnCCR) must be programmed as 000. However, capture and/or interrupt can be selected for the other 3 CAPn inputs in the same timer."> + <Enum name="CAPN_0_FOR_TIMERN" start="0x0" description="CAPn.0 for TIMERn" /> + <Enum name="CAPN_1_FOR_TIMERN" start="0x1" description="CAPn.1 for TIMERn" /> + </BitField> + <BitField start="4" size="28" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + </RegisterGroup> + <RegisterGroup name="TIMER3" start="0x40094000" description="Timer0/1/2/3 "> + <Register start="+0x000" size="4" name="IR" access="Read/Write" description="Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="MR0INT" description="Interrupt flag for match channel 0." /> + <BitField start="1" size="1" name="MR1INT" description="Interrupt flag for match channel 1." /> + <BitField start="2" size="1" name="MR2INT" description="Interrupt flag for match channel 2." /> + <BitField start="3" size="1" name="MR3INT" description="Interrupt flag for match channel 3." /> + <BitField start="4" size="1" name="CR0INT" description="Interrupt flag for capture channel 0 event." /> + <BitField start="5" size="1" name="CR1INT" description="Interrupt flag for capture channel 1 event." /> + <BitField start="6" size="26" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x004" size="4" name="TCR" access="Read/Write" description="Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="CEN" description="When one, the Timer Counter and Prescale Counter are enabled for counting. When zero, the counters are disabled." /> + <BitField start="1" size="1" name="CRST" description="When one, the Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero." /> + <BitField start="2" size="30" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x008" size="4" name="TC" access="Read/Write" description="Timer Counter. The 32 bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="TC" description="Timer counter value." /> + </Register> + <Register start="+0x00C" size="4" name="PR" access="Read/Write" description="Prescale Register. When the Prescale Counter (PC) is equal to this value, the next clock increments the TC and clears the PC." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="PM" description="Prescale counter maximum value." /> + </Register> + <Register start="+0x010" size="4" name="PC" access="Read/Write" description="Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="PC" description="Prescale counter value." /> + </Register> + <Register start="+0x014" size="4" name="MCR" access="Read/Write" description="Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="MR0I" description="Interrupt on MR0"> + <Enum name="INTERRUPT_IS_GENERAT" start="1" description="Interrupt is generated when MR0 matches the value in the TC." /> + <Enum name="INTERRUPT_IS_DISABLE" start="0" description="Interrupt is disabled" /> + </BitField> + <BitField start="1" size="1" name="MR0R" description="Reset on MR0"> + <Enum name="TC_WILL_BE_RESET_IF_" start="1" description="TC will be reset if MR0 matches it." /> + <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." /> + </BitField> + <BitField start="2" size="1" name="MR0S" description="Stop on MR0"> + <Enum name="TC_AND_PC_WILL_BE_ST" start="1" description="TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC." /> + <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." /> + </BitField> + <BitField start="3" size="1" name="MR1I" description="Interrupt on MR1"> + <Enum name="INTERRUPT_IS_GENERAT" start="1" description="Interrupt is generated when MR1 matches the value in the TC." /> + <Enum name="INTERRUPT_IS_DISABLE" start="0" description="Interrupt is disabled." /> + </BitField> + <BitField start="4" size="1" name="MR1R" description="Reset on MR1"> + <Enum name="TC_WILL_BE_RESET_IF_" start="1" description="TC will be reset if MR1 matches it." /> + <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." /> + </BitField> + <BitField start="5" size="1" name="MR1S" description="Stop on MR1"> + <Enum name="TC_AND_PC_WILL_BE_ST" start="1" description="TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC." /> + <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." /> + </BitField> + <BitField start="6" size="1" name="MR2I" description="Interrupt on MR2"> + <Enum name="INTERRUPT_IS_GENERAT" start="1" description="Interrupt is generated when MR2 matches the value in the TC." /> + <Enum name="INTERRUPT_IS_DISABLE" start="0" description="Interrupt is disabled" /> + </BitField> + <BitField start="7" size="1" name="MR2R" description="Reset on MR2"> + <Enum name="TC_WILL_BE_RESET_IF_" start="1" description="TC will be reset if MR2 matches it." /> + <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." /> + </BitField> + <BitField start="8" size="1" name="MR2S" description="Stop on MR2."> + <Enum name="TC_AND_PC_WILL_BE_ST" start="1" description="TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC" /> + <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." /> + </BitField> + <BitField start="9" size="1" name="MR3I" description="Interrupt on MR3"> + <Enum name="INTERRUPT_IS_GENERAT" start="1" description="Interrupt is generated when MR3 matches the value in the TC." /> + <Enum name="THIS_INTERRUPT_IS_DI" start="0" description="This interrupt is disabled" /> + </BitField> + <BitField start="10" size="1" name="MR3R" description="Reset on MR3"> + <Enum name="TC_WILL_BE_RESET_IF_" start="1" description="TC will be reset if MR3 matches it." /> + <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." /> + </BitField> + <BitField start="11" size="1" name="MR3S" description="Stop on MR3"> + <Enum name="TC_AND_PC_WILL_BE_ST" start="1" description="TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC." /> + <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." /> + </BitField> + <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x018+0" size="4" name="MR[0]" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="MATCH" description="Timer counter match value." /> + </Register> + <Register start="+0x018+4" size="4" name="MR[1]" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="MATCH" description="Timer counter match value." /> + </Register> + <Register start="+0x018+8" size="4" name="MR[2]" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="MATCH" description="Timer counter match value." /> + </Register> + <Register start="+0x018+12" size="4" name="MR[3]" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="MATCH" description="Timer counter match value." /> + </Register> + <Register start="+0x028" size="4" name="CCR" access="Read/Write" description="Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="CAP0RE" description="Capture on CAPn.0 rising edge"> + <Enum name="ENABLE" start="1" description="A sequence of 0 then 1 on CAPn.0 will cause CR0 to be loaded with the contents of TC." /> + <Enum name="DISABLE" start="0" description="This feature is disabled." /> + </BitField> + <BitField start="1" size="1" name="CAP0FE" description="Capture on CAPn.0 falling edge"> + <Enum name="ENABLE" start="1" description="A sequence of 1 then 0 on CAPn.0 will cause CR0 to be loaded with the contents of TC." /> + <Enum name="DISABLE" start="0" description="This feature is disabled." /> + </BitField> + <BitField start="2" size="1" name="CAP0I" description="Interrupt on CAPn.0 event"> + <Enum name="ENABLE" start="1" description="A CR0 load due to a CAPn.0 event will generate an interrupt." /> + <Enum name="DISABLE" start="0" description="This feature is disabled." /> + </BitField> + <BitField start="3" size="1" name="CAP1RE" description="Capture on CAPn.1 rising edge"> + <Enum name="ENABLE" start="1" description="A sequence of 0 then 1 on CAPn.1 will cause CR1 to be loaded with the contents of TC." /> + <Enum name="DISABLE" start="0" description="This feature is disabled." /> + </BitField> + <BitField start="4" size="1" name="CAP1FE" description="Capture on CAPn.1 falling edge"> + <Enum name="ENABLE" start="1" description="A sequence of 1 then 0 on CAPn.1 will cause CR1 to be loaded with the contents of TC." /> + <Enum name="DISABLE" start="0" description="This feature is disabled." /> + </BitField> + <BitField start="5" size="1" name="CAP1I" description="Interrupt on CAPn.1 event"> + <Enum name="ENABLE" start="1" description="A CR1 load due to a CAPn.1 event will generate an interrupt." /> + <Enum name="DISABLE" start="0" description="This feature is disabled." /> + </BitField> + <BitField start="6" size="26" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x02C+0" size="4" name="CR[0]" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CAP" description="Timer counter capture value." /> + </Register> + <Register start="+0x02C+4" size="4" name="CR[1]" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CAP" description="Timer counter capture value." /> + </Register> + <Register start="+0x03C" size="4" name="EMR" access="Read/Write" description="External Match Register. The EMR controls the external match pins." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="EM0" description="External Match 0. When a match occurs between the TC and MR0, this bit can either toggle, go low, go high, or do nothing, depending on bits 5:4 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." /> + <BitField start="1" size="1" name="EM1" description="External Match 1. When a match occurs between the TC and MR1, this bit can either toggle, go low, go high, or do nothing, depending on bits 7:6 of this register. This bit can be driven onto a MATn.1 pin, in a positive-logic manner (0 = low, 1 = high)." /> + <BitField start="2" size="1" name="EM2" description="External Match 2. When a match occurs between the TC and MR2, this bit can either toggle, go low, go high, or do nothing, depending on bits 9:8 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." /> + <BitField start="3" size="1" name="EM3" description="External Match 3. When a match occurs between the TC and MR3, this bit can either toggle, go low, go high, or do nothing, depending on bits 11:10 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." /> + <BitField start="4" size="2" name="EMC0" description="External Match Control 0. Determines the functionality of External Match 0."> + <Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." /> + <Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." /> + <Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." /> + <Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." /> + </BitField> + <BitField start="6" size="2" name="EMC1" description="External Match Control 1. Determines the functionality of External Match 1."> + <Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." /> + <Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." /> + <Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." /> + <Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." /> + </BitField> + <BitField start="8" size="2" name="EMC2" description="External Match Control 2. Determines the functionality of External Match 2."> + <Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." /> + <Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." /> + <Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." /> + <Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." /> + </BitField> + <BitField start="10" size="2" name="EMC3" description="External Match Control 3. Determines the functionality of External Match 3."> + <Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." /> + <Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." /> + <Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." /> + <Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." /> + </BitField> + <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x070" size="4" name="CTCR" access="Read/Write" description="Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="CTMODE" description="Counter/Timer Mode This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale Register."> + <Enum name="TIMER_MODE_EVERY_RI" start="0x0" description="Timer Mode: every rising PCLK edge" /> + <Enum name="RISING" start="0x1" description="Counter Mode: TC is incremented on rising edges on the CAP input selected by bits 3:2." /> + <Enum name="FALLING" start="0x2" description="Counter Mode: TC is incremented on falling edges on the CAP input selected by bits 3:2." /> + <Enum name="DUALEDGE" start="0x3" description="Counter Mode: TC is incremented on both edges on the CAP input selected by bits 3:2." /> + </BitField> + <BitField start="2" size="2" name="CINSEL" description="Count Input Select When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the TnCTCR, the 3 bits for that input in the Capture Control Register (TnCCR) must be programmed as 000. However, capture and/or interrupt can be selected for the other 3 CAPn inputs in the same timer."> + <Enum name="CAPN_0_FOR_TIMERN" start="0x0" description="CAPn.0 for TIMERn" /> + <Enum name="CAPN_1_FOR_TIMERN" start="0x1" description="CAPn.1 for TIMERn" /> + </BitField> + <BitField start="4" size="28" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + </RegisterGroup> + <RegisterGroup name="UART2" start="0x40098000" description="UART0/2/3 "> + <Register start="+0x000" size="4" name="RBR" access="None" description="Receiver Buffer Register. Contains the next received character to be read (DLAB =0)." reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="8" name="RBR" description="The UARTn Receiver Buffer Register contains the oldest received byte in the UARTn Rx FIFO." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x000" size="4" name="THR" access="WriteOnly" description="Transmit Holding Regiter. The next character to be transmitted is written here (DLAB =0)." reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="8" name="THR" description="Writing to the UARTn Transmit Holding Register causes the data to be stored in the UARTn transmit FIFO. The byte will be sent when it reaches the bottom of the FIFO and the transmitter is available." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x000" size="4" name="DLL" access="Read/Write" description="Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB =1)." reset_value="0x01" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="DLLSB" description="The UARTn Divisor Latch LSB Register, along with the UnDLM register, determines the baud rate of the UARTn." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x004" size="4" name="DLM" access="Read/Write" description="Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB =1)." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="DLMSB" description="The UARTn Divisor Latch MSB Register, along with the U0DLL register, determines the baud rate of the UARTn." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x004" size="4" name="IER" access="Read/Write" description="Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential UART interrupts (DLAB =0)." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RBRIE" description="RBR Interrupt Enable. Enables the Receive Data Available interrupt for UARTn. It also controls the Character Receive Time-out interrupt."> + <Enum name="DISABLE_THE_RDA_INTE" start="0" description="Disable the RDA interrupts." /> + <Enum name="ENABLE_THE_RDA_INTER" start="1" description="Enable the RDA interrupts." /> + </BitField> + <BitField start="1" size="1" name="THREIE" description="THRE Interrupt Enable. Enables the THRE interrupt for UARTn. The status of this can be read from UnLSR[5]."> + <Enum name="DISABLE_THE_THRE_INT" start="0" description="Disable the THRE interrupts." /> + <Enum name="ENABLE_THE_THRE_INTE" start="1" description="Enable the THRE interrupts." /> + </BitField> + <BitField start="2" size="1" name="RXIE" description="RX Line Status Interrupt Enable. Enables the UARTn RX line status interrupts. The status of this interrupt can be read from UnLSR[4:1]."> + <Enum name="DISABLE_THE_RX_LINE_" start="0" description="Disable the RX line status interrupts." /> + <Enum name="ENABLE_THE_RX_LINE_S" start="1" description="Enable the RX line status interrupts." /> + </BitField> + <BitField start="3" size="5" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="8" size="1" name="ABEOINTEN" description="Enables the end of auto-baud interrupt."> + <Enum name="DISABLE_END_OF_AUTO_" start="0" description="Disable end of auto-baud Interrupt." /> + <Enum name="ENABLE_END_OF_AUTO_B" start="1" description="Enable end of auto-baud Interrupt." /> + </BitField> + <BitField start="9" size="1" name="ABTOINTEN" description="Enables the auto-baud time-out interrupt."> + <Enum name="DISABLE_AUTO_BAUD_TI" start="0" description="Disable auto-baud time-out Interrupt." /> + <Enum name="ENABLE_AUTO_BAUD_TIM" start="1" description="Enable auto-baud time-out Interrupt." /> + </BitField> + <BitField start="10" size="22" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x008" size="4" name="IIR" access="ReadOnly" description="Interrupt ID Register. Identifies which interrupt(s) are pending." reset_value="0x01" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="INTSTATUS" description="Interrupt status. Note that UnIIR[0] is active low. The pending interrupt can be determined by evaluating UnIIR[3:1]."> + <Enum name="AT_LEAST_ONE_INTERRU" start="0" description="At least one interrupt is pending." /> + <Enum name="NO_INTERRUPT_IS_PEND" start="1" description="No interrupt is pending." /> + </BitField> + <BitField start="1" size="3" name="INTID" description="Interrupt identification. UnIER[3:1] identifies an interrupt corresponding to the UARTn Rx or TX FIFO. All other combinations of UnIER[3:1] not listed below are reserved (000,100,101,111)."> + <Enum name="1_RECEIVE_LINE_S" start="0x3" description="1 - Receive Line Status (RLS)." /> + <Enum name="2A__RECEIVE_DATA_AV" start="0x2" description="2a - Receive Data Available (RDA)." /> + <Enum name="2B__CHARACTER_TIME_" start="0x6" description="2b - Character Time-out Indicator (CTI)." /> + <Enum name="3_THRE_INTERRUPT" start="0x1" description="3 - THRE Interrupt" /> + </BitField> + <BitField start="4" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="6" size="2" name="FIFOENABLE" description="Copies of UnFCR[0]." /> + <BitField start="8" size="1" name="ABEOINT" description="End of auto-baud interrupt. True if auto-baud has finished successfully and interrupt is enabled." /> + <BitField start="9" size="1" name="ABTOINT" description="Auto-baud time-out interrupt. True if auto-baud has timed out and interrupt is enabled." /> + <BitField start="10" size="22" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x008" size="4" name="FCR" access="WriteOnly" description="FIFO Control Register. Controls UART FIFO usage and modes." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="FIFOEN" description="FIFO Enable."> + <Enum name="UARTN_FIFOS_ARE_DISA" start="0" description="UARTn FIFOs are disabled. Must not be used in the application." /> + <Enum name="ACTIVE_HIGH_ENABLE_F" start="1" description="Active high enable for both UARTn Rx and TX FIFOs and UnFCR[7:1] access. This bit must be set for proper UART operation. Any transition on this bit will automatically clear the related UART FIFOs." /> + </BitField> + <BitField start="1" size="1" name="RXFIFORES" description="RX FIFO Reset."> + <Enum name="NO_IMPACT_ON_EITHER_" start="0" description="No impact on either of UARTn FIFOs." /> + <Enum name="WRITING_A_LOGIC_1_TO" start="1" description="Writing a logic 1 to UnFCR[1] will clear all bytes in UARTn Rx FIFO, reset the pointer logic. This bit is self-clearing." /> + </BitField> + <BitField start="2" size="1" name="TXFIFORES" description="TX FIFO Reset."> + <Enum name="NO_IMPACT_ON_EITHER_" start="0" description="No impact on either of UARTn FIFOs." /> + <Enum name="WRITING_A_LOGIC_1_TO" start="1" description="Writing a logic 1 to UnFCR[2] will clear all bytes in UARTn TX FIFO, reset the pointer logic. This bit is self-clearing." /> + </BitField> + <BitField start="3" size="1" name="DMAMODE" description="DMA Mode Select. When the FIFO enable (bit 0 of this register) is set, this bit selects the DMA mode. See Section 18.6.6.1." /> + <BitField start="4" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="6" size="2" name="RXTRIGLVL" description="RX Trigger Level. These two bits determine how many receiver UARTn FIFO characters must be written before an interrupt or DMA request is activated."> + <Enum name="TRIGGER_LEVEL_0_1_C" start="0x0" description="Trigger level 0 (1 character or 0x01)." /> + <Enum name="TRIGGER_LEVEL_1_4_C" start="0x1" description="Trigger level 1 (4 characters or 0x04)." /> + <Enum name="TRIGGER_LEVEL_2_8_C" start="0x2" description="Trigger level 2 (8 characters or 0x08)." /> + <Enum name="TRIGGER_LEVEL_3_14_" start="0x3" description="Trigger level 3 (14 characters or 0x0E)." /> + </BitField> + <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x00C" size="4" name="LCR" access="Read/Write" description="Line Control Register. Contains controls for frame formatting and break generation." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="WLS" description="Word Length Select."> + <Enum name="5_BIT_CHARACTER_LENG" start="0x0" description="5-bit character length" /> + <Enum name="6_BIT_CHARACTER_LENG" start="0x1" description="6-bit character length" /> + <Enum name="7_BIT_CHARACTER_LENG" start="0x2" description="7-bit character length" /> + <Enum name="8_BIT_CHARACTER_LENG" start="0x3" description="8-bit character length" /> + </BitField> + <BitField start="2" size="1" name="SBS" description="Stop Bit Select"> + <Enum name="1_STOP_BIT_" start="0" description="1 stop bit." /> + <Enum name="2_STOP_BITS_1_5_IF_" start="1" description="2 stop bits (1.5 if UnLCR[1:0]=00)." /> + </BitField> + <BitField start="3" size="1" name="PE" description="Parity Enable."> + <Enum name="DISABLE_PARITY_GENER" start="0" description="Disable parity generation and checking." /> + <Enum name="ENABLE_PARITY_GENERA" start="1" description="Enable parity generation and checking." /> + </BitField> + <BitField start="4" size="2" name="PS" description="Parity Select"> + <Enum name="ODD_PARITY_NUMBER_O" start="0x0" description="Odd parity. Number of 1s in the transmitted character and the attached parity bit will be odd." /> + <Enum name="EVEN_PARITY_NUMBER_" start="0x1" description="Even Parity. Number of 1s in the transmitted character and the attached parity bit will be even." /> + <Enum name="FORCED_1_STICK_PARIT" start="0x2" description="Forced 1 stick parity." /> + <Enum name="FORCED_0_STICK_PARIT" start="0x3" description="Forced 0 stick parity." /> + </BitField> + <BitField start="6" size="1" name="BC" description="Break Control"> + <Enum name="DISABLE_BREAK_TRANSM" start="0" description="Disable break transmission." /> + <Enum name="ENABLE_BREAK_TRANSMI" start="1" description="Enable break transmission. Output pin UARTn TXD is forced to logic 0 when UnLCR[6] is active high." /> + </BitField> + <BitField start="7" size="1" name="DLAB" description="Divisor Latch Access Bit"> + <Enum name="DISABLE_ACCESS_TO_DI" start="0" description="Disable access to Divisor Latches." /> + <Enum name="ENABLE_ACCESS_TO_DIV" start="1" description="Enable access to Divisor Latches." /> + </BitField> + <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x014" size="4" name="LSR" access="None" description="Line Status Register. Contains flags for transmit and receive status, including line errors." reset_value="0x60" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RDR" description="Receiver Data Ready. UnLSR[0] is set when the UnRBR holds an unread character and is cleared when the UARTn RBR FIFO is empty."> + <Enum name="EMPTY" start="0" description="The UARTn receiver FIFO is empty." /> + <Enum name="NOTEMPTY" start="1" description="The UARTn receiver FIFO is not empty." /> + </BitField> + <BitField start="1" size="1" name="OE" description="Overrun Error. The overrun error condition is set as soon as it occurs. An UnLSR read clears UnLSR[1]. UnLSR[1] is set when UARTn RSR has a new character assembled and the UARTn RBR FIFO is full. In this case, the UARTn RBR FIFO will not be overwritten and the character in the UARTn RSR will be lost."> + <Enum name="INACTIVE" start="0" description="Overrun error status is inactive." /> + <Enum name="ACTIVE" start="1" description="Overrun error status is active." /> + </BitField> + <BitField start="2" size="1" name="PE" description="Parity Error. When the parity bit of a received character is in the wrong state, a parity error occurs. An UnLSR read clears UnLSR[2]. Time of parity error detection is dependent on UnFCR[0]. Note: A parity error is associated with the character at the top of the UARTn RBR FIFO."> + <Enum name="INACTIVE" start="0" description="Parity error status is inactive." /> + <Enum name="ACTIVE" start="1" description="Parity error status is active." /> + </BitField> + <BitField start="3" size="1" name="FE" description="Framing Error. When the stop bit of a received character is a logic 0, a framing error occurs. An UnLSR read clears UnLSR[3]. The time of the framing error detection is dependent on UnFCR[0]. Upon detection of a framing error, the Rx will attempt to resynchronize to the data and assume that the bad stop bit is actually an early start bit. However, it cannot be assumed that the next received byte will be correct even if there is no Framing Error. Note: A framing error is associated with the character at the top of the UARTn RBR FIFO."> + <Enum name="INACTIVE" start="0" description="Framing error status is inactive." /> + <Enum name="ACTIVE" start="1" description="Framing error status is active." /> + </BitField> + <BitField start="4" size="1" name="BI" description="Break Interrupt. When RXDn is held in the spacing state (all zeroes) for one full character transmission (start, data, parity, stop), a break interrupt occurs. Once the break condition has been detected, the receiver goes idle until RXDn goes to marking state (all ones). An UnLSR read clears this status bit. The time of break detection is dependent on UnFCR[0]. Note: The break interrupt is associated with the character at the top of the UARTn RBR FIFO."> + <Enum name="INACTIVE" start="0" description="Break interrupt status is inactive." /> + <Enum name="ACTIVE" start="1" description="Break interrupt status is active." /> + </BitField> + <BitField start="5" size="1" name="THRE" description="Transmitter Holding Register Empty. THRE is set immediately upon detection of an empty UARTn THR and is cleared on a UnTHR write."> + <Enum name="VALIDDATA" start="0" description="UnTHR contains valid data." /> + <Enum name="EMPTY" start="1" description="UnTHR is empty." /> + </BitField> + <BitField start="6" size="1" name="TEMT" description="Transmitter Empty. TEMT is set when both UnTHR and UnTSR are empty; TEMT is cleared when either the UnTSR or the UnTHR contain valid data."> + <Enum name="VALIDDATA" start="0" description="UnTHR and/or the UnTSR contains valid data." /> + <Enum name="EMPTY" start="1" description="UnTHR and the UnTSR are empty." /> + </BitField> + <BitField start="7" size="1" name="RXFE" description="Error in RX FIFO . UnLSR[7] is set when a character with a Rx error such as framing error, parity error or break interrupt, is loaded into the UnRBR. This bit is cleared when the UnLSR register is read and there are no subsequent errors in the UARTn FIFO."> + <Enum name="NOERROR" start="0" description="UnRBR contains no UARTn RX errors or UnFCR[0]=0." /> + <Enum name="ERRORS" start="1" description="UARTn RBR contains at least one UARTn RX error." /> + </BitField> + <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x01C" size="4" name="SCR" access="Read/Write" description="Scratch Pad Register. 8-bit temporary storage for software." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="PAD" description="A readable, writable byte." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x020" size="4" name="ACR" access="Read/Write" description="Auto-baud Control Register. Contains controls for the auto-baud feature." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="START" description="Start bit. This bit is automatically cleared after auto-baud completion."> + <Enum name="AUTO_BAUD_STOP_AUTO" start="0" description="Auto-baud stop (auto-baud is not running)." /> + <Enum name="AUTO_BAUD_START_AUT" start="1" description="Auto-baud start (auto-baud is running). Auto-baud run bit. This bit is automatically cleared after auto-baud completion." /> + </BitField> + <BitField start="1" size="1" name="MODE" description="Auto-baud mode select bit."> + <Enum name="MODE_0_" start="0" description="Mode 0." /> + <Enum name="MODE_1_" start="1" description="Mode 1." /> + </BitField> + <BitField start="2" size="1" name="AUTORESTART" description="Restart bit."> + <Enum name="NO_RESTART_" start="0" description="No restart." /> + <Enum name="RESTART_IN_CASE_OF_T" start="1" description="Restart in case of time-out (counter restarts at next UARTn Rx falling edge)" /> + </BitField> + <BitField start="3" size="5" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="8" size="1" name="ABEOINTCLR" description="End of auto-baud interrupt clear bit (write-only accessible). Writing a 1 will clear the corresponding interrupt in the UnIIR. Writing a 0 has no impact."> + <Enum name="NO_IMPACT_" start="0" description="No impact." /> + <Enum name="CLEAR_THE_CORRESPOND" start="1" description="Clear the corresponding interrupt in the IIR." /> + </BitField> + <BitField start="9" size="1" name="ABTOINTCLR" description="Auto-baud time-out interrupt clear bit (write-only accessible). Writing a 1 will clear the corresponding interrupt in the UnIIR. Writing a 0 has no impact."> + <Enum name="NO_IMPACT_" start="0" description="No impact." /> + <Enum name="CLEAR_THE_CORRESPOND" start="1" description="Clear the corresponding interrupt in the IIR." /> + </BitField> + <BitField start="10" size="22" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x028" size="4" name="FDR" access="Read/Write" description="Fractional Divider Register. Generates a clock input for the baud rate divider." reset_value="0x10" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="4" name="DIVADDVAL" description="Baud-rate generation pre-scaler divisor value. If this field is 0, fractional baud-rate generator will not impact the UARTn baudrate." /> + <BitField start="4" size="4" name="MULVAL" description="Baud-rate pre-scaler multiplier value. This field must be greater or equal 1 for UARTn to operate properly, regardless of whether the fractional baud-rate generator is used or not." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x030" size="4" name="TER" access="Read/Write" description="Transmit Enable Register. Turns off UART transmitter for use with software flow control." reset_value="0x80" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="7" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="7" size="1" name="TXEN" description="When this bit is 1, as it is after a Reset, data written to the THR is output on the TXD pin as soon as any preceding data has been sent. If this bit is cleared to 0 while a character is being sent, the transmission of that character is completed, but no further characters are sent until this bit is set again. In other words, a 0 in this bit blocks the transfer of characters from the THR or TX FIFO into the transmit shift register. Software implementing software-handshaking can clear this bit when it receives an XOFF character (DC3). Software can set this bit again when it receives an XON (DC1) character." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x04C" size="4" name="RS485CTRL" access="Read/Write" description="RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="NMMEN" description="NMM enable."> + <Enum name="DISABLED" start="0" description="RS-485/EIA-485 Normal Multidrop Mode (NMM) is disabled." /> + <Enum name="ENABLED" start="1" description="RS-485/EIA-485 Normal Multidrop Mode (NMM) is enabled. In this mode, an address is detected when a received byte has the parity bit = 1, generating a received data interrupt. See Section 18.6.16 RS-485/EIA-485 modes of operation." /> + </BitField> + <BitField start="1" size="1" name="RXDIS" description="Receiver enable."> + <Enum name="ENABLED" start="0" description="The receiver is enabled." /> + <Enum name="DISABLED" start="1" description="The receiver is disabled." /> + </BitField> + <BitField start="2" size="1" name="AADEN" description="AAD enable."> + <Enum name="DISABLED" start="0" description="Auto Address Detect (AAD) is disabled." /> + <Enum name="ENABLED" start="1" description="Auto Address Detect (AAD) is enabled." /> + </BitField> + <BitField start="3" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="4" size="1" name="DCTRL" description="Direction control enable."> + <Enum name="DISABLE_AUTO_DIRECTI" start="0" description="Disable Auto Direction Control." /> + <Enum name="ENABLE_AUTO_DIRECTIO" start="1" description="Enable Auto Direction Control." /> + </BitField> + <BitField start="5" size="1" name="OINV" description="Direction control pin polarity. This bit reverses the polarity of the direction control signal on the Un_OE pin."> + <Enum name="DIRLOW" start="0" description="The direction control pin will be driven to logic 0 when the transmitter has data to be sent. It will be driven to logic 1 after the last bit of data has been transmitted." /> + <Enum name="DIRHIGH" start="1" description="The direction control pin will be driven to logic 1 when the transmitter has data to be sent. It will be driven to logic 0 after the last bit of data has been transmitted." /> + </BitField> + <BitField start="6" size="26" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x050" size="4" name="RS485ADRMATCH" access="Read/Write" description="RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="ADRMATCH" description="Contains the address match value." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x054" size="4" name="RS485DLY" access="Read/Write" description="RS-485/EIA-485 direction control delay." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="DLY" description="Contains the direction control (UnOE) delay value. This register works in conjunction with an 8-bit counter." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + </RegisterGroup> + <RegisterGroup name="UART3" start="0x4009C000" description="UART0/2/3 "> + <Register start="+0x000" size="4" name="RBR" access="None" description="Receiver Buffer Register. Contains the next received character to be read (DLAB =0)." reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="8" name="RBR" description="The UARTn Receiver Buffer Register contains the oldest received byte in the UARTn Rx FIFO." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x000" size="4" name="THR" access="WriteOnly" description="Transmit Holding Regiter. The next character to be transmitted is written here (DLAB =0)." reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="8" name="THR" description="Writing to the UARTn Transmit Holding Register causes the data to be stored in the UARTn transmit FIFO. The byte will be sent when it reaches the bottom of the FIFO and the transmitter is available." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x000" size="4" name="DLL" access="Read/Write" description="Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB =1)." reset_value="0x01" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="DLLSB" description="The UARTn Divisor Latch LSB Register, along with the UnDLM register, determines the baud rate of the UARTn." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x004" size="4" name="DLM" access="Read/Write" description="Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB =1)." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="DLMSB" description="The UARTn Divisor Latch MSB Register, along with the U0DLL register, determines the baud rate of the UARTn." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x004" size="4" name="IER" access="Read/Write" description="Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential UART interrupts (DLAB =0)." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RBRIE" description="RBR Interrupt Enable. Enables the Receive Data Available interrupt for UARTn. It also controls the Character Receive Time-out interrupt."> + <Enum name="DISABLE_THE_RDA_INTE" start="0" description="Disable the RDA interrupts." /> + <Enum name="ENABLE_THE_RDA_INTER" start="1" description="Enable the RDA interrupts." /> + </BitField> + <BitField start="1" size="1" name="THREIE" description="THRE Interrupt Enable. Enables the THRE interrupt for UARTn. The status of this can be read from UnLSR[5]."> + <Enum name="DISABLE_THE_THRE_INT" start="0" description="Disable the THRE interrupts." /> + <Enum name="ENABLE_THE_THRE_INTE" start="1" description="Enable the THRE interrupts." /> + </BitField> + <BitField start="2" size="1" name="RXIE" description="RX Line Status Interrupt Enable. Enables the UARTn RX line status interrupts. The status of this interrupt can be read from UnLSR[4:1]."> + <Enum name="DISABLE_THE_RX_LINE_" start="0" description="Disable the RX line status interrupts." /> + <Enum name="ENABLE_THE_RX_LINE_S" start="1" description="Enable the RX line status interrupts." /> + </BitField> + <BitField start="3" size="5" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="8" size="1" name="ABEOINTEN" description="Enables the end of auto-baud interrupt."> + <Enum name="DISABLE_END_OF_AUTO_" start="0" description="Disable end of auto-baud Interrupt." /> + <Enum name="ENABLE_END_OF_AUTO_B" start="1" description="Enable end of auto-baud Interrupt." /> + </BitField> + <BitField start="9" size="1" name="ABTOINTEN" description="Enables the auto-baud time-out interrupt."> + <Enum name="DISABLE_AUTO_BAUD_TI" start="0" description="Disable auto-baud time-out Interrupt." /> + <Enum name="ENABLE_AUTO_BAUD_TIM" start="1" description="Enable auto-baud time-out Interrupt." /> + </BitField> + <BitField start="10" size="22" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x008" size="4" name="IIR" access="ReadOnly" description="Interrupt ID Register. Identifies which interrupt(s) are pending." reset_value="0x01" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="INTSTATUS" description="Interrupt status. Note that UnIIR[0] is active low. The pending interrupt can be determined by evaluating UnIIR[3:1]."> + <Enum name="AT_LEAST_ONE_INTERRU" start="0" description="At least one interrupt is pending." /> + <Enum name="NO_INTERRUPT_IS_PEND" start="1" description="No interrupt is pending." /> + </BitField> + <BitField start="1" size="3" name="INTID" description="Interrupt identification. UnIER[3:1] identifies an interrupt corresponding to the UARTn Rx or TX FIFO. All other combinations of UnIER[3:1] not listed below are reserved (000,100,101,111)."> + <Enum name="1_RECEIVE_LINE_S" start="0x3" description="1 - Receive Line Status (RLS)." /> + <Enum name="2A__RECEIVE_DATA_AV" start="0x2" description="2a - Receive Data Available (RDA)." /> + <Enum name="2B__CHARACTER_TIME_" start="0x6" description="2b - Character Time-out Indicator (CTI)." /> + <Enum name="3_THRE_INTERRUPT" start="0x1" description="3 - THRE Interrupt" /> + </BitField> + <BitField start="4" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="6" size="2" name="FIFOENABLE" description="Copies of UnFCR[0]." /> + <BitField start="8" size="1" name="ABEOINT" description="End of auto-baud interrupt. True if auto-baud has finished successfully and interrupt is enabled." /> + <BitField start="9" size="1" name="ABTOINT" description="Auto-baud time-out interrupt. True if auto-baud has timed out and interrupt is enabled." /> + <BitField start="10" size="22" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x008" size="4" name="FCR" access="WriteOnly" description="FIFO Control Register. Controls UART FIFO usage and modes." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="FIFOEN" description="FIFO Enable."> + <Enum name="UARTN_FIFOS_ARE_DISA" start="0" description="UARTn FIFOs are disabled. Must not be used in the application." /> + <Enum name="ACTIVE_HIGH_ENABLE_F" start="1" description="Active high enable for both UARTn Rx and TX FIFOs and UnFCR[7:1] access. This bit must be set for proper UART operation. Any transition on this bit will automatically clear the related UART FIFOs." /> + </BitField> + <BitField start="1" size="1" name="RXFIFORES" description="RX FIFO Reset."> + <Enum name="NO_IMPACT_ON_EITHER_" start="0" description="No impact on either of UARTn FIFOs." /> + <Enum name="WRITING_A_LOGIC_1_TO" start="1" description="Writing a logic 1 to UnFCR[1] will clear all bytes in UARTn Rx FIFO, reset the pointer logic. This bit is self-clearing." /> + </BitField> + <BitField start="2" size="1" name="TXFIFORES" description="TX FIFO Reset."> + <Enum name="NO_IMPACT_ON_EITHER_" start="0" description="No impact on either of UARTn FIFOs." /> + <Enum name="WRITING_A_LOGIC_1_TO" start="1" description="Writing a logic 1 to UnFCR[2] will clear all bytes in UARTn TX FIFO, reset the pointer logic. This bit is self-clearing." /> + </BitField> + <BitField start="3" size="1" name="DMAMODE" description="DMA Mode Select. When the FIFO enable (bit 0 of this register) is set, this bit selects the DMA mode. See Section 18.6.6.1." /> + <BitField start="4" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="6" size="2" name="RXTRIGLVL" description="RX Trigger Level. These two bits determine how many receiver UARTn FIFO characters must be written before an interrupt or DMA request is activated."> + <Enum name="TRIGGER_LEVEL_0_1_C" start="0x0" description="Trigger level 0 (1 character or 0x01)." /> + <Enum name="TRIGGER_LEVEL_1_4_C" start="0x1" description="Trigger level 1 (4 characters or 0x04)." /> + <Enum name="TRIGGER_LEVEL_2_8_C" start="0x2" description="Trigger level 2 (8 characters or 0x08)." /> + <Enum name="TRIGGER_LEVEL_3_14_" start="0x3" description="Trigger level 3 (14 characters or 0x0E)." /> + </BitField> + <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x00C" size="4" name="LCR" access="Read/Write" description="Line Control Register. Contains controls for frame formatting and break generation." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="WLS" description="Word Length Select."> + <Enum name="5_BIT_CHARACTER_LENG" start="0x0" description="5-bit character length" /> + <Enum name="6_BIT_CHARACTER_LENG" start="0x1" description="6-bit character length" /> + <Enum name="7_BIT_CHARACTER_LENG" start="0x2" description="7-bit character length" /> + <Enum name="8_BIT_CHARACTER_LENG" start="0x3" description="8-bit character length" /> + </BitField> + <BitField start="2" size="1" name="SBS" description="Stop Bit Select"> + <Enum name="1_STOP_BIT_" start="0" description="1 stop bit." /> + <Enum name="2_STOP_BITS_1_5_IF_" start="1" description="2 stop bits (1.5 if UnLCR[1:0]=00)." /> + </BitField> + <BitField start="3" size="1" name="PE" description="Parity Enable."> + <Enum name="DISABLE_PARITY_GENER" start="0" description="Disable parity generation and checking." /> + <Enum name="ENABLE_PARITY_GENERA" start="1" description="Enable parity generation and checking." /> + </BitField> + <BitField start="4" size="2" name="PS" description="Parity Select"> + <Enum name="ODD_PARITY_NUMBER_O" start="0x0" description="Odd parity. Number of 1s in the transmitted character and the attached parity bit will be odd." /> + <Enum name="EVEN_PARITY_NUMBER_" start="0x1" description="Even Parity. Number of 1s in the transmitted character and the attached parity bit will be even." /> + <Enum name="FORCED_1_STICK_PARIT" start="0x2" description="Forced 1 stick parity." /> + <Enum name="FORCED_0_STICK_PARIT" start="0x3" description="Forced 0 stick parity." /> + </BitField> + <BitField start="6" size="1" name="BC" description="Break Control"> + <Enum name="DISABLE_BREAK_TRANSM" start="0" description="Disable break transmission." /> + <Enum name="ENABLE_BREAK_TRANSMI" start="1" description="Enable break transmission. Output pin UARTn TXD is forced to logic 0 when UnLCR[6] is active high." /> + </BitField> + <BitField start="7" size="1" name="DLAB" description="Divisor Latch Access Bit"> + <Enum name="DISABLE_ACCESS_TO_DI" start="0" description="Disable access to Divisor Latches." /> + <Enum name="ENABLE_ACCESS_TO_DIV" start="1" description="Enable access to Divisor Latches." /> + </BitField> + <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x014" size="4" name="LSR" access="None" description="Line Status Register. Contains flags for transmit and receive status, including line errors." reset_value="0x60" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RDR" description="Receiver Data Ready. UnLSR[0] is set when the UnRBR holds an unread character and is cleared when the UARTn RBR FIFO is empty."> + <Enum name="EMPTY" start="0" description="The UARTn receiver FIFO is empty." /> + <Enum name="NOTEMPTY" start="1" description="The UARTn receiver FIFO is not empty." /> + </BitField> + <BitField start="1" size="1" name="OE" description="Overrun Error. The overrun error condition is set as soon as it occurs. An UnLSR read clears UnLSR[1]. UnLSR[1] is set when UARTn RSR has a new character assembled and the UARTn RBR FIFO is full. In this case, the UARTn RBR FIFO will not be overwritten and the character in the UARTn RSR will be lost."> + <Enum name="INACTIVE" start="0" description="Overrun error status is inactive." /> + <Enum name="ACTIVE" start="1" description="Overrun error status is active." /> + </BitField> + <BitField start="2" size="1" name="PE" description="Parity Error. When the parity bit of a received character is in the wrong state, a parity error occurs. An UnLSR read clears UnLSR[2]. Time of parity error detection is dependent on UnFCR[0]. Note: A parity error is associated with the character at the top of the UARTn RBR FIFO."> + <Enum name="INACTIVE" start="0" description="Parity error status is inactive." /> + <Enum name="ACTIVE" start="1" description="Parity error status is active." /> + </BitField> + <BitField start="3" size="1" name="FE" description="Framing Error. When the stop bit of a received character is a logic 0, a framing error occurs. An UnLSR read clears UnLSR[3]. The time of the framing error detection is dependent on UnFCR[0]. Upon detection of a framing error, the Rx will attempt to resynchronize to the data and assume that the bad stop bit is actually an early start bit. However, it cannot be assumed that the next received byte will be correct even if there is no Framing Error. Note: A framing error is associated with the character at the top of the UARTn RBR FIFO."> + <Enum name="INACTIVE" start="0" description="Framing error status is inactive." /> + <Enum name="ACTIVE" start="1" description="Framing error status is active." /> + </BitField> + <BitField start="4" size="1" name="BI" description="Break Interrupt. When RXDn is held in the spacing state (all zeroes) for one full character transmission (start, data, parity, stop), a break interrupt occurs. Once the break condition has been detected, the receiver goes idle until RXDn goes to marking state (all ones). An UnLSR read clears this status bit. The time of break detection is dependent on UnFCR[0]. Note: The break interrupt is associated with the character at the top of the UARTn RBR FIFO."> + <Enum name="INACTIVE" start="0" description="Break interrupt status is inactive." /> + <Enum name="ACTIVE" start="1" description="Break interrupt status is active." /> + </BitField> + <BitField start="5" size="1" name="THRE" description="Transmitter Holding Register Empty. THRE is set immediately upon detection of an empty UARTn THR and is cleared on a UnTHR write."> + <Enum name="VALIDDATA" start="0" description="UnTHR contains valid data." /> + <Enum name="EMPTY" start="1" description="UnTHR is empty." /> + </BitField> + <BitField start="6" size="1" name="TEMT" description="Transmitter Empty. TEMT is set when both UnTHR and UnTSR are empty; TEMT is cleared when either the UnTSR or the UnTHR contain valid data."> + <Enum name="VALIDDATA" start="0" description="UnTHR and/or the UnTSR contains valid data." /> + <Enum name="EMPTY" start="1" description="UnTHR and the UnTSR are empty." /> + </BitField> + <BitField start="7" size="1" name="RXFE" description="Error in RX FIFO . UnLSR[7] is set when a character with a Rx error such as framing error, parity error or break interrupt, is loaded into the UnRBR. This bit is cleared when the UnLSR register is read and there are no subsequent errors in the UARTn FIFO."> + <Enum name="NOERROR" start="0" description="UnRBR contains no UARTn RX errors or UnFCR[0]=0." /> + <Enum name="ERRORS" start="1" description="UARTn RBR contains at least one UARTn RX error." /> + </BitField> + <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x01C" size="4" name="SCR" access="Read/Write" description="Scratch Pad Register. 8-bit temporary storage for software." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="PAD" description="A readable, writable byte." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x020" size="4" name="ACR" access="Read/Write" description="Auto-baud Control Register. Contains controls for the auto-baud feature." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="START" description="Start bit. This bit is automatically cleared after auto-baud completion."> + <Enum name="AUTO_BAUD_STOP_AUTO" start="0" description="Auto-baud stop (auto-baud is not running)." /> + <Enum name="AUTO_BAUD_START_AUT" start="1" description="Auto-baud start (auto-baud is running). Auto-baud run bit. This bit is automatically cleared after auto-baud completion." /> + </BitField> + <BitField start="1" size="1" name="MODE" description="Auto-baud mode select bit."> + <Enum name="MODE_0_" start="0" description="Mode 0." /> + <Enum name="MODE_1_" start="1" description="Mode 1." /> + </BitField> + <BitField start="2" size="1" name="AUTORESTART" description="Restart bit."> + <Enum name="NO_RESTART_" start="0" description="No restart." /> + <Enum name="RESTART_IN_CASE_OF_T" start="1" description="Restart in case of time-out (counter restarts at next UARTn Rx falling edge)" /> + </BitField> + <BitField start="3" size="5" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="8" size="1" name="ABEOINTCLR" description="End of auto-baud interrupt clear bit (write-only accessible). Writing a 1 will clear the corresponding interrupt in the UnIIR. Writing a 0 has no impact."> + <Enum name="NO_IMPACT_" start="0" description="No impact." /> + <Enum name="CLEAR_THE_CORRESPOND" start="1" description="Clear the corresponding interrupt in the IIR." /> + </BitField> + <BitField start="9" size="1" name="ABTOINTCLR" description="Auto-baud time-out interrupt clear bit (write-only accessible). Writing a 1 will clear the corresponding interrupt in the UnIIR. Writing a 0 has no impact."> + <Enum name="NO_IMPACT_" start="0" description="No impact." /> + <Enum name="CLEAR_THE_CORRESPOND" start="1" description="Clear the corresponding interrupt in the IIR." /> + </BitField> + <BitField start="10" size="22" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x028" size="4" name="FDR" access="Read/Write" description="Fractional Divider Register. Generates a clock input for the baud rate divider." reset_value="0x10" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="4" name="DIVADDVAL" description="Baud-rate generation pre-scaler divisor value. If this field is 0, fractional baud-rate generator will not impact the UARTn baudrate." /> + <BitField start="4" size="4" name="MULVAL" description="Baud-rate pre-scaler multiplier value. This field must be greater or equal 1 for UARTn to operate properly, regardless of whether the fractional baud-rate generator is used or not." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x030" size="4" name="TER" access="Read/Write" description="Transmit Enable Register. Turns off UART transmitter for use with software flow control." reset_value="0x80" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="7" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="7" size="1" name="TXEN" description="When this bit is 1, as it is after a Reset, data written to the THR is output on the TXD pin as soon as any preceding data has been sent. If this bit is cleared to 0 while a character is being sent, the transmission of that character is completed, but no further characters are sent until this bit is set again. In other words, a 0 in this bit blocks the transfer of characters from the THR or TX FIFO into the transmit shift register. Software implementing software-handshaking can clear this bit when it receives an XOFF character (DC3). Software can set this bit again when it receives an XON (DC1) character." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x04C" size="4" name="RS485CTRL" access="Read/Write" description="RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="NMMEN" description="NMM enable."> + <Enum name="DISABLED" start="0" description="RS-485/EIA-485 Normal Multidrop Mode (NMM) is disabled." /> + <Enum name="ENABLED" start="1" description="RS-485/EIA-485 Normal Multidrop Mode (NMM) is enabled. In this mode, an address is detected when a received byte has the parity bit = 1, generating a received data interrupt. See Section 18.6.16 RS-485/EIA-485 modes of operation." /> + </BitField> + <BitField start="1" size="1" name="RXDIS" description="Receiver enable."> + <Enum name="ENABLED" start="0" description="The receiver is enabled." /> + <Enum name="DISABLED" start="1" description="The receiver is disabled." /> + </BitField> + <BitField start="2" size="1" name="AADEN" description="AAD enable."> + <Enum name="DISABLED" start="0" description="Auto Address Detect (AAD) is disabled." /> + <Enum name="ENABLED" start="1" description="Auto Address Detect (AAD) is enabled." /> + </BitField> + <BitField start="3" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="4" size="1" name="DCTRL" description="Direction control enable."> + <Enum name="DISABLE_AUTO_DIRECTI" start="0" description="Disable Auto Direction Control." /> + <Enum name="ENABLE_AUTO_DIRECTIO" start="1" description="Enable Auto Direction Control." /> + </BitField> + <BitField start="5" size="1" name="OINV" description="Direction control pin polarity. This bit reverses the polarity of the direction control signal on the Un_OE pin."> + <Enum name="DIRLOW" start="0" description="The direction control pin will be driven to logic 0 when the transmitter has data to be sent. It will be driven to logic 1 after the last bit of data has been transmitted." /> + <Enum name="DIRHIGH" start="1" description="The direction control pin will be driven to logic 1 when the transmitter has data to be sent. It will be driven to logic 0 after the last bit of data has been transmitted." /> + </BitField> + <BitField start="6" size="26" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x050" size="4" name="RS485ADRMATCH" access="Read/Write" description="RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="ADRMATCH" description="Contains the address match value." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x054" size="4" name="RS485DLY" access="Read/Write" description="RS-485/EIA-485 direction control delay." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="DLY" description="Contains the direction control (UnOE) delay value. This register works in conjunction with an 8-bit counter." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + </RegisterGroup> + <RegisterGroup name="I2C2" start="0x400A0000" description="I2C bus interface"> + <Register start="+0x000" size="4" name="CONSET" access="Read/Write" description="I2C Control Set Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is set. Writing a zero has no effect on the corresponding bit in the I2C control register." reset_value="0x00" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + <BitField start="2" size="1" name="AA" description="Assert acknowledge flag." /> + <BitField start="3" size="1" name="SI" description="I2C interrupt flag." /> + <BitField start="4" size="1" name="STO" description="STOP flag." /> + <BitField start="5" size="1" name="STA" description="START flag." /> + <BitField start="6" size="1" name="I2EN" description="I2C interface enable." /> + <BitField start="7" size="25" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x004" size="4" name="STAT" access="ReadOnly" description="I2C Status Register. During I2C operation, this register provides detailed status codes that allow software to determine the next action needed." reset_value="0xF8" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="RESERVED" description="These bits are unused and are always 0." /> + <BitField start="3" size="5" name="Status" description="These bits give the actual status information about the I 2C interface." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x008" size="4" name="DAT" access="Read/Write" description="I2C Data Register. During master or slave transmit mode, data to be transmitted is written to this register. During master or slave receive mode, data that has been received may be read from this register." reset_value="0x00" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="Data" description="This register holds data values that have been received or are to be transmitted." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x00C" size="4" name="ADR0" access="Read/Write" description="I2C Slave Address Register 0. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="GC" description="General Call enable bit." /> + <BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x010" size="4" name="SCLH" access="Read/Write" description="SCH Duty Cycle Register High Half Word. Determines the high time of the I2C clock." reset_value="0x04" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="16" name="SCLH" description="Count for SCL HIGH time period selection." /> + <BitField start="16" size="16" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x014" size="4" name="SCLL" access="Read/Write" description="SCL Duty Cycle Register Low Half Word. Determines the low time of the I2C clock. SCLL and SCLH together determine the clock frequency generated by an I2C master and certain times used in slave mode." reset_value="0x04" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="16" name="SCLL" description="Count for SCL low time period selection." /> + <BitField start="16" size="16" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x018" size="4" name="CONCLR" access="WriteOnly" description="I2C Control Clear Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is cleared. Writing a zero has no effect on the corresponding bit in the I2C control register." reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="2" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + <BitField start="2" size="1" name="AAC" description="Assert acknowledge Clear bit." /> + <BitField start="3" size="1" name="SIC" description="I2C interrupt Clear bit." /> + <BitField start="4" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + <BitField start="5" size="1" name="STAC" description="START flag Clear bit." /> + <BitField start="6" size="1" name="I2ENC" description="I2C interface Disable bit." /> + <BitField start="7" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x01C" size="4" name="MMCTRL" access="Read/Write" description="Monitor mode control register." reset_value="0x00" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="MM_ENA" description="Monitor mode enable."> + <Enum name="MONITOR_MODE_DISABLE" start="0" description="Monitor mode disabled." /> + <Enum name="THE_I_2C_MODULE_WILL" start="1" description="The I 2C module will enter monitor mode. In this mode the SDA output will be forced high. This will prevent the I2C module from outputting data of any kind (including ACK) onto the I2C data bus. Depending on the state of the ENA_SCL bit, the output may be also forced high, preventing the module from having control over the I2C clock line." /> + </BitField> + <BitField start="1" size="1" name="ENA_SCL" description="SCL output enable."> + <Enum name="WHEN_THIS_BIT_IS_CLE" start="0" description="When this bit is cleared to 0, the SCL output will be forced high when the module is in monitor mode. As described above, this will prevent the module from having any control over the I2C clock line." /> + <Enum name="WHEN_THIS_BIT_IS_SET" start="1" description="When this bit is set, the I2C module may exercise the same control over the clock line that it would in normal operation. This means that, acting as a slave peripheral, the I2C module can stretch the clock line (hold it low) until it has had time to respond to an I2C interrupt.[1]" /> + </BitField> + <BitField start="2" size="1" name="MATCH_ALL" description="Select interrupt register match."> + <Enum name="WHEN_THIS_BIT_IS_CLE" start="0" description="When this bit is cleared, an interrupt will only be generated when a match occurs to one of the (up-to) four address registers described above. That is, the module will respond as a normal slave as far as address-recognition is concerned." /> + <Enum name="WHEN_THIS_BIT_IS_SET" start="1" description="When this bit is set to 1 and the I2C is in monitor mode, an interrupt will be generated on ANY address received. This will enable the part to monitor all traffic on the bus." /> + </BitField> + <BitField start="3" size="29" name="RESERVED" description="Reserved. The value read from reserved bits is not defined." /> + </Register> + <Register start="+0x020+0" size="4" name="ADR1" access="Read/Write" description="I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="GC" description="General Call enable bit." /> + <BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x020+4" size="4" name="ADR2" access="Read/Write" description="I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="GC" description="General Call enable bit." /> + <BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x020+8" size="4" name="ADR3" access="Read/Write" description="I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="GC" description="General Call enable bit." /> + <BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x02C" size="4" name="DATA_BUFFER" access="ReadOnly" description="Data buffer register. The contents of the 8 MSBs of the DAT shift register will be transferred to the DATA_BUFFER automatically after every nine bits (8 bits of data plus ACK or NACK) has been received on the bus." reset_value="0x00" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="Data" description="This register holds contents of the 8 MSBs of the DAT shift register." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x030+0" size="4" name="MASK[0]" access="Read/Write" description="I2C Slave address mask register" reset_value="0x00" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." /> + <BitField start="1" size="7" name="MASK" description="Mask bits." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x030+4" size="4" name="MASK[1]" access="Read/Write" description="I2C Slave address mask register" reset_value="0x00" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." /> + <BitField start="1" size="7" name="MASK" description="Mask bits." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x030+8" size="4" name="MASK[2]" access="Read/Write" description="I2C Slave address mask register" reset_value="0x00" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." /> + <BitField start="1" size="7" name="MASK" description="Mask bits." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x030+12" size="4" name="MASK[3]" access="Read/Write" description="I2C Slave address mask register" reset_value="0x00" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." /> + <BitField start="1" size="7" name="MASK" description="Mask bits." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + </RegisterGroup> + <RegisterGroup name="I2S" start="0x400A8000" description="I2S interface"> + <Register start="+0x000" size="4" name="DAO" access="Read/Write" description="I2S Digital Audio Output Register. Contains control bits for the I2S transmit channel." reset_value="0x87E1" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="WORDWIDTH" description="Selects the number of bytes in data as follows:"> + <Enum name="8_BIT_DATA" start="0x0" description="8-bit data" /> + <Enum name="16_BIT_DATA" start="0x1" description="16-bit data" /> + <Enum name="32_BIT_DATA" start="0x3" description="32-bit data" /> + </BitField> + <BitField start="2" size="1" name="MONO" description="When 1, data is of monaural format. When 0, the data is in stereo format." /> + <BitField start="3" size="1" name="STOP" description="When 1, disables accesses on FIFOs, places the transmit channel in mute mode." /> + <BitField start="4" size="1" name="RESET" description="When 1, asynchronously resets the transmit channel and FIFO." /> + <BitField start="5" size="1" name="WS_SEL" description="When 0, the interface is in master mode. When 1, the interface is in slave mode. See Section 34.7.2 for a summary of useful combinations for this bit with TXMODE." /> + <BitField start="6" size="9" name="WS_HALFPERIOD" description="Word select half period minus 1, i.e. WS 64clk period -> ws_halfperiod = 31." /> + <BitField start="15" size="1" name="MUTE" description="When 1, the transmit channel sends only zeroes." /> + <BitField start="16" size="16" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x004" size="4" name="DAI" access="Read/Write" description="I2S Digital Audio Input Register. Contains control bits for the I2S receive channel." reset_value="0x07E1" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="WORDWIDTH" description="Selects the number of bytes in data as follows:"> + <Enum name="8_BIT_DATA" start="0x0" description="8-bit data" /> + <Enum name="16_BIT_DATA" start="0x1" description="16-bit data" /> + <Enum name="32_BIT_DATA" start="0x3" description="32-bit data" /> + </BitField> + <BitField start="2" size="1" name="MONO" description="When 1, data is of monaural format. When 0, the data is in stereo format." /> + <BitField start="3" size="1" name="STOP" description="When 1, disables accesses on FIFOs, places the transmit channel in mute mode." /> + <BitField start="4" size="1" name="RESET" description="When 1, asynchronously reset the transmit channel and FIFO." /> + <BitField start="5" size="1" name="WS_SEL" description="When 0, the interface is in master mode. When 1, the interface is in slave mode. See Section 34.7.2 for a summary of useful combinations for this bit with RXMODE." /> + <BitField start="6" size="9" name="WS_HALFPERIOD" description="Word select half period minus 1, i.e. WS 64clk period -> ws_halfperiod = 31." /> + <BitField start="15" size="17" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x008" size="4" name="TXFIFO" access="WriteOnly" description="I2S Transmit FIFO. Access register for the 8 x 32-bit transmitter FIFO." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="I2STXFIFO" description="8 x 32-bit transmit FIFO." /> + </Register> + <Register start="+0x00C" size="4" name="RXFIFO" access="None" description="I2S Receive FIFO. Access register for the 8 x 32-bit receiver FIFO." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="I2SRXFIFO" description="8 x 32-bit transmit FIFO." /> + </Register> + <Register start="+0x010" size="4" name="STATE" access="ReadOnly" description="I2S Status Feedback Register. Contains status information about the I2S interface." reset_value="0x7" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="IRQ" description="This bit reflects the presence of Receive Interrupt or Transmit Interrupt. This is determined by comparing the current FIFO levels to the rx_depth_irq and tx_depth_irq fields in the IRQ register." /> + <BitField start="1" size="1" name="DMAREQ1" description="This bit reflects the presence of Receive or Transmit DMA Request 1. This is determined by comparing the current FIFO levels to the rx_depth_dma1 and tx_depth_dma1 fields in the DMA1 register." /> + <BitField start="2" size="1" name="DMAREQ2" description="This bit reflects the presence of Receive or Transmit DMA Request 2. This is determined by comparing the current FIFO levels to the rx_depth_dma2 and tx_depth_dma2 fields in the DMA2 register." /> + <BitField start="3" size="5" name="RESERVED" description="Reserved." /> + <BitField start="8" size="4" name="RX_LEVEL" description="Reflects the current level of the Receive FIFO." /> + <BitField start="12" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + <BitField start="16" size="4" name="TX_LEVEL" description="Reflects the current level of the Transmit FIFO." /> + <BitField start="20" size="12" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x014" size="4" name="DMA1" access="Read/Write" description="I2S DMA Configuration Register 1. Contains control information for DMA request 1." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RX_DMA1_ENABLE" description="When 1, enables DMA1 for I2S receive." /> + <BitField start="1" size="1" name="TX_DMA1_ENABLE" description="When 1, enables DMA1 for I2S transmit." /> + <BitField start="2" size="6" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + <BitField start="8" size="4" name="RX_DEPTH_DMA1" description="Set the FIFO level that triggers a receive DMA request on DMA1." /> + <BitField start="12" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + <BitField start="16" size="4" name="TX_DEPTH_DMA1" description="Set the FIFO level that triggers a transmit DMA request on DMA1." /> + <BitField start="20" size="12" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x018" size="4" name="DMA2" access="Read/Write" description="I2S DMA Configuration Register 2. Contains control information for DMA request 2." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RX_DMA2_ENABLE" description="When 1, enables DMA1 for I2S receive." /> + <BitField start="1" size="1" name="TX_DMA2_ENABLE" description="When 1, enables DMA1 for I2S transmit." /> + <BitField start="2" size="6" name="RESERVED" description="Reserved." /> + <BitField start="8" size="4" name="RX_DEPTH_DMA2" description="Set the FIFO level that triggers a receive DMA request on DMA2." /> + <BitField start="12" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + <BitField start="16" size="4" name="TX_DEPTH_DMA2" description="Set the FIFO level that triggers a transmit DMA request on DMA2." /> + <BitField start="20" size="12" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x01C" size="4" name="IRQ" access="Read/Write" description="I2S Interrupt Request Control Register. Contains bits that control how the I2S interrupt request is generated." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RX_IRQ_ENABLE" description="When 1, enables I2S receive interrupt." /> + <BitField start="1" size="1" name="TX_IRQ_ENABLE" description="When 1, enables I2S transmit interrupt." /> + <BitField start="2" size="6" name="RESERVED" description="Reserved." /> + <BitField start="8" size="4" name="RX_DEPTH_IRQ" description="Set the FIFO level on which to create an irq request." /> + <BitField start="12" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + <BitField start="16" size="4" name="TX_DEPTH_IRQ" description="Set the FIFO level on which to create an irq request." /> + <BitField start="20" size="12" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x020" size="4" name="TXRATE" access="Read/Write" description="I2S Transmit MCLK divider. This register determines the I2S TX MCLK rate by specifying the value to divide PCLK by in order to produce MCLK." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="Y_DIVIDER" description="I2S transmit MCLK rate denominator. This value is used to divide PCLK to produce the transmit MCLK. Eight bits of fractional divide supports a wide range of possibilities. A value of 0 stops the clock." /> + <BitField start="8" size="8" name="X_DIVIDER" description="I2S transmit MCLK rate numerator. This value is used to multiply PCLK by to produce the transmit MCLK. A value of 0 stops the clock. Eight bits of fractional divide supports a wide range of possibilities. Note: the resulting ratio X/Y is divided by 2." /> + <BitField start="16" size="16" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x024" size="4" name="RXRATE" access="Read/Write" description="I2S Receive MCLK divider. This register determines the I2S RX MCLK rate by specifying the value to divide PCLK by in order to produce MCLK." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="Y_DIVIDER" description="I2S receive MCLK rate denominator. This value is used to divide PCLK to produce the receive MCLK. Eight bits of fractional divide supports a wide range of possibilities. A value of 0 stops the clock." /> + <BitField start="8" size="8" name="X_DIVIDER" description="I2S receive MCLK rate numerator. This value is used to multiply PCLK by to produce the receive MCLK. A value of 0 stops the clock. Eight bits of fractional divide supports a wide range of possibilities. Note: the resulting ratio X/Y is divided by 2." /> + <BitField start="16" size="16" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x028" size="4" name="TXBITRATE" access="Read/Write" description="I2S Transmit bit rate divider. This register determines the I2S transmit bit rate by specifying the value to divide TX_MCLK by in order to produce the transmit bit clock." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="6" name="TX_BITRATE" description="I2S transmit bit rate. This value plus one is used to divide TX_MCLK to produce the transmit bit clock." /> + <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x02C" size="4" name="RXBITRATE" access="Read/Write" description="I2S Receive bit rate divider. This register determines the I2S receive bit rate by specifying the value to divide RX_MCLK by in order to produce the receive bit clock." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="6" name="RX_BITRATE" description="I2S receive bit rate. This value plus one is used to divide RX_MCLK to produce the receive bit clock." /> + <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x030" size="4" name="TXMODE" access="Read/Write" description="I2S Transmit mode control." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="TXCLKSEL" description="Clock source selection for the transmit bit clock divider."> + <Enum name="SELECT_THE_TX_FRACTI" start="0x0" description="Select the TX fractional rate divider clock output as the source" /> + <Enum name="SELECT_THE_RX_MCLK_S" start="0x2" description="Select the RX_MCLK signal as the TX_MCLK clock source" /> + </BitField> + <BitField start="2" size="1" name="TX4PIN" description="Transmit 4-pin mode selection. When 1, enables 4-pin mode." /> + <BitField start="3" size="1" name="TXMCENA" description="Enable for the TX_MCLK output. When 0, output of TX_MCLK is not enabled. When 1, output of TX_MCLK is enabled." /> + <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x034" size="4" name="RXMODE" access="Read/Write" description="I2S Receive mode control." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="RXCLKSEL" description="Clock source selection for the receive bit clock divider."> + <Enum name="SELECT_THE_RX_FRACTI" start="0x0" description="Select the RX fractional rate divider clock output as the source" /> + <Enum name="SELECT_THE_TX_MCLK_S" start="0x2" description="Select the TX_MCLK signal as the RX_MCLK clock source" /> + </BitField> + <BitField start="2" size="1" name="RX4PIN" description="Receive 4-pin mode selection. When 1, enables 4-pin mode." /> + <BitField start="3" size="1" name="RXMCENA" description="Enable for the RX_MCLK output. When 0, output of RX_MCLK is not enabled. When 1, output of RX_MCLK is enabled." /> + <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + </RegisterGroup> + <RegisterGroup name="RITIMER" start="0x400B0000" description="Repetitive Interrupt Timer (RIT) "> + <Register start="+0x000" size="4" name="COMPVAL" access="Read/Write" description="Compare register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="RICOMP" description="Compare register. Holds the compare value which is compared to the counter." /> + </Register> + <Register start="+0x004" size="4" name="MASK" access="Read/Write" description="Mask register. This register holds the 32-bit mask value. A 1 written to any bit will force a compare on the corresponding bit of the counter and compare register." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="RIMASK" description="Mask register. This register holds the 32-bit mask value. A one written to any bit overrides the result of the comparison for the corresponding bit of the counter and compare register (causes the comparison of the register bits to be always true)." /> + </Register> + <Register start="+0x008" size="4" name="CTRL" access="Read/Write" description="Control register." reset_value="0xC" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RITINT" description="Interrupt flag"> + <Enum name="THIS_BIT_IS_SET_TO_1" start="1" description="This bit is set to 1 by hardware whenever the counter value equals the masked compare value specified by the contents of RICOMPVAL and RIMASK registers. Writing a 1 to this bit will clear it to 0. Writing a 0 has no effect." /> + <Enum name="THE_COUNTER_VALUE_DO" start="0" description="The counter value does not equal the masked compare value." /> + </BitField> + <BitField start="1" size="1" name="RITENCLR" description="Timer enable clear"> + <Enum name="THE_TIMER_WILL_BE_CL" start="1" description="The timer will be cleared to 0 whenever the counter value equals the masked compare value specified by the contents of RICOMPVAL and RIMASK registers. This will occur on the same clock that sets the interrupt flag." /> + <Enum name="THE_TIMER_WILL_NOT_B" start="0" description="The timer will not be cleared to 0." /> + </BitField> + <BitField start="2" size="1" name="RITENBR" description="Timer enable for debug"> + <Enum name="THE_TIMER_IS_HALTED_" start="1" description="The timer is halted when the processor is halted for debugging." /> + <Enum name="DEBUG_HAS_NO_EFFECT_" start="0" description="Debug has no effect on the timer operation." /> + </BitField> + <BitField start="3" size="1" name="RITEN" description="Timer enable."> + <Enum name="TIMER_ENABLED_THIS_" start="1" description="Timer enabled. This can be overruled by a debug halt if enabled in bit 2." /> + <Enum name="TIMER_DISABLED_" start="0" description="Timer disabled." /> + </BitField> + <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x00C" size="4" name="COUNTER" access="Read/Write" description="32-bit counter" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="RICOUNTER" description="32-bit up counter. Counts continuously unless RITEN bit in RICTRL register is cleared or debug mode is entered (if enabled by the RITNEBR bit in RICTRL). Can be loaded to any value in software." /> + </Register> + </RegisterGroup> + <RegisterGroup name="MCPWM" start="0x400B8000" description="Motor Control PWM"> + <Register start="+0x000" size="4" name="CON" access="ReadOnly" description="PWM Control read address" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RUN0" description="Stops/starts timer channel 0."> + <Enum name="STOP_" start="0" description="Stop." /> + <Enum name="RUN_" start="1" description="Run." /> + </BitField> + <BitField start="1" size="1" name="CENTER0" description="Edge/center aligned operation for channel 0."> + <Enum name="EDGE_ALIGNED_" start="0" description="Edge-aligned." /> + <Enum name="CENTER_ALIGNED_" start="1" description="Center-aligned." /> + </BitField> + <BitField start="2" size="1" name="POLA0" description="Selects polarity of the MCOA0 and MCOB0 pins."> + <Enum name="PASSIVE_STATE_IS_LOW" start="0" description="Passive state is LOW, active state is HIGH." /> + <Enum name="PASSIVE_STATE_IS_HIG" start="1" description="Passive state is HIGH, active state is LOW." /> + </BitField> + <BitField start="3" size="1" name="DTE0" description="Controls the dead-time feature for channel 0."> + <Enum name="DEAD_TIME_DISABLED_" start="0" description="Dead-time disabled." /> + <Enum name="DEAD_TIME_ENABLED_" start="1" description="Dead-time enabled." /> + </BitField> + <BitField start="4" size="1" name="DISUP0" description="Enable/disable updates of functional registers for channel 0 (see Section 24.8.2)."> + <Enum name="UPDATE" start="0" description="Functional registers are updated from the write registers at the end of each PWM cycle." /> + <Enum name="NOUPDATE" start="1" description="Functional registers remain the same as long as the timer is running." /> + </BitField> + <BitField start="5" size="3" name="RESERVED" description="Reserved." /> + <BitField start="8" size="1" name="RUN1" description="Stops/starts timer channel 1."> + <Enum name="STOP_" start="0" description="Stop." /> + <Enum name="RUN_" start="1" description="Run." /> + </BitField> + <BitField start="9" size="1" name="CENTER1" description="Edge/center aligned operation for channel 1."> + <Enum name="EDGE_ALIGNED_" start="0" description="Edge-aligned." /> + <Enum name="CENTER_ALIGNED_" start="1" description="Center-aligned." /> + </BitField> + <BitField start="10" size="1" name="POLA1" description="Selects polarity of the MCOA1 and MCOB1 pins."> + <Enum name="PASSIVE_STATE_IS_LOW" start="0" description="Passive state is LOW, active state is HIGH." /> + <Enum name="PASSIVE_STATE_IS_HIG" start="1" description="Passive state is HIGH, active state is LOW." /> + </BitField> + <BitField start="11" size="1" name="DTE1" description="Controls the dead-time feature for channel 1."> + <Enum name="DEAD_TIME_DISABLED_" start="0" description="Dead-time disabled." /> + <Enum name="DEAD_TIME_ENABLED_" start="1" description="Dead-time enabled." /> + </BitField> + <BitField start="12" size="1" name="DISUP1" description="Enable/disable updates of functional registers for channel 1 (see Section 24.8.2)."> + <Enum name="UPDATE" start="0" description="Functional registers are updated from the write registers at the end of each PWM cycle." /> + <Enum name="NOUPDATE" start="1" description="Functional registers remain the same as long as the timer is running." /> + </BitField> + <BitField start="13" size="3" name="RESERVED" description="Reserved." /> + <BitField start="16" size="1" name="RUN2" description="Stops/starts timer channel 2."> + <Enum name="STOP_" start="0" description="Stop." /> + <Enum name="RUN_" start="1" description="Run." /> + </BitField> + <BitField start="17" size="1" name="CENTER2" description="Edge/center aligned operation for channel 2."> + <Enum name="EDGE_ALIGNED_" start="0" description="Edge-aligned." /> + <Enum name="CENTER_ALIGNED_" start="1" description="Center-aligned." /> + </BitField> + <BitField start="18" size="1" name="POLA2" description="Selects polarity of the MCOA2 and MCOB2 pins."> + <Enum name="PASSIVE_STATE_IS_LOW" start="0" description="Passive state is LOW, active state is HIGH." /> + <Enum name="PASSIVE_STATE_IS_HIG" start="1" description="Passive state is HIGH, active state is LOW." /> + </BitField> + <BitField start="19" size="1" name="DTE2" description="Controls the dead-time feature for channel 1."> + <Enum name="DEAD_TIME_DISABLED_" start="0" description="Dead-time disabled." /> + <Enum name="DEAD_TIME_ENABLED_" start="1" description="Dead-time enabled." /> + </BitField> + <BitField start="20" size="1" name="DISUP2" description="Enable/disable updates of functional registers for channel 2 (see Section 24.8.2)."> + <Enum name="UPDATE" start="0" description="Functional registers are updated from the write registers at the end of each PWM cycle." /> + <Enum name="NOUPDATE" start="1" description="Functional registers remain the same as long as the timer is running." /> + </BitField> + <BitField start="21" size="8" name="RESERVED" description="Reserved." /> + <BitField start="29" size="1" name="INVBDC" description="Controls the polarity of the MCOB outputs for all 3 channels. This bit is typically set to 1 only in 3-phase DC mode."> + <Enum name="OPPOSITE" start="0" description="The MCOB outputs have opposite polarity from the MCOA outputs (aside from dead time)." /> + <Enum name="SAME" start="1" description="The MCOB outputs have the same basic polarity as the MCOA outputs. (see Section 24.8.6)" /> + </BitField> + <BitField start="30" size="1" name="ACMODE" description="3-phase AC mode select (see Section 24.8.7)."> + <Enum name="3_PHASE_AC_MODE_OFF" start="0" description="3-phase AC-mode off: Each PWM channel uses its own timer-counter and period register." /> + <Enum name="3_PHASE_AC_MODE_ON_" start="1" description="3-phase AC-mode on: All PWM channels use the timer-counter and period register of channel 0." /> + </BitField> + <BitField start="31" size="1" name="DCMODE" description="3-phase DC mode select (see Section 24.8.6)."> + <Enum name="3_PHASE_DC_MODE_OFF" start="0" description="3-phase DC mode off: PWM channels are independent (unless bit ACMODE = 1)" /> + <Enum name="3_PHASE_DC_MODE_ON_" start="1" description="3-phase DC mode on: The internal MCOA0 output is routed through the CP register (i.e. a mask) register to all six PWM outputs." /> + </BitField> + </Register> + <Register start="+0x004" size="4" name="CON_SET" access="WriteOnly" description="PWM Control set address" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="RUN0_SET" description="Writing a one sets the corresponding bit in the CON register." /> + <BitField start="1" size="1" name="CENTER0_SET" description="Writing a one sets the corresponding bit in the CON register." /> + <BitField start="2" size="1" name="POLA0_SET" description="Writing a one sets the corresponding bit in the CON register." /> + <BitField start="3" size="1" name="DTE0_SET" description="Writing a one sets the corresponding bit in the CON register." /> + <BitField start="4" size="1" name="DISUP0_SET" description="Writing a one sets the corresponding bit in the CON register." /> + <BitField start="5" size="3" name="RESERVED" description="Writing a one sets the corresponding bit in the CON register." /> + <BitField start="8" size="1" name="RUN1_SET" description="Writing a one sets the corresponding bit in the CON register." /> + <BitField start="9" size="1" name="CENTER1_SET" description="Writing a one sets the corresponding bit in the CON register." /> + <BitField start="10" size="1" name="POLA1_SET" description="Writing a one sets the corresponding bit in the CON register." /> + <BitField start="11" size="1" name="DTE1_SET" description="Writing a one sets the corresponding bit in the CON register." /> + <BitField start="12" size="1" name="DISUP1_SET" description="Writing a one sets the corresponding bit in the CON register." /> + <BitField start="13" size="3" name="RESERVED" description="Writing a one sets the corresponding bit in the CON register." /> + <BitField start="16" size="1" name="RUN2_SET" description="Writing a one sets the corresponding bit in the CON register." /> + <BitField start="17" size="1" name="CENTER2_SET" description="Writing a one sets the corresponding bit in the CON register." /> + <BitField start="18" size="1" name="POLA2_SET" description="Writing a one sets the corresponding bit in the CON register." /> + <BitField start="19" size="1" name="DTE2_SET" description="Writing a one sets the corresponding bit in the CON register." /> + <BitField start="20" size="1" name="DISUP2_SET" description="Writing a one sets the corresponding bit in the CON register." /> + <BitField start="21" size="8" name="RESERVED" description="Writing a one sets the corresponding bit in the CON register." /> + <BitField start="29" size="1" name="INVBDC_SET" description="Writing a one sets the corresponding bit in the CON register." /> + <BitField start="30" size="1" name="ACMODE_SET" description="Writing a one sets the corresponding bit in the CON register." /> + <BitField start="31" size="1" name="DCMODE_SET" description="Writing a one sets the corresponding bit in the CON register." /> + </Register> + <Register start="+0x008" size="4" name="CON_CLR" access="WriteOnly" description="PWM Control clear address" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="RUN0_CLR" description="Writing a one clears the corresponding bit in the CON register." /> + <BitField start="1" size="1" name="CENTER0_CLR" description="Writing a one clears the corresponding bit in the CON register." /> + <BitField start="2" size="1" name="POLA0_CLR" description="Writing a one clears the corresponding bit in the CON register." /> + <BitField start="3" size="1" name="DTE0_CLR" description="Writing a one clears the corresponding bit in the CON register." /> + <BitField start="4" size="1" name="DISUP0_CLR" description="Writing a one clears the corresponding bit in the CON register." /> + <BitField start="5" size="3" name="RESERVED" description="Writing a one clears the corresponding bit in the CON register." /> + <BitField start="8" size="1" name="RUN1_CLR" description="Writing a one clears the corresponding bit in the CON register." /> + <BitField start="9" size="1" name="CENTER1_CLR" description="Writing a one clears the corresponding bit in the CON register." /> + <BitField start="10" size="1" name="POLA1_CLR" description="Writing a one clears the corresponding bit in the CON register." /> + <BitField start="11" size="1" name="DTE1_CLR" description="Writing a one clears the corresponding bit in the CON register." /> + <BitField start="12" size="1" name="DISUP1_CLR" description="Writing a one clears the corresponding bit in the CON register." /> + <BitField start="13" size="3" name="RESERVED" description="Writing a one clears the corresponding bit in the CON register." /> + <BitField start="16" size="1" name="RUN2_CLR" description="Writing a one clears the corresponding bit in the CON register." /> + <BitField start="17" size="1" name="CENTER2_CLR" description="Writing a one clears the corresponding bit in the CON register." /> + <BitField start="18" size="1" name="POLA2_CLR" description="Writing a one clears the corresponding bit in the CON register." /> + <BitField start="19" size="1" name="DTE2_CLR" description="Writing a one clears the corresponding bit in the CON register." /> + <BitField start="20" size="1" name="DISUP2_CLR" description="Writing a one clears the corresponding bit in the CON register." /> + <BitField start="21" size="8" name="RESERVED" description="Writing a one clears the corresponding bit in the CON register." /> + <BitField start="29" size="1" name="INVBDC_CLR" description="Writing a one clears the corresponding bit in the CON register." /> + <BitField start="30" size="1" name="ACMOD_CLR" description="Writing a one clears the corresponding bit in the CON register." /> + <BitField start="31" size="1" name="DCMODE_CLR" description="Writing a one clears the corresponding bit in the CON register." /> + </Register> + <Register start="+0x00C" size="4" name="CAPCON" access="ReadOnly" description="Capture Control read address" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="CAP0MCI0_RE" description="A 1 in this bit enables a channel 0 capture event on a rising edge on MCI0." /> + <BitField start="1" size="1" name="CAP0MCI0_FE" description="A 1 in this bit enables a channel 0 capture event on a falling edge on MCI0." /> + <BitField start="2" size="1" name="CAP0MCI1_RE" description="A 1 in this bit enables a channel 0 capture event on a rising edge on MCI1." /> + <BitField start="3" size="1" name="CAP0MCI1_FE" description="A 1 in this bit enables a channel 0 capture event on a falling edge on MCI1." /> + <BitField start="4" size="1" name="CAP0MCI2_RE" description="A 1 in this bit enables a channel 0 capture event on a rising edge on MCI2." /> + <BitField start="5" size="1" name="CAP0MCI2_FE" description="A 1 in this bit enables a channel 0 capture event on a falling edge on MCI2." /> + <BitField start="6" size="1" name="CAP1MCI0_RE" description="A 1 in this bit enables a channel 1 capture event on a rising edge on MCI0." /> + <BitField start="7" size="1" name="CAP1MCI0_FE" description="A 1 in this bit enables a channel 1 capture event on a falling edge on MCI0." /> + <BitField start="8" size="1" name="CAP1MCI1_RE" description="A 1 in this bit enables a channel 1 capture event on a rising edge on MCI1." /> + <BitField start="9" size="1" name="CAP1MCI1_FE" description="A 1 in this bit enables a channel 1 capture event on a falling edge on MCI1." /> + <BitField start="10" size="1" name="CAP1MCI2_RE" description="A 1 in this bit enables a channel 1 capture event on a rising edge on MCI2." /> + <BitField start="11" size="1" name="CAP1MCI2_FE" description="A 1 in this bit enables a channel 1 capture event on a falling edge on MCI2." /> + <BitField start="12" size="1" name="CAP2MCI0_RE" description="A 1 in this bit enables a channel 2 capture event on a rising edge on MCI0." /> + <BitField start="13" size="1" name="CAP2MCI0_FE" description="A 1 in this bit enables a channel 2 capture event on a falling edge on MCI0." /> + <BitField start="14" size="1" name="CAP2MCI1_RE" description="A 1 in this bit enables a channel 2 capture event on a rising edge on MCI1." /> + <BitField start="15" size="1" name="CAP2MCI1_FE" description="A 1 in this bit enables a channel 2 capture event on a falling edge on MCI1." /> + <BitField start="16" size="1" name="CAP2MCI2_RE" description="A 1 in this bit enables a channel 2 capture event on a rising edge on MCI2." /> + <BitField start="17" size="1" name="CAP2MCI2_FE" description="A 1 in this bit enables a channel 2 capture event on a falling edge on MCI2." /> + <BitField start="18" size="1" name="RT0" description="If this bit is 1, TC0 is reset by a channel 0 capture event." /> + <BitField start="19" size="1" name="RT1" description="If this bit is 1, TC1 is reset by a channel 1 capture event." /> + <BitField start="20" size="1" name="RT2" description="If this bit is 1, TC2 is reset by a channel 2 capture event." /> + <BitField start="21" size="11" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x010" size="4" name="CAPCON_SET" access="WriteOnly" description="Capture Control set address" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="CAP0MCI0_RE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." /> + <BitField start="1" size="1" name="CAP0MCI0_FE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." /> + <BitField start="2" size="1" name="CAP0MCI1_RE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." /> + <BitField start="3" size="1" name="CAP0MCI1_FE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." /> + <BitField start="4" size="1" name="CAP0MCI2_RE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." /> + <BitField start="5" size="1" name="CAP0MCI2_FE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." /> + <BitField start="6" size="1" name="CAP1MCI0_RE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." /> + <BitField start="7" size="1" name="CAP1MCI0_FE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." /> + <BitField start="8" size="1" name="CAP1MCI1_RE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." /> + <BitField start="9" size="1" name="CAP1MCI1_FE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." /> + <BitField start="10" size="1" name="CAP1MCI2_RE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." /> + <BitField start="11" size="1" name="CAP1MCI2_FE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." /> + <BitField start="12" size="1" name="CAP2MCI0_RE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." /> + <BitField start="13" size="1" name="CAP2MCI0_FE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." /> + <BitField start="14" size="1" name="CAP2MCI1_RE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." /> + <BitField start="15" size="1" name="CAP2MCI1_FE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." /> + <BitField start="16" size="1" name="CAP2MCI2_RE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." /> + <BitField start="17" size="1" name="CAP2MCI2_FE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." /> + <BitField start="18" size="1" name="RT0_SET" description="Writing a one sets the corresponding bits in the CAPCON register." /> + <BitField start="19" size="1" name="RT1_SET" description="Writing a one sets the corresponding bits in the CAPCON register." /> + <BitField start="20" size="1" name="RT2_SET" description="Writing a one sets the corresponding bits in the CAPCON register." /> + <BitField start="21" size="11" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x014" size="4" name="CAPCON_CLR" access="WriteOnly" description="Event Control clear address" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="CAP0MCI0_RE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." /> + <BitField start="1" size="1" name="CAP0MCI0_FE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." /> + <BitField start="2" size="1" name="CAP0MCI1_RE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." /> + <BitField start="3" size="1" name="CAP0MCI1_FE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." /> + <BitField start="4" size="1" name="CAP0MCI2_RE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." /> + <BitField start="5" size="1" name="CAP0MCI2_FE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." /> + <BitField start="6" size="1" name="CAP1MCI0_RE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." /> + <BitField start="7" size="1" name="CAP1MCI0_FE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." /> + <BitField start="8" size="1" name="CAP1MCI1_RE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." /> + <BitField start="9" size="1" name="CAP1MCI1_FE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." /> + <BitField start="10" size="1" name="CAP1MCI2_RE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." /> + <BitField start="11" size="1" name="CAP1MCI2_FE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." /> + <BitField start="12" size="1" name="CAP2MCI0_RE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." /> + <BitField start="13" size="1" name="CAP2MCI0_FE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." /> + <BitField start="14" size="1" name="CAP2MCI1_RE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." /> + <BitField start="15" size="1" name="CAP2MCI1_FE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." /> + <BitField start="16" size="1" name="CAP2MCI2_RE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." /> + <BitField start="17" size="1" name="CAP2MCI2_FE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." /> + <BitField start="18" size="1" name="RT0_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." /> + <BitField start="19" size="1" name="RT1_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." /> + <BitField start="20" size="1" name="RT2_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." /> + <BitField start="21" size="11" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x018+0" size="4" name="TC[0]" access="Read/Write" description="Timer Counter register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="MCTC" description="Timer/Counter value." /> + </Register> + <Register start="+0x018+4" size="4" name="TC[1]" access="Read/Write" description="Timer Counter register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="MCTC" description="Timer/Counter value." /> + </Register> + <Register start="+0x018+8" size="4" name="TC[2]" access="Read/Write" description="Timer Counter register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="MCTC" description="Timer/Counter value." /> + </Register> + <Register start="+0x024+0" size="4" name="LIM[0]" access="Read/Write" description="Limit register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="MCLIM" description="Limit value." /> + </Register> + <Register start="+0x024+4" size="4" name="LIM[1]" access="Read/Write" description="Limit register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="MCLIM" description="Limit value." /> + </Register> + <Register start="+0x024+8" size="4" name="LIM[2]" access="Read/Write" description="Limit register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="MCLIM" description="Limit value." /> + </Register> + <Register start="+0x030+0" size="4" name="MAT[0]" access="Read/Write" description="Match register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="MCMAT" description="Match value." /> + </Register> + <Register start="+0x030+4" size="4" name="MAT[1]" access="Read/Write" description="Match register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="MCMAT" description="Match value." /> + </Register> + <Register start="+0x030+8" size="4" name="MAT[2]" access="Read/Write" description="Match register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="MCMAT" description="Match value." /> + </Register> + <Register start="+0x03C" size="4" name="DT" access="Read/Write" description="Dead time register" reset_value="0x3FFFFFFF" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="10" name="DT0" description="Dead time for channel 0.[1]" /> + <BitField start="10" size="10" name="DT1" description="Dead time for channel 1.[2]" /> + <BitField start="20" size="10" name="DT2" description="Dead time for channel 2.[2]" /> + <BitField start="30" size="2" name="RESERVED" description="reserved" /> + </Register> + <Register start="+0x040" size="4" name="CP" access="Read/Write" description="Communication Pattern register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="CCPA0" description="Communication pattern output A, channel 0."> + <Enum name="MCOA0_PASSIVE_" start="0" description="MCOA0 passive." /> + <Enum name="INTERNAL_MCOA0_" start="1" description="internal MCOA0." /> + </BitField> + <BitField start="1" size="1" name="CCPB0" description="Communication pattern output B, channel 0."> + <Enum name="MCOB0_PASSIVE_" start="0" description="MCOB0 passive." /> + <Enum name="MCOB0_TRACKS_INTERNA" start="1" description="MCOB0 tracks internal MCOA0." /> + </BitField> + <BitField start="2" size="1" name="CCPA1" description="Communication pattern output A, channel 1."> + <Enum name="MCOA1_PASSIVE_" start="0" description="MCOA1 passive." /> + <Enum name="MCOA1_TRACKS_INTERNA" start="1" description="MCOA1 tracks internal MCOA0." /> + </BitField> + <BitField start="3" size="1" name="CCPB1" description="Communication pattern output B, channel 1."> + <Enum name="MCOB1_PASSIVE_" start="0" description="MCOB1 passive." /> + <Enum name="MCOB1_TRACKS_INTERNA" start="1" description="MCOB1 tracks internal MCOA0." /> + </BitField> + <BitField start="4" size="1" name="CCPA2" description="Communication pattern output A, channel 2."> + <Enum name="MCOA2_PASSIVE_" start="0" description="MCOA2 passive." /> + <Enum name="MCOA2_TRACKS_INTERNA" start="1" description="MCOA2 tracks internal MCOA0." /> + </BitField> + <BitField start="5" size="1" name="CCPB2" description="Communication pattern output B, channel 2."> + <Enum name="MCOB2_PASSIVE_" start="0" description="MCOB2 passive." /> + <Enum name="MCOB2_TRACKS_INTERNA" start="1" description="MCOB2 tracks internal MCOA0." /> + </BitField> + <BitField start="6" size="26" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x044+0" size="4" name="CAP[0]" access="ReadOnly" description="Capture register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CAP" description="Current TC value at a capture event." /> + </Register> + <Register start="+0x044+4" size="4" name="CAP[1]" access="ReadOnly" description="Capture register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CAP" description="Current TC value at a capture event." /> + </Register> + <Register start="+0x044+8" size="4" name="CAP[2]" access="ReadOnly" description="Capture register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="CAP" description="Current TC value at a capture event." /> + </Register> + <Register start="+0x050" size="4" name="INTEN" access="ReadOnly" description="Interrupt Enable read address" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="ILIM0" description="Limit interrupt for channel 0."> + <Enum name="INTERRUPT_DISABLED_" start="0" description="Interrupt disabled." /> + <Enum name="INTERRUPT_ENABLED_" start="1" description="Interrupt enabled." /> + </BitField> + <BitField start="1" size="1" name="IMAT0" description="Match interrupt for channel 0."> + <Enum name="INTERRUPT_DISABLED_" start="0" description="Interrupt disabled." /> + <Enum name="INTERRUPT_ENABLED_" start="1" description="Interrupt enabled." /> + </BitField> + <BitField start="2" size="1" name="ICAP0" description="Capture interrupt for channel 0."> + <Enum name="INTERRUPT_DISABLED_" start="0" description="Interrupt disabled." /> + <Enum name="INTERRUPT_ENABLED_" start="1" description="Interrupt enabled." /> + </BitField> + <BitField start="3" size="1" name="RESERVED" description="Reserved." /> + <BitField start="4" size="1" name="ILIM1" description="Limit interrupt for channel 1."> + <Enum name="INTERRUPT_DISABLED_" start="0" description="Interrupt disabled." /> + <Enum name="INTERRUPT_ENABLED_" start="1" description="Interrupt enabled." /> + </BitField> + <BitField start="5" size="1" name="IMAT1" description="Match interrupt for channel 1."> + <Enum name="INTERRUPT_DISABLED_" start="0" description="Interrupt disabled." /> + <Enum name="INTERRUPT_ENABLED_" start="1" description="Interrupt enabled." /> + </BitField> + <BitField start="6" size="1" name="ICAP1" description="Capture interrupt for channel 1."> + <Enum name="INTERRUPT_DISABLED_" start="0" description="Interrupt disabled." /> + <Enum name="INTERRUPT_ENABLED_" start="1" description="Interrupt enabled." /> + </BitField> + <BitField start="7" size="1" name="RESERVED" description="Reserved." /> + <BitField start="8" size="1" name="ILIM2" description="Limit interrupt for channel 2."> + <Enum name="INTERRUPT_DISABLED_" start="0" description="Interrupt disabled." /> + <Enum name="INTERRUPT_ENABLED_" start="1" description="Interrupt enabled." /> + </BitField> + <BitField start="9" size="1" name="IMAT2" description="Match interrupt for channel 2."> + <Enum name="INTERRUPT_DISABLED_" start="0" description="Interrupt disabled." /> + <Enum name="INTERRUPT_ENABLED_" start="1" description="Interrupt enabled." /> + </BitField> + <BitField start="10" size="1" name="ICAP2" description="Capture interrupt for channel 2."> + <Enum name="INTERRUPT_DISABLED_" start="0" description="Interrupt disabled." /> + <Enum name="INTERRUPT_ENABLED_" start="1" description="Interrupt enabled." /> + </BitField> + <BitField start="11" size="4" name="RESERVED" description="Reserved." /> + <BitField start="15" size="1" name="ABORT" description="Fast abort interrupt."> + <Enum name="INTERRUPT_DISABLED_" start="0" description="Interrupt disabled." /> + <Enum name="INTERRUPT_ENABLED_" start="1" description="Interrupt enabled." /> + </BitField> + <BitField start="16" size="16" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x054" size="4" name="INTEN_SET" access="WriteOnly" description="Interrupt Enable set address" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="ILIM0_SET" description="Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt." /> + <BitField start="1" size="1" name="IMAT0_SET" description="Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt." /> + <BitField start="2" size="1" name="ICAP0_SET" description="Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt." /> + <BitField start="3" size="1" name="RESERVED" description="Reserved." /> + <BitField start="4" size="1" name="ILIM1_SET" description="Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt." /> + <BitField start="5" size="1" name="IMAT1_SET" description="Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt." /> + <BitField start="6" size="1" name="ICAP1_SET" description="Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt." /> + <BitField start="7" size="1" name="RESERVED" description="Reserved." /> + <BitField start="9" size="1" name="ILIM2_SET" description="Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt." /> + <BitField start="10" size="1" name="IMAT2_SET" description="Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt." /> + <BitField start="11" size="1" name="ICAP2_SET" description="Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt." /> + <BitField start="12" size="3" name="RESERVED" description="Reserved." /> + <BitField start="15" size="1" name="ABORT_SET" description="Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt." /> + <BitField start="16" size="16" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x058" size="4" name="INTEN_CLR" access="WriteOnly" description="Interrupt Enable clear address" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="ILIM0_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." /> + <BitField start="1" size="1" name="IMAT0_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." /> + <BitField start="2" size="1" name="ICAP0_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." /> + <BitField start="3" size="1" name="RESERVED" description="Reserved." /> + <BitField start="4" size="1" name="ILIM1_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." /> + <BitField start="5" size="1" name="IMAT1_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." /> + <BitField start="6" size="1" name="ICAP1_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." /> + <BitField start="7" size="1" name="RESERVED" description="Reserved." /> + <BitField start="8" size="1" name="ILIM2_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." /> + <BitField start="9" size="1" name="IMAT2_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." /> + <BitField start="10" size="1" name="ICAP2_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." /> + <BitField start="11" size="4" name="RESERVED" description="Reserved." /> + <BitField start="15" size="1" name="ABORT_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." /> + <BitField start="16" size="16" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x068" size="4" name="INTF" access="ReadOnly" description="Interrupt flags read address" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="ILIM0_F" description="Limit interrupt flag for channel 0."> + <Enum name="THIS_INTERRUPT_SOURC" start="0" description="This interrupt source is not contributing to the MCPWM interrupt request." /> + <Enum name="IF_THE_CORRESPONDING" start="1" description="If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller." /> + </BitField> + <BitField start="1" size="1" name="IMAT0_F" description="Match interrupt flag for channel 0."> + <Enum name="THIS_INTERRUPT_SOURC" start="0" description="This interrupt source is not contributing to the MCPWM interrupt request." /> + <Enum name="IF_THE_CORRESPONDING" start="1" description="If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller." /> + </BitField> + <BitField start="2" size="1" name="ICAP0_F" description="Capture interrupt flag for channel 0."> + <Enum name="THIS_INTERRUPT_SOURC" start="0" description="This interrupt source is not contributing to the MCPWM interrupt request." /> + <Enum name="IF_THE_CORRESPONDING" start="1" description="If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller." /> + </BitField> + <BitField start="3" size="1" name="RESERVED" description="Reserved." /> + <BitField start="4" size="1" name="ILIM1_F" description="Limit interrupt flag for channel 1."> + <Enum name="THIS_INTERRUPT_SOURC" start="0" description="This interrupt source is not contributing to the MCPWM interrupt request." /> + <Enum name="IF_THE_CORRESPONDING" start="1" description="If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller." /> + </BitField> + <BitField start="5" size="1" name="IMAT1_F" description="Match interrupt flag for channel 1."> + <Enum name="THIS_INTERRUPT_SOURC" start="0" description="This interrupt source is not contributing to the MCPWM interrupt request." /> + <Enum name="IF_THE_CORRESPONDING" start="1" description="If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller." /> + </BitField> + <BitField start="6" size="1" name="ICAP1_F" description="Capture interrupt flag for channel 1."> + <Enum name="THIS_INTERRUPT_SOURC" start="0" description="This interrupt source is not contributing to the MCPWM interrupt request." /> + <Enum name="IF_THE_CORRESPONDING" start="1" description="If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller." /> + </BitField> + <BitField start="7" size="1" name="RESERVED" description="Reserved." /> + <BitField start="8" size="1" name="ILIM2_F" description="Limit interrupt flag for channel 2."> + <Enum name="THIS_INTERRUPT_SOURC" start="0" description="This interrupt source is not contributing to the MCPWM interrupt request." /> + <Enum name="IF_THE_CORRESPONDING" start="1" description="If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller." /> + </BitField> + <BitField start="9" size="1" name="IMAT2_F" description="Match interrupt flag for channel 2."> + <Enum name="THIS_INTERRUPT_SOURC" start="0" description="This interrupt source is not contributing to the MCPWM interrupt request." /> + <Enum name="IF_THE_CORRESPONDING" start="1" description="If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller." /> + </BitField> + <BitField start="10" size="1" name="ICAP2_F" description="Capture interrupt flag for channel 2."> + <Enum name="THIS_INTERRUPT_SOURC" start="0" description="This interrupt source is not contributing to the MCPWM interrupt request." /> + <Enum name="IF_THE_CORRESPONDING" start="1" description="If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller." /> + </BitField> + <BitField start="11" size="4" name="RESERVED" description="Reserved." /> + <BitField start="15" size="1" name="ABORT_F" description="Fast abort interrupt flag."> + <Enum name="THIS_INTERRUPT_SOURC" start="0" description="This interrupt source is not contributing to the MCPWM interrupt request." /> + <Enum name="IF_THE_CORRESPONDING" start="1" description="If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller." /> + </BitField> + <BitField start="16" size="16" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x06C" size="4" name="INTF_SET" access="WriteOnly" description="Interrupt flags set address" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="ILIM0_F_SET" description="Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt." /> + <BitField start="1" size="1" name="IMAT0_F_SET" description="Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt." /> + <BitField start="2" size="1" name="ICAP0_F_SET" description="Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt." /> + <BitField start="3" size="1" name="RESERVED" description="Reserved." /> + <BitField start="4" size="1" name="ILIM1_F_SET" description="Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt." /> + <BitField start="5" size="1" name="IMAT1_F_SET" description="Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt." /> + <BitField start="6" size="1" name="ICAP1_F_SET" description="Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt." /> + <BitField start="7" size="1" name="RESERVED" description="Reserved." /> + <BitField start="8" size="1" name="ILIM2_F_SET" description="Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt." /> + <BitField start="9" size="1" name="IMAT2_F_SET" description="Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt." /> + <BitField start="10" size="1" name="ICAP2_F_SET" description="Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt." /> + <BitField start="11" size="4" name="RESERVED" description="Reserved." /> + <BitField start="15" size="1" name="ABORT_F_SET" description="Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt." /> + <BitField start="16" size="16" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x070" size="4" name="INTF_CLR" access="WriteOnly" description="Interrupt flags clear address" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="ILIM0_F_CLR" description="Writing a one clears the corresponding bit in the INTF register, thus clearing the corresponding interrupt request." /> + <BitField start="1" size="1" name="IMAT0_F_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." /> + <BitField start="2" size="1" name="ICAP0_F_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." /> + <BitField start="3" size="1" name="RESERVED" description="Reserved." /> + <BitField start="4" size="1" name="ILIM1_F_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." /> + <BitField start="5" size="1" name="IMAT1_F_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." /> + <BitField start="6" size="1" name="ICAP1_F_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." /> + <BitField start="7" size="1" name="RESERVED" description="Reserved." /> + <BitField start="8" size="1" name="ILIM2_F_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." /> + <BitField start="9" size="1" name="IMAT2_F_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." /> + <BitField start="10" size="1" name="ICAP2_F_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." /> + <BitField start="11" size="4" name="RESERVED" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." /> + <BitField start="15" size="1" name="ABORT_F_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." /> + <BitField start="16" size="16" name="RESERVED" description="Reserved." /> + </Register> + <Register start="+0x05C" size="4" name="CNTCON" access="ReadOnly" description="Count Control read address" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="TC0MCI0_RE" description="Counter 0 rising edge mode, channel 0."> + <Enum name="A_RISING_EDGE_ON_MCI" start="0" description="A rising edge on MCI0 does not affect counter 0." /> + <Enum name="RISING" start="1" description="If MODE0 is 1, counter 0 advances on a rising edge on MCI0." /> + </BitField> + <BitField start="1" size="1" name="TC0MCI0_FE" description="Counter 0 falling edge mode, channel 0."> + <Enum name="A_FALLING_EDGE_ON_MC" start="0" description="A falling edge on MCI0 does not affect counter 0." /> + <Enum name="FALLING" start="1" description="If MODE0 is 1, counter 0 advances on a falling edge on MCI0." /> + </BitField> + <BitField start="2" size="1" name="TC0MCI1_RE" description="Counter 0 rising edge mode, channel 1."> + <Enum name="A_RISING_EDGE_ON_MCI" start="0" description="A rising edge on MCI1 does not affect counter 0." /> + <Enum name="RISING" start="1" description="If MODE0 is 1, counter 0 advances on a rising edge on MCI1." /> + </BitField> + <BitField start="3" size="1" name="TC0MCI1_FE" description="Counter 0 falling edge mode, channel 1."> + <Enum name="A_FALLING_EDGE_ON_MC" start="0" description="A falling edge on MCI1 does not affect counter 0." /> + <Enum name="FALLING" start="1" description="If MODE0 is 1, counter 0 advances on a falling edge on MCI1." /> + </BitField> + <BitField start="4" size="1" name="TC0MCI2_RE" description="Counter 0 rising edge mode, channel 2."> + <Enum name="A_RISING_EDGE_ON_MCI" start="0" description="A rising edge on MCI0 does not affect counter 0." /> + <Enum name="RISING" start="1" description="If MODE0 is 1, counter 0 advances on a rising edge on MCI2." /> + </BitField> + <BitField start="5" size="1" name="TC0MCI2_FE" description="Counter 0 falling edge mode, channel 2."> + <Enum name="A_FALLING_EDGE_ON_MC" start="0" description="A falling edge on MCI0 does not affect counter 0." /> + <Enum name="FALLLING" start="1" description="If MODE0 is 1, counter 0 advances on a falling edge on MCI2." /> + </BitField> + <BitField start="6" size="1" name="TC1MCI0_RE" description="Counter 1 rising edge mode, channel 0."> + <Enum name="A_RISING_EDGE_ON_MCI" start="0" description="A rising edge on MCI0 does not affect counter 1." /> + <Enum name="RISING" start="1" description="If MODE1 is 1, counter 1 advances on a rising edge on MCI0." /> + </BitField> + <BitField start="7" size="1" name="TC1MCI0_FE" description="Counter 1 falling edge mode, channel 0."> + <Enum name="A_FALLING_EDGE_ON_MC" start="0" description="A falling edge on MCI0 does not affect counter 1." /> + <Enum name="FALLING" start="1" description="If MODE1 is 1, counter 1 advances on a falling edge on MCI0." /> + </BitField> + <BitField start="8" size="1" name="TC1MCI1_RE" description="Counter 1 rising edge mode, channel 1."> + <Enum name="A_RISING_EDGE_ON_MCI" start="0" description="A rising edge on MCI1 does not affect counter 1." /> + <Enum name="RISING" start="1" description="If MODE1 is 1, counter 1 advances on a rising edge on MCI1." /> + </BitField> + <BitField start="9" size="1" name="TC1MCI1_FE" description="Counter 1 falling edge mode, channel 1."> + <Enum name="A_FALLING_EDGE_ON_MC" start="0" description="A falling edge on MCI0 does not affect counter 1." /> + <Enum name="FALLING" start="1" description="If MODE1 is 1, counter 1 advances on a falling edge on MCI1." /> + </BitField> + <BitField start="10" size="1" name="TC1MCI2_RE" description="Counter 1 rising edge mode, channel 2."> + <Enum name="A_RISING_EDGE_ON_MCI" start="0" description="A rising edge on MCI2 does not affect counter 1." /> + <Enum name="RISING" start="1" description="If MODE1 is 1, counter 1 advances on a rising edge on MCI2." /> + </BitField> + <BitField start="11" size="1" name="TC1MCI2_FE" description="Counter 1 falling edge mode, channel 2."> + <Enum name="A_FALLING_EDGE_ON_MC" start="0" description="A falling edge on MCI2 does not affect counter 1." /> + <Enum name="FALLING" start="1" description="If MODE1 is 1, counter 1 advances on a falling edge on MCI2." /> + </BitField> + <BitField start="12" size="1" name="TC2MCI0_RE" description="Counter 2 rising edge mode, channel 0."> + <Enum name="A_RISING_EDGE_ON_MCI" start="0" description="A rising edge on MCI0 does not affect counter 2." /> + <Enum name="RISING" start="1" description="If MODE2 is 1, counter 2 advances on a rising edge on MCI0." /> + </BitField> + <BitField start="13" size="1" name="TC2MCI0_FE" description="Counter 2 falling edge mode, channel 0."> + <Enum name="A_FALLING_EDGE_ON_MC" start="0" description="A falling edge on MCI0 does not affect counter 2." /> + <Enum name="FALLING" start="1" description="If MODE2 is 1, counter 2 advances on a falling edge on MCI0." /> + </BitField> + <BitField start="14" size="1" name="TC2MCI1_RE" description="Counter 2 rising edge mode, channel 1."> + <Enum name="A_RISING_EDGE_ON_MCI" start="0" description="A rising edge on MCI1 does not affect counter 2." /> + <Enum name="RISING" start="1" description="If MODE2 is 1, counter 2 advances on a rising edge on MCI1." /> + </BitField> + <BitField start="15" size="1" name="TC2MCI1_FE" description="Counter 2 falling edge mode, channel 1."> + <Enum name="A_FALLING_EDGE_ON_MC" start="0" description="A falling edge on MCI1 does not affect counter 2." /> + <Enum name="FALLING" start="1" description="If MODE2 is 1, counter 2 advances on a falling edge on MCI1." /> + </BitField> + <BitField start="16" size="1" name="TC2MCI2_RE" description="Counter 2 rising edge mode, channel 2."> + <Enum name="A_RISING_EDGE_ON_MCI" start="0" description="A rising edge on MCI2 does not affect counter 2." /> + <Enum name="RISIING" start="1" description="If MODE2 is 1, counter 2 advances on a rising edge on MCI2." /> + </BitField> + <BitField start="17" size="1" name="TC2MCI2_FE" description="Counter 2 falling edge mode, channel 2."> + <Enum name="A_FALLING_EDGE_ON_MC" start="0" description="A falling edge on MCI2 does not affect counter 2." /> + <Enum name="FALLING" start="1" description="If MODE2 is 1, counter 2 advances on a falling edge on MCI2." /> + </BitField> + <BitField start="18" size="11" name="RESERVED" description="Reserved." /> + <BitField start="29" size="1" name="CNTR0" description="Channel 0 counter/timer mode."> + <Enum name="CHANNEL_0_IS_IN_TIME" start="0" description="Channel 0 is in timer mode." /> + <Enum name="CHANNEL_0_IS_IN_COUN" start="1" description="Channel 0 is in counter mode." /> + </BitField> + <BitField start="30" size="1" name="CNTR1" description="Channel 1 counter/timer mode."> + <Enum name="CHANNEL_1_IS_IN_TIME" start="0" description="Channel 1 is in timer mode." /> + <Enum name="CHANNEL_1_IS_IN_COUN" start="1" description="Channel 1 is in counter mode." /> + </BitField> + <BitField start="31" size="1" name="CNTR2" description="Channel 2 counter/timer mode."> + <Enum name="CHANNEL_2_IS_IN_TIME" start="0" description="Channel 2 is in timer mode." /> + <Enum name="CHANNEL_2_IS_IN_COUN" start="1" description="Channel 2 is in counter mode." /> + </BitField> + </Register> + <Register start="+0x060" size="4" name="CNTCON_SET" access="WriteOnly" description="Count Control set address" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="TC0MCI0_RE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." /> + <BitField start="1" size="1" name="TC0MCI0_FE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." /> + <BitField start="2" size="1" name="TC0MCI1_RE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." /> + <BitField start="3" size="1" name="TC0MCI1_FE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." /> + <BitField start="4" size="1" name="TC0MCI2_RE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." /> + <BitField start="5" size="1" name="TC0MCI2_FE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." /> + <BitField start="6" size="1" name="TC1MCI0_RE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." /> + <BitField start="7" size="1" name="TC1MCI0_FE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." /> + <BitField start="8" size="1" name="TC1MCI1_RE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." /> + <BitField start="9" size="1" name="TC1MCI1_FE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." /> + <BitField start="10" size="1" name="TC1MCI2_RE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." /> + <BitField start="11" size="1" name="TC1MCI2_FE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." /> + <BitField start="12" size="1" name="TC2MCI0_RE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." /> + <BitField start="13" size="1" name="TC2MCI0_FE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." /> + <BitField start="14" size="1" name="TC2MCI1_RE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." /> + <BitField start="15" size="1" name="TC2MCI1_FE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." /> + <BitField start="16" size="1" name="TC2MCI2_RE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." /> + <BitField start="17" size="1" name="TC2MCI2_FE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." /> + <BitField start="18" size="11" name="RESERVED" description="Reserved." /> + <BitField start="29" size="1" name="CNTR0_SET" description="Writing a one sets the corresponding bit in the CNTCON register." /> + <BitField start="30" size="1" name="CNTR1_SET" description="Writing a one sets the corresponding bit in the CNTCON register." /> + <BitField start="31" size="1" name="CNTR2_SET" description="Writing a one sets the corresponding bit in the CNTCON register." /> + </Register> + <Register start="+0x064" size="4" name="CNTCON_CLR" access="WriteOnly" description="Count Control clear address" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="TC0MCI0_RE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." /> + <BitField start="1" size="1" name="TC0MCI0_FE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." /> + <BitField start="2" size="1" name="TC0MCI1_RE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." /> + <BitField start="3" size="1" name="TC0MCI1_FE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." /> + <BitField start="4" size="1" name="TC0MCI2_RE" description="Writing a one clears the corresponding bit in the CNTCON register." /> + <BitField start="5" size="1" name="TC0MCI2_FE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." /> + <BitField start="6" size="1" name="TC1MCI0_RE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." /> + <BitField start="7" size="1" name="TC1MCI0_FE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." /> + <BitField start="8" size="1" name="TC1MCI1_RE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." /> + <BitField start="9" size="1" name="TC1MCI1_FE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." /> + <BitField start="10" size="1" name="TC1MCI2_RE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." /> + <BitField start="11" size="1" name="TC1MCI2_FE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." /> + <BitField start="12" size="1" name="TC2MCI0_RE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." /> + <BitField start="13" size="1" name="TC2MCI0_FE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." /> + <BitField start="14" size="1" name="TC2MCI1_RE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." /> + <BitField start="15" size="1" name="TC2MCI1_FE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." /> + <BitField start="16" size="1" name="TC2MCI2_RE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." /> + <BitField start="17" size="1" name="TC2MCI2_FE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." /> + <BitField start="18" size="11" name="RESERVED" description="Reserved." /> + <BitField start="29" size="1" name="CNTR0_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." /> + <BitField start="30" size="1" name="CNTR1_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." /> + <BitField start="31" size="1" name="CNTR2_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." /> + </Register> + <Register start="+0x074" size="4" name="CAP_CLR" access="WriteOnly" description="Capture clear address" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="CAP_CLR0" description="Writing a 1 to this bit clears the CAP0 register." /> + <BitField start="1" size="1" name="CAP_CLR1" description="Writing a 1 to this bit clears the CAP1 register." /> + <BitField start="2" size="1" name="CAP_CLR2" description="Writing a 1 to this bit clears the CAP2 register." /> + <BitField start="3" size="29" name="RESERVED" description="Reserved" /> + </Register> + </RegisterGroup> + <RegisterGroup name="QEI" start="0x400BC000" description="Quadrature Encoder Interface (QEI) "> + <Register start="+0x000" size="4" name="CON" access="WriteOnly" description="Control register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="RESP" description="Reset position counter. When set = 1, resets the position counter to all zeros. Autoclears when the position counter is cleared." /> + <BitField start="1" size="1" name="RESPI" description="Reset position counter on index. When set = 1, resets the position counter to all zeros once only the first time an index pulse occurs. Autoclears when the position counter is cleared." /> + <BitField start="2" size="1" name="RESV" description="Reset velocity. When set = 1, resets the velocity counter to all zeros, reloads the velocity timer, and presets the velocity compare register. Autoclears when the velocity counter is cleared." /> + <BitField start="3" size="1" name="RESI" description="Reset index counter. When set = 1, resets the index counter to all zeros. Autoclears when the index counter is cleared." /> + <BitField start="4" size="28" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x008" size="4" name="CONF" access="Read/Write" description="Configuration register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="DIRINV" description="Direction invert. When 1, complements the DIR bit." /> + <BitField start="1" size="1" name="SIGMODE" description="Signal Mode. When 0, PhA and PhB function as quadrature encoder inputs. When 1, PhA functions as the direction signal and PhB functions as the clock signal." /> + <BitField start="2" size="1" name="CAPMODE" description="Capture Mode. When 0, only PhA edges are counted (2X). When 1, BOTH PhA and PhB edges are counted (4X), increasing resolution but decreasing range." /> + <BitField start="3" size="1" name="INVINX" description="Invert Index. When 1, inverts the sense of the index input." /> + <BitField start="4" size="1" name="CRESPI" description="Continuously reset the position counter on index. When 1, resets the position counter to all zeros whenever an index pulse occurs after the next position increase (recalibration)." /> + <BitField start="5" size="11" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="16" size="4" name="INXGATE" description="Index gating configuration: When INXGATE[16] = 1, pass the index when PHA = 1 and PHB = 0, otherwise block index. When INXGATE[17] = 1, pass the index when PHA = 1 and PHB = 1, otherwise block index. When INXGATE[18] = 1, pass the index when PHA = 0 and PHB = 1, otherwise block index. When INXGATE[19] = 1, pass the index when PHA = 0 and PHB = 0, otherwise block index." /> + <BitField start="20" size="12" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x004" size="4" name="STAT" access="ReadOnly" description="Status register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="DIR" description="Direction bit. In combination with DIRINV bit indicates forward or reverse direction. See Table 597." /> + <BitField start="1" size="31" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x00C" size="4" name="POS" access="ReadOnly" description="Position register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="POS" description="Current position value." /> + </Register> + <Register start="+0x010" size="4" name="MAXPOS" access="Read/Write" description="Maximum position register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="MAXPOS" description="Current maximum position value." /> + </Register> + <Register start="+0x014" size="4" name="CMPOS0" access="Read/Write" description="Position compare register 0" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="PCMP0" description="Position compare value 0." /> + </Register> + <Register start="+0x018" size="4" name="CMPOS1" access="Read/Write" description="Position compare register 1" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="PCMP1" description="Position compare value 1." /> + </Register> + <Register start="+0x01C" size="4" name="CMPOS2" access="Read/Write" description="Position compare register 2" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="PCMP2" description="Position compare value 2." /> + </Register> + <Register start="+0x020" size="4" name="INXCNT" access="ReadOnly" description="Index count register 0" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="ENCPOS" description="Current index counter value." /> + </Register> + <Register start="+0x024" size="4" name="INXCMP0" access="Read/Write" description="Index compare register 0" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="ICMP0" description="Index compare value 0." /> + </Register> + <Register start="+0x028" size="4" name="LOAD" access="Read/Write" description="Velocity timer reload register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="VELLOAD" description="Current velocity timer load value." /> + </Register> + <Register start="+0x02C" size="4" name="TIME" access="ReadOnly" description="Velocity timer register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="VELVAL" description="Current velocity timer value." /> + </Register> + <Register start="+0x030" size="4" name="VEL" access="ReadOnly" description="Velocity counter register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="VELPC" description="Current velocity pulse count." /> + </Register> + <Register start="+0x034" size="4" name="CAP" access="ReadOnly" description="Velocity capture register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="VELCAP" description="Last velocity capture." /> + </Register> + <Register start="+0x038" size="4" name="VELCOMP" access="Read/Write" description="Velocity compare register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="VELPC" description="Compare velocity pulse count." /> + </Register> + <Register start="+0x03C" size="4" name="FILTER" access="Read/Write" description="Digital filter register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="FILTA" description="Digital filter sampling delay." /> + </Register> + <Register start="+0xFE0" size="4" name="INTSTAT" access="ReadOnly" description="Interrupt status register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="INX_INT" description="Indicates that an index pulse was detected." /> + <BitField start="1" size="1" name="TIM_INT" description="Indicates that a velocity timer overflow occurred" /> + <BitField start="2" size="1" name="VELC_INT" description="Indicates that captured velocity is less than compare velocity." /> + <BitField start="3" size="1" name="DIR_INT" description="Indicates that a change of direction was detected." /> + <BitField start="4" size="1" name="ERR_INT" description="Indicates that an encoder phase error was detected." /> + <BitField start="5" size="1" name="ENCLK_INT" description="Indicates that and encoder clock pulse was detected." /> + <BitField start="6" size="1" name="POS0_INT" description="Indicates that the position 0 compare value is equal to the current position." /> + <BitField start="7" size="1" name="POS1_INT" description="Indicates that the position 1compare value is equal to the current position." /> + <BitField start="8" size="1" name="POS2_INT" description="Indicates that the position 2 compare value is equal to the current position." /> + <BitField start="9" size="1" name="REV0_INT" description="Indicates that the index compare 0 value is equal to the current index count." /> + <BitField start="10" size="1" name="POS0REV_INT" description="Combined position 0 and revolution count interrupt. Set when both the POS0_Int bit is set and the REV0_Int is set." /> + <BitField start="11" size="1" name="POS1REV_INT" description="Combined position 1 and revolution count interrupt. Set when both the POS1_Int bit is set and the REV1_Int is set." /> + <BitField start="12" size="1" name="POS2REV_INT" description="Combined position 2 and revolution count interrupt. Set when both the POS2_Int bit is set and the REV2_Int is set." /> + <BitField start="13" size="1" name="REV1_INT" description="Indicates that the index compare 1value is equal to the current index count." /> + <BitField start="14" size="1" name="REV2_INT" description="Indicates that the index compare 2 value is equal to the current index count." /> + <BitField start="15" size="1" name="MAXPOS_INT" description="Indicates that the current position count goes through the MAXPOS value to zero in the forward direction, or through zero to MAXPOS in the reverse direction." /> + <BitField start="16" size="16" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0xFEC" size="4" name="SET" access="WriteOnly" description="Interrupt status set register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="INX_INT" description="Writing a 1 sets the INX_Int bit in QEIINTSTAT." /> + <BitField start="1" size="1" name="TIM_INT" description="Writing a 1 sets the TIN_Int bit in QEIINTSTAT." /> + <BitField start="2" size="1" name="VELC_INT" description="Writing a 1 sets the VELC_Int bit in QEIINTSTAT." /> + <BitField start="3" size="1" name="DIR_INT" description="Writing a 1 sets the DIR_Int bit in QEIINTSTAT." /> + <BitField start="4" size="1" name="ERR_INT" description="Writing a 1 sets the ERR_Int bit in QEIINTSTAT." /> + <BitField start="5" size="1" name="ENCLK_INT" description="Writing a 1 sets the ENCLK_Int bit in QEIINTSTAT." /> + <BitField start="6" size="1" name="POS0_INT" description="Writing a 1 sets the POS0_Int bit in QEIINTSTAT." /> + <BitField start="7" size="1" name="POS1_INT" description="Writing a 1 sets the POS1_Int bit in QEIINTSTAT." /> + <BitField start="8" size="1" name="POS2_INT" description="Writing a 1 sets the POS2_Int bit in QEIINTSTAT." /> + <BitField start="9" size="1" name="REV0_INT" description="Writing a 1 sets the REV0_Int bit in QEIINTSTAT." /> + <BitField start="10" size="1" name="POS0REV_INT" description="Writing a 1 sets the POS0REV_Int bit in QEIINTSTAT." /> + <BitField start="11" size="1" name="POS1REV_INT" description="Writing a 1 sets the POS1REV_Int bit in QEIINTSTAT." /> + <BitField start="12" size="1" name="POS2REV_INT" description="Writing a 1 sets the POS2REV_Int bit in QEIINTSTAT." /> + <BitField start="13" size="1" name="REV1_INT" description="Writing a 1 sets the REV1_Int bit in QEIINTSTAT." /> + <BitField start="14" size="1" name="REV2_INT" description="Writing a 1 sets the REV2_Int bit in QEIINTSTAT." /> + <BitField start="15" size="1" name="MAXPOS_INT" description="Writing a 1 sets the MAXPOS_Int bit in QEIINTSTAT." /> + <BitField start="16" size="16" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0xFE8" size="4" name="CLR" access="WriteOnly" description="Interrupt status clear register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="INX_INT" description="Writing a 1 clears the INX_Int bit in QEIINTSTAT." /> + <BitField start="1" size="1" name="TIM_INT" description="Writing a 1 clears the TIN_Int bit in QEIINTSTAT." /> + <BitField start="2" size="1" name="VELC_INT" description="Writing a 1 clears the VELC_Int bit in QEIINTSTAT." /> + <BitField start="3" size="1" name="DIR_INT" description="Writing a 1 clears the DIR_Int bit in QEIINTSTAT." /> + <BitField start="4" size="1" name="ERR_INT" description="Writing a 1 clears the ERR_Int bit in QEIINTSTAT." /> + <BitField start="5" size="1" name="ENCLK_INT" description="Writing a 1 clears the ENCLK_Int bit in QEIINTSTAT." /> + <BitField start="6" size="1" name="POS0_INT" description="Writing a 1 clears the POS0_Int bit in QEIINTSTAT." /> + <BitField start="7" size="1" name="POS1_INT" description="Writing a 1 clears the POS1_Int bit in QEIINTSTAT." /> + <BitField start="8" size="1" name="POS2_INT" description="Writing a 1 clears the POS2_Int bit in QEIINTSTAT." /> + <BitField start="9" size="1" name="REV0_INT" description="Writing a 1 clears the REV0_Int bit in QEIINTSTAT." /> + <BitField start="10" size="1" name="POS0REV_INT" description="Writing a 1 clears the POS0REV_Int bit in QEIINTSTAT." /> + <BitField start="11" size="1" name="POS1REV_INT" description="Writing a 1 clears the POS1REV_Int bit in QEIINTSTAT." /> + <BitField start="12" size="1" name="POS2REV_INT" description="Writing a 1 clears the POS2REV_Int bit in QEIINTSTAT." /> + <BitField start="13" size="1" name="REV1_INT" description="Writing a 1 clears the REV1_Int bit in QEIINTSTAT." /> + <BitField start="14" size="1" name="REV2_INT" description="Writing a 1 clears the REV2_Int bit in QEIINTSTAT." /> + <BitField start="15" size="1" name="MAXPOS_INT" description="Writing a 1 clears the MAXPOS_Int bit in QEIINTSTAT." /> + <BitField start="16" size="16" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0xFE4" size="4" name="IE" access="ReadOnly" description="Interrupt enable register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="INX_INT" description="When 1, the INX_Int interrupt is enabled." /> + <BitField start="1" size="1" name="TIM_INT" description="When 1, the TIN_Int interrupt is enabled." /> + <BitField start="2" size="1" name="VELC_INT" description="When 1, the VELC_Int interrupt is enabled." /> + <BitField start="3" size="1" name="DIR_INT" description="When 1, the DIR_Int interrupt is enabled." /> + <BitField start="4" size="1" name="ERR_INT" description="When 1, the ERR_Int interrupt is enabled." /> + <BitField start="5" size="1" name="ENCLK_INT" description="When 1, the ENCLK_Int interrupt is enabled." /> + <BitField start="6" size="1" name="POS0_INT" description="When 1, the POS0_Int interrupt is enabled." /> + <BitField start="7" size="1" name="POS1_INT" description="When 1, the POS1_Int interrupt is enabled." /> + <BitField start="8" size="1" name="POS2_INT" description="When 1, the POS2_Int interrupt is enabled." /> + <BitField start="9" size="1" name="REV0_INT" description="When 1, the REV0_Int interrupt is enabled." /> + <BitField start="10" size="1" name="POS0REV_INT" description="When 1, the POS0REV_Int interrupt is enabled." /> + <BitField start="11" size="1" name="POS1REV_INT" description="When 1, the POS1REV_Int interrupt is enabled." /> + <BitField start="12" size="1" name="POS2REV_INT" description="When 1, the POS2REV_Int interrupt is enabled." /> + <BitField start="13" size="1" name="REV1_INT" description="When 1, the REV1_Int interrupt is enabled." /> + <BitField start="14" size="1" name="REV2_INT" description="When 1, the REV2_Int interrupt is enabled." /> + <BitField start="15" size="1" name="MAXPOS_INT" description="When 1, the MAXPOS_Int interrupt is enabled." /> + <BitField start="16" size="16" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0xFDC" size="4" name="IES" access="WriteOnly" description="Interrupt enable set register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="INX_INT" description="Writing a 1 enables the INX_Int interrupt in the QEIIE register." /> + <BitField start="1" size="1" name="TIM_INT" description="Writing a 1 enables the TIN_Int interrupt in the QEIIE register." /> + <BitField start="2" size="1" name="VELC_INT" description="Writing a 1 enables the VELC_Int interrupt in the QEIIE register." /> + <BitField start="3" size="1" name="DIR_INT" description="Writing a 1 enables the DIR_Int interrupt in the QEIIE register." /> + <BitField start="4" size="1" name="ERR_INT" description="Writing a 1 enables the ERR_Int interrupt in the QEIIE register." /> + <BitField start="5" size="1" name="ENCLK_INT" description="Writing a 1 enables the ENCLK_Int interrupt in the QEIIE register." /> + <BitField start="6" size="1" name="POS0_INT" description="Writing a 1 enables the POS0_Int interrupt in the QEIIE register." /> + <BitField start="7" size="1" name="POS1_INT" description="Writing a 1 enables the POS1_Int interrupt in the QEIIE register." /> + <BitField start="8" size="1" name="POS2_INT" description="Writing a 1 enables the POS2_Int interrupt in the QEIIE register." /> + <BitField start="9" size="1" name="REV0_INT" description="Writing a 1 enables the REV0_Int interrupt in the QEIIE register." /> + <BitField start="10" size="1" name="POS0REV_INT" description="Writing a 1 enables the POS0REV_Int interrupt in the QEIIE register." /> + <BitField start="11" size="1" name="POS1REV_INT" description="Writing a 1 enables the POS1REV_Int interrupt in the QEIIE register." /> + <BitField start="12" size="1" name="POS2REV_INT" description="Writing a 1 enables the POS2REV_Int interrupt in the QEIIE register." /> + <BitField start="13" size="1" name="REV1_INT" description="Writing a 1 enables the REV1_Int interrupt in the QEIIE register." /> + <BitField start="14" size="1" name="REV2_INT" description="Writing a 1 enables the REV2_Int interrupt in the QEIIE register." /> + <BitField start="15" size="1" name="MAXPOS_INT" description="Writing a 1 enables the MAXPOS_Int interrupt in the QEIIE register." /> + <BitField start="16" size="16" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0xFD8" size="4" name="IEC" access="WriteOnly" description="Interrupt enable clear register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="INX_INT" description="Writing a 1 disables the INX_Int interrupt in the QEIIE register." /> + <BitField start="1" size="1" name="TIM_INT" description="Writing a 1 disables the TIN_Int interrupt in the QEIIE register." /> + <BitField start="2" size="1" name="VELC_INT" description="Writing a 1 disables the VELC_Int interrupt in the QEIIE register." /> + <BitField start="3" size="1" name="DIR_INT" description="Writing a 1 disables the DIR_Int interrupt in the QEIIE register." /> + <BitField start="4" size="1" name="ERR_INT" description="Writing a 1 disables the ERR_Int interrupt in the QEIIE register." /> + <BitField start="5" size="1" name="ENCLK_INT" description="Writing a 1 disables the ENCLK_Int interrupt in the QEIIE register." /> + <BitField start="6" size="1" name="POS0_INT" description="Writing a 1 disables the POS0_Int interrupt in the QEIIE register." /> + <BitField start="7" size="1" name="POS1_INT" description="Writing a 1 disables the POS1_Int interrupt in the QEIIE register." /> + <BitField start="8" size="1" name="POS2_INT" description="Writing a 1 disables the POS2_Int interrupt in the QEIIE register." /> + <BitField start="9" size="1" name="REV0_INT" description="Writing a 1 disables the REV0_Int interrupt in the QEIIE register." /> + <BitField start="10" size="1" name="POS0REV_INT" description="Writing a 1 disables the POS0REV_Int interrupt in the QEIIE register." /> + <BitField start="11" size="1" name="POS1REV_INT" description="Writing a 1 disables the POS1REV_Int interrupt in the QEIIE register." /> + <BitField start="12" size="1" name="POS2REV_INT" description="Writing a 1 disables the POS2REV_Int interrupt in the QEIIE register." /> + <BitField start="13" size="1" name="REV1_INT" description="Writing a 1 disables the REV1_Int interrupt in the QEIIE register." /> + <BitField start="14" size="1" name="REV2_INT" description="Writing a 1 disables the REV2_Int interrupt in the QEIIE register." /> + <BitField start="15" size="1" name="MAXPOS_INT" description="Writing a 1 disables the MAXPOS_Int interrupt in the QEIIE register." /> + <BitField start="16" size="16" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + </RegisterGroup> + <RegisterGroup name="SYSCON" start="0x400FC000" description="System and clock control"> + <Register start="+0x000" size="4" name="FLASHCFG" access="Read/Write" description="Flash Accelerator Configuration Register. Controls flash access timing." reset_value="0x303A" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="12" name="RESERVED" description="Reserved, user software should not change these bits from the reset value." /> + <BitField start="12" size="4" name="FLASHTIM" description="Flash access time. The value of this field plus 1 gives the number of CPU clocks used for a flash access. Warning: improper setting of this value may result in incorrect operation of the device. Other values are reserved."> + <Enum name="1CLK" start="0x0" description="Flash accesses use 1 CPU clock. Use for up to 20 MHz CPU clock." /> + <Enum name="2CLK" start="0x1" description="Flash accesses use 2 CPU clocks. Use for up to 40 MHz CPU clock." /> + <Enum name="3CLK" start="0x2" description="Flash accesses use 3 CPU clocks. Use for up to 60 MHz CPU clock." /> + <Enum name="4CLK" start="0x3" description="Flash accesses use 4 CPU clocks. Use for up to 80 MHz CPU clock." /> + <Enum name="5CLK" start="0x4" description="Flash accesses use 5 CPU clocks. Use for up to 100 MHz CPU clock. Use for up to 120 Mhz for LPC1759 and LPC1769 only." /> + <Enum name="6CLK" start="0x5" description="Flash accesses use 6 CPU clocks. This safe setting will work under any conditions." /> + </BitField> + <BitField start="16" size="16" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x080" size="4" name="PLL0CON" access="Read/Write" description="PLL0 Control Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="PLLE0" description="PLL0 Enable. When one, and after a valid PLL0 feed, this bit will activate PLL0 and allow it to lock to the requested frequency. See PLL0STAT register." /> + <BitField start="1" size="1" name="PLLC0" description="PLL0 Connect. Setting PLLC0 to one after PLL0 has been enabled and locked, then followed by a valid PLL0 feed sequence causes PLL0 to become the clock source for the CPU, AHB peripherals, and used to derive the clocks for APB peripherals. The PLL0 output may potentially be used to clock the USB subsystem if the frequency is 48 MHz. See PLL0STAT register." /> + <BitField start="2" size="30" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x084" size="4" name="PLL0CFG" access="Read/Write" description="PLL0 Configuration Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="15" name="MSEL0" description="PLL0 Multiplier value. Supplies the value M in PLL0 frequency calculations. The value stored here is M - 1. Note: Not all values of M are needed, and therefore some are not supported by hardware." /> + <BitField start="15" size="1" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + <BitField start="16" size="8" name="NSEL0" description="PLL0 Pre-Divider value. Supplies the value N in PLL0 frequency calculations. The value stored here is N - 1. Supported values for N are 1 through 32." /> + <BitField start="24" size="8" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x088" size="4" name="PLL0STAT" access="ReadOnly" description="PLL0 Status Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="15" name="MSEL0" description="Read-back for the PLL0 Multiplier value. This is the value currently used by PLL0, and is one less than the actual multiplier." /> + <BitField start="15" size="1" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + <BitField start="16" size="8" name="NSEL0" description="Read-back for the PLL0 Pre-Divider value. This is the value currently used by PLL0, and is one less than the actual divider." /> + <BitField start="24" size="1" name="PLLE0_STAT" description="Read-back for the PLL0 Enable bit. This bit reflects the state of the PLEC0 bit in PLL0CON after a valid PLL0 feed. When one, PLL0 is currently enabled. When zero, PLL0 is turned off. This bit is automatically cleared when Power-down mode is entered." /> + <BitField start="25" size="1" name="PLLC0_STAT" description="Read-back for the PLL0 Connect bit. This bit reflects the state of the PLLC0 bit in PLL0CON after a valid PLL0 feed. When PLLC0 and PLLE0 are both one, PLL0 is connected as the clock source for the CPU. When either PLLC0 or PLLE0 is zero, PLL0 is bypassed. This bit is automatically cleared when Power-down mode is entered." /> + <BitField start="26" size="1" name="PLOCK0" description="Reflects the PLL0 Lock status. When zero, PLL0 is not locked. When one, PLL0 is locked onto the requested frequency. See text for details." /> + <BitField start="27" size="5" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x08C" size="4" name="PLL0FEED" access="WriteOnly" description="PLL0 Feed Register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="8" name="PLL0FEED" description="The PLL0 feed sequence must be written to this register in order for PLL0 configuration and control register changes to take effect." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x0A0" size="4" name="PLL1CON" access="Read/Write" description="PLL1 Control Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="PLLE1" description="PLL1 Enable. When one, and after a valid PLL1 feed, this bit will activate PLL1 and allow it to lock to the requested frequency." /> + <BitField start="1" size="1" name="PLLC1" description="PLL1 Connect. Setting PLLC to one after PLL1 has been enabled and locked, then followed by a valid PLL1 feed sequence causes PLL1 to become the clock source for the USB subsystem via the USB clock divider. See PLL1STAT register." /> + <BitField start="2" size="30" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x0A4" size="4" name="PLL1CFG" access="Read/Write" description="PLL1 Configuration Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="MSEL1" description="PLL1 Multiplier value. Supplies the value M in the PLL1 frequency calculations." /> + <BitField start="5" size="2" name="PSEL1" description="PLL1 Divider value. Supplies the value P in the PLL1 frequency calculations." /> + <BitField start="7" size="25" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x0A8" size="4" name="PLL1STAT" access="ReadOnly" description="PLL1 Status Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="MSEL1" description="Read-back for the PLL1 Multiplier value. This is the value currently used by PLL1." /> + <BitField start="5" size="2" name="PSEL1" description="Read-back for the PLL1 Divider value. This is the value currently used by PLL1." /> + <BitField start="7" size="1" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + <BitField start="8" size="1" name="PLLE1_STAT" description="Read-back for the PLL1 Enable bit. When one, PLL1 is currently activated. When zero, PLL1 is turned off. This bit is automatically cleared when Power-down mode is activated." /> + <BitField start="9" size="1" name="PLLC1_STAT" description="Read-back for the PLL1 Connect bit. When PLLC and PLLE are both one, PLL1 is connected as the clock source for the microcontroller. When either PLLC or PLLE is zero, PLL1 is bypassed and the oscillator clock is used directly by the microcontroller. This bit is automatically cleared when Power-down mode is activated." /> + <BitField start="10" size="1" name="PLOCK1" description="Reflects the PLL1 Lock status. When zero, PLL1 is not locked. When one, PLL1 is locked onto the requested frequency." /> + <BitField start="11" size="21" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x0AC" size="4" name="PLL1FEED" access="WriteOnly" description="PLL1 Feed Register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="8" name="PLL1FEED" description="The PLL1 feed sequence must be written to this register in order for PLL1 configuration and control register changes to take effect." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x0C0" size="4" name="PCON" access="Read/Write" description="Power Control Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="PM0" description="Power mode control bit 0. This bit controls entry to the Power-down mode." /> + <BitField start="1" size="1" name="PM1" description="Power mode control bit 1. This bit controls entry to the Deep Power-down mode." /> + <BitField start="2" size="1" name="BODRPM" description="Brown-Out Reduced Power Mode. When BODRPM is 1, the Brown-Out Detect circuitry will be turned off when chip Power-down mode or Deep Sleep mode is entered, resulting in a further reduction in power usage. However, the possibility of using Brown-Out Detect as a wake-up source from the reduced power mode will be lost. When 0, the Brown-Out Detect function remains active during Power-down and Deep Sleep modes. See the System Control Block chapter for details of Brown-Out detection." /> + <BitField start="3" size="1" name="BOGD" description="Brown-Out Global Disable. When BOGD is 1, the Brown-Out Detect circuitry is fully disabled at all times, and does not consume power. When 0, the Brown-Out Detect circuitry is enabled. See the System Control Block chapter for details of Brown-Out detection. Note: the Brown-Out Reset Disable (BORD, in this register) and the Brown-Out Interrupt (xx) must be disabled when software changes the value of this bit." /> + <BitField start="4" size="1" name="BORD" description="Brown-Out Reset Disable. When BORD is 1, the BOD will not reset the device when the VDD(REG)(3V3) voltage dips goes below the BOD reset trip level. The Brown-Out interrupt is not affected. When BORD is 0, the BOD reset is enabled." /> + <BitField start="3" size="5" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + <BitField start="8" size="1" name="SMFLAG" description="Sleep Mode entry flag. Set when the Sleep mode is successfully entered. Cleared by software writing a one to this bit." /> + <BitField start="9" size="1" name="DSFLAG" description="Deep Sleep entry flag. Set when the Deep Sleep mode is successfully entered. Cleared by software writing a one to this bit." /> + <BitField start="10" size="1" name="PDFLAG" description="Power-down entry flag. Set when the Power-down mode is successfully entered. Cleared by software writing a one to this bit." /> + <BitField start="11" size="1" name="DPDFLAG" description="Deep Power-down entry flag. Set when the Deep Power-down mode is successfully entered. Cleared by software writing a one to this bit." /> + <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x0C4" size="4" name="PCONP" access="Read/Write" description="Power Control for Peripherals Register" reset_value="0x03BE" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RESERVED" description="Reserved." /> + <BitField start="1" size="1" name="PCTIM0" description="Timer/Counter 0 power/clock control bit." /> + <BitField start="2" size="1" name="PCTIM1" description="Timer/Counter 1 power/clock control bit." /> + <BitField start="3" size="1" name="PCUART0" description="UART0 power/clock control bit." /> + <BitField start="4" size="1" name="PCUART1" description="UART1 power/clock control bit." /> + <BitField start="5" size="1" name="RESERVED" description="Reserved." /> + <BitField start="6" size="1" name="PCPWM1" description="PWM1 power/clock control bit." /> + <BitField start="7" size="1" name="PCI2C0" description="The I2C0 interface power/clock control bit." /> + <BitField start="8" size="1" name="PCSPI" description="The SPI interface power/clock control bit." /> + <BitField start="9" size="1" name="PCRTC" description="The RTC power/clock control bit." /> + <BitField start="10" size="1" name="PCSSP1" description="The SSP 1 interface power/clock control bit." /> + <BitField start="11" size="1" name="RESERVED" description="Reserved." /> + <BitField start="12" size="1" name="PCADC" description="A/D converter (ADC) power/clock control bit. Note: Clear the PDN bit in the AD0CR before clearing this bit, and set this bit before setting PDN." /> + <BitField start="13" size="1" name="PCCAN1" description="CAN Controller 1 power/clock control bit." /> + <BitField start="14" size="1" name="PCCAN2" description="CAN Controller 2 power/clock control bit." /> + <BitField start="15" size="1" name="PCGPIO" description="Power/clock control bit for IOCON, GPIO, and GPIO interrupts." /> + <BitField start="16" size="1" name="PCRIT" description="Repetitive Interrupt Timer power/clock control bit." /> + <BitField start="17" size="1" name="PCMCPWM" description="Motor Control PWM" /> + <BitField start="18" size="1" name="PCQEI" description="Quadrature Encoder Interface power/clock control bit." /> + <BitField start="19" size="1" name="PCI2C1" description="The I2C1 interface power/clock control bit." /> + <BitField start="20" size="1" name="RESERVED" description="Reserved." /> + <BitField start="21" size="1" name="PCSSP0" description="The SSP0 interface power/clock control bit." /> + <BitField start="22" size="1" name="PCTIM2" description="Timer 2 power/clock control bit." /> + <BitField start="23" size="1" name="PCTIM3" description="Timer 3 power/clock control bit." /> + <BitField start="24" size="1" name="PCUART2" description="UART 2 power/clock control bit." /> + <BitField start="25" size="1" name="PCUART3" description="UART 3 power/clock control bit." /> + <BitField start="26" size="1" name="PCI2C2" description="I2C interface 2 power/clock control bit." /> + <BitField start="27" size="1" name="PCI2S" description="I2S interface power/clock control bit." /> + <BitField start="28" size="1" name="RESERVED" description="Reserved." /> + <BitField start="29" size="1" name="PCGPDMA" description="GPDMA function power/clock control bit." /> + <BitField start="30" size="1" name="PCENET" description="Ethernet block power/clock control bit." /> + <BitField start="31" size="1" name="PCUSB" description="USB interface power/clock control bit." /> + </Register> + <Register start="+0x104" size="4" name="CCLKCFG" access="Read/Write" description="CPU Clock Configuration Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="CCLKSEL" description="Selects the divide value for creating the CPU clock (CCLK) from the PLL0 output. 0 = pllclk is divided by 1 to produce the CPU clock. This setting is not allowed when the PLL0 is connected, because the rate would always be greater than the maximum allowed CPU clock. 1 = pllclk is divided by 2 to produce the CPU clock. This setting is not allowed when the PLL0 is connected, because the rate would always be greater than the maximum allowed CPU clock. 2 = pllclk is divided by 3 to produce the CPU clock. 3 = pllclk is divided by 4 to produce the CPU clock. ... 255 = pllclk is divided by 256 to produce the CPU clock." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x108" size="4" name="USBCLKCFG" access="Read/Write" description="USB Clock Configuration Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="4" name="USBSEL" description="Selects the divide value for creating the USB clock from the PLL0 output. Only the values shown below can produce even number multiples of 48 MHz from the PLL0 output. Warning: Improper setting of this value will result in incorrect operation of the USB interface. 5 = PLL0 output is divided by 6. PLL0 output must be 288 MHz. 7 = PLL0 output is divided by 8. PLL0 output must be 384 MHz. 9 = PLL0 output is divided by 10. PLL0 output must be 480 MHz." /> + <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x10C" size="4" name="CLKSRCSEL" access="Read/Write" description="Clock Source Select Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="CLKSRC" description="Selects the clock source for PLL0 as follows. Warning: Improper setting of this value, or an incorrect sequence of changing this value may result in incorrect operation of the device."> + <Enum name="SELECTS_THE_INTERNAL" start="0x0" description="Selects the Internal RC oscillator as the PLL0 clock source (default)." /> + <Enum name="SELECTS_THE_MAIN_OSC" start="0x1" description="Selects the main oscillator as the PLL0 clock source. Select the main oscillator as PLL0 clock source if the PLL0 clock output is used for USB or for CAN with baudrates > 100 kBit/s." /> + <Enum name="SELECTS_THE_RTC_OSCI" start="0x2" description="Selects the RTC oscillator as the PLL0 clock source." /> + <Enum name="RESERVED" start="0x3" description="Reserved, do not use this setting." /> + </BitField> + <BitField start="2" size="30" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x110" size="4" name="CANSLEEPCLR" access="Read/Write" description="Allows clearing the current CAN channel sleep state as well as reading that state." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="1" size="1" name="CAN1SLEEP" description="Sleep status and control for CAN channel 1. Read: when 1, indicates that CAN channel 1 is in the sleep mode. Write: writing a 1 causes clocks to be restored to CAN channel 1." /> + <BitField start="2" size="1" name="CAN2SLEEP" description="Sleep status and control for CAN channel 2. Read: when 1, indicates that CAN channel 2 is in the sleep mode. Write: writing a 1 causes clocks to be restored to CAN channel 2." /> + <BitField start="3" size="29" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x114" size="4" name="CANWAKEFLAGS" access="Read/Write" description="Allows reading the wake-up state of the CAN channels." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="1" size="1" name="CAN1WAKE" description="Wake-up status for CAN channel 1. Read: when 1, indicates that a falling edge has occurred on the receive data line of CAN channel 1. Write: writing a 1 clears this bit." /> + <BitField start="2" size="1" name="CAN2WAKE" description="Wake-up status for CAN channel 2. Read: when 1, indicates that a falling edge has occurred on the receive data line of CAN channel 2. Write: writing a 1 clears this bit." /> + <BitField start="3" size="29" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x140" size="4" name="EXTINT" access="Read/Write" description="External Interrupt Flag Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="EINT0" description="In level-sensitive mode, this bit is set if the EINT0 function is selected for its pin, and the pin is in its active state. In edge-sensitive mode, this bit is set if the EINT0 function is selected for its pin, and the selected edge occurs on the pin. This bit is cleared by writing a one to it, except in level sensitive mode when the pin is in its active state." /> + <BitField start="1" size="1" name="EINT1" description="In level-sensitive mode, this bit is set if the EINT1 function is selected for its pin, and the pin is in its active state. In edge-sensitive mode, this bit is set if the EINT1 function is selected for its pin, and the selected edge occurs on the pin. This bit is cleared by writing a one to it, except in level sensitive mode when the pin is in its active state." /> + <BitField start="2" size="1" name="EINT2" description="In level-sensitive mode, this bit is set if the EINT2 function is selected for its pin, and the pin is in its active state. In edge-sensitive mode, this bit is set if the EINT2 function is selected for its pin, and the selected edge occurs on the pin. This bit is cleared by writing a one to it, except in level sensitive mode when the pin is in its active state." /> + <BitField start="3" size="1" name="EINT3" description="In level-sensitive mode, this bit is set if the EINT3 function is selected for its pin, and the pin is in its active state. In edge-sensitive mode, this bit is set if the EINT3 function is selected for its pin, and the selected edge occurs on the pin. This bit is cleared by writing a one to it, except in level sensitive mode when the pin is in its active state." /> + <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x148" size="4" name="EXTMODE" access="Read/Write" description="External Interrupt Mode register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="EXTMODE0" description="External interrupt 0 EINT0 mode."> + <Enum name="LEVEL_SENSITIVE" start="0" description="Level-sensitive. Level-sensitivity is selected for EINT0." /> + <Enum name="EDGE_SENSITIVE" start="1" description="Edge-sensitive. EINT0 is edge sensitive." /> + </BitField> + <BitField start="1" size="1" name="EXTMODE1" description="External interrupt 1 EINT1 mode."> + <Enum name="LEVEL_SENSITIVE" start="0" description="Level-sensitive. Level-sensitivity is selected for EINT1." /> + <Enum name="EDGE_SENSITIVE" start="1" description="Edge-sensitive. EINT1 is edge sensitive." /> + </BitField> + <BitField start="2" size="1" name="EXTMODE2" description="External interrupt 2 EINT2 mode."> + <Enum name="LEVEL_SENSITIVE" start="0" description="Level-sensitive. Level-sensitivity is selected for EINT2." /> + <Enum name="EDGE_SENSITIVE" start="1" description="Edge-sensitive. EINT2 is edge sensitive." /> + </BitField> + <BitField start="3" size="1" name="EXTMODE3" description="External interrupt 3 EINT3 mode."> + <Enum name="LEVEL_SENSITIVE" start="0" description="Level-sensitive. Level-sensitivity is selected for EINT3." /> + <Enum name="EDGE_SENSITIVE" start="1" description="Edge-sensitive. EINT3 is edge sensitive." /> + </BitField> + <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x14C" size="4" name="EXTPOLAR" access="Read/Write" description="External Interrupt Polarity Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="EXTPOLAR0" description="External interrupt 0 EINT0 polarity."> + <Enum name="FALLING_EDGE" start="0" description="Falling edge. EINT0 is low-active or falling-edge sensitive (depending on EXTMODE0)." /> + <Enum name="RISING_EDGE" start="1" description="Rising edge. EINT0 is high-active or rising-edge sensitive (depending on EXTMODE0)." /> + </BitField> + <BitField start="1" size="1" name="EXTPOLAR1" description="External interrupt 1 EINT1 polarity."> + <Enum name="FALLING_EDGE" start="0" description="Falling edge. EINT1 is low-active or falling-edge sensitive (depending on EXTMODE1)." /> + <Enum name="RISING_EDGE" start="1" description="Rising edge. EINT1 is high-active or rising-edge sensitive (depending on EXTMODE1)." /> + </BitField> + <BitField start="2" size="1" name="EXTPOLAR2" description="External interrupt 2 EINT2 polarity."> + <Enum name="FALLING_EDGE" start="0" description="Falling edge. EINT2 is low-active or falling-edge sensitive (depending on EXTMODE2)." /> + <Enum name="RISING_EDGE" start="1" description="Rising edge. EINT2 is high-active or rising-edge sensitive (depending on EXTMODE2)." /> + </BitField> + <BitField start="3" size="1" name="EXTPOLAR3" description="External interrupt 3 EINT3 polarity."> + <Enum name="FALLING_EDGE" start="0" description="Falling edge. EINT3 is low-active or falling-edge sensitive (depending on EXTMODE3)." /> + <Enum name="RISING_EDGE" start="1" description="Rising edge. EINT3 is high-active or rising-edge sensitive (depending on EXTMODE3)." /> + </BitField> + <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x180" size="4" name="RSID" access="Read/Write" description="Reset Source Identification Register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="POR" description="Assertion of the POR signal sets this bit, and clears all of the other bits in this register. But if another Reset signal (e.g., External Reset) remains asserted after the POR signal is negated, then its bit is set. This bit is not affected by any of the other sources of Reset." /> + <BitField start="1" size="1" name="EXTR" description="Assertion of the RESET signal sets this bit. This bit is cleared only by software or POR." /> + <BitField start="2" size="1" name="WDTR" description="This bit is set when the Watchdog Timer times out and the WDTRESET bit in the Watchdog Mode Register is 1. This bit is cleared only by software or POR." /> + <BitField start="3" size="1" name="BODR" description="This bit is set when the VDD(REG)(3V3) voltage reaches a level below the BOD reset trip level (typically 1.85 V under nominal room temperature conditions). If the VDD(REG)(3V3) voltage dips from the normal operating range to below the BOD reset trip level and recovers, the BODR bit will be set to 1. If the VDD(REG)(3V3) voltage dips from the normal operating range to below the BOD reset trip level and continues to decline to the level at which POR is asserted (nominally 1 V), the BODR bit is cleared. If the VDD(REG)(3V3) voltage rises continuously from below 1 V to a level above the BOD reset trip level, the BODR will be set to 1. This bit is cleared only by software or POR. Note: Only in the case where a reset occurs and the POR = 0, the BODR bit indicates if the VDD(REG)(3V3) voltage was below the BOD reset trip level or not." /> + <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x1A0" size="4" name="SCS" access="Read/Write" description="System control and status" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="4" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + <BitField start="4" size="1" name="OSCRANGE" description="Main oscillator range select."> + <Enum name="LOW" start="0" description="Low. The frequency range of the main oscillator is 1 MHz to 20 MHz." /> + <Enum name="HIGH" start="1" description="High. The frequency range of the main oscillator is 15 MHz to 25 MHz." /> + </BitField> + <BitField start="5" size="1" name="OSCEN" description="Main oscillator enable."> + <Enum name="DISABLED" start="0" description="Disabled. The main oscillator is disabled." /> + <Enum name="ENABLED" start="1" description="Enabled.The main oscillator is enabled, and will start up if the correct external circuitry is connected to the XTAL1 and XTAL2 pins." /> + </BitField> + <BitField start="6" size="1" name="OSCSTAT" description="Main oscillator status."> + <Enum name="NOT_READY" start="0" description="Not ready. The main oscillator is not ready to be used as a clock source." /> + <Enum name="READY" start="1" description="Ready. The main oscillator is ready to be used as a clock source. The main oscillator must be enabled via the OSCEN bit." /> + </BitField> + <BitField start="7" size="25" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x1A8" size="4" name="PCLKSEL0" access="Read/Write" description="Peripheral Clock Selection register 0." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="PCLK_WDT" description="Peripheral clock selection for WDT."> + <Enum name="CCLK_DIV_4" start="0x0" description="CCLK div 4. PCLK_peripheral = CCLK/4" /> + <Enum name="CCLK" start="0x1" description="CCLK. PCLK_peripheral = CCLK" /> + <Enum name="CCLK_DIV_2" start="0x2" description="CCLK div 2. PCLK_peripheral = CCLK/2" /> + <Enum name="CCLK_DIV_8" start="0x3" description="CCLK div 8. PCLK_peripheral = CCLK/8" /> + </BitField> + <BitField start="2" size="2" name="PCLK_TIMER0" description="Peripheral clock selection for TIMER0."> + <Enum name="CCLK_DIV_4" start="0x0" description="CCLK div 4. PCLK_peripheral = CCLK/4" /> + <Enum name="CCLK" start="0x1" description="CCLK. PCLK_peripheral = CCLK" /> + <Enum name="CCLK_DIV_2" start="0x2" description="CCLK div 2. PCLK_peripheral = CCLK/2" /> + <Enum name="CCLK_DIV_8" start="0x3" description="CCLK div 8. PCLK_peripheral = CCLK/8" /> + </BitField> + <BitField start="4" size="2" name="PCLK_TIMER1" description="Peripheral clock selection for TIMER1."> + <Enum name="CCLK_DIV_4" start="0x0" description="CCLK div 4. PCLK_peripheral = CCLK/4" /> + <Enum name="CCLK" start="0x1" description="CCLK. PCLK_peripheral = CCLK" /> + <Enum name="CCLK_DIV_2" start="0x2" description="CCLK div 2. PCLK_peripheral = CCLK/2" /> + <Enum name="CCLK_DIV_8" start="0x3" description="CCLK div 8. PCLK_peripheral = CCLK/8" /> + </BitField> + <BitField start="6" size="2" name="PCLK_UART0" description="Peripheral clock selection for UART0."> + <Enum name="CCLK_DIV_4" start="0x0" description="CCLK div 4. PCLK_peripheral = CCLK/4" /> + <Enum name="CCLK" start="0x1" description="CCLK. PCLK_peripheral = CCLK" /> + <Enum name="CCLK_DIV_2" start="0x2" description="CCLK div 2. PCLK_peripheral = CCLK/2" /> + <Enum name="CCLK_DIV_8" start="0x3" description="CCLK div 8. PCLK_peripheral = CCLK/8" /> + </BitField> + <BitField start="8" size="2" name="PCLK_UART1" description="Peripheral clock selection for UART1."> + <Enum name="CCLK_DIV_4" start="0x0" description="CCLK div 4. PCLK_peripheral = CCLK/4" /> + <Enum name="CCLK" start="0x1" description="CCLK. PCLK_peripheral = CCLK" /> + <Enum name="CCLK_DIV_2" start="0x2" description="CCLK div 2. PCLK_peripheral = CCLK/2" /> + <Enum name="CCLK_DIV_8" start="0x3" description="CCLK div 8. PCLK_peripheral = CCLK/8" /> + </BitField> + <BitField start="10" size="2" name="RESERVED" description="Reserved." /> + <BitField start="12" size="2" name="PCLK_PWM1" description="Peripheral clock selection for PWM1."> + <Enum name="CCLK_DIV_4" start="0x0" description="CCLK div 4. PCLK_peripheral = CCLK/4" /> + <Enum name="CCLK" start="0x1" description="CCLK. PCLK_peripheral = CCLK" /> + <Enum name="CCLK_DIV_2" start="0x2" description="CCLK div 2. PCLK_peripheral = CCLK/2" /> + <Enum name="CCLK_DIV_8" start="0x3" description="CCLK div 8. PCLK_peripheral = CCLK/8" /> + </BitField> + <BitField start="14" size="2" name="PCLK_I2C0" description="Peripheral clock selection for I2C0."> + <Enum name="CCLK_DIV_4" start="0x0" description="CCLK div 4. PCLK_peripheral = CCLK/4" /> + <Enum name="CCLK" start="0x1" description="CCLK. PCLK_peripheral = CCLK" /> + <Enum name="CCLK_DIV_2" start="0x2" description="CCLK div 2. PCLK_peripheral = CCLK/2" /> + <Enum name="CCLK_DIV_8" start="0x3" description="CCLK div 8. PCLK_peripheral = CCLK/8" /> + </BitField> + <BitField start="16" size="2" name="PCLK_SPI" description="Peripheral clock selection for SPI."> + <Enum name="CCLK_DIV_4" start="0x0" description="CCLK div 4. PCLK_peripheral = CCLK/4" /> + <Enum name="CCLK" start="0x1" description="CCLK. PCLK_peripheral = CCLK" /> + <Enum name="CCLK_DIV_2" start="0x2" description="CCLK div 2. PCLK_peripheral = CCLK/2" /> + <Enum name="CCLK_DIV_8" start="0x3" description="CCLK div 8. PCLK_peripheral = CCLK/8" /> + </BitField> + <BitField start="18" size="2" name="RESERVED" description="Reserved." /> + <BitField start="20" size="2" name="PCLK_SSP1" description="Peripheral clock selection for SSP1."> + <Enum name="CCLK_DIV_4" start="0x0" description="CCLK div 4. PCLK_peripheral = CCLK/4" /> + <Enum name="CCLK" start="0x1" description="CCLK. PCLK_peripheral = CCLK" /> + <Enum name="CCLK_DIV_2" start="0x2" description="CCLK div 2. PCLK_peripheral = CCLK/2" /> + <Enum name="CCLK_DIV_8" start="0x3" description="CCLK div 8. PCLK_peripheral = CCLK/8" /> + </BitField> + <BitField start="22" size="2" name="PCLK_DAC" description="Peripheral clock selection for DAC."> + <Enum name="CCLK_DIV_4" start="0x0" description="CCLK div 4. PCLK_peripheral = CCLK/4" /> + <Enum name="CCLK" start="0x1" description="CCLK. PCLK_peripheral = CCLK" /> + <Enum name="CCLK_DIV_2" start="0x2" description="CCLK div 2. PCLK_peripheral = CCLK/2" /> + <Enum name="CCLK_DIV_8" start="0x3" description="CCLK div 8. PCLK_peripheral = CCLK/8" /> + </BitField> + <BitField start="24" size="2" name="PCLK_ADC" description="Peripheral clock selection for ADC."> + <Enum name="CCLK_DIV_4" start="0x0" description="CCLK div 4. PCLK_peripheral = CCLK/4" /> + <Enum name="CCLK" start="0x1" description="CCLK. PCLK_peripheral = CCLK" /> + <Enum name="CCLK_DIV_2" start="0x2" description="CCLK div 2. PCLK_peripheral = CCLK/2" /> + <Enum name="CCLK_DIV_8" start="0x3" description="CCLK div 8. PCLK_peripheral = CCLK/8" /> + </BitField> + <BitField start="26" size="2" name="PCLK_CAN1" description="Peripheral clock selection for CAN1.PCLK_CAN1 and PCLK_CAN2 must have the same PCLK divide value when the CAN function is used."> + <Enum name="CCLK_DIV_4" start="0x0" description="CCLK div 4. PCLK_peripheral = CCLK/4" /> + <Enum name="CCLK" start="0x1" description="CCLK. PCLK_peripheral = CCLK" /> + <Enum name="CCLK_DIV_2" start="0x2" description="CCLK div 2. PCLK_peripheral = CCLK/2" /> + <Enum name="CCLK_DIV_6" start="0x3" description="CCLK div 6. PCLK_peripheral = CCLK/6." /> + </BitField> + <BitField start="28" size="2" name="PCLK_CAN2" description="Peripheral clock selection for CAN2.PCLK_CAN1 and PCLK_CAN2 must have the same PCLK divide value when the CAN function is used."> + <Enum name="CCLK_DIV_4" start="0x0" description="CCLK div 4. PCLK_peripheral = CCLK/4" /> + <Enum name="CCLK" start="0x1" description="CCLK. PCLK_peripheral = CCLK" /> + <Enum name="CCLK_DIV_2" start="0x2" description="CCLK div 2. PCLK_peripheral = CCLK/2" /> + <Enum name="CCLK_DIV_6" start="0x3" description="CCLK div 6. PCLK_peripheral = CCLK/6," /> + </BitField> + <BitField start="30" size="2" name="PCLK_ACF" description="Peripheral clock selection for CAN acceptance filtering.PCLK_CAN1 and PCLK_CAN2 must have the same PCLK divide value when the CAN function is used."> + <Enum name="CCLK_DIV_4" start="0x0" description="CCLK div 4. PCLK_peripheral = CCLK/4" /> + <Enum name="CCLK" start="0x1" description="CCLK. PCLK_peripheral = CCLK" /> + <Enum name="CCLK_DIV_2" start="0x2" description="CCLK div 2. PCLK_peripheral = CCLK/2" /> + <Enum name="CCLK_DIV_6" start="0x3" description="CCLK div 6. PCLK_peripheral = CCLK/6" /> + </BitField> + </Register> + <Register start="+0x1AC" size="4" name="PCLKSEL1" access="Read/Write" description="Peripheral Clock Selection register 1." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="PCLK_QEI" description="Peripheral clock selection for the Quadrature Encoder Interface."> + <Enum name="CCLK_DIV_4" start="0x0" description="CCLK div 4. PCLK_peripheral = CCLK/4" /> + <Enum name="CCLK" start="0x1" description="CCLK. PCLK_peripheral = CCLK" /> + <Enum name="CCLK_DIV_2" start="0x2" description="CCLK div 2. PCLK_peripheral = CCLK/2" /> + <Enum name="CCLK_DIV_8" start="0x3" description="CCLK div 8. PCLK_peripheral = CCLK/8" /> + </BitField> + <BitField start="2" size="2" name="PCLK_GPIOINT" description="Peripheral clock selection for GPIO interrupts."> + <Enum name="CCLK_DIV_4" start="0x0" description="CCLK div 4. PCLK_peripheral = CCLK/4" /> + <Enum name="CCLK" start="0x1" description="CCLK. PCLK_peripheral = CCLK" /> + <Enum name="CCLK_DIV_2" start="0x2" description="CCLK div 2. PCLK_peripheral = CCLK/2" /> + <Enum name="CCLK_DIV_8" start="0x3" description="CCLK div 8. PCLK_peripheral = CCLK/8" /> + </BitField> + <BitField start="4" size="2" name="PCLK_PCB" description="Peripheral clock selection for the Pin Connect block."> + <Enum name="CCLK_DIV_4" start="0x0" description="CCLK div 4. PCLK_peripheral = CCLK/4" /> + <Enum name="CCLK" start="0x1" description="CCLK. PCLK_peripheral = CCLK" /> + <Enum name="CCLK_DIV_2" start="0x2" description="CCLK div 2. PCLK_peripheral = CCLK/2" /> + <Enum name="CCLK_DIV_8" start="0x3" description="CCLK div 8. PCLK_peripheral = CCLK/8" /> + </BitField> + <BitField start="6" size="2" name="PCLK_I2C1" description="Peripheral clock selection for I2C1."> + <Enum name="CCLK_DIV_4" start="0x0" description="CCLK div 4. PCLK_peripheral = CCLK/4" /> + <Enum name="CCLK" start="0x1" description="CCLK. PCLK_peripheral = CCLK" /> + <Enum name="CCLK_DIV_2" start="0x2" description="CCLK div 2. PCLK_peripheral = CCLK/2" /> + <Enum name="CCLK_DIV_8" start="0x3" description="CCLK div 8. PCLK_peripheral = CCLK/8" /> + </BitField> + <BitField start="8" size="2" name="RESERVED" description="Reserved." /> + <BitField start="10" size="2" name="PCLK_SSP0" description="Peripheral clock selection for SSP0."> + <Enum name="CCLK_DIV_4" start="0x0" description="CCLK div 4. PCLK_peripheral = CCLK/4" /> + <Enum name="CCLK" start="0x1" description="CCLK. PCLK_peripheral = CCLK" /> + <Enum name="CCLK_DIV_2" start="0x2" description="CCLK div 2. PCLK_peripheral = CCLK/2" /> + <Enum name="CCLK_DIV_8" start="0x3" description="CCLK div 8. PCLK_peripheral = CCLK/8" /> + </BitField> + <BitField start="12" size="2" name="PCLK_TIMER2" description="Peripheral clock selection for TIMER2."> + <Enum name="CCLK_DIV_4" start="0x0" description="CCLK div 4. PCLK_peripheral = CCLK/4" /> + <Enum name="CCLK" start="0x1" description="CCLK. PCLK_peripheral = CCLK" /> + <Enum name="CCLK_DIV_2" start="0x2" description="CCLK div 2. PCLK_peripheral = CCLK/2" /> + <Enum name="CCLK_DIV_8" start="0x3" description="CCLK div 8. PCLK_peripheral = CCLK/8" /> + </BitField> + <BitField start="14" size="2" name="PCLK_TIMER3" description="Peripheral clock selection for TIMER3."> + <Enum name="CCLK_DIV_4" start="0x0" description="CCLK div 4. PCLK_peripheral = CCLK/4" /> + <Enum name="CCLK" start="0x1" description="CCLK. PCLK_peripheral = CCLK" /> + <Enum name="CCLK_DIV_2" start="0x2" description="CCLK div 2. PCLK_peripheral = CCLK/2" /> + <Enum name="CCLK_DIV_8" start="0x3" description="CCLK div 8. PCLK_peripheral = CCLK/8" /> + </BitField> + <BitField start="16" size="2" name="PCLK_UART2" description="Peripheral clock selection for UART2."> + <Enum name="CCLK_DIV_4" start="0x0" description="CCLK div 4. PCLK_peripheral = CCLK/4" /> + <Enum name="CCLK" start="0x1" description="CCLK. PCLK_peripheral = CCLK" /> + <Enum name="CCLK_DIV_2" start="0x2" description="CCLK div 2. PCLK_peripheral = CCLK/2" /> + <Enum name="CCLK_DIV_8" start="0x3" description="CCLK div 8. PCLK_peripheral = CCLK/8" /> + </BitField> + <BitField start="18" size="2" name="PCLK_UART3" description="Peripheral clock selection for UART3."> + <Enum name="CCLK_DIV_4" start="0x0" description="CCLK div 4. PCLK_peripheral = CCLK/4" /> + <Enum name="CCLK" start="0x1" description="CCLK. PCLK_peripheral = CCLK" /> + <Enum name="CCLK_DIV_2" start="0x2" description="CCLK div 2. PCLK_peripheral = CCLK/2" /> + <Enum name="CCLK_DIV_8" start="0x3" description="CCLK div 8. PCLK_peripheral = CCLK/8" /> + </BitField> + <BitField start="20" size="2" name="PCLK_I2C2" description="Peripheral clock selection for I2C2."> + <Enum name="CCLK_DIV_4" start="0x0" description="CCLK div 4. PCLK_peripheral = CCLK/4" /> + <Enum name="CCLK" start="0x1" description="CCLK. PCLK_peripheral = CCLK" /> + <Enum name="CCLK_DIV_2" start="0x2" description="CCLK div 2. PCLK_peripheral = CCLK/2" /> + <Enum name="CCLK_DIV_8" start="0x3" description="CCLK div 8. PCLK_peripheral = CCLK/8" /> + </BitField> + <BitField start="22" size="2" name="PCLK_I2S" description="Peripheral clock selection for I2S."> + <Enum name="CCLK_DIV_4" start="0x0" description="CCLK div 4. PCLK_peripheral = CCLK/4" /> + <Enum name="CCLK" start="0x1" description="CCLK. PCLK_peripheral = CCLK" /> + <Enum name="CCLK_DIV_2" start="0x2" description="CCLK div 2. PCLK_peripheral = CCLK/2" /> + <Enum name="CCLK_DIV_8" start="0x3" description="CCLK div 8. PCLK_peripheral = CCLK/8" /> + </BitField> + <BitField start="24" size="2" name="RESERVED" description="Reserved." /> + <BitField start="26" size="2" name="PCLK_RIT" description="Peripheral clock selection for Repetitive Interrupt Timer."> + <Enum name="CCLK_DIV_4" start="0x0" description="CCLK div 4. PCLK_peripheral = CCLK/4" /> + <Enum name="CCLK" start="0x1" description="CCLK. PCLK_peripheral = CCLK" /> + <Enum name="CCLK_DIV_2" start="0x2" description="CCLK div 2. PCLK_peripheral = CCLK/2" /> + <Enum name="CCLK_DIV_8" start="0x3" description="CCLK div 8. PCLK_peripheral = CCLK/8" /> + </BitField> + <BitField start="28" size="2" name="PCLK_SYSCON" description="Peripheral clock selection for the System Control block."> + <Enum name="CCLK_DIV_4" start="0x0" description="CCLK div 4. PCLK_peripheral = CCLK/4" /> + <Enum name="CCLK" start="0x1" description="CCLK. PCLK_peripheral = CCLK" /> + <Enum name="CCLK_DIV_2" start="0x2" description="CCLK div 2. PCLK_peripheral = CCLK/2" /> + <Enum name="CCLK_DIV_8" start="0x3" description="CCLK div 8. PCLK_peripheral = CCLK/8" /> + </BitField> + <BitField start="30" size="2" name="PCLK_MC" description="Peripheral clock selection for the Motor Control PWM."> + <Enum name="CCLK_DIV_4" start="0x0" description="CCLK div 4. PCLK_peripheral = CCLK/4" /> + <Enum name="CCLK" start="0x1" description="CCLK. PCLK_peripheral = CCLK" /> + <Enum name="CCLK_DIV_2" start="0x2" description="CCLK div 2. PCLK_peripheral = CCLK/2" /> + <Enum name="CCLK_DIV_8" start="0x3" description="CCLK div 8. PCLK_peripheral = CCLK/8" /> + </BitField> + </Register> + <Register start="+0x1C0" size="4" name="USBINTST" access="Read/Write" description="USB Interrupt Status" reset_value="0x80000000" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="USB_INT_REQ_LP" description="Low priority interrupt line status. This bit is read-only." /> + <BitField start="1" size="1" name="USB_INT_REQ_HP" description="High priority interrupt line status. This bit is read-only." /> + <BitField start="2" size="1" name="USB_INT_REQ_DMA" description="DMA interrupt line status. This bit is read-only." /> + <BitField start="3" size="1" name="USB_HOST_INT" description="USB host interrupt line status. This bit is read-only." /> + <BitField start="4" size="1" name="USB_ATX_INT" description="External ATX interrupt line status. This bit is read-only." /> + <BitField start="5" size="1" name="USB_OTG_INT" description="OTG interrupt line status. This bit is read-only." /> + <BitField start="6" size="1" name="USB_I2C_INT" description="I2C module interrupt line status. This bit is read-only." /> + <BitField start="7" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="8" size="1" name="USB_NEED_CLK" description="USB need clock indicator. This bit is read-only. This bit is set to 1 when USB activity or a change of state on the USB data pins is detected, and it indicates that a PLL supplied clock of 48 MHz is needed. Once USB_NEED_CLK becomes one, it resets to zero 5 ms after the last packet has been received/sent, or 2 ms after the Suspend Change (SUS_CH) interrupt has occurred. A change of this bit from 0 to 1 can wake up the microcontroller if activity on the USB bus is selected to wake up the part from the Power-down mode (see Section 4.7.9 Wake-up from Reduced Power Modes for details). Also see Section 4.5.8 PLLs and Power-down mode and Section 4.7.10 Power Control for Peripherals register (PCONP - 0x400F C0C4) for considerations about the PLL and invoking the Power-down mode. This bit is read-only." /> + <BitField start="9" size="22" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="31" size="1" name="EN_USB_INTS" description="Enable all USB interrupts. When this bit is cleared, the NVIC does not see the ORed output of the USB interrupt lines." /> + </Register> + <Register start="+0x1C4" size="4" name="DMACREQSEL" access="Read/Write" description="Selects between alternative requests on DMA channels 0 through 7 and 10 through 15" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="DMASEL08" description="Selects the DMA request for GPDMA input 8: 0 - uart0 tx 1 - Timer 0 match 0 is selected." /> + <BitField start="1" size="1" name="DMASEL09" description="Selects the DMA request for GPDMA input 9: 0 - uart0 rx 1 - Timer 0 match 1 is selected." /> + <BitField start="2" size="1" name="DMASEL10" description="Selects the DMA request for GPDMA input 10: 0 - uart1 tx is selected. 1 - Timer 1 match 0 is selected." /> + <BitField start="3" size="1" name="DMASEL11" description="Selects the DMA request for GPDMA input 11: 0 - uart1 rx is selected. 1 - Timer 1 match 1 is selected." /> + <BitField start="4" size="1" name="DMASEL12" description="Selects the DMA request for GPDMA input 12: 0 - uart2 tx is selected. 1 - Timer 2 match 0 is selected." /> + <BitField start="5" size="1" name="DMASEL13" description="Selects the DMA request for GPDMA input 13: 0 - uart2 rx is selected. 1 - Timer 2 match 1 is selected." /> + <BitField start="6" size="1" name="DMASEL14" description="Selects the DMA request for GPDMA input 14: 0 - uart3 tx is selected. 1 - I2S channel 0 is selected." /> + <BitField start="7" size="1" name="DMASEL15" description="Selects the DMA request for GPDMA input 15: 0 - uart3 rx is selected. 1 - I2S channel 1 is selected." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x1C8" size="4" name="CLKOUTCFG" access="Read/Write" description="Clock Output Configuration Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="4" name="CLKOUTSEL" description="Selects the clock source for the CLKOUT function. Other values are reserved. Do not use."> + <Enum name="SELECTS_THE_CPU_CLOC" start="0x0" description="Selects the CPU clock as the CLKOUT source." /> + <Enum name="SELECTS_THE_MAIN_OSC" start="0x1" description="Selects the main oscillator as the CLKOUT source." /> + <Enum name="SELECTS_THE_INTERNAL" start="0x2" description="Selects the Internal RC oscillator as the CLKOUT source." /> + <Enum name="SELECTS_THE_USB_CLOC" start="0x3" description="Selects the USB clock as the CLKOUT source." /> + <Enum name="SELECTS_THE_RTC_OSCI" start="0x4" description="Selects the RTC oscillator as the CLKOUT source." /> + </BitField> + <BitField start="4" size="4" name="CLKOUTDIV" description="Integer value to divide the output clock by, minus one. 0 = Clock is divided by 1 1 = Clock is divided by 2. 2 = Clock is divided by 3. ... 15 = Clock is divided by 16." /> + <BitField start="8" size="1" name="CLKOUT_EN" description="CLKOUT enable control, allows switching the CLKOUT source without glitches. Clear to stop CLKOUT on the next falling edge. Set to enable CLKOUT." /> + <BitField start="9" size="1" name="CLKOUT_ACT" description="CLKOUT activity indication. Reads as 1 when CLKOUT is enabled. Read as 0 when CLKOUT has been disabled via the CLKOUT_EN bit and the clock has completed being stopped." /> + <BitField start="10" size="22" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." /> + </Register> + </RegisterGroup> + <RegisterGroup name="EMAC" start="0x50000000" description="Ethernet"> + <Register start="+0x000" size="4" name="MAC1" access="Read/Write" description="MAC configuration register 1." reset_value="0x8000" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RXENABLE" description="RECEIVE ENABLE. Set this to allow receive frames to be received. Internally the MAC synchronizes this control bit to the incoming receive stream." /> + <BitField start="1" size="1" name="PARF" description="PASS ALL RECEIVE FRAMES. When enabled (set to 1), the MAC will pass all frames regardless of type (normal vs. Control). When disabled, the MAC does not pass valid Control frames." /> + <BitField start="2" size="1" name="RXFLOWCTRL" description="RX FLOW CONTROL. When enabled (set to 1), the MAC acts upon received PAUSE Flow Control frames. When disabled, received PAUSE Flow Control frames are ignored." /> + <BitField start="3" size="1" name="TXFLOWCTRL" description="TX FLOW CONTROL. When enabled (set to 1), PAUSE Flow Control frames are allowed to be transmitted. When disabled, Flow Control frames are blocked." /> + <BitField start="4" size="1" name="LOOPBACK" description="Setting this bit will cause the MAC Transmit interface to be looped back to the MAC Receive interface. Clearing this bit results in normal operation." /> + <BitField start="5" size="3" name="RESERVED" description="Unused" /> + <BitField start="8" size="1" name="RESETTX" description="Setting this bit will put the Transmit Function logic in reset." /> + <BitField start="9" size="1" name="RESETMCSTX" description="Setting this bit resets the MAC Control Sublayer / Transmit logic. The MCS logic implements flow control." /> + <BitField start="10" size="1" name="RESETRX" description="Setting this bit will put the Ethernet receive logic in reset." /> + <BitField start="11" size="1" name="RESETMCSRX" description="Setting this bit resets the MAC Control Sublayer / Receive logic. The MCS logic implements flow control." /> + <BitField start="12" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="14" size="1" name="SIMRESET" description="SIMULATION RESET. Setting this bit will cause a reset to the random number generator within the Transmit Function." /> + <BitField start="15" size="1" name="SOFTRESET" description="SOFT RESET. Setting this bit will put all modules within the MAC in reset except the Host Interface." /> + <BitField start="16" size="16" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x004" size="4" name="MAC2" access="Read/Write" description="MAC configuration register 2." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="FULLDUPLEX" description="When enabled (set to 1), the MAC operates in Full-Duplex mode. When disabled, the MAC operates in Half-Duplex mode." /> + <BitField start="1" size="1" name="FLC" description="FRAMELENGTH CHECKING. When enabled (set to 1), both transmit and receive frame lengths are compared to the Length/Type field. If the Length/Type field represents a length then the check is performed. Mismatches are reported in the StatusInfo word for each received frame." /> + <BitField start="2" size="1" name="HFEN" description="HUGE FRAME ENABLEWhen enabled (set to 1), frames of any length are transmitted and received." /> + <BitField start="3" size="1" name="DELAYEDCRC" description="DELAYED CRC. This bit determines the number of bytes, if any, of proprietary header information that exist on the front of IEEE 802.3 frames. When 1, four bytes of header (ignored by the CRC function) are added. When 0, there is no proprietary header." /> + <BitField start="4" size="1" name="CRCEN" description="CRC ENABLESet this bit to append a CRC to every frame whether padding was required or not. Must be set if PAD/CRC ENABLE is set. Clear this bit if frames presented to the MAC contain a CRC." /> + <BitField start="5" size="1" name="PADCRCEN" description="PAD CRC ENABLE. Set this bit to have the MAC pad all short frames. Clear this bit if frames presented to the MAC have a valid length. This bit is used in conjunction with AUTO PAD ENABLE and VLAN PAD ENABLE. See Table 153 - Pad Operation for details on the pad function." /> + <BitField start="6" size="1" name="VLANPADEN" description="VLAN PAD ENABLE. Set this bit to cause the MAC to pad all short frames to 64 bytes and append a valid CRC. Consult Table 153 - Pad Operation for more information on the various padding features. Note: This bit is ignored if PAD / CRC ENABLE is cleared." /> + <BitField start="7" size="1" name="AUTODETPADEN" description="AUTODETECTPAD ENABLE. Set this bit to cause the MAC to automatically detect the type of frame, either tagged or un-tagged, by comparing the two octets following the source address with 0x8100 (VLAN Protocol ID) and pad accordingly. Table 153 - Pad Operation provides a description of the pad function based on the configuration of this register. Note: This bit is ignored if PAD / CRC ENABLE is cleared." /> + <BitField start="8" size="1" name="PPENF" description="PURE PREAMBLE ENFORCEMEN. When enabled (set to 1), the MAC will verify the content of the preamble to ensure it contains 0x55 and is error-free. A packet with an incorrect preamble is discarded. When disabled, no preamble checking is performed." /> + <BitField start="9" size="1" name="LPENF" description="LONG PREAMBLE ENFORCEMENT. When enabled (set to 1), the MAC only allows receive packets which contain preamble fields less than 12 bytes in length. When disabled, the MAC allows any length preamble as per the Standard." /> + <BitField start="10" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="12" size="1" name="NOBACKOFF" description="When enabled (set to 1), the MAC will immediately retransmit following a collision rather than using the Binary Exponential Backoff algorithm as specified in the Standard." /> + <BitField start="13" size="1" name="BP_NOBACKOFF" description="BACK PRESSURE / NO BACKOFF. When enabled (set to 1), after the MAC incidentally causes a collision during back pressure, it will immediately retransmit without backoff, reducing the chance of further collisions and ensuring transmit packets get sent." /> + <BitField start="14" size="1" name="EXCESSDEFER" description="When enabled (set to 1) the MAC will defer to carrier indefinitely as per the Standard. When disabled, the MAC will abort when the excessive deferral limit is reached." /> + <BitField start="15" size="17" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x008" size="4" name="IPGT" access="Read/Write" description="Back-to-Back Inter-Packet-Gap register." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="7" name="BTOBINTEGAP" description="BACK-TO-BACK INTER-PACKET-GAP.This is a programmable field representing the nibble time offset of the minimum possible period between the end of any transmitted packet to the beginning of the next. In Full-Duplex mode, the register value should be the desired period in nibble times minus 3. In Half-Duplex mode, the register value should be the desired period in nibble times minus 6. In Full-Duplex the recommended setting is 0x15 (21d), which represents the minimum IPG of 960 ns (in 100 Mbps mode) or 9.6 us (in 10 Mbps mode). In Half-Duplex the recommended setting is 0x12 (18d), which also represents the minimum IPG of 960 ns (in 100 Mbps mode) or 9.6 us (in 10 Mbps mode)." /> + <BitField start="7" size="25" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x00C" size="4" name="IPGR" access="Read/Write" description="Non Back-to-Back Inter-Packet-Gap register." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="7" name="NBTOBINTEGAP2" description="NON-BACK-TO-BACK INTER-PACKET-GAP PART2. This is a programmable field representing the Non-Back-to-Back Inter-Packet-Gap. The recommended value is 0x12 (18d), which represents the minimum IPG of 960 ns (in 100 Mbps mode) or 9.6 us (in 10 Mbps mode)." /> + <BitField start="7" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="8" size="7" name="NBTOBINTEGAP1" description="NON-BACK-TO-BACK INTER-PACKET-GAP PART1. This is a programmable field representing the optional carrierSense window referenced in IEEE 802.3/4.2.3.2.1 'Carrier Deference'. If carrier is detected during the timing of IPGR1, the MAC defers to carrier. If, however, carrier becomes active after IPGR1, the MAC continues timing IPGR2 and transmits, knowingly causing a collision, thus ensuring fair access to medium. Its range of values is 0x0 to IPGR2. The recommended value is 0xC (12d)" /> + <BitField start="15" size="17" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x010" size="4" name="CLRT" access="Read/Write" description="Collision window / Retry register." reset_value="0x370F" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="4" name="RETRANSMAX" description="RETRANSMISSION MAXIMUM.This is a programmable field specifying the number of retransmission attempts following a collision before aborting the packet due to excessive collisions. The Standard specifies the attemptLimit to be 0xF (15d). See IEEE 802.3/4.2.3.2.5." /> + <BitField start="4" size="4" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="8" size="6" name="COLLWIN" description="COLLISION WINDOW. This is a programmable field representing the slot time or collision window during which collisions occur in properly configured networks. The default value of 0x37 (55d) represents a 56 byte window following the preamble and SFD." /> + <BitField start="14" size="18" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x014" size="4" name="MAXF" access="Read/Write" description="Maximum Frame register." reset_value="0x0600" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="16" name="MAXFLEN" description="MAXIMUM FRAME LENGTH. This field resets to the value 0x0600, which represents a maximum receive frame of 1536 octets. An untagged maximum size Ethernet frame is 1518 octets. A tagged frame adds four octets for a total of 1522 octets. If a shorter maximum length restriction is desired, program this 16-bit field." /> + <BitField start="16" size="16" name="RESERVED" description="Unused" /> + </Register> + <Register start="+0x018" size="4" name="SUPP" access="Read/Write" description="PHY Support register." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="RESERVED" description="Unused" /> + <BitField start="8" size="1" name="SPEED" description="This bit configures the Reduced MII logic for the current operating speed. When set, 100 Mbps mode is selected. When cleared, 10 Mbps mode is selected." /> + <BitField start="9" size="23" name="RESERVED" description="Unused" /> + </Register> + <Register start="+0x01C" size="4" name="TEST" access="Read/Write" description="Test register." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="SCPQ" description="SHORTCUT PAUSE QUANTA. This bit reduces the effective PAUSE quanta from 64 byte-times to 1 byte-time." /> + <BitField start="1" size="1" name="TESTPAUSE" description="This bit causes the MAC Control sublayer to inhibit transmissions, just as if a PAUSE Receive Control frame with a nonzero pause time parameter was received." /> + <BitField start="2" size="1" name="TESTBP" description="TEST BACKPRESSURE. Setting this bit will cause the MAC to assert backpressure on the link. Backpressure causes preamble to be transmitted, raising carrier sense. A transmit packet from the system will be sent during backpressure." /> + <BitField start="3" size="29" name="RESERVED" description="Unused" /> + </Register> + <Register start="+0x020" size="4" name="MCFG" access="Read/Write" description="MII Mgmt Configuration register." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="SCANINC" description="SCAN INCREMENT. Set this bit to cause the MII Management hardware to perform read cycles across a range of PHYs. When set, the MII Management hardware will perform read cycles from address 1 through the value set in PHY ADDRESS[4:0]. Clear this bit to allow continuous reads of the same PHY." /> + <BitField start="1" size="1" name="SUPPPREAMBLE" description="SUPPRESS PREAMBLE. Set this bit to cause the MII Management hardware to perform read/write cycles without the 32-bit preamble field. Clear this bit to cause normal cycles to be performed. Some PHYs support suppressed preamble." /> + <BitField start="2" size="4" name="CLOCKSEL" description="CLOCK SELECT. This field is used by the clock divide logic in creating the MII Management Clock (MDC) which IEEE 802.3u defines to be no faster than 2.5 MHz. Some PHYs support clock rates up to 12.5 MHz, however. The AHB bus clock (HCLK) is divided by the specified amount. Refer to Table 160 below for the definition of values for this field." /> + <BitField start="6" size="9" name="RESERVED" description="Unused" /> + <BitField start="15" size="1" name="RESETMIIMGMT" description="RESET MII MGMT. This bit resets the MII Management hardware." /> + <BitField start="16" size="16" name="RESERVED" description="Unused" /> + </Register> + <Register start="+0x024" size="4" name="MCMD" access="Read/Write" description="MII Mgmt Command register." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="READ" description="This bit causes the MII Management hardware to perform a single Read cycle. The Read data is returned in Register MRDD (MII Mgmt Read Data)." /> + <BitField start="1" size="1" name="SCAN" description="This bit causes the MII Management hardware to perform Read cycles continuously. This is useful for monitoring Link Fail for example." /> + <BitField start="2" size="30" name="RESERVED" description="Unused" /> + </Register> + <Register start="+0x028" size="4" name="MADR" access="Read/Write" description="MII Mgmt Address register." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="REGADDR" description="REGISTER ADDRESS. This field represents the 5-bit Register Address field of Mgmt cycles. Up to 32 registers can be accessed." /> + <BitField start="5" size="3" name="RESERVED" description="Unused" /> + <BitField start="8" size="5" name="PHYADDR" description="PHY ADDRESS. This field represents the 5-bit PHY Address field of Mgmt cycles. Up to 31 PHYs can be addressed (0 is reserved)." /> + <BitField start="13" size="19" name="RESERVED" description="Unused" /> + </Register> + <Register start="+0x02C" size="4" name="MWTD" access="WriteOnly" description="MII Mgmt Write Data register." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="16" name="WRITEDATA" description="WRITE DATA. When written, an MII Mgmt write cycle is performed using the 16-bit data and the pre-configured PHY and Register addresses from the MII Mgmt Address register (MADR)." /> + <BitField start="16" size="16" name="RESERVED" description="Unused" /> + </Register> + <Register start="+0x030" size="4" name="MRDD" access="ReadOnly" description="MII Mgmt Read Data register." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="16" name="READDATA" description="READ DATA. Following an MII Mgmt Read Cycle, the 16-bit data can be read from this location." /> + <BitField start="16" size="16" name="RESERVED" description="Unused" /> + </Register> + <Register start="+0x034" size="4" name="MIND" access="ReadOnly" description="MII Mgmt Indicators register." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="BUSY" description="When 1 is returned - indicates MII Mgmt is currently performing an MII Mgmt Read or Write cycle." /> + <BitField start="1" size="1" name="SCANNING" description="When 1 is returned - indicates a scan operation (continuous MII Mgmt Read cycles) is in progress." /> + <BitField start="2" size="1" name="NOTVALID" description="When 1 is returned - indicates MII Mgmt Read cycle has not completed and the Read Data is not yet valid." /> + <BitField start="3" size="1" name="MIILINKFAIL" description="When 1 is returned - indicates that an MII Mgmt link fail has occurred." /> + <BitField start="4" size="28" name="RESERVED" description="Unused" /> + </Register> + <Register start="+0x040" size="4" name="SA0" access="Read/Write" description="Station Address 0 register." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="SADDR2" description="STATION ADDRESS, 2nd octet. This field holds the second octet of the station address." /> + <BitField start="8" size="8" name="SADDR1" description="STATION ADDRESS, 1st octet. This field holds the first octet of the station address." /> + <BitField start="16" size="16" name="RESERVED" description="Unused" /> + </Register> + <Register start="+0x044" size="4" name="SA1" access="Read/Write" description="Station Address 1 register." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="SADDR4" description="STATION ADDRESS, 4th octet. This field holds the fourth octet of the station address." /> + <BitField start="8" size="8" name="SADDR3" description="STATION ADDRESS, 3rd octet. This field holds the third octet of the station address." /> + <BitField start="16" size="16" name="RESERVED" description="Unused" /> + </Register> + <Register start="+0x048" size="4" name="SA2" access="Read/Write" description="Station Address 2 register." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="SADDR6" description="STATION ADDRESS, 6th octet. This field holds the sixth octet of the station address." /> + <BitField start="8" size="8" name="SADDR5" description="STATION ADDRESS, 5th octet. This field holds the fifth octet of the station address." /> + <BitField start="16" size="16" name="RESERVED" description="Unused" /> + </Register> + <Register start="+0x100" size="4" name="COMMAND" access="Read/Write" description="Command register." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RXENABLE" description="Enable receive." /> + <BitField start="1" size="1" name="TXENABLE" description="Enable transmit." /> + <BitField start="2" size="1" name="RESERVED" description="Unused" /> + <BitField start="3" size="1" name="REGRESET" description="When a 1 is written, all datapaths and the host registers are reset. The MAC needs to be reset separately." /> + <BitField start="4" size="1" name="TXRESET" description="When a 1 is written, the transmit datapath is reset." /> + <BitField start="5" size="1" name="RXRESET" description="When a 1 is written, the receive datapath is reset." /> + <BitField start="6" size="1" name="PASSRUNTFRAME" description="When set to 1 , passes runt frames s1maller than 64 bytes to memory unless they have a CRC error. If 0 runt frames are filtered out." /> + <BitField start="7" size="1" name="PASSRXFILTER" description="When set to 1 , disables receive filtering i.e. all frames received are written to memory." /> + <BitField start="8" size="1" name="TXFLOWCONTROL" description="Enable IEEE 802.3 / clause 31 flow control sending pause frames in full duplex and continuous preamble in half duplex." /> + <BitField start="9" size="1" name="RMII" description="When set to 1 , RMII mode is selected; if 0, MII mode is selected." /> + <BitField start="10" size="1" name="FULLDUPLEX" description="When set to 1 , indicates full duplex operation." /> + <BitField start="11" size="21" name="RESERVED" description="Unused" /> + </Register> + <Register start="+0x104" size="4" name="STATUS" access="ReadOnly" description="Status register." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RXSTATUS" description="If 1, the receive channel is active. If 0, the receive channel is inactive." /> + <BitField start="1" size="1" name="TXSTATUS" description="If 1, the transmit channel is active. If 0, the transmit channel is inactive." /> + <BitField start="2" size="30" name="RESERVED" description="Unused" /> + </Register> + <Register start="+0x108" size="4" name="RXDESCRIPTOR" access="Read/Write" description="Receive descriptor base address register." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="RESERVED" description="Fixed to 00" /> + <BitField start="2" size="30" name="RXDESCRIPTOR" description="MSBs of receive descriptor base address." /> + </Register> + <Register start="+0x10C" size="4" name="RXSTATUS" access="Read/Write" description="Receive status base address register." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="3" name="RESERVED" description="Fixed to 000" /> + <BitField start="3" size="29" name="RXSTATUS" description="MSBs of receive status base address." /> + </Register> + <Register start="+0x110" size="4" name="RXDESCRIPTORNUMBER" access="Read/Write" description="Receive number of descriptors register." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="16" name="RXDESCRIPTORN" description="RxDescriptorNumber. Number of descriptors in the descriptor array for which RxDescriptor is the base address. The number of descriptors is minus one encoded." /> + <BitField start="16" size="16" name="RESERVED" description="Unused" /> + </Register> + <Register start="+0x114" size="4" name="RXPRODUCEINDEX" access="ReadOnly" description="Receive produce index register." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="16" name="RXPRODUCEIX" description="Index of the descriptor that is going to be filled next by the receive datapath." /> + <BitField start="16" size="16" name="RESERVED" description="Unused" /> + </Register> + <Register start="+0x118" size="4" name="RXCONSUMEINDEX" access="Read/Write" description="Receive consume index register." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="16" name="RXCONSUMEIX" description="Index of the descriptor that is going to be processed next by the receive" /> + <BitField start="16" size="16" name="RESERVED" description="Unused" /> + </Register> + <Register start="+0x11C" size="4" name="TXDESCRIPTOR" access="Read/Write" description="Transmit descriptor base address register." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="RESERVED" description="Fixed to 00" /> + <BitField start="2" size="30" name="TXD" description="TxDescriptor. MSBs of transmit descriptor base address." /> + </Register> + <Register start="+0x120" size="4" name="TXSTATUS" access="Read/Write" description="Transmit status base address register." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="RESERVED" description="Fixed to 00" /> + <BitField start="2" size="30" name="TXSTAT" description="TxStatus. MSBs of transmit status base address." /> + </Register> + <Register start="+0x124" size="4" name="TXDESCRIPTORNUMBER" access="Read/Write" description="Transmit number of descriptors register." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="16" name="TXDN" description="TxDescriptorNumber. Number of descriptors in the descriptor array for which TxDescriptor is the base address. The register is minus one encoded." /> + <BitField start="16" size="16" name="RESERVED" description="Unused" /> + </Register> + <Register start="+0x128" size="4" name="TXPRODUCEINDEX" access="Read/Write" description="Transmit produce index register." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="16" name="TXPI" description="TxProduceIndex. Index of the descriptor that is going to be filled next by the transmit software driver." /> + <BitField start="16" size="16" name="RESERVED" description="Unused" /> + </Register> + <Register start="+0x12C" size="4" name="TXCONSUMEINDEX" access="ReadOnly" description="Transmit consume index register." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="16" name="TXCI" description="TxConsumeIndex. Index of the descriptor that is going to be transmitted next by the transmit datapath." /> + <BitField start="16" size="16" name="RESERVED" description="Unused" /> + </Register> + <Register start="+0x158" size="4" name="TSV0" access="ReadOnly" description="Transmit status vector 0 register." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="CRCERR" description="CRC error. The attached CRC in the packet did not match the internally generated CRC." /> + <BitField start="1" size="1" name="LCE" description="Length check error. Indicates the frame length field does not match the actual number of data items and is not a type field." /> + <BitField start="2" size="1" name="LOR" description="Length out of range. Indicates that frame type/length field was larger than 1500 bytes. The EMAC doesn't distinguish the frame type and frame length, so, e.g. when the IP(0x8000) or ARP(0x0806) packets are received, it compares the frame type with the max length and gives the "Length out of range" error. In fact, this bit is not an error indication, but simply a statement by the chip regarding the status of the received frame." /> + <BitField start="3" size="1" name="DONE" description="Transmission of packet was completed." /> + <BitField start="4" size="1" name="MULTICAST" description="Packet's destination was a multicast address." /> + <BitField start="5" size="1" name="BROADCAST" description="Packet's destination was a broadcast address." /> + <BitField start="6" size="1" name="PACKETDEFER" description="Packet was deferred for at least one attempt, but less than an excessive defer." /> + <BitField start="7" size="1" name="EXDF" description="Excessive Defer. Packet was deferred in excess of 6071 nibble times in 100 Mbps or 24287 bit times in 10 Mbps mode." /> + <BitField start="8" size="1" name="EXCOL" description="Excessive Collision. Packet was aborted due to exceeding of maximum allowed number of collisions." /> + <BitField start="9" size="1" name="LCOL" description="Late Collision. Collision occurred beyond collision window, 512 bit times." /> + <BitField start="10" size="1" name="GIANT" description="Byte count in frame was greater than can be represented in the transmit byte count field in TSV1." /> + <BitField start="11" size="1" name="UNDERRUN" description="Host side caused buffer underrun." /> + <BitField start="12" size="16" name="TOTALBYTES" description="The total number of bytes transferred including collided attempts." /> + <BitField start="28" size="1" name="CONTROLFRAME" description="The frame was a control frame." /> + <BitField start="29" size="1" name="PAUSE" description="The frame was a control frame with a valid PAUSE opcode." /> + <BitField start="30" size="1" name="BACKPRESSURE" description="Carrier-sense method backpressure was previously applied." /> + <BitField start="31" size="1" name="VLAN" description="Frame's length/type field contained 0x8100 which is the VLAN protocol identifier." /> + </Register> + <Register start="+0x15C" size="4" name="TSV1" access="ReadOnly" description="Transmit status vector 1 register." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="16" name="TBC" description="Transmit byte count. The total number of bytes in the frame, not counting the collided bytes." /> + <BitField start="16" size="4" name="TCC" description="Transmit collision count. Number of collisions the current packet incurred during transmission attempts. The maximum number of collisions (16) cannot be represented." /> + <BitField start="20" size="12" name="RESERVED" description="Unused" /> + </Register> + <Register start="+0x160" size="4" name="RSV" access="ReadOnly" description="Receive status vector register." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="16" name="RBC" description="Received byte count. Indicates length of received frame." /> + <BitField start="16" size="1" name="PPI" description="Packet previously ignored. Indicates that a packet was dropped." /> + <BitField start="17" size="1" name="RXDVSEEN" description="RXDV event previously seen. Indicates that the last receive event seen was not long enough to be a valid packet." /> + <BitField start="18" size="1" name="CESEEN" description="Carrier event previously seen. Indicates that at some time since the last receive statistics, a carrier event was detected." /> + <BitField start="19" size="1" name="RCV" description="Receive code violation. Indicates that received PHY data does not represent a valid receive code." /> + <BitField start="20" size="1" name="CRCERR" description="CRC error. The attached CRC in the packet did not match the internally generated CRC." /> + <BitField start="21" size="1" name="LCERR" description="Length check error. Indicates the frame length field does not match the actual number of data items and is not a type field." /> + <BitField start="22" size="1" name="LOR" description="Length out of range. Indicates that frame type/length field was larger than 1518 bytes. The EMAC doesn't distinguish the frame type and frame length, so, e.g. when the IP(0x8000) or ARP(0x0806) packets are received, it compares the frame type with the max length and gives the "Length out of range" error. In fact, this bit is not an error indication, but simply a statement by the chip regarding the status of the received frame." /> + <BitField start="23" size="1" name="ROK" description="Receive OK. The packet had valid CRC and no symbol errors." /> + <BitField start="24" size="1" name="MULTICAST" description="The packet destination was a multicast address." /> + <BitField start="25" size="1" name="BROADCAST" description="The packet destination was a broadcast address." /> + <BitField start="26" size="1" name="DRIBBLENIBBLE" description="Indicates that after the end of packet another 1-7 bits were received. A single nibble, called dribble nibble, is formed but not sent out." /> + <BitField start="27" size="1" name="CONTROLFRAME" description="The frame was a control frame." /> + <BitField start="28" size="1" name="PAUSE" description="The frame was a control frame with a valid PAUSE opcode." /> + <BitField start="29" size="1" name="UO" description="Unsupported Opcode. The current frame was recognized as a Control Frame but contains an unknown opcode." /> + <BitField start="30" size="1" name="VLAN" description="Frame's length/type field contained 0x8100 which is the VLAN protocol identifier." /> + <BitField start="31" size="1" name="RESERVED" description="Unused" /> + </Register> + <Register start="+0x170" size="4" name="FLOWCONTROLCOUNTER" access="Read/Write" description="Flow control counter register." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="16" name="MC" description="MirrorCounter. In full duplex mode the MirrorCounter specifies the number of cycles before re-issuing the Pause control frame." /> + <BitField start="16" size="16" name="PT" description="PauseTimer. In full-duplex mode the PauseTimer specifies the value that is inserted into the pause timer field of a pause flow control frame. In half duplex mode the PauseTimer specifies the number of backpressure cycles." /> + </Register> + <Register start="+0x174" size="4" name="FLOWCONTROLSTATUS" access="ReadOnly" description="Flow control status register." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="16" name="MCC" description="MirrorCounterCurrent. In full duplex mode this register represents the current value of the datapath's mirror counter which counts up to the value specified by the MirrorCounter field in the FlowControlCounter register. In half duplex mode the register counts until it reaches the value of the PauseTimer bits in the FlowControlCounter register." /> + <BitField start="16" size="16" name="RESERVED" description="Unused" /> + </Register> + <Register start="+0x200" size="4" name="RXFILTERCTRL" access="Read/Write" description="Receive filter control register." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="AUE" description="AcceptUnicastEn. When set to 1, all unicast frames are accepted." /> + <BitField start="1" size="1" name="ABE" description="AcceptBroadcastEn. When set to 1, all broadcast frames are accepted." /> + <BitField start="2" size="1" name="AME" description="AcceptMulticastEn. When set to 1, all multicast frames are accepted." /> + <BitField start="3" size="1" name="AUHE" description="AcceptUnicastHashEn. When set to 1, unicast frames that pass the imperfect hash filter are accepted." /> + <BitField start="4" size="1" name="AMHE" description="AcceptMulticastHashEn. When set to 1, multicast frames that pass the imperfect hash filter are accepted." /> + <BitField start="5" size="1" name="APE" description="AcceptPerfectEn. When set to 1, the frames with a destination address identical to the station address are accepted." /> + <BitField start="6" size="6" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="12" size="1" name="MPEW" description="MagicPacketEnWoL. When set to 1, the result of the magic packet filter will generate a WoL interrupt when there is a match." /> + <BitField start="13" size="1" name="RFEW" description="RxFilterEnWoL. When set to 1, the result of the perfect address matching filter and the imperfect hash filter will generate a WoL interrupt when there is a match." /> + <BitField start="14" size="18" name="RESERVED" description="Unused" /> + </Register> + <Register start="+0x204" size="4" name="RXFILTERWOLSTATUS" access="ReadOnly" description="Receive filter WoL status register." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="AUW" description="AcceptUnicastWoL. When the value is 1, a unicast frames caused WoL." /> + <BitField start="1" size="1" name="ABW" description="AcceptBroadcastWoL. When the value is 1, a broadcast frame caused WoL." /> + <BitField start="2" size="1" name="AMW" description="AcceptMulticastWoL. When the value is 1, a multicast frame caused WoL." /> + <BitField start="3" size="1" name="AUHW" description="AcceptUnicastHashWoL. When the value is 1, a unicast frame that passes the imperfect hash filter caused WoL." /> + <BitField start="4" size="1" name="AMHW" description="AcceptMulticastHashWoL. When the value is 1, a multicast frame that passes the imperfect hash filter caused WoL." /> + <BitField start="5" size="1" name="APW" description="AcceptPerfectWoL. When the value is 1, the perfect address matching filter caused WoL." /> + <BitField start="6" size="1" name="RESERVED" description="Unused" /> + <BitField start="7" size="1" name="RFW" description="RxFilterWoL. When the value is 1, the receive filter caused WoL." /> + <BitField start="8" size="1" name="MPW" description="MagicPacketWoL. When the value is 1, the magic packet filter caused WoL." /> + <BitField start="9" size="23" name="RESERVED" description="Unused" /> + </Register> + <Register start="+0x208" size="4" name="RXFILTERWOLCLEAR" access="WriteOnly" description="Receive filter WoL clear register." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="AUWCLR" description="AcceptUnicastWoLClr. When a 1 is written, the corresponding status bit in the RxFilterWoLStatus register is cleared." /> + <BitField start="1" size="1" name="ABWCLR" description="AcceptBroadcastWoLClr. When a 1 is written, the corresponding status bit in the RxFilterWoLStatus register is cleared." /> + <BitField start="2" size="1" name="AMWCLR" description="AcceptMulticastWoLClr. When a 1 is written, the corresponding status bit in the RxFilterWoLStatus register is cleared." /> + <BitField start="3" size="1" name="AUHWCLR" description="AcceptUnicastHashWoLClr. When a 1 is written, the corresponding status bit in the RxFilterWoLStatus register is cleared." /> + <BitField start="4" size="1" name="AMHWCLR" description="AcceptMulticastHashWoLClr. When a 1 is written, the corresponding status bit in the RxFilterWoLStatus register is cleared." /> + <BitField start="5" size="1" name="APWCLR" description="AcceptPerfectWoLClr. When a 1 is written, the corresponding status bit in the RxFilterWoLStatus register is cleared." /> + <BitField start="6" size="1" name="RESERVED" description="Unused" /> + <BitField start="7" size="1" name="RFWCLR" description="RxFilterWoLClr. When a 1 is written, the corresponding status bit in the RxFilterWoLStatus register is cleared." /> + <BitField start="8" size="1" name="MPWCLR" description="MagicPacketWoLClr. When a 1 is written, the corresponding status bit in the RxFilterWoLStatus register is cleared." /> + <BitField start="9" size="23" name="RESERVED" description="Unused" /> + </Register> + <Register start="+0x210" size="4" name="HASHFILTERL" access="Read/Write" description="Hash filter table LSBs register." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="HFL" description="HashFilterL. Bits 31:0 of the imperfect filter hash table for receive filtering." /> + </Register> + <Register start="+0x214" size="4" name="HASHFILTERH" access="Read/Write" description="Hash filter table MSBs register." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="HFH" description="Bits 63:32 of the imperfect filter hash table for receive filtering." /> + </Register> + <Register start="+0xFE0" size="4" name="INTSTATUS" access="ReadOnly" description="Interrupt status register." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RXOVERRUNINT" description="Interrupt set on a fatal overrun error in the receive queue. The fatal interrupt should be resolved by a Rx soft-reset. The bit is not set when there is a nonfatal overrun error." /> + <BitField start="1" size="1" name="RXERRORINT" description="Interrupt trigger on receive errors: AlignmentError, RangeError, LengthError, SymbolError, CRCError or NoDescriptor or Overrun." /> + <BitField start="2" size="1" name="RXFINISHEDINT" description="Interrupt triggered when all receive descriptors have been processed i.e. on the transition to the situation where ProduceIndex == ConsumeIndex." /> + <BitField start="3" size="1" name="RXDONEINT" description="Interrupt triggered when a receive descriptor has been processed while the Interrupt bit in the Control field of the descriptor was set." /> + <BitField start="4" size="1" name="TXUNDERRUNINT" description="Interrupt set on a fatal underrun error in the transmit queue. The fatal interrupt should be resolved by a Tx soft-reset. The bit is not set when there is a nonfatal underrun error." /> + <BitField start="5" size="1" name="TXERRORINT" description="Interrupt trigger on transmit errors: LateCollision, ExcessiveCollision and ExcessiveDefer, NoDescriptor or Underrun." /> + <BitField start="6" size="1" name="TXFINISHEDINT" description="Interrupt triggered when all transmit descriptors have been processed i.e. on the transition to the situation where ProduceIndex == ConsumeIndex." /> + <BitField start="7" size="1" name="TXDONEINT" description="Interrupt triggered when a descriptor has been transmitted while the Interrupt bit in the Control field of the descriptor was set." /> + <BitField start="8" size="4" name="RESERVED" description="Unused" /> + <BitField start="12" size="1" name="SOFTINT" description="Interrupt triggered by software writing a 1 to the SoftIntSet bit in the IntSet register." /> + <BitField start="13" size="1" name="WAKEUPINT" description="Interrupt triggered by a Wake-up event detected by the receive filter." /> + <BitField start="14" size="18" name="RESERVED" description="Unused" /> + </Register> + <Register start="+0xFE4" size="4" name="INTENABLE" access="Read/Write" description="Interrupt enable register." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RXOVERRUNINTEN" description="Enable for interrupt trigger on receive buffer overrun or descriptor underrun situations." /> + <BitField start="1" size="1" name="RXERRORINTEN" description="Enable for interrupt trigger on receive errors." /> + <BitField start="2" size="1" name="RXFINISHEDINTEN" description="Enable for interrupt triggered when all receive descriptors have been processed i.e. on the transition to the situation where ProduceIndex == ConsumeIndex." /> + <BitField start="3" size="1" name="RXDONEINTEN" description="Enable for interrupt triggered when a receive descriptor has been processed while the Interrupt bit in the Control field of the descriptor was set." /> + <BitField start="4" size="1" name="TXUNDERRUNINTEN" description="Enable for interrupt trigger on transmit buffer or descriptor underrun situations." /> + <BitField start="5" size="1" name="TXERRORINTEN" description="Enable for interrupt trigger on transmit errors." /> + <BitField start="6" size="1" name="TXFINISHEDINTEN" description="Enable for interrupt triggered when all transmit descriptors have been processed i.e. on the transition to the situation where ProduceIndex == ConsumeIndex." /> + <BitField start="7" size="1" name="TXDONEINTEN" description="Enable for interrupt triggered when a descriptor has been transmitted while the Interrupt bit in the Control field of the descriptor was set." /> + <BitField start="8" size="4" name="RESERVED" description="Unused" /> + <BitField start="12" size="1" name="SOFTINTEN" description="Enable for interrupt triggered by the SoftInt bit in the IntStatus register, caused by software writing a 1 to the SoftIntSet bit in the IntSet register." /> + <BitField start="13" size="1" name="WAKEUPINTEN" description="Enable for interrupt triggered by a Wake-up event detected by the receive filter." /> + <BitField start="14" size="18" name="RESERVED" description="Unused" /> + </Register> + <Register start="+0xFE8" size="4" name="INTCLEAR" access="WriteOnly" description="Interrupt clear register." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RXOVERRUNINTCLR" description="Writing a 1 clears the corresponding status bit in interrupt status register IntStatus." /> + <BitField start="1" size="1" name="RXERRORINTCLR" description="Writing a 1 clears the corresponding status bit in interrupt status register IntStatus." /> + <BitField start="2" size="1" name="RXFINISHEDINTCLR" description="Writing a 1 clears the corresponding status bit in interrupt status register IntStatus." /> + <BitField start="3" size="1" name="RXDONEINTCLR" description="Writing a 1 clears the corresponding status bit in interrupt status register IntStatus." /> + <BitField start="4" size="1" name="TXUNDERRUNINTCLR" description="Writing a 1 clears the corresponding status bit in interrupt status register IntStatus." /> + <BitField start="5" size="1" name="TXERRORINTCLR" description="Writing a 1 clears the corresponding status bit in interrupt status register IntStatus." /> + <BitField start="6" size="1" name="TXFINISHEDINTCLR" description="Writing a 1 clears the corresponding status bit in interrupt status register IntStatus." /> + <BitField start="7" size="1" name="TXDONEINTCLR" description="Writing a 1 clears the corresponding status bit in interrupt status register IntStatus." /> + <BitField start="8" size="4" name="RESERVED" description="Unused" /> + <BitField start="12" size="1" name="SOFTINTCLR" description="Writing a 1 clears the corresponding status bit in interrupt status register IntStatus." /> + <BitField start="13" size="1" name="WAKEUPINTCLR" description="Writing a 1 clears the corresponding status bit in interrupt status register IntStatus." /> + <BitField start="14" size="18" name="RESERVED" description="Unused" /> + </Register> + <Register start="+0xFEC" size="4" name="INTSET" access="WriteOnly" description="Interrupt set register." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RXOVERRUNINTSET" description="Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus." /> + <BitField start="1" size="1" name="RXERRORINTSET" description="Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus." /> + <BitField start="2" size="1" name="RXFINISHEDINTSET" description="Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus." /> + <BitField start="3" size="1" name="RXDONEINTSET" description="Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus." /> + <BitField start="4" size="1" name="TXUNDERRUNINTSET" description="Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus." /> + <BitField start="5" size="1" name="TXERRORINTSET" description="Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus." /> + <BitField start="6" size="1" name="TXFINISHEDINTSET" description="Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus." /> + <BitField start="7" size="1" name="TXDONEINTSET" description="Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus." /> + <BitField start="8" size="4" name="RESERVED" description="Unused" /> + <BitField start="12" size="1" name="SOFTINTSET" description="Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus." /> + <BitField start="13" size="1" name="WAKEUPINTSET" description="Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus." /> + <BitField start="14" size="18" name="RESERVED" description="Unused" /> + </Register> + <Register start="+0xFF4" size="4" name="POWERDOWN" access="Read/Write" description="Power-down register." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="31" name="RESERVED" description="Unused" /> + <BitField start="31" size="1" name="PD" description="PowerDownMACAHB. If true, all AHB accesses will return a read/write error, except accesses to the Power-Down register." /> + </Register> + </RegisterGroup> + <RegisterGroup name="GPDMA" start="0x50004000" description="General purpose DMA controller"> + <Register start="+0x000" size="4" name="INTSTAT" access="ReadOnly" description="DMA Interrupt Status Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="INTSTAT0" description="Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request." /> + <BitField start="1" size="1" name="INTSTAT1" description="Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request." /> + <BitField start="2" size="1" name="INTSTAT2" description="Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request." /> + <BitField start="3" size="1" name="INTSTAT3" description="Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request." /> + <BitField start="4" size="1" name="INTSTAT4" description="Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request." /> + <BitField start="5" size="1" name="INTSTAT5" description="Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request." /> + <BitField start="6" size="1" name="INTSTAT6" description="Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request." /> + <BitField start="7" size="1" name="INTSTAT7" description="Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x004" size="4" name="INTTCSTAT" access="ReadOnly" description="DMA Interrupt Terminal Count Request Status Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="INTTCSTAT0" description="Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." /> + <BitField start="1" size="1" name="INTTCSTAT1" description="Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." /> + <BitField start="2" size="1" name="INTTCSTAT2" description="Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." /> + <BitField start="3" size="1" name="INTTCSTAT3" description="Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." /> + <BitField start="4" size="1" name="INTTCSTAT4" description="Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." /> + <BitField start="5" size="1" name="INTTCSTAT5" description="Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." /> + <BitField start="6" size="1" name="INTTCSTAT6" description="Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." /> + <BitField start="7" size="1" name="INTTCSTAT7" description="Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x008" size="4" name="INTTCCLEAR" access="WriteOnly" description="DMA Interrupt Terminal Count Request Clear Register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="INTTCCLEAR0" description="Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt." /> + <BitField start="1" size="1" name="INTTCCLEAR1" description="Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt." /> + <BitField start="2" size="1" name="INTTCCLEAR2" description="Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt." /> + <BitField start="3" size="1" name="INTTCCLEAR3" description="Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt." /> + <BitField start="4" size="1" name="INTTCCLEAR4" description="Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt." /> + <BitField start="5" size="1" name="INTTCCLEAR5" description="Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt." /> + <BitField start="6" size="1" name="INTTCCLEAR6" description="Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt." /> + <BitField start="7" size="1" name="INTTCCLEAR7" description="Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x00C" size="4" name="INTERRSTAT" access="ReadOnly" description="DMA Interrupt Error Status Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="INTERRSTAT0" description="Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." /> + <BitField start="1" size="1" name="INTERRSTAT1" description="Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." /> + <BitField start="2" size="1" name="INTERRSTAT2" description="Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." /> + <BitField start="3" size="1" name="INTERRSTAT3" description="Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." /> + <BitField start="4" size="1" name="INTERRSTAT4" description="Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." /> + <BitField start="5" size="1" name="INTERRSTAT5" description="Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." /> + <BitField start="6" size="1" name="INTERRSTAT6" description="Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." /> + <BitField start="7" size="1" name="INTERRSTAT7" description="Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x010" size="4" name="INTERRCLR" access="WriteOnly" description="DMA Interrupt Error Clear Register" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="INTERRCLR0" description="Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt." /> + <BitField start="1" size="1" name="INTERRCLR1" description="Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt." /> + <BitField start="2" size="1" name="INTERRCLR2" description="Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt." /> + <BitField start="3" size="1" name="INTERRCLR3" description="Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt." /> + <BitField start="4" size="1" name="INTERRCLR4" description="Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt." /> + <BitField start="5" size="1" name="INTERRCLR5" description="Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt." /> + <BitField start="6" size="1" name="INTERRCLR6" description="Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt." /> + <BitField start="7" size="1" name="INTERRCLR7" description="Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x014" size="4" name="RAWINTTCSTAT" access="ReadOnly" description="DMA Raw Interrupt Terminal Count Status Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RAWINTTCSTAT0" description="Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." /> + <BitField start="1" size="1" name="RAWINTTCSTAT1" description="Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." /> + <BitField start="2" size="1" name="RAWINTTCSTAT2" description="Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." /> + <BitField start="3" size="1" name="RAWINTTCSTAT3" description="Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." /> + <BitField start="4" size="1" name="RAWINTTCSTAT4" description="Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." /> + <BitField start="5" size="1" name="RAWINTTCSTAT5" description="Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." /> + <BitField start="6" size="1" name="RAWINTTCSTAT6" description="Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." /> + <BitField start="7" size="1" name="RAWINTTCSTAT7" description="Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x018" size="4" name="RAWINTERRSTAT" access="ReadOnly" description="DMA Raw Error Interrupt Status Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RAWINTERRSTAT0" description="Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." /> + <BitField start="1" size="1" name="RAWINTERRSTAT1" description="Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." /> + <BitField start="2" size="1" name="RAWINTERRSTAT2" description="Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." /> + <BitField start="3" size="1" name="RAWINTERRSTAT3" description="Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." /> + <BitField start="4" size="1" name="RAWINTERRSTAT4" description="Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." /> + <BitField start="5" size="1" name="RAWINTERRSTAT5" description="Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." /> + <BitField start="6" size="1" name="RAWINTERRSTAT6" description="Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." /> + <BitField start="7" size="1" name="RAWINTERRSTAT7" description="Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x01C" size="4" name="ENBLDCHNS" access="ReadOnly" description="DMA Enabled Channel Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="ENABLEDCHANNELS0" description="Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled." /> + <BitField start="1" size="1" name="ENABLEDCHANNELS1" description="Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled." /> + <BitField start="2" size="1" name="ENABLEDCHANNELS2" description="Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled." /> + <BitField start="3" size="1" name="ENABLEDCHANNELS3" description="Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled." /> + <BitField start="4" size="1" name="ENABLEDCHANNELS4" description="Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled." /> + <BitField start="5" size="1" name="ENABLEDCHANNELS5" description="Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled." /> + <BitField start="6" size="1" name="ENABLEDCHANNELS6" description="Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled." /> + <BitField start="7" size="1" name="ENABLEDCHANNELS7" description="Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x020" size="4" name="SOFTBREQ" access="Read/Write" description="DMA Software Burst Request Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="SOFTBREQ0" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." /> + <BitField start="1" size="1" name="SOFTBREQ1" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." /> + <BitField start="2" size="1" name="SOFTBREQ2" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." /> + <BitField start="3" size="1" name="SOFTBREQ3" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." /> + <BitField start="4" size="1" name="SOFTBREQ4" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." /> + <BitField start="5" size="1" name="SOFTBREQ5" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." /> + <BitField start="6" size="1" name="SOFTBREQ6" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." /> + <BitField start="7" size="1" name="SOFTBREQ7" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." /> + <BitField start="8" size="1" name="SOFTBREQ8" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." /> + <BitField start="9" size="1" name="SOFTBREQ9" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." /> + <BitField start="10" size="1" name="SOFTBREQ10" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." /> + <BitField start="11" size="1" name="SOFTBREQ11" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." /> + <BitField start="12" size="1" name="SOFTBREQ12" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." /> + <BitField start="13" size="1" name="SOFTBREQ13" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." /> + <BitField start="14" size="1" name="SOFTBREQ14" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." /> + <BitField start="15" size="1" name="SOFTBREQ15" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." /> + <BitField start="16" size="16" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x024" size="4" name="SOFTSREQ" access="Read/Write" description="DMA Software Single Request Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="SOFTSREQ0" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." /> + <BitField start="1" size="1" name="SOFTSREQ1" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." /> + <BitField start="2" size="1" name="SOFTSREQ2" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." /> + <BitField start="3" size="1" name="SOFTSREQ3" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." /> + <BitField start="4" size="1" name="SOFTSREQ4" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." /> + <BitField start="5" size="1" name="SOFTSREQ5" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." /> + <BitField start="6" size="1" name="SOFTSREQ6" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." /> + <BitField start="7" size="1" name="SOFTSREQ7" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." /> + <BitField start="8" size="1" name="SOFTSREQ8" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." /> + <BitField start="9" size="1" name="SOFTSREQ9" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." /> + <BitField start="10" size="1" name="SOFTSREQ10" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." /> + <BitField start="11" size="1" name="SOFTSREQ11" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." /> + <BitField start="12" size="1" name="SOFTSREQ12" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." /> + <BitField start="13" size="1" name="SOFTSREQ13" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." /> + <BitField start="14" size="1" name="SOFTSREQ14" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." /> + <BitField start="15" size="1" name="SOFTSREQ15" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." /> + <BitField start="16" size="16" name="RESERVED" description="Reserved. Read undefined. Write reserved bits as zero." /> + </Register> + <Register start="+0x028" size="4" name="SOFTLBREQ" access="Read/Write" description="DMA Software Last Burst Request Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="SOFTLBREQ0" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." /> + <BitField start="1" size="1" name="SOFTLBREQ1" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." /> + <BitField start="2" size="1" name="SOFTLBREQ2" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." /> + <BitField start="3" size="1" name="SOFTLBREQ3" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." /> + <BitField start="4" size="1" name="SOFTLBREQ4" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." /> + <BitField start="5" size="1" name="SOFTLBREQ5" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." /> + <BitField start="6" size="1" name="SOFTLBREQ6" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." /> + <BitField start="7" size="1" name="SOFTLBREQ7" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." /> + <BitField start="8" size="1" name="SOFTLBREQ8" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." /> + <BitField start="9" size="1" name="SOFTLBREQ9" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." /> + <BitField start="10" size="1" name="SOFTLBREQ10" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." /> + <BitField start="11" size="1" name="SOFTLBREQ11" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." /> + <BitField start="12" size="1" name="SOFTLBREQ12" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." /> + <BitField start="13" size="1" name="SOFTLBREQ13" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." /> + <BitField start="14" size="1" name="SOFTLBREQ14" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." /> + <BitField start="15" size="1" name="SOFTLBREQ15" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." /> + <BitField start="16" size="16" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x02C" size="4" name="SOFTLSREQ" access="Read/Write" description="DMA Software Last Single Request Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="SOFTLSREQ0" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." /> + <BitField start="1" size="1" name="SOFTLSREQ1" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." /> + <BitField start="2" size="1" name="SOFTLSREQ2" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." /> + <BitField start="3" size="1" name="SOFTLSREQ3" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." /> + <BitField start="4" size="1" name="SOFTLSREQ4" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." /> + <BitField start="5" size="1" name="SOFTLSREQ5" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." /> + <BitField start="6" size="1" name="SOFTLSREQ6" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." /> + <BitField start="7" size="1" name="SOFTLSREQ7" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." /> + <BitField start="8" size="1" name="SOFTLSREQ8" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." /> + <BitField start="9" size="1" name="SOFTLSREQ9" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." /> + <BitField start="10" size="1" name="SOFTLSREQ10" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." /> + <BitField start="11" size="1" name="SOFTLSREQ11" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." /> + <BitField start="12" size="1" name="SOFTLSREQ12" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." /> + <BitField start="13" size="1" name="SOFTLSREQ13" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." /> + <BitField start="14" size="1" name="SOFTLSREQ14" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." /> + <BitField start="15" size="1" name="SOFTLSREQ15" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." /> + <BitField start="16" size="16" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x030" size="4" name="CONFIG" access="Read/Write" description="DMA Configuration Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="E" description="DMA Controller enable: 0 = disabled (default). Disabling the DMA Controller reduces power consumption. 1 = enabled." /> + <BitField start="1" size="1" name="M" description="AHB Master endianness configuration: 0 = little-endian mode (default). 1 = big-endian mode." /> + <BitField start="2" size="30" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x034" size="4" name="SYNC" access="Read/Write" description="DMA Synchronization Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="DMACSYNC0" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled." /> + <BitField start="1" size="1" name="DMACSYNC1" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled." /> + <BitField start="2" size="1" name="DMACSYNC2" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled." /> + <BitField start="3" size="1" name="DMACSYNC3" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled." /> + <BitField start="4" size="1" name="DMACSYNC4" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled." /> + <BitField start="5" size="1" name="DMACSYNC5" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled." /> + <BitField start="6" size="1" name="DMACSYNC6" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled." /> + <BitField start="7" size="1" name="DMACSYNC7" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled." /> + <BitField start="8" size="1" name="DMACSYNC8" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled." /> + <BitField start="9" size="1" name="DMACSYNC9" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled." /> + <BitField start="10" size="1" name="DMACSYNC10" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled." /> + <BitField start="11" size="1" name="DMACSYNC11" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled." /> + <BitField start="12" size="1" name="DMACSYNC12" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled." /> + <BitField start="13" size="1" name="DMACSYNC13" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled." /> + <BitField start="14" size="1" name="DMACSYNC14" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled." /> + <BitField start="15" size="1" name="DMACSYNC15" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled." /> + <BitField start="16" size="16" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x100+0" size="4" name="SRCADDR0" access="Read/Write" description="DMA Channel 0 Source Address Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="SRCADDR" description="DMA source address. Reading this register will return the current source address." /> + </Register> + <Register start="+0x100+32" size="4" name="SRCADDR1" access="Read/Write" description="DMA Channel 0 Source Address Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="SRCADDR" description="DMA source address. Reading this register will return the current source address." /> + </Register> + <Register start="+0x100+64" size="4" name="SRCADDR2" access="Read/Write" description="DMA Channel 0 Source Address Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="SRCADDR" description="DMA source address. Reading this register will return the current source address." /> + </Register> + <Register start="+0x100+96" size="4" name="SRCADDR3" access="Read/Write" description="DMA Channel 0 Source Address Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="SRCADDR" description="DMA source address. Reading this register will return the current source address." /> + </Register> + <Register start="+0x100+128" size="4" name="SRCADDR4" access="Read/Write" description="DMA Channel 0 Source Address Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="SRCADDR" description="DMA source address. Reading this register will return the current source address." /> + </Register> + <Register start="+0x100+160" size="4" name="SRCADDR5" access="Read/Write" description="DMA Channel 0 Source Address Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="SRCADDR" description="DMA source address. Reading this register will return the current source address." /> + </Register> + <Register start="+0x100+192" size="4" name="SRCADDR6" access="Read/Write" description="DMA Channel 0 Source Address Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="SRCADDR" description="DMA source address. Reading this register will return the current source address." /> + </Register> + <Register start="+0x100+224" size="4" name="SRCADDR7" access="Read/Write" description="DMA Channel 0 Source Address Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="SRCADDR" description="DMA source address. Reading this register will return the current source address." /> + </Register> + <Register start="+0x104+0" size="4" name="DESTADDR0" access="Read/Write" description="DMA Channel 0 Destination Address Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="DESTADDR" description="DMA Destination address. Reading this register will return the current destination address." /> + </Register> + <Register start="+0x104+32" size="4" name="DESTADDR1" access="Read/Write" description="DMA Channel 0 Destination Address Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="DESTADDR" description="DMA Destination address. Reading this register will return the current destination address." /> + </Register> + <Register start="+0x104+64" size="4" name="DESTADDR2" access="Read/Write" description="DMA Channel 0 Destination Address Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="DESTADDR" description="DMA Destination address. Reading this register will return the current destination address." /> + </Register> + <Register start="+0x104+96" size="4" name="DESTADDR3" access="Read/Write" description="DMA Channel 0 Destination Address Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="DESTADDR" description="DMA Destination address. Reading this register will return the current destination address." /> + </Register> + <Register start="+0x104+128" size="4" name="DESTADDR4" access="Read/Write" description="DMA Channel 0 Destination Address Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="DESTADDR" description="DMA Destination address. Reading this register will return the current destination address." /> + </Register> + <Register start="+0x104+160" size="4" name="DESTADDR5" access="Read/Write" description="DMA Channel 0 Destination Address Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="DESTADDR" description="DMA Destination address. Reading this register will return the current destination address." /> + </Register> + <Register start="+0x104+192" size="4" name="DESTADDR6" access="Read/Write" description="DMA Channel 0 Destination Address Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="DESTADDR" description="DMA Destination address. Reading this register will return the current destination address." /> + </Register> + <Register start="+0x104+224" size="4" name="DESTADDR7" access="Read/Write" description="DMA Channel 0 Destination Address Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="DESTADDR" description="DMA Destination address. Reading this register will return the current destination address." /> + </Register> + <Register start="+0x108+0" size="4" name="LLI0" access="Read/Write" description="DMA Channel 0 Linked List Item Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="RESERVED" description="Reserved, and must be written as 0." /> + <BitField start="2" size="30" name="LLI" description="Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0." /> + </Register> + <Register start="+0x108+32" size="4" name="LLI1" access="Read/Write" description="DMA Channel 0 Linked List Item Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="RESERVED" description="Reserved, and must be written as 0." /> + <BitField start="2" size="30" name="LLI" description="Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0." /> + </Register> + <Register start="+0x108+64" size="4" name="LLI2" access="Read/Write" description="DMA Channel 0 Linked List Item Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="RESERVED" description="Reserved, and must be written as 0." /> + <BitField start="2" size="30" name="LLI" description="Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0." /> + </Register> + <Register start="+0x108+96" size="4" name="LLI3" access="Read/Write" description="DMA Channel 0 Linked List Item Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="RESERVED" description="Reserved, and must be written as 0." /> + <BitField start="2" size="30" name="LLI" description="Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0." /> + </Register> + <Register start="+0x108+128" size="4" name="LLI4" access="Read/Write" description="DMA Channel 0 Linked List Item Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="RESERVED" description="Reserved, and must be written as 0." /> + <BitField start="2" size="30" name="LLI" description="Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0." /> + </Register> + <Register start="+0x108+160" size="4" name="LLI5" access="Read/Write" description="DMA Channel 0 Linked List Item Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="RESERVED" description="Reserved, and must be written as 0." /> + <BitField start="2" size="30" name="LLI" description="Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0." /> + </Register> + <Register start="+0x108+192" size="4" name="LLI6" access="Read/Write" description="DMA Channel 0 Linked List Item Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="RESERVED" description="Reserved, and must be written as 0." /> + <BitField start="2" size="30" name="LLI" description="Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0." /> + </Register> + <Register start="+0x108+224" size="4" name="LLI7" access="Read/Write" description="DMA Channel 0 Linked List Item Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="RESERVED" description="Reserved, and must be written as 0." /> + <BitField start="2" size="30" name="LLI" description="Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0." /> + </Register> + <Register start="+0x10C+0" size="4" name="CONTROL0" access="Read/Write" description="DMA Channel 0 Control Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="12" name="TRANSFERSIZE" description="Transfer size. This field sets the size of the transfer when the DMA controller is the flow controller, in which case the value must be set before the channel is enabled. Transfer size is updated as data transfers are completed. A read from this field indicates the number of transfers completed on the destination bus. Reading the register when the channel is active does not give useful information because by the time that the software has processed the value read, the channel might have progressed. It is intended to be used only when a channel is enabled and then disabled. The transfer size value is not used if a peripheral is the flow controller." /> + <BitField start="12" size="3" name="SBSIZE" description="Source burst size. Indicates the number of transfers that make up a source burst. This value must be set to the burst size of the source peripheral, or if the source is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the source peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256" /> + <BitField start="15" size="3" name="DBSIZE" description="Destination burst size. Indicates the number of transfers that make up a destination burst transfer request. This value must be set to the burst size of the destination peripheral or, if the destination is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the destination peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256" /> + <BitField start="18" size="3" name="SWIDTH" description="Source transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved" /> + <BitField start="21" size="3" name="DWIDTH" description="Destination transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved" /> + <BitField start="24" size="2" name="RESERVED" description="Reserved, and must be written as 0." /> + <BitField start="26" size="1" name="SI" description="Source increment: 0 - the source address is not incremented after each transfer. 1 - the source address is incremented after each transfer." /> + <BitField start="27" size="1" name="DI" description="Destination increment: 0 - the destination address is not incremented after each transfer. 1 - the destination address is incremented after each transfer." /> + <BitField start="28" size="1" name="PROT1" description="This is provided to the peripheral during a DMA bus access and indicates that the access is in user mode or privileged mode. This information is not used in the LPC178x/177x. 0 - access is in user mode. 1 - access is in privileged mode." /> + <BitField start="29" size="1" name="PROT2" description="This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is bufferable or not bufferable. This information is not used in the LPC178x/177x. 0 - access is not bufferable. 1 - access is bufferable." /> + <BitField start="30" size="1" name="PROT3" description="This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is cacheable or not cacheable. This information is not used in the LPC178x/177x. 0 - access is not cacheable. 1 - access is cacheable." /> + <BitField start="31" size="1" name="I" description="Terminal count interrupt enable bit. 0 - the terminal count interrupt is disabled. 1 - the terminal count interrupt is enabled." /> + </Register> + <Register start="+0x10C+32" size="4" name="CONTROL1" access="Read/Write" description="DMA Channel 0 Control Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="12" name="TRANSFERSIZE" description="Transfer size. This field sets the size of the transfer when the DMA controller is the flow controller, in which case the value must be set before the channel is enabled. Transfer size is updated as data transfers are completed. A read from this field indicates the number of transfers completed on the destination bus. Reading the register when the channel is active does not give useful information because by the time that the software has processed the value read, the channel might have progressed. It is intended to be used only when a channel is enabled and then disabled. The transfer size value is not used if a peripheral is the flow controller." /> + <BitField start="12" size="3" name="SBSIZE" description="Source burst size. Indicates the number of transfers that make up a source burst. This value must be set to the burst size of the source peripheral, or if the source is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the source peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256" /> + <BitField start="15" size="3" name="DBSIZE" description="Destination burst size. Indicates the number of transfers that make up a destination burst transfer request. This value must be set to the burst size of the destination peripheral or, if the destination is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the destination peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256" /> + <BitField start="18" size="3" name="SWIDTH" description="Source transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved" /> + <BitField start="21" size="3" name="DWIDTH" description="Destination transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved" /> + <BitField start="24" size="2" name="RESERVED" description="Reserved, and must be written as 0." /> + <BitField start="26" size="1" name="SI" description="Source increment: 0 - the source address is not incremented after each transfer. 1 - the source address is incremented after each transfer." /> + <BitField start="27" size="1" name="DI" description="Destination increment: 0 - the destination address is not incremented after each transfer. 1 - the destination address is incremented after each transfer." /> + <BitField start="28" size="1" name="PROT1" description="This is provided to the peripheral during a DMA bus access and indicates that the access is in user mode or privileged mode. This information is not used in the LPC178x/177x. 0 - access is in user mode. 1 - access is in privileged mode." /> + <BitField start="29" size="1" name="PROT2" description="This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is bufferable or not bufferable. This information is not used in the LPC178x/177x. 0 - access is not bufferable. 1 - access is bufferable." /> + <BitField start="30" size="1" name="PROT3" description="This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is cacheable or not cacheable. This information is not used in the LPC178x/177x. 0 - access is not cacheable. 1 - access is cacheable." /> + <BitField start="31" size="1" name="I" description="Terminal count interrupt enable bit. 0 - the terminal count interrupt is disabled. 1 - the terminal count interrupt is enabled." /> + </Register> + <Register start="+0x10C+64" size="4" name="CONTROL2" access="Read/Write" description="DMA Channel 0 Control Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="12" name="TRANSFERSIZE" description="Transfer size. This field sets the size of the transfer when the DMA controller is the flow controller, in which case the value must be set before the channel is enabled. Transfer size is updated as data transfers are completed. A read from this field indicates the number of transfers completed on the destination bus. Reading the register when the channel is active does not give useful information because by the time that the software has processed the value read, the channel might have progressed. It is intended to be used only when a channel is enabled and then disabled. The transfer size value is not used if a peripheral is the flow controller." /> + <BitField start="12" size="3" name="SBSIZE" description="Source burst size. Indicates the number of transfers that make up a source burst. This value must be set to the burst size of the source peripheral, or if the source is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the source peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256" /> + <BitField start="15" size="3" name="DBSIZE" description="Destination burst size. Indicates the number of transfers that make up a destination burst transfer request. This value must be set to the burst size of the destination peripheral or, if the destination is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the destination peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256" /> + <BitField start="18" size="3" name="SWIDTH" description="Source transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved" /> + <BitField start="21" size="3" name="DWIDTH" description="Destination transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved" /> + <BitField start="24" size="2" name="RESERVED" description="Reserved, and must be written as 0." /> + <BitField start="26" size="1" name="SI" description="Source increment: 0 - the source address is not incremented after each transfer. 1 - the source address is incremented after each transfer." /> + <BitField start="27" size="1" name="DI" description="Destination increment: 0 - the destination address is not incremented after each transfer. 1 - the destination address is incremented after each transfer." /> + <BitField start="28" size="1" name="PROT1" description="This is provided to the peripheral during a DMA bus access and indicates that the access is in user mode or privileged mode. This information is not used in the LPC178x/177x. 0 - access is in user mode. 1 - access is in privileged mode." /> + <BitField start="29" size="1" name="PROT2" description="This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is bufferable or not bufferable. This information is not used in the LPC178x/177x. 0 - access is not bufferable. 1 - access is bufferable." /> + <BitField start="30" size="1" name="PROT3" description="This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is cacheable or not cacheable. This information is not used in the LPC178x/177x. 0 - access is not cacheable. 1 - access is cacheable." /> + <BitField start="31" size="1" name="I" description="Terminal count interrupt enable bit. 0 - the terminal count interrupt is disabled. 1 - the terminal count interrupt is enabled." /> + </Register> + <Register start="+0x10C+96" size="4" name="CONTROL3" access="Read/Write" description="DMA Channel 0 Control Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="12" name="TRANSFERSIZE" description="Transfer size. This field sets the size of the transfer when the DMA controller is the flow controller, in which case the value must be set before the channel is enabled. Transfer size is updated as data transfers are completed. A read from this field indicates the number of transfers completed on the destination bus. Reading the register when the channel is active does not give useful information because by the time that the software has processed the value read, the channel might have progressed. It is intended to be used only when a channel is enabled and then disabled. The transfer size value is not used if a peripheral is the flow controller." /> + <BitField start="12" size="3" name="SBSIZE" description="Source burst size. Indicates the number of transfers that make up a source burst. This value must be set to the burst size of the source peripheral, or if the source is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the source peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256" /> + <BitField start="15" size="3" name="DBSIZE" description="Destination burst size. Indicates the number of transfers that make up a destination burst transfer request. This value must be set to the burst size of the destination peripheral or, if the destination is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the destination peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256" /> + <BitField start="18" size="3" name="SWIDTH" description="Source transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved" /> + <BitField start="21" size="3" name="DWIDTH" description="Destination transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved" /> + <BitField start="24" size="2" name="RESERVED" description="Reserved, and must be written as 0." /> + <BitField start="26" size="1" name="SI" description="Source increment: 0 - the source address is not incremented after each transfer. 1 - the source address is incremented after each transfer." /> + <BitField start="27" size="1" name="DI" description="Destination increment: 0 - the destination address is not incremented after each transfer. 1 - the destination address is incremented after each transfer." /> + <BitField start="28" size="1" name="PROT1" description="This is provided to the peripheral during a DMA bus access and indicates that the access is in user mode or privileged mode. This information is not used in the LPC178x/177x. 0 - access is in user mode. 1 - access is in privileged mode." /> + <BitField start="29" size="1" name="PROT2" description="This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is bufferable or not bufferable. This information is not used in the LPC178x/177x. 0 - access is not bufferable. 1 - access is bufferable." /> + <BitField start="30" size="1" name="PROT3" description="This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is cacheable or not cacheable. This information is not used in the LPC178x/177x. 0 - access is not cacheable. 1 - access is cacheable." /> + <BitField start="31" size="1" name="I" description="Terminal count interrupt enable bit. 0 - the terminal count interrupt is disabled. 1 - the terminal count interrupt is enabled." /> + </Register> + <Register start="+0x10C+128" size="4" name="CONTROL4" access="Read/Write" description="DMA Channel 0 Control Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="12" name="TRANSFERSIZE" description="Transfer size. This field sets the size of the transfer when the DMA controller is the flow controller, in which case the value must be set before the channel is enabled. Transfer size is updated as data transfers are completed. A read from this field indicates the number of transfers completed on the destination bus. Reading the register when the channel is active does not give useful information because by the time that the software has processed the value read, the channel might have progressed. It is intended to be used only when a channel is enabled and then disabled. The transfer size value is not used if a peripheral is the flow controller." /> + <BitField start="12" size="3" name="SBSIZE" description="Source burst size. Indicates the number of transfers that make up a source burst. This value must be set to the burst size of the source peripheral, or if the source is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the source peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256" /> + <BitField start="15" size="3" name="DBSIZE" description="Destination burst size. Indicates the number of transfers that make up a destination burst transfer request. This value must be set to the burst size of the destination peripheral or, if the destination is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the destination peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256" /> + <BitField start="18" size="3" name="SWIDTH" description="Source transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved" /> + <BitField start="21" size="3" name="DWIDTH" description="Destination transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved" /> + <BitField start="24" size="2" name="RESERVED" description="Reserved, and must be written as 0." /> + <BitField start="26" size="1" name="SI" description="Source increment: 0 - the source address is not incremented after each transfer. 1 - the source address is incremented after each transfer." /> + <BitField start="27" size="1" name="DI" description="Destination increment: 0 - the destination address is not incremented after each transfer. 1 - the destination address is incremented after each transfer." /> + <BitField start="28" size="1" name="PROT1" description="This is provided to the peripheral during a DMA bus access and indicates that the access is in user mode or privileged mode. This information is not used in the LPC178x/177x. 0 - access is in user mode. 1 - access is in privileged mode." /> + <BitField start="29" size="1" name="PROT2" description="This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is bufferable or not bufferable. This information is not used in the LPC178x/177x. 0 - access is not bufferable. 1 - access is bufferable." /> + <BitField start="30" size="1" name="PROT3" description="This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is cacheable or not cacheable. This information is not used in the LPC178x/177x. 0 - access is not cacheable. 1 - access is cacheable." /> + <BitField start="31" size="1" name="I" description="Terminal count interrupt enable bit. 0 - the terminal count interrupt is disabled. 1 - the terminal count interrupt is enabled." /> + </Register> + <Register start="+0x10C+160" size="4" name="CONTROL5" access="Read/Write" description="DMA Channel 0 Control Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="12" name="TRANSFERSIZE" description="Transfer size. This field sets the size of the transfer when the DMA controller is the flow controller, in which case the value must be set before the channel is enabled. Transfer size is updated as data transfers are completed. A read from this field indicates the number of transfers completed on the destination bus. Reading the register when the channel is active does not give useful information because by the time that the software has processed the value read, the channel might have progressed. It is intended to be used only when a channel is enabled and then disabled. The transfer size value is not used if a peripheral is the flow controller." /> + <BitField start="12" size="3" name="SBSIZE" description="Source burst size. Indicates the number of transfers that make up a source burst. This value must be set to the burst size of the source peripheral, or if the source is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the source peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256" /> + <BitField start="15" size="3" name="DBSIZE" description="Destination burst size. Indicates the number of transfers that make up a destination burst transfer request. This value must be set to the burst size of the destination peripheral or, if the destination is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the destination peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256" /> + <BitField start="18" size="3" name="SWIDTH" description="Source transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved" /> + <BitField start="21" size="3" name="DWIDTH" description="Destination transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved" /> + <BitField start="24" size="2" name="RESERVED" description="Reserved, and must be written as 0." /> + <BitField start="26" size="1" name="SI" description="Source increment: 0 - the source address is not incremented after each transfer. 1 - the source address is incremented after each transfer." /> + <BitField start="27" size="1" name="DI" description="Destination increment: 0 - the destination address is not incremented after each transfer. 1 - the destination address is incremented after each transfer." /> + <BitField start="28" size="1" name="PROT1" description="This is provided to the peripheral during a DMA bus access and indicates that the access is in user mode or privileged mode. This information is not used in the LPC178x/177x. 0 - access is in user mode. 1 - access is in privileged mode." /> + <BitField start="29" size="1" name="PROT2" description="This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is bufferable or not bufferable. This information is not used in the LPC178x/177x. 0 - access is not bufferable. 1 - access is bufferable." /> + <BitField start="30" size="1" name="PROT3" description="This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is cacheable or not cacheable. This information is not used in the LPC178x/177x. 0 - access is not cacheable. 1 - access is cacheable." /> + <BitField start="31" size="1" name="I" description="Terminal count interrupt enable bit. 0 - the terminal count interrupt is disabled. 1 - the terminal count interrupt is enabled." /> + </Register> + <Register start="+0x10C+192" size="4" name="CONTROL6" access="Read/Write" description="DMA Channel 0 Control Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="12" name="TRANSFERSIZE" description="Transfer size. This field sets the size of the transfer when the DMA controller is the flow controller, in which case the value must be set before the channel is enabled. Transfer size is updated as data transfers are completed. A read from this field indicates the number of transfers completed on the destination bus. Reading the register when the channel is active does not give useful information because by the time that the software has processed the value read, the channel might have progressed. It is intended to be used only when a channel is enabled and then disabled. The transfer size value is not used if a peripheral is the flow controller." /> + <BitField start="12" size="3" name="SBSIZE" description="Source burst size. Indicates the number of transfers that make up a source burst. This value must be set to the burst size of the source peripheral, or if the source is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the source peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256" /> + <BitField start="15" size="3" name="DBSIZE" description="Destination burst size. Indicates the number of transfers that make up a destination burst transfer request. This value must be set to the burst size of the destination peripheral or, if the destination is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the destination peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256" /> + <BitField start="18" size="3" name="SWIDTH" description="Source transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved" /> + <BitField start="21" size="3" name="DWIDTH" description="Destination transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved" /> + <BitField start="24" size="2" name="RESERVED" description="Reserved, and must be written as 0." /> + <BitField start="26" size="1" name="SI" description="Source increment: 0 - the source address is not incremented after each transfer. 1 - the source address is incremented after each transfer." /> + <BitField start="27" size="1" name="DI" description="Destination increment: 0 - the destination address is not incremented after each transfer. 1 - the destination address is incremented after each transfer." /> + <BitField start="28" size="1" name="PROT1" description="This is provided to the peripheral during a DMA bus access and indicates that the access is in user mode or privileged mode. This information is not used in the LPC178x/177x. 0 - access is in user mode. 1 - access is in privileged mode." /> + <BitField start="29" size="1" name="PROT2" description="This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is bufferable or not bufferable. This information is not used in the LPC178x/177x. 0 - access is not bufferable. 1 - access is bufferable." /> + <BitField start="30" size="1" name="PROT3" description="This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is cacheable or not cacheable. This information is not used in the LPC178x/177x. 0 - access is not cacheable. 1 - access is cacheable." /> + <BitField start="31" size="1" name="I" description="Terminal count interrupt enable bit. 0 - the terminal count interrupt is disabled. 1 - the terminal count interrupt is enabled." /> + </Register> + <Register start="+0x10C+224" size="4" name="CONTROL7" access="Read/Write" description="DMA Channel 0 Control Register" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="12" name="TRANSFERSIZE" description="Transfer size. This field sets the size of the transfer when the DMA controller is the flow controller, in which case the value must be set before the channel is enabled. Transfer size is updated as data transfers are completed. A read from this field indicates the number of transfers completed on the destination bus. Reading the register when the channel is active does not give useful information because by the time that the software has processed the value read, the channel might have progressed. It is intended to be used only when a channel is enabled and then disabled. The transfer size value is not used if a peripheral is the flow controller." /> + <BitField start="12" size="3" name="SBSIZE" description="Source burst size. Indicates the number of transfers that make up a source burst. This value must be set to the burst size of the source peripheral, or if the source is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the source peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256" /> + <BitField start="15" size="3" name="DBSIZE" description="Destination burst size. Indicates the number of transfers that make up a destination burst transfer request. This value must be set to the burst size of the destination peripheral or, if the destination is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the destination peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256" /> + <BitField start="18" size="3" name="SWIDTH" description="Source transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved" /> + <BitField start="21" size="3" name="DWIDTH" description="Destination transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved" /> + <BitField start="24" size="2" name="RESERVED" description="Reserved, and must be written as 0." /> + <BitField start="26" size="1" name="SI" description="Source increment: 0 - the source address is not incremented after each transfer. 1 - the source address is incremented after each transfer." /> + <BitField start="27" size="1" name="DI" description="Destination increment: 0 - the destination address is not incremented after each transfer. 1 - the destination address is incremented after each transfer." /> + <BitField start="28" size="1" name="PROT1" description="This is provided to the peripheral during a DMA bus access and indicates that the access is in user mode or privileged mode. This information is not used in the LPC178x/177x. 0 - access is in user mode. 1 - access is in privileged mode." /> + <BitField start="29" size="1" name="PROT2" description="This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is bufferable or not bufferable. This information is not used in the LPC178x/177x. 0 - access is not bufferable. 1 - access is bufferable." /> + <BitField start="30" size="1" name="PROT3" description="This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is cacheable or not cacheable. This information is not used in the LPC178x/177x. 0 - access is not cacheable. 1 - access is cacheable." /> + <BitField start="31" size="1" name="I" description="Terminal count interrupt enable bit. 0 - the terminal count interrupt is disabled. 1 - the terminal count interrupt is enabled." /> + </Register> + <Register start="+0x110+0" size="4" name="CONFIG0" access="Read/Write" description="DMA Channel 0 Configuration Register[1]" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="E" description="Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: 0 = channel disabled. 1 = channel enabled. The Channel Enable bit status can also be found by reading the DMACEnbldChns Register. A channel is enabled by setting this bit. A channel can be disabled by clearing the Enable bit. This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled. Any data in the FIFO of the relevant channel is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached, the DMA transfer is completed, or if a channel error is encountered. If a channel must be disabled without losing data in the FIFO, the Halt bit must be set so that further DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable bit can be cleared." /> + <BitField start="1" size="5" name="SRCPERIPHERAL" description="Source peripheral. This value selects the DMA source request peripheral. This field is ignored if the source of the transfer is from memory. See Table 672 for peripheral identification." /> + <BitField start="6" size="5" name="DESTPERIPHERAL" description="Destination peripheral. This value selects the DMA destination request peripheral. This field is ignored if the destination of the transfer is to memory. See Table 672 for peripheral identification." /> + <BitField start="11" size="3" name="TRANSFERTYPE" description="This value indicates the type of transfer and specifies the flow controller. The transfer type can be memory-to-memory, memory-to-peripheral, peripheral-to-memory, or peripheral-to-peripheral. Flow can be controlled by the DMA controller, the source peripheral, or the destination peripheral. Refer to Table 694 for the encoding of this field." /> + <BitField start="14" size="1" name="IE" description="Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel." /> + <BitField start="15" size="1" name="ITC" description="Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel." /> + <BitField start="16" size="1" name="L" description="Lock. When set, this bit enables locked transfers. This information is not used in the LPC178x/177x." /> + <BitField start="17" size="1" name="A" description="Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel. This is a read-only bit." /> + <BitField start="18" size="1" name="H" description="Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The contents of the channel FIFO are drained. This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel." /> + <BitField start="19" size="13" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x110+32" size="4" name="CONFIG1" access="Read/Write" description="DMA Channel 0 Configuration Register[1]" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="E" description="Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: 0 = channel disabled. 1 = channel enabled. The Channel Enable bit status can also be found by reading the DMACEnbldChns Register. A channel is enabled by setting this bit. A channel can be disabled by clearing the Enable bit. This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled. Any data in the FIFO of the relevant channel is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached, the DMA transfer is completed, or if a channel error is encountered. If a channel must be disabled without losing data in the FIFO, the Halt bit must be set so that further DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable bit can be cleared." /> + <BitField start="1" size="5" name="SRCPERIPHERAL" description="Source peripheral. This value selects the DMA source request peripheral. This field is ignored if the source of the transfer is from memory. See Table 672 for peripheral identification." /> + <BitField start="6" size="5" name="DESTPERIPHERAL" description="Destination peripheral. This value selects the DMA destination request peripheral. This field is ignored if the destination of the transfer is to memory. See Table 672 for peripheral identification." /> + <BitField start="11" size="3" name="TRANSFERTYPE" description="This value indicates the type of transfer and specifies the flow controller. The transfer type can be memory-to-memory, memory-to-peripheral, peripheral-to-memory, or peripheral-to-peripheral. Flow can be controlled by the DMA controller, the source peripheral, or the destination peripheral. Refer to Table 694 for the encoding of this field." /> + <BitField start="14" size="1" name="IE" description="Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel." /> + <BitField start="15" size="1" name="ITC" description="Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel." /> + <BitField start="16" size="1" name="L" description="Lock. When set, this bit enables locked transfers. This information is not used in the LPC178x/177x." /> + <BitField start="17" size="1" name="A" description="Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel. This is a read-only bit." /> + <BitField start="18" size="1" name="H" description="Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The contents of the channel FIFO are drained. This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel." /> + <BitField start="19" size="13" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x110+64" size="4" name="CONFIG2" access="Read/Write" description="DMA Channel 0 Configuration Register[1]" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="E" description="Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: 0 = channel disabled. 1 = channel enabled. The Channel Enable bit status can also be found by reading the DMACEnbldChns Register. A channel is enabled by setting this bit. A channel can be disabled by clearing the Enable bit. This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled. Any data in the FIFO of the relevant channel is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached, the DMA transfer is completed, or if a channel error is encountered. If a channel must be disabled without losing data in the FIFO, the Halt bit must be set so that further DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable bit can be cleared." /> + <BitField start="1" size="5" name="SRCPERIPHERAL" description="Source peripheral. This value selects the DMA source request peripheral. This field is ignored if the source of the transfer is from memory. See Table 672 for peripheral identification." /> + <BitField start="6" size="5" name="DESTPERIPHERAL" description="Destination peripheral. This value selects the DMA destination request peripheral. This field is ignored if the destination of the transfer is to memory. See Table 672 for peripheral identification." /> + <BitField start="11" size="3" name="TRANSFERTYPE" description="This value indicates the type of transfer and specifies the flow controller. The transfer type can be memory-to-memory, memory-to-peripheral, peripheral-to-memory, or peripheral-to-peripheral. Flow can be controlled by the DMA controller, the source peripheral, or the destination peripheral. Refer to Table 694 for the encoding of this field." /> + <BitField start="14" size="1" name="IE" description="Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel." /> + <BitField start="15" size="1" name="ITC" description="Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel." /> + <BitField start="16" size="1" name="L" description="Lock. When set, this bit enables locked transfers. This information is not used in the LPC178x/177x." /> + <BitField start="17" size="1" name="A" description="Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel. This is a read-only bit." /> + <BitField start="18" size="1" name="H" description="Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The contents of the channel FIFO are drained. This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel." /> + <BitField start="19" size="13" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x110+96" size="4" name="CONFIG3" access="Read/Write" description="DMA Channel 0 Configuration Register[1]" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="E" description="Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: 0 = channel disabled. 1 = channel enabled. The Channel Enable bit status can also be found by reading the DMACEnbldChns Register. A channel is enabled by setting this bit. A channel can be disabled by clearing the Enable bit. This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled. Any data in the FIFO of the relevant channel is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached, the DMA transfer is completed, or if a channel error is encountered. If a channel must be disabled without losing data in the FIFO, the Halt bit must be set so that further DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable bit can be cleared." /> + <BitField start="1" size="5" name="SRCPERIPHERAL" description="Source peripheral. This value selects the DMA source request peripheral. This field is ignored if the source of the transfer is from memory. See Table 672 for peripheral identification." /> + <BitField start="6" size="5" name="DESTPERIPHERAL" description="Destination peripheral. This value selects the DMA destination request peripheral. This field is ignored if the destination of the transfer is to memory. See Table 672 for peripheral identification." /> + <BitField start="11" size="3" name="TRANSFERTYPE" description="This value indicates the type of transfer and specifies the flow controller. The transfer type can be memory-to-memory, memory-to-peripheral, peripheral-to-memory, or peripheral-to-peripheral. Flow can be controlled by the DMA controller, the source peripheral, or the destination peripheral. Refer to Table 694 for the encoding of this field." /> + <BitField start="14" size="1" name="IE" description="Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel." /> + <BitField start="15" size="1" name="ITC" description="Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel." /> + <BitField start="16" size="1" name="L" description="Lock. When set, this bit enables locked transfers. This information is not used in the LPC178x/177x." /> + <BitField start="17" size="1" name="A" description="Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel. This is a read-only bit." /> + <BitField start="18" size="1" name="H" description="Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The contents of the channel FIFO are drained. This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel." /> + <BitField start="19" size="13" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x110+128" size="4" name="CONFIG4" access="Read/Write" description="DMA Channel 0 Configuration Register[1]" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="E" description="Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: 0 = channel disabled. 1 = channel enabled. The Channel Enable bit status can also be found by reading the DMACEnbldChns Register. A channel is enabled by setting this bit. A channel can be disabled by clearing the Enable bit. This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled. Any data in the FIFO of the relevant channel is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached, the DMA transfer is completed, or if a channel error is encountered. If a channel must be disabled without losing data in the FIFO, the Halt bit must be set so that further DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable bit can be cleared." /> + <BitField start="1" size="5" name="SRCPERIPHERAL" description="Source peripheral. This value selects the DMA source request peripheral. This field is ignored if the source of the transfer is from memory. See Table 672 for peripheral identification." /> + <BitField start="6" size="5" name="DESTPERIPHERAL" description="Destination peripheral. This value selects the DMA destination request peripheral. This field is ignored if the destination of the transfer is to memory. See Table 672 for peripheral identification." /> + <BitField start="11" size="3" name="TRANSFERTYPE" description="This value indicates the type of transfer and specifies the flow controller. The transfer type can be memory-to-memory, memory-to-peripheral, peripheral-to-memory, or peripheral-to-peripheral. Flow can be controlled by the DMA controller, the source peripheral, or the destination peripheral. Refer to Table 694 for the encoding of this field." /> + <BitField start="14" size="1" name="IE" description="Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel." /> + <BitField start="15" size="1" name="ITC" description="Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel." /> + <BitField start="16" size="1" name="L" description="Lock. When set, this bit enables locked transfers. This information is not used in the LPC178x/177x." /> + <BitField start="17" size="1" name="A" description="Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel. This is a read-only bit." /> + <BitField start="18" size="1" name="H" description="Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The contents of the channel FIFO are drained. This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel." /> + <BitField start="19" size="13" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x110+160" size="4" name="CONFIG5" access="Read/Write" description="DMA Channel 0 Configuration Register[1]" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="E" description="Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: 0 = channel disabled. 1 = channel enabled. The Channel Enable bit status can also be found by reading the DMACEnbldChns Register. A channel is enabled by setting this bit. A channel can be disabled by clearing the Enable bit. This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled. Any data in the FIFO of the relevant channel is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached, the DMA transfer is completed, or if a channel error is encountered. If a channel must be disabled without losing data in the FIFO, the Halt bit must be set so that further DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable bit can be cleared." /> + <BitField start="1" size="5" name="SRCPERIPHERAL" description="Source peripheral. This value selects the DMA source request peripheral. This field is ignored if the source of the transfer is from memory. See Table 672 for peripheral identification." /> + <BitField start="6" size="5" name="DESTPERIPHERAL" description="Destination peripheral. This value selects the DMA destination request peripheral. This field is ignored if the destination of the transfer is to memory. See Table 672 for peripheral identification." /> + <BitField start="11" size="3" name="TRANSFERTYPE" description="This value indicates the type of transfer and specifies the flow controller. The transfer type can be memory-to-memory, memory-to-peripheral, peripheral-to-memory, or peripheral-to-peripheral. Flow can be controlled by the DMA controller, the source peripheral, or the destination peripheral. Refer to Table 694 for the encoding of this field." /> + <BitField start="14" size="1" name="IE" description="Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel." /> + <BitField start="15" size="1" name="ITC" description="Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel." /> + <BitField start="16" size="1" name="L" description="Lock. When set, this bit enables locked transfers. This information is not used in the LPC178x/177x." /> + <BitField start="17" size="1" name="A" description="Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel. This is a read-only bit." /> + <BitField start="18" size="1" name="H" description="Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The contents of the channel FIFO are drained. This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel." /> + <BitField start="19" size="13" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x110+192" size="4" name="CONFIG6" access="Read/Write" description="DMA Channel 0 Configuration Register[1]" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="E" description="Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: 0 = channel disabled. 1 = channel enabled. The Channel Enable bit status can also be found by reading the DMACEnbldChns Register. A channel is enabled by setting this bit. A channel can be disabled by clearing the Enable bit. This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled. Any data in the FIFO of the relevant channel is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached, the DMA transfer is completed, or if a channel error is encountered. If a channel must be disabled without losing data in the FIFO, the Halt bit must be set so that further DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable bit can be cleared." /> + <BitField start="1" size="5" name="SRCPERIPHERAL" description="Source peripheral. This value selects the DMA source request peripheral. This field is ignored if the source of the transfer is from memory. See Table 672 for peripheral identification." /> + <BitField start="6" size="5" name="DESTPERIPHERAL" description="Destination peripheral. This value selects the DMA destination request peripheral. This field is ignored if the destination of the transfer is to memory. See Table 672 for peripheral identification." /> + <BitField start="11" size="3" name="TRANSFERTYPE" description="This value indicates the type of transfer and specifies the flow controller. The transfer type can be memory-to-memory, memory-to-peripheral, peripheral-to-memory, or peripheral-to-peripheral. Flow can be controlled by the DMA controller, the source peripheral, or the destination peripheral. Refer to Table 694 for the encoding of this field." /> + <BitField start="14" size="1" name="IE" description="Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel." /> + <BitField start="15" size="1" name="ITC" description="Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel." /> + <BitField start="16" size="1" name="L" description="Lock. When set, this bit enables locked transfers. This information is not used in the LPC178x/177x." /> + <BitField start="17" size="1" name="A" description="Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel. This is a read-only bit." /> + <BitField start="18" size="1" name="H" description="Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The contents of the channel FIFO are drained. This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel." /> + <BitField start="19" size="13" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x110+224" size="4" name="CONFIG7" access="Read/Write" description="DMA Channel 0 Configuration Register[1]" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="E" description="Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: 0 = channel disabled. 1 = channel enabled. The Channel Enable bit status can also be found by reading the DMACEnbldChns Register. A channel is enabled by setting this bit. A channel can be disabled by clearing the Enable bit. This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled. Any data in the FIFO of the relevant channel is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached, the DMA transfer is completed, or if a channel error is encountered. If a channel must be disabled without losing data in the FIFO, the Halt bit must be set so that further DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable bit can be cleared." /> + <BitField start="1" size="5" name="SRCPERIPHERAL" description="Source peripheral. This value selects the DMA source request peripheral. This field is ignored if the source of the transfer is from memory. See Table 672 for peripheral identification." /> + <BitField start="6" size="5" name="DESTPERIPHERAL" description="Destination peripheral. This value selects the DMA destination request peripheral. This field is ignored if the destination of the transfer is to memory. See Table 672 for peripheral identification." /> + <BitField start="11" size="3" name="TRANSFERTYPE" description="This value indicates the type of transfer and specifies the flow controller. The transfer type can be memory-to-memory, memory-to-peripheral, peripheral-to-memory, or peripheral-to-peripheral. Flow can be controlled by the DMA controller, the source peripheral, or the destination peripheral. Refer to Table 694 for the encoding of this field." /> + <BitField start="14" size="1" name="IE" description="Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel." /> + <BitField start="15" size="1" name="ITC" description="Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel." /> + <BitField start="16" size="1" name="L" description="Lock. When set, this bit enables locked transfers. This information is not used in the LPC178x/177x." /> + <BitField start="17" size="1" name="A" description="Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel. This is a read-only bit." /> + <BitField start="18" size="1" name="H" description="Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The contents of the channel FIFO are drained. This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel." /> + <BitField start="19" size="13" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + </RegisterGroup> + <RegisterGroup name="USB" start="0x50008000" description="USB device/host/OTG controller"> + <Register start="+0x100" size="4" name="INTST" access="ReadOnly" description="OTG Interrupt Status" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="TMR" description="Timer time-out." /> + <BitField start="1" size="1" name="REMOVE_PU" description="Remove pull-up. This bit is set by hardware to indicate that software needs to disable the D+ pull-up resistor." /> + <BitField start="2" size="1" name="HNP_FAILURE" description="HNP failed. This bit is set by hardware to indicate that the HNP switching has failed." /> + <BitField start="3" size="1" name="HNP_SUCCESS" description="HNP succeeded. This bit is set by hardware to indicate that the HNP switching has succeeded." /> + <BitField start="4" size="28" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x104" size="4" name="INTEN" access="Read/Write" description="OTG Interrupt Enable" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="TMR_EN" description="1 = enable the corresponding bit in the IntSt register." /> + <BitField start="1" size="1" name="REMOVE_PU_EN" description="1 = enable the corresponding bit in the IntSt register." /> + <BitField start="2" size="1" name="HNP_FAILURE_EN" description="1 = enable the corresponding bit in the IntSt register." /> + <BitField start="3" size="1" name="HNP_SUCCES_EN" description="1 = enable the corresponding bit in the IntSt register." /> + <BitField start="4" size="28" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x108" size="4" name="INTSET" access="WriteOnly" description="OTG Interrupt Set" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="TMR_SET" description="0 = no effect. 1 = set the corresponding bit in the IntSt register." /> + <BitField start="1" size="1" name="REMOVE_PU_SET" description="0 = no effect. 1 = set the corresponding bit in the IntSt register." /> + <BitField start="2" size="1" name="HNP_FAILURE_SET" description="0 = no effect. 1 = set the corresponding bit in the IntSt register." /> + <BitField start="3" size="1" name="HNP_SUCCES_SET" description="0 = no effect. 1 = set the corresponding bit in the IntSt register." /> + <BitField start="4" size="28" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x10C" size="4" name="INTCLR" access="WriteOnly" description="OTG Interrupt Clear" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="1" name="TMR_CLR" description="0 = no effect. 1 = clear the corresponding bit in the IntSt register." /> + <BitField start="1" size="1" name="REMOVE_PU_CLR" description="0 = no effect. 1 = clear the corresponding bit in the IntSt register." /> + <BitField start="2" size="1" name="HNP_FAILURE_CLR" description="0 = no effect. 1 = clear the corresponding bit in the IntSt register." /> + <BitField start="3" size="1" name="HNP_SUCCES_CLR" description="0 = no effect. 1 = clear the corresponding bit in the IntSt register." /> + <BitField start="4" size="28" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x110" size="4" name="STCTRL" access="Read/Write" description="OTG Status and Control and USB port select" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="2" name="PORT_FUNC" description="Controls connection of USB functions (see Figure 51). Bit 0 is set or cleared by hardware when B_HNP_TRACK or A_HNP_TRACK is set and HNP succeeds. See Section 14.9. 00: U1 = device (OTG), U2 = host 01: U1 = host (OTG), U2 = host 10: Reserved 11: U1 = host, U2 = device In a device-only configuration, the following values are allowed: 00: U1 = device. The USB device controller signals are mapped to the U1 port: USB_CONNECT1, USB_UP_LED1, USB_D+1, USB_D-1. 11: U2 = device. The USB device controller signals are mapped to the U2 port: USB_CONNECT2, USB_UP_LED2, USB_D+2, USB_D-2." /> + <BitField start="2" size="2" name="TMR_SCALE" description="Timer scale selection. This field determines the duration of each timer count. 00: 10 ms (100 KHz) 01: 100 ms (10 KHz) 10: 1000 ms (1 KHz) 11: Reserved" /> + <BitField start="4" size="1" name="TMR_MODE" description="Timer mode selection. 0: monoshot 1: free running" /> + <BitField start="5" size="1" name="TMR_EN" description="Timer enable. When set, TMR_CNT increments. When cleared, TMR_CNT is reset to 0." /> + <BitField start="6" size="1" name="TMR_RST" description="Timer reset. Writing one to this bit resets TMR_CNT to 0. This provides a single bit control for the software to restart the timer when the timer is enabled." /> + <BitField start="7" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="8" size="1" name="B_HNP_TRACK" description="Enable HNP tracking for B-device (peripheral), see Section 14.9. Hardware clears this bit when HNP_SUCCESS or HNP_FAILURE is set." /> + <BitField start="9" size="1" name="A_HNP_TRACK" description="Enable HNP tracking for A-device (host), see Section 14.9. Hardware clears this bit when HNP_SUCCESS or HNP_FAILURE is set." /> + <BitField start="10" size="1" name="PU_REMOVED" description="When the B-device changes its role from peripheral to host, software sets this bit when it removes the D+ pull-up, see Section 14.9. Hardware clears this bit when HNP_SUCCESS or HNP_FAILURE is set." /> + <BitField start="11" size="5" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="16" size="16" name="TMR_CNT" description="Current timer count value." /> + </Register> + <Register start="+0x114" size="4" name="TMR" access="Read/Write" description="OTG Timer" reset_value="0xFFFF" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="16" name="TIMEOUT_CNT" description="The TMR interrupt is set when TMR_CNT reaches this value." /> + <BitField start="16" size="16" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x200" size="4" name="DEVINTST" access="ReadOnly" description="USB Device Interrupt Status" reset_value="0x10" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="FRAME" description="The frame interrupt occurs every 1 ms. This is used in isochronous packet transfers." /> + <BitField start="1" size="1" name="EP_FAST" description="Fast endpoint interrupt. If an Endpoint Interrupt Priority register (USBEpIntPri) bit is set, the corresponding endpoint interrupt will be routed to this bit." /> + <BitField start="2" size="1" name="EP_SLOW" description="Slow endpoints interrupt. If an Endpoint Interrupt Priority Register (USBEpIntPri) bit is not set, the corresponding endpoint interrupt will be routed to this bit." /> + <BitField start="3" size="1" name="DEV_STAT" description="Set when USB Bus reset, USB suspend change or Connect change event occurs. Refer to Section 13.12.6 Set Device Status (Command: 0xFE, Data: write 1 byte) on page 366." /> + <BitField start="4" size="1" name="CCEMPTY" description="The command code register (USBCmdCode) is empty (New command can be written)." /> + <BitField start="5" size="1" name="CDFULL" description="Command data register (USBCmdData) is full (Data can be read now)." /> + <BitField start="6" size="1" name="RxENDPKT" description="The current packet in the endpoint buffer is transferred to the CPU." /> + <BitField start="7" size="1" name="TxENDPKT" description="The number of data bytes transferred to the endpoint buffer equals the number of bytes programmed in the TxPacket length register (USBTxPLen)." /> + <BitField start="8" size="1" name="EP_RLZED" description="Endpoints realized. Set when Realize Endpoint register (USBReEp) or MaxPacketSize register (USBMaxPSize) is updated and the corresponding operation is completed." /> + <BitField start="9" size="1" name="ERR_INT" description="Error Interrupt. Any bus error interrupt from the USB device. Refer to Section 13.12.9 Read Error Status (Command: 0xFB, Data: read 1 byte) on page 368" /> + <BitField start="10" size="22" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x204" size="4" name="DEVINTEN" access="Read/Write" description="USB Device Interrupt Enable" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="FRAMEEN" description="0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri." /> + <BitField start="1" size="1" name="EP_FASTEN" description="0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri." /> + <BitField start="2" size="1" name="EP_SLOWEN" description="0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri." /> + <BitField start="3" size="1" name="DEV_STATEN" description="0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri." /> + <BitField start="4" size="1" name="CCEMPTYEN" description="0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri." /> + <BitField start="5" size="1" name="CDFULLEN" description="0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri." /> + <BitField start="6" size="1" name="RxENDPKTEN" description="0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri." /> + <BitField start="7" size="1" name="TxENDPKTEN" description="0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri." /> + <BitField start="8" size="1" name="EP_RLZEDEN" description="0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri." /> + <BitField start="9" size="1" name="ERR_INTEN" description="0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri." /> + <BitField start="10" size="22" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x208" size="4" name="DEVINTCLR" access="WriteOnly" description="USB Device Interrupt Clear" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="FRAMECLR" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared." /> + <BitField start="1" size="1" name="EP_FASTCLR" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared." /> + <BitField start="2" size="1" name="EP_SLOWCLR" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared." /> + <BitField start="3" size="1" name="DEV_STATCLR" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared." /> + <BitField start="4" size="1" name="CCEMPTYCLR" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared." /> + <BitField start="5" size="1" name="CDFULLCLR" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared." /> + <BitField start="6" size="1" name="RxENDPKTCLR" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared." /> + <BitField start="7" size="1" name="TxENDPKTCLR" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared." /> + <BitField start="8" size="1" name="EP_RLZEDCLR" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared." /> + <BitField start="9" size="1" name="ERR_INTCLR" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared." /> + <BitField start="10" size="22" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x20C" size="4" name="DEVINTSET" access="WriteOnly" description="USB Device Interrupt Set" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="FRAMESET" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set." /> + <BitField start="1" size="1" name="EP_FASTSET" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set." /> + <BitField start="2" size="1" name="EP_SLOWSET" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set." /> + <BitField start="3" size="1" name="DEV_STATSET" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set." /> + <BitField start="4" size="1" name="CCEMPTYSET" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set." /> + <BitField start="5" size="1" name="CDFULLSET" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set." /> + <BitField start="6" size="1" name="RxENDPKTSET" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set." /> + <BitField start="7" size="1" name="TxENDPKTSET" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set." /> + <BitField start="8" size="1" name="EP_RLZEDSET" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set." /> + <BitField start="9" size="1" name="ERR_INTSET" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set." /> + <BitField start="10" size="22" name="RESERVED" description="Reserved" /> + </Register> + <Register start="+0x210" size="4" name="CMDCODE" access="WriteOnly" description="USB Command Code" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="8" size="8" name="CMD_PHASE" description="The command phase:"> + <Enum name="READ" start="0x02" description="Read" /> + <Enum name="WRITE" start="0x01" description="Write" /> + <Enum name="COMMAND" start="0x05" description="Command" /> + </BitField> + <BitField start="16" size="8" name="CMD_CODE_WDATA" description="This is a multi-purpose field. When CMD_PHASE is Command or Read, this field contains the code for the command (CMD_CODE). When CMD_PHASE is Write, this field contains the command write data (CMD_WDATA)." /> + <BitField start="24" size="8" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x214" size="4" name="CMDDATA" access="ReadOnly" description="USB Command Data" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="CMD_RDATA" description="Command Read Data." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x218" size="4" name="RXDATA" access="ReadOnly" description="USB Receive Data" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="RX_DATA" description="Data received." /> + </Register> + <Register start="+0x21C" size="4" name="TXDATA" access="WriteOnly" description="USB Transmit Data" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="32" name="TX_DATA" description="Transmit Data." /> + </Register> + <Register start="+220" size="4" name="RXPLEN" access="ReadOnly" description="USB Receive Packet Length" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="10" name="PKT_LNGTH" description="The remaining number of bytes to be read from the currently selected endpoint's buffer. When this field decrements to 0, the RxENDPKT bit will be set in USBDevIntSt." /> + <BitField start="10" size="1" name="DV" description="Data valid. This bit is useful for isochronous endpoints. Non-isochronous endpoints do not raise an interrupt when an erroneous data packet is received. But invalid data packet can be produced with a bus reset. For isochronous endpoints, data transfer will happen even if an erroneous packet is received. In this case DV bit will not be set for the packet."> + <Enum name="DATA_IS_INVALID_" start="0" description="Data is invalid." /> + <Enum name="DATA_IS_VALID_" start="1" description="Data is valid." /> + </BitField> + <BitField start="11" size="1" name="PKT_RDY" description="The PKT_LNGTH field is valid and the packet is ready for reading." /> + <BitField start="12" size="20" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x224" size="4" name="TXPLEN" access="WriteOnly" description="USB Transmit Packet Length" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="10" name="PKT_LNGTH" description="The remaining number of bytes to be written to the selected endpoint buffer. This field is decremented by 4 by hardware after each write to USBTxData. When this field decrements to 0, the TxENDPKT bit will be set in USBDevIntSt." /> + <BitField start="10" size="22" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x228" size="4" name="CTRL" access="Read/Write" description="USB Control" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RD_EN" description="Read mode control. Enables reading data from the OUT endpoint buffer for the endpoint specified in the LOG_ENDPOINT field using the USBRxData register. This bit is cleared by hardware when the last word of the current packet is read from USBRxData."> + <Enum name="DISABLED_" start="0" description="Disabled." /> + <Enum name="ENABLED_" start="1" description="Enabled." /> + </BitField> + <BitField start="1" size="1" name="WR_EN" description="Write mode control. Enables writing data to the IN endpoint buffer for the endpoint specified in the LOG_ENDPOINT field using the USBTxData register. This bit is cleared by hardware when the number of bytes in USBTxLen have been sent."> + <Enum name="DISABLED_" start="0" description="Disabled." /> + <Enum name="ENABLED_" start="1" description="Enabled." /> + </BitField> + <BitField start="2" size="4" name="LOG_ENDPOINT" description="Logical Endpoint number." /> + <BitField start="6" size="26" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x22C" size="4" name="DEVINTPRI" access="WriteOnly" description="USB Device Interrupt Priority" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="FRAME" description="Frame interrupt routing"> + <Enum name="LP" start="0" description="FRAME interrupt is routed to USB_INT_REQ_LP." /> + <Enum name="HP" start="1" description="FRAME interrupt is routed to USB_INT_REQ_HP." /> + </BitField> + <BitField start="1" size="1" name="EP_FAST" description="Fast endpoint interrupt routing"> + <Enum name="LP" start="0" description="EP_FAST interrupt is routed to USB_INT_REQ_LP." /> + <Enum name="HP" start="1" description="EP_FAST interrupt is routed to USB_INT_REQ_HP." /> + </BitField> + <BitField start="2" size="30" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x230" size="4" name="EPINTST" access="ReadOnly" description="USB Endpoint Interrupt Status" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="EPST0" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." /> + <BitField start="1" size="1" name="EPST1" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." /> + <BitField start="2" size="1" name="EPST2" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." /> + <BitField start="3" size="1" name="EPST3" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." /> + <BitField start="4" size="1" name="EPST4" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." /> + <BitField start="5" size="1" name="EPST5" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." /> + <BitField start="6" size="1" name="EPST6" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." /> + <BitField start="7" size="1" name="EPST7" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." /> + <BitField start="8" size="1" name="EPST8" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." /> + <BitField start="9" size="1" name="EPST9" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." /> + <BitField start="10" size="1" name="EPST10" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." /> + <BitField start="11" size="1" name="EPST11" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." /> + <BitField start="12" size="1" name="EPST12" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." /> + <BitField start="13" size="1" name="EPST13" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." /> + <BitField start="14" size="1" name="EPST14" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." /> + <BitField start="15" size="1" name="EPST15" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." /> + <BitField start="16" size="1" name="EPST16" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." /> + <BitField start="17" size="1" name="EPST17" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." /> + <BitField start="18" size="1" name="EPST18" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." /> + <BitField start="19" size="1" name="EPST19" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." /> + <BitField start="20" size="1" name="EPST20" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." /> + <BitField start="21" size="1" name="EPST21" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." /> + <BitField start="22" size="1" name="EPST22" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." /> + <BitField start="23" size="1" name="EPST23" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." /> + <BitField start="24" size="1" name="EPST24" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." /> + <BitField start="25" size="1" name="EPST25" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." /> + <BitField start="26" size="1" name="EPST26" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." /> + <BitField start="27" size="1" name="EPST27" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." /> + <BitField start="28" size="1" name="EPST28" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." /> + <BitField start="29" size="1" name="EPST29" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." /> + <BitField start="30" size="1" name="EPST30" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." /> + <BitField start="31" size="1" name="EPST31" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." /> + </Register> + <Register start="+0x234" size="4" name="EPINTEN" access="Read/Write" description="USB Endpoint Interrupt Enable" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="EPEN0" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." /> + <BitField start="1" size="1" name="EPEN1" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." /> + <BitField start="2" size="1" name="EPEN2" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." /> + <BitField start="3" size="1" name="EPEN3" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." /> + <BitField start="4" size="1" name="EPEN4" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." /> + <BitField start="5" size="1" name="EPEN5" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." /> + <BitField start="6" size="1" name="EPEN6" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." /> + <BitField start="7" size="1" name="EPEN7" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." /> + <BitField start="8" size="1" name="EPEN8" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." /> + <BitField start="9" size="1" name="EPEN9" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." /> + <BitField start="10" size="1" name="EPEN10" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." /> + <BitField start="11" size="1" name="EPEN11" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." /> + <BitField start="12" size="1" name="EPEN12" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." /> + <BitField start="13" size="1" name="EPEN13" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." /> + <BitField start="14" size="1" name="EPEN14" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." /> + <BitField start="15" size="1" name="EPEN15" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." /> + <BitField start="16" size="1" name="EPEN16" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." /> + <BitField start="17" size="1" name="EPEN17" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." /> + <BitField start="18" size="1" name="EPEN18" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." /> + <BitField start="19" size="1" name="EPEN19" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." /> + <BitField start="20" size="1" name="EPEN20" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." /> + <BitField start="21" size="1" name="EPEN21" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." /> + <BitField start="22" size="1" name="EPEN22" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." /> + <BitField start="23" size="1" name="EPEN23" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." /> + <BitField start="24" size="1" name="EPEN24" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." /> + <BitField start="25" size="1" name="EPEN25" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." /> + <BitField start="26" size="1" name="EPEN26" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." /> + <BitField start="27" size="1" name="EPEN27" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." /> + <BitField start="28" size="1" name="EPEN28" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." /> + <BitField start="29" size="1" name="EPEN29" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." /> + <BitField start="30" size="1" name="EPEN30" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." /> + <BitField start="31" size="1" name="EPEN31" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." /> + </Register> + <Register start="+0x238" size="4" name="EPINTCLR" access="WriteOnly" description="USB Endpoint Interrupt Clear" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="EPCLR0" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." /> + <BitField start="1" size="1" name="EPCLR1" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." /> + <BitField start="2" size="1" name="EPCLR2" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." /> + <BitField start="3" size="1" name="EPCLR3" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." /> + <BitField start="4" size="1" name="EPCLR4" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." /> + <BitField start="5" size="1" name="EPCLR5" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." /> + <BitField start="6" size="1" name="EPCLR6" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." /> + <BitField start="7" size="1" name="EPCLR7" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." /> + <BitField start="8" size="1" name="EPCLR8" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." /> + <BitField start="9" size="1" name="EPCLR9" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." /> + <BitField start="10" size="1" name="EPCLR10" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." /> + <BitField start="11" size="1" name="EPCLR11" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." /> + <BitField start="12" size="1" name="EPCLR12" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." /> + <BitField start="13" size="1" name="EPCLR13" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." /> + <BitField start="14" size="1" name="EPCLR14" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." /> + <BitField start="15" size="1" name="EPCLR15" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." /> + <BitField start="16" size="1" name="EPCLR16" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." /> + <BitField start="17" size="1" name="EPCLR17" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." /> + <BitField start="18" size="1" name="EPCLR18" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." /> + <BitField start="19" size="1" name="EPCLR19" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." /> + <BitField start="20" size="1" name="EPCLR20" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." /> + <BitField start="21" size="1" name="EPCLR21" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." /> + <BitField start="22" size="1" name="EPCLR22" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." /> + <BitField start="23" size="1" name="EPCLR23" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." /> + <BitField start="24" size="1" name="EPCLR24" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." /> + <BitField start="25" size="1" name="EPCLR25" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." /> + <BitField start="26" size="1" name="EPCLR26" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." /> + <BitField start="27" size="1" name="EPCLR27" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." /> + <BitField start="28" size="1" name="EPCLR28" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." /> + <BitField start="29" size="1" name="EPCLR29" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." /> + <BitField start="30" size="1" name="EPCLR30" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." /> + <BitField start="31" size="1" name="EPCLR31" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." /> + </Register> + <Register start="+0x23C" size="4" name="EPINTSET" access="WriteOnly" description="USB Endpoint Interrupt Set" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="EPSET0" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." /> + <BitField start="1" size="1" name="EPSET1" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." /> + <BitField start="2" size="1" name="EPSET2" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." /> + <BitField start="3" size="1" name="EPSET3" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." /> + <BitField start="4" size="1" name="EPSET4" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." /> + <BitField start="5" size="1" name="EPSET5" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." /> + <BitField start="6" size="1" name="EPSET6" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." /> + <BitField start="7" size="1" name="EPSET7" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." /> + <BitField start="8" size="1" name="EPSET8" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." /> + <BitField start="9" size="1" name="EPSET9" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." /> + <BitField start="10" size="1" name="EPSET10" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." /> + <BitField start="11" size="1" name="EPSET11" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." /> + <BitField start="12" size="1" name="EPSET12" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." /> + <BitField start="13" size="1" name="EPSET13" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." /> + <BitField start="14" size="1" name="EPSET14" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." /> + <BitField start="15" size="1" name="EPSET15" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." /> + <BitField start="16" size="1" name="EPSET16" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." /> + <BitField start="17" size="1" name="EPSET17" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." /> + <BitField start="18" size="1" name="EPSET18" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." /> + <BitField start="19" size="1" name="EPSET19" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." /> + <BitField start="20" size="1" name="EPSET20" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." /> + <BitField start="21" size="1" name="EPSET21" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." /> + <BitField start="22" size="1" name="EPSET22" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." /> + <BitField start="23" size="1" name="EPSET23" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." /> + <BitField start="24" size="1" name="EPSET24" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." /> + <BitField start="25" size="1" name="EPSET25" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." /> + <BitField start="26" size="1" name="EPSET26" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." /> + <BitField start="27" size="1" name="EPSET27" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." /> + <BitField start="28" size="1" name="EPSET28" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." /> + <BitField start="29" size="1" name="EPSET29" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." /> + <BitField start="30" size="1" name="EPSET30" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." /> + <BitField start="31" size="1" name="EPSET31" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." /> + </Register> + <Register start="+0x240" size="4" name="EPINTPRI" access="WriteOnly" description="USB Endpoint Priority" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="EPPRI0" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" /> + <BitField start="1" size="1" name="EPPRI1" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" /> + <BitField start="2" size="1" name="EPPRI2" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" /> + <BitField start="3" size="1" name="EPPRI3" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" /> + <BitField start="4" size="1" name="EPPRI4" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" /> + <BitField start="5" size="1" name="EPPRI5" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" /> + <BitField start="6" size="1" name="EPPRI6" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" /> + <BitField start="7" size="1" name="EPPRI7" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" /> + <BitField start="8" size="1" name="EPPRI8" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" /> + <BitField start="9" size="1" name="EPPRI9" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" /> + <BitField start="10" size="1" name="EPPRI10" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" /> + <BitField start="11" size="1" name="EPPRI11" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" /> + <BitField start="12" size="1" name="EPPRI12" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" /> + <BitField start="13" size="1" name="EPPRI13" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" /> + <BitField start="14" size="1" name="EPPRI14" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" /> + <BitField start="15" size="1" name="EPPRI15" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" /> + <BitField start="16" size="1" name="EPPRI16" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" /> + <BitField start="17" size="1" name="EPPRI17" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" /> + <BitField start="18" size="1" name="EPPRI18" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" /> + <BitField start="19" size="1" name="EPPRI19" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" /> + <BitField start="20" size="1" name="EPPRI20" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" /> + <BitField start="21" size="1" name="EPPRI21" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" /> + <BitField start="22" size="1" name="EPPRI22" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" /> + <BitField start="23" size="1" name="EPPRI23" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" /> + <BitField start="24" size="1" name="EPPRI24" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" /> + <BitField start="25" size="1" name="EPPRI25" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" /> + <BitField start="26" size="1" name="EPPRI26" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" /> + <BitField start="27" size="1" name="EPPRI27" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" /> + <BitField start="28" size="1" name="EPPRI28" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" /> + <BitField start="29" size="1" name="EPPRI29" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" /> + <BitField start="30" size="1" name="EPPRI30" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" /> + <BitField start="31" size="1" name="EPPRI31" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" /> + </Register> + <Register start="+0x244" size="4" name="REEP" access="Read/Write" description="USB Realize Endpoint" reset_value="0x3" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="EPR0" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." /> + <BitField start="1" size="1" name="EPR1" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." /> + <BitField start="2" size="1" name="EPR2" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." /> + <BitField start="3" size="1" name="EPR3" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." /> + <BitField start="4" size="1" name="EPR4" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." /> + <BitField start="5" size="1" name="EPR5" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." /> + <BitField start="6" size="1" name="EPR6" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." /> + <BitField start="7" size="1" name="EPR7" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." /> + <BitField start="8" size="1" name="EPR8" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." /> + <BitField start="9" size="1" name="EPR9" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." /> + <BitField start="10" size="1" name="EPR10" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." /> + <BitField start="11" size="1" name="EPR11" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." /> + <BitField start="12" size="1" name="EPR12" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." /> + <BitField start="13" size="1" name="EPR13" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." /> + <BitField start="14" size="1" name="EPR14" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." /> + <BitField start="15" size="1" name="EPR15" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." /> + <BitField start="16" size="1" name="EPR16" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." /> + <BitField start="17" size="1" name="EPR17" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." /> + <BitField start="18" size="1" name="EPR18" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." /> + <BitField start="19" size="1" name="EPR19" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." /> + <BitField start="20" size="1" name="EPR20" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." /> + <BitField start="21" size="1" name="EPR21" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." /> + <BitField start="22" size="1" name="EPR22" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." /> + <BitField start="23" size="1" name="EPR23" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." /> + <BitField start="24" size="1" name="EPR24" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." /> + <BitField start="25" size="1" name="EPR25" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." /> + <BitField start="26" size="1" name="EPR26" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." /> + <BitField start="27" size="1" name="EPR27" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." /> + <BitField start="28" size="1" name="EPR28" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." /> + <BitField start="29" size="1" name="EPR29" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." /> + <BitField start="30" size="1" name="EPR30" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." /> + <BitField start="31" size="1" name="EPR31" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." /> + </Register> + <Register start="+0x248" size="4" name="EPIND" access="WriteOnly" description="USB Endpoint Index" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="5" name="PHY_EP" description="Physical endpoint number (0-31)" /> + <BitField start="5" size="27" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x24C" size="4" name="MAXPSIZE" access="Read/Write" description="USB MaxPacketSize" reset_value="0x8" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="10" name="MPS" description="The maximum packet size value." /> + <BitField start="10" size="22" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x250" size="4" name="DMARST" access="ReadOnly" description="USB DMA Request Status" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="EPRST0" description="Control endpoint OUT (DMA cannot be enabled for this endpoint and EP0 bit must be 0)." /> + <BitField start="1" size="1" name="EPRST1" description="Control endpoint IN (DMA cannot be enabled for this endpoint and EP1 bit must be 0)." /> + <BitField start="2" size="1" name="EPRST2" description="Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." /> + <BitField start="3" size="1" name="EPRST3" description="Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." /> + <BitField start="4" size="1" name="EPRST4" description="Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." /> + <BitField start="5" size="1" name="EPRST5" description="Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." /> + <BitField start="6" size="1" name="EPRST6" description="Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." /> + <BitField start="7" size="1" name="EPRST7" description="Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." /> + <BitField start="8" size="1" name="EPRST8" description="Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." /> + <BitField start="9" size="1" name="EPRST9" description="Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." /> + <BitField start="10" size="1" name="EPRST10" description="Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." /> + <BitField start="11" size="1" name="EPRST11" description="Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." /> + <BitField start="12" size="1" name="EPRST12" description="Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." /> + <BitField start="13" size="1" name="EPRST13" description="Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." /> + <BitField start="14" size="1" name="EPRST14" description="Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." /> + <BitField start="15" size="1" name="EPRST15" description="Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." /> + <BitField start="16" size="1" name="EPRST16" description="Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." /> + <BitField start="17" size="1" name="EPRST17" description="Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." /> + <BitField start="18" size="1" name="EPRST18" description="Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." /> + <BitField start="19" size="1" name="EPRST19" description="Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." /> + <BitField start="20" size="1" name="EPRST20" description="Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." /> + <BitField start="21" size="1" name="EPRST21" description="Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." /> + <BitField start="22" size="1" name="EPRST22" description="Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." /> + <BitField start="23" size="1" name="EPRST23" description="Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." /> + <BitField start="24" size="1" name="EPRST24" description="Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." /> + <BitField start="25" size="1" name="EPRST25" description="Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." /> + <BitField start="26" size="1" name="EPRST26" description="Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." /> + <BitField start="27" size="1" name="EPRST27" description="Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." /> + <BitField start="28" size="1" name="EPRST28" description="Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." /> + <BitField start="29" size="1" name="EPRST29" description="Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." /> + <BitField start="30" size="1" name="EPRST30" description="Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." /> + <BitField start="31" size="1" name="EPRST31" description="Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." /> + </Register> + <Register start="+0x254" size="4" name="DMARCLR" access="WriteOnly" description="USB DMA Request Clear" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="EPRCLR0" description="Control endpoint OUT (DMA cannot be enabled for this endpoint and the EP0 bit must be 0)." /> + <BitField start="1" size="1" name="EPRCLR1" description="Control endpoint IN (DMA cannot be enabled for this endpoint and the EP1 bit must be 0)." /> + <BitField start="2" size="1" name="EPRCLR2" description="Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." /> + <BitField start="3" size="1" name="EPRCLR3" description="Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." /> + <BitField start="4" size="1" name="EPRCLR4" description="Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." /> + <BitField start="5" size="1" name="EPRCLR5" description="Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." /> + <BitField start="6" size="1" name="EPRCLR6" description="Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." /> + <BitField start="7" size="1" name="EPRCLR7" description="Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." /> + <BitField start="8" size="1" name="EPRCLR8" description="Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." /> + <BitField start="9" size="1" name="EPRCLR9" description="Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." /> + <BitField start="10" size="1" name="EPRCLR10" description="Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." /> + <BitField start="11" size="1" name="EPRCLR11" description="Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." /> + <BitField start="12" size="1" name="EPRCLR12" description="Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." /> + <BitField start="13" size="1" name="EPRCLR13" description="Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." /> + <BitField start="14" size="1" name="EPRCLR14" description="Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." /> + <BitField start="15" size="1" name="EPRCLR15" description="Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." /> + <BitField start="16" size="1" name="EPRCLR16" description="Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." /> + <BitField start="17" size="1" name="EPRCLR17" description="Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." /> + <BitField start="18" size="1" name="EPRCLR18" description="Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." /> + <BitField start="19" size="1" name="EPRCLR19" description="Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." /> + <BitField start="20" size="1" name="EPRCLR20" description="Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." /> + <BitField start="21" size="1" name="EPRCLR21" description="Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." /> + <BitField start="22" size="1" name="EPRCLR22" description="Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." /> + <BitField start="23" size="1" name="EPRCLR23" description="Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." /> + <BitField start="24" size="1" name="EPRCLR24" description="Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." /> + <BitField start="25" size="1" name="EPRCLR25" description="Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." /> + <BitField start="26" size="1" name="EPRCLR26" description="Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." /> + <BitField start="27" size="1" name="EPRCLR27" description="Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." /> + <BitField start="28" size="1" name="EPRCLR28" description="Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." /> + <BitField start="29" size="1" name="EPRCLR29" description="Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." /> + <BitField start="30" size="1" name="EPRCLR30" description="Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." /> + <BitField start="31" size="1" name="EPRCLR31" description="Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." /> + </Register> + <Register start="+0x258" size="4" name="DMARSET" access="WriteOnly" description="USB DMA Request Set" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="EPRSET0" description="Control endpoint OUT (DMA cannot be enabled for this endpoint and the EP0 bit must be 0)." /> + <BitField start="1" size="1" name="EPRSET1" description="Control endpoint IN (DMA cannot be enabled for this endpoint and the EP1 bit must be 0)." /> + <BitField start="2" size="1" name="EPRSET2" description="Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." /> + <BitField start="3" size="1" name="EPRSET3" description="Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." /> + <BitField start="4" size="1" name="EPRSET4" description="Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." /> + <BitField start="5" size="1" name="EPRSET5" description="Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." /> + <BitField start="6" size="1" name="EPRSET6" description="Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." /> + <BitField start="7" size="1" name="EPRSET7" description="Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." /> + <BitField start="8" size="1" name="EPRSET8" description="Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." /> + <BitField start="9" size="1" name="EPRSET9" description="Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." /> + <BitField start="10" size="1" name="EPRSET10" description="Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." /> + <BitField start="11" size="1" name="EPRSET11" description="Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." /> + <BitField start="12" size="1" name="EPRSET12" description="Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." /> + <BitField start="13" size="1" name="EPRSET13" description="Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." /> + <BitField start="14" size="1" name="EPRSET14" description="Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." /> + <BitField start="15" size="1" name="EPRSET15" description="Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." /> + <BitField start="16" size="1" name="EPRSET16" description="Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." /> + <BitField start="17" size="1" name="EPRSET17" description="Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." /> + <BitField start="18" size="1" name="EPRSET18" description="Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." /> + <BitField start="19" size="1" name="EPRSET19" description="Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." /> + <BitField start="20" size="1" name="EPRSET20" description="Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." /> + <BitField start="21" size="1" name="EPRSET21" description="Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." /> + <BitField start="22" size="1" name="EPRSET22" description="Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." /> + <BitField start="23" size="1" name="EPRSET23" description="Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." /> + <BitField start="24" size="1" name="EPRSET24" description="Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." /> + <BitField start="25" size="1" name="EPRSET25" description="Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." /> + <BitField start="26" size="1" name="EPRSET26" description="Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." /> + <BitField start="27" size="1" name="EPRSET27" description="Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." /> + <BitField start="28" size="1" name="EPRSET28" description="Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." /> + <BitField start="29" size="1" name="EPRSET29" description="Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." /> + <BitField start="30" size="1" name="EPRSET30" description="Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." /> + <BitField start="31" size="1" name="EPRSET31" description="Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." /> + </Register> + <Register start="+0x280" size="4" name="UDCAH" access="Read/Write" description="USB UDCA Head" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="7" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written. The UDCA is aligned to 128-byte boundaries." /> + <BitField start="7" size="25" name="UDCA_ADDR" description="Start address of the UDCA." /> + </Register> + <Register start="+0x284" size="4" name="EPDMAST" access="ReadOnly" description="USB Endpoint DMA Status" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="EP_DMA_ST0" description="Control endpoint OUT (DMA cannot be enabled for this endpoint and the EP0_DMA_ENABLE bit must be 0)." /> + <BitField start="1" size="1" name="EP_DMA_ST1" description="Control endpoint IN (DMA cannot be enabled for this endpoint and the EP1_DMA_ENABLE bit must be 0)." /> + <BitField start="2" size="1" name="EP_DMA_ST2" description="Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." /> + <BitField start="3" size="1" name="EP_DMA_ST3" description="Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." /> + <BitField start="4" size="1" name="EP_DMA_ST4" description="Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." /> + <BitField start="5" size="1" name="EP_DMA_ST5" description="Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." /> + <BitField start="6" size="1" name="EP_DMA_ST6" description="Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." /> + <BitField start="7" size="1" name="EP_DMA_ST7" description="Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." /> + <BitField start="8" size="1" name="EP_DMA_ST8" description="Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." /> + <BitField start="9" size="1" name="EP_DMA_ST9" description="Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." /> + <BitField start="10" size="1" name="EP_DMA_ST10" description="Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." /> + <BitField start="11" size="1" name="EP_DMA_ST11" description="Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." /> + <BitField start="12" size="1" name="EP_DMA_ST12" description="Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." /> + <BitField start="13" size="1" name="EP_DMA_ST13" description="Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." /> + <BitField start="14" size="1" name="EP_DMA_ST14" description="Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." /> + <BitField start="15" size="1" name="EP_DMA_ST15" description="Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." /> + <BitField start="16" size="1" name="EP_DMA_ST16" description="Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." /> + <BitField start="17" size="1" name="EP_DMA_ST17" description="Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." /> + <BitField start="18" size="1" name="EP_DMA_ST18" description="Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." /> + <BitField start="19" size="1" name="EP_DMA_ST19" description="Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." /> + <BitField start="20" size="1" name="EP_DMA_ST20" description="Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." /> + <BitField start="21" size="1" name="EP_DMA_ST21" description="Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." /> + <BitField start="22" size="1" name="EP_DMA_ST22" description="Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." /> + <BitField start="23" size="1" name="EP_DMA_ST23" description="Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." /> + <BitField start="24" size="1" name="EP_DMA_ST24" description="Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." /> + <BitField start="25" size="1" name="EP_DMA_ST25" description="Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." /> + <BitField start="26" size="1" name="EP_DMA_ST26" description="Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." /> + <BitField start="27" size="1" name="EP_DMA_ST27" description="Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." /> + <BitField start="28" size="1" name="EP_DMA_ST28" description="Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." /> + <BitField start="29" size="1" name="EP_DMA_ST29" description="Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." /> + <BitField start="30" size="1" name="EP_DMA_ST30" description="Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." /> + <BitField start="31" size="1" name="EP_DMA_ST31" description="Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." /> + </Register> + <Register start="+0x288" size="4" name="EPDMAEN" access="WriteOnly" description="USB Endpoint DMA Enable" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="EP_DMA_EN0" description="Control endpoint OUT (DMA cannot be enabled for this endpoint and the EP0_DMA_ENABLE bit value must be 0)." /> + <BitField start="1" size="1" name="EP_DMA_EN1" description="Control endpoint IN (DMA cannot be enabled for this endpoint and the EP1_DMA_ENABLE bit must be 0)." /> + <BitField start="2" size="30" name="EP_DMA_EN" description="Endpoint xx(2 <= xx <= 31) DMA enable control bit. 0 = No effect. 1 = Enable the DMA operation for endpoint EPxx." /> + </Register> + <Register start="+0x28C" size="4" name="EPDMADIS" access="WriteOnly" description="USB Endpoint DMA Disable" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="EP_DMA_DIS0" description="Control endpoint OUT (DMA cannot be enabled for this endpoint and the EP0_DMA_DISABLE bit value must be 0)." /> + <BitField start="1" size="1" name="EP_DMA_DIS1" description="Control endpoint IN (DMA cannot be enabled for this endpoint and the EP1_DMA_DISABLE bit value must be 0)." /> + <BitField start="2" size="1" name="EP_DMA_DIS2" description="Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." /> + <BitField start="3" size="1" name="EP_DMA_DIS3" description="Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." /> + <BitField start="4" size="1" name="EP_DMA_DIS4" description="Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." /> + <BitField start="5" size="1" name="EP_DMA_DIS5" description="Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." /> + <BitField start="6" size="1" name="EP_DMA_DIS6" description="Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." /> + <BitField start="7" size="1" name="EP_DMA_DIS7" description="Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." /> + <BitField start="8" size="1" name="EP_DMA_DIS8" description="Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." /> + <BitField start="9" size="1" name="EP_DMA_DIS9" description="Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." /> + <BitField start="10" size="1" name="EP_DMA_DIS10" description="Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." /> + <BitField start="11" size="1" name="EP_DMA_DIS11" description="Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." /> + <BitField start="12" size="1" name="EP_DMA_DIS12" description="Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." /> + <BitField start="13" size="1" name="EP_DMA_DIS13" description="Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." /> + <BitField start="14" size="1" name="EP_DMA_DIS14" description="Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." /> + <BitField start="15" size="1" name="EP_DMA_DIS15" description="Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." /> + <BitField start="16" size="1" name="EP_DMA_DIS16" description="Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." /> + <BitField start="17" size="1" name="EP_DMA_DIS17" description="Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." /> + <BitField start="18" size="1" name="EP_DMA_DIS18" description="Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." /> + <BitField start="19" size="1" name="EP_DMA_DIS19" description="Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." /> + <BitField start="20" size="1" name="EP_DMA_DIS20" description="Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." /> + <BitField start="21" size="1" name="EP_DMA_DIS21" description="Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." /> + <BitField start="22" size="1" name="EP_DMA_DIS22" description="Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." /> + <BitField start="23" size="1" name="EP_DMA_DIS23" description="Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." /> + <BitField start="24" size="1" name="EP_DMA_DIS24" description="Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." /> + <BitField start="25" size="1" name="EP_DMA_DIS25" description="Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." /> + <BitField start="26" size="1" name="EP_DMA_DIS26" description="Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." /> + <BitField start="27" size="1" name="EP_DMA_DIS27" description="Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." /> + <BitField start="28" size="1" name="EP_DMA_DIS28" description="Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." /> + <BitField start="29" size="1" name="EP_DMA_DIS29" description="Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." /> + <BitField start="30" size="1" name="EP_DMA_DIS30" description="Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." /> + <BitField start="31" size="1" name="EP_DMA_DIS31" description="Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." /> + </Register> + <Register start="+0x290" size="4" name="DMAINTST" access="ReadOnly" description="USB DMA Interrupt Status" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="EOT" description="End of Transfer Interrupt bit."> + <Enum name="ALL_BITS_IN_THE_USBE" start="0" description="All bits in the USBEoTIntSt register are 0." /> + <Enum name="AT_LEAST_ONE_BIT_IN_" start="1" description="At least one bit in the USBEoTIntSt is set." /> + </BitField> + <BitField start="1" size="1" name="NDDR" description="New DD Request Interrupt bit."> + <Enum name="ALL_BITS_IN_THE_USBN" start="0" description="All bits in the USBNDDRIntSt register are 0." /> + <Enum name="AT_LEAST_ONE_BIT_IN_" start="1" description="At least one bit in the USBNDDRIntSt is set." /> + </BitField> + <BitField start="2" size="1" name="ERR" description="System Error Interrupt bit."> + <Enum name="ALL_BITS_IN_THE_USBS" start="0" description="All bits in the USBSysErrIntSt register are 0." /> + <Enum name="AT_LEAST_ONE_BIT_IN_" start="1" description="At least one bit in the USBSysErrIntSt is set." /> + </BitField> + <BitField start="3" size="29" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0x294" size="4" name="DMAINTEN" access="Read/Write" description="USB DMA Interrupt Enable" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="EOT" description="End of Transfer Interrupt enable bit."> + <Enum name="DISABLED_" start="0" description="Disabled." /> + <Enum name="ENABLED_" start="1" description="Enabled." /> + </BitField> + <BitField start="1" size="1" name="NDDR" description="New DD Request Interrupt enable bit."> + <Enum name="DISABLED_" start="0" description="Disabled." /> + <Enum name="ENABLED_" start="1" description="Enabled." /> + </BitField> + <BitField start="2" size="1" name="ERR" description="System Error Interrupt enable bit."> + <Enum name="DISABLED_" start="0" description="Disabled." /> + <Enum name="ENABLED_" start="1" description="Enabled." /> + </BitField> + <BitField start="3" size="29" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x2A0" size="4" name="EOTINTST" access="ReadOnly" description="USB End of Transfer Interrupt Status" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="EPTXINTST0" description="Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." /> + <BitField start="1" size="1" name="EPTXINTST1" description="Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." /> + <BitField start="2" size="1" name="EPTXINTST2" description="Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." /> + <BitField start="3" size="1" name="EPTXINTST3" description="Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." /> + <BitField start="4" size="1" name="EPTXINTST4" description="Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." /> + <BitField start="5" size="1" name="EPTXINTST5" description="Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." /> + <BitField start="6" size="1" name="EPTXINTST6" description="Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." /> + <BitField start="7" size="1" name="EPTXINTST7" description="Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." /> + <BitField start="8" size="1" name="EPTXINTST8" description="Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." /> + <BitField start="9" size="1" name="EPTXINTST9" description="Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." /> + <BitField start="10" size="1" name="EPTXINTST10" description="Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." /> + <BitField start="11" size="1" name="EPTXINTST11" description="Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." /> + <BitField start="12" size="1" name="EPTXINTST12" description="Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." /> + <BitField start="13" size="1" name="EPTXINTST13" description="Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." /> + <BitField start="14" size="1" name="EPTXINTST14" description="Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." /> + <BitField start="15" size="1" name="EPTXINTST15" description="Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." /> + <BitField start="16" size="1" name="EPTXINTST16" description="Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." /> + <BitField start="17" size="1" name="EPTXINTST17" description="Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." /> + <BitField start="18" size="1" name="EPTXINTST18" description="Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." /> + <BitField start="19" size="1" name="EPTXINTST19" description="Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." /> + <BitField start="20" size="1" name="EPTXINTST20" description="Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." /> + <BitField start="21" size="1" name="EPTXINTST21" description="Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." /> + <BitField start="22" size="1" name="EPTXINTST22" description="Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." /> + <BitField start="23" size="1" name="EPTXINTST23" description="Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." /> + <BitField start="24" size="1" name="EPTXINTST24" description="Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." /> + <BitField start="25" size="1" name="EPTXINTST25" description="Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." /> + <BitField start="26" size="1" name="EPTXINTST26" description="Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." /> + <BitField start="27" size="1" name="EPTXINTST27" description="Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." /> + <BitField start="28" size="1" name="EPTXINTST28" description="Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." /> + <BitField start="29" size="1" name="EPTXINTST29" description="Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." /> + <BitField start="30" size="1" name="EPTXINTST30" description="Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." /> + <BitField start="31" size="1" name="EPTXINTST31" description="Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." /> + </Register> + <Register start="+0x2A4" size="4" name="EOTINTCLR" access="WriteOnly" description="USB End of Transfer Interrupt Clear" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="EPTXINTCLR0" description="Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." /> + <BitField start="1" size="1" name="EPTXINTCLR1" description="Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." /> + <BitField start="2" size="1" name="EPTXINTCLR2" description="Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." /> + <BitField start="3" size="1" name="EPTXINTCLR3" description="Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." /> + <BitField start="4" size="1" name="EPTXINTCLR4" description="Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." /> + <BitField start="5" size="1" name="EPTXINTCLR5" description="Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." /> + <BitField start="6" size="1" name="EPTXINTCLR6" description="Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." /> + <BitField start="7" size="1" name="EPTXINTCLR7" description="Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." /> + <BitField start="8" size="1" name="EPTXINTCLR8" description="Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." /> + <BitField start="9" size="1" name="EPTXINTCLR9" description="Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." /> + <BitField start="10" size="1" name="EPTXINTCLR10" description="Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." /> + <BitField start="11" size="1" name="EPTXINTCLR11" description="Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." /> + <BitField start="12" size="1" name="EPTXINTCLR12" description="Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." /> + <BitField start="13" size="1" name="EPTXINTCLR13" description="Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." /> + <BitField start="14" size="1" name="EPTXINTCLR14" description="Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." /> + <BitField start="15" size="1" name="EPTXINTCLR15" description="Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." /> + <BitField start="16" size="1" name="EPTXINTCLR16" description="Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." /> + <BitField start="17" size="1" name="EPTXINTCLR17" description="Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." /> + <BitField start="18" size="1" name="EPTXINTCLR18" description="Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." /> + <BitField start="19" size="1" name="EPTXINTCLR19" description="Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." /> + <BitField start="20" size="1" name="EPTXINTCLR20" description="Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." /> + <BitField start="21" size="1" name="EPTXINTCLR21" description="Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." /> + <BitField start="22" size="1" name="EPTXINTCLR22" description="Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." /> + <BitField start="23" size="1" name="EPTXINTCLR23" description="Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." /> + <BitField start="24" size="1" name="EPTXINTCLR24" description="Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." /> + <BitField start="25" size="1" name="EPTXINTCLR25" description="Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." /> + <BitField start="26" size="1" name="EPTXINTCLR26" description="Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." /> + <BitField start="27" size="1" name="EPTXINTCLR27" description="Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." /> + <BitField start="28" size="1" name="EPTXINTCLR28" description="Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." /> + <BitField start="29" size="1" name="EPTXINTCLR29" description="Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." /> + <BitField start="30" size="1" name="EPTXINTCLR30" description="Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." /> + <BitField start="31" size="1" name="EPTXINTCLR31" description="Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." /> + </Register> + <Register start="+0x2A8" size="4" name="EOTINTSET" access="WriteOnly" description="USB End of Transfer Interrupt Set" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="EPTXINTSET0" description="Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." /> + <BitField start="1" size="1" name="EPTXINTSET1" description="Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." /> + <BitField start="2" size="1" name="EPTXINTSET2" description="Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." /> + <BitField start="3" size="1" name="EPTXINTSET3" description="Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." /> + <BitField start="4" size="1" name="EPTXINTSET4" description="Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." /> + <BitField start="5" size="1" name="EPTXINTSET5" description="Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." /> + <BitField start="6" size="1" name="EPTXINTSET6" description="Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." /> + <BitField start="7" size="1" name="EPTXINTSET7" description="Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." /> + <BitField start="8" size="1" name="EPTXINTSET8" description="Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." /> + <BitField start="9" size="1" name="EPTXINTSET9" description="Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." /> + <BitField start="10" size="1" name="EPTXINTSET10" description="Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." /> + <BitField start="11" size="1" name="EPTXINTSET11" description="Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." /> + <BitField start="12" size="1" name="EPTXINTSET12" description="Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." /> + <BitField start="13" size="1" name="EPTXINTSET13" description="Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." /> + <BitField start="14" size="1" name="EPTXINTSET14" description="Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." /> + <BitField start="15" size="1" name="EPTXINTSET15" description="Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." /> + <BitField start="16" size="1" name="EPTXINTSET16" description="Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." /> + <BitField start="17" size="1" name="EPTXINTSET17" description="Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." /> + <BitField start="18" size="1" name="EPTXINTSET18" description="Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." /> + <BitField start="19" size="1" name="EPTXINTSET19" description="Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." /> + <BitField start="20" size="1" name="EPTXINTSET20" description="Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." /> + <BitField start="21" size="1" name="EPTXINTSET21" description="Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." /> + <BitField start="22" size="1" name="EPTXINTSET22" description="Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." /> + <BitField start="23" size="1" name="EPTXINTSET23" description="Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." /> + <BitField start="24" size="1" name="EPTXINTSET24" description="Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." /> + <BitField start="25" size="1" name="EPTXINTSET25" description="Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." /> + <BitField start="26" size="1" name="EPTXINTSET26" description="Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." /> + <BitField start="27" size="1" name="EPTXINTSET27" description="Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." /> + <BitField start="28" size="1" name="EPTXINTSET28" description="Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." /> + <BitField start="29" size="1" name="EPTXINTSET29" description="Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." /> + <BitField start="30" size="1" name="EPTXINTSET30" description="Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." /> + <BitField start="31" size="1" name="EPTXINTSET31" description="Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." /> + </Register> + <Register start="+0x2AC" size="4" name="NDDRINTST" access="ReadOnly" description="USB New DD Request Interrupt Status" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="EPNDDINTST0" description="Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." /> + <BitField start="1" size="1" name="EPNDDINTST1" description="Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." /> + <BitField start="2" size="1" name="EPNDDINTST2" description="Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." /> + <BitField start="3" size="1" name="EPNDDINTST3" description="Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." /> + <BitField start="4" size="1" name="EPNDDINTST4" description="Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." /> + <BitField start="5" size="1" name="EPNDDINTST5" description="Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." /> + <BitField start="6" size="1" name="EPNDDINTST6" description="Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." /> + <BitField start="7" size="1" name="EPNDDINTST7" description="Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." /> + <BitField start="8" size="1" name="EPNDDINTST8" description="Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." /> + <BitField start="9" size="1" name="EPNDDINTST9" description="Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." /> + <BitField start="10" size="1" name="EPNDDINTST10" description="Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." /> + <BitField start="11" size="1" name="EPNDDINTST11" description="Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." /> + <BitField start="12" size="1" name="EPNDDINTST12" description="Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." /> + <BitField start="13" size="1" name="EPNDDINTST13" description="Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." /> + <BitField start="14" size="1" name="EPNDDINTST14" description="Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." /> + <BitField start="15" size="1" name="EPNDDINTST15" description="Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." /> + <BitField start="16" size="1" name="EPNDDINTST16" description="Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." /> + <BitField start="17" size="1" name="EPNDDINTST17" description="Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." /> + <BitField start="18" size="1" name="EPNDDINTST18" description="Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." /> + <BitField start="19" size="1" name="EPNDDINTST19" description="Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." /> + <BitField start="20" size="1" name="EPNDDINTST20" description="Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." /> + <BitField start="21" size="1" name="EPNDDINTST21" description="Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." /> + <BitField start="22" size="1" name="EPNDDINTST22" description="Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." /> + <BitField start="23" size="1" name="EPNDDINTST23" description="Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." /> + <BitField start="24" size="1" name="EPNDDINTST24" description="Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." /> + <BitField start="25" size="1" name="EPNDDINTST25" description="Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." /> + <BitField start="26" size="1" name="EPNDDINTST26" description="Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." /> + <BitField start="27" size="1" name="EPNDDINTST27" description="Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." /> + <BitField start="28" size="1" name="EPNDDINTST28" description="Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." /> + <BitField start="29" size="1" name="EPNDDINTST29" description="Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." /> + <BitField start="30" size="1" name="EPNDDINTST30" description="Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." /> + <BitField start="31" size="1" name="EPNDDINTST31" description="Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." /> + </Register> + <Register start="+0x2B0" size="4" name="NDDRINTCLR" access="WriteOnly" description="USB New DD Request Interrupt Clear" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="EPNDDINTCLR0" description="Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." /> + <BitField start="1" size="1" name="EPNDDINTCLR1" description="Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." /> + <BitField start="2" size="1" name="EPNDDINTCLR2" description="Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." /> + <BitField start="3" size="1" name="EPNDDINTCLR3" description="Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." /> + <BitField start="4" size="1" name="EPNDDINTCLR4" description="Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." /> + <BitField start="5" size="1" name="EPNDDINTCLR5" description="Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." /> + <BitField start="6" size="1" name="EPNDDINTCLR6" description="Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." /> + <BitField start="7" size="1" name="EPNDDINTCLR7" description="Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." /> + <BitField start="8" size="1" name="EPNDDINTCLR8" description="Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." /> + <BitField start="9" size="1" name="EPNDDINTCLR9" description="Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." /> + <BitField start="10" size="1" name="EPNDDINTCLR10" description="Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." /> + <BitField start="11" size="1" name="EPNDDINTCLR11" description="Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." /> + <BitField start="12" size="1" name="EPNDDINTCLR12" description="Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." /> + <BitField start="13" size="1" name="EPNDDINTCLR13" description="Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." /> + <BitField start="14" size="1" name="EPNDDINTCLR14" description="Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." /> + <BitField start="15" size="1" name="EPNDDINTCLR15" description="Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." /> + <BitField start="16" size="1" name="EPNDDINTCLR16" description="Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." /> + <BitField start="17" size="1" name="EPNDDINTCLR17" description="Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." /> + <BitField start="18" size="1" name="EPNDDINTCLR18" description="Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." /> + <BitField start="19" size="1" name="EPNDDINTCLR19" description="Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." /> + <BitField start="20" size="1" name="EPNDDINTCLR20" description="Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." /> + <BitField start="21" size="1" name="EPNDDINTCLR21" description="Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." /> + <BitField start="22" size="1" name="EPNDDINTCLR22" description="Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." /> + <BitField start="23" size="1" name="EPNDDINTCLR23" description="Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." /> + <BitField start="24" size="1" name="EPNDDINTCLR24" description="Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." /> + <BitField start="25" size="1" name="EPNDDINTCLR25" description="Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." /> + <BitField start="26" size="1" name="EPNDDINTCLR26" description="Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." /> + <BitField start="27" size="1" name="EPNDDINTCLR27" description="Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." /> + <BitField start="28" size="1" name="EPNDDINTCLR28" description="Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." /> + <BitField start="29" size="1" name="EPNDDINTCLR29" description="Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." /> + <BitField start="30" size="1" name="EPNDDINTCLR30" description="Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." /> + <BitField start="31" size="1" name="EPNDDINTCLR31" description="Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." /> + </Register> + <Register start="+0x2B4" size="4" name="NDDRINTSET" access="WriteOnly" description="USB New DD Request Interrupt Set" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="EPNDDINTSET0" description="Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." /> + <BitField start="1" size="1" name="EPNDDINTSET1" description="Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." /> + <BitField start="2" size="1" name="EPNDDINTSET2" description="Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." /> + <BitField start="3" size="1" name="EPNDDINTSET3" description="Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." /> + <BitField start="4" size="1" name="EPNDDINTSET4" description="Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." /> + <BitField start="5" size="1" name="EPNDDINTSET5" description="Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." /> + <BitField start="6" size="1" name="EPNDDINTSET6" description="Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." /> + <BitField start="7" size="1" name="EPNDDINTSET7" description="Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." /> + <BitField start="8" size="1" name="EPNDDINTSET8" description="Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." /> + <BitField start="9" size="1" name="EPNDDINTSET9" description="Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." /> + <BitField start="10" size="1" name="EPNDDINTSET10" description="Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." /> + <BitField start="11" size="1" name="EPNDDINTSET11" description="Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." /> + <BitField start="12" size="1" name="EPNDDINTSET12" description="Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." /> + <BitField start="13" size="1" name="EPNDDINTSET13" description="Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." /> + <BitField start="14" size="1" name="EPNDDINTSET14" description="Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." /> + <BitField start="15" size="1" name="EPNDDINTSET15" description="Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." /> + <BitField start="16" size="1" name="EPNDDINTSET16" description="Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." /> + <BitField start="17" size="1" name="EPNDDINTSET17" description="Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." /> + <BitField start="18" size="1" name="EPNDDINTSET18" description="Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." /> + <BitField start="19" size="1" name="EPNDDINTSET19" description="Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." /> + <BitField start="20" size="1" name="EPNDDINTSET20" description="Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." /> + <BitField start="21" size="1" name="EPNDDINTSET21" description="Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." /> + <BitField start="22" size="1" name="EPNDDINTSET22" description="Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." /> + <BitField start="23" size="1" name="EPNDDINTSET23" description="Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." /> + <BitField start="24" size="1" name="EPNDDINTSET24" description="Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." /> + <BitField start="25" size="1" name="EPNDDINTSET25" description="Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." /> + <BitField start="26" size="1" name="EPNDDINTSET26" description="Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." /> + <BitField start="27" size="1" name="EPNDDINTSET27" description="Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." /> + <BitField start="28" size="1" name="EPNDDINTSET28" description="Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." /> + <BitField start="29" size="1" name="EPNDDINTSET29" description="Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." /> + <BitField start="30" size="1" name="EPNDDINTSET30" description="Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." /> + <BitField start="31" size="1" name="EPNDDINTSET31" description="Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." /> + </Register> + <Register start="+0x2B8" size="4" name="SYSERRINTST" access="ReadOnly" description="USB System Error Interrupt Status" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="EPERRINTST0" description="Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." /> + <BitField start="1" size="1" name="EPERRINTST1" description="Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." /> + <BitField start="2" size="1" name="EPERRINTST2" description="Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." /> + <BitField start="3" size="1" name="EPERRINTST3" description="Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." /> + <BitField start="4" size="1" name="EPERRINTST4" description="Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." /> + <BitField start="5" size="1" name="EPERRINTST5" description="Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." /> + <BitField start="6" size="1" name="EPERRINTST6" description="Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." /> + <BitField start="7" size="1" name="EPERRINTST7" description="Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." /> + <BitField start="8" size="1" name="EPERRINTST8" description="Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." /> + <BitField start="9" size="1" name="EPERRINTST9" description="Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." /> + <BitField start="10" size="1" name="EPERRINTST10" description="Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." /> + <BitField start="11" size="1" name="EPERRINTST11" description="Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." /> + <BitField start="12" size="1" name="EPERRINTST12" description="Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." /> + <BitField start="13" size="1" name="EPERRINTST13" description="Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." /> + <BitField start="14" size="1" name="EPERRINTST14" description="Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." /> + <BitField start="15" size="1" name="EPERRINTST15" description="Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." /> + <BitField start="16" size="1" name="EPERRINTST16" description="Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." /> + <BitField start="17" size="1" name="EPERRINTST17" description="Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." /> + <BitField start="18" size="1" name="EPERRINTST18" description="Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." /> + <BitField start="19" size="1" name="EPERRINTST19" description="Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." /> + <BitField start="20" size="1" name="EPERRINTST20" description="Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." /> + <BitField start="21" size="1" name="EPERRINTST21" description="Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." /> + <BitField start="22" size="1" name="EPERRINTST22" description="Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." /> + <BitField start="23" size="1" name="EPERRINTST23" description="Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." /> + <BitField start="24" size="1" name="EPERRINTST24" description="Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." /> + <BitField start="25" size="1" name="EPERRINTST25" description="Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." /> + <BitField start="26" size="1" name="EPERRINTST26" description="Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." /> + <BitField start="27" size="1" name="EPERRINTST27" description="Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." /> + <BitField start="28" size="1" name="EPERRINTST28" description="Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." /> + <BitField start="29" size="1" name="EPERRINTST29" description="Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." /> + <BitField start="30" size="1" name="EPERRINTST30" description="Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." /> + <BitField start="31" size="1" name="EPERRINTST31" description="Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." /> + </Register> + <Register start="+0x2BC" size="4" name="SYSERRINTCLR" access="WriteOnly" description="USB System Error Interrupt Clear" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="EPERRINTCLR0" description="Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." /> + <BitField start="1" size="1" name="EPERRINTCLR1" description="Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." /> + <BitField start="2" size="1" name="EPERRINTCLR2" description="Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." /> + <BitField start="3" size="1" name="EPERRINTCLR3" description="Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." /> + <BitField start="4" size="1" name="EPERRINTCLR4" description="Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." /> + <BitField start="5" size="1" name="EPERRINTCLR5" description="Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." /> + <BitField start="6" size="1" name="EPERRINTCLR6" description="Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." /> + <BitField start="7" size="1" name="EPERRINTCLR7" description="Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." /> + <BitField start="8" size="1" name="EPERRINTCLR8" description="Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." /> + <BitField start="9" size="1" name="EPERRINTCLR9" description="Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." /> + <BitField start="10" size="1" name="EPERRINTCLR10" description="Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." /> + <BitField start="11" size="1" name="EPERRINTCLR11" description="Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." /> + <BitField start="12" size="1" name="EPERRINTCLR12" description="Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." /> + <BitField start="13" size="1" name="EPERRINTCLR13" description="Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." /> + <BitField start="14" size="1" name="EPERRINTCLR14" description="Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." /> + <BitField start="15" size="1" name="EPERRINTCLR15" description="Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." /> + <BitField start="16" size="1" name="EPERRINTCLR16" description="Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." /> + <BitField start="17" size="1" name="EPERRINTCLR17" description="Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." /> + <BitField start="18" size="1" name="EPERRINTCLR18" description="Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." /> + <BitField start="19" size="1" name="EPERRINTCLR19" description="Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." /> + <BitField start="20" size="1" name="EPERRINTCLR20" description="Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." /> + <BitField start="21" size="1" name="EPERRINTCLR21" description="Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." /> + <BitField start="22" size="1" name="EPERRINTCLR22" description="Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." /> + <BitField start="23" size="1" name="EPERRINTCLR23" description="Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." /> + <BitField start="24" size="1" name="EPERRINTCLR24" description="Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." /> + <BitField start="25" size="1" name="EPERRINTCLR25" description="Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." /> + <BitField start="26" size="1" name="EPERRINTCLR26" description="Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." /> + <BitField start="27" size="1" name="EPERRINTCLR27" description="Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." /> + <BitField start="28" size="1" name="EPERRINTCLR28" description="Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." /> + <BitField start="29" size="1" name="EPERRINTCLR29" description="Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." /> + <BitField start="30" size="1" name="EPERRINTCLR30" description="Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." /> + <BitField start="31" size="1" name="EPERRINTCLR31" description="Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." /> + </Register> + <Register start="+0x2C0" size="4" name="SYSERRINTSET" access="WriteOnly" description="USB System Error Interrupt Set" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="EPERRINTSET0" description="Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." /> + <BitField start="1" size="1" name="EPERRINTSET1" description="Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." /> + <BitField start="2" size="1" name="EPERRINTSET2" description="Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." /> + <BitField start="3" size="1" name="EPERRINTSET3" description="Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." /> + <BitField start="4" size="1" name="EPERRINTSET4" description="Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." /> + <BitField start="5" size="1" name="EPERRINTSET5" description="Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." /> + <BitField start="6" size="1" name="EPERRINTSET6" description="Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." /> + <BitField start="7" size="1" name="EPERRINTSET7" description="Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." /> + <BitField start="8" size="1" name="EPERRINTSET8" description="Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." /> + <BitField start="9" size="1" name="EPERRINTSET9" description="Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." /> + <BitField start="10" size="1" name="EPERRINTSET10" description="Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." /> + <BitField start="11" size="1" name="EPERRINTSET11" description="Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." /> + <BitField start="12" size="1" name="EPERRINTSET12" description="Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." /> + <BitField start="13" size="1" name="EPERRINTSET13" description="Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." /> + <BitField start="14" size="1" name="EPERRINTSET14" description="Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." /> + <BitField start="15" size="1" name="EPERRINTSET15" description="Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." /> + <BitField start="16" size="1" name="EPERRINTSET16" description="Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." /> + <BitField start="17" size="1" name="EPERRINTSET17" description="Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." /> + <BitField start="18" size="1" name="EPERRINTSET18" description="Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." /> + <BitField start="19" size="1" name="EPERRINTSET19" description="Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." /> + <BitField start="20" size="1" name="EPERRINTSET20" description="Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." /> + <BitField start="21" size="1" name="EPERRINTSET21" description="Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." /> + <BitField start="22" size="1" name="EPERRINTSET22" description="Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." /> + <BitField start="23" size="1" name="EPERRINTSET23" description="Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." /> + <BitField start="24" size="1" name="EPERRINTSET24" description="Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." /> + <BitField start="25" size="1" name="EPERRINTSET25" description="Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." /> + <BitField start="26" size="1" name="EPERRINTSET26" description="Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." /> + <BitField start="27" size="1" name="EPERRINTSET27" description="Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." /> + <BitField start="28" size="1" name="EPERRINTSET28" description="Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." /> + <BitField start="29" size="1" name="EPERRINTSET29" description="Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." /> + <BitField start="30" size="1" name="EPERRINTSET30" description="Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." /> + <BitField start="31" size="1" name="EPERRINTSET31" description="Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." /> + </Register> + <Register start="+0x300" size="4" name="I2C_RX" access="ReadOnly" description="I2C Receive" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="8" name="RXDATA" description="Receive data." /> + </Register> + <Register start="+0x300" size="4" name="I2C_WO" access="WriteOnly" description="I2C Transmit" reset_value="0" reset_mask="0x00000000"> + <BitField start="0" size="8" name="TXDATA" description="Transmit data." /> + <BitField start="8" size="1" name="START" description="When 1, issue a START condition before transmitting this byte." /> + <BitField start="9" size="1" name="STOP" description="When 1, issue a STOP condition after transmitting this byte." /> + <BitField start="10" size="22" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x304" size="4" name="I2C_STS" access="ReadOnly" description="I2C Status" reset_value="0x0A00" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="TDI" description="Transaction Done Interrupt. This flag is set if a transaction completes successfully. It is cleared by writing a one to bit 0 of the status register. It is unaffected by slave transactions."> + <Enum name="NOT_COMPLETE" start="0" description="Transaction has not completed." /> + <Enum name="COMPLETE" start="1" description="Transaction completed." /> + </BitField> + <BitField start="1" size="1" name="AFI" description="Arbitration Failure Interrupt. When transmitting, if the SDA is low when SDAOUT is high, then this I2C has lost the arbitration to another device on the bus. The Arbitration Failure bit is set when this happens. It is cleared by writing a one to bit 1 of the status register."> + <Enum name="NO_ARBITRATION_FAILU" start="0" description="No arbitration failure on last transmission." /> + <Enum name="ARBITRATION_FAILURE_" start="1" description="Arbitration failure occurred on last transmission." /> + </BitField> + <BitField start="2" size="1" name="NAI" description="No Acknowledge Interrupt. After every byte of data is sent, the transmitter expects an acknowledge from the receiver. This bit is set if the acknowledge is not received. It is cleared when a byte is written to the master TX FIFO."> + <Enum name="ACKNOWLEDGE_RCVD" start="0" description="Last transmission received an acknowledge." /> + <Enum name="NO_ACKNOWLEDGE_RCVD" start="1" description="Last transmission did not receive an acknowledge." /> + </BitField> + <BitField start="3" size="1" name="DRMI" description="Master Data Request Interrupt. Once a transmission is started, the transmitter must have data to transmit as long as it isn't followed by a stop condition or it will hold SCL low until more data is available. The Master Data Request bit is set when the master transmitter is data-starved. If the master TX FIFO is empty and the last byte did not have a STOP condition flag, then SCL is held low until the CPU writes another byte to transmit. This bit is cleared when a byte is written to the master TX FIFO."> + <Enum name="BUSY" start="0" description="Master transmitter does not need data." /> + <Enum name="NEED_DATA" start="1" description="Master transmitter needs data." /> + </BitField> + <BitField start="4" size="1" name="DRSI" description="Slave Data Request Interrupt. Once a transmission is started, the transmitter must have data to transmit as long as it isn't followed by a STOP condition or it will hold SCL low until more data is available. The Slave Data Request bit is set when the slave transmitter is data-starved. If the slave TX FIFO is empty and the last byte transmitted was acknowledged, then SCL is held low until the CPU writes another byte to transmit. This bit is cleared when a byte is written to the slave Tx FIFO."> + <Enum name="BUSY" start="0" description="Slave transmitter does not need data." /> + <Enum name="NEED_DATA" start="1" description="Slave transmitter needs data." /> + </BitField> + <BitField start="5" size="1" name="Active" description="Indicates whether the bus is busy. This bit is set when a START condition has been seen. It is cleared when a STOP condition is seen.." /> + <BitField start="6" size="1" name="SCL" description="The current value of the SCL signal." /> + <BitField start="7" size="1" name="SDA" description="The current value of the SDA signal." /> + <BitField start="8" size="1" name="RFF" description="Receive FIFO Full (RFF). This bit is set when the RX FIFO is full and cannot accept any more data. It is cleared when the RX FIFO is not full. If a byte arrives when the Receive FIFO is full, the SCL is held low until the CPU reads the RX FIFO and makes room for it."> + <Enum name="RX_FIFO_IS_NOT_FULL" start="0" description="RX FIFO is not full" /> + <Enum name="RX_FIFO_IS_FULL" start="1" description="RX FIFO is full" /> + </BitField> + <BitField start="9" size="1" name="RFE" description="Receive FIFO Empty. RFE is set when the RX FIFO is empty and is cleared when the RX FIFO contains valid data."> + <Enum name="DATA" start="0" description="RX FIFO contains data." /> + <Enum name="EMPTY" start="1" description="RX FIFO is empty" /> + </BitField> + <BitField start="10" size="1" name="TFF" description="Transmit FIFO Full. TFF is set when the TX FIFO is full and is cleared when the TX FIFO is not full."> + <Enum name="TX_FIFO_IS_NOT_FULL_" start="0" description="TX FIFO is not full." /> + <Enum name="TX_FIFO_IS_FULL" start="1" description="TX FIFO is full" /> + </BitField> + <BitField start="11" size="1" name="TFE" description="Transmit FIFO Empty. TFE is set when the TX FIFO is empty and is cleared when the TX FIFO contains valid data."> + <Enum name="VALID_DATA" start="0" description="TX FIFO contains valid data." /> + <Enum name="EMPTY" start="1" description="TX FIFO is empty" /> + </BitField> + <BitField start="12" size="20" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x308" size="4" name="I2C_CTL" access="Read/Write" description="I2C Control" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="TDIE" description="Transmit Done Interrupt Enable. This enables the TDI interrupt signalling that this I2C issued a STOP condition."> + <Enum name="DISABLE_THE_TDI_INTE" start="0" description="Disable the TDI interrupt." /> + <Enum name="ENABLE_THE_TDI_INTER" start="1" description="Enable the TDI interrupt." /> + </BitField> + <BitField start="1" size="1" name="AFIE" description="Transmitter Arbitration Failure Interrupt Enable. This enables the AFI interrupt which is asserted during transmission when trying to set SDA high, but the bus is driven low by another device."> + <Enum name="DISABLE_THE_AFI_" start="0" description="Disable the AFI." /> + <Enum name="ENABLE_THE_AFI_" start="1" description="Enable the AFI." /> + </BitField> + <BitField start="2" size="1" name="NAIE" description="Transmitter No Acknowledge Interrupt Enable. This enables the NAI interrupt signalling that transmitted byte was not acknowledged."> + <Enum name="DISABLE_THE_NAI_" start="0" description="Disable the NAI." /> + <Enum name="ENABLE_THE_NAI_" start="1" description="Enable the NAI." /> + </BitField> + <BitField start="3" size="1" name="DRMIE" description="Master Transmitter Data Request Interrupt Enable. This enables the DRMI interrupt which signals that the master transmitter has run out of data, has not issued a STOP, and is holding the SCL line low."> + <Enum name="DISABLE_THE_DRMI_INT" start="0" description="Disable the DRMI interrupt." /> + <Enum name="ENABLE_THE_DRMI_INTE" start="1" description="Enable the DRMI interrupt." /> + </BitField> + <BitField start="4" size="1" name="DRSIE" description="Slave Transmitter Data Request Interrupt Enable. This enables the DRSI interrupt which signals that the slave transmitter has run out of data and the last byte was acknowledged, so the SCL line is being held low."> + <Enum name="DISABLE_THE_DRSI_INT" start="0" description="Disable the DRSI interrupt." /> + <Enum name="ENABLE_THE_DRSI_INTE" start="1" description="Enable the DRSI interrupt." /> + </BitField> + <BitField start="5" size="1" name="REFIE" description="Receive FIFO Full Interrupt Enable. This enables the Receive FIFO Full interrupt to indicate that the receive FIFO cannot accept any more data."> + <Enum name="DISABLE_THE_RFFI_" start="0" description="Disable the RFFI." /> + <Enum name="ENABLE_THE_RFFI_" start="1" description="Enable the RFFI." /> + </BitField> + <BitField start="6" size="1" name="RFDAIE" description="Receive Data Available Interrupt Enable. This enables the DAI interrupt to indicate that data is available in the receive FIFO (i.e. not empty)."> + <Enum name="DISABLE_THE_DAI_" start="0" description="Disable the DAI." /> + <Enum name="ENABLE_THE_DAI_" start="1" description="Enable the DAI." /> + </BitField> + <BitField start="7" size="1" name="TFFIE" description="Transmit FIFO Not Full Interrupt Enable. This enables the Transmit FIFO Not Full interrupt to indicate that the more data can be written to the transmit FIFO. Note that this is not full. It is intended help the CPU to write to the I2C block only when there is room in the FIFO and do this without polling the status register."> + <Enum name="DISABLE_THE_TFFI_" start="0" description="Disable the TFFI." /> + <Enum name="ENABLE_THE_TFFI_" start="1" description="Enable the TFFI." /> + </BitField> + <BitField start="8" size="1" name="SRST" description="Soft reset. This is only needed in unusual circumstances. If a device issues a start condition without issuing a stop condition. A system timer may be used to reset the I2C if the bus remains busy longer than the time-out period. On a soft reset, the Tx and Rx FIFOs are flushed, I2C_STS register is cleared, and all internal state machines are reset to appear idle. The I2C_CLKHI, I2C_CLKLO and I2C_CTL (except Soft Reset Bit) are NOT modified by a soft reset."> + <Enum name="NO_RESET" start="0" description="No reset." /> + <Enum name="RESET" start="1" description="Reset the I2C to idle state. Self clearing." /> + </BitField> + <BitField start="9" size="23" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x30C" size="4" name="I2C_CLKHI" access="Read/Write" description="I2C Clock High" reset_value="0xB9" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="CDHI" description="Clock divisor high. This value is the number of 48 MHz clocks the serial clock (SCL) will be high." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0x310" size="4" name="I2C_CLKLO" access="WriteOnly" description="I2C Clock Low" reset_value="0xB9" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="8" name="CDLO" description="Clock divisor low. This value is the number of 48 MHz clocks the serial clock (SCL) will be low." /> + <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0xFF4" size="4" name="USBCLKCTRL" access="Read/Write" description="USB Clock Control" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="1" size="1" name="DEV_CLK_EN" description="Device clock enable. Enables the usbclk input to the device controller" /> + <BitField start="2" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="3" size="1" name="PORTSEL_CLK_EN" description="Port select register clock enable." /> + <BitField start="4" size="1" name="AHB_CLK_EN" description="AHB clock enable" /> + <BitField start="5" size="27" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0xFF4" size="4" name="OTGCLKCTRL" access="Read/Write" description="OTG clock controller" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="HOST_CLK_EN" description="Host clock enable"> + <Enum name="DISABLE_THE_HOST_CLO" start="0" description="Disable the Host clock." /> + <Enum name="ENABLE_THE_HOST_CLOC" start="1" description="Enable the Host clock." /> + </BitField> + <BitField start="1" size="1" name="DEV_CLK_EN" description="Device clock enable"> + <Enum name="DISABLE_THE_DEVICE_C" start="0" description="Disable the Device clock." /> + <Enum name="ENABLE_THE_DEVICE_CL" start="1" description="Enable the Device clock." /> + </BitField> + <BitField start="2" size="1" name="I2C_CLK_EN" description="I2C clock enable"> + <Enum name="DISABLE_THE_I2C_CLOC" start="0" description="Disable the I2C clock." /> + <Enum name="ENABLE_THE_I2C_CLOCK" start="1" description="Enable the I2C clock." /> + </BitField> + <BitField start="3" size="1" name="OTG_CLK_EN" description="OTG clock enable. In device-only applications, this bit enables access to the PORTSEL register."> + <Enum name="DISABLE_THE_OTG_CLOC" start="0" description="Disable the OTG clock." /> + <Enum name="ENABLE_THE_OTG_CLOCK" start="1" description="Enable the OTG clock." /> + </BitField> + <BitField start="4" size="1" name="AHB_CLK_EN" description="AHB master clock enable"> + <Enum name="DISABLE_THE_AHB_CLOC" start="0" description="Disable the AHB clock." /> + <Enum name="ENABLE_THE_AHB_CLOCK" start="1" description="Enable the AHB clock." /> + </BitField> + <BitField start="5" size="27" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + <Register start="+0xFF8" size="4" name="USBCLKST" access="ReadOnly" description="USB Clock Status" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="1" size="1" name="DEV_CLK_ON" description="Device clock on. The usbclk input to the device controller is active	." /> + <BitField start="2" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + <BitField start="3" size="1" name="PORTSEL_CLK_ON" description="Port select register clock on." /> + <BitField start="4" size="1" name="AHB_CLK_ON" description="AHB clock on." /> + <BitField start="5" size="27" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." /> + </Register> + <Register start="+0xFF8" size="4" name="OTGCLKST" access="ReadOnly" description="OTG clock status" reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="HOST_CLK_ON" description="Host clock status."> + <Enum name="HOST_CLOCK_IS_NOT_AV" start="0" description="Host clock is not available." /> + <Enum name="HOST_CLOCK_IS_AVAILA" start="1" description="Host clock is available." /> + </BitField> + <BitField start="1" size="1" name="DEV_CLK_ON" description="Device clock status."> + <Enum name="DEVICE_CLOCK_IS_NOT_" start="0" description="Device clock is not available." /> + <Enum name="DEVICE_CLOCK_IS_AVAI" start="1" description="Device clock is available." /> + </BitField> + <BitField start="2" size="1" name="I2C_CLK_ON" description="I2C clock status."> + <Enum name="I2C_CLOCK_IS_NOT_AVA" start="0" description="I2C clock is not available." /> + <Enum name="I2C_CLOCK_IS_AVAILAB" start="1" description="I2C clock is available." /> + </BitField> + <BitField start="3" size="1" name="OTG_CLK_ON" description="OTG clock status."> + <Enum name="OTG_CLOCK_IS_NOT_AVA" start="0" description="OTG clock is not available." /> + <Enum name="OTG_CLOCK_IS_AVAILAB" start="1" description="OTG clock is available." /> + </BitField> + <BitField start="4" size="1" name="AHB_CLK_ON" description="AHB master clock status."> + <Enum name="AHB_CLOCK_IS_NOT_AVA" start="0" description="AHB clock is not available." /> + <Enum name="AHB_CLOCK_IS_AVAILAB" start="1" description="AHB clock is available." /> + </BitField> + <BitField start="5" size="27" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." /> + </Register> + </RegisterGroup> + <RegisterGroup name="GPIO" start="0x2009C000" description="General Purpose I/O "> + <Register start="+0x000+0" size="4" name="DIR0" access="Read/Write" description="GPIO Port Direction control register." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="PINDIR0" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="1" size="1" name="PINDIR1" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="2" size="1" name="PINDIR2" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="3" size="1" name="PINDIR3" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="4" size="1" name="PINDIR4" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="5" size="1" name="PINDIR5" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="6" size="1" name="PINDIR6" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="7" size="1" name="PINDIR7" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="8" size="1" name="PINDIR8" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="9" size="1" name="PINDIR9" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="10" size="1" name="PINDIR10" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="11" size="1" name="PINDIR11" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="12" size="1" name="PINDIR12" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="13" size="1" name="PINDIR13" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="14" size="1" name="PINDIR14" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="15" size="1" name="PINDIR15" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="16" size="1" name="PINDIR16" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="17" size="1" name="PINDIR17" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="18" size="1" name="PINDIR18" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="19" size="1" name="PINDIR19" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="20" size="1" name="PINDIR20" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="21" size="1" name="PINDIR21" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="22" size="1" name="PINDIR22" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="23" size="1" name="PINDIR23" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="24" size="1" name="PINDIR24" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="25" size="1" name="PINDIR25" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="26" size="1" name="PINDIR26" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="27" size="1" name="PINDIR27" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="28" size="1" name="PINDIR28" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="29" size="1" name="PINDIR29" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="30" size="1" name="PINDIR30" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="31" size="1" name="PINDIR31" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + </Register> + <Register start="+0x000+32" size="4" name="DIR1" access="Read/Write" description="GPIO Port Direction control register." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="PINDIR0" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="1" size="1" name="PINDIR1" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="2" size="1" name="PINDIR2" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="3" size="1" name="PINDIR3" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="4" size="1" name="PINDIR4" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="5" size="1" name="PINDIR5" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="6" size="1" name="PINDIR6" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="7" size="1" name="PINDIR7" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="8" size="1" name="PINDIR8" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="9" size="1" name="PINDIR9" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="10" size="1" name="PINDIR10" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="11" size="1" name="PINDIR11" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="12" size="1" name="PINDIR12" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="13" size="1" name="PINDIR13" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="14" size="1" name="PINDIR14" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="15" size="1" name="PINDIR15" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="16" size="1" name="PINDIR16" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="17" size="1" name="PINDIR17" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="18" size="1" name="PINDIR18" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="19" size="1" name="PINDIR19" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="20" size="1" name="PINDIR20" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="21" size="1" name="PINDIR21" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="22" size="1" name="PINDIR22" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="23" size="1" name="PINDIR23" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="24" size="1" name="PINDIR24" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="25" size="1" name="PINDIR25" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="26" size="1" name="PINDIR26" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="27" size="1" name="PINDIR27" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="28" size="1" name="PINDIR28" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="29" size="1" name="PINDIR29" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="30" size="1" name="PINDIR30" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="31" size="1" name="PINDIR31" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + </Register> + <Register start="+0x000+64" size="4" name="DIR2" access="Read/Write" description="GPIO Port Direction control register." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="PINDIR0" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="1" size="1" name="PINDIR1" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="2" size="1" name="PINDIR2" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="3" size="1" name="PINDIR3" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="4" size="1" name="PINDIR4" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="5" size="1" name="PINDIR5" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="6" size="1" name="PINDIR6" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="7" size="1" name="PINDIR7" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="8" size="1" name="PINDIR8" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="9" size="1" name="PINDIR9" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="10" size="1" name="PINDIR10" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="11" size="1" name="PINDIR11" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="12" size="1" name="PINDIR12" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="13" size="1" name="PINDIR13" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="14" size="1" name="PINDIR14" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="15" size="1" name="PINDIR15" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="16" size="1" name="PINDIR16" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="17" size="1" name="PINDIR17" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="18" size="1" name="PINDIR18" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="19" size="1" name="PINDIR19" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="20" size="1" name="PINDIR20" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="21" size="1" name="PINDIR21" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="22" size="1" name="PINDIR22" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="23" size="1" name="PINDIR23" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="24" size="1" name="PINDIR24" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="25" size="1" name="PINDIR25" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="26" size="1" name="PINDIR26" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="27" size="1" name="PINDIR27" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="28" size="1" name="PINDIR28" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="29" size="1" name="PINDIR29" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="30" size="1" name="PINDIR30" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="31" size="1" name="PINDIR31" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + </Register> + <Register start="+0x000+96" size="4" name="DIR3" access="Read/Write" description="GPIO Port Direction control register." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="PINDIR0" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="1" size="1" name="PINDIR1" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="2" size="1" name="PINDIR2" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="3" size="1" name="PINDIR3" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="4" size="1" name="PINDIR4" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="5" size="1" name="PINDIR5" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="6" size="1" name="PINDIR6" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="7" size="1" name="PINDIR7" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="8" size="1" name="PINDIR8" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="9" size="1" name="PINDIR9" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="10" size="1" name="PINDIR10" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="11" size="1" name="PINDIR11" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="12" size="1" name="PINDIR12" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="13" size="1" name="PINDIR13" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="14" size="1" name="PINDIR14" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="15" size="1" name="PINDIR15" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="16" size="1" name="PINDIR16" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="17" size="1" name="PINDIR17" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="18" size="1" name="PINDIR18" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="19" size="1" name="PINDIR19" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="20" size="1" name="PINDIR20" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="21" size="1" name="PINDIR21" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="22" size="1" name="PINDIR22" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="23" size="1" name="PINDIR23" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="24" size="1" name="PINDIR24" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="25" size="1" name="PINDIR25" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="26" size="1" name="PINDIR26" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="27" size="1" name="PINDIR27" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="28" size="1" name="PINDIR28" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="29" size="1" name="PINDIR29" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="30" size="1" name="PINDIR30" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="31" size="1" name="PINDIR31" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + </Register> + <Register start="+0x000+128" size="4" name="DIR4" access="Read/Write" description="GPIO Port Direction control register." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="PINDIR0" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="1" size="1" name="PINDIR1" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="2" size="1" name="PINDIR2" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="3" size="1" name="PINDIR3" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="4" size="1" name="PINDIR4" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="5" size="1" name="PINDIR5" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="6" size="1" name="PINDIR6" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="7" size="1" name="PINDIR7" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="8" size="1" name="PINDIR8" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="9" size="1" name="PINDIR9" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="10" size="1" name="PINDIR10" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="11" size="1" name="PINDIR11" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="12" size="1" name="PINDIR12" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="13" size="1" name="PINDIR13" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="14" size="1" name="PINDIR14" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="15" size="1" name="PINDIR15" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="16" size="1" name="PINDIR16" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="17" size="1" name="PINDIR17" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="18" size="1" name="PINDIR18" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="19" size="1" name="PINDIR19" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="20" size="1" name="PINDIR20" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="21" size="1" name="PINDIR21" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="22" size="1" name="PINDIR22" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="23" size="1" name="PINDIR23" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="24" size="1" name="PINDIR24" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="25" size="1" name="PINDIR25" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="26" size="1" name="PINDIR26" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="27" size="1" name="PINDIR27" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="28" size="1" name="PINDIR28" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="29" size="1" name="PINDIR29" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="30" size="1" name="PINDIR30" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + <BitField start="31" size="1" name="PINDIR31" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." /> + </Register> + <Register start="+0x010+0" size="4" name="MASK0" access="Read/Write" description="Mask register for Port." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="PINMASK0" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="1" size="1" name="PINMASK1" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="2" size="1" name="PINMASK2" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="3" size="1" name="PINMASK3" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="4" size="1" name="PINMASK4" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="5" size="1" name="PINMASK5" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="6" size="1" name="PINMASK6" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="7" size="1" name="PINMASK7" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="8" size="1" name="PINMASK8" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="9" size="1" name="PINMASK9" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="10" size="1" name="PINMASK10" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="11" size="1" name="PINMASK11" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="12" size="1" name="PINMASK12" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="13" size="1" name="PINMASK13" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="14" size="1" name="PINMASK14" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="15" size="1" name="PINMASK15" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="16" size="1" name="PINMASK16" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="17" size="1" name="PINMASK17" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="18" size="1" name="PINMASK18" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="19" size="1" name="PINMASK19" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="20" size="1" name="PINMASK20" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="21" size="1" name="PINMASK21" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="22" size="1" name="PINMASK22" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="23" size="1" name="PINMASK23" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="24" size="1" name="PINMASK24" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="25" size="1" name="PINMASK25" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="26" size="1" name="PINMASK26" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="27" size="1" name="PINMASK27" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="28" size="1" name="PINMASK28" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="29" size="1" name="PINMASK29" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="30" size="1" name="PINMASK30" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="31" size="1" name="PINMASK31" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + </Register> + <Register start="+0x010+32" size="4" name="MASK1" access="Read/Write" description="Mask register for Port." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="PINMASK0" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="1" size="1" name="PINMASK1" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="2" size="1" name="PINMASK2" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="3" size="1" name="PINMASK3" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="4" size="1" name="PINMASK4" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="5" size="1" name="PINMASK5" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="6" size="1" name="PINMASK6" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="7" size="1" name="PINMASK7" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="8" size="1" name="PINMASK8" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="9" size="1" name="PINMASK9" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="10" size="1" name="PINMASK10" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="11" size="1" name="PINMASK11" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="12" size="1" name="PINMASK12" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="13" size="1" name="PINMASK13" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="14" size="1" name="PINMASK14" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="15" size="1" name="PINMASK15" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="16" size="1" name="PINMASK16" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="17" size="1" name="PINMASK17" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="18" size="1" name="PINMASK18" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="19" size="1" name="PINMASK19" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="20" size="1" name="PINMASK20" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="21" size="1" name="PINMASK21" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="22" size="1" name="PINMASK22" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="23" size="1" name="PINMASK23" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="24" size="1" name="PINMASK24" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="25" size="1" name="PINMASK25" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="26" size="1" name="PINMASK26" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="27" size="1" name="PINMASK27" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="28" size="1" name="PINMASK28" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="29" size="1" name="PINMASK29" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="30" size="1" name="PINMASK30" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="31" size="1" name="PINMASK31" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + </Register> + <Register start="+0x010+64" size="4" name="MASK2" access="Read/Write" description="Mask register for Port." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="PINMASK0" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="1" size="1" name="PINMASK1" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="2" size="1" name="PINMASK2" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="3" size="1" name="PINMASK3" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="4" size="1" name="PINMASK4" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="5" size="1" name="PINMASK5" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="6" size="1" name="PINMASK6" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="7" size="1" name="PINMASK7" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="8" size="1" name="PINMASK8" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="9" size="1" name="PINMASK9" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="10" size="1" name="PINMASK10" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="11" size="1" name="PINMASK11" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="12" size="1" name="PINMASK12" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="13" size="1" name="PINMASK13" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="14" size="1" name="PINMASK14" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="15" size="1" name="PINMASK15" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="16" size="1" name="PINMASK16" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="17" size="1" name="PINMASK17" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="18" size="1" name="PINMASK18" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="19" size="1" name="PINMASK19" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="20" size="1" name="PINMASK20" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="21" size="1" name="PINMASK21" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="22" size="1" name="PINMASK22" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="23" size="1" name="PINMASK23" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="24" size="1" name="PINMASK24" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="25" size="1" name="PINMASK25" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="26" size="1" name="PINMASK26" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="27" size="1" name="PINMASK27" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="28" size="1" name="PINMASK28" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="29" size="1" name="PINMASK29" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="30" size="1" name="PINMASK30" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="31" size="1" name="PINMASK31" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + </Register> + <Register start="+0x010+96" size="4" name="MASK3" access="Read/Write" description="Mask register for Port." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="PINMASK0" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="1" size="1" name="PINMASK1" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="2" size="1" name="PINMASK2" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="3" size="1" name="PINMASK3" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="4" size="1" name="PINMASK4" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="5" size="1" name="PINMASK5" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="6" size="1" name="PINMASK6" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="7" size="1" name="PINMASK7" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="8" size="1" name="PINMASK8" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="9" size="1" name="PINMASK9" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="10" size="1" name="PINMASK10" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="11" size="1" name="PINMASK11" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="12" size="1" name="PINMASK12" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="13" size="1" name="PINMASK13" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="14" size="1" name="PINMASK14" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="15" size="1" name="PINMASK15" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="16" size="1" name="PINMASK16" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="17" size="1" name="PINMASK17" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="18" size="1" name="PINMASK18" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="19" size="1" name="PINMASK19" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="20" size="1" name="PINMASK20" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="21" size="1" name="PINMASK21" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="22" size="1" name="PINMASK22" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="23" size="1" name="PINMASK23" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="24" size="1" name="PINMASK24" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="25" size="1" name="PINMASK25" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="26" size="1" name="PINMASK26" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="27" size="1" name="PINMASK27" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="28" size="1" name="PINMASK28" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="29" size="1" name="PINMASK29" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="30" size="1" name="PINMASK30" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="31" size="1" name="PINMASK31" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + </Register> + <Register start="+0x010+128" size="4" name="MASK4" access="Read/Write" description="Mask register for Port." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="PINMASK0" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="1" size="1" name="PINMASK1" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="2" size="1" name="PINMASK2" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="3" size="1" name="PINMASK3" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="4" size="1" name="PINMASK4" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="5" size="1" name="PINMASK5" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="6" size="1" name="PINMASK6" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="7" size="1" name="PINMASK7" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="8" size="1" name="PINMASK8" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="9" size="1" name="PINMASK9" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="10" size="1" name="PINMASK10" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="11" size="1" name="PINMASK11" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="12" size="1" name="PINMASK12" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="13" size="1" name="PINMASK13" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="14" size="1" name="PINMASK14" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="15" size="1" name="PINMASK15" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="16" size="1" name="PINMASK16" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="17" size="1" name="PINMASK17" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="18" size="1" name="PINMASK18" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="19" size="1" name="PINMASK19" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="20" size="1" name="PINMASK20" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="21" size="1" name="PINMASK21" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="22" size="1" name="PINMASK22" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="23" size="1" name="PINMASK23" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="24" size="1" name="PINMASK24" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="25" size="1" name="PINMASK25" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="26" size="1" name="PINMASK26" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="27" size="1" name="PINMASK27" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="28" size="1" name="PINMASK28" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="29" size="1" name="PINMASK29" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="30" size="1" name="PINMASK30" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + <BitField start="31" size="1" name="PINMASK31" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." /> + </Register> + <Register start="+0x014+0" size="4" name="PIN0" access="Read/Write" description="Port Pin value register using FIOMASK." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="PINVAL0" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="1" size="1" name="PINVAL1" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="2" size="1" name="PINVAL2" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="3" size="1" name="PINVAL3" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="4" size="1" name="PINVAL4" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="5" size="1" name="PINVAL5" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="6" size="1" name="PINVAL6" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="7" size="1" name="PINVAL7" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="8" size="1" name="PINVAL8" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="9" size="1" name="PINVAL9" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="10" size="1" name="PINVAL10" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="11" size="1" name="PINVAL11" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="12" size="1" name="PINVAL12" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="13" size="1" name="PINVAL13" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="14" size="1" name="PINVAL14" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="15" size="1" name="PINVAL15" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="16" size="1" name="PINVAL16" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="17" size="1" name="PINVAL17" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="18" size="1" name="PINVAL18" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="19" size="1" name="PINVAL19" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="20" size="1" name="PINVAL20" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="21" size="1" name="PINVAL21" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="22" size="1" name="PINVAL22" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="23" size="1" name="PINVAL23" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="24" size="1" name="PINVAL24" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="25" size="1" name="PINVAL25" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="26" size="1" name="PINVAL26" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="27" size="1" name="PINVAL27" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="28" size="1" name="PINVAL28" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="29" size="1" name="PINVAL29" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="30" size="1" name="PINVAL30" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="31" size="1" name="PINVAL31" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + </Register> + <Register start="+0x014+32" size="4" name="PIN1" access="Read/Write" description="Port Pin value register using FIOMASK." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="PINVAL0" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="1" size="1" name="PINVAL1" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="2" size="1" name="PINVAL2" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="3" size="1" name="PINVAL3" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="4" size="1" name="PINVAL4" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="5" size="1" name="PINVAL5" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="6" size="1" name="PINVAL6" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="7" size="1" name="PINVAL7" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="8" size="1" name="PINVAL8" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="9" size="1" name="PINVAL9" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="10" size="1" name="PINVAL10" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="11" size="1" name="PINVAL11" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="12" size="1" name="PINVAL12" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="13" size="1" name="PINVAL13" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="14" size="1" name="PINVAL14" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="15" size="1" name="PINVAL15" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="16" size="1" name="PINVAL16" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="17" size="1" name="PINVAL17" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="18" size="1" name="PINVAL18" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="19" size="1" name="PINVAL19" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="20" size="1" name="PINVAL20" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="21" size="1" name="PINVAL21" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="22" size="1" name="PINVAL22" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="23" size="1" name="PINVAL23" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="24" size="1" name="PINVAL24" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="25" size="1" name="PINVAL25" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="26" size="1" name="PINVAL26" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="27" size="1" name="PINVAL27" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="28" size="1" name="PINVAL28" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="29" size="1" name="PINVAL29" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="30" size="1" name="PINVAL30" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="31" size="1" name="PINVAL31" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + </Register> + <Register start="+0x014+64" size="4" name="PIN2" access="Read/Write" description="Port Pin value register using FIOMASK." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="PINVAL0" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="1" size="1" name="PINVAL1" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="2" size="1" name="PINVAL2" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="3" size="1" name="PINVAL3" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="4" size="1" name="PINVAL4" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="5" size="1" name="PINVAL5" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="6" size="1" name="PINVAL6" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="7" size="1" name="PINVAL7" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="8" size="1" name="PINVAL8" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="9" size="1" name="PINVAL9" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="10" size="1" name="PINVAL10" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="11" size="1" name="PINVAL11" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="12" size="1" name="PINVAL12" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="13" size="1" name="PINVAL13" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="14" size="1" name="PINVAL14" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="15" size="1" name="PINVAL15" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="16" size="1" name="PINVAL16" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="17" size="1" name="PINVAL17" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="18" size="1" name="PINVAL18" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="19" size="1" name="PINVAL19" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="20" size="1" name="PINVAL20" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="21" size="1" name="PINVAL21" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="22" size="1" name="PINVAL22" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="23" size="1" name="PINVAL23" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="24" size="1" name="PINVAL24" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="25" size="1" name="PINVAL25" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="26" size="1" name="PINVAL26" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="27" size="1" name="PINVAL27" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="28" size="1" name="PINVAL28" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="29" size="1" name="PINVAL29" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="30" size="1" name="PINVAL30" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="31" size="1" name="PINVAL31" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + </Register> + <Register start="+0x014+96" size="4" name="PIN3" access="Read/Write" description="Port Pin value register using FIOMASK." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="PINVAL0" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="1" size="1" name="PINVAL1" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="2" size="1" name="PINVAL2" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="3" size="1" name="PINVAL3" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="4" size="1" name="PINVAL4" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="5" size="1" name="PINVAL5" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="6" size="1" name="PINVAL6" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="7" size="1" name="PINVAL7" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="8" size="1" name="PINVAL8" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="9" size="1" name="PINVAL9" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="10" size="1" name="PINVAL10" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="11" size="1" name="PINVAL11" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="12" size="1" name="PINVAL12" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="13" size="1" name="PINVAL13" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="14" size="1" name="PINVAL14" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="15" size="1" name="PINVAL15" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="16" size="1" name="PINVAL16" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="17" size="1" name="PINVAL17" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="18" size="1" name="PINVAL18" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="19" size="1" name="PINVAL19" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="20" size="1" name="PINVAL20" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="21" size="1" name="PINVAL21" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="22" size="1" name="PINVAL22" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="23" size="1" name="PINVAL23" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="24" size="1" name="PINVAL24" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="25" size="1" name="PINVAL25" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="26" size="1" name="PINVAL26" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="27" size="1" name="PINVAL27" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="28" size="1" name="PINVAL28" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="29" size="1" name="PINVAL29" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="30" size="1" name="PINVAL30" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="31" size="1" name="PINVAL31" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + </Register> + <Register start="+0x014+128" size="4" name="PIN4" access="Read/Write" description="Port Pin value register using FIOMASK." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="PINVAL0" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="1" size="1" name="PINVAL1" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="2" size="1" name="PINVAL2" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="3" size="1" name="PINVAL3" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="4" size="1" name="PINVAL4" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="5" size="1" name="PINVAL5" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="6" size="1" name="PINVAL6" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="7" size="1" name="PINVAL7" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="8" size="1" name="PINVAL8" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="9" size="1" name="PINVAL9" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="10" size="1" name="PINVAL10" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="11" size="1" name="PINVAL11" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="12" size="1" name="PINVAL12" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="13" size="1" name="PINVAL13" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="14" size="1" name="PINVAL14" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="15" size="1" name="PINVAL15" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="16" size="1" name="PINVAL16" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="17" size="1" name="PINVAL17" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="18" size="1" name="PINVAL18" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="19" size="1" name="PINVAL19" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="20" size="1" name="PINVAL20" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="21" size="1" name="PINVAL21" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="22" size="1" name="PINVAL22" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="23" size="1" name="PINVAL23" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="24" size="1" name="PINVAL24" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="25" size="1" name="PINVAL25" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="26" size="1" name="PINVAL26" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="27" size="1" name="PINVAL27" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="28" size="1" name="PINVAL28" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="29" size="1" name="PINVAL29" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="30" size="1" name="PINVAL30" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + <BitField start="31" size="1" name="PINVAL31" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." /> + </Register> + <Register start="+0x018+0" size="4" name="SET0" access="Read/Write" description="Port Output Set register using FIOMASK." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="PINSET0" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="1" size="1" name="PINSET1" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="2" size="1" name="PINSET2" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="3" size="1" name="PINSET3" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="4" size="1" name="PINSET4" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="5" size="1" name="PINSET5" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="6" size="1" name="PINSET6" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="7" size="1" name="PINSET7" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="8" size="1" name="PINSET8" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="9" size="1" name="PINSET9" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="10" size="1" name="PINSET10" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="11" size="1" name="PINSET11" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="12" size="1" name="PINSET12" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="13" size="1" name="PINSET13" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="14" size="1" name="PINSET14" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="15" size="1" name="PINSET15" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="16" size="1" name="PINSET16" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="17" size="1" name="PINSET17" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="18" size="1" name="PINSET18" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="19" size="1" name="PINSET19" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="20" size="1" name="PINSET20" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="21" size="1" name="PINSET21" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="22" size="1" name="PINSET22" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="23" size="1" name="PINSET23" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="24" size="1" name="PINSET24" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="25" size="1" name="PINSET25" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="26" size="1" name="PINSET26" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="27" size="1" name="PINSET27" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="28" size="1" name="PINSET28" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="29" size="1" name="PINSET29" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="30" size="1" name="PINSET30" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="31" size="1" name="PINSET31" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + </Register> + <Register start="+0x018+32" size="4" name="SET1" access="Read/Write" description="Port Output Set register using FIOMASK." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="PINSET0" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="1" size="1" name="PINSET1" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="2" size="1" name="PINSET2" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="3" size="1" name="PINSET3" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="4" size="1" name="PINSET4" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="5" size="1" name="PINSET5" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="6" size="1" name="PINSET6" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="7" size="1" name="PINSET7" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="8" size="1" name="PINSET8" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="9" size="1" name="PINSET9" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="10" size="1" name="PINSET10" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="11" size="1" name="PINSET11" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="12" size="1" name="PINSET12" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="13" size="1" name="PINSET13" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="14" size="1" name="PINSET14" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="15" size="1" name="PINSET15" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="16" size="1" name="PINSET16" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="17" size="1" name="PINSET17" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="18" size="1" name="PINSET18" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="19" size="1" name="PINSET19" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="20" size="1" name="PINSET20" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="21" size="1" name="PINSET21" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="22" size="1" name="PINSET22" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="23" size="1" name="PINSET23" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="24" size="1" name="PINSET24" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="25" size="1" name="PINSET25" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="26" size="1" name="PINSET26" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="27" size="1" name="PINSET27" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="28" size="1" name="PINSET28" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="29" size="1" name="PINSET29" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="30" size="1" name="PINSET30" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="31" size="1" name="PINSET31" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + </Register> + <Register start="+0x018+64" size="4" name="SET2" access="Read/Write" description="Port Output Set register using FIOMASK." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="PINSET0" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="1" size="1" name="PINSET1" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="2" size="1" name="PINSET2" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="3" size="1" name="PINSET3" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="4" size="1" name="PINSET4" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="5" size="1" name="PINSET5" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="6" size="1" name="PINSET6" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="7" size="1" name="PINSET7" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="8" size="1" name="PINSET8" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="9" size="1" name="PINSET9" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="10" size="1" name="PINSET10" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="11" size="1" name="PINSET11" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="12" size="1" name="PINSET12" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="13" size="1" name="PINSET13" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="14" size="1" name="PINSET14" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="15" size="1" name="PINSET15" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="16" size="1" name="PINSET16" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="17" size="1" name="PINSET17" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="18" size="1" name="PINSET18" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="19" size="1" name="PINSET19" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="20" size="1" name="PINSET20" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="21" size="1" name="PINSET21" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="22" size="1" name="PINSET22" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="23" size="1" name="PINSET23" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="24" size="1" name="PINSET24" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="25" size="1" name="PINSET25" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="26" size="1" name="PINSET26" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="27" size="1" name="PINSET27" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="28" size="1" name="PINSET28" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="29" size="1" name="PINSET29" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="30" size="1" name="PINSET30" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="31" size="1" name="PINSET31" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + </Register> + <Register start="+0x018+96" size="4" name="SET3" access="Read/Write" description="Port Output Set register using FIOMASK." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="PINSET0" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="1" size="1" name="PINSET1" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="2" size="1" name="PINSET2" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="3" size="1" name="PINSET3" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="4" size="1" name="PINSET4" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="5" size="1" name="PINSET5" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="6" size="1" name="PINSET6" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="7" size="1" name="PINSET7" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="8" size="1" name="PINSET8" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="9" size="1" name="PINSET9" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="10" size="1" name="PINSET10" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="11" size="1" name="PINSET11" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="12" size="1" name="PINSET12" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="13" size="1" name="PINSET13" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="14" size="1" name="PINSET14" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="15" size="1" name="PINSET15" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="16" size="1" name="PINSET16" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="17" size="1" name="PINSET17" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="18" size="1" name="PINSET18" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="19" size="1" name="PINSET19" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="20" size="1" name="PINSET20" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="21" size="1" name="PINSET21" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="22" size="1" name="PINSET22" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="23" size="1" name="PINSET23" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="24" size="1" name="PINSET24" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="25" size="1" name="PINSET25" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="26" size="1" name="PINSET26" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="27" size="1" name="PINSET27" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="28" size="1" name="PINSET28" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="29" size="1" name="PINSET29" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="30" size="1" name="PINSET30" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="31" size="1" name="PINSET31" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + </Register> + <Register start="+0x018+128" size="4" name="SET4" access="Read/Write" description="Port Output Set register using FIOMASK." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="PINSET0" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="1" size="1" name="PINSET1" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="2" size="1" name="PINSET2" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="3" size="1" name="PINSET3" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="4" size="1" name="PINSET4" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="5" size="1" name="PINSET5" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="6" size="1" name="PINSET6" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="7" size="1" name="PINSET7" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="8" size="1" name="PINSET8" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="9" size="1" name="PINSET9" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="10" size="1" name="PINSET10" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="11" size="1" name="PINSET11" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="12" size="1" name="PINSET12" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="13" size="1" name="PINSET13" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="14" size="1" name="PINSET14" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="15" size="1" name="PINSET15" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="16" size="1" name="PINSET16" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="17" size="1" name="PINSET17" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="18" size="1" name="PINSET18" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="19" size="1" name="PINSET19" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="20" size="1" name="PINSET20" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="21" size="1" name="PINSET21" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="22" size="1" name="PINSET22" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="23" size="1" name="PINSET23" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="24" size="1" name="PINSET24" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="25" size="1" name="PINSET25" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="26" size="1" name="PINSET26" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="27" size="1" name="PINSET27" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="28" size="1" name="PINSET28" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="29" size="1" name="PINSET29" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="30" size="1" name="PINSET30" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + <BitField start="31" size="1" name="PINSET31" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." /> + </Register> + <Register start="+0x01C+0" size="4" name="CLR0" access="WriteOnly" description="Port Output Clear register using FIOMASK." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="PINCLR0" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="1" size="1" name="PINCLR1" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="2" size="1" name="PINCLR2" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="3" size="1" name="PINCLR3" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="4" size="1" name="PINCLR4" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="5" size="1" name="PINCLR5" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="6" size="1" name="PINCLR6" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="7" size="1" name="PINCLR7" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="8" size="1" name="PINCLR8" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="9" size="1" name="PINCLR9" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="10" size="1" name="PINCLR10" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="11" size="1" name="PINCLR11" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="12" size="1" name="PINCLR12" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="13" size="1" name="PINCLR13" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="14" size="1" name="PINCLR14" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="15" size="1" name="PINCLR15" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="16" size="1" name="PINCLR16" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="17" size="1" name="PINCLR17" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="18" size="1" name="PINCLR18" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="19" size="1" name="PINCLR19" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="20" size="1" name="PINCLR20" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="21" size="1" name="PINCLR21" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="22" size="1" name="PINCLR22" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="23" size="1" name="PINCLR23" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="24" size="1" name="PINCLR24" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="25" size="1" name="PINCLR25" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="26" size="1" name="PINCLR26" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="27" size="1" name="PINCLR27" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="28" size="1" name="PINCLR28" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="29" size="1" name="PINCLR29" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="30" size="1" name="PINCLR30" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="31" size="1" name="PINCLR31" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + </Register> + <Register start="+0x01C+32" size="4" name="CLR1" access="WriteOnly" description="Port Output Clear register using FIOMASK." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="PINCLR0" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="1" size="1" name="PINCLR1" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="2" size="1" name="PINCLR2" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="3" size="1" name="PINCLR3" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="4" size="1" name="PINCLR4" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="5" size="1" name="PINCLR5" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="6" size="1" name="PINCLR6" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="7" size="1" name="PINCLR7" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="8" size="1" name="PINCLR8" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="9" size="1" name="PINCLR9" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="10" size="1" name="PINCLR10" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="11" size="1" name="PINCLR11" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="12" size="1" name="PINCLR12" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="13" size="1" name="PINCLR13" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="14" size="1" name="PINCLR14" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="15" size="1" name="PINCLR15" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="16" size="1" name="PINCLR16" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="17" size="1" name="PINCLR17" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="18" size="1" name="PINCLR18" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="19" size="1" name="PINCLR19" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="20" size="1" name="PINCLR20" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="21" size="1" name="PINCLR21" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="22" size="1" name="PINCLR22" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="23" size="1" name="PINCLR23" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="24" size="1" name="PINCLR24" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="25" size="1" name="PINCLR25" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="26" size="1" name="PINCLR26" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="27" size="1" name="PINCLR27" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="28" size="1" name="PINCLR28" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="29" size="1" name="PINCLR29" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="30" size="1" name="PINCLR30" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="31" size="1" name="PINCLR31" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + </Register> + <Register start="+0x01C+64" size="4" name="CLR2" access="WriteOnly" description="Port Output Clear register using FIOMASK." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="PINCLR0" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="1" size="1" name="PINCLR1" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="2" size="1" name="PINCLR2" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="3" size="1" name="PINCLR3" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="4" size="1" name="PINCLR4" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="5" size="1" name="PINCLR5" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="6" size="1" name="PINCLR6" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="7" size="1" name="PINCLR7" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="8" size="1" name="PINCLR8" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="9" size="1" name="PINCLR9" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="10" size="1" name="PINCLR10" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="11" size="1" name="PINCLR11" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="12" size="1" name="PINCLR12" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="13" size="1" name="PINCLR13" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="14" size="1" name="PINCLR14" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="15" size="1" name="PINCLR15" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="16" size="1" name="PINCLR16" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="17" size="1" name="PINCLR17" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="18" size="1" name="PINCLR18" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="19" size="1" name="PINCLR19" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="20" size="1" name="PINCLR20" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="21" size="1" name="PINCLR21" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="22" size="1" name="PINCLR22" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="23" size="1" name="PINCLR23" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="24" size="1" name="PINCLR24" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="25" size="1" name="PINCLR25" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="26" size="1" name="PINCLR26" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="27" size="1" name="PINCLR27" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="28" size="1" name="PINCLR28" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="29" size="1" name="PINCLR29" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="30" size="1" name="PINCLR30" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="31" size="1" name="PINCLR31" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + </Register> + <Register start="+0x01C+96" size="4" name="CLR3" access="WriteOnly" description="Port Output Clear register using FIOMASK." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="PINCLR0" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="1" size="1" name="PINCLR1" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="2" size="1" name="PINCLR2" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="3" size="1" name="PINCLR3" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="4" size="1" name="PINCLR4" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="5" size="1" name="PINCLR5" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="6" size="1" name="PINCLR6" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="7" size="1" name="PINCLR7" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="8" size="1" name="PINCLR8" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="9" size="1" name="PINCLR9" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="10" size="1" name="PINCLR10" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="11" size="1" name="PINCLR11" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="12" size="1" name="PINCLR12" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="13" size="1" name="PINCLR13" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="14" size="1" name="PINCLR14" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="15" size="1" name="PINCLR15" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="16" size="1" name="PINCLR16" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="17" size="1" name="PINCLR17" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="18" size="1" name="PINCLR18" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="19" size="1" name="PINCLR19" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="20" size="1" name="PINCLR20" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="21" size="1" name="PINCLR21" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="22" size="1" name="PINCLR22" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="23" size="1" name="PINCLR23" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="24" size="1" name="PINCLR24" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="25" size="1" name="PINCLR25" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="26" size="1" name="PINCLR26" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="27" size="1" name="PINCLR27" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="28" size="1" name="PINCLR28" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="29" size="1" name="PINCLR29" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="30" size="1" name="PINCLR30" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="31" size="1" name="PINCLR31" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + </Register> + <Register start="+0x01C+128" size="4" name="CLR4" access="WriteOnly" description="Port Output Clear register using FIOMASK." reset_value="0" reset_mask="0xFFFFFFFF"> + <BitField start="0" size="1" name="PINCLR0" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="1" size="1" name="PINCLR1" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="2" size="1" name="PINCLR2" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="3" size="1" name="PINCLR3" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="4" size="1" name="PINCLR4" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="5" size="1" name="PINCLR5" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="6" size="1" name="PINCLR6" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="7" size="1" name="PINCLR7" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="8" size="1" name="PINCLR8" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="9" size="1" name="PINCLR9" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="10" size="1" name="PINCLR10" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="11" size="1" name="PINCLR11" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="12" size="1" name="PINCLR12" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="13" size="1" name="PINCLR13" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="14" size="1" name="PINCLR14" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="15" size="1" name="PINCLR15" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="16" size="1" name="PINCLR16" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="17" size="1" name="PINCLR17" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="18" size="1" name="PINCLR18" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="19" size="1" name="PINCLR19" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="20" size="1" name="PINCLR20" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="21" size="1" name="PINCLR21" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="22" size="1" name="PINCLR22" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="23" size="1" name="PINCLR23" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="24" size="1" name="PINCLR24" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="25" size="1" name="PINCLR25" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="26" size="1" name="PINCLR26" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="27" size="1" name="PINCLR27" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="28" size="1" name="PINCLR28" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="29" size="1" name="PINCLR29" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="30" size="1" name="PINCLR30" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + <BitField start="31" size="1" name="PINCLR31" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." /> + </Register> + </RegisterGroup> + <RegisterGroup name="NVIC" start="0xE000E100" description="Nested Vectored Interrupt Controller"> + <Register name="NVIC_ISER0" description="Interrupt Set-Enable Register 0" start="0xE000E100"> + <BitField name="WDT" start="0" size="1" /> + <BitField name="TIMER0" start="1" size="1" /> + <BitField name="TIMER1" start="2" size="1" /> + <BitField name="TIMER2" start="3" size="1" /> + <BitField name="TIMER3" start="4" size="1" /> + <BitField name="UART0" start="5" size="1" /> + <BitField name="UART1" start="6" size="1" /> + <BitField name="UART2" start="7" size="1" /> + <BitField name="UART3" start="8" size="1" /> + <BitField name="PWM1" start="9" size="1" /> + <BitField name="I2C0" start="10" size="1" /> + <BitField name="I2C1" start="11" size="1" /> + <BitField name="I2C2" start="12" size="1" /> + <BitField name="SPI" start="13" size="1" /> + <BitField name="SSP0" start="14" size="1" /> + <BitField name="SSP1" start="15" size="1" /> + <BitField name="PLL0" start="16" size="1" /> + <BitField name="RTC" start="17" size="1" /> + <BitField name="EINT0" start="18" size="1" /> + <BitField name="EINT1" start="19" size="1" /> + <BitField name="EINT2" start="20" size="1" /> + <BitField name="EINT3" start="21" size="1" /> + <BitField name="ADC" start="22" size="1" /> + <BitField name="BOD" start="23" size="1" /> + <BitField name="USB" start="24" size="1" /> + <BitField name="CAN" start="25" size="1" /> + <BitField name="DMA" start="26" size="1" /> + <BitField name="I2S" start="27" size="1" /> + <BitField name="ENET" start="28" size="1" /> + <BitField name="RIT" start="29" size="1" /> + <BitField name="MCPWM" start="30" size="1" /> + <BitField name="QEI" start="31" size="1" /> + </Register> + <Register name="NVIC_ISER1" description="Interrupt Set-Enable Register 1" start="0xE000E104"> + <BitField name="PLL1" start="0" size="1" /> + <BitField name="USBActivity" start="1" size="1" /> + <BitField name="CANActivity" start="2" size="1" /> + </Register> + <Register name="NVIC_ICER0" description="Interrupt Clear-Enable Register 0" start="0xE000E180"> + <BitField name="WDT" start="0" size="1" /> + <BitField name="TIMER0" start="1" size="1" /> + <BitField name="TIMER1" start="2" size="1" /> + <BitField name="TIMER2" start="3" size="1" /> + <BitField name="TIMER3" start="4" size="1" /> + <BitField name="UART0" start="5" size="1" /> + <BitField name="UART1" start="6" size="1" /> + <BitField name="UART2" start="7" size="1" /> + <BitField name="UART3" start="8" size="1" /> + <BitField name="PWM1" start="9" size="1" /> + <BitField name="I2C0" start="10" size="1" /> + <BitField name="I2C1" start="11" size="1" /> + <BitField name="I2C2" start="12" size="1" /> + <BitField name="SPI" start="13" size="1" /> + <BitField name="SSP0" start="14" size="1" /> + <BitField name="SSP1" start="15" size="1" /> + <BitField name="PLL0" start="16" size="1" /> + <BitField name="RTC" start="17" size="1" /> + <BitField name="EINT0" start="18" size="1" /> + <BitField name="EINT1" start="19" size="1" /> + <BitField name="EINT2" start="20" size="1" /> + <BitField name="EINT3" start="21" size="1" /> + <BitField name="ADC" start="22" size="1" /> + <BitField name="BOD" start="23" size="1" /> + <BitField name="USB" start="24" size="1" /> + <BitField name="CAN" start="25" size="1" /> + <BitField name="DMA" start="26" size="1" /> + <BitField name="I2S" start="27" size="1" /> + <BitField name="ENET" start="28" size="1" /> + <BitField name="RIT" start="29" size="1" /> + <BitField name="MCPWM" start="30" size="1" /> + <BitField name="QEI" start="31" size="1" /> + </Register> + <Register name="NVIC_ICER1" description="Interrupt Clear-Enable Register 1" start="0xE000E184"> + <BitField name="PLL1" start="0" size="1" /> + <BitField name="USBActivity" start="1" size="1" /> + <BitField name="CANActivity" start="2" size="1" /> + </Register> + <Register name="NVIC_ISPR0" description="Interrupt Set-Pending Register 0" start="0xE000E200"> + <BitField name="WDT" start="0" size="1" /> + <BitField name="TIMER0" start="1" size="1" /> + <BitField name="TIMER1" start="2" size="1" /> + <BitField name="TIMER2" start="3" size="1" /> + <BitField name="TIMER3" start="4" size="1" /> + <BitField name="UART0" start="5" size="1" /> + <BitField name="UART1" start="6" size="1" /> + <BitField name="UART2" start="7" size="1" /> + <BitField name="UART3" start="8" size="1" /> + <BitField name="PWM1" start="9" size="1" /> + <BitField name="I2C0" start="10" size="1" /> + <BitField name="I2C1" start="11" size="1" /> + <BitField name="I2C2" start="12" size="1" /> + <BitField name="SPI" start="13" size="1" /> + <BitField name="SSP0" start="14" size="1" /> + <BitField name="SSP1" start="15" size="1" /> + <BitField name="PLL0" start="16" size="1" /> + <BitField name="RTC" start="17" size="1" /> + <BitField name="EINT0" start="18" size="1" /> + <BitField name="EINT1" start="19" size="1" /> + <BitField name="EINT2" start="20" size="1" /> + <BitField name="EINT3" start="21" size="1" /> + <BitField name="ADC" start="22" size="1" /> + <BitField name="BOD" start="23" size="1" /> + <BitField name="USB" start="24" size="1" /> + <BitField name="CAN" start="25" size="1" /> + <BitField name="DMA" start="26" size="1" /> + <BitField name="I2S" start="27" size="1" /> + <BitField name="ENET" start="28" size="1" /> + <BitField name="RIT" start="29" size="1" /> + <BitField name="MCPWM" start="30" size="1" /> + <BitField name="QEI" start="31" size="1" /> + </Register> + <Register name="NVIC_ISPR1" description="Interrupt Set-Pending Register 1" start="0xE000E204"> + <BitField name="PLL1" start="0" size="1" /> + <BitField name="USBActivity" start="1" size="1" /> + <BitField name="CANActivity" start="2" size="1" /> + </Register> + <Register name="NVIC_ICPR0" description="Interrupt Clear-Pending Register 0" start="0xE000E280"> + <BitField name="WDT" start="0" size="1" /> + <BitField name="TIMER0" start="1" size="1" /> + <BitField name="TIMER1" start="2" size="1" /> + <BitField name="TIMER2" start="3" size="1" /> + <BitField name="TIMER3" start="4" size="1" /> + <BitField name="UART0" start="5" size="1" /> + <BitField name="UART1" start="6" size="1" /> + <BitField name="UART2" start="7" size="1" /> + <BitField name="UART3" start="8" size="1" /> + <BitField name="PWM1" start="9" size="1" /> + <BitField name="I2C0" start="10" size="1" /> + <BitField name="I2C1" start="11" size="1" /> + <BitField name="I2C2" start="12" size="1" /> + <BitField name="SPI" start="13" size="1" /> + <BitField name="SSP0" start="14" size="1" /> + <BitField name="SSP1" start="15" size="1" /> + <BitField name="PLL0" start="16" size="1" /> + <BitField name="RTC" start="17" size="1" /> + <BitField name="EINT0" start="18" size="1" /> + <BitField name="EINT1" start="19" size="1" /> + <BitField name="EINT2" start="20" size="1" /> + <BitField name="EINT3" start="21" size="1" /> + <BitField name="ADC" start="22" size="1" /> + <BitField name="BOD" start="23" size="1" /> + <BitField name="USB" start="24" size="1" /> + <BitField name="CAN" start="25" size="1" /> + <BitField name="DMA" start="26" size="1" /> + <BitField name="I2S" start="27" size="1" /> + <BitField name="ENET" start="28" size="1" /> + <BitField name="RIT" start="29" size="1" /> + <BitField name="MCPWM" start="30" size="1" /> + <BitField name="QEI" start="31" size="1" /> + </Register> + <Register name="NVIC_ICPR1" description="Interrupt Clear-Pending Register 1" start="0xE000E284"> + <BitField name="PLL1" start="0" size="1" /> + <BitField name="USBActivity" start="1" size="1" /> + <BitField name="CANActivity" start="2" size="1" /> + </Register> + <Register name="NVIC_IABR0" description="Interrupt Active Bit Register 0" start="0xE000E300" access="ReadOnly"> + <BitField name="WDT" start="0" size="1" /> + <BitField name="TIMER0" start="1" size="1" /> + <BitField name="TIMER1" start="2" size="1" /> + <BitField name="TIMER2" start="3" size="1" /> + <BitField name="TIMER3" start="4" size="1" /> + <BitField name="UART0" start="5" size="1" /> + <BitField name="UART1" start="6" size="1" /> + <BitField name="UART2" start="7" size="1" /> + <BitField name="UART3" start="8" size="1" /> + <BitField name="PWM1" start="9" size="1" /> + <BitField name="I2C0" start="10" size="1" /> + <BitField name="I2C1" start="11" size="1" /> + <BitField name="I2C2" start="12" size="1" /> + <BitField name="SPI" start="13" size="1" /> + <BitField name="SSP0" start="14" size="1" /> + <BitField name="SSP1" start="15" size="1" /> + <BitField name="PLL0" start="16" size="1" /> + <BitField name="RTC" start="17" size="1" /> + <BitField name="EINT0" start="18" size="1" /> + <BitField name="EINT1" start="19" size="1" /> + <BitField name="EINT2" start="20" size="1" /> + <BitField name="EINT3" start="21" size="1" /> + <BitField name="ADC" start="22" size="1" /> + <BitField name="BOD" start="23" size="1" /> + <BitField name="USB" start="24" size="1" /> + <BitField name="CAN" start="25" size="1" /> + <BitField name="DMA" start="26" size="1" /> + <BitField name="I2S" start="27" size="1" /> + <BitField name="ENET" start="28" size="1" /> + <BitField name="RIT" start="29" size="1" /> + <BitField name="MCPWM" start="30" size="1" /> + <BitField name="QEI" start="31" size="1" /> + </Register> + <Register name="NVIC_IABR1" description="Interrupt Active Bit Register 1" start="0xE000E304" access="ReadOnly"> + <BitField name="PLL1" start="0" size="1" /> + <BitField name="USBActivity" start="1" size="1" /> + <BitField name="CANActivity" start="2" size="1" /> + </Register> + <Register name="NVIC_IPR0" description="Interrupt Priority Register 0" start="0xE000E400"> + <BitField name="WDT" start="4" size="4" /> + <BitField name="TIMER0" start="12" size="4" /> + <BitField name="TIMER1" start="20" size="4" /> + <BitField name="TIMER2" start="28" size="4" /> + </Register> + <Register name="NVIC_IPR1" description="Interrupt Priority Register 1" start="0xE000E404"> + <BitField name="TIMER3" start="4" size="4" /> + <BitField name="UART0" start="12" size="4" /> + <BitField name="UART1" start="20" size="4" /> + <BitField name="UART2" start="28" size="4" /> + </Register> + <Register name="NVIC_IPR2" description="Interrupt Priority Register 2" start="0xE000E408"> + <BitField name="UART3" start="4" size="4" /> + <BitField name="PWM1" start="12" size="4" /> + <BitField name="I2C0" start="20" size="4" /> + <BitField name="I2C1" start="28" size="4" /> + </Register> + <Register name="NVIC_IPR3" description="Interrupt Priority Register 3" start="0xE000E40C"> + <BitField name="I2C2" start="4" size="4" /> + <BitField name="SPI" start="12" size="4" /> + <BitField name="SSP0" start="20" size="4" /> + <BitField name="SSP1" start="28" size="4" /> + </Register> + <Register name="NVIC_IPR4" description="Interrupt Priority Register 4" start="0xE000E410"> + <BitField name="PLL0" start="4" size="4" /> + <BitField name="RTC" start="12" size="4" /> + <BitField name="EINT0" start="20" size="4" /> + <BitField name="EINT1" start="28" size="4" /> + </Register> + <Register name="NVIC_IPR5" description="Interrupt Priority Register 5" start="0xE000E414"> + <BitField name="EINT2" start="4" size="4" /> + <BitField name="EINT3" start="12" size="4" /> + <BitField name="ADC" start="20" size="4" /> + <BitField name="BOD" start="28" size="4" /> + </Register> + <Register name="NVIC_IPR6" description="Interrupt Priority Register 6" start="0xE000E418"> + <BitField name="USB" start="4" size="4" /> + <BitField name="CAN" start="12" size="4" /> + <BitField name="DMA" start="20" size="4" /> + <BitField name="I2S" start="28" size="4" /> + </Register> + <Register name="NVIC_IPR7" description="Interrupt Priority Register 7" start="0xE000E41C"> + <BitField name="ENET" start="4" size="4" /> + <BitField name="RIT" start="12" size="4" /> + <BitField name="MCPWM" start="20" size="4" /> + <BitField name="QEI" start="28" size="4" /> + </Register> + <Register name="NVIC_IPR8" description="Interrupt Priority Register 8" start="0xE000E420"> + <BitField name="PLL1" start="4" size="4" /> + <BitField name="USBActivity" start="12" size="4" /> + <BitField name="CANActivity" start="20" size="4" /> + </Register> + </RegisterGroup> + <RegisterGroup name="SysTick" start="0xE000E010" description="24-bit System Timer"> + <Register name="SYS_CSR" start="0xE000E010" description="SysTick Control and Status Register"> + <BitField name="COUNTFLAG" start="16" size="1" description="Counter Flag" /> + <BitField name="CLKSOURCE" start="2" size="1" description="Timer Clock Source" /> + <BitField name="TICKINT" start="1" size="1" description="Tick Interrupt Enable" /> + <BitField name="ENABLE" start="0" size="1" description="Enable SysTick Timer" /> + </Register> + <Register name="SYS_RVR" start="0xE000E014" description="SysTick Reload Value Register"> + <BitField name="RELOAD" start="0" size="24" description="Value to load into the SYST_CVR when the counter is enabled and when it reaches 0" /> + </Register> + <Register name="SYS_CVR" start="0xE000E018" description="SysTick Current Value Register Register"> + <BitField name="CURRENT" start="0" size="24" description="The current value of the SysTick counter" /> + </Register> + <Register name="SYS_CALIB" start="0xE000E01C" access="ReadOnly" description="SysTick Calibration Value Register"> + <BitField name="NOREF" start="31" size="1" description="Indicates whether the device provides a reference clock to the processor" /> + <BitField name="SKEW" start="30" size="1" description="Indicates whether the TENMS value is exact" /> + <BitField name="TENMS" start="0" size="24" description="Reload value for 10ms (100Hz) timing, subject to system clock skew errors" /> + </Register> + </RegisterGroup> + <RegisterGroup name="SCB" start="" description="System Control Block"> + <Register name="ACTLR" start="0xE000E008" description="Auxiliary Control Register"> + <BitField name="DISDEFWBUF" start="1" size="1" description="When set to 1, disables write buffer use during default memory map accesses" /> + <BitField name="DISMCYCINT" start="0" size="1" description="When set to 1, disables interruption of load multiple and store multiple instructions" /> + </Register> + <Register name="CPUID" start="0xE000ED00" access="ReadOnly" description="CPUID Register"> + <BitField name="IMPLEMENTER" start="24" size="8" description="Implementer Code" /> + <BitField name="VARIANT" start="20" size="4" description="Variant Number" /> + <BitField name="PARTNO" start="4" size="12" description="Part Number" /> + <BitField name="REVISION" start="0" size="4" description="Revision Number" /> + </Register> + <Register name="ICSR" start="0xE000ED04" description="Interrupt Control and State Register"> + <BitField name="NMIPENDSET" start="31" size="1" description="NMI set-pending bit" /> + <BitField name="PENDSVSET" start="28" size="1" description="PendSV set-pending bit" /> + <BitField name="PENDSVCLR" start="27" size="1" description="PendSV clear-pending bit" /> + <BitField name="PENDSTSET" start="26" size="1" description="SysTick exception set-pending bit" /> + <BitField name="PENDSTCLR" start="25" size="1" description="SysTick exception clear-pending bit" /> + <BitField name="ISRPREEMPT" start="23" size="1" description="" /> + <BitField name="ISRPENDING" start="22" size="1" description="Interrupt pending flag" /> + <BitField name="VECTPENDING" start="12" size="9" description="Indicates the exception number of the highest priority pending enabled exception" /> + <BitField name="RETTOBASE" start="11" size="1" description="Indicates whether there are preempted active exceptions" /> + <BitField name="VECTACTIVE" start="0" size="9" description="Contains the active exception number" /> + </Register> + <Register name="VTOR" start="0xE000ED08" description="Vector Table Offset Register"> + <BitField name="TBLOFF" start="7" size="25" description="Vector table base offset field" /> + </Register> + <Register name="AIRCR" start="0xE000ED0C" description="Application Interrupt and Reset Control Register"> + <BitField name="VECTKEY" start="16" size="16" description="Register key" /> + <BitField name="ENDIANESS" start="15" size="1" description="Data endianness bit" /> + <BitField name="PRIGROUP" start="8" size="3" description="Interrupt priority grouping field" /> + <BitField name="SYSRESETREQ" start="2" size="1" description="System reset request bit" /> + <BitField name="VECTCLRACTIVE" start="1" size="1" description="" /> + <BitField name="VECTRESET" start="0" size="1" description="" /> + </Register> + <Register name="SCR" start="0xE000ED10" description="System Control Register"> + <BitField name="SEVONPEND" start="4" size="1" description="Send event on pending bit" /> + <BitField name="SLEEPDEEP" start="2" size="1" description="Controls whether the processor uses sleep or deep sleep as its low power mode" /> + <BitField name="SLEEPONEXIT" start="1" size="1" description="Indicates sleep-on-exit when returning from Handler mode to Thread mode" /> + </Register> + <Register name="CCR" start="0xE000ED14" access="ReadOnly" description="Configuration and Control Register"> + <BitField name="STKALIGN" start="9" size="1" description="Indicates stack alignment on exception entry" /> + <BitField name="BFHFNMIGN" start="8" size="1" description="Enables handlers with priority -1 or-2 to ignore data BusFaults caused by load and store instructions" /> + <BitField name="DIV_0_TRP" start="4" size="1" description="Enables faulting or halting when the processor executes an SDIVor UDIV instruction with a divisor of 0" /> + <BitField name="UNALIGN_TRP" start="3" size="1" description="Enables unaligned access traps" /> + <BitField name="USERSETMPEND" start="1" size="1" description="Enables unprivileged software access to the STIR" /> + <BitField name="NONBASETHRDENA" start="0" size="1" description="Indicates how the processor enters Thread mode" /> + </Register> + <Register name="SHPR1" start="0xE000ED18" description="System Handler Priority Register 1"> + <BitField name="PRI_6" start="20" size="4" description="Priority of system handler 6 (UsageFault)" /> + <BitField name="PRI_5" start="12" size="4" description="Priority of system handler 5 (BusFault)" /> + <BitField name="PRI_4" start="4" size="4" description="Priority of system handler 4 (MemManage)" /> + </Register> + <Register name="SHPR2" start="0xE000ED1C" description="System Handler Priority Register 2"> + <BitField name="PRI_11" start="28" size="4" description="Priority of system handler 11 (SVCall)" /> + </Register> + <Register name="SHPR3" start="0xE000ED20" description="System Handler Priority Register 3"> + <BitField name="PRI_15" start="28" size="4" description="Priority of system handler 15 (SysTick)" /> + <BitField name="PRI_14" start="20" size="4" description="Priority of system handler 14 (PendSV)" /> + </Register> + <Register name="SHCSR" start="0xE000ED24" description="System Handler Control and State Register"> + <BitField name="USGFAULTENA" start="18" size="1" description="UsageFault enable Bit" /> + <BitField name="BUSFAULTENA" start="17" size="1" description="BusFault Enable Bit" /> + <BitField name="MEMFAULTENA" start="16" size="1" description="MemManage Enable Bit" /> + <BitField name="SVCALLPENDED" start="15" size="1" description="SVCall Pending Bit" /> + <BitField name="BUSFAULTPENDED" start="14" size="1" description="BusFault Exception Pending Bit" /> + <BitField name="MEMFAULTPENDED" start="13" size="1" description="MemManage Exception Pending Bit" /> + <BitField name="USGFAULTPENDED" start="12" size="1" description="UsageFault Exception Pending Bit" /> + <BitField name="SYSTICKACT" start="11" size="1" description="SysTick Exception Active Bit" /> + <BitField name="PENDSVACT" start="10" size="1" description="PendSV Exception Active Bit" /> + <BitField name="MONITORACT" start="8" size="1" description="Debug Monitor Active Bit" /> + <BitField name="SVCALLACT" start="7" size="1" description="SVCall Active Bit" /> + <BitField name="USGFAULTACT" start="3" size="1" description="UsageFault Exception Active Bit" /> + <BitField name="BUSFAULTACT" start="1" size="1" description="BusFault Exception Active Bit" /> + <BitField name="MEMFAULTACT" start="0" size="1" description="MemManage Exception Active Bit" /> + </Register> + <Register name="MMSR" start="0xE000ED28" size="1" description="MemManage Fault Status Register"> + <BitField name="MMARVALID" start="7" size="1" description="MemManage Fault Address Register(MMFAR) valid flag" /> + <BitField name="MSTKERR" start="4" size="1" description="MemManage fault on stacking for exception entry" /> + <BitField name="MUNSTKERR" start="3" size="1" description="MemManage fault on unstacking for a return from exception" /> + <BitField name="DACCVIOL" start="1" size="1" description="Data access violation flag" /> + <BitField name="IACCVIOL" start="0" size="1" description="Instruction access violation flag" /> + </Register> + <Register name="BFSR" start="0xE000ED29" size="1" description="BusFault Status Register"> + <BitField name="BFARVALID" start="7" size="1" description="BusFault Address Register(BFAR) valid flag" /> + <BitField name="STKERR" start="4" size="1" description="BusFault on stacking for exception entry" /> + <BitField name="UNSTKERR" start="3" size="1" description="BusFault on unstacking for a return from exception" /> + <BitField name="IMPRECISERR" start="2" size="1" description="Imprecise data bus error" /> + <BitField name="PRECISERR" start="1" size="1" description="Precise data bus error" /> + <BitField name="IBUSERR" start="0" size="1" description="Instruction bus error" /> + </Register> + <Register name="UFSR" start="0xE000ED2A" size="2" description="UsageFault Status Register"> + <BitField name="DIVBYZERO" start="9" size="1" description="Divide by zero UsageFault" /> + <BitField name="UNALIGNED" start="8" size="1" description="Unaligned access UsageFault" /> + <BitField name="NOCP" start="3" size="1" description="No coprocessor UsageFault" /> + <BitField name="INVPC" start="2" size="1" description="Invalid PC load UsageFault, causedby an invalid PC load by EXC_RETURN" /> + <BitField name="INVSTATE" start="1" size="1" description="Invalid state UsageFault" /> + <BitField name="UNDEFINSTR" start="0" size="1" description="Undefined instruction UsageFault" /> + </Register> + <Register name="HFSR" start="0xE000ED2C" description="HardFault Status Register"> + <BitField name="DEBUGEVT" start="31" size="1" description="" /> + <BitField name="FORCED" start="30" size="1" description="Indicates a forced hard fault, generated by escalation of a fault with configurable priority that cannot be handled, either because of priority or because it is disabled" /> + <BitField name="VECTTBL" start="1" size="1" description="Indicates a BusFault on a vectortable read during exception processing" /> + </Register> + <Register name="MMAR" start="0xE000ED34" description="MemManage Fault Address Register"> + <BitField name="ADDRESS" start="0" size="32" description="When the MMARVALID bit of the MMFSR is set to 1, this field holds the address of the location that generated the MemManage fault" /> + </Register> + <Register name="BFAR" start="0xE000ED38" description="BusFault Address Register"> + <BitField name="ADDRESS" start="0" size="32" description="When the BFARVALID bit of the BFSR is set to1, this field holds the address of the location that generated the BusFault" /> + </Register> + <Register name="AFSR" start="0xE000ED3C" description="Auxiliary Fault Status Register"> + <BitField name="IMPDEF" start="0" size="32" description="Implementation defined, the bits map to the AUXFAULT input signals" /> + </Register> + </RegisterGroup> + <RegisterGroup name="MPU" start="0xE000ED90" description="Memory Protection Unit"> + <Register name="MPU_TYPE" start="0xE000ED90" access="ReadOnly" description="MPU Type Register"> + <BitField name="IREGION" start="16" size="8" description="Number of supported MPU instruction regions" /> + <BitField name="DREGION" start="8" size="8" description="Number of supported MPU data regions" /> + <BitField name="SEPARATE" start="0" size="1" description="Support for unified or separate instruction and date memory maps" /> + </Register> + <Register name="MPU_CTRL" start="0xE000ED94" description="MPU Control Register"> + <BitField name="PRIVDEFENA" start="2" size="1" description="Enables privileged software access to the default memory map" /> + <BitField name="HFNMIENA" start="1" size="1" description="Enable the operation of MPU during hard fault, NMI, and FAULTMASK handlers" /> + <BitField name="ENABLE" start="0" size="1" description="Enable MPU" /> + </Register> + <Register name="MPU_RNR" start="0xE000ED98" description="MPU Region Number Register"> + <BitField name="REGION" start="0" size="8" description="Indicates the MPU region referenced by the MPU_RBAR and MPU_RASR registers" /> + </Register> + <Register name="MPU_RBAR" start="0xE000ED9C" description="MPU Region Base Address Register"> + <BitField name="ADDR" start="5" size="27" description="Region base address field" /> + <BitField name="VALID" start="4" size="1" description="MPU Region Number valid bit" /> + <BitField name="REGION" start="0" size="4" description="MPU region field" /> + </Register> + <Register name="MPU_RASR" start="0xE000EDA0" description="MPU Region Attribute and Size Register"> + <BitField name="XN" start="28" size="1" description="Instruction access disable bit" /> + <BitField name="AP" start="24" size="3" description="Access permission field" /> + <BitField name="TEX" start="19" size="3" description="Memory access attribute" /> + <BitField name="S" start="18" size="1" description="Shareable bit" /> + <BitField name="C" start="17" size="1" description="Memory access attribute" /> + <BitField name="B" start="16" size="1" description="Memory access attribute" /> + <BitField name="SRD" start="8" size="8" description="Subregion disable bits" /> + <BitField name="SIZE" start="1" size="5" description="MPU protection region size" /> + <BitField name="ENABLE" start="0" size="1" description="Region enable bit" /> + </Register> + </RegisterGroup> +</Processor> diff --git a/examples/device/cdc_msc_hid_freertos/ses/lpc175x_6x/LPC176x5x_Vectors.s b/examples/device/cdc_msc_hid_freertos/ses/lpc175x_6x/LPC176x5x_Vectors.s new file mode 100644 index 000000000..c5fae1310 --- /dev/null +++ b/examples/device/cdc_msc_hid_freertos/ses/lpc175x_6x/LPC176x5x_Vectors.s @@ -0,0 +1,418 @@ +/***************************************************************************** + * SEGGER Microcontroller GmbH & Co. KG * + * Solutions for real time microcontroller applications * + ***************************************************************************** + * * + * (c) 2015 SEGGER Microcontroller GmbH & Co. KG * + * * + * Internet: www.segger.com Support: [email protected] * + * * + *****************************************************************************/ + +/***************************************************************************** + * Preprocessor Definitions * + * ------------------------ * + * VECTORS_IN_RAM * + * * + * If defined, an area of RAM will large enough to store the vector table * + * will be reserved. * + * * + *****************************************************************************/ + + .syntax unified + .code 16 + + .section .init, "ax" + .align 0 + +/***************************************************************************** + * Default Exception Handlers * + *****************************************************************************/ + + .thumb_func + .weak NMI_Handler +NMI_Handler: + b . + + .thumb_func + .weak HardFault_Handler +HardFault_Handler: + b . + + .thumb_func + .weak SVC_Handler +SVC_Handler: + b . + + .thumb_func + .weak PendSV_Handler +PendSV_Handler: + b . + + .thumb_func + .weak SysTick_Handler +SysTick_Handler: + b . + + .thumb_func +Dummy_Handler: + b . + +#if defined(__OPTIMIZATION_SMALL) + + .weak WDT_IRQHandler + .thumb_set WDT_IRQHandler,Dummy_Handler + + .weak TIMER0_IRQHandler + .thumb_set TIMER0_IRQHandler,Dummy_Handler + + .weak TIMER1_IRQHandler + .thumb_set TIMER1_IRQHandler,Dummy_Handler + + .weak TIMER2_IRQHandler + .thumb_set TIMER2_IRQHandler,Dummy_Handler + + .weak TIMER3_IRQHandler + .thumb_set TIMER3_IRQHandler,Dummy_Handler + + .weak UART0_IRQHandler + .thumb_set UART0_IRQHandler,Dummy_Handler + + .weak UART1_IRQHandler + .thumb_set UART1_IRQHandler,Dummy_Handler + + .weak UART2_IRQHandler + .thumb_set UART2_IRQHandler,Dummy_Handler + + .weak UART3_IRQHandler + .thumb_set UART3_IRQHandler,Dummy_Handler + + .weak PWM1_IRQHandler + .thumb_set PWM1_IRQHandler,Dummy_Handler + + .weak I2C0_IRQHandler + .thumb_set I2C0_IRQHandler,Dummy_Handler + + .weak I2C1_IRQHandler + .thumb_set I2C1_IRQHandler,Dummy_Handler + + .weak I2C2_IRQHandler + .thumb_set I2C2_IRQHandler,Dummy_Handler + + .weak SPI_IRQHandler + .thumb_set SPI_IRQHandler,Dummy_Handler + + .weak SSP0_IRQHandler + .thumb_set SSP0_IRQHandler,Dummy_Handler + + .weak SSP1_IRQHandler + .thumb_set SSP1_IRQHandler,Dummy_Handler + + .weak PLL0_IRQHandler + .thumb_set PLL0_IRQHandler,Dummy_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Dummy_Handler + + .weak EINT0_IRQHandler + .thumb_set EINT0_IRQHandler,Dummy_Handler + + .weak EINT1_IRQHandler + .thumb_set EINT1_IRQHandler,Dummy_Handler + + .weak EINT2_IRQHandler + .thumb_set EINT2_IRQHandler,Dummy_Handler + + .weak EINT3_IRQHandler + .thumb_set EINT3_IRQHandler,Dummy_Handler + + .weak ADC_IRQHandler + .thumb_set ADC_IRQHandler,Dummy_Handler + + .weak BOD_IRQHandler + .thumb_set BOD_IRQHandler,Dummy_Handler + + .weak USB_IRQHandler + .thumb_set USB_IRQHandler,Dummy_Handler + + .weak CAN_IRQHandler + .thumb_set CAN_IRQHandler,Dummy_Handler + + .weak DMA_IRQHandler + .thumb_set DMA_IRQHandler,Dummy_Handler + + .weak I2S_IRQHandler + .thumb_set I2S_IRQHandler,Dummy_Handler + + .weak ENET_IRQHandler + .thumb_set ENET_IRQHandler,Dummy_Handler + + .weak RIT_IRQHandler + .thumb_set RIT_IRQHandler,Dummy_Handler + + .weak MCPWM_IRQHandler + .thumb_set MCPWM_IRQHandler,Dummy_Handler + + .weak QEI_IRQHandler + .thumb_set QEI_IRQHandler,Dummy_Handler + + .weak PLL1_IRQHandler + .thumb_set PLL1_IRQHandler,Dummy_Handler + + .weak USBActivity_IRQHandler + .thumb_set USBActivity_IRQHandler,Dummy_Handler + + .weak CANActivity_IRQHandler + .thumb_set CANActivity_IRQHandler,Dummy_Handler + +#else + + .thumb_func + .weak WDT_IRQHandler +WDT_IRQHandler: + b . + + .thumb_func + .weak TIMER0_IRQHandler +TIMER0_IRQHandler: + b . + + .thumb_func + .weak TIMER1_IRQHandler +TIMER1_IRQHandler: + b . + + .thumb_func + .weak TIMER2_IRQHandler +TIMER2_IRQHandler: + b . + + .thumb_func + .weak TIMER3_IRQHandler +TIMER3_IRQHandler: + b . + + .thumb_func + .weak UART0_IRQHandler +UART0_IRQHandler: + b . + + .thumb_func + .weak UART1_IRQHandler +UART1_IRQHandler: + b . + + .thumb_func + .weak UART2_IRQHandler +UART2_IRQHandler: + b . + + .thumb_func + .weak UART3_IRQHandler +UART3_IRQHandler: + b . + + .thumb_func + .weak PWM1_IRQHandler +PWM1_IRQHandler: + b . + + .thumb_func + .weak I2C0_IRQHandler +I2C0_IRQHandler: + b . + + .thumb_func + .weak I2C1_IRQHandler +I2C1_IRQHandler: + b . + + .thumb_func + .weak I2C2_IRQHandler +I2C2_IRQHandler: + b . + + .thumb_func + .weak SPI_IRQHandler +SPI_IRQHandler: + b . + + .thumb_func + .weak SSP0_IRQHandler +SSP0_IRQHandler: + b . + + .thumb_func + .weak SSP1_IRQHandler +SSP1_IRQHandler: + b . + + .thumb_func + .weak PLL0_IRQHandler +PLL0_IRQHandler: + b . + + .thumb_func + .weak RTC_IRQHandler +RTC_IRQHandler: + b . + + .thumb_func + .weak EINT0_IRQHandler +EINT0_IRQHandler: + b . + + .thumb_func + .weak EINT1_IRQHandler +EINT1_IRQHandler: + b . + + .thumb_func + .weak EINT2_IRQHandler +EINT2_IRQHandler: + b . + + .thumb_func + .weak EINT3_IRQHandler +EINT3_IRQHandler: + b . + + .thumb_func + .weak ADC_IRQHandler +ADC_IRQHandler: + b . + + .thumb_func + .weak BOD_IRQHandler +BOD_IRQHandler: + b . + + .thumb_func + .weak USB_IRQHandler +USB_IRQHandler: + b . + + .thumb_func + .weak CAN_IRQHandler +CAN_IRQHandler: + b . + + .thumb_func + .weak DMA_IRQHandler +DMA_IRQHandler: + b . + + .thumb_func + .weak I2S_IRQHandler +I2S_IRQHandler: + b . + + .thumb_func + .weak ENET_IRQHandler +ENET_IRQHandler: + b . + + .thumb_func + .weak RIT_IRQHandler +RIT_IRQHandler: + b . + + .thumb_func + .weak MCPWM_IRQHandler +MCPWM_IRQHandler: + b . + + .thumb_func + .weak QEI_IRQHandler +QEI_IRQHandler: + b . + + .thumb_func + .weak PLL1_IRQHandler +PLL1_IRQHandler: + b . + + .thumb_func + .weak USBActivity_IRQHandler +USBActivity_IRQHandler: + b . + + .thumb_func + .weak CANActivity_IRQHandler +CANActivity_IRQHandler: + b . + +#endif + +/***************************************************************************** + * Vector Table * + *****************************************************************************/ + + .section .vectors, "ax" + .align 0 + .global _vectors + .extern __stack_end__ + .extern Reset_Handler + +_vectors: + .word __stack_end__ + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word SVC_Handler + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word PendSV_Handler + .word SysTick_Handler + .word WDT_IRQHandler + .word TIMER0_IRQHandler + .word TIMER1_IRQHandler + .word TIMER2_IRQHandler + .word TIMER3_IRQHandler + .word UART0_IRQHandler + .word UART1_IRQHandler + .word UART2_IRQHandler + .word UART3_IRQHandler + .word PWM1_IRQHandler + .word I2C0_IRQHandler + .word I2C1_IRQHandler + .word I2C2_IRQHandler + .word SPI_IRQHandler + .word SSP0_IRQHandler + .word SSP1_IRQHandler + .word PLL0_IRQHandler + .word RTC_IRQHandler + .word EINT0_IRQHandler + .word EINT1_IRQHandler + .word EINT2_IRQHandler + .word EINT3_IRQHandler + .word ADC_IRQHandler + .word BOD_IRQHandler + .word USB_IRQHandler + .word CAN_IRQHandler + .word DMA_IRQHandler + .word I2S_IRQHandler + .word ENET_IRQHandler + .word RIT_IRQHandler + .word MCPWM_IRQHandler + .word QEI_IRQHandler + .word PLL1_IRQHandler + .word USBActivity_IRQHandler + .word CANActivity_IRQHandler +_vectors_end: + +#ifdef VECTORS_IN_RAM + .section .vectors_ram, "ax" + .align 0 + .global _vectors_ram + +_vectors_ram: + .space _vectors_end - _vectors, 0 +#endif diff --git a/examples/device/cdc_msc_hid_freertos/ses/lpc175x_6x/flash_placement.xml b/examples/device/cdc_msc_hid_freertos/ses/lpc175x_6x/flash_placement.xml new file mode 100644 index 000000000..79bedc537 --- /dev/null +++ b/examples/device/cdc_msc_hid_freertos/ses/lpc175x_6x/flash_placement.xml @@ -0,0 +1,37 @@ +<!DOCTYPE Linker_Placement_File> +<Root name="Flash Section Placement"> + <MemorySegment name="$(FLASH_NAME:FLASH)"> + <ProgramSection alignment="0x100" load="Yes" name=".vectors" start="$(FLASH_START:)" /> + <ProgramSection alignment="4" load="Yes" name=".init" /> + <ProgramSection alignment="4" load="Yes" name=".init_rodata" /> + <ProgramSection alignment="4" load="Yes" name=".text" /> + <ProgramSection alignment="4" load="Yes" name=".dtors" /> + <ProgramSection alignment="4" load="Yes" name=".ctors" /> + <ProgramSection alignment="4" load="Yes" name=".rodata" /> + <ProgramSection alignment="4" load="Yes" name=".ARM.exidx" address_symbol="__exidx_start" end_symbol="__exidx_end" /> + <ProgramSection alignment="4" load="Yes" runin=".fast_run" name=".fast" /> + <ProgramSection alignment="4" load="Yes" runin=".data_run" name=".data" /> + <ProgramSection alignment="4" load="Yes" runin=".tdata_run" name=".tdata" /> + </MemorySegment> + <MemorySegment name="$(RAM_NAME:RAM);SRAM"> + <ProgramSection alignment="0x100" load="No" name=".vectors_ram" start="$(RAM_START:$(SRAM_START:))" /> + <ProgramSection alignment="4" load="No" name=".fast_run" /> + <ProgramSection alignment="4" load="No" name=".data_run" /> + <ProgramSection alignment="4" load="No" name=".bss" /> + <ProgramSection alignment="4" load="No" name=".tbss" /> + <ProgramSection alignment="4" load="No" name=".tdata_run" /> + <ProgramSection alignment="4" load="No" name=".non_init" /> + <ProgramSection alignment="4" size="__HEAPSIZE__" load="No" name=".heap" /> + <ProgramSection alignment="8" size="__STACKSIZE__" load="No" place_from_segment_end="Yes" name=".stack" /> + <ProgramSection alignment="8" size="__STACKSIZE_PROCESS__" load="No" name=".stack_process" /> + </MemorySegment> + <MemorySegment name="$(FLASH2_NAME:FLASH2)"> + <ProgramSection alignment="4" load="Yes" name=".text2" /> + <ProgramSection alignment="4" load="Yes" name=".rodata2" /> + <ProgramSection alignment="4" load="Yes" runin=".data2_run" name=".data2" /> + </MemorySegment> + <MemorySegment name="$(RAM2_NAME:RAM2)"> + <ProgramSection alignment="4" load="No" name=".data2_run" /> + <ProgramSection alignment="4" load="No" name=".bss2" /> + </MemorySegment> +</Root> diff --git a/examples/device/cdc_msc_hid_freertos/ses/lpc175x_6x/lpc175x_6x.emProject b/examples/device/cdc_msc_hid_freertos/ses/lpc175x_6x/lpc175x_6x.emProject new file mode 100644 index 000000000..893d6b507 --- /dev/null +++ b/examples/device/cdc_msc_hid_freertos/ses/lpc175x_6x/lpc175x_6x.emProject @@ -0,0 +1,141 @@ +<!DOCTYPE CrossStudio_Project_File> +<solution Name="lpc175x_6x" target="8" version="2"> + <project Name="lpc175x_6x"> + <configuration + Name="Common" + Placement="Flash" + Target="LPC4357 Cortex-M4" + arm_architecture="v7M" + arm_core_type="Cortex-M3" + arm_endian="Little" + arm_fp_abi="Soft" + arm_fpu_type="None" + arm_interwork="No" + arm_linker_heap_size="1024" + arm_linker_process_stack_size="0" + arm_linker_stack_size="1024" + arm_simulator_memory_simulation_parameter="RX 00000000,00080000,FFFFFFFF;RWX 10000000,00008000,CDCDCDCD" + arm_target_debug_interface_type="ADIv5" + arm_target_device_name="LPC1769" + arm_target_interface_type="SWD" + build_treat_warnings_as_errors="No" + c_preprocessor_definitions="LPC175x_6x;__LPC1700_FAMILY;__LPC176x_SUBFAMILY;ARM_MATH_CM3;FLASH_PLACEMENT=1;BOARD_LPCXPRESSO1769;CFG_TUSB_MCU=OPT_MCU_LPC175X_6X" + c_user_include_directories=".;../../src;$(rootDir)/hw;$(rootDir)/src;$(lpcDir)/CMSIS_CORE_LPC17xx/inc;$(lpcDir)/LPC17xx_DriverLib/include;$(freertosDir)/Source/include;$(freertosDir)/Source/portable/GCC/ARM_CM3" + debug_register_definition_file="LPC176x5x_Registers.xml" + debug_target_connection="J-Link" + gcc_enable_all_warnings="Yes" + gcc_entry_point="Reset_Handler" + link_use_linker_script_file="No" + linker_memory_map_file="LPC1769_MemoryMap.xml" + linker_section_placement_file="flash_placement.xml" + linker_section_placements_segments="FLASH RX 0x00000000 0x00080000;RAM RWX 0x10000000 0x00008000" + macros="DeviceFamily=LPC1700;DeviceSubFamily=LPC176x;Target=LPC1769;Placement=Flash;rootDir=../../../../..;lpcDir=../../../../../hw/mcu/nxp/lpc175x_6x;freertosDir=../../../../../lib/FreeRTOS" + project_directory="" + project_type="Executable" + target_reset_script="Reset();" + target_script_file="$(ProjectDir)/LPC1700_Target.js" + target_trace_initialize_script="EnableTrace("$(TraceInterfaceType)")" /> + <folder + Name="tinyusb" + exclude="" + filter="*.c;*.h" + path="../../../../../src" + recurse="Yes" /> + <folder Name="hw"> + <folder Name="bsp"> + <file file_name="../../../../../hw/bsp/ansi_escape.h" /> + <file file_name="../../../../../hw/bsp/board.h" /> + <folder Name="lpcxpresso1769"> + <file file_name="../../../../../hw/bsp/lpcxpresso1769/board_lpcxpresso1769.c" /> + <file file_name="../../../../../hw/bsp/lpcxpresso1769/board_lpcxpresso1769.h" /> + </folder> + </folder> + <folder Name="mcu"> + <folder Name="nxp"> + <folder Name="lpc175x_6x"> + <folder Name="CMSIS_CORE_LPC17xx"> + <folder Name="inc"> + <file file_name="../../../../../hw/mcu/nxp/lpc175x_6x/CMSIS_CORE_LPC17xx/inc/LPC17xx.h" /> + <file file_name="../../../../../hw/mcu/nxp/lpc175x_6x/CMSIS_CORE_LPC17xx/inc/system_LPC17xx.h" /> + </folder> + <folder Name="src"> + <file file_name="../../../../../hw/mcu/nxp/lpc175x_6x/CMSIS_CORE_LPC17xx/src/system_LPC17xx.c" /> + </folder> + </folder> + <folder Name="LPC17xx_DriverLib"> + <folder Name="include" /> + <folder Name="source"> + <file file_name="../../../../../hw/mcu/nxp/lpc175x_6x/LPC17xx_DriverLib/source/lpc17xx_gpio.c" /> + <file file_name="../../../../../hw/mcu/nxp/lpc175x_6x/LPC17xx_DriverLib/source/lpc17xx_pinsel.c" /> + </folder> + </folder> + </folder> + </folder> + </folder> + </folder> + <configuration Name="Debug" build_treat_warnings_as_errors="Yes" /> + <folder + Name="src" + exclude="" + filter="*.c;*.h" + path="../../src" + recurse="Yes" /> + <folder Name="System Files"> + <file file_name="flash_placement.xml" /> + <file file_name="LPC1700_Startup.s" /> + <file file_name="LPC1700_Target.js" /> + <file file_name="LPC1769_MemoryMap.xml" /> + <file file_name="LPC176x5x_Registers.xml" /> + <file file_name="LPC176x5x_Vectors.s" /> + <file file_name="thumb_crt0.s" /> + </folder> + <folder + Name="segger_rtt" + exclude="" + filter="*.c;*.h" + path="../../../../../lib/segger_rtt" + recurse="No" /> + <folder Name="lib"> + <folder Name="FreeRTOS"> + <folder Name="Source"> + <folder Name="include"> + <file file_name="../../../../../lib/FreeRTOS/Source/include/croutine.h" /> + <file file_name="../../../../../lib/FreeRTOS/Source/include/deprecated_definitions.h" /> + <file file_name="../../../../../lib/FreeRTOS/Source/include/event_groups.h" /> + <file file_name="../../../../../lib/FreeRTOS/Source/include/FreeRTOS.h" /> + <file file_name="../../../../../lib/FreeRTOS/Source/include/list.h" /> + <file file_name="../../../../../lib/FreeRTOS/Source/include/message_buffer.h" /> + <file file_name="../../../../../lib/FreeRTOS/Source/include/mpu_prototypes.h" /> + <file file_name="../../../../../lib/FreeRTOS/Source/include/mpu_wrappers.h" /> + <file file_name="../../../../../lib/FreeRTOS/Source/include/portable.h" /> + <file file_name="../../../../../lib/FreeRTOS/Source/include/projdefs.h" /> + <file file_name="../../../../../lib/FreeRTOS/Source/include/queue.h" /> + <file file_name="../../../../../lib/FreeRTOS/Source/include/semphr.h" /> + <file file_name="../../../../../lib/FreeRTOS/Source/include/stack_macros.h" /> + <file file_name="../../../../../lib/FreeRTOS/Source/include/StackMacros.h" /> + <file file_name="../../../../../lib/FreeRTOS/Source/include/stream_buffer.h" /> + <file file_name="../../../../../lib/FreeRTOS/Source/include/task.h" /> + <file file_name="../../../../../lib/FreeRTOS/Source/include/timers.h" /> + </folder> + <folder Name="portable"> + <folder Name="GCC"> + <folder Name="ARM_CM3"> + <file file_name="../../../../../lib/FreeRTOS/Source/portable/GCC/ARM_CM3/port.c" /> + <file file_name="../../../../../lib/FreeRTOS/Source/portable/GCC/ARM_CM3/portmacro.h" /> + </folder> + </folder> + <folder Name="MemMang"> + <file file_name="../../../../../lib/FreeRTOS/Source/portable/MemMang/heap_4.c" /> + </folder> + </folder> + <file file_name="../../../../../lib/FreeRTOS/Source/list.c" /> + <file file_name="../../../../../lib/FreeRTOS/Source/queue.c" /> + <file file_name="../../../../../lib/FreeRTOS/Source/tasks.c" /> + <file file_name="../../../../../lib/FreeRTOS/Source/timers.c" /> + </folder> + <file file_name="../../../../../lib/FreeRTOS/freertos_hook.c" /> + </folder> + </folder> + </project> + <configuration Name="LPCXpresso 1769" /> +</solution> diff --git a/examples/device/cdc_msc_hid_freertos/ses/lpc175x_6x/thumb_crt0.s b/examples/device/cdc_msc_hid_freertos/ses/lpc175x_6x/thumb_crt0.s new file mode 100644 index 000000000..17f88e0ca --- /dev/null +++ b/examples/device/cdc_msc_hid_freertos/ses/lpc175x_6x/thumb_crt0.s @@ -0,0 +1,415 @@ +// ********************************************************************** +// * SEGGER Microcontroller GmbH * +// * The Embedded Experts * +// ********************************************************************** +// * * +// * (c) 2014 - 2018 SEGGER Microcontroller GmbH * +// * (c) 2001 - 2018 Rowley Associates Limited * +// * * +// * www.segger.com Support: [email protected] * +// * * +// ********************************************************************** +// * * +// * All rights reserved. * +// * * +// * Redistribution and use in source and binary forms, with or * +// * without modification, are permitted provided that the following * +// * conditions are met: * +// * * +// * - Redistributions of source code must retain the above copyright * +// * notice, this list of conditions and the following disclaimer. * +// * * +// * - Neither the name of SEGGER Microcontroller GmbH * +// * nor the names of its contributors may be used to endorse or * +// * promote products derived from this software without specific * +// * prior written permission. * +// * * +// * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND * +// * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, * +// * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * +// * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * +// * DISCLAIMED. * +// * IN NO EVENT SHALL SEGGER Microcontroller GmbH BE LIABLE FOR * +// * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * +// * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT * +// * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * +// * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF * +// * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * +// * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE * +// * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH * +// * DAMAGE. * +// * * +// ********************************************************************** +// +// +// Preprocessor Definitions +// ------------------------ +// APP_ENTRY_POINT +// +// Defines the application entry point function, if undefined this setting +// defaults to "main". +// +// INITIALIZE_STACK +// +// If defined, the contents of the stack will be initialized to a the +// value 0xCC. +// +// INITIALIZE_SECONDARY_SECTIONS +// +// If defined, the .data2, .text2, .rodata2 and .bss2 sections will be initialized. +// +// INITIALIZE_TCM_SECTIONS +// +// If defined, the .data_tcm, .text_tcm, .rodata_tcm and .bss_tcm sections +// will be initialized. +// +// INITIALIZE_USER_SECTIONS +// +// If defined, the function InitializeUserMemorySections will be called prior +// to entering main in order to allow the user to initialize any user defined +// memory sections. +// +// FULL_LIBRARY +// +// If defined then +// - argc, argv are setup by the debug_getargs. +// - the exit symbol is defined and executes on return from main. +// - the exit symbol calls destructors, atexit functions and then debug_exit. +// +// If not defined then +// - argc and argv are zero. +// - the exit symbol is defined, executes on return from main and loops +// + +#ifndef APP_ENTRY_POINT +#define APP_ENTRY_POINT main +#endif + +#ifndef ARGSSPACE +#define ARGSSPACE 128 +#endif + .syntax unified + + .global _start + .extern APP_ENTRY_POINT + .global exit + .weak exit + +#ifdef INITIALIZE_USER_SECTIONS + .extern InitializeUserMemorySections +#endif + + .section .init, "ax" + .code 16 + .balign 2 + .thumb_func + +_start: + /* Set up main stack if size > 0 */ + ldr r1, =__stack_end__ + ldr r0, =__stack_start__ + subs r2, r1, r0 + beq 1f +#ifdef __ARM_EABI__ + movs r2, #0x7 + bics r1, r2 +#endif + mov sp, r1 +#ifdef INITIALIZE_STACK + movs r2, #0xCC + ldr r0, =__stack_start__ + bl memory_set +#endif +1: + + /* Set up process stack if size > 0 */ + ldr r1, =__stack_process_end__ + ldr r0, =__stack_process_start__ + subs r2, r1, r0 + beq 1f +#ifdef __ARM_EABI__ + movs r2, #0x7 + bics r1, r2 +#endif + msr psp, r1 + movs r2, #2 + msr control, r2 +#ifdef INITIALIZE_STACK + movs r2, #0xCC + bl memory_set +#endif +1: + + /* Copy initialized memory sections into RAM (if necessary). */ + ldr r0, =__data_load_start__ + ldr r1, =__data_start__ + ldr r2, =__data_end__ + bl memory_copy + ldr r0, =__text_load_start__ + ldr r1, =__text_start__ + ldr r2, =__text_end__ + bl memory_copy + ldr r0, =__fast_load_start__ + ldr r1, =__fast_start__ + ldr r2, =__fast_end__ + bl memory_copy + ldr r0, =__ctors_load_start__ + ldr r1, =__ctors_start__ + ldr r2, =__ctors_end__ + bl memory_copy + ldr r0, =__dtors_load_start__ + ldr r1, =__dtors_start__ + ldr r2, =__dtors_end__ + bl memory_copy + ldr r0, =__rodata_load_start__ + ldr r1, =__rodata_start__ + ldr r2, =__rodata_end__ + bl memory_copy + ldr r0, =__tdata_load_start__ + ldr r1, =__tdata_start__ + ldr r2, =__tdata_end__ + bl memory_copy +#ifdef INITIALIZE_SECONDARY_SECTIONS + ldr r0, =__data2_load_start__ + ldr r1, =__data2_start__ + ldr r2, =__data2_end__ + bl memory_copy + ldr r0, =__text2_load_start__ + ldr r1, =__text2_start__ + ldr r2, =__text2_end__ + bl memory_copy + ldr r0, =__rodata2_load_start__ + ldr r1, =__rodata2_start__ + ldr r2, =__rodata2_end__ + bl memory_copy +#endif /* #ifdef INITIALIZE_SECONDARY_SECTIONS */ +#ifdef INITIALIZE_TCM_SECTIONS + ldr r0, =__data_tcm_load_start__ + ldr r1, =__data_tcm_start__ + ldr r2, =__data_tcm_end__ + bl memory_copy + ldr r0, =__text_tcm_load_start__ + ldr r1, =__text_tcm_start__ + ldr r2, =__text_tcm_end__ + bl memory_copy + ldr r0, =__rodata_tcm_load_start__ + ldr r1, =__rodata_tcm_start__ + ldr r2, =__rodata_tcm_end__ + bl memory_copy +#endif /* #ifdef INITIALIZE_TCM_SECTIONS */ + + /* Zero the bss. */ + ldr r0, =__bss_start__ + ldr r1, =__bss_end__ + movs r2, #0 + bl memory_set + ldr r0, =__tbss_start__ + ldr r1, =__tbss_end__ + movs r2, #0 + bl memory_set +#ifdef INITIALIZE_SECONDARY_SECTIONS + ldr r0, =__bss2_start__ + ldr r1, =__bss2_end__ + mov r2, #0 + bl memory_set +#endif /* #ifdef INITIALIZE_SECONDARY_SECTIONS */ +#ifdef INITIALIZE_TCM_SECTIONS + ldr r0, =__bss_tcm_start__ + ldr r1, =__bss_tcm_end__ + mov r2, #0 + bl memory_set +#endif /* #ifdef INITIALIZE_TCM_SECTIONS */ + + /* Initialize the heap */ + ldr r0, = __heap_start__ + ldr r1, = __heap_end__ + subs r1, r1, r0 + cmp r1, #8 + blt 1f + movs r2, #0 + str r2, [r0] + adds r0, r0, #4 + str r1, [r0] +1: + +#ifdef INITIALIZE_USER_SECTIONS + ldr r2, =InitializeUserMemorySections + blx r2 +#endif + + /* Call constructors */ + ldr r0, =__ctors_start__ + ldr r1, =__ctors_end__ +ctor_loop: + cmp r0, r1 + beq ctor_end + ldr r2, [r0] + adds r0, #4 + push {r0-r1} + blx r2 + pop {r0-r1} + b ctor_loop +ctor_end: + + /* Setup initial call frame */ + movs r0, #0 + mov lr, r0 + mov r12, sp + + .type start, function +start: + /* Jump to application entry point */ +#ifdef FULL_LIBRARY + movs r0, #ARGSSPACE + ldr r1, =args + ldr r2, =debug_getargs + blx r2 + ldr r1, =args +#else + movs r0, #0 + movs r1, #0 +#endif + ldr r2, =APP_ENTRY_POINT + blx r2 + + .thumb_func +exit: +#ifdef FULL_LIBRARY + mov r5, r0 // save the exit parameter/return result + + /* Call destructors */ + ldr r0, =__dtors_start__ + ldr r1, =__dtors_end__ +dtor_loop: + cmp r0, r1 + beq dtor_end + ldr r2, [r0] + add r0, #4 + push {r0-r1} + blx r2 + pop {r0-r1} + b dtor_loop +dtor_end: + + /* Call atexit functions */ + ldr r2, =_execute_at_exit_fns + blx r2 + + /* Call debug_exit with return result/exit parameter */ + mov r0, r5 + ldr r2, =debug_exit + blx r2 +#endif + + /* Returned from application entry point, loop forever. */ +exit_loop: + b exit_loop + + .thumb_func +memory_copy: + cmp r0, r1 + beq 2f + subs r2, r2, r1 + beq 2f +1: + ldrb r3, [r0] + adds r0, r0, #1 + strb r3, [r1] + adds r1, r1, #1 + subs r2, r2, #1 + bne 1b +2: + bx lr + + .thumb_func +memory_set: + cmp r0, r1 + beq 1f + strb r2, [r0] + adds r0, r0, #1 + b memory_set +1: + bx lr + + // default C/C++ library helpers + +.macro HELPER helper_name + .section .text.\helper_name, "ax", %progbits + .balign 2 + .global \helper_name + .weak \helper_name +\helper_name: + .thumb_func +.endm + +.macro JUMPTO name +#if defined(__thumb__) && !defined(__thumb2__) + mov r12, r0 + ldr r0, =\name + push {r0} + mov r0, r12 + pop {pc} +#else + b \name +#endif +.endm + +HELPER __aeabi_read_tp + ldr r0, =__tbss_start__-8 + bx lr +HELPER abort + b . +HELPER __assert + b . +HELPER __aeabi_assert + b . +HELPER __sync_synchronize + bx lr +HELPER __getchar + JUMPTO debug_getchar +HELPER __putchar + JUMPTO debug_putchar +HELPER __open + JUMPTO debug_fopen +HELPER __close + JUMPTO debug_fclose +HELPER __write + mov r3, r0 + mov r0, r1 + movs r1, #1 + JUMPTO debug_fwrite +HELPER __read + mov r3, r0 + mov r0, r1 + movs r1, #1 + JUMPTO debug_fread +HELPER __seek + push {r4, lr} + mov r4, r0 + bl debug_fseek + cmp r0, #0 + bne 1f + mov r0, r4 + bl debug_ftell + pop {r4, pc} +1: + ldr r0, =-1 + pop {r4, pc} + // char __user_locale_name_buffer[]; + .section .bss.__user_locale_name_buffer, "aw", %nobits + .global __user_locale_name_buffer + .weak __user_locale_name_buffer + __user_locale_name_buffer: + .word 0x0 + +#ifdef FULL_LIBRARY + .bss +args: + .space ARGSSPACE +#endif + + /* Setup attibutes of stack and heap sections so they don't take up room in the elf file */ + .section .stack, "wa", %nobits + .section .stack_process, "wa", %nobits + .section .heap, "wa", %nobits + diff --git a/examples/device/cdc_msc_hid_freertos/ses/nrf5x/FreeRTOSConfig.h b/examples/device/cdc_msc_hid_freertos/ses/nrf5x/FreeRTOSConfig.h index 96de8f8c5..26df38d3d 100644 --- a/examples/device/cdc_msc_hid_freertos/ses/nrf5x/FreeRTOSConfig.h +++ b/examples/device/cdc_msc_hid_freertos/ses/nrf5x/FreeRTOSConfig.h @@ -137,8 +137,7 @@ #error "This port requires __NVIC_PRIO_BITS to be defined" #endif -/* The lowest interrupt priority that can be used in a call to a "set priority" -function. */ +/* The lowest interrupt priority that can be used in a call to a "set priority" function. */ #define configLIBRARY_LOWEST_INTERRUPT_PRIORITY ((1<<configPRIO_BITS) - 1) /* The highest interrupt priority that can be used by any interrupt service diff --git a/examples/device/cdc_msc_hid_freertos/ses/nrf5x/nrf5x.emProject b/examples/device/cdc_msc_hid_freertos/ses/nrf5x/nrf5x.emProject index 4bfbe6467..ea4950682 100644 --- a/examples/device/cdc_msc_hid_freertos/ses/nrf5x/nrf5x.emProject +++ b/examples/device/cdc_msc_hid_freertos/ses/nrf5x/nrf5x.emProject @@ -18,11 +18,12 @@ arm_target_debug_interface_type="ADIv5" arm_target_device_name="nRF52840_xxAA" arm_target_interface_type="SWD" - build_treat_warnings_as_errors="Yes" + build_treat_warnings_as_errors="No" c_preprocessor_definitions="NRF52840_XXAA;__nRF_FAMILY;ARM_MATH_CM4;FLASH_PLACEMENT=1;BOARD_PCA10056;CFG_TUSB_MCU=OPT_MCU_NRF5X" c_user_include_directories="./;../../src;$(rootDir)/hw/cmsis/Include;$(rootDir)/hw;$(rootDir)/src;$(nrfxDir)/..;$(nrfxDir);$(nrfxDir)/mdk;$(nrfxDir)/hal;$(nrfxDir)/drivers/include;$(freertosDir)/Source/include;$(freertosDir)/Source/portable/GCC/ARM_CM4F" debug_register_definition_file="nrf52840_Registers.xml" debug_target_connection="J-Link" + gcc_enable_all_warnings="Yes" gcc_entry_point="Reset_Handler" link_use_linker_script_file="No" linker_memory_map_file="nRF52840_xxAA_MemoryMap.xml" @@ -127,7 +128,6 @@ <file file_name="../../../../../lib/FreeRTOS/Source/include/timers.h" /> </folder> <folder Name="portable"> - <folder Name="Common" /> <folder Name="GCC"> <folder Name="ARM_CM4F"> <file file_name="../../../../../lib/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.c" /> diff --git a/examples/device/cdc_msc_hid_freertos/ses/samd21/samd21.emProject b/examples/device/cdc_msc_hid_freertos/ses/samd21/samd21.emProject index 2ae0d66a1..07e902645 100644 --- a/examples/device/cdc_msc_hid_freertos/ses/samd21/samd21.emProject +++ b/examples/device/cdc_msc_hid_freertos/ses/samd21/samd21.emProject @@ -19,7 +19,7 @@ arm_target_interface_type="SWD" build_treat_warnings_as_errors="Yes" c_preprocessor_definitions="__SAMD21G18A__;__SAMD21_FAMILY;__SAM_D21_SUBFAMILY;ARM_MATH_CM0PLUS;FLASH_PLACEMENT=1;USE_SIMPLE_ASSERT;CONF_XOSC32K_CONFIG=1;CONF_OSC32K_ENABLE=1;CONF_OSC32K_EN32K=1;CONF_XOSC32K_STARTUP=CONF_XOSC32K_STARTUP_TIME_2000092MCS;CONF_DFLL_ONDEMAND=0;CONF_DFLL_OVERWRITE_CALIBRATION=0;BOARD_METRO_M0_EXPRESS;CFG_TUSB_MCU=OPT_MCU_SAMD21" - c_user_include_directories="./;../../src;$(rootDir)/hw/cmsis/Include;$(rootDir)/hw;$(rootDir)/src;$(asf4Dir);$(asf4Dir)/include;$(asf4Dir)/config;$(asf4Dir)/hri;$(asf4Dir)/hal/include;$(asf4Dir)/hal/utils/include;$(asf4Dir)/hpl/port;$(asf4Dir)/hpl/gclk;$(asf4Dir)/hpl/pm;$(freertosDir)/Source/include;$(freertosDir)/Source/portable/GCC/ARM_CM0" + c_user_include_directories="./;../../src;$(rootDir)/hw;$(rootDir)/src;$(asf4Dir);$(asf4Dir)/CMSIS/Include;$(asf4Dir)/include;$(asf4Dir)/config;$(asf4Dir)/hri;$(asf4Dir)/hal/include;$(asf4Dir)/hal/utils/include;$(asf4Dir)/hpl/port;$(asf4Dir)/hpl/gclk;$(asf4Dir)/hpl/pm;$(freertosDir)/Source/include;$(freertosDir)/Source/portable/GCC/ARM_CM0" debug_register_definition_file="ATSAMD21G18A_Registers.xml" debug_target_connection="J-Link" gcc_entry_point="Reset_Handler" @@ -121,7 +121,6 @@ <file file_name="../../../../../lib/FreeRTOS/Source/include/timers.h" /> </folder> <folder Name="portable"> - <folder Name="Common" /> <folder Name="GCC"> <folder Name="ARM_CM0"> <file file_name="../../../../../lib/FreeRTOS/Source/portable/GCC/ARM_CM0/port.c" /> @@ -137,7 +136,6 @@ <file file_name="../../../../../lib/FreeRTOS/Source/tasks.c" /> <file file_name="../../../../../lib/FreeRTOS/Source/timers.c" /> </folder> - <file file_name="../../../../../lib/FreeRTOS/FreeRTOSConfig.h" /> <file file_name="../../../../../lib/FreeRTOS/freertos_hook.c" /> </folder> </folder> diff --git a/examples/device/cdc_msc_hid_freertos/ses/samd51/samd51.emProject b/examples/device/cdc_msc_hid_freertos/ses/samd51/samd51.emProject index b08ad276d..81758d177 100644 --- a/examples/device/cdc_msc_hid_freertos/ses/samd51/samd51.emProject +++ b/examples/device/cdc_msc_hid_freertos/ses/samd51/samd51.emProject @@ -20,7 +20,7 @@ arm_target_interface_type="SWD" build_treat_warnings_as_errors="Yes" c_preprocessor_definitions="__SAMD51_FAMILY;__SAMD51J19A__;ARM_MATH_CM4;FLASH_PLACEMENT=1;USE_SIMPLE_ASSERT;BOARD_METRO_M4_EXPRESS;CFG_TUSB_MCU=OPT_MCU_SAMD51" - c_user_include_directories="./;../../src;$(rootDir)/hw/cmsis/Include;$(rootDir)/hw;$(rootDir)/src;$(asf4Dir);$(asf4Dir)/include;$(asf4Dir)/config;$(asf4Dir)/hri;$(asf4Dir)/hal/include;$(asf4Dir)/hal/utils/include;$(asf4Dir)/hpl/port;$(asf4Dir)/hpl/gclk;$(freertosDir)/Source/include;$(freertosDir)/Source/portable/GCC/ARM_CM4F" + c_user_include_directories="./;../../src;$(rootDir)/hw;$(rootDir)/src;$(asf4Dir);$(asf4Dir)/CMSIS/Include;$(asf4Dir)/include;$(asf4Dir)/config;$(asf4Dir)/hri;$(asf4Dir)/hal/include;$(asf4Dir)/hal/utils/include;$(asf4Dir)/hpl/port;$(asf4Dir)/hpl/gclk;$(freertosDir)/Source/include;$(freertosDir)/Source/portable/GCC/ARM_CM4F" debug_register_definition_file="ATSAMD51J19A_Registers.xml" debug_target_connection="J-Link" gcc_entry_point="Reset_Handler" @@ -125,7 +125,6 @@ <file file_name="../../../../../lib/FreeRTOS/Source/include/timers.h" /> </folder> <folder Name="portable"> - <folder Name="Common" /> <folder Name="GCC"> <folder Name="ARM_CM4F"> <file file_name="../../../../../lib/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.c" /> @@ -141,7 +140,6 @@ <file file_name="../../../../../lib/FreeRTOS/Source/tasks.c" /> <file file_name="../../../../../lib/FreeRTOS/Source/timers.c" /> </folder> - <file file_name="../../../../../lib/FreeRTOS/FreeRTOSConfig.h" /> <file file_name="../../../../../lib/FreeRTOS/freertos_hook.c" /> </folder> </folder> diff --git a/examples/device/cdc_msc_hid_freertos/src/main.c b/examples/device/cdc_msc_hid_freertos/src/main.c index d5a5d0c2c..946972c16 100644 --- a/examples/device/cdc_msc_hid_freertos/src/main.c +++ b/examples/device/cdc_msc_hid_freertos/src/main.c @@ -59,14 +59,13 @@ //--------------------------------------------------------------------+ // INTERNAL OBJECT & FUNCTION DECLARATION //--------------------------------------------------------------------+ -void print_greeting(void); void led_blinky_cb(TimerHandle_t xTimer); +void usb_device_task(void* param); /*------------- MAIN -------------*/ int main(void) { board_init(); - print_greeting(); // soft timer for blinky TimerHandle_t tm_hdl = xTimerCreate(NULL, pdMS_TO_TICKS(1000), true, NULL, led_blinky_cb); @@ -74,10 +73,13 @@ int main(void) tusb_init(); + // Create a task for tinyusb device stack + xTaskCreate( usb_device_task, "usbd", 150, NULL, configMAX_PRIORITIES-1, NULL); + // Create task #if CFG_TUD_CDC extern void cdc_task(void* params); - xTaskCreate( cdc_task, "cdc", 256, NULL, 2, NULL); + xTaskCreate( cdc_task, "cdc", 256, NULL, configMAX_PRIORITIES-2, NULL); #endif #if CFG_TUD_HID @@ -90,6 +92,20 @@ int main(void) return 0; } +// USB Device Driver task +// This top level thread process all usb events and invoke callbacks +void usb_device_task(void* param) +{ + (void) param; + + // RTOS forever loop + while (1) + { + // tinyusb device task + tud_task(); + } +} + //--------------------------------------------------------------------+ // USB CDC //--------------------------------------------------------------------+ @@ -98,11 +114,12 @@ void cdc_task(void* params) { (void) params; + // RTOS forever loop while ( 1 ) { - // connected and there are data available if ( tud_cdc_connected() ) { + // connected and there are data available if ( tud_cdc_available() ) { uint8_t buf[64]; @@ -110,10 +127,15 @@ void cdc_task(void* params) // read and echo back uint32_t count = tud_cdc_read(buf, sizeof(buf)); - tud_cdc_write(buf, count); - } + for(uint32_t i=0; i<count; i++) + { + tud_cdc_write_char(buf[i]); - tud_cdc_write_flush(); + if ( buf[i] == '\r' ) tud_cdc_write_char('\n'); + } + + tud_cdc_write_flush(); + } } } } @@ -125,8 +147,8 @@ void tud_cdc_line_state_cb(uint8_t itf, bool dtr, bool rts) // connected if ( dtr && rts ) { - // print greeting - tud_cdc_write_str("tinyusb usb cdc\n"); + // print initial message when connected + tud_cdc_write_str("\r\nTinyUSB CDC MSC HID device with FreeRTOS example\r\n"); } } #endif @@ -206,6 +228,7 @@ void tud_umount_cb(void) void tud_cdc_rx_cb(uint8_t itf) { + (void) itf; } //--------------------------------------------------------------------+ @@ -216,31 +239,6 @@ void led_blinky_cb(TimerHandle_t xTimer) (void) xTimer; static bool led_state = false; - board_led_control(BOARD_LED0, led_state); + board_led_control(led_state); led_state = 1 - led_state; // toggle } - -//--------------------------------------------------------------------+ -// HELPER FUNCTION -//--------------------------------------------------------------------+ -void print_greeting(void) -{ - char const * const rtos_name[] = - { - [OPT_OS_NONE] = "None", - [OPT_OS_FREERTOS] = "FreeRTOS", - }; - - printf("\n--------------------------------------------------------------------\n"); - printf("- Device Demo (a tinyusb example)\n"); - printf("- if you find any bugs or get any questions, feel free to file an\n"); - printf("- issue at https://github.com/hathach/tinyusb\n"); - printf("--------------------------------------------------------------------\n\n"); - - printf("This DEVICE demo is configured to support:"); - printf(" - RTOS = %s\n", rtos_name[CFG_TUSB_OS]); - if (CFG_TUD_CDC ) puts(" - Communication Device Class"); - if (CFG_TUD_MSC ) puts(" - Mass Storage"); - if (CFG_TUD_HID_KEYBOARD ) puts(" - HID Keyboard"); - if (CFG_TUD_HID_MOUSE ) puts(" - HID Mouse"); -} diff --git a/examples/device/cdc_msc_hid_freertos/src/msc_disk_ram.c b/examples/device/cdc_msc_hid_freertos/src/msc_disk_ram.c index 5e2f5e6be..03a87043c 100644 --- a/examples/device/cdc_msc_hid_freertos/src/msc_disk_ram.c +++ b/examples/device/cdc_msc_hid_freertos/src/msc_disk_ram.c @@ -41,6 +41,12 @@ #if CFG_TUD_MSC +// Some MCU doesn't have enough 8KB SRAM to store the whole disk +// We will use Flash as read-only disk +#if CFG_TUSB_MCU == OPT_MCU_LPC13XX +#define DISK_READONLY +#endif + #define README_CONTENTS \ "This is tinyusb's MassStorage Class demo.\r\n\r\n\ If you find any bugs or get any questions, feel free to file an\r\n\ @@ -52,7 +58,10 @@ enum DISK_BLOCK_SIZE = 512 }; -uint8_t msc_device_ramdisk[DISK_BLOCK_NUM][DISK_BLOCK_SIZE] = +#ifdef DISK_READONLY +const +#endif +static uint8_t msc_disk[DISK_BLOCK_NUM][DISK_BLOCK_SIZE] = { //------------- Boot Sector -------------// // byte_per_sector = DISK_BLOCK_SIZE; fat12_sector_num_16 = DISK_BLOCK_NUM; @@ -97,7 +106,9 @@ uint8_t msc_device_ramdisk[DISK_BLOCK_NUM][DISK_BLOCK_SIZE] = // Copy disk's data to buffer (up to bufsize) and return number of copied bytes. int32_t tud_msc_read10_cb(uint8_t lun, uint32_t lba, uint32_t offset, void* buffer, uint32_t bufsize) { - uint8_t* addr = msc_device_ramdisk[lba] + offset; + (void) lun; + + uint8_t* addr = msc_disk[lba] + offset; memcpy(buffer, addr, bufsize); return bufsize; @@ -107,14 +118,20 @@ int32_t tud_msc_read10_cb(uint8_t lun, uint32_t lba, uint32_t offset, void* buff // Process data in buffer to disk's storage and return number of written bytes int32_t tud_msc_write10_cb(uint8_t lun, uint32_t lba, uint32_t offset, uint8_t* buffer, uint32_t bufsize) { - uint8_t* addr = msc_device_ramdisk[lba] + offset; + (void) lun; + +#ifndef DISK_READONLY + uint8_t* addr = msc_disk[lba] + offset; memcpy(addr, buffer, bufsize); +#endif return bufsize; } void tud_msc_capacity_cb(uint8_t lun, uint32_t* block_count, uint16_t* block_size) { + (void) lun; + *block_count = DISK_BLOCK_NUM; *block_size = DISK_BLOCK_SIZE; } diff --git a/examples/device/cdc_msc_hid_freertos/src/tusb_config.h b/examples/device/cdc_msc_hid_freertos/src/tusb_config.h index 777930ba3..c35526d7e 100644 --- a/examples/device/cdc_msc_hid_freertos/src/tusb_config.h +++ b/examples/device/cdc_msc_hid_freertos/src/tusb_config.h @@ -39,8 +39,6 @@ #ifndef _TUSB_CONFIG_H_ #define _TUSB_CONFIG_H_ -#include "bsp/board.h" - #ifdef __cplusplus extern "C" { #endif @@ -48,20 +46,30 @@ //-------------------------------------------------------------------- // COMMON CONFIGURATION //-------------------------------------------------------------------- + // defined by compiler flags for flexibility #ifndef CFG_TUSB_MCU - #error CFG_TUSB_MCU should be defined using compiler flags + #error CFG_TUSB_MCU must be defined #endif #define CFG_TUSB_RHPORT0_MODE OPT_MODE_DEVICE - +#define CFG_TUSB_OS OPT_OS_FREERTOS #define CFG_TUSB_DEBUG 2 -/*------------- RTOS -------------*/ -#define CFG_TUSB_OS OPT_OS_FREERTOS -#define CFG_TUD_TASK_PRIO (configMAX_PRIORITIES-1) -//#define CFG_TUD_TASK_QUEUE_SZ 16 -//#define CFG_TUD_TASK_STACK_SZ 150 +/* USB DMA on some MCUs can only access a specific SRAM region with restriction on alignment. + * Tinyusb use follows macros to declare transferring memory so that they can be put + * into those specific section. + * e.g + * - CFG_TUSB_MEM SECTION : __attribute__ (( section(".usb_ram") )) + * - CFG_TUSB_MEM_ALIGN : __attribute__ ((aligned(4))) + */ +#ifndef CFG_TUSB_MEM_SECTION +#define CFG_TUSB_MEM_SECTION +#endif + +#ifndef CFG_TUSB_MEM_ALIGN +#define CFG_TUSB_MEM_ALIGN ATTR_ALIGNED(4) +#endif //-------------------------------------------------------------------- // DEVICE CONFIGURATION @@ -78,12 +86,23 @@ */ #define CFG_TUD_DESC_AUTO 1 -/* USB VID/PID if not defined, tinyusb to use default value +/* If USB VID/PID is not defined, tinyusb will use default value * Note: different class combination e.g CDC and (CDC + MSC) should have different * PID since Host OS will "remembered" device driver after the first plug */ // #define CFG_TUD_DESC_VID 0xCAFE // #define CFG_TUD_DESC_PID 0x0001 +// LPC175x_6x's endpoint type (bulk/interrupt/iso) are fixed by its number +// Therefor we need to force endpoint number to correct type on lpc17xx +#if CFG_TUSB_MCU == OPT_MCU_LPC175X_6X +#define CFG_TUD_DESC_CDC_EPNUM_NOTIF 1 +#define CFG_TUD_DESC_CDC_EPNUM 2 +#define CFG_TUD_DESC_MSC_EPNUM 5 +#define CFG_TUD_DESC_HID_KEYBOARD_EPNUM 4 +#define CFG_TUD_DESC_HID_MOUSE_EPNUM 7 +#endif + + //------------- CLASS -------------// #define CFG_TUD_CDC 1 #define CFG_TUD_MSC 1 @@ -137,13 +156,6 @@ */ #define CFG_TUD_HID_ASCII_TO_KEYCODE_LOOKUP 1 -//-------------------------------------------------------------------- -// USB RAM PLACEMENT -//-------------------------------------------------------------------- -#define CFG_TUSB_MEM_SECTION -#define CFG_TUSB_MEM_ALIGN ATTR_ALIGNED(4) - - #ifdef __cplusplus } #endif diff --git a/examples/device/device_virtual_com/segger/SEGGER_RTT.c b/examples/device/device_virtual_com/segger/SEGGER_RTT.c deleted file mode 100644 index aee5bd21e..000000000 --- a/examples/device/device_virtual_com/segger/SEGGER_RTT.c +++ /dev/null @@ -1,1329 +0,0 @@ -/********************************************************************* -* SEGGER MICROCONTROLLER GmbH & Co. KG * -* Solutions for real time microcontroller applications * -********************************************************************** -* * -* (c) 2014 - 2016 SEGGER Microcontroller GmbH & Co. KG * -* * -* www.segger.com Support: [email protected] * -* * -********************************************************************** -* * -* SEGGER RTT * Real Time Transfer for embedded targets * -* * -********************************************************************** -* * -* All rights reserved. * -* * -* * This software may in its unmodified form be freely redistributed * -* in source form. * -* * The source code may be modified, provided the source code * -* retains the above copyright notice, this list of conditions and * -* the following disclaimer. * -* * Modified versions of this software in source or linkable form * -* may not be distributed without prior consent of SEGGER. * -* * This software may only be used for communication with SEGGER * -* J-Link debug probes. * -* * -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND * -* CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, * -* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * -* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * -* DISCLAIMED. IN NO EVENT SHALL SEGGER Microcontroller BE LIABLE FOR * -* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT * -* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * -* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF * -* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE * -* USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH * -* DAMAGE. * -* * -********************************************************************** -* * -* RTT version: 5.12e * -* * -********************************************************************** ----------------------------END-OF-HEADER------------------------------ -File : SEGGER_RTT.c -Purpose : Implementation of SEGGER real-time transfer (RTT) which - allows real-time communication on targets which support - debugger memory accesses while the CPU is running. - -Additional information: - Type "int" is assumed to be 32-bits in size - H->T Host to target communication - T->H Target to host communication - - RTT channel 0 is always present and reserved for Terminal usage. - Name is fixed to "Terminal" - - Effective buffer size: SizeOfBuffer - 1 - - WrOff == RdOff: Buffer is empty - WrOff == (RdOff - 1): Buffer is full - WrOff > RdOff: Free space includes wrap-around - WrOff < RdOff: Used space includes wrap-around - (WrOff == (SizeOfBuffer - 1)) && (RdOff == 0): - Buffer full and wrap-around after next byte - - ----------------------------------------------------------------------- -*/ - -#include "SEGGER_RTT.h" - -#include <string.h> // for memcpy - -/********************************************************************* -* -* Configuration, default values -* -********************************************************************** -*/ - -#ifndef BUFFER_SIZE_UP - #define BUFFER_SIZE_UP 1024 // Size of the buffer for terminal output of target, up to host -#endif - -#ifndef BUFFER_SIZE_DOWN - #define BUFFER_SIZE_DOWN 16 // Size of the buffer for terminal input to target from host (Usually keyboard input) -#endif - -#ifndef SEGGER_RTT_MAX_NUM_UP_BUFFERS - #define SEGGER_RTT_MAX_NUM_UP_BUFFERS 2 // Number of up-buffers (T->H) available on this target -#endif - -#ifndef SEGGER_RTT_MAX_NUM_DOWN_BUFFERS - #define SEGGER_RTT_MAX_NUM_DOWN_BUFFERS 2 // Number of down-buffers (H->T) available on this target -#endif - -#ifndef SEGGER_RTT_BUFFER_SECTION - #if defined SEGGER_RTT_SECTION - #define SEGGER_RTT_BUFFER_SECTION SEGGER_RTT_SECTION - #endif -#endif - -#ifndef SEGGER_RTT_MODE_DEFAULT - #define SEGGER_RTT_MODE_DEFAULT SEGGER_RTT_MODE_NO_BLOCK_SKIP -#endif - -#ifndef SEGGER_RTT_LOCK - #define SEGGER_RTT_LOCK() -#endif - -#ifndef SEGGER_RTT_UNLOCK - #define SEGGER_RTT_UNLOCK() -#endif - -#ifndef STRLEN - #define STRLEN(a) strlen((a)) -#endif - -#ifndef MEMCPY - #define MEMCPY(pDest, pSrc, NumBytes) memcpy((pDest), (pSrc), (NumBytes)) -#endif - -#ifndef MIN - #define MIN(a, b) (((a) < (b)) ? (a) : (b)) -#endif - -#ifndef MAX - #define MAX(a, b) (((a) > (b)) ? (a) : (b)) -#endif -// -// For some environments, NULL may not be defined until certain headers are included -// -#ifndef NULL - #define NULL 0 -#endif - -/********************************************************************* -* -* Static const data -* -********************************************************************** -*/ - -static unsigned char _aTerminalId[16] = { '0', '1', '2', '3', '4', '5', '6', '7', '8', '9', 'A', 'B', 'C', 'D', 'E', 'F' }; - -/********************************************************************* -* -* Static data -* -********************************************************************** -*/ -// -// RTT Control Block and allocate buffers for channel 0 -// -#ifdef SEGGER_RTT_SECTION - #if (defined __GNUC__) - __attribute__ ((section (SEGGER_RTT_SECTION))) SEGGER_RTT_CB _SEGGER_RTT; - #elif (defined __ICCARM__) || (defined __ICCRX__) - #pragma location=SEGGER_RTT_SECTION - SEGGER_RTT_CB _SEGGER_RTT; - #elif (defined __CC_ARM__) - __attribute__ ((section (SEGGER_RTT_SECTION), zero_init)) SEGGER_RTT_CB _SEGGER_RTT; - #else - SEGGER_RTT_CB _SEGGER_RTT; - #endif -#else - SEGGER_RTT_CB _SEGGER_RTT; -#endif - -#ifdef SEGGER_RTT_BUFFER_SECTION - #if (defined __GNUC__) - __attribute__ ((section (SEGGER_RTT_BUFFER_SECTION))) static char _acUpBuffer [BUFFER_SIZE_UP]; - __attribute__ ((section (SEGGER_RTT_BUFFER_SECTION))) static char _acDownBuffer[BUFFER_SIZE_DOWN]; - #elif (defined __ICCARM__) || (defined __ICCRX__) - #pragma location=SEGGER_RTT_BUFFER_SECTION - static char _acUpBuffer [BUFFER_SIZE_UP]; - #pragma location=SEGGER_RTT_BUFFER_SECTION - static char _acDownBuffer[BUFFER_SIZE_DOWN]; - #elif (defined __CC_ARM__) - __attribute__ ((section (SEGGER_RTT_BUFFER_SECTION), zero_init)) static char _acUpBuffer [BUFFER_SIZE_UP]; - __attribute__ ((section (SEGGER_RTT_BUFFER_SECTION), zero_init)) static char _acDownBuffer[BUFFER_SIZE_DOWN]; - #else - static char _acUpBuffer [BUFFER_SIZE_UP]; - static char _acDownBuffer[BUFFER_SIZE_DOWN]; - #endif -#else - static char _acUpBuffer [BUFFER_SIZE_UP]; - static char _acDownBuffer[BUFFER_SIZE_DOWN]; -#endif - -static char _ActiveTerminal; - -/********************************************************************* -* -* Static functions -* -********************************************************************** -*/ - -/********************************************************************* -* -* _DoInit() -* -* Function description -* Initializes the control block an buffers. -* May only be called via INIT() to avoid overriding settings. -* -*/ -#define INIT() do { \ - if (_SEGGER_RTT.acID[0] == '\0') { _DoInit(); } \ - } while (0) -static void _DoInit(void) { - SEGGER_RTT_CB* p; - // - // Initialize control block - // - p = &_SEGGER_RTT; - p->MaxNumUpBuffers = SEGGER_RTT_MAX_NUM_UP_BUFFERS; - p->MaxNumDownBuffers = SEGGER_RTT_MAX_NUM_DOWN_BUFFERS; - // - // Initialize up buffer 0 - // - p->aUp[0].sName = "Terminal"; - p->aUp[0].pBuffer = _acUpBuffer; - p->aUp[0].SizeOfBuffer = sizeof(_acUpBuffer); - p->aUp[0].RdOff = 0u; - p->aUp[0].WrOff = 0u; - p->aUp[0].Flags = SEGGER_RTT_MODE_DEFAULT; - // - // Initialize down buffer 0 - // - p->aDown[0].sName = "Terminal"; - p->aDown[0].pBuffer = _acDownBuffer; - p->aDown[0].SizeOfBuffer = sizeof(_acDownBuffer); - p->aDown[0].RdOff = 0u; - p->aDown[0].WrOff = 0u; - p->aDown[0].Flags = SEGGER_RTT_MODE_DEFAULT; - // - // Finish initialization of the control block. - // Copy Id string in three steps to make sure "SEGGER RTT" is not found - // in initializer memory (usually flash) by J-Link - // - strcpy(&p->acID[7], "RTT"); - strcpy(&p->acID[0], "SEGGER"); - p->acID[6] = ' '; -} - -/********************************************************************* -* -* _WriteBlocking() -* -* Function description -* Stores a specified number of characters in SEGGER RTT ring buffer -* and updates the associated write pointer which is periodically -* read by the host. -* The caller is responsible for managing the write chunk sizes as -* _WriteBlocking() will block until all data has been posted successfully. -* -* Parameters -* pRing Ring buffer to post to. -* pBuffer Pointer to character array. Does not need to point to a \0 terminated string. -* NumBytes Number of bytes to be stored in the SEGGER RTT control block. -* -* Return value -* >= 0 - Number of bytes written into buffer. -*/ -static unsigned _WriteBlocking(SEGGER_RTT_BUFFER_UP* pRing, const char* pBuffer, unsigned NumBytes) { - unsigned NumBytesToWrite; - unsigned NumBytesWritten; - unsigned RdOff; - unsigned WrOff; - // - // Write data to buffer and handle wrap-around if necessary - // - NumBytesWritten = 0u; - WrOff = pRing->WrOff; - do { - RdOff = pRing->RdOff; // May be changed by host (debug probe) in the meantime - if (RdOff > WrOff) { - NumBytesToWrite = RdOff - WrOff - 1u; - } else { - NumBytesToWrite = pRing->SizeOfBuffer - (WrOff - RdOff + 1u); - } - NumBytesToWrite = MIN(NumBytesToWrite, (pRing->SizeOfBuffer - WrOff)); // Number of bytes that can be written until buffer wrap-around - NumBytesToWrite = MIN(NumBytesToWrite, NumBytes); - memcpy(pRing->pBuffer + WrOff, pBuffer, NumBytesToWrite); - NumBytesWritten += NumBytesToWrite; - pBuffer += NumBytesToWrite; - NumBytes -= NumBytesToWrite; - WrOff += NumBytesToWrite; - if (WrOff == pRing->SizeOfBuffer) { - WrOff = 0u; - } - pRing->WrOff = WrOff; - } while (NumBytes); - // - return NumBytesWritten; -} - -/********************************************************************* -* -* _WriteNoCheck() -* -* Function description -* Stores a specified number of characters in SEGGER RTT ring buffer -* and updates the associated write pointer which is periodically -* read by the host. -* It is callers responsibility to make sure data actually fits in buffer. -* -* Parameters -* pRing Ring buffer to post to. -* pBuffer Pointer to character array. Does not need to point to a \0 terminated string. -* NumBytes Number of bytes to be stored in the SEGGER RTT control block. -* -* Notes -* (1) If there might not be enough space in the "Up"-buffer, call _WriteBlocking -*/ -static void _WriteNoCheck(SEGGER_RTT_BUFFER_UP* pRing, const char* pData, unsigned NumBytes) { - unsigned NumBytesAtOnce; - unsigned WrOff; - unsigned Rem; - - WrOff = pRing->WrOff; - Rem = pRing->SizeOfBuffer - WrOff; - if (Rem > NumBytes) { - // - // All data fits before wrap around - // - memcpy(pRing->pBuffer + WrOff, pData, NumBytes); - pRing->WrOff = WrOff + NumBytes; - } else { - // - // We reach the end of the buffer, so need to wrap around - // - NumBytesAtOnce = Rem; - memcpy(pRing->pBuffer + WrOff, pData, NumBytesAtOnce); - NumBytesAtOnce = NumBytes - Rem; - memcpy(pRing->pBuffer, pData + Rem, NumBytesAtOnce); - pRing->WrOff = NumBytesAtOnce; - } -} - -/********************************************************************* -* -* _PostTerminalSwitch() -* -* Function description -* Switch terminal to the given terminal ID. It is the caller's -* responsibility to ensure the terminal ID is correct and there is -* enough space in the buffer for this to complete successfully. -* -* Parameters -* pRing Ring buffer to post to. -* TerminalId Terminal ID to switch to. -*/ -static void _PostTerminalSwitch(SEGGER_RTT_BUFFER_UP* pRing, unsigned char TerminalId) { - char ac[2]; - - ac[0] = 0xFFu; - ac[1] = _aTerminalId[TerminalId]; // Caller made already sure that TerminalId does not exceed our terminal limit - _WriteBlocking(pRing, ac, 2u); -} - -/********************************************************************* -* -* _GetAvailWriteSpace() -* -* Function description -* Returns the number of bytes that can be written to the ring -* buffer without blocking. -* -* Parameters -* pRing Ring buffer to check. -* -* Return value -* Number of bytes that are free in the buffer. -*/ -static unsigned _GetAvailWriteSpace(SEGGER_RTT_BUFFER_UP* pRing) { - unsigned RdOff; - unsigned WrOff; - unsigned r; - // - // Avoid warnings regarding volatile access order. It's not a problem - // in this case, but dampen compiler enthusiasm. - // - RdOff = pRing->RdOff; - WrOff = pRing->WrOff; - if (RdOff <= WrOff) { - r = pRing->SizeOfBuffer - 1u - WrOff + RdOff; - } else { - r = RdOff - WrOff - 1u; - } - return r; -} - -/********************************************************************* -* -* Public code -* -********************************************************************** -*/ -/********************************************************************* -* -* SEGGER_RTT_ReadNoLock() -* -* Function description -* Reads characters from SEGGER real-time-terminal control block -* which have been previously stored by the host. -* Do not lock against interrupts and multiple access. -* -* Parameters -* BufferIndex Index of Down-buffer to be used (e.g. 0 for "Terminal"). -* pBuffer Pointer to buffer provided by target application, to copy characters from RTT-down-buffer to. -* BufferSize Size of the target application buffer. -* -* Return value -* Number of bytes that have been read. -*/ -unsigned SEGGER_RTT_ReadNoLock(unsigned BufferIndex, void* pData, unsigned BufferSize) { - unsigned NumBytesRem; - unsigned NumBytesRead; - unsigned RdOff; - unsigned WrOff; - unsigned char* pBuffer; - SEGGER_RTT_BUFFER_DOWN* pRing; - // - INIT(); - pRing = &_SEGGER_RTT.aDown[BufferIndex]; - pBuffer = (unsigned char*)pData; - RdOff = pRing->RdOff; - WrOff = pRing->WrOff; - NumBytesRead = 0u; - // - // Read from current read position to wrap-around of buffer, first - // - if (RdOff > WrOff) { - NumBytesRem = pRing->SizeOfBuffer - RdOff; - NumBytesRem = MIN(NumBytesRem, BufferSize); - memcpy(pBuffer, pRing->pBuffer + RdOff, NumBytesRem); - NumBytesRead += NumBytesRem; - pBuffer += NumBytesRem; - BufferSize -= NumBytesRem; - RdOff += NumBytesRem; - // - // Handle wrap-around of buffer - // - if (RdOff == pRing->SizeOfBuffer) { - RdOff = 0u; - } - } - // - // Read remaining items of buffer - // - NumBytesRem = WrOff - RdOff; - NumBytesRem = MIN(NumBytesRem, BufferSize); - if (NumBytesRem > 0u) { - memcpy(pBuffer, pRing->pBuffer + RdOff, NumBytesRem); - NumBytesRead += NumBytesRem; - pBuffer += NumBytesRem; - BufferSize -= NumBytesRem; - RdOff += NumBytesRem; - } - if (NumBytesRead) { - pRing->RdOff = RdOff; - } - // - return NumBytesRead; -} - -/********************************************************************* -* -* SEGGER_RTT_Read -* -* Function description -* Reads characters from SEGGER real-time-terminal control block -* which have been previously stored by the host. -* -* Parameters -* BufferIndex Index of Down-buffer to be used (e.g. 0 for "Terminal"). -* pBuffer Pointer to buffer provided by target application, to copy characters from RTT-down-buffer to. -* BufferSize Size of the target application buffer. -* -* Return value -* Number of bytes that have been read. -*/ -unsigned SEGGER_RTT_Read(unsigned BufferIndex, void* pBuffer, unsigned BufferSize) { - unsigned NumBytesRead; - // - SEGGER_RTT_LOCK(); - // - // Call the non-locking read function - // - NumBytesRead = SEGGER_RTT_ReadNoLock(BufferIndex, pBuffer, BufferSize); - // - // Finish up. - // - SEGGER_RTT_UNLOCK(); - // - return NumBytesRead; -} - -/********************************************************************* -* -* SEGGER_RTT_WriteWithOverwriteNoLock -* -* Function description -* Stores a specified number of characters in SEGGER RTT -* control block. -* SEGGER_RTT_WriteWithOverwriteNoLock does not lock the application -* and overwrites data if the data does not fit into the buffer. -* -* Parameters -* BufferIndex Index of "Up"-buffer to be used (e.g. 0 for "Terminal"). -* pBuffer Pointer to character array. Does not need to point to a \0 terminated string. -* NumBytes Number of bytes to be stored in the SEGGER RTT control block. -* -* Notes -* (1) If there is not enough space in the "Up"-buffer, data is overwritten. -* (2) For performance reasons this function does not call Init() -* and may only be called after RTT has been initialized. -* Either by calling SEGGER_RTT_Init() or calling another RTT API function first. -* (3) Do not use SEGGER_RTT_WriteWithOverwriteNoLock if a J-Link -* connection reads RTT data. -*/ -void SEGGER_RTT_WriteWithOverwriteNoLock(unsigned BufferIndex, const void* pBuffer, unsigned NumBytes) { - const char* pData; - SEGGER_RTT_BUFFER_UP* pRing; - unsigned Avail; - - pData = (const char *)pBuffer; - // - // Get "to-host" ring buffer and copy some elements into local variables. - // - pRing = &_SEGGER_RTT.aUp[BufferIndex]; - // - // Check if we will overwrite data and need to adjust the RdOff. - // - if (pRing->WrOff == pRing->RdOff) { - Avail = pRing->SizeOfBuffer - 1u; - } else if ( pRing->WrOff < pRing->RdOff) { - Avail = pRing->RdOff - pRing->WrOff - 1u; - } else { - Avail = pRing->RdOff - pRing->WrOff - 1u + pRing->SizeOfBuffer; - } - if (NumBytes > Avail) { - pRing->RdOff += (NumBytes - Avail); - while (pRing->RdOff >= pRing->SizeOfBuffer) { - pRing->RdOff -= pRing->SizeOfBuffer; - } - } - // - // Write all data, no need to check the RdOff, but possibly handle multiple wrap-arounds - // - Avail = pRing->SizeOfBuffer - pRing->WrOff; - do { - if (Avail > NumBytes) { - // - // Last round - // -#if 1 // memcpy() is good for large amounts of data, but the overhead is too big for small amounts. Use a simple byte loop instead. - char* pDst; - pDst = pRing->pBuffer + pRing->WrOff; - pRing->WrOff += NumBytes; - do { - *pDst++ = *pData++; - } while (--NumBytes); -#else - memcpy(pRing->pBuffer + WrOff, pData, NumBytes); - pRing->WrOff += NumBytes; -#endif - break; //Alternatively: NumBytes = 0; - } else { - // - // Wrap-around necessary, write until wrap-around and reset WrOff - // - memcpy(pRing->pBuffer + pRing->WrOff, pData, Avail); - pData += Avail; - pRing->WrOff = 0; - NumBytes -= Avail; - Avail = (pRing->SizeOfBuffer - 1); - } - } while (NumBytes); -} - -/********************************************************************* -* -* SEGGER_RTT_WriteSkipNoLock -* -* Function description -* Stores a specified number of characters in SEGGER RTT -* control block which is then read by the host. -* SEGGER_RTT_WriteSkipNoLock does not lock the application and -* skips all data, if the data does not fit into the buffer. -* -* Parameters -* BufferIndex Index of "Up"-buffer to be used (e.g. 0 for "Terminal"). -* pBuffer Pointer to character array. Does not need to point to a \0 terminated string. -* NumBytes Number of bytes to be stored in the SEGGER RTT control block. -* -* Return value -* Number of bytes which have been stored in the "Up"-buffer. -* -* Notes -* (1) If there is not enough space in the "Up"-buffer, all data is dropped. -* (2) For performance reasons this function does not call Init() -* and may only be called after RTT has been initialized. -* Either by calling SEGGER_RTT_Init() or calling another RTT API function first. -*/ -unsigned SEGGER_RTT_WriteSkipNoLock(unsigned BufferIndex, const void* pBuffer, unsigned NumBytes) { - const char* pData; - SEGGER_RTT_BUFFER_UP* pRing; - unsigned Avail; - unsigned RdOff; - unsigned WrOff; - unsigned Rem; - - pData = (const char *)pBuffer; - // - // Get "to-host" ring buffer and copy some elements into local variables. - // - pRing = &_SEGGER_RTT.aUp[BufferIndex]; - RdOff = pRing->RdOff; - WrOff = pRing->WrOff; - // - // Handle the most common cases fastest. - // Which is: - // RdOff <= WrOff -> Space until wrap around is free. - // AND - // WrOff + NumBytes < SizeOfBuffer -> No Wrap around necessary. - // - // OR - // - // RdOff > WrOff -> Space until RdOff - 1 is free. - // AND - // WrOff + NumBytes < RdOff -> Data fits into buffer - // - if (RdOff <= WrOff) { - // - // Get space until WrOff will be at wrap around. - // - Avail = pRing->SizeOfBuffer - 1u - WrOff ; - if (Avail >= NumBytes) { -#if 1 // memcpy() is good for large amounts of data, but the overhead is too big for small amounts. Use a simple byte loop instead. - char* pDst; - pDst = pRing->pBuffer + WrOff; - WrOff += NumBytes; - do { - *pDst++ = *pData++; - } while (--NumBytes); - pRing->WrOff = WrOff + NumBytes; -#else - memcpy(pRing->pBuffer + WrOff, pData, NumBytes); - pRing->WrOff = WrOff + NumBytes; -#endif - return 1; - } - // - // If data did not fit into space until wrap around calculate complete space in buffer. - // - Avail += RdOff; - // - // If there is still no space for the whole of this output, don't bother. - // - if (Avail >= NumBytes) { - // - // OK, we have enough space in buffer. Copy in one or 2 chunks - // - Rem = pRing->SizeOfBuffer - WrOff; // Space until end of buffer - if (Rem > NumBytes) { - memcpy(pRing->pBuffer + WrOff, pData, NumBytes); - pRing->WrOff = WrOff + NumBytes; - } else { - // - // We reach the end of the buffer, so need to wrap around - // - memcpy(pRing->pBuffer + WrOff, pData, Rem); - memcpy(pRing->pBuffer, pData + Rem, NumBytes - Rem); - pRing->WrOff = NumBytes - Rem; - } - return 1; - } - } else { - Avail = RdOff - WrOff - 1u; - if (Avail >= NumBytes) { - memcpy(pRing->pBuffer + WrOff, pData, NumBytes); - pRing->WrOff = WrOff + NumBytes; - return 1; - } - } - // - // If we reach this point no data has been written - // - return 0; -} - -/********************************************************************* -* -* SEGGER_RTT_WriteNoLock -* -* Function description -* Stores a specified number of characters in SEGGER RTT -* control block which is then read by the host. -* SEGGER_RTT_WriteNoLock does not lock the application. -* -* Parameters -* BufferIndex Index of "Up"-buffer to be used (e.g. 0 for "Terminal"). -* pBuffer Pointer to character array. Does not need to point to a \0 terminated string. -* NumBytes Number of bytes to be stored in the SEGGER RTT control block. -* -* Return value -* Number of bytes which have been stored in the "Up"-buffer. -* -* Notes -* (1) If there is not enough space in the "Up"-buffer, remaining characters of pBuffer are dropped. -* (2) For performance reasons this function does not call Init() -* and may only be called after RTT has been initialized. -* Either by calling SEGGER_RTT_Init() or calling another RTT API function first. -*/ -unsigned SEGGER_RTT_WriteNoLock(unsigned BufferIndex, const void* pBuffer, unsigned NumBytes) { - unsigned Status; - unsigned Avail; - const char* pData; - SEGGER_RTT_BUFFER_UP* pRing; - - pData = (const char *)pBuffer; - // - // Get "to-host" ring buffer. - // - pRing = &_SEGGER_RTT.aUp[BufferIndex]; - // - // How we output depends upon the mode... - // - switch (pRing->Flags) { - case SEGGER_RTT_MODE_NO_BLOCK_SKIP: - // - // If we are in skip mode and there is no space for the whole - // of this output, don't bother. - // - Avail = _GetAvailWriteSpace(pRing); - if (Avail < NumBytes) { - Status = 0u; - } else { - Status = NumBytes; - _WriteNoCheck(pRing, pData, NumBytes); - } - break; - case SEGGER_RTT_MODE_NO_BLOCK_TRIM: - // - // If we are in trim mode, trim to what we can output without blocking. - // - Avail = _GetAvailWriteSpace(pRing); - Status = Avail < NumBytes ? Avail : NumBytes; - _WriteNoCheck(pRing, pData, Status); - break; - case SEGGER_RTT_MODE_BLOCK_IF_FIFO_FULL: - // - // If we are in blocking mode, output everything. - // - Status = _WriteBlocking(pRing, pData, NumBytes); - break; - default: - Status = 0u; - break; - } - // - // Finish up. - // - return Status; -} - -/********************************************************************* -* -* SEGGER_RTT_Write -* -* Function description -* Stores a specified number of characters in SEGGER RTT -* control block which is then read by the host. -* -* Parameters -* BufferIndex Index of "Up"-buffer to be used (e.g. 0 for "Terminal"). -* pBuffer Pointer to character array. Does not need to point to a \0 terminated string. -* NumBytes Number of bytes to be stored in the SEGGER RTT control block. -* -* Return value -* Number of bytes which have been stored in the "Up"-buffer. -* -* Notes -* (1) If there is not enough space in the "Up"-buffer, remaining characters of pBuffer are dropped. -*/ -unsigned SEGGER_RTT_Write(unsigned BufferIndex, const void* pBuffer, unsigned NumBytes) { - unsigned Status; - // - INIT(); - SEGGER_RTT_LOCK(); - // - // Call the non-locking write function - // - Status = SEGGER_RTT_WriteNoLock(BufferIndex, pBuffer, NumBytes); - // - // Finish up. - // - SEGGER_RTT_UNLOCK(); - // - return Status; -} - -/********************************************************************* -* -* SEGGER_RTT_WriteString -* -* Function description -* Stores string in SEGGER RTT control block. -* This data is read by the host. -* -* Parameters -* BufferIndex Index of "Up"-buffer to be used (e.g. 0 for "Terminal"). -* s Pointer to string. -* -* Return value -* Number of bytes which have been stored in the "Up"-buffer. -* -* Notes -* (1) If there is not enough space in the "Up"-buffer, depending on configuration, -* remaining characters may be dropped or RTT module waits until there is more space in the buffer. -* (2) String passed to this function has to be \0 terminated -* (3) \0 termination character is *not* stored in RTT buffer -*/ -unsigned SEGGER_RTT_WriteString(unsigned BufferIndex, const char* s) { - unsigned Len; - - Len = STRLEN(s); - return SEGGER_RTT_Write(BufferIndex, s, Len); -} - -/********************************************************************* -* -* SEGGER_RTT_GetKey -* -* Function description -* Reads one character from the SEGGER RTT buffer. -* Host has previously stored data there. -* -* Return value -* < 0 - No character available (buffer empty). -* >= 0 - Character which has been read. (Possible values: 0 - 255) -* -* Notes -* (1) This function is only specified for accesses to RTT buffer 0. -*/ -int SEGGER_RTT_GetKey(void) { - char c; - int r; - - r = (int)SEGGER_RTT_Read(0u, &c, 1u); - if (r == 1) { - r = (int)(unsigned char)c; - } else { - r = -1; - } - return r; -} - -/********************************************************************* -* -* SEGGER_RTT_WaitKey -* -* Function description -* Waits until at least one character is avaible in the SEGGER RTT buffer. -* Once a character is available, it is read and this function returns. -* -* Return value -* >=0 - Character which has been read. -* -* Notes -* (1) This function is only specified for accesses to RTT buffer 0 -* (2) This function is blocking if no character is present in RTT buffer -*/ -int SEGGER_RTT_WaitKey(void) { - int r; - - do { - r = SEGGER_RTT_GetKey(); - } while (r < 0); - return r; -} - -/********************************************************************* -* -* SEGGER_RTT_HasKey -* -* Function description -* Checks if at least one character for reading is available in the SEGGER RTT buffer. -* -* Return value -* == 0 - No characters are available to read. -* == 1 - At least one character is available. -* -* Notes -* (1) This function is only specified for accesses to RTT buffer 0 -*/ -int SEGGER_RTT_HasKey(void) { - unsigned RdOff; - int r; - - INIT(); - RdOff = _SEGGER_RTT.aDown[0].RdOff; - if (RdOff != _SEGGER_RTT.aDown[0].WrOff) { - r = 1; - } else { - r = 0; - } - return r; -} - -/********************************************************************* -* -* SEGGER_RTT_HasData -* -* Function description -* Check if there is data from the host in the given buffer. -* -* Return value: -* ==0: No data -* !=0: Data in buffer -* -*/ -unsigned SEGGER_RTT_HasData(unsigned BufferIndex) { - SEGGER_RTT_BUFFER_DOWN* pRing; - unsigned v; - - pRing = &_SEGGER_RTT.aDown[BufferIndex]; - v = pRing->WrOff; - return v - pRing->RdOff; -} - -/********************************************************************* -* -* SEGGER_RTT_AllocDownBuffer -* -* Function description -* Run-time configuration of the next down-buffer (H->T). -* The next buffer, which is not used yet is configured. -* This includes: Buffer address, size, name, flags, ... -* -* Parameters -* sName Pointer to a constant name string. -* pBuffer Pointer to a buffer to be used. -* BufferSize Size of the buffer. -* Flags Operating modes. Define behavior if buffer is full (not enough space for entire message). -* -* Return value -* >= 0 - O.K. Buffer Index -* < 0 - Error -*/ -int SEGGER_RTT_AllocDownBuffer(const char* sName, void* pBuffer, unsigned BufferSize, unsigned Flags) { - int BufferIndex; - - INIT(); - SEGGER_RTT_LOCK(); - BufferIndex = 0; - do { - if (_SEGGER_RTT.aDown[BufferIndex].pBuffer == NULL) { - break; - } - BufferIndex++; - } while (BufferIndex < _SEGGER_RTT.MaxNumDownBuffers); - if (BufferIndex < _SEGGER_RTT.MaxNumDownBuffers) { - _SEGGER_RTT.aDown[BufferIndex].sName = sName; - _SEGGER_RTT.aDown[BufferIndex].pBuffer = pBuffer; - _SEGGER_RTT.aDown[BufferIndex].SizeOfBuffer = BufferSize; - _SEGGER_RTT.aDown[BufferIndex].RdOff = 0u; - _SEGGER_RTT.aDown[BufferIndex].WrOff = 0u; - _SEGGER_RTT.aDown[BufferIndex].Flags = Flags; - } else { - BufferIndex = -1; - } - SEGGER_RTT_UNLOCK(); - return BufferIndex; -} - -/********************************************************************* -* -* SEGGER_RTT_AllocUpBuffer -* -* Function description -* Run-time configuration of the next up-buffer (T->H). -* The next buffer, which is not used yet is configured. -* This includes: Buffer address, size, name, flags, ... -* -* Parameters -* sName Pointer to a constant name string. -* pBuffer Pointer to a buffer to be used. -* BufferSize Size of the buffer. -* Flags Operating modes. Define behavior if buffer is full (not enough space for entire message). -* -* Return value -* >= 0 - O.K. Buffer Index -* < 0 - Error -*/ -int SEGGER_RTT_AllocUpBuffer(const char* sName, void* pBuffer, unsigned BufferSize, unsigned Flags) { - int BufferIndex; - - INIT(); - SEGGER_RTT_LOCK(); - BufferIndex = 0; - do { - if (_SEGGER_RTT.aUp[BufferIndex].pBuffer == NULL) { - break; - } - BufferIndex++; - } while (BufferIndex < _SEGGER_RTT.MaxNumUpBuffers); - if (BufferIndex < _SEGGER_RTT.MaxNumUpBuffers) { - _SEGGER_RTT.aUp[BufferIndex].sName = sName; - _SEGGER_RTT.aUp[BufferIndex].pBuffer = pBuffer; - _SEGGER_RTT.aUp[BufferIndex].SizeOfBuffer = BufferSize; - _SEGGER_RTT.aUp[BufferIndex].RdOff = 0u; - _SEGGER_RTT.aUp[BufferIndex].WrOff = 0u; - _SEGGER_RTT.aUp[BufferIndex].Flags = Flags; - } else { - BufferIndex = -1; - } - SEGGER_RTT_UNLOCK(); - return BufferIndex; -} - -/********************************************************************* -* -* SEGGER_RTT_ConfigUpBuffer -* -* Function description -* Run-time configuration of a specific up-buffer (T->H). -* Buffer to be configured is specified by index. -* This includes: Buffer address, size, name, flags, ... -* -* Parameters -* BufferIndex Index of the buffer to configure. -* sName Pointer to a constant name string. -* pBuffer Pointer to a buffer to be used. -* BufferSize Size of the buffer. -* Flags Operating modes. Define behavior if buffer is full (not enough space for entire message). -* -* Return value -* >= 0 - O.K. -* < 0 - Error -*/ -int SEGGER_RTT_ConfigUpBuffer(unsigned BufferIndex, const char* sName, void* pBuffer, unsigned BufferSize, unsigned Flags) { - int r; - - INIT(); - if (BufferIndex < (unsigned)_SEGGER_RTT.MaxNumUpBuffers) { - SEGGER_RTT_LOCK(); - if (BufferIndex > 0u) { - _SEGGER_RTT.aUp[BufferIndex].sName = sName; - _SEGGER_RTT.aUp[BufferIndex].pBuffer = pBuffer; - _SEGGER_RTT.aUp[BufferIndex].SizeOfBuffer = BufferSize; - _SEGGER_RTT.aUp[BufferIndex].RdOff = 0u; - _SEGGER_RTT.aUp[BufferIndex].WrOff = 0u; - } - _SEGGER_RTT.aUp[BufferIndex].Flags = Flags; - SEGGER_RTT_UNLOCK(); - r = 0; - } else { - r = -1; - } - return r; -} - -/********************************************************************* -* -* SEGGER_RTT_ConfigDownBuffer -* -* Function description -* Run-time configuration of a specific down-buffer (H->T). -* Buffer to be configured is specified by index. -* This includes: Buffer address, size, name, flags, ... -* -* Parameters -* BufferIndex Index of the buffer to configure. -* sName Pointer to a constant name string. -* pBuffer Pointer to a buffer to be used. -* BufferSize Size of the buffer. -* Flags Operating modes. Define behavior if buffer is full (not enough space for entire message). -* -* Return value -* >= 0 O.K. -* < 0 Error -*/ -int SEGGER_RTT_ConfigDownBuffer(unsigned BufferIndex, const char* sName, void* pBuffer, unsigned BufferSize, unsigned Flags) { - int r; - - INIT(); - if (BufferIndex < (unsigned)_SEGGER_RTT.MaxNumDownBuffers) { - SEGGER_RTT_LOCK(); - if (BufferIndex > 0u) { - _SEGGER_RTT.aDown[BufferIndex].sName = sName; - _SEGGER_RTT.aDown[BufferIndex].pBuffer = pBuffer; - _SEGGER_RTT.aDown[BufferIndex].SizeOfBuffer = BufferSize; - _SEGGER_RTT.aDown[BufferIndex].RdOff = 0u; - _SEGGER_RTT.aDown[BufferIndex].WrOff = 0u; - } - _SEGGER_RTT.aDown[BufferIndex].Flags = Flags; - SEGGER_RTT_UNLOCK(); - r = 0; - } else { - r = -1; - } - return r; -} - -/********************************************************************* -* -* SEGGER_RTT_SetNameUpBuffer -* -* Function description -* Run-time configuration of a specific up-buffer name (T->H). -* Buffer to be configured is specified by index. -* -* Parameters -* BufferIndex Index of the buffer to renamed. -* sName Pointer to a constant name string. -* -* Return value -* >= 0 O.K. -* < 0 Error -*/ -int SEGGER_RTT_SetNameUpBuffer(unsigned BufferIndex, const char* sName) { - int r; - - INIT(); - if (BufferIndex < (unsigned)_SEGGER_RTT.MaxNumUpBuffers) { - SEGGER_RTT_LOCK(); - _SEGGER_RTT.aUp[BufferIndex].sName = sName; - SEGGER_RTT_UNLOCK(); - r = 0; - } else { - r = -1; - } - return r; -} - -/********************************************************************* -* -* SEGGER_RTT_SetNameDownBuffer -* -* Function description -* Run-time configuration of a specific Down-buffer name (T->H). -* Buffer to be configured is specified by index. -* -* Parameters -* BufferIndex Index of the buffer to renamed. -* sName Pointer to a constant name string. -* -* Return value -* >= 0 O.K. -* < 0 Error -*/ -int SEGGER_RTT_SetNameDownBuffer(unsigned BufferIndex, const char* sName) { - int r; - - INIT(); - if (BufferIndex < (unsigned)_SEGGER_RTT.MaxNumDownBuffers) { - SEGGER_RTT_LOCK(); - _SEGGER_RTT.aDown[BufferIndex].sName = sName; - SEGGER_RTT_UNLOCK(); - r = 0; - } else { - r = -1; - } - return r; -} - -/********************************************************************* -* -* SEGGER_RTT_Init -* -* Function description -* Initializes the RTT Control Block. -* Should be used in RAM targets, at start of the application. -* -*/ -void SEGGER_RTT_Init (void) { - _DoInit(); -} - -/********************************************************************* -* -* SEGGER_RTT_SetTerminal -* -* Function description -* Sets the terminal to be used for output on channel 0. -* -* Parameters -* TerminalId Index of the terminal. -* -* Return value -* >= 0 O.K. -* < 0 Error (e.g. if RTT is configured for non-blocking mode and there was no space in the buffer to set the new terminal Id) -*/ -int SEGGER_RTT_SetTerminal (char TerminalId) { - char ac[2]; - SEGGER_RTT_BUFFER_UP* pRing; - unsigned Avail; - int r; - // - INIT(); - // - r = 0; - ac[0] = 0xFFU; - if ((unsigned char)TerminalId < (unsigned char)sizeof(_aTerminalId)) { // We only support a certain number of channels - ac[1] = _aTerminalId[(unsigned char)TerminalId]; - pRing = &_SEGGER_RTT.aUp[0]; // Buffer 0 is always reserved for terminal I/O, so we can use index 0 here, fixed - SEGGER_RTT_LOCK(); // Lock to make sure that no other task is writing into buffer, while we are and number of free bytes in buffer does not change downwards after checking and before writing - if ((pRing->Flags & SEGGER_RTT_MODE_MASK) == SEGGER_RTT_MODE_BLOCK_IF_FIFO_FULL) { - _ActiveTerminal = TerminalId; - _WriteBlocking(pRing, ac, 2u); - } else { // Skipping mode or trim mode? => We cannot trim this command so handling is the same for both modes - Avail = _GetAvailWriteSpace(pRing); - if (Avail >= 2) { - _ActiveTerminal = TerminalId; // Only change active terminal in case of success - _WriteNoCheck(pRing, ac, 2u); - } else { - r = -1; - } - } - SEGGER_RTT_UNLOCK(); - } else { - r = -1; - } - return r; -} - -/********************************************************************* -* -* SEGGER_RTT_TerminalOut -* -* Function description -* Writes a string to the given terminal -* without changing the terminal for channel 0. -* -* Parameters -* TerminalId Index of the terminal. -* s String to be printed on the terminal. -* -* Return value -* >= 0 - Number of bytes written. -* < 0 - Error. -* -*/ -int SEGGER_RTT_TerminalOut (char TerminalId, const char* s) { - int Status; - unsigned FragLen; - unsigned Avail; - SEGGER_RTT_BUFFER_UP* pRing; - // - INIT(); - // - // Validate terminal ID. - // - if (TerminalId < (char)sizeof(_aTerminalId)) { // We only support a certain number of channels - // - // Get "to-host" ring buffer. - // - pRing = &_SEGGER_RTT.aUp[0]; - // - // Need to be able to change terminal, write data, change back. - // Compute the fixed and variable sizes. - // - FragLen = strlen(s); - // - // How we output depends upon the mode... - // - SEGGER_RTT_LOCK(); - Avail = _GetAvailWriteSpace(pRing); - switch (pRing->Flags & SEGGER_RTT_MODE_MASK) { - case SEGGER_RTT_MODE_NO_BLOCK_SKIP: - // - // If we are in skip mode and there is no space for the whole - // of this output, don't bother switching terminals at all. - // - if (Avail < (FragLen + 4u)) { - Status = 0; - } else { - _PostTerminalSwitch(pRing, TerminalId); - Status = (int)_WriteBlocking(pRing, s, FragLen); - _PostTerminalSwitch(pRing, _ActiveTerminal); - } - break; - case SEGGER_RTT_MODE_NO_BLOCK_TRIM: - // - // If we are in trim mode and there is not enough space for everything, - // trim the output but always include the terminal switch. If no room - // for terminal switch, skip that totally. - // - if (Avail < 4u) { - Status = -1; - } else { - _PostTerminalSwitch(pRing, TerminalId); - Status = (int)_WriteBlocking(pRing, s, (FragLen < (Avail - 4u)) ? FragLen : (Avail - 4u)); - _PostTerminalSwitch(pRing, _ActiveTerminal); - } - break; - case SEGGER_RTT_MODE_BLOCK_IF_FIFO_FULL: - // - // If we are in blocking mode, output everything. - // - _PostTerminalSwitch(pRing, TerminalId); - Status = (int)_WriteBlocking(pRing, s, FragLen); - _PostTerminalSwitch(pRing, _ActiveTerminal); - break; - default: - Status = -1; - break; - } - // - // Finish up. - // - SEGGER_RTT_UNLOCK(); - } else { - Status = -1; - } - return Status; -} - - -/*************************** End of file ****************************/ diff --git a/examples/device/device_virtual_com/segger/SEGGER_RTT.h b/examples/device/device_virtual_com/segger/SEGGER_RTT.h deleted file mode 100644 index d3cac44dd..000000000 --- a/examples/device/device_virtual_com/segger/SEGGER_RTT.h +++ /dev/null @@ -1,234 +0,0 @@ -/********************************************************************* -* SEGGER MICROCONTROLLER GmbH & Co. KG * -* Solutions for real time microcontroller applications * -********************************************************************** -* * -* (c) 2014 - 2016 SEGGER Microcontroller GmbH & Co. KG * -* * -* www.segger.com Support: [email protected] * -* * -********************************************************************** -* * -* SEGGER RTT * Real Time Transfer for embedded targets * -* * -********************************************************************** -* * -* All rights reserved. * -* * -* * This software may in its unmodified form be freely redistributed * -* in source form. * -* * The source code may be modified, provided the source code * -* retains the above copyright notice, this list of conditions and * -* the following disclaimer. * -* * Modified versions of this software in source or linkable form * -* may not be distributed without prior consent of SEGGER. * -* * This software may only be used for communication with SEGGER * -* J-Link debug probes. * -* * -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND * -* CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, * -* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * -* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * -* DISCLAIMED. IN NO EVENT SHALL SEGGER Microcontroller BE LIABLE FOR * -* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT * -* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * -* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF * -* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE * -* USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH * -* DAMAGE. * -* * -********************************************************************** -* * -* RTT version: 5.12e * -* * -********************************************************************** ----------------------------END-OF-HEADER------------------------------ -File : SEGGER_RTT.h -Purpose : Implementation of SEGGER real-time transfer which allows - real-time communication on targets which support debugger - memory accesses while the CPU is running. ----------------------------------------------------------------------- -*/ - -#ifndef SEGGER_RTT_H -#define SEGGER_RTT_H - -#include "SEGGER_RTT_Conf.h" - -/********************************************************************* -* -* Defines, fixed -* -********************************************************************** -*/ - -/********************************************************************* -* -* Types -* -********************************************************************** -*/ - -// -// Description for a circular buffer (also called "ring buffer") -// which is used as up-buffer (T->H) -// -typedef struct { - const char* sName; // Optional name. Standard names so far are: "Terminal", "SysView", "J-Scope_t4i4" - char* pBuffer; // Pointer to start of buffer - unsigned SizeOfBuffer; // Buffer size in bytes. Note that one byte is lost, as this implementation does not fill up the buffer in order to avoid the problem of being unable to distinguish between full and empty. - unsigned WrOff; // Position of next item to be written by either target. - volatile unsigned RdOff; // Position of next item to be read by host. Must be volatile since it may be modified by host. - unsigned Flags; // Contains configuration flags -} SEGGER_RTT_BUFFER_UP; - -// -// Description for a circular buffer (also called "ring buffer") -// which is used as down-buffer (H->T) -// -typedef struct { - const char* sName; // Optional name. Standard names so far are: "Terminal", "SysView", "J-Scope_t4i4" - char* pBuffer; // Pointer to start of buffer - unsigned SizeOfBuffer; // Buffer size in bytes. Note that one byte is lost, as this implementation does not fill up the buffer in order to avoid the problem of being unable to distinguish between full and empty. - volatile unsigned WrOff; // Position of next item to be written by host. Must be volatile since it may be modified by host. - unsigned RdOff; // Position of next item to be read by target (down-buffer). - unsigned Flags; // Contains configuration flags -} SEGGER_RTT_BUFFER_DOWN; - -// -// RTT control block which describes the number of buffers available -// as well as the configuration for each buffer -// -// -typedef struct { - char acID[16]; // Initialized to "SEGGER RTT" - int MaxNumUpBuffers; // Initialized to SEGGER_RTT_MAX_NUM_UP_BUFFERS (type. 2) - int MaxNumDownBuffers; // Initialized to SEGGER_RTT_MAX_NUM_DOWN_BUFFERS (type. 2) - SEGGER_RTT_BUFFER_UP aUp[SEGGER_RTT_MAX_NUM_UP_BUFFERS]; // Up buffers, transferring information up from target via debug probe to host - SEGGER_RTT_BUFFER_DOWN aDown[SEGGER_RTT_MAX_NUM_DOWN_BUFFERS]; // Down buffers, transferring information down from host via debug probe to target -} SEGGER_RTT_CB; - -/********************************************************************* -* -* Global data -* -********************************************************************** -*/ -extern SEGGER_RTT_CB _SEGGER_RTT; - -/********************************************************************* -* -* RTT API functions -* -********************************************************************** -*/ -#ifdef __cplusplus - extern "C" { -#endif -int SEGGER_RTT_AllocDownBuffer (const char* sName, void* pBuffer, unsigned BufferSize, unsigned Flags); -int SEGGER_RTT_AllocUpBuffer (const char* sName, void* pBuffer, unsigned BufferSize, unsigned Flags); -int SEGGER_RTT_ConfigUpBuffer (unsigned BufferIndex, const char* sName, void* pBuffer, unsigned BufferSize, unsigned Flags); -int SEGGER_RTT_ConfigDownBuffer (unsigned BufferIndex, const char* sName, void* pBuffer, unsigned BufferSize, unsigned Flags); -int SEGGER_RTT_GetKey (void); -unsigned SEGGER_RTT_HasData (unsigned BufferIndex); -int SEGGER_RTT_HasKey (void); -void SEGGER_RTT_Init (void); -unsigned SEGGER_RTT_Read (unsigned BufferIndex, void* pBuffer, unsigned BufferSize); -unsigned SEGGER_RTT_ReadNoLock (unsigned BufferIndex, void* pData, unsigned BufferSize); -int SEGGER_RTT_SetNameDownBuffer(unsigned BufferIndex, const char* sName); -int SEGGER_RTT_SetNameUpBuffer (unsigned BufferIndex, const char* sName); -int SEGGER_RTT_WaitKey (void); -unsigned SEGGER_RTT_Write (unsigned BufferIndex, const void* pBuffer, unsigned NumBytes); -unsigned SEGGER_RTT_WriteNoLock (unsigned BufferIndex, const void* pBuffer, unsigned NumBytes); -unsigned SEGGER_RTT_WriteSkipNoLock (unsigned BufferIndex, const void* pBuffer, unsigned NumBytes); -unsigned SEGGER_RTT_WriteString (unsigned BufferIndex, const char* s); -void SEGGER_RTT_WriteWithOverwriteNoLock(unsigned BufferIndex, const void* pBuffer, unsigned NumBytes); -// -// Function macro for performance optimization -// -#define SEGGER_RTT_HASDATA(n) (_SEGGER_RTT.aDown[n].WrOff - _SEGGER_RTT.aDown[n].RdOff) - -/********************************************************************* -* -* RTT "Terminal" API functions -* -********************************************************************** -*/ -int SEGGER_RTT_SetTerminal (char TerminalId); -int SEGGER_RTT_TerminalOut (char TerminalId, const char* s); - -/********************************************************************* -* -* RTT printf functions (require SEGGER_RTT_printf.c) -* -********************************************************************** -*/ -int SEGGER_RTT_printf(unsigned BufferIndex, const char * sFormat, ...); -#ifdef __cplusplus - } -#endif - -/********************************************************************* -* -* Defines -* -********************************************************************** -*/ - -// -// Operating modes. Define behavior if buffer is full (not enough space for entire message) -// -#define SEGGER_RTT_MODE_NO_BLOCK_SKIP (0U) // Skip. Do not block, output nothing. (Default) -#define SEGGER_RTT_MODE_NO_BLOCK_TRIM (1U) // Trim: Do not block, output as much as fits. -#define SEGGER_RTT_MODE_BLOCK_IF_FIFO_FULL (2U) // Block: Wait until there is space in the buffer. -#define SEGGER_RTT_MODE_MASK (3U) - -// -// Control sequences, based on ANSI. -// Can be used to control color, and clear the screen -// -#define RTT_CTRL_RESET "[0m" // Reset to default colors -#define RTT_CTRL_CLEAR "[2J" // Clear screen, reposition cursor to top left - -#define RTT_CTRL_TEXT_BLACK "[2;30m" -#define RTT_CTRL_TEXT_RED "[2;31m" -#define RTT_CTRL_TEXT_GREEN "[2;32m" -#define RTT_CTRL_TEXT_YELLOW "[2;33m" -#define RTT_CTRL_TEXT_BLUE "[2;34m" -#define RTT_CTRL_TEXT_MAGENTA "[2;35m" -#define RTT_CTRL_TEXT_CYAN "[2;36m" -#define RTT_CTRL_TEXT_WHITE "[2;37m" - -#define RTT_CTRL_TEXT_BRIGHT_BLACK "[1;30m" -#define RTT_CTRL_TEXT_BRIGHT_RED "[1;31m" -#define RTT_CTRL_TEXT_BRIGHT_GREEN "[1;32m" -#define RTT_CTRL_TEXT_BRIGHT_YELLOW "[1;33m" -#define RTT_CTRL_TEXT_BRIGHT_BLUE "[1;34m" -#define RTT_CTRL_TEXT_BRIGHT_MAGENTA "[1;35m" -#define RTT_CTRL_TEXT_BRIGHT_CYAN "[1;36m" -#define RTT_CTRL_TEXT_BRIGHT_WHITE "[1;37m" - -#define RTT_CTRL_BG_BLACK "[24;40m" -#define RTT_CTRL_BG_RED "[24;41m" -#define RTT_CTRL_BG_GREEN "[24;42m" -#define RTT_CTRL_BG_YELLOW "[24;43m" -#define RTT_CTRL_BG_BLUE "[24;44m" -#define RTT_CTRL_BG_MAGENTA "[24;45m" -#define RTT_CTRL_BG_CYAN "[24;46m" -#define RTT_CTRL_BG_WHITE "[24;47m" - -#define RTT_CTRL_BG_BRIGHT_BLACK "[4;40m" -#define RTT_CTRL_BG_BRIGHT_RED "[4;41m" -#define RTT_CTRL_BG_BRIGHT_GREEN "[4;42m" -#define RTT_CTRL_BG_BRIGHT_YELLOW "[4;43m" -#define RTT_CTRL_BG_BRIGHT_BLUE "[4;44m" -#define RTT_CTRL_BG_BRIGHT_MAGENTA "[4;45m" -#define RTT_CTRL_BG_BRIGHT_CYAN "[4;46m" -#define RTT_CTRL_BG_BRIGHT_WHITE "[4;47m" - - -#endif - -/*************************** End of file ****************************/ diff --git a/examples/device/device_virtual_com/segger/SEGGER_RTT_Conf.h b/examples/device/device_virtual_com/segger/SEGGER_RTT_Conf.h deleted file mode 100644 index aef3b4053..000000000 --- a/examples/device/device_virtual_com/segger/SEGGER_RTT_Conf.h +++ /dev/null @@ -1,242 +0,0 @@ -/********************************************************************* -* SEGGER MICROCONTROLLER GmbH & Co. KG * -* Solutions for real time microcontroller applications * -********************************************************************** -* * -* (c) 2014 - 2016 SEGGER Microcontroller GmbH & Co. KG * -* * -* www.segger.com Support: [email protected] * -* * -********************************************************************** -* * -* SEGGER RTT * Real Time Transfer for embedded targets * -* * -********************************************************************** -* * -* All rights reserved. * -* * -* * This software may in its unmodified form be freely redistributed * -* in source form. * -* * The source code may be modified, provided the source code * -* retains the above copyright notice, this list of conditions and * -* the following disclaimer. * -* * Modified versions of this software in source or linkable form * -* may not be distributed without prior consent of SEGGER. * -* * This software may only be used for communication with SEGGER * -* J-Link debug probes. * -* * -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND * -* CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, * -* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * -* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * -* DISCLAIMED. IN NO EVENT SHALL SEGGER Microcontroller BE LIABLE FOR * -* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT * -* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * -* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF * -* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE * -* USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH * -* DAMAGE. * -* * -********************************************************************** -* * -* RTT version: 5.12e * -* * -********************************************************************** ----------------------------------------------------------------------- -File : SEGGER_RTT_Conf.h -Purpose : Implementation of SEGGER real-time transfer (RTT) which - allows real-time communication on targets which support - debugger memory accesses while the CPU is running. ----------------------------END-OF-HEADER------------------------------ -*/ - -#ifndef SEGGER_RTT_CONF_H -#define SEGGER_RTT_CONF_H - -#ifdef __ICCARM__ - #include <intrinsics.h> -#endif - -/********************************************************************* -* -* Defines, configurable -* -********************************************************************** -*/ - -#define SEGGER_RTT_MAX_NUM_UP_BUFFERS (2) // Max. number of up-buffers (T->H) available on this target (Default: 2) -#define SEGGER_RTT_MAX_NUM_DOWN_BUFFERS (2) // Max. number of down-buffers (H->T) available on this target (Default: 2) - -#define BUFFER_SIZE_UP (1024) // Size of the buffer for terminal output of target, up to host (Default: 1k) -#define BUFFER_SIZE_DOWN (16) // Size of the buffer for terminal input to target from host (Usually keyboard input) (Default: 16) - -#define SEGGER_RTT_PRINTF_BUFFER_SIZE (64u) // Size of buffer for RTT printf to bulk-send chars via RTT (Default: 64) - -#define SEGGER_RTT_MODE_DEFAULT SEGGER_RTT_MODE_NO_BLOCK_SKIP // Mode for pre-initialized terminal channel (buffer 0) - -// -// Target is not allowed to perform other RTT operations while string still has not been stored completely. -// Otherwise we would probably end up with a mixed string in the buffer. -// If using RTT from within interrupts, multiple tasks or multi processors, define the SEGGER_RTT_LOCK() and SEGGER_RTT_UNLOCK() function here. -// -// SEGGER_RTT_MAX_INTERRUPT_PRIORITY can be used in the sample lock routines on Cortex-M3/4. -// Make sure to mask all interrupts which can send RTT data, i.e. generate SystemView events, or cause task switches. -// When high-priority interrupts must not be masked while sending RTT data, SEGGER_RTT_MAX_INTERRUPT_PRIORITY needs to be adjusted accordingly. -// (Higher priority = lower priority number) -// Default value for embOS: 128u -// Default configuration in FreeRTOS: configMAX_SYSCALL_INTERRUPT_PRIORITY: ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) ) -// In case of doubt mask all interrupts: 0u -// - -#define SEGGER_RTT_MAX_INTERRUPT_PRIORITY (0x20) // Interrupt priority to lock on SEGGER_RTT_LOCK on Cortex-M3/4 (Default: 0x20) - -/********************************************************************* -* -* RTT lock configuration for SEGGER Embedded Studio, -* Rowley CrossStudio and GCC -*/ -#if (defined __SES_ARM) || (defined __CROSSWORKS_ARM) || (defined __GNUC__) - #ifdef __ARM_ARCH_6M__ - #define SEGGER_RTT_LOCK() { \ - unsigned int LockState; \ - __asm volatile ("mrs %0, primask \n\t" \ - "mov r1, $1 \n\t" \ - "msr primask, r1 \n\t" \ - : "=r" (LockState) \ - : \ - : "r1" \ - ); - - #define SEGGER_RTT_UNLOCK() __asm volatile ("msr primask, %0 \n\t" \ - : \ - : "r" (LockState) \ - : \ - ); \ - } - - #elif (defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)) - #ifndef SEGGER_RTT_MAX_INTERRUPT_PRIORITY - #define SEGGER_RTT_MAX_INTERRUPT_PRIORITY (0x20) - #endif - #define SEGGER_RTT_LOCK() { \ - unsigned int LockState; \ - __asm volatile ("mrs %0, basepri \n\t" \ - "mov r1, %1 \n\t" \ - "msr basepri, r1 \n\t" \ - : "=r" (LockState) \ - : "i"(SEGGER_RTT_MAX_INTERRUPT_PRIORITY) \ - : "r1" \ - ); - - #define SEGGER_RTT_UNLOCK() __asm volatile ("msr basepri, %0 \n\t" \ - : \ - : "r" (LockState) \ - : \ - ); \ - } - - #elif defined(__ARM_ARCH_7A__) - #define SEGGER_RTT_LOCK() { \ - unsigned int LockState; \ - __asm volatile ("mrs r1, CPSR \n\t" \ - "mov %0, r1 \n\t" \ - "orr r1, r1, #0xC0 \n\t" \ - "msr CPSR_c, r1 \n\t" \ - : "=r" (LockState) \ - : \ - : "r1" \ - ); - - #define SEGGER_RTT_UNLOCK() __asm volatile ("mov r0, %0 \n\t" \ - "mrs r1, CPSR \n\t" \ - "bic r1, r1, #0xC0 \n\t" \ - "and r0, r0, #0xC0 \n\t" \ - "orr r1, r1, r0 \n\t" \ - "msr CPSR_c, r1 \n\t" \ - : \ - : "r" (LockState) \ - : "r0", "r1" \ - ); \ - } -#else - #define SEGGER_RTT_LOCK() - #define SEGGER_RTT_UNLOCK() - #endif -#endif - -/********************************************************************* -* -* RTT lock configuration for IAR EWARM -*/ -#ifdef __ICCARM__ - #if (defined (__ARM6M__) && (__CORE__ == __ARM6M__)) - #define SEGGER_RTT_LOCK() { \ - unsigned int LockState; \ - LockState = __get_PRIMASK(); \ - __set_PRIMASK(1); - - #define SEGGER_RTT_UNLOCK() __set_PRIMASK(LockState); \ - } - #elif ((defined (__ARM7EM__) && (__CORE__ == __ARM7EM__)) || (defined (__ARM7M__) && (__CORE__ == __ARM7M__))) - #ifndef SEGGER_RTT_MAX_INTERRUPT_PRIORITY - #define SEGGER_RTT_MAX_INTERRUPT_PRIORITY (0x20) - #endif - #define SEGGER_RTT_LOCK() { \ - unsigned int LockState; \ - LockState = __get_BASEPRI(); \ - __set_BASEPRI(SEGGER_RTT_MAX_INTERRUPT_PRIORITY); - - #define SEGGER_RTT_UNLOCK() __set_BASEPRI(LockState); \ - } - #endif -#endif - -/********************************************************************* -* -* RTT lock configuration for KEIL ARM -*/ -#ifdef __CC_ARM - #if (defined __TARGET_ARCH_6S_M) - #define SEGGER_RTT_LOCK() { \ - unsigned int LockState; \ - register unsigned char PRIMASK __asm( "primask"); \ - LockState = PRIMASK; \ - PRIMASK = 1u; \ - __schedule_barrier(); - - #define SEGGER_RTT_UNLOCK() PRIMASK = LockState; \ - __schedule_barrier(); \ - } - #elif (defined(__TARGET_ARCH_7_M) || defined(__TARGET_ARCH_7E_M)) - #ifndef SEGGER_RTT_MAX_INTERRUPT_PRIORITY - #define SEGGER_RTT_MAX_INTERRUPT_PRIORITY (0x20) - #endif - #define SEGGER_RTT_LOCK() { \ - unsigned int LockState; \ - register unsigned char BASEPRI __asm( "basepri"); \ - LockState = BASEPRI; \ - BASEPRI = SEGGER_RTT_MAX_INTERRUPT_PRIORITY; \ - __schedule_barrier(); - - #define SEGGER_RTT_UNLOCK() BASEPRI = LockState; \ - __schedule_barrier(); \ - } - #endif -#endif - -/********************************************************************* -* -* RTT lock configuration fallback -*/ -#ifndef SEGGER_RTT_LOCK - #define SEGGER_RTT_LOCK() // Lock RTT (nestable) (i.e. disable interrupts) -#endif - -#ifndef SEGGER_RTT_UNLOCK - #define SEGGER_RTT_UNLOCK() // Unlock RTT (nestable) (i.e. enable previous interrupt lock state) -#endif - -#endif -/*************************** End of file ****************************/ diff --git a/examples/device/device_virtual_com/segger/SEGGER_RTT_SES.c b/examples/device/device_virtual_com/segger/SEGGER_RTT_SES.c deleted file mode 100644 index 6ca09e9e7..000000000 --- a/examples/device/device_virtual_com/segger/SEGGER_RTT_SES.c +++ /dev/null @@ -1,76 +0,0 @@ -/********************************************************************* -* SEGGER MICROCONTROLLER GmbH & Co. KG * -* Solutions for real time microcontroller applications * -********************************************************************** -* * -* (c) 2014 - 2015 SEGGER Microcontroller GmbH & Co. KG * -* * -* www.segger.com Support: [email protected] * -* * -********************************************************************** -* * -* All rights reserved. * -* * -* * This software may in its unmodified form be freely redistributed * -* in source form. * -* * The source code may be modified, provided the source code * -* retains the above copyright notice, this list of conditions and * -* the following disclaimer. * -* * Modified versions of this software in source or linkable form * -* may not be distributed without prior consent of SEGGER. * -* * This software may only be used for communication with SEGGER * -* J-Link debug probes. * -* * -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND * -* CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, * -* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * -* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * -* DISCLAIMED. IN NO EVENT SHALL SEGGER Microcontroller BE LIABLE FOR * -* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT * -* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * -* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF * -* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE * -* USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH * -* DAMAGE. * -* * -********************************************************************** --------- END-OF-HEADER --------------------------------------------- -File : SEGGER_RTT_Syscalls_SES.c -Purpose : Reimplementation of printf, puts and - implementation of __putchar and __getchar using RTT in SES. - To use RTT for printf output, include this file in your - application. ----------------------------------------------------------------------- -*/ -#include "SEGGER_RTT.h" -#include "__libc.h" -#include <stdarg.h> -#include <stdio.h> - -int printf(const char *fmt,...) { - char buffer[512]; - va_list args; - va_start (args, fmt); - int n = vsnprintf(buffer, sizeof(buffer), fmt, args); - SEGGER_RTT_Write(0, buffer, n); - va_end(args); - return n; -} - -int puts(const char *s) { - return SEGGER_RTT_WriteString(0, s); -} - -int __putchar(int x, __printf_tag_ptr ctx) { - (void)ctx; - SEGGER_RTT_Write(0, (char *)&x, 1); - return x; -} - -int __getchar() { - return SEGGER_RTT_WaitKey(); -} - -/****** End Of File *************************************************/ diff --git a/examples/device/device_virtual_com/segger/device_virtual_com.emProject b/examples/device/device_virtual_com/segger/device_virtual_com.emProject deleted file mode 100644 index 63927ff9d..000000000 --- a/examples/device/device_virtual_com/segger/device_virtual_com.emProject +++ /dev/null @@ -1,218 +0,0 @@ -<!DOCTYPE CrossStudio_Project_File> -<solution Name="device_virtual_com" target="8" version="2"> - <project Name="device_virtual_com"> - <configuration - Name="Common" - Placement="Flash" - Target="LPC4357 Cortex-M4" - arm_architecture="v7EM" - arm_core_type="Cortex-M4" - arm_endian="Little" - arm_fp_abi="Hard" - arm_fpu_type="FPv4-SP-D16" - arm_interwork="No" - arm_linker_heap_size="2048" - arm_linker_process_stack_size="0" - arm_linker_stack_size="2048" - arm_simulator_memory_simulation_parameter="RAM;0x10000000;0x00008000;ROM;0x1A000000;0x00080000;ROM;0x1B000000;0x00080000;RAM;0x20000000;0x00010000" - arm_target_debug_interface_type="ADIv5" - arm_target_device_name="LPC4357_M4" - arm_target_interface_type="SWD" - c_preprocessor_definitions="CORE_M4;__LPC4300_FAMILY;__LPC435x_SUBFAMILY;ARM_MATH_CM4;FLASH_PLACEMENT=1" - c_user_include_directories="../src;$(ProjectDir)/LPC4300/CMSIS/Device/Include;$(RepoDir)/hw/cmsis/Include;$(RepoDir)/hw/mcu/nxp/lpc43xx/tusb_port;$(RepoDir)/hw/mcu/nxp/lpc43xx/CMSIS_LPC43xx_DriverLib/inc;$(RepoDir)/hw/;$(RepoDir)/tinyusb" - debug_register_definition_file="$(ProjectDir)/LPC43xx_Registers.xml" - debug_target_connection="J-Link" - gcc_entry_point="Reset_Handler" - linker_memory_map_file="$(ProjectDir)/LPC4357 Cortex-M4_MemoryMap.xml" - linker_section_placement_file="$(ProjectDir)/flash_placement.xml" - macros="DeviceHeaderFile=$(PackagesDir)/LPC4300/CMSIS/Device/Include/LPC43xx.h;DeviceLibraryIdentifier=M4lf;DeviceSystemFile=$(PackagesDir)/LPC4300/CMSIS/Device/Source/system_LPC43xx.c;DeviceVectorsFile=$(PackagesDir)/LPC4300/Source/LPC43xx_Vectors.s;DeviceFamily=LPC4300;DeviceSubFamily=LPC435x;Target=LPC4357 Cortex-M4;Placement=Flash;RepoDir=../../../.." - package_dependencies="LPC4300" - project_directory="" - project_type="Executable" - target_reset_script="Reset();" - target_trace_initialize_script="EnableTrace("$(TraceInterfaceType)")" /> - <folder Name="RTT Files"> - <file file_name="SEGGER_RTT.c" /> - <file file_name="SEGGER_RTT.h" /> - <file file_name="SEGGER_RTT_Conf.h" /> - <file file_name="SEGGER_RTT_SES.c" /> - </folder> - <folder Name="Script Files"> - <file file_name="LPC4300_Target.js"> - <configuration Name="Common" file_type="Reset Script" /> - </file> - </folder> - <folder Name="src"> - <configuration Name="Common" filter="c;cpp;cxx;cc;h;s;asm;inc" /> - <file file_name="../src/main.c" /> - <file file_name="../src/tusb_config.h" /> - <file file_name="../src/tusb_descriptors.c" /> - <file file_name="../src/tusb_descriptors.h" /> - </folder> - <folder Name="System Files"> - <file file_name="thumb_crt0.s" /> - <file file_name="LPC4300_Startup.s" /> - <file file_name="LPC43xx_Vectors.s"> - <configuration Name="Common" file_type="Assembly" /> - </file> - </folder> - <configuration Name="Debug" c_user_include_directories="." /> - <folder - Name="tinyusb" - exclude="" - filter="*.c;*.h" - path="../../../../tinyusb" - recurse="Yes" /> - <folder Name="hw"> - <folder Name="bsp"> - <file file_name="../../../../hw/bsp/ansi_escape.h" /> - <file file_name="../../../../hw/bsp/board.c" /> - <file file_name="../../../../hw/bsp/board.h" /> - <file file_name="../../../../hw/bsp/printf_retarget.c" /> - <folder Name="ea4357"> - <file file_name="../../../../hw/bsp/ea4357/board_ea4357.c" /> - <file file_name="../../../../hw/bsp/ea4357/board_ea4357.h" /> - <file file_name="../../../../hw/bsp/ea4357/emac.c" /> - <file file_name="../../../../hw/bsp/ea4357/emac.h" /> - <file file_name="../../../../hw/bsp/ea4357/sdram.c" /> - <file file_name="../../../../hw/bsp/ea4357/sdram.h" /> - <folder Name="oem_base_board"> - <file file_name="../../../../hw/bsp/ea4357/oem_base_board/acc.c" /> - <file file_name="../../../../hw/bsp/ea4357/oem_base_board/acc.h" /> - <file file_name="../../../../hw/bsp/ea4357/oem_base_board/base_eeprom.c" /> - <file file_name="../../../../hw/bsp/ea4357/oem_base_board/base_eeprom.h" /> - <file file_name="../../../../hw/bsp/ea4357/oem_base_board/lm75a.c" /> - <file file_name="../../../../hw/bsp/ea4357/oem_base_board/lm75a.h" /> - <file file_name="../../../../hw/bsp/ea4357/oem_base_board/memreg.c" /> - <file file_name="../../../../hw/bsp/ea4357/oem_base_board/memreg.h" /> - <file file_name="../../../../hw/bsp/ea4357/oem_base_board/pca9532.c" /> - <file file_name="../../../../hw/bsp/ea4357/oem_base_board/pca9532.h" /> - <file file_name="../../../../hw/bsp/ea4357/oem_base_board/uda1380.c" /> - <file file_name="../../../../hw/bsp/ea4357/oem_base_board/uda1380.h" /> - </folder> - </folder> - </folder> - <folder Name="cmsis"> - <folder Name="Include"> - <file file_name="../../../../hw/cmsis/Include/arm_common_tables.h" /> - <file file_name="../../../../hw/cmsis/Include/arm_const_structs.h" /> - <file file_name="../../../../hw/cmsis/Include/arm_math.h" /> - <file file_name="../../../../hw/cmsis/Include/cmsis_armcc.h" /> - <file file_name="../../../../hw/cmsis/Include/cmsis_armcc_V6.h" /> - <file file_name="../../../../hw/cmsis/Include/cmsis_gcc.h" /> - <file file_name="../../../../hw/cmsis/Include/core_cm0.h" /> - <file file_name="../../../../hw/cmsis/Include/core_cm0plus.h" /> - <file file_name="../../../../hw/cmsis/Include/core_cm3.h" /> - <file file_name="../../../../hw/cmsis/Include/core_cm4.h" /> - <file file_name="../../../../hw/cmsis/Include/core_cm7.h" /> - <file file_name="../../../../hw/cmsis/Include/core_cmFunc.h" /> - <file file_name="../../../../hw/cmsis/Include/core_cmInstr.h" /> - <file file_name="../../../../hw/cmsis/Include/core_cmSimd.h" /> - <file file_name="../../../../hw/cmsis/Include/core_sc000.h" /> - <file file_name="../../../../hw/cmsis/Include/core_sc300.h" /> - </folder> - </folder> - <folder Name="mcu"> - <folder Name="nxp"> - <folder Name="lpc43xx"> - <folder Name="CMSIS_LPC43xx_DriverLib"> - <folder Name="inc"> - <file file_name="../../../../hw/mcu/nxp/lpc43xx/CMSIS_LPC43xx_DriverLib/inc/debug_frmwrk.h" /> - <file file_name="../../../../hw/mcu/nxp/lpc43xx/CMSIS_LPC43xx_DriverLib/inc/fpu_enable.h" /> - <file file_name="../../../../hw/mcu/nxp/lpc43xx/CMSIS_LPC43xx_DriverLib/inc/fpu_init.h" /> - <file file_name="../../../../hw/mcu/nxp/lpc43xx/CMSIS_LPC43xx_DriverLib/inc/LCDTerm.h" /> - <file file_name="../../../../hw/mcu/nxp/lpc43xx/CMSIS_LPC43xx_DriverLib/inc/LPC43xx.h" /> - <file file_name="../../../../hw/mcu/nxp/lpc43xx/CMSIS_LPC43xx_DriverLib/inc/lpc43xx_adc.h" /> - <file file_name="../../../../hw/mcu/nxp/lpc43xx/CMSIS_LPC43xx_DriverLib/inc/lpc43xx_atimer.h" /> - <file file_name="../../../../hw/mcu/nxp/lpc43xx/CMSIS_LPC43xx_DriverLib/inc/lpc43xx_can.h" /> - <file file_name="../../../../hw/mcu/nxp/lpc43xx/CMSIS_LPC43xx_DriverLib/inc/lpc43xx_cgu.h" /> - <file file_name="../../../../hw/mcu/nxp/lpc43xx/CMSIS_LPC43xx_DriverLib/inc/lpc43xx_dac.h" /> - <file file_name="../../../../hw/mcu/nxp/lpc43xx/CMSIS_LPC43xx_DriverLib/inc/lpc43xx_emc.h" /> - <file file_name="../../../../hw/mcu/nxp/lpc43xx/CMSIS_LPC43xx_DriverLib/inc/lpc43xx_evrt.h" /> - <file file_name="../../../../hw/mcu/nxp/lpc43xx/CMSIS_LPC43xx_DriverLib/inc/lpc43xx_gpdma.h" /> - <file file_name="../../../../hw/mcu/nxp/lpc43xx/CMSIS_LPC43xx_DriverLib/inc/lpc43xx_gpio.h" /> - <file file_name="../../../../hw/mcu/nxp/lpc43xx/CMSIS_LPC43xx_DriverLib/inc/lpc43xx_i2c.h" /> - <file file_name="../../../../hw/mcu/nxp/lpc43xx/CMSIS_LPC43xx_DriverLib/inc/lpc43xx_i2s.h" /> - <file file_name="../../../../hw/mcu/nxp/lpc43xx/CMSIS_LPC43xx_DriverLib/inc/lpc43xx_lcd.h" /> - <file file_name="../../../../hw/mcu/nxp/lpc43xx/CMSIS_LPC43xx_DriverLib/inc/lpc43xx_libcfg_default.h" /> - <file file_name="../../../../hw/mcu/nxp/lpc43xx/CMSIS_LPC43xx_DriverLib/inc/lpc43xx_mcpwm.h" /> - <file file_name="../../../../hw/mcu/nxp/lpc43xx/CMSIS_LPC43xx_DriverLib/inc/lpc43xx_nvic.h" /> - <file file_name="../../../../hw/mcu/nxp/lpc43xx/CMSIS_LPC43xx_DriverLib/inc/lpc43xx_pwr.h" /> - <file file_name="../../../../hw/mcu/nxp/lpc43xx/CMSIS_LPC43xx_DriverLib/inc/lpc43xx_qei.h" /> - <file file_name="../../../../hw/mcu/nxp/lpc43xx/CMSIS_LPC43xx_DriverLib/inc/lpc43xx_rgu.h" /> - <file file_name="../../../../hw/mcu/nxp/lpc43xx/CMSIS_LPC43xx_DriverLib/inc/lpc43xx_rit.h" /> - <file file_name="../../../../hw/mcu/nxp/lpc43xx/CMSIS_LPC43xx_DriverLib/inc/lpc43xx_rtc.h" /> - <file file_name="../../../../hw/mcu/nxp/lpc43xx/CMSIS_LPC43xx_DriverLib/inc/lpc43xx_sct.h" /> - <file file_name="../../../../hw/mcu/nxp/lpc43xx/CMSIS_LPC43xx_DriverLib/inc/lpc43xx_scu.h" /> - <file file_name="../../../../hw/mcu/nxp/lpc43xx/CMSIS_LPC43xx_DriverLib/inc/lpc43xx_sdif.h" /> - <file file_name="../../../../hw/mcu/nxp/lpc43xx/CMSIS_LPC43xx_DriverLib/inc/lpc43xx_sdmmc.h" /> - <file file_name="../../../../hw/mcu/nxp/lpc43xx/CMSIS_LPC43xx_DriverLib/inc/lpc43xx_ssp.h" /> - <file file_name="../../../../hw/mcu/nxp/lpc43xx/CMSIS_LPC43xx_DriverLib/inc/lpc43xx_timer.h" /> - <file file_name="../../../../hw/mcu/nxp/lpc43xx/CMSIS_LPC43xx_DriverLib/inc/lpc43xx_uart.h" /> - <file file_name="../../../../hw/mcu/nxp/lpc43xx/CMSIS_LPC43xx_DriverLib/inc/lpc43xx_wwdt.h" /> - <file file_name="../../../../hw/mcu/nxp/lpc43xx/CMSIS_LPC43xx_DriverLib/inc/lpc_sdmmc.h" /> - <file file_name="../../../../hw/mcu/nxp/lpc43xx/CMSIS_LPC43xx_DriverLib/inc/lpc_types.h" /> - <file file_name="../../../../hw/mcu/nxp/lpc43xx/CMSIS_LPC43xx_DriverLib/inc/sdio.h" /> - <file file_name="../../../../hw/mcu/nxp/lpc43xx/CMSIS_LPC43xx_DriverLib/inc/spifi_rom_api.h" /> - <file file_name="../../../../hw/mcu/nxp/lpc43xx/CMSIS_LPC43xx_DriverLib/inc/system_LPC43xx.h" /> - </folder> - <folder Name="src"> - <file file_name="../../../../hw/mcu/nxp/lpc43xx/CMSIS_LPC43xx_DriverLib/src/debug_frmwrk.c" /> - <file file_name="../../../../hw/mcu/nxp/lpc43xx/CMSIS_LPC43xx_DriverLib/src/Font5x7.c" /> - <file file_name="../../../../hw/mcu/nxp/lpc43xx/CMSIS_LPC43xx_DriverLib/src/LCDTerm.c" /> - <file file_name="../../../../hw/mcu/nxp/lpc43xx/CMSIS_LPC43xx_DriverLib/src/lpc43xx_adc.c" /> - <file file_name="../../../../hw/mcu/nxp/lpc43xx/CMSIS_LPC43xx_DriverLib/src/lpc43xx_atimer.c" /> - <file file_name="../../../../hw/mcu/nxp/lpc43xx/CMSIS_LPC43xx_DriverLib/src/lpc43xx_can.c" /> - <file file_name="../../../../hw/mcu/nxp/lpc43xx/CMSIS_LPC43xx_DriverLib/src/lpc43xx_cgu.c" /> - <file file_name="../../../../hw/mcu/nxp/lpc43xx/CMSIS_LPC43xx_DriverLib/src/lpc43xx_dac.c" /> - <file file_name="../../../../hw/mcu/nxp/lpc43xx/CMSIS_LPC43xx_DriverLib/src/lpc43xx_emc.c" /> - <file file_name="../../../../hw/mcu/nxp/lpc43xx/CMSIS_LPC43xx_DriverLib/src/lpc43xx_evrt.c" /> - <file file_name="../../../../hw/mcu/nxp/lpc43xx/CMSIS_LPC43xx_DriverLib/src/lpc43xx_gpdma.c" /> - <file file_name="../../../../hw/mcu/nxp/lpc43xx/CMSIS_LPC43xx_DriverLib/src/lpc43xx_gpio.c" /> - <file file_name="../../../../hw/mcu/nxp/lpc43xx/CMSIS_LPC43xx_DriverLib/src/lpc43xx_i2c.c" /> - <file file_name="../../../../hw/mcu/nxp/lpc43xx/CMSIS_LPC43xx_DriverLib/src/lpc43xx_i2s.c" /> - <file file_name="../../../../hw/mcu/nxp/lpc43xx/CMSIS_LPC43xx_DriverLib/src/lpc43xx_lcd.c" /> - <file file_name="../../../../hw/mcu/nxp/lpc43xx/CMSIS_LPC43xx_DriverLib/src/lpc43xx_mcpwm.c" /> - <file file_name="../../../../hw/mcu/nxp/lpc43xx/CMSIS_LPC43xx_DriverLib/src/lpc43xx_nvic.c" /> - <file file_name="../../../../hw/mcu/nxp/lpc43xx/CMSIS_LPC43xx_DriverLib/src/lpc43xx_pwr.c" /> - <file file_name="../../../../hw/mcu/nxp/lpc43xx/CMSIS_LPC43xx_DriverLib/src/lpc43xx_qei.c" /> - <file file_name="../../../../hw/mcu/nxp/lpc43xx/CMSIS_LPC43xx_DriverLib/src/lpc43xx_rgu.c" /> - <file file_name="../../../../hw/mcu/nxp/lpc43xx/CMSIS_LPC43xx_DriverLib/src/lpc43xx_rit.c" /> - <file file_name="../../../../hw/mcu/nxp/lpc43xx/CMSIS_LPC43xx_DriverLib/src/lpc43xx_rtc.c" /> - <file file_name="../../../../hw/mcu/nxp/lpc43xx/CMSIS_LPC43xx_DriverLib/src/lpc43xx_sct.c" /> - <file file_name="../../../../hw/mcu/nxp/lpc43xx/CMSIS_LPC43xx_DriverLib/src/lpc43xx_scu.c" /> - <file file_name="../../../../hw/mcu/nxp/lpc43xx/CMSIS_LPC43xx_DriverLib/src/lpc43xx_sdif.c" /> - <file file_name="../../../../hw/mcu/nxp/lpc43xx/CMSIS_LPC43xx_DriverLib/src/lpc43xx_sdmmc.c" /> - <file file_name="../../../../hw/mcu/nxp/lpc43xx/CMSIS_LPC43xx_DriverLib/src/lpc43xx_ssp.c" /> - <file file_name="../../../../hw/mcu/nxp/lpc43xx/CMSIS_LPC43xx_DriverLib/src/lpc43xx_timer.c" /> - <file file_name="../../../../hw/mcu/nxp/lpc43xx/CMSIS_LPC43xx_DriverLib/src/lpc43xx_uart.c" /> - <file file_name="../../../../hw/mcu/nxp/lpc43xx/CMSIS_LPC43xx_DriverLib/src/lpc43xx_wwdt.c" /> - <file file_name="../../../../hw/mcu/nxp/lpc43xx/CMSIS_LPC43xx_DriverLib/src/system_LPC43xx.c" /> - </folder> - </folder> - <folder Name="tusb_port"> - <file file_name="../../../../hw/mcu/nxp/lpc43xx/tusb_port/dcd_lpc43xx.c" /> - <file file_name="../../../../hw/mcu/nxp/lpc43xx/tusb_port/dcd_lpc43xx.h" /> - <file file_name="../../../../hw/mcu/nxp/lpc43xx/tusb_port/hal_lpc43xx.c" /> - </folder> - </folder> - </folder> - </folder> - </folder> - <configuration - Name="EA4357" - c_preprocessor_definitions="BOARD=BOARD_EA4357;CFG_TUSB_MCU=MCU_LPC43XX" /> - </project> - <configuration - Name="Debug" - c_preprocessor_definitions="DEBUG" - gcc_debugging_level="Level 3" - gcc_optimization_level="None" /> - <configuration - Name="Release" - c_preprocessor_definitions="NDEBUG" - gcc_debugging_level="None" - gcc_omit_frame_pointer="Yes" - gcc_optimization_level="Level 1" /> - <configuration Name="EA4357" /> -</solution> diff --git a/examples/device/device_virtual_com/segger/device_virtual_com.emSession b/examples/device/device_virtual_com/segger/device_virtual_com.emSession deleted file mode 100644 index 4858f6b1d..000000000 --- a/examples/device/device_virtual_com/segger/device_virtual_com.emSession +++ /dev/null @@ -1,87 +0,0 @@ -<!DOCTYPE CrossStudio_Session_File> -<session> - <Bookmarks/> - <Breakpoints groups="Breakpoints" active_group="Breakpoints"/> - <ExecutionProfileWindow/> - <FrameBufferWindow> - <FrameBufferWindow bufferHeight="-1" addressSpace="" addressText="" bufferWidth="-1"/> - </FrameBufferWindow> - <Memory1> - <MemoryWindow addressSpace="" dataSize="1" autoEvaluate="0" viewMode="0" addressOrder="0" columnsText="" refreshPeriod="0" name="device_virtual_com" radix="16" sizeText="" addressText=""/> - </Memory1> - <Memory2> - <MemoryWindow addressSpace="" dataSize="1" autoEvaluate="0" viewMode="0" addressOrder="0" columnsText="" refreshPeriod="0" name="device_virtual_com" radix="16" sizeText="" addressText=""/> - </Memory2> - <Memory3> - <MemoryWindow addressSpace="" dataSize="1" autoEvaluate="0" viewMode="0" addressOrder="0" columnsText="" refreshPeriod="0" name="device_virtual_com" radix="16" sizeText="" addressText=""/> - </Memory3> - <Memory4> - <MemoryWindow addressSpace="" dataSize="1" autoEvaluate="0" viewMode="0" addressOrder="0" columnsText="" refreshPeriod="0" name="device_virtual_com" radix="16" sizeText="" addressText=""/> - </Memory4> - <Project> - <ProjectSessionItem path="device_virtual_com"/> - <ProjectSessionItem path="device_virtual_com;device_virtual_com"/> - <ProjectSessionItem path="device_virtual_com;device_virtual_com;hw"/> - <ProjectSessionItem path="device_virtual_com;device_virtual_com;hw;bsp"/> - <ProjectSessionItem path="device_virtual_com;device_virtual_com;hw;cmsis"/> - <ProjectSessionItem path="device_virtual_com;device_virtual_com;hw;mcu"/> - <ProjectSessionItem path="device_virtual_com;device_virtual_com;hw;mcu;nxp"/> - <ProjectSessionItem path="device_virtual_com;device_virtual_com;hw;mcu;nxp;lpc43xx"/> - <ProjectSessionItem path="device_virtual_com;device_virtual_com;hw;mcu;nxp;lpc43xx;CMSIS_LPC43xx_DriverLib"/> - <ProjectSessionItem path="device_virtual_com;device_virtual_com;hw;mcu;nxp;lpc43xx;tusb_port"/> - <ProjectSessionItem path="device_virtual_com;device_virtual_com;RTT Files"/> - <ProjectSessionItem path="device_virtual_com;device_virtual_com;Script Files"/> - <ProjectSessionItem path="device_virtual_com;device_virtual_com;src"/> - <ProjectSessionItem path="device_virtual_com;device_virtual_com;System Files"/> - <ProjectSessionItem path="device_virtual_com;device_virtual_com;tinyusb"/> - </Project> - <Register1> - <RegisterWindow visibleNodes="CPU - Current Context/r0;CPU - Current Context/r1;CPU - Current Context/r2;CPU - Current Context/r3;CPU - Current Context/r4;CPU - Current Context/r5;CPU - Current Context/r6;CPU - Current Context/r7;CPU - Current Context/r8;CPU - Current Context/r9;CPU - Current Context/r10;CPU - Current Context/r11;CPU - Current Context/r12;CPU - Current Context/sp(r13);CPU - Current Context/lr(r14);CPU - Current Context/pc(r15);CPU - Current Context/apsr;CPU/r0;CPU/r1;CPU/r2;CPU/r3;CPU/r4;CPU/r5;CPU/r6;CPU/r7;CPU/r8;CPU/r9;CPU/r10;CPU/r11;CPU/r12;CPU/sp(r13);CPU/lr(r14);CPU/pc(r15);CPU/xpsr;CPU/msp;CPU/psp;CPU/cfbp" binaryNodes="" asciiNodes="" openNodes="CPU - Current Context" name="device_virtual_com" decimalNodes="" octalNodes="" unsignedNodes=""/> - </Register1> - <Register2> - <RegisterWindow visibleNodes="CPU - Current Context/r0;CPU - Current Context/r1;CPU - Current Context/r2;CPU - Current Context/r3;CPU - Current Context/r4;CPU - Current Context/r5;CPU - Current Context/r6;CPU - Current Context/r7;CPU - Current Context/r8;CPU - Current Context/r9;CPU - Current Context/r10;CPU - Current Context/r11;CPU - Current Context/r12;CPU - Current Context/sp(r13);CPU - Current Context/lr(r14);CPU - Current Context/pc(r15);CPU - Current Context/apsr;CPU/r0;CPU/r1;CPU/r2;CPU/r3;CPU/r4;CPU/r5;CPU/r6;CPU/r7;CPU/r8;CPU/r9;CPU/r10;CPU/r11;CPU/r12;CPU/sp(r13);CPU/lr(r14);CPU/pc(r15);CPU/xpsr;CPU/msp;CPU/psp;CPU/cfbp" binaryNodes="" asciiNodes="" openNodes="CPU - Current Context" name="device_virtual_com" decimalNodes="" octalNodes="" unsignedNodes=""/> - </Register2> - <Register3> - <RegisterWindow visibleNodes="CPU - Current Context/r0;CPU - Current Context/r1;CPU - Current Context/r2;CPU - Current Context/r3;CPU - Current Context/r4;CPU - Current Context/r5;CPU - Current Context/r6;CPU - Current Context/r7;CPU - Current Context/r8;CPU - Current Context/r9;CPU - Current Context/r10;CPU - Current Context/r11;CPU - Current Context/r12;CPU - Current Context/sp(r13);CPU - Current Context/lr(r14);CPU - Current Context/pc(r15);CPU - Current Context/apsr;CPU/r0;CPU/r1;CPU/r2;CPU/r3;CPU/r4;CPU/r5;CPU/r6;CPU/r7;CPU/r8;CPU/r9;CPU/r10;CPU/r11;CPU/r12;CPU/sp(r13);CPU/lr(r14);CPU/pc(r15);CPU/xpsr;CPU/msp;CPU/psp;CPU/cfbp" binaryNodes="" asciiNodes="" openNodes="CPU - Current Context" name="device_virtual_com" decimalNodes="" octalNodes="" unsignedNodes=""/> - </Register3> - <Register4> - <RegisterWindow visibleNodes="CPU - Current Context/r0;CPU - Current Context/r1;CPU - Current Context/r2;CPU - Current Context/r3;CPU - Current Context/r4;CPU - Current Context/r5;CPU - Current Context/r6;CPU - Current Context/r7;CPU - Current Context/r8;CPU - Current Context/r9;CPU - Current Context/r10;CPU - Current Context/r11;CPU - Current Context/r12;CPU - Current Context/sp(r13);CPU - Current Context/lr(r14);CPU - Current Context/pc(r15);CPU - Current Context/apsr;CPU/r0;CPU/r1;CPU/r2;CPU/r3;CPU/r4;CPU/r5;CPU/r6;CPU/r7;CPU/r8;CPU/r9;CPU/r10;CPU/r11;CPU/r12;CPU/sp(r13);CPU/lr(r14);CPU/pc(r15);CPU/xpsr;CPU/msp;CPU/psp;CPU/cfbp" binaryNodes="" asciiNodes="" openNodes="CPU - Current Context" name="device_virtual_com" decimalNodes="" octalNodes="" unsignedNodes=""/> - </Register4> - <TraceWindow> - <Trace enabled="Yes"/> - </TraceWindow> - <Watch1> - <Watches active="1" update="Never"/> - </Watch1> - <Watch2> - <Watches active="0" update="Never"/> - </Watch2> - <Watch3> - <Watches active="0" update="Never"/> - </Watch3> - <Watch4> - <Watches active="0" update="Never"/> - </Watch4> - <Files> - <SessionOpenFile windowGroup="DockEditLeft" x="0" y="61" useTextEdit="1" useBinaryEdit="0" left="0" path="../src/main.c" debugPath="../src/main.c" selected="0" top="44" codecName="Default"/> - <SessionOpenFile windowGroup="DockEditLeft" x="0" y="39" useTextEdit="1" useBinaryEdit="0" left="0" path="../src/tusb_descriptors.h" debugPath="../src/tusb_descriptors.h" selected="0" top="16" codecName="Default"/> - <SessionOpenFile windowGroup="DockEditLeft" x="0" y="38" useTextEdit="1" useBinaryEdit="0" left="0" path="../../../../tinyusb/tusb_option.h" debugPath="../../../../tinyusb/tusb_option.h" selected="0" top="29" codecName="Default"/> - <SessionOpenFile windowGroup="DockEditLeft" x="0" y="108" useTextEdit="1" useBinaryEdit="0" left="0" path="../src/tusb_config.h" debugPath="../src/tusb_config.h" selected="0" top="86" codecName="Default"/> - <SessionOpenFile windowGroup="DockEditLeft" x="0" y="33" useTextEdit="1" useBinaryEdit="0" left="0" path="flash_placement.xml" debugPath="flash_placement.xml" selected="0" top="6" codecName="Default"/> - <SessionOpenFile windowGroup="DockEditLeft" x="0" y="64" useTextEdit="1" useBinaryEdit="0" left="0" path="../../../../hw/mcu/nxp/lpc43xx/CMSIS_LPC43xx_DriverLib/inc/LPC43xx.h" debugPath="../../../../hw/mcu/nxp/lpc43xx/CMSIS_LPC43xx_DriverLib/inc/LPC43xx.h" selected="0" top="47" codecName="Default"/> - <SessionOpenFile windowGroup="DockEditLeft" x="0" y="100" useTextEdit="1" useBinaryEdit="0" left="0" path="../../../../hw/bsp/board.h" debugPath="../../../../hw/bsp/board.h" selected="0" top="85" codecName="Default"/> - <SessionOpenFile windowGroup="DockEditLeft" x="0" y="251" useTextEdit="1" useBinaryEdit="0" left="0" path="../../../../hw/bsp/ea4357/nand.c" debugPath="../../../../hw/bsp/ea4357/nand.c" selected="0" top="243" codecName="Default"/> - <SessionOpenFile windowGroup="DockEditLeft" x="0" y="276" useTextEdit="1" useBinaryEdit="0" left="0" path="../../../../hw/bsp/ea4357/oem_base_board/norflash.c" debugPath="../../../../hw/bsp/ea4357/oem_base_board/norflash.c" selected="0" top="269" codecName="Default"/> - <SessionOpenFile windowGroup="DockEditLeft" x="0" y="149" useTextEdit="1" useBinaryEdit="0" left="0" path="../../../../hw/mcu/nxp/lpc43xx/CMSIS_LPC43xx_DriverLib/src/lpc43xx_emc.c" debugPath="../../../../hw/mcu/nxp/lpc43xx/CMSIS_LPC43xx_DriverLib/src/lpc43xx_emc.c" selected="0" top="130" codecName="Default"/> - <SessionOpenFile windowGroup="DockEditLeft" x="0" y="45" useTextEdit="1" useBinaryEdit="0" left="0" path="LPC43xx_Vectors.s" debugPath="LPC43xx_Vectors.s" selected="1" top="22" codecName="Default"/> - <SessionOpenFile windowGroup="DockEditLeft" x="0" y="0" useTextEdit="1" useBinaryEdit="0" left="0" path="../../../../hw/bsp/board.c" debugPath="../../../../hw/bsp/board.c" selected="0" top="72" codecName="Default"/> - <SessionOpenFile windowGroup="DockEditLeft" x="0" y="87" useTextEdit="1" useBinaryEdit="0" left="0" path="../../../../hw/bsp/printf_retarget.c" debugPath="../../../../hw/bsp/printf_retarget.c" selected="0" top="73" codecName="Default"/> - <SessionOpenFile windowGroup="DockEditLeft" x="0" y="51" useTextEdit="1" useBinaryEdit="0" left="0" path="SEGGER_RTT_SES.c" debugPath="SEGGER_RTT_SES.c" selected="0" top="44" codecName="Default"/> - <SessionOpenFile windowGroup="DockEditLeft" x="0" y="332" useTextEdit="1" useBinaryEdit="0" left="0" path="SEGGER_RTT.c" debugPath="SEGGER_RTT.c" selected="0" top="51" codecName="Default"/> - <SessionOpenFile windowGroup="DockEditLeft" x="0" y="0" useTextEdit="1" useBinaryEdit="0" left="0" path="SEGGER_RTT.h" debugPath="SEGGER_RTT.h" selected="0" top="183" codecName="Default"/> - <SessionOpenFile windowGroup="DockEditLeft" x="0" y="179" useTextEdit="1" useBinaryEdit="0" left="0" path="SEGGER_RTT_Conf.h" debugPath="SEGGER_RTT_Conf.h" selected="0" top="174" codecName="Default"/> - <SessionOpenFile windowGroup="DockEditLeft" x="0" y="0" useTextEdit="1" useBinaryEdit="0" left="0" path="LPC4300_Startup.s" debugPath="LPC4300_Startup.s" selected="0" top="0" codecName="Default"/> - <SessionOpenFile windowGroup="DockEditLeft" x="0" y="13" useTextEdit="1" useBinaryEdit="0" left="0" path="thumb_crt0.s" debugPath="thumb_crt0.s" selected="0" top="0" codecName="Default"/> - </Files> - <ARMCrossStudioWindow activeProject="device_virtual_com" fileDialogDefaultFilter="*.c" autoConnectTarget="J-Link" buildConfiguration="EA4357" debugSearchFileMap="" fileDialogInitialDirectory="/home/hathach/Dropbox/tinyusb/workspace/tinyusb/hw/mcu/nxp/lpc43xx/tusb_port" debugSearchPath="" autoConnectCapabilities="3199"/> -</session> diff --git a/examples/device/device_virtual_com/segger/device_virtual_com_EA4357.jlink b/examples/device/device_virtual_com/segger/device_virtual_com_EA4357.jlink deleted file mode 100644 index 39b6d054a..000000000 --- a/examples/device/device_virtual_com/segger/device_virtual_com_EA4357.jlink +++ /dev/null @@ -1,39 +0,0 @@ -[BREAKPOINTS] -ForceImpTypeAny = 0 -ShowInfoWin = 1 -EnableFlashBP = 2 -BPDuringExecution = 0 -[CFI] -CFISize = 0x00 -CFIAddr = 0x00 -[CPU] -MonModeVTableAddr = 0xFFFFFFFF -MonModeDebug = 0 -MaxNumAPs = 0 -LowPowerHandlingMode = 0 -OverrideMemMap = 0 -AllowSimulation = 1 -ScriptFile="" -[FLASH] -CacheExcludeSize = 0x00 -CacheExcludeAddr = 0x00 -MinNumBytesFlashDL = 0 -SkipProgOnCRCMatch = 1 -VerifyDownload = 1 -AllowCaching = 1 -EnableFlashDL = 2 -Override = 0 -Device="ARM7" -[GENERAL] -WorkRAMSize = 0x00 -WorkRAMAddr = 0x00 -RAMUsageLimit = 0x00 -[SWO] -SWOLogFile="" -[MEM] -RdOverrideOrMask = 0x00 -RdOverrideAndMask = 0xFFFFFFFF -RdOverrideAddr = 0xFFFFFFFF -WrOverrideOrMask = 0x00 -WrOverrideAndMask = 0xFFFFFFFF -WrOverrideAddr = 0xFFFFFFFF diff --git a/examples/device/device_virtual_com/src/main.c b/examples/device/device_virtual_com/src/main.c deleted file mode 100644 index 60f93a000..000000000 --- a/examples/device/device_virtual_com/src/main.c +++ /dev/null @@ -1,154 +0,0 @@ -/**************************************************************************/ -/*! - @file main.c - @author hathach (tinyusb.org) - - @section LICENSE - - Software License Agreement (BSD License) - - Copyright (c) 2013, hathach (tinyusb.org) - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holders nor the - names of its contributors may be used to endorse or promote products - derived from this software without specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ''AS IS'' AND ANY - EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER BE LIABLE FOR ANY - DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION HOWEVER CAUSED AND - ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - INCLUDING NEGLIGENCE OR OTHERWISE ARISING IN ANY WAY OUT OF THE USE OF THIS - SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - - This file is part of the tinyusb stack. -*/ -/**************************************************************************/ - -//--------------------------------------------------------------------+ -// INCLUDE -//--------------------------------------------------------------------+ -#include <stdlib.h> -#include <stdio.h> -#include <string.h> - -#include "bsp/board.h" -#include "tusb.h" - -//--------------------------------------------------------------------+ -// MACRO CONSTANT TYPEDEF -//--------------------------------------------------------------------+ - -//--------------------------------------------------------------------+ -// INTERNAL OBJECT & FUNCTION DECLARATION -//--------------------------------------------------------------------+ -void print_greeting(void); -void led_blinking_task(void); -void virtual_com_task(void); - -/*------------- MAIN -------------*/ -int main(void) -{ - board_init(); - print_greeting(); - - tusb_init(); - - while (1) - { - tusb_task(); - - led_blinking_task(); - virtual_com_task(); - } - - return 0; -} - -void virtual_com_task(void) -{ - // connected and there are data available - if ( tud_mounted() && tud_cdc_available() ) - { - uint8_t buf[64]; - - // read and echo back - uint32_t count = tud_cdc_read(buf, sizeof(buf)); - - tud_cdc_write(buf, count); - } -} - - -//--------------------------------------------------------------------+ -// tinyusb callbacks -//--------------------------------------------------------------------+ -void tud_mount_cb(void) -{ - -} - -void tud_umount_cb(void) -{ -} - -void tud_cdc_rx_cb(uint8_t itf) -{ -} - -//--------------------------------------------------------------------+ -// BLINKING TASK -//--------------------------------------------------------------------+ -void led_blinking_task(void) -{ - enum { BLINK_INTEVAL = 1000 }; - - static bool led_state = false; - static uint32_t last_blink = 0; - - // not enough time - if ( last_blink + BLINK_INTEVAL > tusb_hal_tick_get() ) return; - - last_blink += BLINK_INTEVAL; - - board_led_control(BOARD_LED0, led_state); - led_state = 1 - led_state; // toggle -} - -//--------------------------------------------------------------------+ -// HELPER FUNCTION -//--------------------------------------------------------------------+ -void print_greeting(void) -{ - char const * const rtos_name[] = - { - [OPT_OS_NONE] = "None", - [OPT_OS_FREERTOS] = "FreeRTOS", - }; - - printf("\n\ ---------------------------------------------------------------------\n\ -- Device Demo (a tinyusb example)\n\ -- if you find any bugs or get any questions, feel free to file an\n\ -- issue at https://github.com/hathach/tinyusb\n\ ---------------------------------------------------------------------\n\n" - ); - - puts("This DEVICE demo is configured to support:"); - printf(" - RTOS = %s\n", rtos_name[CFG_TUSB_OS]); - if (CFG_TUD_HID_MOUSE ) puts(" - HID Mouse"); - if (CFG_TUD_HID_KEYBOARD ) puts(" - HID Keyboard"); - if (CFG_TUD_MSC ) puts(" - Mass Storage"); - if (CFG_TUD_CDC ) puts(" - Communication Device Class"); -} diff --git a/examples/device/device_virtual_com/src/tusb_config.h b/examples/device/device_virtual_com/src/tusb_config.h deleted file mode 100644 index fd3f41b01..000000000 --- a/examples/device/device_virtual_com/src/tusb_config.h +++ /dev/null @@ -1,148 +0,0 @@ -/**************************************************************************/ -/*! - @file tusb_config.h - @author hathach (tinyusb.org) - - @section LICENSE - - Software License Agreement (BSD License) - - Copyright (c) 2013, hathach (tinyusb.org) - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holders nor the - names of its contributors may be used to endorse or promote products - derived from this software without specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ''AS IS'' AND ANY - EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER BE LIABLE FOR ANY - DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION HOWEVER CAUSED AND - ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - INCLUDING NEGLIGENCE OR OTHERWISE ARISING IN ANY WAY OUT OF THE USE OF THIS - SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - - This file is part of the tinyusb stack. -*/ -/**************************************************************************/ - -#ifndef _TUSB_CONFIG_H_ -#define _TUSB_CONFIG_H_ - -#ifdef __cplusplus - extern "C" { -#endif - -//--------------------------------------------------------------------+ -// CONTROLLER CONFIGURATION -//--------------------------------------------------------------------+ -//#define CFG_TUSB_MCU will be passed from IDE/command line for easy board/mcu switching - -#define CFG_TUSB_RHPORT0_MODE (OPT_MODE_DEVICE) -//#define CFG_TUSB_RHPORT1_MODE (OPT_MODE_DEVICE) - -#define CFG_TUSB_DEBUG 2 - -/*------------- RTOS -------------*/ -//#define CFG_TUSB_OS OPT_OS_NONE // be passed from IDE/command line for easy project switching -//#define CFG_TUD_TASK_PRIO 0 -//#define CFG_TUD_TASK_QUEUE_SZ 16 -//#define CFG_TUD_TASK_STACK_SZ 150 - -//--------------------------------------------------------------------+ -// DEVICE CONFIGURATION -//--------------------------------------------------------------------+ - -/*------------- Core -------------*/ -#define CFG_TUD_DESC_AUTO 1 - -// #define CFG_TUD_DESC_VID 0xCAFE -// #define CFG_TUD_DESC_PID 0x0001 - -#define CFG_TUD_ENDOINT0_SIZE 64 - - -//------------- CLASS -------------// -#define CFG_TUD_CDC 1 -#define CFG_TUD_MSC 0 -#define CFG_TUD_HID_KEYBOARD 0 -#define CFG_TUD_HID_MOUSE 0 - - -/*------------------------------------------------------------------*/ -/* CLASS DRIVER - *------------------------------------------------------------------*/ - -// FIFO size of CDC TX and RX -#define CFG_TUD_CDC_RX_BUFSIZE 64 -#define CFG_TUD_CDC_TX_BUFSIZE 64 - -//--------------------------------------------------------------------+ -// USB RAM PLACEMENT -//--------------------------------------------------------------------+ -#ifdef __CODE_RED // compiled with lpcxpresso - - #if (CFG_TUSB_MCU == OPT_MCU_LPC11UXX) || (CFG_TUSB_MCU == OPT_MCU_LPC13UXX) - #define CFG_TUSB_MEM_SECTION ATTR_SECTION(.data.$RAM2) ATTR_ALIGNED(64) // lp11u & lp13u requires data to be 64 byte aligned - #elif CFG_TUSB_MCU == OPT_MCU_LPC175X_6X - #define CFG_TUSB_MEM_SECTION // LPC17xx USB DMA can access all - #elif (CFG_TUSB_MCU == OPT_MCU_LPC43XX) - #define CFG_TUSB_MEM_SECTION ATTR_SECTION(.data.$RAM3) - #endif - -#elif defined __CC_ARM // Compiled with Keil armcc, USBRAM_SECTION is defined in scatter files - - #if (CFG_TUSB_MCU == OPT_MCU_LPC11UXX) || (CFG_TUSB_MCU == OPT_MCU_LPC13UXX) - #define CFG_TUSB_MEM_SECTION ATTR_SECTION(USBRAM_SECTION) ATTR_ALIGNED(64) // lp11u & lp13u requires data to be 64 byte aligned - #elif (CFG_TUSB_MCU == OPT_MCU_LPC175X_6X) - #define CFG_TUSB_MEM_SECTION // LPC17xx USB DMA can access all address - #elif (CFG_TUSB_MCU == OPT_MCU_LPC43XX) - #define CFG_TUSB_MEM_SECTION // Use keil tool configure to have AHB SRAM as default memory - #endif - -#elif defined __ICCARM__ // compiled with IAR - - #if (CFG_TUSB_MCU == OPT_MCU_LPC11UXX) || (CFG_TUSB_MCU == OPT_MCU_LPC13UXX) - #define CFG_TUSB_MEM_SECTION _Pragma("location=\"USB_PACKET_MEMORY\"") ATTR_ALIGNED(64) - #elif (CFG_TUSB_MCU == OPT_MCU_LPC175X_6X) - #define CFG_TUSB_MEM_SECTION - #elif (CFG_TUSB_MCU == OPT_MCU_LPC43XX) - #define CFG_TUSB_MEM_SECTION _Pragma("location=\".ahb_sram1\"") - #endif - -#elif defined __SES_ARM - -#define CFG_TUSB_MEM_SECTION ATTR_SECTION(.bss2) - -#else - - #error compiler not specified - -#endif - - -// LPC11uxx and LPC13uxx requires each buffer has to be 64-byte alignment -#if CFG_TUSB_MCU == OPT_MCU_LPC11UXX || CFG_TUSB_MCU == OPT_MCU_LPC13UXX - #define CFG_TUSB_MEM_ALIGN ATTR_ALIGNED(64) -#elif CFG_TUSB_MCU == OPT_MCU_NRF5X - #define CFG_TUSB_MEM_ALIGN ATTR_ALIGNED(4) -#else - #define CFG_TUSB_MEM_ALIGN -#endif - - -#ifdef __cplusplus - } -#endif - -#endif /* _TUSB_CONFIG_H_ */ diff --git a/examples/device/device_virtual_com/src/tusb_descriptors.c b/examples/device/device_virtual_com/src/tusb_descriptors.c deleted file mode 100644 index 2ba5434cc..000000000 --- a/examples/device/device_virtual_com/src/tusb_descriptors.c +++ /dev/null @@ -1,100 +0,0 @@ -/**************************************************************************/ -/*! - @file tusb_descriptors.c - @author hathach (tinyusb.org) - - @section LICENSE - - Software License Agreement (BSD License) - - Copyright (c) 2013, hathach (tinyusb.org) - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holders nor the - names of its contributors may be used to endorse or promote products - derived from this software without specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ''AS IS'' AND ANY - EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER BE LIABLE FOR ANY - DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION HOWEVER CAUSED AND - ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - INCLUDING NEGLIGENCE OR OTHERWISE ARISING IN ANY WAY OUT OF THE USE OF THIS - SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - - This file is part of the tinyusb stack. -*/ -/**************************************************************************/ - -#include "tusb.h" - -//--------------------------------------------------------------------+ -// STRING DESCRIPTORS -//--------------------------------------------------------------------+ -#define STRING_LEN_UNICODE(n) (2 + (2*(n))) // also includes 2 byte header -#define ENDIAN_BE16_FROM( high, low) ENDIAN_BE16(high << 8 | low) - -// array of pointer to string descriptors -uint16_t const * const string_desc_arr [] = -{ - [0] = (uint16_t []) { // supported language - ENDIAN_BE16_FROM( STRING_LEN_UNICODE(1), TUSB_DESC_STRING ), - 0x0409 // English - }, - - [1] = (uint16_t []) { // manufacturer - ENDIAN_BE16_FROM( STRING_LEN_UNICODE(11), TUSB_DESC_STRING), - 't', 'i', 'n', 'y', 'u', 's', 'b', '.', 'o', 'r', 'g' // len = 11 - }, - - [2] = (uint16_t []) { // product - ENDIAN_BE16_FROM( STRING_LEN_UNICODE(14), TUSB_DESC_STRING), - 't', 'i', 'n', 'y', 'u', 's', 'b', ' ', 'd', 'e', 'v', 'i', 'c', 'e' // len = 14 - }, - - [3] = (uint16_t []) { // serials - ENDIAN_BE16_FROM( STRING_LEN_UNICODE(4), TUSB_DESC_STRING), - '1', '2', '3', '4' // len = 4 - }, - - [4] = (uint16_t []) { // CDC Interface - ENDIAN_BE16_FROM( STRING_LEN_UNICODE(3), TUSB_DESC_STRING), - 'c', 'd', 'c' // len = 3 - }, - - [5] = (uint16_t []) { // Keyboard Interface - ENDIAN_BE16_FROM( STRING_LEN_UNICODE(5), TUSB_DESC_STRING), - 'm', 'o', 'u', 's', 'e' // len = 5 - }, - - [6] = (uint16_t []) { // Keyboard Interface - ENDIAN_BE16_FROM( STRING_LEN_UNICODE(8), TUSB_DESC_STRING), - 'k', 'e', 'y', 'b', 'o', 'a', 'r', 'd' // len = 8 - }, - - [7] = (uint16_t []) { // MSC Interface - ENDIAN_BE16_FROM( STRING_LEN_UNICODE(3), TUSB_DESC_STRING), - 'm', 's', 'c' // len = 3 - } -}; - - -// tud_desc_set is required by tinyusb stack -// since CFG_TUD_DESC_AUTO is enabled, we only need to set string_arr -tud_desc_set_t tud_desc_set = -{ - .device = NULL, - .config = NULL, - .string_arr = (uint8_t const **) string_desc_arr, - .hid_report = NULL -}; diff --git a/examples/device/device_virtual_com/xpresso/.cproject b/examples/device/device_virtual_com/xpresso/.cproject deleted file mode 100644 index 1e76a688c..000000000 --- a/examples/device/device_virtual_com/xpresso/.cproject +++ /dev/null @@ -1,207 +0,0 @@ -<?xml version="1.0" encoding="UTF-8" standalone="no"?> -<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage"> - 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size="0x4000"/> -<memoryInstance derived_from="RAM" edited="true" id="RamAHB_ETB16" location="0x2000c000" size="0x4000"/> -<prog_flash blocksz="0x2000" location="0x1a000000" maxprgbuff="0x400" progwithcode="TRUE" size="0x10000"/> -<prog_flash blocksz="0x10000" location="0x1a010000" maxprgbuff="0x400" progwithcode="TRUE" size="0x70000"/> -<prog_flash blocksz="0x2000" location="0x1b000000" maxprgbuff="0x400" progwithcode="TRUE" size="0x10000"/> -<prog_flash blocksz="0x10000" location="0x1b010000" maxprgbuff="0x400" progwithcode="TRUE" size="0x70000"/> -<peripheralInstance derived_from="V7M_MPU" id="MPU" location="0xe000ed90"/> -<peripheralInstance derived_from="V7M_NVIC" id="NVIC" location="0xe000e000"/> -<peripheralInstance derived_from="V7M_DCR" id="DCR" location="0xe000edf0"/> -<peripheralInstance derived_from="V7M_ITM" id="ITM" location="0xe0000000"/> -<peripheralInstance derived_from="SCT" id="SCT" location="0x40000000"/> -<peripheralInstance derived_from="GPDMA" id="GPDMA" location="0x40002000"/> -<peripheralInstance derived_from="SPIFI" id="SPIFI" location="0x40003000"/> -<peripheralInstance derived_from="SDMMC" id="SDMMC" location="0x40004000"/> -<peripheralInstance derived_from="EMC" id="EMC" location="0x40005000"/> -<peripheralInstance derived_from="USB0" id="USB0" location="0x40006000"/> -<peripheralInstance derived_from="USB1" id="USB1" location="0x40007000"/> -<peripheralInstance derived_from="LCD" id="LCD" location="0x40008000"/> -<peripheralInstance derived_from="EEPROM" id="EEPROM" location="0x4000e000"/> -<peripheralInstance derived_from="ETHERNET" id="ETHERNET" location="0x40010000"/> -<peripheralInstance derived_from="ATIMER" id="ATIMER" location="0x40040000"/> -<peripheralInstance derived_from="REGFILE" id="REGFILE" location="0x40041000"/> -<peripheralInstance derived_from="PMC" id="PMC" location="0x40042000"/> -<peripheralInstance derived_from="CREG" id="CREG" location="0x40043000"/> -<peripheralInstance derived_from="EVENTROUTER" id="EVENTROUTER" location="0x40044000"/> -<peripheralInstance derived_from="RTC" id="RTC" location="0x40046000"/> -<peripheralInstance derived_from="CGU" id="CGU" location="0x40050000"/> -<peripheralInstance derived_from="CCU1" id="CCU1" location="0x40051000"/> -<peripheralInstance derived_from="CCU2" id="CCU2" location="0x40052000"/> -<peripheralInstance derived_from="RGU" id="RGU" location="0x40053000"/> -<peripheralInstance derived_from="WWDT" id="WWDT" location="0x40080000"/> -<peripheralInstance derived_from="USART0" id="USART0" location="0x40081000"/> -<peripheralInstance derived_from="USART2" id="USART2" location="0x400c1000"/> -<peripheralInstance derived_from="USART3" id="USART3" location="0x400c2000"/> -<peripheralInstance derived_from="UART1" id="UART1" location="0x40082000"/> -<peripheralInstance derived_from="SSP0" id="SSP0" location="0x40083000"/> -<peripheralInstance derived_from="SSP1" id="SSP1" location="0x400c5000"/> -<peripheralInstance derived_from="TIMER0" id="TIMER0" location="0x40084000"/> -<peripheralInstance derived_from="TIMER1" id="TIMER1" location="0x40085000"/> -<peripheralInstance derived_from="TIMER2" id="TIMER2" location="0x400c3000"/> -<peripheralInstance derived_from="TIMER3" id="TIMER3" location="0x400c4000"/> -<peripheralInstance derived_from="SCU" id="SCU" location="0x40086000"/> -<peripheralInstance derived_from="GPIO-PIN-INT" id="GPIO-PIN-INT" location="0x40087000"/> -<peripheralInstance derived_from="GPIO-GROUP-INT0" id="GPIO-GROUP-INT0" location="0x40088000"/> -<peripheralInstance derived_from="GPIO-GROUP-INT1" id="GPIO-GROUP-INT1" location="0x40089000"/> -<peripheralInstance derived_from="MCPWM" id="MCPWM" location="0x400a0000"/> -<peripheralInstance derived_from="I2C0" id="I2C0" location="0x400a1000"/> -<peripheralInstance derived_from="I2C1" id="I2C1" location="0x400e0000"/> -<peripheralInstance derived_from="I2S0" id="I2S0" location="0x400a2000"/> -<peripheralInstance derived_from="I2S1" id="I2S1" location="0x400a3000"/> -<peripheralInstance derived_from="C-CAN1" id="C-CAN1" location="0x400a4000"/> -<peripheralInstance derived_from="RITIMER" id="RITIMER" location="0x400c0000"/> -<peripheralInstance derived_from="QEI" id="QEI" location="0x400c6000"/> -<peripheralInstance derived_from="GIMA" id="GIMA" location="0x400c7000"/> -<peripheralInstance derived_from="DAC" id="DAC" location="0x400e1000"/> -<peripheralInstance derived_from="C-CAN0" id="C-CAN0" location="0x400e2000"/> -<peripheralInstance derived_from="ADC0" id="ADC0" location="0x400e3000"/> -<peripheralInstance derived_from="ADC1" id="ADC1" location="0x400e4000"/> -<peripheralInstance derived_from="GPIO-PORT" id="GPIO-PORT" location="0x400f4000"/> -<peripheralInstance derived_from="SPI" id="SPI" location="0x40100000"/> -<peripheralInstance derived_from="SGPIO" id="SGPIO" location="0x40101000"/> -</chip> -<processor><name gcc_name="cortex-m4">Cortex-M4</name> -<family>Cortex-M</family> -</processor> -<link href="nxp_lpc43xx_peripheral.xme" show="embed" type="simple"/> -</info> -</infoList> -</TargetConfig></projectStorage> - </storageModule> - <storageModule moduleId="refreshScope" versionNumber="2"> - <configuration configurationName="Debug"> - <resource resourceType="PROJECT" workspacePath="/device_virtual_com"/> - </configuration> - <configuration configurationName="Release"> - <resource resourceType="PROJECT" workspacePath="/device_virtual_com"/> - </configuration> - </storageModule> - <storageModule moduleId="com.crt.advproject"> - <boardId>MCB4357</boardId> - </storageModule> - <storageModule moduleId="org.eclipse.cdt.make.core.buildtargets"/> -</cproject> diff --git a/examples/device/device_virtual_com/xpresso/.project b/examples/device/device_virtual_com/xpresso/.project deleted file mode 100644 index c3c9ed67d..000000000 --- a/examples/device/device_virtual_com/xpresso/.project +++ /dev/null @@ -1,63 +0,0 @@ -<?xml version="1.0" encoding="UTF-8"?> -<projectDescription> - <name>device_virtual_com</name> - <comment></comment> - <projects> - </projects> - <buildSpec> - <buildCommand> - <name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name> - <triggers>clean,full,incremental,</triggers> - <arguments> - </arguments> - </buildCommand> - <buildCommand> - <name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name> - <triggers>full,incremental,</triggers> - <arguments> - </arguments> - </buildCommand> - </buildSpec> - <natures> - <nature>org.eclipse.cdt.core.cnature</nature> - <nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature> - <nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature> - </natures> - <linkedResources> - <link> - <name>hw</name> - <type>2</type> - <locationURI>PARENT-4-PROJECT_LOC/hw</locationURI> - </link> - <link> - <name>src</name> - <type>2</type> - <locationURI>PARENT-1-PROJECT_LOC/src</locationURI> - </link> - <link> - <name>tinyusb</name> - <type>2</type> - <locationURI>PARENT-4-PROJECT_LOC/src</locationURI> - </link> - </linkedResources> - <filteredResources> - <filter> - <id>1520932840443</id> - <name></name> - <type>22</type> - <matcher> - <id>org.eclipse.ui.ide.multiFilter</id> - <arguments>1.0-name-matches-false-false-*.d</arguments> - </matcher> - </filter> - <filter> - <id>1520932840444</id> - <name></name> - <type>22</type> - <matcher> - <id>org.eclipse.ui.ide.multiFilter</id> - <arguments>1.0-name-matches-false-false-*.o</arguments> - </matcher> - </filter> - </filteredResources> -</projectDescription> |